[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_H_
#define _IXGBE_H_

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/aer.h>

#include "ixgbe_type.h"
#include "ixgbe_common.h"
#include "ixgbe_dcb.h"
#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
#define IXGBE_FCOE
#include "ixgbe_fcoe.h"
#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
#ifdef CONFIG_IXGBE_DCA
#include <linux/dca.h>
#endif

#define PFX "ixgbe: "
#define DPRINTK(nlevel, klevel, fmt, args...) \
	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
		__func__ , ## args)))

/* TX/RX descriptor defines */
#define IXGBE_DEFAULT_TXD		   1024
#define IXGBE_MAX_TXD			   4096
#define IXGBE_MIN_TXD			     64

#define IXGBE_DEFAULT_RXD		   1024
#define IXGBE_MAX_RXD			   4096
#define IXGBE_MIN_RXD			     64

/* flow control */
#define IXGBE_DEFAULT_FCRTL		0x10000
#define IXGBE_MIN_FCRTL			   0x40
#define IXGBE_MAX_FCRTL			0x7FF80
#define IXGBE_DEFAULT_FCRTH		0x20000
#define IXGBE_MIN_FCRTH			  0x600
#define IXGBE_MAX_FCRTH			0x7FFF0
#define IXGBE_DEFAULT_FCPAUSE		 0xFFFF
#define IXGBE_MIN_FCPAUSE		      0
#define IXGBE_MAX_FCPAUSE		 0xFFFF

/* Supported Rx Buffer Sizes */
#define IXGBE_RXBUFFER_64    64     /* Used for packet split */
#define IXGBE_RXBUFFER_128   128    /* Used for packet split */
#define IXGBE_RXBUFFER_256   256    /* Used for packet split */
#define IXGBE_RXBUFFER_2048  2048
#define IXGBE_RXBUFFER_4096  4096
#define IXGBE_RXBUFFER_8192  8192
#define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */

#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256

#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBE_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_FCOE		(u32)(1 << 4)
#define IXGBE_TX_FLAGS_FSO		(u32)(1 << 5)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbe_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u16 next_to_watch;
};

struct ixgbe_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	unsigned int page_offset;
};

struct ixgbe_queue_stats {
	u64 packets;
	u64 bytes;
};

struct ixgbe_ring {
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	unsigned int count;		/* amount of descriptors */
	unsigned int next_to_use;
	unsigned int next_to_clean;

	int queue_index; /* needed for multiqueue queue management */
	union {
		struct ixgbe_tx_buffer *tx_buffer_info;
		struct ixgbe_rx_buffer *rx_buffer_info;
	};

	u16 head;
	u16 tail;

	unsigned int total_bytes;
	unsigned int total_packets;

	u16 reg_idx; /* holds the special value that gets the hardware register
		      * offset associated with this ring, which is different
		      * for DCB and RSS modes */

#ifdef CONFIG_IXGBE_DCA
	/* cpu for tx queue */
	int cpu;
#endif
	struct ixgbe_queue_stats stats;
	u64 v_idx; /* maps directly to the index for this ring in the hardware
	            * vector array, can also be used for finding the bit in EICR
	            * and friends that represents the vector for this ring */


	u16 work_limit;                /* max work per interrupt */
	u16 rx_buf_len;
	u64 rsc_count;                 /* stat for coalesced packets */
};

enum ixgbe_ring_f_enum {
	RING_F_NONE = 0,
	RING_F_DCB,
	RING_F_VMDQ,
	RING_F_RSS,
#ifdef IXGBE_FCOE
	RING_F_FCOE,
#endif /* IXGBE_FCOE */

	RING_F_ARRAY_SIZE      /* must be last in enum set */
};

#define IXGBE_MAX_DCB_INDICES   8
#define IXGBE_MAX_RSS_INDICES  16
#define IXGBE_MAX_VMDQ_INDICES 16
#ifdef IXGBE_FCOE
#define IXGBE_MAX_FCOE_INDICES  8
#endif /* IXGBE_FCOE */
struct ixgbe_ring_feature {
	int indices;
	int mask;
};

#define MAX_RX_QUEUES 128
#define MAX_TX_QUEUES 128

#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
                              ? 8 : 1)
#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbe_q_vector {
	struct ixgbe_adapter *adapter;
	struct napi_struct napi;
	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	u8 rxr_count;     /* Rx ring count assigned to this vector */
	u8 txr_count;     /* Tx ring count assigned to this vector */
	u8 tx_itr;
	u8 rx_itr;
	u32 eitr;
	u32 v_idx;        /* vector index in list */
};

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.  The lowest value
 * supported by all of the ixgbe hardware is 8.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define IXGBE_RX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
#define IXGBE_TX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
#define IXGBE_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))

#define IXGBE_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
#define IXGBE_TX_DESC(R, i)	IXGBE_GET_DESC(R, i, ixgbe_legacy_tx_desc)
#define IXGBE_RX_DESC(R, i)	IXGBE_GET_DESC(R, i, ixgbe_legacy_rx_desc)

#define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
#ifdef IXGBE_FCOE
/* Use 3K as the baby jumbo frame size for FCoE */
#define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
#endif /* IXGBE_FCOE */

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_VECTORS_82599 64
#define MAX_MSIX_Q_VECTORS_82599 64
#define MAX_MSIX_VECTORS_82598 18
#define MAX_MSIX_Q_VECTORS_82598 16

#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599

#define MIN_MSIX_Q_VECTORS 2
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbe_adapter {
	struct timer_list watchdog_timer;
	struct vlan_group *vlgrp;
	u16 bd_number;
	struct work_struct reset_task;
	struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
	char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
	struct ixgbe_dcb_config dcb_cfg;
	struct ixgbe_dcb_config temp_dcb_cfg;
	u8 dcb_set_bitmap;
	enum ixgbe_fc_mode last_lfc_mode;

	/* Interrupt Throttle Rate */
	u32 itr_setting;
	u16 eitr_low;
	u16 eitr_high;

	/* TX */
	struct ixgbe_ring *tx_ring;	/* One per active queue */
	int num_tx_queues;
	u64 restart_queue;
	u64 hw_csum_tx_good;
	u64 lsc_int;
	u64 hw_tso_ctxt;
	u64 hw_tso6_ctxt;
	u32 tx_timeout_count;
	bool detect_tx_hung;

	/* RX */
	struct ixgbe_ring *rx_ring;	/* One per active queue */
	int num_rx_queues;
	u64 hw_csum_rx_error;
	u64 hw_rx_no_dma_resources;
	u64 hw_csum_rx_good;
	u64 non_eop_descs;
	int num_msix_vectors;
	int max_msix_q_vectors;         /* true count of q_vectors for device */
	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
	struct msix_entry *msix_entries;

	u64 rx_hdr_split;
	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
#define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
#define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
#define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
#define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
#define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
#define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
#define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
#define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
#define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
#define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
#define IXGBE_FLAG_IN_SFP_LINK_TASK             (u32)(1 << 24)
#define IXGBE_FLAG_IN_SFP_MOD_TASK              (u32)(1 << 25)
#define IXGBE_FLAG_RSC_CAPABLE                  (u32)(1 << 26)
#define IXGBE_FLAG_RSC_ENABLED                  (u32)(1 << 27)
#define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 29)

/* default to trying for four seconds */
#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;

	u32 test_icr;
	struct ixgbe_ring test_tx_ring;
	struct ixgbe_ring test_rx_ring;

	/* structs defined in ixgbe_hw.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	struct ixgbe_hw_stats stats;

	/* Interrupt Throttle Rate */
	u32 eitr_param;

	unsigned long state;
	u64 tx_busy;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

	u32 link_speed;
	bool link_up;
	unsigned long link_check_timeout;

	struct work_struct watchdog_task;
	struct work_struct sfp_task;
	struct timer_list sfp_timer;
	struct work_struct multispeed_fiber_task;
	struct work_struct sfp_config_module_task;
#ifdef IXGBE_FCOE
	struct ixgbe_fcoe fcoe;
#endif /* IXGBE_FCOE */
	u64 rsc_count;
	u32 wol;
	u16 eeprom_version;
};

enum ixbge_state_t {
	__IXGBE_TESTING,
	__IXGBE_RESETTING,
	__IXGBE_DOWN,
	__IXGBE_SFP_MODULE_NOT_FOUND
};

enum ixgbe_boards {
	board_82598,
	board_82599,
};

extern struct ixgbe_info ixgbe_82598_info;
extern struct ixgbe_info ixgbe_82599_info;
#ifdef CONFIG_IXGBE_DCB
extern struct dcbnl_rtnl_ops dcbnl_ops;
extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
                              struct ixgbe_dcb_config *dst_dcb_cfg,
                              int tc_max);
#endif

extern char ixgbe_driver_name[];
extern const char ixgbe_driver_version[];

extern int ixgbe_up(struct ixgbe_adapter *adapter);
extern void ixgbe_down(struct ixgbe_adapter *adapter);
extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
extern void ixgbe_reset(struct ixgbe_adapter *adapter);
extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
extern void ixgbe_write_eitr(struct ixgbe_adapter *, int, u32);
#ifdef IXGBE_FCOE
extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
extern int ixgbe_fso(struct ixgbe_adapter *adapter,
                     struct ixgbe_ring *tx_ring, struct sk_buff *skb,
                     u32 tx_flags, u8 *hdr_len);
extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
                          union ixgbe_adv_rx_desc *rx_desc,
                          struct sk_buff *skb);
extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
                              struct scatterlist *sgl, unsigned int sgc);
extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
#endif /* IXGBE_FCOE */

#endif /* _IXGBE_H_ */
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
3efac5a0	4	Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
9a799d71 AK	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBE_H_
	29	#define _IXGBE_H_
	30
	31	#include <linux/types.h>
	32	#include <linux/pci.h>
	33	#include <linux/netdevice.h>
6fabd715	34	#include <linux/aer.h>
9a799d71 AK	35
	36	#include "ixgbe_type.h"
	37	#include "ixgbe_common.h"
2f90b865	38	#include "ixgbe_dcb.h"
eacd73f7 YZ	39	#if defined(CONFIG_FCOE) \|\| defined(CONFIG_FCOE_MODULE)
	40	#define IXGBE_FCOE
	41	#include "ixgbe_fcoe.h"
	42	#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332	43	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	44	#include <linux/dca.h>
bd0362dd JC	45	#endif
9a799d71	46
9a799d71 AK	47	#define PFX "ixgbe: "
	48	#define DPRINTK(nlevel, klevel, fmt, args...) \
	49	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	50	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
b39d66a8	51	__func__ , ## args)))
9a799d71 AK	52
	53	/* TX/RX descriptor defines */
	54	#define IXGBE_DEFAULT_TXD 1024
	55	#define IXGBE_MAX_TXD 4096
	56	#define IXGBE_MIN_TXD 64
	57
	58	#define IXGBE_DEFAULT_RXD 1024
	59	#define IXGBE_MAX_RXD 4096
	60	#define IXGBE_MIN_RXD 64
	61
9a799d71 AK	62	/* flow control */
9a799d71 AK	63	#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93	64	#define IXGBE_MIN_FCRTL 0x40
9a799d71 AK	65	#define IXGBE_MAX_FCRTL 0x7FF80
9a799d71 AK	66	#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93	67	#define IXGBE_MIN_FCRTH 0x600
9a799d71	68	#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93	69	#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71 AK	70	#define IXGBE_MIN_FCPAUSE 0
	71	#define IXGBE_MAX_FCPAUSE 0xFFFF
	72
	73	/* Supported Rx Buffer Sizes */
	74	#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
	75	#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
	76	#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
	77	#define IXGBE_RXBUFFER_2048 2048
e76678dd AD	78	#define IXGBE_RXBUFFER_4096 4096
e76678dd AD	79	#define IXGBE_RXBUFFER_8192 8192
32344a39	80	#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 AK	81
	82	#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
	83
	84	#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
	85
9a799d71 AK	86	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	87	#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	88
	89	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
	90	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
	91	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
	92	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7 YZ	93	#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
eacd73f7 YZ	94	#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71	95	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865	96	#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71 AK	97	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
	98
	99	/* wrapper around a pointer to a socket buffer,
	100	* so a DMA handle can be stored along with the buffer */
	101	struct ixgbe_tx_buffer {
	102	struct sk_buff *skb;
	103	dma_addr_t dma;
	104	unsigned long time_stamp;
	105	u16 length;
	106	u16 next_to_watch;
	107	};
	108
	109	struct ixgbe_rx_buffer {
	110	struct sk_buff *skb;
	111	dma_addr_t dma;
	112	struct page *page;
	113	dma_addr_t page_dma;
762f4c57	114	unsigned int page_offset;
9a799d71 AK	115	};
	116
	117	struct ixgbe_queue_stats {
	118	u64 packets;
	119	u64 bytes;
	120	};
	121
	122	struct ixgbe_ring {
9a799d71 AK	123	void desc; / descriptor ring memory */
	124	dma_addr_t dma; /* phys. address of descriptor ring */
	125	unsigned int size; /* length in bytes */
	126	unsigned int count; /* amount of descriptors */
	127	unsigned int next_to_use;
	128	unsigned int next_to_clean;
	129
021230d4	130	int queue_index; /* needed for multiqueue queue management */
9a799d71 AK	131	union {
	132	struct ixgbe_tx_buffer *tx_buffer_info;
	133	struct ixgbe_rx_buffer *rx_buffer_info;
	134	};
	135
	136	u16 head;
	137	u16 tail;
	138
f494e8fa AV	139	unsigned int total_bytes;
f494e8fa AV	140	unsigned int total_packets;
9a799d71	141
021230d4 AV	142	u16 reg_idx; /* holds the special value that gets the hardware register
021230d4 AV	143	* offset associated with this ring, which is different
2f90b865	144	* for DCB and RSS modes */
bd0362dd	145
5dd2d332	146	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	147	/* cpu for tx queue */
	148	int cpu;
	149	#endif
9a799d71	150	struct ixgbe_queue_stats stats;
e8e26350 PW	151	u64 v_idx; /* maps directly to the index for this ring in the hardware
	152	* vector array, can also be used for finding the bit in EICR
	153	* and friends that represents the vector for this ring */
9a799d71	154
9a799d71	155
9a799d71	156	u16 work_limit; /* max work per interrupt */
7c6e0a43	157	u16 rx_buf_len;
f8212f97	158	u64 rsc_count; /* stat for coalesced packets */
9a799d71 AK	159	};
9a799d71 AK	160
c7e4358a SN	161	enum ixgbe_ring_f_enum {
	162	RING_F_NONE = 0,
	163	RING_F_DCB,
	164	RING_F_VMDQ,
	165	RING_F_RSS,
0331a832 YZ	166	#ifdef IXGBE_FCOE
	167	RING_F_FCOE,
	168	#endif /* IXGBE_FCOE */
c7e4358a SN	169
	170	RING_F_ARRAY_SIZE /* must be last in enum set */
	171	};
	172
2f90b865	173	#define IXGBE_MAX_DCB_INDICES 8
021230d4 AV	174	#define IXGBE_MAX_RSS_INDICES 16
021230d4 AV	175	#define IXGBE_MAX_VMDQ_INDICES 16
0331a832 YZ	176	#ifdef IXGBE_FCOE
	177	#define IXGBE_MAX_FCOE_INDICES 8
	178	#endif /* IXGBE_FCOE */
021230d4 AV	179	struct ixgbe_ring_feature {
	180	int indices;
	181	int mask;
	182	};
	183
e8e26350 PW	184	#define MAX_RX_QUEUES 128
e8e26350 PW	185	#define MAX_TX_QUEUES 128
021230d4	186
2f90b865 AD	187	#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
	188	? 8 : 1)
	189	#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
	190
021230d4 AV	191	/* MAX_MSIX_Q_VECTORS of these are allocated,
	192	* but we only use one per queue-specific vector.
	193	*/
	194	struct ixgbe_q_vector {
	195	struct ixgbe_adapter *adapter;
	196	struct napi_struct napi;
	197	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	198	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	199	u8 rxr_count; /* Rx ring count assigned to this vector */
	200	u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3 JB	201	u8 tx_itr;
30efa5a3 JB	202	u8 rx_itr;
021230d4	203	u32 eitr;
7a921c93	204	u32 v_idx; /* vector index in list */
021230d4 AV	205	};
021230d4 AV	206
9a799d71	207	/* Helper macros to switch between ints/sec and what the register uses.
509ee935 JB	208	* And yes, it's the same math going both ways. The lowest value
509ee935 JB	209	* supported by all of the ixgbe hardware is 8.
9a799d71 AK	210	*/
9a799d71 AK	211	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935	212	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71 AK	213	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	214
	215	#define IXGBE_DESC_UNUSED(R) \
	216	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	217	(R)->next_to_clean - (R)->next_to_use - 1)
	218
	219	#define IXGBE_RX_DESC_ADV(R, i) \
	220	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
	221	#define IXGBE_TX_DESC_ADV(R, i) \
	222	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
	223	#define IXGBE_TX_CTXTDESC_ADV(R, i) \
	224	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
	225
da4dd0f7 PWJ	226	#define IXGBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
	227	#define IXGBE_TX_DESC(R, i) IXGBE_GET_DESC(R, i, ixgbe_legacy_tx_desc)
	228	#define IXGBE_RX_DESC(R, i) IXGBE_GET_DESC(R, i, ixgbe_legacy_rx_desc)
	229
9a799d71	230	#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1 YZ	231	#ifdef IXGBE_FCOE
	232	/* Use 3K as the baby jumbo frame size for FCoE */
	233	#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
	234	#endif /* IXGBE_FCOE */
9a799d71	235
021230d4 AV	236	#define OTHER_VECTOR 1
	237	#define NON_Q_VECTORS (OTHER_VECTOR)
	238
e8e26350 PW	239	#define MAX_MSIX_VECTORS_82599 64
e8e26350 PW	240	#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c PWJ	241	#define MAX_MSIX_VECTORS_82598 18
	242	#define MAX_MSIX_Q_VECTORS_82598 16
	243
e8e26350 PW	244	#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
e8e26350 PW	245	#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c	246
021230d4	247	#define MIN_MSIX_Q_VECTORS 2
021230d4 AV	248	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
021230d4 AV	249
9a799d71 AK	250	/* board specific private data structure */
	251	struct ixgbe_adapter {
	252	struct timer_list watchdog_timer;
	253	struct vlan_group *vlgrp;
	254	u16 bd_number;
9a799d71	255	struct work_struct reset_task;
7a921c93	256	struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350	257	char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865 AD	258	struct ixgbe_dcb_config dcb_cfg;
	259	struct ixgbe_dcb_config temp_dcb_cfg;
	260	u8 dcb_set_bitmap;
264857b8	261	enum ixgbe_fc_mode last_lfc_mode;
9a799d71	262
f494e8fa AV	263	/* Interrupt Throttle Rate */
	264	u32 itr_setting;
	265	u16 eitr_low;
	266	u16 eitr_high;
	267
9a799d71 AK	268	/* TX */
9a799d71 AK	269	struct ixgbe_ring tx_ring; / One per active queue */
30efa5a3	270	int num_tx_queues;
9a799d71	271	u64 restart_queue;
30efa5a3	272	u64 hw_csum_tx_good;
9a799d71 AK	273	u64 lsc_int;
	274	u64 hw_tso_ctxt;
	275	u64 hw_tso6_ctxt;
	276	u32 tx_timeout_count;
	277	bool detect_tx_hung;
	278
	279	/* RX */
	280	struct ixgbe_ring rx_ring; / One per active queue */
30efa5a3	281	int num_rx_queues;
9a799d71	282	u64 hw_csum_rx_error;
e8e26350	283	u64 hw_rx_no_dma_resources;
9a799d71 AK	284	u64 hw_csum_rx_good;
9a799d71 AK	285	u64 non_eop_descs;
021230d4	286	int num_msix_vectors;
eb7f139c	287	int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a	288	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71 AK	289	struct msix_entry *msix_entries;
	290
	291	u64 rx_hdr_split;
	292	u32 alloc_rx_page_failed;
	293	u32 alloc_rx_buff_failed;
	294
021230d4 AV	295	/* Some features need tri-state capability,
	296	* thus the additional *_CAPABLE flags.
	297	*/
9a799d71	298	u32 flags;
96b0e0f6 JB	299	#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
	300	#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
	301	#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
	302	#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
	303	#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
	304	#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
	305	#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
	306	#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
	307	#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
	308	#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
	309	#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
	310	#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
	311	#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350	312	#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6 JB	313	#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
	314	#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
	315	#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
	316	#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e	317	#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 JB	318	#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
96b0e0f6 JB	319	#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
e8e26350 PW	320	#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
e8e26350 PW	321	#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
f8212f97 AD	322	#define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 26)
f8212f97 AD	323	#define IXGBE_FLAG_RSC_ENABLED (u32)(1 << 27)
eacd73f7	324	#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
96b0e0f6 JB	325
	326	/* default to trying for four seconds */
	327	#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71 AK	328
	329	/* OS defined structs */
	330	struct net_device *netdev;
	331	struct pci_dev *pdev;
	332	struct net_device_stats net_stats;
	333
da4dd0f7 PWJ	334	u32 test_icr;
	335	struct ixgbe_ring test_tx_ring;
	336	struct ixgbe_ring test_rx_ring;
	337
9a799d71 AK	338	/* structs defined in ixgbe_hw.h */
	339	struct ixgbe_hw hw;
	340	u16 msg_enable;
	341	struct ixgbe_hw_stats stats;
021230d4 AV	342
021230d4 AV	343	/* Interrupt Throttle Rate */
30efa5a3	344	u32 eitr_param;
9a799d71 AK	345
	346	unsigned long state;
	347	u64 tx_busy;
30efa5a3 JB	348	unsigned int tx_ring_count;
30efa5a3 JB	349	unsigned int rx_ring_count;
cf8280ee JB	350
	351	u32 link_speed;
	352	bool link_up;
	353	unsigned long link_check_timeout;
	354
	355	struct work_struct watchdog_task;
c4900be0 DS	356	struct work_struct sfp_task;
c4900be0 DS	357	struct timer_list sfp_timer;
e8e26350 PW	358	struct work_struct multispeed_fiber_task;
e8e26350 PW	359	struct work_struct sfp_config_module_task;
d0ed8937 YZ	360	#ifdef IXGBE_FCOE
	361	struct ixgbe_fcoe fcoe;
	362	#endif /* IXGBE_FCOE */
f8212f97	363	u64 rsc_count;
e8e26350	364	u32 wol;
34b0368c	365	u16 eeprom_version;
9a799d71 AK	366	};
	367
	368	enum ixbge_state_t {
	369	__IXGBE_TESTING,
	370	__IXGBE_RESETTING,
c4900be0 DS	371	__IXGBE_DOWN,
c4900be0 DS	372	__IXGBE_SFP_MODULE_NOT_FOUND
9a799d71 AK	373	};
	374
	375	enum ixgbe_boards {
3957d63d	376	board_82598,
e8e26350	377	board_82599,
9a799d71 AK	378	};
9a799d71 AK	379
3957d63d	380	extern struct ixgbe_info ixgbe_82598_info;
e8e26350	381	extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51	382	#ifdef CONFIG_IXGBE_DCB
2f90b865 AD	383	extern struct dcbnl_rtnl_ops dcbnl_ops;
	384	extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
	385	struct ixgbe_dcb_config *dst_dcb_cfg,
	386	int tc_max);
	387	#endif
9a799d71 AK	388
9a799d71 AK	389	extern char ixgbe_driver_name[];
9c8eb720	390	extern const char ixgbe_driver_version[];
9a799d71 AK	391
	392	extern int ixgbe_up(struct ixgbe_adapter *adapter);
	393	extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882	394	extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71	395	extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71	396	extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240 PW	397	extern int ixgbe_setup_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	398	extern int ixgbe_setup_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	399	extern void ixgbe_free_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	400	extern void ixgbe_free_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	401	extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865	402	extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93	403	extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
509ee935	404	extern void ixgbe_write_eitr(struct ixgbe_adapter *, int, u32);
eacd73f7 YZ	405	#ifdef IXGBE_FCOE
	406	extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
	407	extern int ixgbe_fso(struct ixgbe_adapter *adapter,
	408	struct ixgbe_ring tx_ring, struct sk_buff skb,
	409	u32 tx_flags, u8 *hdr_len);
332d4a7d YZ	410	extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
	411	extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
	412	union ixgbe_adv_rx_desc *rx_desc,
	413	struct sk_buff *skb);
	414	extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
	415	struct scatterlist *sgl, unsigned int sgc);
	416	extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
eacd73f7	417	#endif /* IXGBE_FCOE */
9a799d71 AK	418
9a799d71 AK	419	#endif /* _IXGBE_H_ */