git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /******************************************************************************* |
| 2 | ||
| 0abb6eb1 | 3 | Intel PRO/10GbE Linux driver |
| f731a9ef | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
| 0abb6eb1 AK |
5 | |
| 6 | This program is free software; you can redistribute it and/or modify it | |
| 7 | under the terms and conditions of the GNU General Public License, | |
| 8 | version 2, as published by the Free Software Foundation. | |
| 9 | ||
| 10 | This program is distributed in the hope it will be useful, but WITHOUT | |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 1da177e4 | 13 | more details. |
| 0abb6eb1 | 14 | |
| 1da177e4 | 15 | You should have received a copy of the GNU General Public License along with |
| 0abb6eb1 AK |
16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 | ||
| 19 | The full GNU General Public License is included in this distribution in | |
| 20 | the file called "COPYING". | |
| 21 | ||
| 1da177e4 LT |
22 | Contact Information: |
| 23 | Linux NICS <linux.nics@intel.com> | |
| 0abb6eb1 | 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 1da177e4 LT |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | ||
| 27 | *******************************************************************************/ | |
| 28 | ||
| 29 | #ifndef _IXGB_HW_H_ | |
| 30 | #define _IXGB_HW_H_ | |
| 31 | ||
| cdbf0eb4 BH |
32 | #include <linux/mdio.h> |
| 33 | ||
| 1da177e4 LT |
34 | #include "ixgb_osdep.h" |
| 35 | ||
| 36 | /* Enums */ | |
| 37 | typedef enum { | |
| 38 | ixgb_mac_unknown = 0, | |
| 39 | ixgb_82597, | |
| 40 | ixgb_num_macs | |
| 41 | } ixgb_mac_type; | |
| 42 | ||
| 43 | /* Types of physical layer modules */ | |
| 44 | typedef enum { | |
| 45 | ixgb_phy_type_unknown = 0, | |
| 46 | ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */ | |
| 47 | ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */ | |
| 48 | ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */ | |
| 8b32e63d MW |
49 | ixgb_phy_type_txn17401, /* 1310nm, SM fiber, XENPAK transceiver */ |
| 50 | ixgb_phy_type_bcm /* SUN specific board */ | |
| 1da177e4 LT |
51 | } ixgb_phy_type; |
| 52 | ||
| 53 | /* XPAK transceiver vendors, for the SR adapters */ | |
| 54 | typedef enum { | |
| 55 | ixgb_xpak_vendor_intel, | |
| 56 | ixgb_xpak_vendor_infineon | |
| 57 | } ixgb_xpak_vendor; | |
| 58 | ||
| 59 | /* Media Types */ | |
| 60 | typedef enum { | |
| 61 | ixgb_media_type_unknown = 0, | |
| 62 | ixgb_media_type_fiber = 1, | |
| 940829e2 | 63 | ixgb_media_type_copper = 2, |
| 1da177e4 LT |
64 | ixgb_num_media_types |
| 65 | } ixgb_media_type; | |
| 66 | ||
| 67 | /* Flow Control Settings */ | |
| 68 | typedef enum { | |
| 69 | ixgb_fc_none = 0, | |
| 70 | ixgb_fc_rx_pause = 1, | |
| 71 | ixgb_fc_tx_pause = 2, | |
| 72 | ixgb_fc_full = 3, | |
| 73 | ixgb_fc_default = 0xFF | |
| 74 | } ixgb_fc_type; | |
| 75 | ||
| 76 | /* PCI bus types */ | |
| 77 | typedef enum { | |
| 78 | ixgb_bus_type_unknown = 0, | |
| 79 | ixgb_bus_type_pci, | |
| 80 | ixgb_bus_type_pcix | |
| 81 | } ixgb_bus_type; | |
| 82 | ||
| 83 | /* PCI bus speeds */ | |
| 84 | typedef enum { | |
| 85 | ixgb_bus_speed_unknown = 0, | |
| 86 | ixgb_bus_speed_33, | |
| 87 | ixgb_bus_speed_66, | |
| 88 | ixgb_bus_speed_100, | |
| 89 | ixgb_bus_speed_133, | |
| 90 | ixgb_bus_speed_reserved | |
| 91 | } ixgb_bus_speed; | |
| 92 | ||
| 93 | /* PCI bus widths */ | |
| 94 | typedef enum { | |
| 95 | ixgb_bus_width_unknown = 0, | |
| 96 | ixgb_bus_width_32, | |
| 97 | ixgb_bus_width_64 | |
| 98 | } ixgb_bus_width; | |
| 99 | ||
| 100 | #define IXGB_ETH_LENGTH_OF_ADDRESS 6 | |
| 101 | ||
| 102 | #define IXGB_EEPROM_SIZE 64 /* Size in words */ | |
| 103 | ||
| 104 | #define SPEED_10000 10000 | |
| 105 | #define FULL_DUPLEX 2 | |
| 106 | ||
| 107 | #define MIN_NUMBER_OF_DESCRIPTORS 8 | |
| 108 | #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */ | |
| 109 | ||
| 110 | #define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */ | |
| 111 | #define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */ | |
| 112 | #define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */ | |
| 113 | ||
| 114 | #define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after the reset */ | |
| 115 | /* NOTE: this is MICROSECONDS */ | |
| 116 | #define MAX_RESET_ITERATIONS 8 /* number of iterations to get things right */ | |
| 117 | ||
| 118 | /* General Registers */ | |
| 119 | #define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */ | |
| 120 | #define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */ | |
| 121 | #define IXGB_STATUS 0x00010 /* Device Status Register - RO */ | |
| 122 | #define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */ | |
| 123 | #define IXGB_MFS 0x00020 /* Maximum Frame Size - RW */ | |
| 124 | ||
| 125 | /* Interrupt */ | |
| 126 | #define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */ | |
| 127 | #define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */ | |
| 128 | #define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */ | |
| 129 | #define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */ | |
| 130 | ||
| 131 | /* Receive */ | |
| 132 | #define IXGB_RCTL 0x00100 /* RX Control - RW */ | |
| 133 | #define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */ | |
| 134 | #define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */ | |
| 135 | #define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */ | |
| 136 | #define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */ | |
| 137 | #define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */ | |
| 138 | #define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */ | |
| 139 | #define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */ | |
| 140 | #define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */ | |
| 141 | #define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */ | |
| 142 | #define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */ | |
| 143 | #define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */ | |
| 144 | #define IXGB_RA 0x00180 /* Receive Address Array Base - RW */ | |
| 145 | #define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */ | |
| 146 | #define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */ | |
| 147 | #define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */ | |
| 148 | #define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */ | |
| 149 | #define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8 | |
| 150 | ||
| 151 | /* Transmit */ | |
| 152 | #define IXGB_TCTL 0x00600 /* TX Control - RW */ | |
| 153 | #define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */ | |
| 154 | #define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */ | |
| 155 | #define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */ | |
| 156 | #define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */ | |
| 157 | #define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */ | |
| 158 | #define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */ | |
| 159 | #define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */ | |
| 160 | #define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */ | |
| 161 | #define IXGB_PAP 0x00640 /* Pause and Pace - RW */ | |
| 162 | #define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8 | |
| 163 | ||
| 164 | /* Physical */ | |
| 165 | #define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */ | |
| 166 | #define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */ | |
| 167 | #define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */ | |
| 168 | #define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */ | |
| 169 | #define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */ | |
| 170 | #define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */ | |
| 171 | #define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */ | |
| 172 | #define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */ | |
| 173 | #define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */ | |
| 174 | #define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */ | |
| 175 | #define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */ | |
| 176 | #define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */ | |
| 177 | #define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */ | |
| 178 | ||
| 179 | /* Wake-up */ | |
| 180 | #define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */ | |
| 181 | #define IXGB_WUS 0x00810 /* Wake Up Status - RO */ | |
| 182 | #define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */ | |
| 183 | #define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */ | |
| 184 | #define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */ | |
| 185 | ||
| 186 | /* Statistics */ | |
| 187 | #define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */ | |
| 188 | #define IXGB_TPRH 0x02004 /* Total Packets Received (High) */ | |
| 189 | #define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */ | |
| 190 | #define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */ | |
| 191 | #define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */ | |
| 192 | #define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */ | |
| 193 | #define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */ | |
| 194 | #define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */ | |
| 195 | #define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */ | |
| 196 | #define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */ | |
| 197 | #define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */ | |
| 198 | #define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */ | |
| 199 | #define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */ | |
| 200 | #define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */ | |
| 201 | #define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */ | |
| 202 | #define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */ | |
| 203 | #define IXGB_TORL 0x02040 /* Total Octets Received (Low) */ | |
| 204 | #define IXGB_TORH 0x02044 /* Total Octets Received (High) */ | |
| 205 | #define IXGB_RNBC 0x02048 /* Receive No Buffers Count */ | |
| 206 | #define IXGB_RUC 0x02050 /* Receive Undersize Count */ | |
| 207 | #define IXGB_ROC 0x02058 /* Receive Oversize Count */ | |
| 208 | #define IXGB_RLEC 0x02060 /* Receive Length Error Count */ | |
| 209 | #define IXGB_CRCERRS 0x02068 /* CRC Error Count */ | |
| 210 | #define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */ | |
| 211 | #define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */ | |
| 212 | #define IXGB_MPC 0x02080 /* Missed Packets Count */ | |
| 213 | #define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */ | |
| 214 | #define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */ | |
| 215 | #define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */ | |
| 216 | #define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */ | |
| 217 | #define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */ | |
| 218 | #define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */ | |
| 219 | #define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */ | |
| 220 | #define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */ | |
| 221 | #define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */ | |
| 222 | #define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */ | |
| 223 | #define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */ | |
| 224 | #define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */ | |
| 225 | #define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */ | |
| 226 | #define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */ | |
| 227 | #define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */ | |
| 228 | #define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */ | |
| 229 | #define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */ | |
| 230 | #define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */ | |
| 231 | #define IXGB_DC 0x02148 /* Defer Count */ | |
| 232 | #define IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */ | |
| 233 | #define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */ | |
| 234 | #define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */ | |
| 235 | #define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */ | |
| 236 | #define IXGB_RFC 0x02188 /* Remote Fault Count */ | |
| 237 | #define IXGB_LFC 0x02190 /* Local Fault Count */ | |
| 238 | #define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */ | |
| 239 | #define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */ | |
| 240 | #define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */ | |
| 241 | #define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */ | |
| 242 | #define IXGB_XONRXC 0x021B8 /* XON Received Count */ | |
| 243 | #define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */ | |
| 244 | #define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */ | |
| 245 | #define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */ | |
| 246 | #define IXGB_RJC 0x021D8 /* Receive Jabber Count */ | |
| 247 | ||
| 248 | /* CTRL0 Bit Masks */ | |
| 249 | #define IXGB_CTRL0_LRST 0x00000008 | |
| 250 | #define IXGB_CTRL0_JFE 0x00000010 | |
| 251 | #define IXGB_CTRL0_XLE 0x00000020 | |
| 252 | #define IXGB_CTRL0_MDCS 0x00000040 | |
| 253 | #define IXGB_CTRL0_CMDC 0x00000080 | |
| 254 | #define IXGB_CTRL0_SDP0 0x00040000 | |
| 255 | #define IXGB_CTRL0_SDP1 0x00080000 | |
| 256 | #define IXGB_CTRL0_SDP2 0x00100000 | |
| 257 | #define IXGB_CTRL0_SDP3 0x00200000 | |
| 258 | #define IXGB_CTRL0_SDP0_DIR 0x00400000 | |
| 259 | #define IXGB_CTRL0_SDP1_DIR 0x00800000 | |
| 260 | #define IXGB_CTRL0_SDP2_DIR 0x01000000 | |
| 261 | #define IXGB_CTRL0_SDP3_DIR 0x02000000 | |
| 262 | #define IXGB_CTRL0_RST 0x04000000 | |
| 263 | #define IXGB_CTRL0_RPE 0x08000000 | |
| 264 | #define IXGB_CTRL0_TPE 0x10000000 | |
| 265 | #define IXGB_CTRL0_VME 0x40000000 | |
| 266 | ||
| 267 | /* CTRL1 Bit Masks */ | |
| 268 | #define IXGB_CTRL1_GPI0_EN 0x00000001 | |
| 269 | #define IXGB_CTRL1_GPI1_EN 0x00000002 | |
| 270 | #define IXGB_CTRL1_GPI2_EN 0x00000004 | |
| 271 | #define IXGB_CTRL1_GPI3_EN 0x00000008 | |
| 272 | #define IXGB_CTRL1_SDP4 0x00000010 | |
| 273 | #define IXGB_CTRL1_SDP5 0x00000020 | |
| 274 | #define IXGB_CTRL1_SDP6 0x00000040 | |
| 275 | #define IXGB_CTRL1_SDP7 0x00000080 | |
| 276 | #define IXGB_CTRL1_SDP4_DIR 0x00000100 | |
| 277 | #define IXGB_CTRL1_SDP5_DIR 0x00000200 | |
| 278 | #define IXGB_CTRL1_SDP6_DIR 0x00000400 | |
| 279 | #define IXGB_CTRL1_SDP7_DIR 0x00000800 | |
| 280 | #define IXGB_CTRL1_EE_RST 0x00002000 | |
| 281 | #define IXGB_CTRL1_RO_DIS 0x00020000 | |
| 282 | #define IXGB_CTRL1_PCIXHM_MASK 0x00C00000 | |
| 283 | #define IXGB_CTRL1_PCIXHM_1_2 0x00000000 | |
| 284 | #define IXGB_CTRL1_PCIXHM_5_8 0x00400000 | |
| 285 | #define IXGB_CTRL1_PCIXHM_3_4 0x00800000 | |
| 286 | #define IXGB_CTRL1_PCIXHM_7_8 0x00C00000 | |
| 287 | ||
| 288 | /* STATUS Bit Masks */ | |
| 289 | #define IXGB_STATUS_LU 0x00000002 | |
| 290 | #define IXGB_STATUS_AIP 0x00000004 | |
| 291 | #define IXGB_STATUS_TXOFF 0x00000010 | |
| 292 | #define IXGB_STATUS_XAUIME 0x00000020 | |
| 293 | #define IXGB_STATUS_RES 0x00000040 | |
| 294 | #define IXGB_STATUS_RIS 0x00000080 | |
| 295 | #define IXGB_STATUS_RIE 0x00000100 | |
| 296 | #define IXGB_STATUS_RLF 0x00000200 | |
| 297 | #define IXGB_STATUS_RRF 0x00000400 | |
| 298 | #define IXGB_STATUS_PCI_SPD 0x00000800 | |
| 299 | #define IXGB_STATUS_BUS64 0x00001000 | |
| 300 | #define IXGB_STATUS_PCIX_MODE 0x00002000 | |
| 301 | #define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000 | |
| 302 | #define IXGB_STATUS_PCIX_SPD_66 0x00000000 | |
| 303 | #define IXGB_STATUS_PCIX_SPD_100 0x00004000 | |
| 304 | #define IXGB_STATUS_PCIX_SPD_133 0x00008000 | |
| 305 | #define IXGB_STATUS_REV_ID_MASK 0x000F0000 | |
| 306 | #define IXGB_STATUS_REV_ID_SHIFT 16 | |
| 307 | ||
| 308 | /* EECD Bit Masks */ | |
| 309 | #define IXGB_EECD_SK 0x00000001 | |
| 310 | #define IXGB_EECD_CS 0x00000002 | |
| 311 | #define IXGB_EECD_DI 0x00000004 | |
| 312 | #define IXGB_EECD_DO 0x00000008 | |
| 313 | #define IXGB_EECD_FWE_MASK 0x00000030 | |
| 314 | #define IXGB_EECD_FWE_DIS 0x00000010 | |
| 315 | #define IXGB_EECD_FWE_EN 0x00000020 | |
| 316 | ||
| 317 | /* MFS */ | |
| 318 | #define IXGB_MFS_SHIFT 16 | |
| 319 | ||
| 320 | /* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */ | |
| 321 | #define IXGB_INT_TXDW 0x00000001 | |
| 322 | #define IXGB_INT_TXQE 0x00000002 | |
| 323 | #define IXGB_INT_LSC 0x00000004 | |
| 324 | #define IXGB_INT_RXSEQ 0x00000008 | |
| 325 | #define IXGB_INT_RXDMT0 0x00000010 | |
| 326 | #define IXGB_INT_RXO 0x00000040 | |
| 327 | #define IXGB_INT_RXT0 0x00000080 | |
| 328 | #define IXGB_INT_AUTOSCAN 0x00000200 | |
| 329 | #define IXGB_INT_GPI0 0x00000800 | |
| 330 | #define IXGB_INT_GPI1 0x00001000 | |
| 331 | #define IXGB_INT_GPI2 0x00002000 | |
| 332 | #define IXGB_INT_GPI3 0x00004000 | |
| 333 | ||
| 334 | /* RCTL Bit Masks */ | |
| 335 | #define IXGB_RCTL_RXEN 0x00000002 | |
| 336 | #define IXGB_RCTL_SBP 0x00000004 | |
| 337 | #define IXGB_RCTL_UPE 0x00000008 | |
| 338 | #define IXGB_RCTL_MPE 0x00000010 | |
| 339 | #define IXGB_RCTL_RDMTS_MASK 0x00000300 | |
| 340 | #define IXGB_RCTL_RDMTS_1_2 0x00000000 | |
| 341 | #define IXGB_RCTL_RDMTS_1_4 0x00000100 | |
| 342 | #define IXGB_RCTL_RDMTS_1_8 0x00000200 | |
| 343 | #define IXGB_RCTL_MO_MASK 0x00003000 | |
| 344 | #define IXGB_RCTL_MO_47_36 0x00000000 | |
| 345 | #define IXGB_RCTL_MO_46_35 0x00001000 | |
| 346 | #define IXGB_RCTL_MO_45_34 0x00002000 | |
| 347 | #define IXGB_RCTL_MO_43_32 0x00003000 | |
| 348 | #define IXGB_RCTL_MO_SHIFT 12 | |
| 349 | #define IXGB_RCTL_BAM 0x00008000 | |
| 350 | #define IXGB_RCTL_BSIZE_MASK 0x00030000 | |
| 351 | #define IXGB_RCTL_BSIZE_2048 0x00000000 | |
| 352 | #define IXGB_RCTL_BSIZE_4096 0x00010000 | |
| 353 | #define IXGB_RCTL_BSIZE_8192 0x00020000 | |
| 354 | #define IXGB_RCTL_BSIZE_16384 0x00030000 | |
| 355 | #define IXGB_RCTL_VFE 0x00040000 | |
| 356 | #define IXGB_RCTL_CFIEN 0x00080000 | |
| 357 | #define IXGB_RCTL_CFI 0x00100000 | |
| 358 | #define IXGB_RCTL_RPDA_MASK 0x00600000 | |
| 359 | #define IXGB_RCTL_RPDA_MC_MAC 0x00000000 | |
| 360 | #define IXGB_RCTL_MC_ONLY 0x00400000 | |
| 361 | #define IXGB_RCTL_CFF 0x00800000 | |
| 362 | #define IXGB_RCTL_SECRC 0x04000000 | |
| 363 | #define IXGB_RDT_FPDB 0x80000000 | |
| 364 | ||
| 365 | #define IXGB_RCTL_IDLE_RX_UNIT 0 | |
| 366 | ||
| 367 | /* FCRTL Bit Masks */ | |
| 368 | #define IXGB_FCRTL_XONE 0x80000000 | |
| 369 | ||
| 370 | /* RXDCTL Bit Masks */ | |
| 371 | #define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF | |
| 372 | #define IXGB_RXDCTL_PTHRESH_SHIFT 0 | |
| 373 | #define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00 | |
| 374 | #define IXGB_RXDCTL_HTHRESH_SHIFT 9 | |
| 375 | #define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000 | |
| 376 | #define IXGB_RXDCTL_WTHRESH_SHIFT 18 | |
| 377 | ||
| 378 | /* RAIDC Bit Masks */ | |
| 379 | #define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F | |
| 380 | #define IXGB_RAIDC_DELAY_MASK 0x000FF800 | |
| 381 | #define IXGB_RAIDC_DELAY_SHIFT 11 | |
| 382 | #define IXGB_RAIDC_POLL_MASK 0x1FF00000 | |
| 383 | #define IXGB_RAIDC_POLL_SHIFT 20 | |
| 384 | #define IXGB_RAIDC_RXT_GATE 0x40000000 | |
| 385 | #define IXGB_RAIDC_EN 0x80000000 | |
| 386 | ||
| 387 | #define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220 | |
| 388 | #define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244 | |
| 389 | #define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122 | |
| 390 | #define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61 | |
| 391 | ||
| 392 | /* RXCSUM Bit Masks */ | |
| 393 | #define IXGB_RXCSUM_IPOFL 0x00000100 | |
| 394 | #define IXGB_RXCSUM_TUOFL 0x00000200 | |
| 395 | ||
| 396 | /* RAH Bit Masks */ | |
| 397 | #define IXGB_RAH_ASEL_MASK 0x00030000 | |
| 398 | #define IXGB_RAH_ASEL_DEST 0x00000000 | |
| 399 | #define IXGB_RAH_ASEL_SRC 0x00010000 | |
| 400 | #define IXGB_RAH_AV 0x80000000 | |
| 401 | ||
| 402 | /* TCTL Bit Masks */ | |
| 403 | #define IXGB_TCTL_TCE 0x00000001 | |
| 404 | #define IXGB_TCTL_TXEN 0x00000002 | |
| 405 | #define IXGB_TCTL_TPDE 0x00000004 | |
| 406 | ||
| 407 | #define IXGB_TCTL_IDLE_TX_UNIT 0 | |
| 408 | ||
| 409 | /* TXDCTL Bit Masks */ | |
| 410 | #define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F | |
| 411 | #define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00 | |
| 412 | #define IXGB_TXDCTL_HTHRESH_SHIFT 8 | |
| 413 | #define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000 | |
| 414 | #define IXGB_TXDCTL_WTHRESH_SHIFT 16 | |
| 415 | ||
| 416 | /* TSPMT Bit Masks */ | |
| 417 | #define IXGB_TSPMT_TSMT_MASK 0x0000FFFF | |
| 418 | #define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000 | |
| 419 | #define IXGB_TSPMT_TSPBP_SHIFT 16 | |
| 420 | ||
| 421 | /* PAP Bit Masks */ | |
| 422 | #define IXGB_PAP_TXPC_MASK 0x0000FFFF | |
| 423 | #define IXGB_PAP_TXPV_MASK 0x000F0000 | |
| 424 | #define IXGB_PAP_TXPV_10G 0x00000000 | |
| 425 | #define IXGB_PAP_TXPV_1G 0x00010000 | |
| 426 | #define IXGB_PAP_TXPV_2G 0x00020000 | |
| 427 | #define IXGB_PAP_TXPV_3G 0x00030000 | |
| 428 | #define IXGB_PAP_TXPV_4G 0x00040000 | |
| 429 | #define IXGB_PAP_TXPV_5G 0x00050000 | |
| 430 | #define IXGB_PAP_TXPV_6G 0x00060000 | |
| 431 | #define IXGB_PAP_TXPV_7G 0x00070000 | |
| 432 | #define IXGB_PAP_TXPV_8G 0x00080000 | |
| 433 | #define IXGB_PAP_TXPV_9G 0x00090000 | |
| 434 | #define IXGB_PAP_TXPV_WAN 0x000F0000 | |
| 435 | ||
| 436 | /* PCSC1 Bit Masks */ | |
| 437 | #define IXGB_PCSC1_LOOPBACK 0x00004000 | |
| 438 | ||
| 439 | /* PCSC2 Bit Masks */ | |
| 440 | #define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003 | |
| 441 | #define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001 | |
| 442 | ||
| 443 | /* PCSS1 Bit Masks */ | |
| 444 | #define IXGB_PCSS1_LOCAL_FAULT 0x00000080 | |
| 445 | #define IXGB_PCSS1_RX_LINK_STATUS 0x00000004 | |
| 446 | ||
| 447 | /* PCSS2 Bit Masks */ | |
| 448 | #define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000 | |
| 449 | #define IXGB_PCSS2_DEV_PRES 0x00004000 | |
| 450 | #define IXGB_PCSS2_TX_LF 0x00000800 | |
| 451 | #define IXGB_PCSS2_RX_LF 0x00000400 | |
| 452 | #define IXGB_PCSS2_10GBW 0x00000004 | |
| 453 | #define IXGB_PCSS2_10GBX 0x00000002 | |
| 454 | #define IXGB_PCSS2_10GBR 0x00000001 | |
| 455 | ||
| 456 | /* XPCSS Bit Masks */ | |
| 457 | #define IXGB_XPCSS_ALIGN_STATUS 0x00001000 | |
| 458 | #define IXGB_XPCSS_PATTERN_TEST 0x00000800 | |
| 459 | #define IXGB_XPCSS_LANE_3_SYNC 0x00000008 | |
| 460 | #define IXGB_XPCSS_LANE_2_SYNC 0x00000004 | |
| 461 | #define IXGB_XPCSS_LANE_1_SYNC 0x00000002 | |
| 462 | #define IXGB_XPCSS_LANE_0_SYNC 0x00000001 | |
| 463 | ||
| 464 | /* XPCSTC Bit Masks */ | |
| 465 | #define IXGB_XPCSTC_BERT_TRIG 0x00200000 | |
| 466 | #define IXGB_XPCSTC_BERT_SST 0x00100000 | |
| 467 | #define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000 | |
| 468 | #define IXGB_XPCSTC_BERT_PSZ_SHIFT 17 | |
| 469 | #define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003 | |
| 470 | #define IXGB_XPCSTC_BERT_PSZ_68 0x00000001 | |
| 471 | #define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000 | |
| 472 | ||
| 473 | /* MSCA bit Masks */ | |
| 474 | /* New Protocol Address */ | |
| 475 | #define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF | |
| 476 | #define IXGB_MSCA_NP_ADDR_SHIFT 0 | |
| 477 | /* Either Device Type or Register Address,depending on ST_CODE */ | |
| 478 | #define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000 | |
| 479 | #define IXGB_MSCA_DEV_TYPE_SHIFT 16 | |
| 480 | #define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000 | |
| 481 | #define IXGB_MSCA_PHY_ADDR_SHIFT 21 | |
| 482 | #define IXGB_MSCA_OP_CODE_MASK 0x0C000000 | |
| 483 | /* OP_CODE == 00, Address cycle, New Protocol */ | |
| 484 | /* OP_CODE == 01, Write operation */ | |
| 485 | /* OP_CODE == 10, Read operation */ | |
| 486 | /* OP_CODE == 11, Read, auto increment, New Protocol */ | |
| 487 | #define IXGB_MSCA_ADDR_CYCLE 0x00000000 | |
| 488 | #define IXGB_MSCA_WRITE 0x04000000 | |
| 489 | #define IXGB_MSCA_READ 0x08000000 | |
| 490 | #define IXGB_MSCA_READ_AUTOINC 0x0C000000 | |
| 491 | #define IXGB_MSCA_OP_CODE_SHIFT 26 | |
| 492 | #define IXGB_MSCA_ST_CODE_MASK 0x30000000 | |
| 493 | /* ST_CODE == 00, New Protocol */ | |
| 494 | /* ST_CODE == 01, Old Protocol */ | |
| 495 | #define IXGB_MSCA_NEW_PROTOCOL 0x00000000 | |
| 496 | #define IXGB_MSCA_OLD_PROTOCOL 0x10000000 | |
| 497 | #define IXGB_MSCA_ST_CODE_SHIFT 28 | |
| 498 | /* Initiate command, self-clearing when command completes */ | |
| 499 | #define IXGB_MSCA_MDI_COMMAND 0x40000000 | |
| 500 | /*MDI In Progress Enable. */ | |
| 501 | #define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000 | |
| 502 | ||
| 503 | /* MSRWD bit masks */ | |
| 504 | #define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF | |
| 505 | #define IXGB_MSRWD_WRITE_DATA_SHIFT 0 | |
| 506 | #define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000 | |
| 507 | #define IXGB_MSRWD_READ_DATA_SHIFT 16 | |
| 508 | ||
| 509 | /* Definitions for the optics devices on the MDIO bus. */ | |
| 510 | #define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */ | |
| 511 | ||
| 1da177e4 LT |
512 | #define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */ |
| 513 | ||
| 514 | /* Vendor-specific MDIO registers */ | |
| 515 | #define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */ | |
| 516 | #define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */ | |
| 517 | ||
| 518 | #define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80 | |
| 519 | #define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00 | |
| 520 | #define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */ | |
| 521 | ||
| 522 | /* Layout of a single receive descriptor. The controller assumes that this | |
| 523 | * structure is packed into 16 bytes, which is a safe assumption with most | |
| 524 | * compilers. However, some compilers may insert padding between the fields, | |
| 525 | * in which case the structure must be packed in some compiler-specific | |
| 526 | * manner. */ | |
| 527 | struct ixgb_rx_desc { | |
| a7df90a5 AV |
528 | __le64 buff_addr; |
| 529 | __le16 length; | |
| 530 | __le16 reserved; | |
| 222441a6 JP |
531 | u8 status; |
| 532 | u8 errors; | |
| a7df90a5 | 533 | __le16 special; |
| 1da177e4 LT |
534 | }; |
| 535 | ||
| 536 | #define IXGB_RX_DESC_STATUS_DD 0x01 | |
| 537 | #define IXGB_RX_DESC_STATUS_EOP 0x02 | |
| 538 | #define IXGB_RX_DESC_STATUS_IXSM 0x04 | |
| 539 | #define IXGB_RX_DESC_STATUS_VP 0x08 | |
| 540 | #define IXGB_RX_DESC_STATUS_TCPCS 0x20 | |
| 541 | #define IXGB_RX_DESC_STATUS_IPCS 0x40 | |
| 542 | #define IXGB_RX_DESC_STATUS_PIF 0x80 | |
| 543 | ||
| 544 | #define IXGB_RX_DESC_ERRORS_CE 0x01 | |
| 545 | #define IXGB_RX_DESC_ERRORS_SE 0x02 | |
| 546 | #define IXGB_RX_DESC_ERRORS_P 0x08 | |
| 547 | #define IXGB_RX_DESC_ERRORS_TCPE 0x20 | |
| 548 | #define IXGB_RX_DESC_ERRORS_IPE 0x40 | |
| 549 | #define IXGB_RX_DESC_ERRORS_RXE 0x80 | |
| 550 | ||
| 551 | #define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | |
| 552 | #define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ | |
| 553 | #define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ | |
| 554 | ||
| 555 | /* Layout of a single transmit descriptor. The controller assumes that this | |
| 556 | * structure is packed into 16 bytes, which is a safe assumption with most | |
| 557 | * compilers. However, some compilers may insert padding between the fields, | |
| 558 | * in which case the structure must be packed in some compiler-specific | |
| 559 | * manner. */ | |
| 560 | struct ixgb_tx_desc { | |
| a7df90a5 AV |
561 | __le64 buff_addr; |
| 562 | __le32 cmd_type_len; | |
| 222441a6 JP |
563 | u8 status; |
| 564 | u8 popts; | |
| a7df90a5 | 565 | __le16 vlan; |
| 1da177e4 LT |
566 | }; |
| 567 | ||
| 568 | #define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF | |
| 569 | #define IXGB_TX_DESC_TYPE_MASK 0x00F00000 | |
| 570 | #define IXGB_TX_DESC_TYPE_SHIFT 20 | |
| 571 | #define IXGB_TX_DESC_CMD_MASK 0xFF000000 | |
| 572 | #define IXGB_TX_DESC_CMD_SHIFT 24 | |
| 573 | #define IXGB_TX_DESC_CMD_EOP 0x01000000 | |
| 574 | #define IXGB_TX_DESC_CMD_TSE 0x04000000 | |
| 575 | #define IXGB_TX_DESC_CMD_RS 0x08000000 | |
| 576 | #define IXGB_TX_DESC_CMD_VLE 0x40000000 | |
| 577 | #define IXGB_TX_DESC_CMD_IDE 0x80000000 | |
| 578 | ||
| 579 | #define IXGB_TX_DESC_TYPE 0x00100000 | |
| 580 | ||
| 581 | #define IXGB_TX_DESC_STATUS_DD 0x01 | |
| 582 | ||
| 583 | #define IXGB_TX_DESC_POPTS_IXSM 0x01 | |
| 584 | #define IXGB_TX_DESC_POPTS_TXSM 0x02 | |
| 585 | #define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */ | |
| 586 | ||
| 587 | struct ixgb_context_desc { | |
| 222441a6 JP |
588 | u8 ipcss; |
| 589 | u8 ipcso; | |
| a7df90a5 | 590 | __le16 ipcse; |
| 222441a6 JP |
591 | u8 tucss; |
| 592 | u8 tucso; | |
| a7df90a5 AV |
593 | __le16 tucse; |
| 594 | __le32 cmd_type_len; | |
| 222441a6 JP |
595 | u8 status; |
| 596 | u8 hdr_len; | |
| a7df90a5 | 597 | __le16 mss; |
| 1da177e4 LT |
598 | }; |
| 599 | ||
| 600 | #define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000 | |
| 601 | #define IXGB_CONTEXT_DESC_CMD_IP 0x02000000 | |
| 602 | #define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000 | |
| 603 | #define IXGB_CONTEXT_DESC_CMD_RS 0x08000000 | |
| 604 | #define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000 | |
| 605 | ||
| 606 | #define IXGB_CONTEXT_DESC_TYPE 0x00000000 | |
| 607 | ||
| 608 | #define IXGB_CONTEXT_DESC_STATUS_DD 0x01 | |
| 609 | ||
| 610 | /* Filters */ | |
| 611 | #define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ | |
| 612 | #define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ | |
| 613 | #define IXGB_RAR_ENTRIES 3 /* Number of entries in Rx Address array */ | |
| 614 | ||
| 615 | #define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0 | |
| 616 | #define ENET_HEADER_SIZE 14 | |
| 617 | #define ENET_FCS_LENGTH 4 | |
| 618 | #define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128 | |
| 619 | #define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60 | |
| 620 | #define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514 | |
| 621 | #define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00 | |
| 622 | ||
| 623 | /* Phy Addresses */ | |
| 624 | #define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */ | |
| 625 | #define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */ | |
| 626 | #define IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */ | |
| 627 | ||
| 628 | /* This structure takes a 64k flash and maps it for identification commands */ | |
| 629 | struct ixgb_flash_buffer { | |
| 222441a6 JP |
630 | u8 manufacturer_id; |
| 631 | u8 device_id; | |
| 632 | u8 filler1[0x2AA8]; | |
| 633 | u8 cmd2; | |
| 634 | u8 filler2[0x2AAA]; | |
| 635 | u8 cmd1; | |
| 636 | u8 filler3[0xAAAA]; | |
| 1da177e4 LT |
637 | }; |
| 638 | ||
| 1da177e4 LT |
639 | /* Flow control parameters */ |
| 640 | struct ixgb_fc { | |
| 222441a6 JP |
641 | u32 high_water; /* Flow Control High-water */ |
| 642 | u32 low_water; /* Flow Control Low-water */ | |
| 643 | u16 pause_time; /* Flow Control Pause timer */ | |
| 446490ca | 644 | bool send_xon; /* Flow control send XON */ |
| 1da177e4 LT |
645 | ixgb_fc_type type; /* Type of flow control */ |
| 646 | }; | |
| 647 | ||
| 648 | /* The historical defaults for the flow control values are given below. */ | |
| 649 | #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ | |
| 650 | #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ | |
| 651 | #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ | |
| 652 | ||
| 653 | /* Phy definitions */ | |
| 654 | #define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF | |
| 655 | #define IXGB_MAX_PHY_ADDRESS 31 | |
| 656 | #define IXGB_MAX_PHY_DEV_TYPE 31 | |
| 657 | ||
| 658 | /* Bus parameters */ | |
| 659 | struct ixgb_bus { | |
| 660 | ixgb_bus_speed speed; | |
| 661 | ixgb_bus_width width; | |
| 662 | ixgb_bus_type type; | |
| 663 | }; | |
| 664 | ||
| 665 | struct ixgb_hw { | |
| 222441a6 | 666 | u8 __iomem *hw_addr;/* Base Address of the hardware */ |
| 1da177e4 LT |
667 | void *back; /* Pointer to OS-dependent struct */ |
| 668 | struct ixgb_fc fc; /* Flow control parameters */ | |
| 669 | struct ixgb_bus bus; /* Bus parameters */ | |
| 222441a6 JP |
670 | u32 phy_id; /* Phy Identifier */ |
| 671 | u32 phy_addr; /* XGMII address of Phy */ | |
| 1da177e4 LT |
672 | ixgb_mac_type mac_type; /* Identifier for MAC controller */ |
| 673 | ixgb_phy_type phy_type; /* Transceiver/phy identifier */ | |
| 222441a6 JP |
674 | u32 max_frame_size; /* Maximum frame size supported */ |
| 675 | u32 mc_filter_type; /* Multicast filter hash type */ | |
| 676 | u32 num_mc_addrs; /* Number of current Multicast addrs */ | |
| 677 | u8 curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */ | |
| 678 | u32 num_tx_desc; /* Number of Transmit descriptors */ | |
| 679 | u32 num_rx_desc; /* Number of Receive descriptors */ | |
| 680 | u32 rx_buffer_size; /* Size of Receive buffer */ | |
| 446490ca JP |
681 | bool link_up; /* true if link is valid */ |
| 682 | bool adapter_stopped; /* State of adapter */ | |
| 222441a6 JP |
683 | u16 device_id; /* device id from PCI configuration space */ |
| 684 | u16 vendor_id; /* vendor id from PCI configuration space */ | |
| 685 | u8 revision_id; /* revision id from PCI configuration space */ | |
| 686 | u16 subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */ | |
| 687 | u16 subsystem_id; /* subsystem id from PCI configuration space */ | |
| 688 | u32 bar0; /* Base Address registers */ | |
| 689 | u32 bar1; | |
| 690 | u32 bar2; | |
| 691 | u32 bar3; | |
| 692 | u16 pci_cmd_word; /* PCI command register id from PCI configuration space */ | |
| c676504e | 693 | __le16 eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */ |
| 1da177e4 | 694 | unsigned long io_base; /* Our I/O mapped location */ |
| 222441a6 JP |
695 | u32 lastLFC; |
| 696 | u32 lastRFC; | |
| 1da177e4 LT |
697 | }; |
| 698 | ||
| 699 | /* Statistics reported by the hardware */ | |
| 700 | struct ixgb_hw_stats { | |
| 222441a6 JP |
701 | u64 tprl; |
| 702 | u64 tprh; | |
| 703 | u64 gprcl; | |
| 704 | u64 gprch; | |
| 705 | u64 bprcl; | |
| 706 | u64 bprch; | |
| 707 | u64 mprcl; | |
| 708 | u64 mprch; | |
| 709 | u64 uprcl; | |
| 710 | u64 uprch; | |
| 711 | u64 vprcl; | |
| 712 | u64 vprch; | |
| 713 | u64 jprcl; | |
| 714 | u64 jprch; | |
| 715 | u64 gorcl; | |
| 716 | u64 gorch; | |
| 717 | u64 torl; | |
| 718 | u64 torh; | |
| 719 | u64 rnbc; | |
| 720 | u64 ruc; | |
| 721 | u64 roc; | |
| 722 | u64 rlec; | |
| 723 | u64 crcerrs; | |
| 724 | u64 icbc; | |
| 725 | u64 ecbc; | |
| 726 | u64 mpc; | |
| 727 | u64 tptl; | |
| 728 | u64 tpth; | |
| 729 | u64 gptcl; | |
| 730 | u64 gptch; | |
| 731 | u64 bptcl; | |
| 732 | u64 bptch; | |
| 733 | u64 mptcl; | |
| 734 | u64 mptch; | |
| 735 | u64 uptcl; | |
| 736 | u64 uptch; | |
| 737 | u64 vptcl; | |
| 738 | u64 vptch; | |
| 739 | u64 jptcl; | |
| 740 | u64 jptch; | |
| 741 | u64 gotcl; | |
| 742 | u64 gotch; | |
| 743 | u64 totl; | |
| 744 | u64 toth; | |
| 745 | u64 dc; | |
| 746 | u64 plt64c; | |
| 747 | u64 tsctc; | |
| 748 | u64 tsctfc; | |
| 749 | u64 ibic; | |
| 750 | u64 rfc; | |
| 751 | u64 lfc; | |
| 752 | u64 pfrc; | |
| 753 | u64 pftc; | |
| 754 | u64 mcfrc; | |
| 755 | u64 mcftc; | |
| 756 | u64 xonrxc; | |
| 757 | u64 xontxc; | |
| 758 | u64 xoffrxc; | |
| 759 | u64 xofftxc; | |
| 760 | u64 rjc; | |
| 1da177e4 LT |
761 | }; |
| 762 | ||
| 763 | /* Function Prototypes */ | |
| 446490ca JP |
764 | extern bool ixgb_adapter_stop(struct ixgb_hw *hw); |
| 765 | extern bool ixgb_init_hw(struct ixgb_hw *hw); | |
| 766 | extern bool ixgb_adapter_start(struct ixgb_hw *hw); | |
| 1da177e4 | 767 | extern void ixgb_check_for_link(struct ixgb_hw *hw); |
| 446490ca | 768 | extern bool ixgb_check_for_bad_link(struct ixgb_hw *hw); |
| 1da177e4 LT |
769 | |
| 770 | extern void ixgb_rar_set(struct ixgb_hw *hw, | |
| 222441a6 JP |
771 | u8 *addr, |
| 772 | u32 index); | |
| 1da177e4 LT |
773 | |
| 774 | ||
| 775 | /* Filters (multicast, vlan, receive) */ | |
| 776 | extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, | |
| 222441a6 JP |
777 | u8 *mc_addr_list, |
| 778 | u32 mc_addr_count, | |
| 779 | u32 pad); | |
| 1da177e4 LT |
780 | |
| 781 | /* Vfta functions */ | |
| 782 | extern void ixgb_write_vfta(struct ixgb_hw *hw, | |
| 222441a6 JP |
783 | u32 offset, |
| 784 | u32 value); | |
| 1da177e4 | 785 | |
| 1da177e4 | 786 | /* Access functions to eeprom data */ |
| 222441a6 JP |
787 | void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, u8 *mac_addr); |
| 788 | u32 ixgb_get_ee_pba_number(struct ixgb_hw *hw); | |
| 789 | u16 ixgb_get_ee_device_id(struct ixgb_hw *hw); | |
| 446490ca | 790 | bool ixgb_get_eeprom_data(struct ixgb_hw *hw); |
| 222441a6 | 791 | __le16 ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index); |
| 1da177e4 LT |
792 | |
| 793 | /* Everything else */ | |
| 794 | void ixgb_led_on(struct ixgb_hw *hw); | |
| 795 | void ixgb_led_off(struct ixgb_hw *hw); | |
| 796 | void ixgb_write_pci_cfg(struct ixgb_hw *hw, | |
| 222441a6 JP |
797 | u32 reg, |
| 798 | u16 * value); | |
| 1da177e4 LT |
799 | |
| 800 | ||
| 801 | #endif /* _IXGB_HW_H_ */ |