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1da177e4 LT |
1 | /******************************************************************************* |
2 | ||
0abb6eb1 | 3 | Intel PRO/10GbE Linux driver |
f731a9ef | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
0abb6eb1 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
1da177e4 | 13 | more details. |
0abb6eb1 | 14 | |
1da177e4 | 15 | You should have received a copy of the GNU General Public License along with |
0abb6eb1 AK |
16 | this program; if not, write to the Free Software Foundation, Inc., |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
1da177e4 LT |
22 | Contact Information: |
23 | Linux NICS <linux.nics@intel.com> | |
0abb6eb1 | 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
1da177e4 LT |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
d328bc83 JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
1da177e4 LT |
31 | #include "ixgb_hw.h" |
32 | #include "ixgb_ee.h" | |
33 | /* Local prototypes */ | |
222441a6 | 34 | static u16 ixgb_shift_in_bits(struct ixgb_hw *hw); |
1da177e4 LT |
35 | |
36 | static void ixgb_shift_out_bits(struct ixgb_hw *hw, | |
222441a6 JP |
37 | u16 data, |
38 | u16 count); | |
1da177e4 LT |
39 | static void ixgb_standby_eeprom(struct ixgb_hw *hw); |
40 | ||
446490ca | 41 | static bool ixgb_wait_eeprom_command(struct ixgb_hw *hw); |
1da177e4 LT |
42 | |
43 | static void ixgb_cleanup_eeprom(struct ixgb_hw *hw); | |
44 | ||
45 | /****************************************************************************** | |
46 | * Raises the EEPROM's clock input. | |
47 | * | |
48 | * hw - Struct containing variables accessed by shared code | |
49 | * eecd_reg - EECD's current value | |
50 | *****************************************************************************/ | |
51 | static void | |
52 | ixgb_raise_clock(struct ixgb_hw *hw, | |
222441a6 | 53 | u32 *eecd_reg) |
1da177e4 LT |
54 | { |
55 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then | |
56 | * wait 50 microseconds. | |
57 | */ | |
58 | *eecd_reg = *eecd_reg | IXGB_EECD_SK; | |
59 | IXGB_WRITE_REG(hw, EECD, *eecd_reg); | |
60 | udelay(50); | |
61 | return; | |
62 | } | |
63 | ||
64 | /****************************************************************************** | |
65 | * Lowers the EEPROM's clock input. | |
66 | * | |
67 | * hw - Struct containing variables accessed by shared code | |
68 | * eecd_reg - EECD's current value | |
69 | *****************************************************************************/ | |
70 | static void | |
71 | ixgb_lower_clock(struct ixgb_hw *hw, | |
222441a6 | 72 | u32 *eecd_reg) |
1da177e4 LT |
73 | { |
74 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then | |
75 | * wait 50 microseconds. | |
76 | */ | |
77 | *eecd_reg = *eecd_reg & ~IXGB_EECD_SK; | |
78 | IXGB_WRITE_REG(hw, EECD, *eecd_reg); | |
79 | udelay(50); | |
80 | return; | |
81 | } | |
82 | ||
83 | /****************************************************************************** | |
84 | * Shift data bits out to the EEPROM. | |
85 | * | |
86 | * hw - Struct containing variables accessed by shared code | |
87 | * data - data to send to the EEPROM | |
88 | * count - number of bits to shift out | |
89 | *****************************************************************************/ | |
90 | static void | |
91 | ixgb_shift_out_bits(struct ixgb_hw *hw, | |
222441a6 JP |
92 | u16 data, |
93 | u16 count) | |
1da177e4 | 94 | { |
222441a6 JP |
95 | u32 eecd_reg; |
96 | u32 mask; | |
1da177e4 LT |
97 | |
98 | /* We need to shift "count" bits out to the EEPROM. So, value in the | |
99 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
100 | * In order to do this, "data" must be broken down into bits. | |
101 | */ | |
102 | mask = 0x01 << (count - 1); | |
103 | eecd_reg = IXGB_READ_REG(hw, EECD); | |
104 | eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI); | |
105 | do { | |
106 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", | |
107 | * and then raising and then lowering the clock (the SK bit controls | |
108 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM | |
109 | * by setting "DI" to "0" and then raising and then lowering the clock. | |
110 | */ | |
111 | eecd_reg &= ~IXGB_EECD_DI; | |
112 | ||
03f83041 | 113 | if (data & mask) |
1da177e4 LT |
114 | eecd_reg |= IXGB_EECD_DI; |
115 | ||
116 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
117 | ||
118 | udelay(50); | |
119 | ||
120 | ixgb_raise_clock(hw, &eecd_reg); | |
121 | ixgb_lower_clock(hw, &eecd_reg); | |
122 | ||
123 | mask = mask >> 1; | |
124 | ||
9a432992 | 125 | } while (mask); |
1da177e4 LT |
126 | |
127 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
128 | eecd_reg &= ~IXGB_EECD_DI; | |
129 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
130 | return; | |
131 | } | |
132 | ||
133 | /****************************************************************************** | |
134 | * Shift data bits in from the EEPROM | |
135 | * | |
136 | * hw - Struct containing variables accessed by shared code | |
137 | *****************************************************************************/ | |
222441a6 | 138 | static u16 |
1da177e4 LT |
139 | ixgb_shift_in_bits(struct ixgb_hw *hw) |
140 | { | |
222441a6 JP |
141 | u32 eecd_reg; |
142 | u32 i; | |
143 | u16 data; | |
1da177e4 LT |
144 | |
145 | /* In order to read a register from the EEPROM, we need to shift 16 bits | |
146 | * in from the EEPROM. Bits are "shifted in" by raising the clock input to | |
147 | * the EEPROM (setting the SK bit), and then reading the value of the "DO" | |
148 | * bit. During this "shifting in" process the "DI" bit should always be | |
149 | * clear.. | |
150 | */ | |
151 | ||
152 | eecd_reg = IXGB_READ_REG(hw, EECD); | |
153 | ||
154 | eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI); | |
155 | data = 0; | |
156 | ||
1459336d | 157 | for (i = 0; i < 16; i++) { |
1da177e4 LT |
158 | data = data << 1; |
159 | ixgb_raise_clock(hw, &eecd_reg); | |
160 | ||
161 | eecd_reg = IXGB_READ_REG(hw, EECD); | |
162 | ||
163 | eecd_reg &= ~(IXGB_EECD_DI); | |
03f83041 | 164 | if (eecd_reg & IXGB_EECD_DO) |
1da177e4 LT |
165 | data |= 1; |
166 | ||
167 | ixgb_lower_clock(hw, &eecd_reg); | |
168 | } | |
169 | ||
170 | return data; | |
171 | } | |
172 | ||
173 | /****************************************************************************** | |
174 | * Prepares EEPROM for access | |
175 | * | |
176 | * hw - Struct containing variables accessed by shared code | |
177 | * | |
178 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This | |
179 | * function should be called before issuing a command to the EEPROM. | |
180 | *****************************************************************************/ | |
181 | static void | |
182 | ixgb_setup_eeprom(struct ixgb_hw *hw) | |
183 | { | |
222441a6 | 184 | u32 eecd_reg; |
1da177e4 LT |
185 | |
186 | eecd_reg = IXGB_READ_REG(hw, EECD); | |
187 | ||
188 | /* Clear SK and DI */ | |
189 | eecd_reg &= ~(IXGB_EECD_SK | IXGB_EECD_DI); | |
190 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
191 | ||
192 | /* Set CS */ | |
193 | eecd_reg |= IXGB_EECD_CS; | |
194 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
195 | return; | |
196 | } | |
197 | ||
198 | /****************************************************************************** | |
199 | * Returns EEPROM to a "standby" state | |
200 | * | |
201 | * hw - Struct containing variables accessed by shared code | |
202 | *****************************************************************************/ | |
203 | static void | |
204 | ixgb_standby_eeprom(struct ixgb_hw *hw) | |
205 | { | |
222441a6 | 206 | u32 eecd_reg; |
1da177e4 LT |
207 | |
208 | eecd_reg = IXGB_READ_REG(hw, EECD); | |
209 | ||
52035bdb | 210 | /* Deselect EEPROM */ |
1da177e4 LT |
211 | eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); |
212 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
213 | udelay(50); | |
214 | ||
215 | /* Clock high */ | |
216 | eecd_reg |= IXGB_EECD_SK; | |
217 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
218 | udelay(50); | |
219 | ||
220 | /* Select EEPROM */ | |
221 | eecd_reg |= IXGB_EECD_CS; | |
222 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
223 | udelay(50); | |
224 | ||
225 | /* Clock low */ | |
226 | eecd_reg &= ~IXGB_EECD_SK; | |
227 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
228 | udelay(50); | |
229 | return; | |
230 | } | |
231 | ||
232 | /****************************************************************************** | |
233 | * Raises then lowers the EEPROM's clock pin | |
234 | * | |
235 | * hw - Struct containing variables accessed by shared code | |
236 | *****************************************************************************/ | |
237 | static void | |
238 | ixgb_clock_eeprom(struct ixgb_hw *hw) | |
239 | { | |
222441a6 | 240 | u32 eecd_reg; |
1da177e4 LT |
241 | |
242 | eecd_reg = IXGB_READ_REG(hw, EECD); | |
243 | ||
244 | /* Rising edge of clock */ | |
245 | eecd_reg |= IXGB_EECD_SK; | |
246 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
247 | udelay(50); | |
248 | ||
249 | /* Falling edge of clock */ | |
250 | eecd_reg &= ~IXGB_EECD_SK; | |
251 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
252 | udelay(50); | |
253 | return; | |
254 | } | |
255 | ||
256 | /****************************************************************************** | |
257 | * Terminates a command by lowering the EEPROM's chip select pin | |
258 | * | |
259 | * hw - Struct containing variables accessed by shared code | |
260 | *****************************************************************************/ | |
261 | static void | |
262 | ixgb_cleanup_eeprom(struct ixgb_hw *hw) | |
263 | { | |
222441a6 | 264 | u32 eecd_reg; |
1da177e4 LT |
265 | |
266 | eecd_reg = IXGB_READ_REG(hw, EECD); | |
267 | ||
268 | eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_DI); | |
269 | ||
270 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | |
271 | ||
272 | ixgb_clock_eeprom(hw); | |
273 | return; | |
274 | } | |
275 | ||
276 | /****************************************************************************** | |
277 | * Waits for the EEPROM to finish the current command. | |
278 | * | |
279 | * hw - Struct containing variables accessed by shared code | |
280 | * | |
281 | * The command is done when the EEPROM's data out pin goes high. | |
282 | * | |
283 | * Returns: | |
446490ca JP |
284 | * true: EEPROM data pin is high before timeout. |
285 | * false: Time expired. | |
1da177e4 | 286 | *****************************************************************************/ |
446490ca | 287 | static bool |
1da177e4 LT |
288 | ixgb_wait_eeprom_command(struct ixgb_hw *hw) |
289 | { | |
222441a6 JP |
290 | u32 eecd_reg; |
291 | u32 i; | |
1da177e4 LT |
292 | |
293 | /* Toggle the CS line. This in effect tells to EEPROM to actually execute | |
294 | * the command in question. | |
295 | */ | |
296 | ixgb_standby_eeprom(hw); | |
297 | ||
52035bdb | 298 | /* Now read DO repeatedly until is high (equal to '1'). The EEPROM will |
1da177e4 LT |
299 | * signal that the command has been completed by raising the DO signal. |
300 | * If DO does not go high in 10 milliseconds, then error out. | |
301 | */ | |
1459336d | 302 | for (i = 0; i < 200; i++) { |
1da177e4 LT |
303 | eecd_reg = IXGB_READ_REG(hw, EECD); |
304 | ||
03f83041 | 305 | if (eecd_reg & IXGB_EECD_DO) |
446490ca | 306 | return (true); |
1da177e4 LT |
307 | |
308 | udelay(50); | |
309 | } | |
310 | ASSERT(0); | |
446490ca | 311 | return (false); |
1da177e4 LT |
312 | } |
313 | ||
314 | /****************************************************************************** | |
315 | * Verifies that the EEPROM has a valid checksum | |
316 | * | |
317 | * hw - Struct containing variables accessed by shared code | |
318 | * | |
319 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. | |
59c51591 | 320 | * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
1da177e4 LT |
321 | * valid. |
322 | * | |
323 | * Returns: | |
446490ca JP |
324 | * true: Checksum is valid |
325 | * false: Checksum is not valid. | |
1da177e4 | 326 | *****************************************************************************/ |
446490ca | 327 | bool |
1da177e4 LT |
328 | ixgb_validate_eeprom_checksum(struct ixgb_hw *hw) |
329 | { | |
222441a6 JP |
330 | u16 checksum = 0; |
331 | u16 i; | |
1da177e4 | 332 | |
1459336d | 333 | for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) |
1da177e4 LT |
334 | checksum += ixgb_read_eeprom(hw, i); |
335 | ||
03f83041 | 336 | if (checksum == (u16) EEPROM_SUM) |
446490ca | 337 | return (true); |
1da177e4 | 338 | else |
446490ca | 339 | return (false); |
1da177e4 LT |
340 | } |
341 | ||
342 | /****************************************************************************** | |
343 | * Calculates the EEPROM checksum and writes it to the EEPROM | |
344 | * | |
345 | * hw - Struct containing variables accessed by shared code | |
346 | * | |
347 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. | |
348 | * Writes the difference to word offset 63 of the EEPROM. | |
349 | *****************************************************************************/ | |
350 | void | |
351 | ixgb_update_eeprom_checksum(struct ixgb_hw *hw) | |
352 | { | |
222441a6 JP |
353 | u16 checksum = 0; |
354 | u16 i; | |
1da177e4 | 355 | |
1459336d | 356 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) |
1da177e4 LT |
357 | checksum += ixgb_read_eeprom(hw, i); |
358 | ||
222441a6 | 359 | checksum = (u16) EEPROM_SUM - checksum; |
1da177e4 LT |
360 | |
361 | ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum); | |
362 | return; | |
363 | } | |
364 | ||
365 | /****************************************************************************** | |
366 | * Writes a 16 bit word to a given offset in the EEPROM. | |
367 | * | |
368 | * hw - Struct containing variables accessed by shared code | |
369 | * reg - offset within the EEPROM to be written to | |
52035bdb | 370 | * data - 16 bit word to be written to the EEPROM |
1da177e4 LT |
371 | * |
372 | * If ixgb_update_eeprom_checksum is not called after this function, the | |
373 | * EEPROM will most likely contain an invalid checksum. | |
374 | * | |
375 | *****************************************************************************/ | |
376 | void | |
222441a6 | 377 | ixgb_write_eeprom(struct ixgb_hw *hw, u16 offset, u16 data) |
1da177e4 LT |
378 | { |
379 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | |
380 | ||
381 | /* Prepare the EEPROM for writing */ | |
382 | ixgb_setup_eeprom(hw); | |
383 | ||
384 | /* Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit opcode | |
385 | * plus 4-bit dummy). This puts the EEPROM into write/erase mode. | |
386 | */ | |
387 | ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5); | |
388 | ixgb_shift_out_bits(hw, 0, 4); | |
389 | ||
390 | /* Prepare the EEPROM */ | |
391 | ixgb_standby_eeprom(hw); | |
392 | ||
393 | /* Send the Write command (3-bit opcode + 6-bit addr) */ | |
394 | ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3); | |
395 | ixgb_shift_out_bits(hw, offset, 6); | |
396 | ||
397 | /* Send the data */ | |
398 | ixgb_shift_out_bits(hw, data, 16); | |
399 | ||
400 | ixgb_wait_eeprom_command(hw); | |
401 | ||
402 | /* Recover from write */ | |
403 | ixgb_standby_eeprom(hw); | |
404 | ||
405 | /* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit | |
406 | * opcode plus 4-bit dummy). This takes the EEPROM out of write/erase | |
407 | * mode. | |
408 | */ | |
409 | ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5); | |
410 | ixgb_shift_out_bits(hw, 0, 4); | |
411 | ||
412 | /* Done with writing */ | |
413 | ixgb_cleanup_eeprom(hw); | |
414 | ||
415 | /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */ | |
c676504e | 416 | ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR); |
1da177e4 LT |
417 | |
418 | return; | |
419 | } | |
420 | ||
421 | /****************************************************************************** | |
422 | * Reads a 16 bit word from the EEPROM. | |
423 | * | |
424 | * hw - Struct containing variables accessed by shared code | |
425 | * offset - offset of 16 bit word in the EEPROM to read | |
426 | * | |
427 | * Returns: | |
428 | * The 16-bit value read from the eeprom | |
429 | *****************************************************************************/ | |
222441a6 | 430 | u16 |
1da177e4 | 431 | ixgb_read_eeprom(struct ixgb_hw *hw, |
222441a6 | 432 | u16 offset) |
1da177e4 | 433 | { |
222441a6 | 434 | u16 data; |
1da177e4 LT |
435 | |
436 | /* Prepare the EEPROM for reading */ | |
437 | ixgb_setup_eeprom(hw); | |
438 | ||
439 | /* Send the READ command (opcode + addr) */ | |
440 | ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3); | |
441 | /* | |
442 | * We have a 64 word EEPROM, there are 6 address bits | |
443 | */ | |
444 | ixgb_shift_out_bits(hw, offset, 6); | |
445 | ||
446 | /* Read the data */ | |
447 | data = ixgb_shift_in_bits(hw); | |
448 | ||
449 | /* End this read operation */ | |
450 | ixgb_standby_eeprom(hw); | |
451 | ||
452 | return (data); | |
453 | } | |
454 | ||
455 | /****************************************************************************** | |
456 | * Reads eeprom and stores data in shared structure. | |
457 | * Validates eeprom checksum and eeprom signature. | |
458 | * | |
459 | * hw - Struct containing variables accessed by shared code | |
460 | * | |
461 | * Returns: | |
446490ca JP |
462 | * true: if eeprom read is successful |
463 | * false: otherwise. | |
1da177e4 | 464 | *****************************************************************************/ |
446490ca | 465 | bool |
1da177e4 LT |
466 | ixgb_get_eeprom_data(struct ixgb_hw *hw) |
467 | { | |
222441a6 JP |
468 | u16 i; |
469 | u16 checksum = 0; | |
1da177e4 LT |
470 | struct ixgb_ee_map_type *ee_map; |
471 | ||
d328bc83 | 472 | ENTER(); |
1da177e4 LT |
473 | |
474 | ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | |
475 | ||
d328bc83 | 476 | pr_debug("Reading eeprom data\n"); |
1459336d | 477 | for (i = 0; i < IXGB_EEPROM_SIZE ; i++) { |
222441a6 | 478 | u16 ee_data; |
1da177e4 LT |
479 | ee_data = ixgb_read_eeprom(hw, i); |
480 | checksum += ee_data; | |
c676504e | 481 | hw->eeprom[i] = cpu_to_le16(ee_data); |
1da177e4 LT |
482 | } |
483 | ||
222441a6 | 484 | if (checksum != (u16) EEPROM_SUM) { |
d328bc83 | 485 | pr_debug("Checksum invalid\n"); |
1da177e4 LT |
486 | /* clear the init_ctrl_reg_1 to signify that the cache is |
487 | * invalidated */ | |
c676504e | 488 | ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR); |
446490ca | 489 | return (false); |
1da177e4 LT |
490 | } |
491 | ||
c676504e AV |
492 | if ((ee_map->init_ctrl_reg_1 & cpu_to_le16(EEPROM_ICW1_SIGNATURE_MASK)) |
493 | != cpu_to_le16(EEPROM_ICW1_SIGNATURE_VALID)) { | |
d328bc83 | 494 | pr_debug("Signature invalid\n"); |
446490ca | 495 | return(false); |
1da177e4 LT |
496 | } |
497 | ||
446490ca | 498 | return(true); |
1da177e4 LT |
499 | } |
500 | ||
501 | /****************************************************************************** | |
502 | * Local function to check if the eeprom signature is good | |
503 | * If the eeprom signature is good, calls ixgb)get_eeprom_data. | |
504 | * | |
505 | * hw - Struct containing variables accessed by shared code | |
506 | * | |
507 | * Returns: | |
446490ca JP |
508 | * true: eeprom signature was good and the eeprom read was successful |
509 | * false: otherwise. | |
1da177e4 | 510 | ******************************************************************************/ |
446490ca | 511 | static bool |
1da177e4 LT |
512 | ixgb_check_and_get_eeprom_data (struct ixgb_hw* hw) |
513 | { | |
514 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | |
515 | ||
c676504e AV |
516 | if ((ee_map->init_ctrl_reg_1 & cpu_to_le16(EEPROM_ICW1_SIGNATURE_MASK)) |
517 | == cpu_to_le16(EEPROM_ICW1_SIGNATURE_VALID)) { | |
446490ca | 518 | return (true); |
1da177e4 LT |
519 | } else { |
520 | return ixgb_get_eeprom_data(hw); | |
521 | } | |
522 | } | |
523 | ||
524 | /****************************************************************************** | |
525 | * return a word from the eeprom | |
526 | * | |
527 | * hw - Struct containing variables accessed by shared code | |
528 | * index - Offset of eeprom word | |
529 | * | |
530 | * Returns: | |
531 | * Word at indexed offset in eeprom, if valid, 0 otherwise. | |
532 | ******************************************************************************/ | |
c676504e | 533 | __le16 |
222441a6 | 534 | ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index) |
1da177e4 LT |
535 | { |
536 | ||
537 | if ((index < IXGB_EEPROM_SIZE) && | |
446490ca | 538 | (ixgb_check_and_get_eeprom_data(hw) == true)) { |
1da177e4 LT |
539 | return(hw->eeprom[index]); |
540 | } | |
541 | ||
542 | return(0); | |
543 | } | |
544 | ||
545 | /****************************************************************************** | |
546 | * return the mac address from EEPROM | |
547 | * | |
548 | * hw - Struct containing variables accessed by shared code | |
549 | * mac_addr - Ethernet Address if EEPROM contents are valid, 0 otherwise | |
550 | * | |
551 | * Returns: None. | |
552 | ******************************************************************************/ | |
553 | void | |
554 | ixgb_get_ee_mac_addr(struct ixgb_hw *hw, | |
222441a6 | 555 | u8 *mac_addr) |
1da177e4 LT |
556 | { |
557 | int i; | |
558 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | |
559 | ||
d328bc83 | 560 | ENTER(); |
1da177e4 | 561 | |
446490ca | 562 | if (ixgb_check_and_get_eeprom_data(hw) == true) { |
1da177e4 LT |
563 | for (i = 0; i < IXGB_ETH_LENGTH_OF_ADDRESS; i++) { |
564 | mac_addr[i] = ee_map->mac_addr[i]; | |
1da177e4 | 565 | } |
d328bc83 | 566 | pr_debug("eeprom mac address = %pM\n", mac_addr); |
1da177e4 LT |
567 | } |
568 | } | |
569 | ||
1da177e4 LT |
570 | |
571 | /****************************************************************************** | |
572 | * return the Printed Board Assembly number from EEPROM | |
573 | * | |
574 | * hw - Struct containing variables accessed by shared code | |
575 | * | |
576 | * Returns: | |
577 | * PBA number if EEPROM contents are valid, 0 otherwise | |
578 | ******************************************************************************/ | |
222441a6 | 579 | u32 |
1da177e4 LT |
580 | ixgb_get_ee_pba_number(struct ixgb_hw *hw) |
581 | { | |
446490ca | 582 | if (ixgb_check_and_get_eeprom_data(hw) == true) |
1da177e4 LT |
583 | return (le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG]) |
584 | | (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG])<<16)); | |
585 | ||
586 | return(0); | |
587 | } | |
588 | ||
1da177e4 LT |
589 | |
590 | /****************************************************************************** | |
591 | * return the Device Id from EEPROM | |
592 | * | |
593 | * hw - Struct containing variables accessed by shared code | |
594 | * | |
595 | * Returns: | |
596 | * Device Id if EEPROM contents are valid, 0 otherwise | |
597 | ******************************************************************************/ | |
222441a6 | 598 | u16 |
1da177e4 LT |
599 | ixgb_get_ee_device_id(struct ixgb_hw *hw) |
600 | { | |
601 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | |
602 | ||
446490ca | 603 | if (ixgb_check_and_get_eeprom_data(hw) == true) |
abf481d6 | 604 | return (le16_to_cpu(ee_map->device_id)); |
1da177e4 | 605 | |
fcb01756 | 606 | return (0); |
1da177e4 LT |
607 | } |
608 |