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ipg: remove some internal comments
[net-next-2.6.git] / drivers / net / ipg.c
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1202d6ff
FR		 1/*
2 * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
3 *
4 * Copyright (C) 2003, 2007 IC Plus Corp
5 *
6 * Original Author:
7 *
8 * Craig Rich
9 * Sundance Technology, Inc.
10 * www.sundanceti.com
11 * craig_rich@sundanceti.com
12 *
13 * Current Maintainer:
14 *
15 * Sorbica Shieh.
16 * http://www.icplus.com.tw
17 * sorbica@icplus.com.tw
18 *
19 * Jesse Huang
20 * http://www.icplus.com.tw
21 * jesse@icplus.com.tw
22 */
23#include <linux/crc32.h>
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/mutex.h>
27
1dad939d 28#include <asm/div64.h>
29
1202d6ff
FR		 30#define IPG_RX_RING_BYTES (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31#define IPG_TX_RING_BYTES (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32#define IPG_RESET_MASK \
33 (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34 IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
35 IPG_AC_AUTO_INIT)
36
37#define ipg_w32(val32,reg) iowrite32((val32), ioaddr + (reg))
38#define ipg_w16(val16,reg) iowrite16((val16), ioaddr + (reg))
39#define ipg_w8(val8,reg) iowrite8((val8), ioaddr + (reg))
40
41#define ipg_r32(reg) ioread32(ioaddr + (reg))
42#define ipg_r16(reg) ioread16(ioaddr + (reg))
43#define ipg_r8(reg) ioread8(ioaddr + (reg))
44
45#define JUMBO_FRAME_4k_ONLY
46enum {
47 netdev_io_size = 128
48};
49
50#include "ipg.h"
51#define DRV_NAME "ipg"
52
53MODULE_AUTHOR("IC Plus Corp. 2003");
1662e4b7 54MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
1202d6ff
FR		 55MODULE_LICENSE("GPL");
56
96fd74b2
AB		 57//variable record -- index by leading revision/length
58//Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
59static unsigned short DefaultPhyParam[] = {
60 // 11/12/03 IP1000A v1-3 rev=0x40
61 /*--------------------------------------------------------------------------
62 (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
63 27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
64 31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7, 9, 0x0700,
65 --------------------------------------------------------------------------*/
66 // 12/17/03 IP1000A v1-4 rev=0x40
67 (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
68 0x0000,
69 30, 0x005e, 9, 0x0700,
70 // 01/09/04 IP1000A v1-5 rev=0x41
71 (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
72 0x0000,
73 30, 0x005e, 9, 0x0700,
74 0x0000
75};
76
1202d6ff
FR		 77static const char *ipg_brand_name[] = {
78 "IC PLUS IP1000 1000/100/10 based NIC",
79 "Sundance Technology ST2021 based NIC",
80 "Tamarack Microelectronics TC9020/9021 based NIC",
81 "Tamarack Microelectronics TC9020/9021 based NIC",
82 "D-Link NIC",
83 "D-Link NIC IP1000A"
84};
85
86static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
87 { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
88 { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
89 { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
90 { PCI_VDEVICE(DLINK, 0x9021), 3 },
91 { PCI_VDEVICE(DLINK, 0x4000), 4 },
92 { PCI_VDEVICE(DLINK, 0x4020), 5 },
93 { 0, }
94};
95
96MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
97
98static inline void __iomem *ipg_ioaddr(struct net_device *dev)
99{
100 struct ipg_nic_private *sp = netdev_priv(dev);
101 return sp->ioaddr;
102}
103
104#ifdef IPG_DEBUG
105static void ipg_dump_rfdlist(struct net_device *dev)
106{
107 struct ipg_nic_private *sp = netdev_priv(dev);
108 void __iomem *ioaddr = sp->ioaddr;
109 unsigned int i;
110 u32 offset;
111
112 IPG_DEBUG_MSG("_dump_rfdlist\n");
113
114 printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
115 printk(KERN_INFO "rx_dirty = %2.2x\n", sp->rx_dirty);
116 printk(KERN_INFO "RFDList start address = %16.16lx\n",
117 (unsigned long) sp->rxd_map);
118 printk(KERN_INFO "RFDListPtr register = %8.8x%8.8x\n",
119 ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
120
121 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
122 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
123 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
124 offset, (unsigned long) sp->rxd[i].next_desc);
125 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
126 printk(KERN_INFO "%2.2x %4.4x RFS = %16.16lx\n", i,
127 offset, (unsigned long) sp->rxd[i].rfs);
128 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
129 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
130 offset, (unsigned long) sp->rxd[i].frag_info);
131 }
132}
133
134static void ipg_dump_tfdlist(struct net_device *dev)
135{
136 struct ipg_nic_private *sp = netdev_priv(dev);
137 void __iomem *ioaddr = sp->ioaddr;
138 unsigned int i;
139 u32 offset;
140
141 IPG_DEBUG_MSG("_dump_tfdlist\n");
142
143 printk(KERN_INFO "tx_current = %2.2x\n", sp->tx_current);
144 printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
145 printk(KERN_INFO "TFDList start address = %16.16lx\n",
146 (unsigned long) sp->txd_map);
147 printk(KERN_INFO "TFDListPtr register = %8.8x%8.8x\n",
148 ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
149
150 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
151 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
152 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
153 offset, (unsigned long) sp->txd[i].next_desc);
154
155 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
156 printk(KERN_INFO "%2.2x %4.4x TFC = %16.16lx\n", i,
157 offset, (unsigned long) sp->txd[i].tfc);
158 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
159 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
160 offset, (unsigned long) sp->txd[i].frag_info);
161 }
162}
163#endif
164
165static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
166{
167 ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
168 ndelay(IPG_PC_PHYCTRLWAIT_NS);
169}
170
171static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
172{
173 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
174 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
175}
176
177static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
178{
179 phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
180
181 ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
182}
183
184static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
185{
186 ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
187 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
188}
189
190static u16 read_phy_bit(void __iomem * ioaddr, u8 phyctrlpolarity)
191{
192 u16 bit_data;
193
194 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
195
196 bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
197
198 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
199
200 return bit_data;
201}
202
203/*
204 * Read a register from the Physical Layer device located
205 * on the IPG NIC, using the IPG PHYCTRL register.
206 */
207static int mdio_read(struct net_device * dev, int phy_id, int phy_reg)
208{
209 void __iomem *ioaddr = ipg_ioaddr(dev);
210 /*
211 * The GMII mangement frame structure for a read is as follows:
212 *
213 * |Preamble|st|op|phyad|regad|ta| data |idle|
214 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
215 *
216 * <32 1s> = 32 consecutive logic 1 values
217 * A = bit of Physical Layer device address (MSB first)
218 * R = bit of register address (MSB first)
219 * z = High impedance state
220 * D = bit of read data (MSB first)
221 *
222 * Transmission order is 'Preamble' field first, bits transmitted
223 * left to right (first to last).
224 */
225 struct {
226 u32 field;
227 unsigned int len;
228 } p[] = {
229 { GMII_PREAMBLE, 32 }, /* Preamble */
230 { GMII_ST, 2 }, /* ST */
231 { GMII_READ, 2 }, /* OP */
232 { phy_id, 5 }, /* PHYAD */
233 { phy_reg, 5 }, /* REGAD */
234 { 0x0000, 2 }, /* TA */
235 { 0x0000, 16 }, /* DATA */
236 { 0x0000, 1 } /* IDLE */
237 };
238 unsigned int i, j;
239 u8 polarity, data;
240
241 polarity = ipg_r8(PHY_CTRL);
242 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
243
244 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
245 for (j = 0; j < 5; j++) {
246 for (i = 0; i < p[j].len; i++) {
247 /* For each variable length field, the MSB must be
248 * transmitted first. Rotate through the field bits,
249 * starting with the MSB, and move each bit into the
250 * the 1st (2^1) bit position (this is the bit position
251 * corresponding to the MgmtData bit of the PhyCtrl
252 * register for the IPG).
253 *
254 * Example: ST = 01;
255 *
256 * First write a '0' to bit 1 of the PhyCtrl
257 * register, then write a '1' to bit 1 of the
258 * PhyCtrl register.
259 *
260 * To do this, right shift the MSB of ST by the value:
261 * [field length - 1 - #ST bits already written]
262 * then left shift this result by 1.
263 */
264 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
265 data &= IPG_PC_MGMTDATA;
266 data |= polarity | IPG_PC_MGMTDIR;
267
268 ipg_drive_phy_ctl_low_high(ioaddr, data);
269 }
270 }
271
272 send_three_state(ioaddr, polarity);
273
274 read_phy_bit(ioaddr, polarity);
275
276 /*
277 * For a read cycle, the bits for the next two fields (TA and
278 * DATA) are driven by the PHY (the IPG reads these bits).
279 */
280 for (i = 0; i < p[6].len; i++) {
281 p[6].field |=
282 (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
283 }
284
285 send_three_state(ioaddr, polarity);
286 send_three_state(ioaddr, polarity);
287 send_three_state(ioaddr, polarity);
288 send_end(ioaddr, polarity);
289
290 /* Return the value of the DATA field. */
291 return p[6].field;
292}
293
294/*
295 * Write to a register from the Physical Layer device located
296 * on the IPG NIC, using the IPG PHYCTRL register.
297 */
298static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
299{
300 void __iomem *ioaddr = ipg_ioaddr(dev);
301 /*
302 * The GMII mangement frame structure for a read is as follows:
303 *
304 * |Preamble|st|op|phyad|regad|ta| data |idle|
305 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
306 *
307 * <32 1s> = 32 consecutive logic 1 values
308 * A = bit of Physical Layer device address (MSB first)
309 * R = bit of register address (MSB first)
310 * z = High impedance state
311 * D = bit of write data (MSB first)
312 *
313 * Transmission order is 'Preamble' field first, bits transmitted
314 * left to right (first to last).
315 */
316 struct {
317 u32 field;
318 unsigned int len;
319 } p[] = {
320 { GMII_PREAMBLE, 32 }, /* Preamble */
321 { GMII_ST, 2 }, /* ST */
322 { GMII_WRITE, 2 }, /* OP */
323 { phy_id, 5 }, /* PHYAD */
324 { phy_reg, 5 }, /* REGAD */
325 { 0x0002, 2 }, /* TA */
326 { val & 0xffff, 16 }, /* DATA */
327 { 0x0000, 1 } /* IDLE */
328 };
329 unsigned int i, j;
330 u8 polarity, data;
331
332 polarity = ipg_r8(PHY_CTRL);
333 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
334
335 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
336 for (j = 0; j < 7; j++) {
337 for (i = 0; i < p[j].len; i++) {
338 /* For each variable length field, the MSB must be
339 * transmitted first. Rotate through the field bits,
340 * starting with the MSB, and move each bit into the
341 * the 1st (2^1) bit position (this is the bit position
342 * corresponding to the MgmtData bit of the PhyCtrl
343 * register for the IPG).
344 *
345 * Example: ST = 01;
346 *
347 * First write a '0' to bit 1 of the PhyCtrl
348 * register, then write a '1' to bit 1 of the
349 * PhyCtrl register.
350 *
351 * To do this, right shift the MSB of ST by the value:
352 * [field length - 1 - #ST bits already written]
353 * then left shift this result by 1.
354 */
355 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
356 data &= IPG_PC_MGMTDATA;
357 data |= polarity | IPG_PC_MGMTDIR;
358
359 ipg_drive_phy_ctl_low_high(ioaddr, data);
360 }
361 }
362
363 /* The last cycle is a tri-state, so read from the PHY. */
364 for (j = 7; j < 8; j++) {
365 for (i = 0; i < p[j].len; i++) {
366 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
367
368 p[j].field |= ((ipg_r8(PHY_CTRL) &
369 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
370
371 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
372 }
373 }
374}
375
1202d6ff
FR		 376static void ipg_set_led_mode(struct net_device *dev)
377{
378 struct ipg_nic_private *sp = netdev_priv(dev);
379 void __iomem *ioaddr = sp->ioaddr;
380 u32 mode;
381
382 mode = ipg_r32(ASIC_CTRL);
383 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
384
385 if ((sp->LED_Mode & 0x03) > 1)
386 mode |= IPG_AC_LED_MODE_BIT_1; /* Write Asic Control Bit 29 */
387
388 if ((sp->LED_Mode & 0x01) == 1)
389 mode |= IPG_AC_LED_MODE; /* Write Asic Control Bit 14 */
390
391 if ((sp->LED_Mode & 0x08) == 8)
392 mode |= IPG_AC_LED_SPEED; /* Write Asic Control Bit 27 */
393
394 ipg_w32(mode, ASIC_CTRL);
395}
396
1202d6ff
FR		 397static void ipg_set_phy_set(struct net_device *dev)
398{
399 struct ipg_nic_private *sp = netdev_priv(dev);
400 void __iomem *ioaddr = sp->ioaddr;
401 int physet;
402
403 physet = ipg_r8(PHY_SET);
404 physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
405 physet |= ((sp->LED_Mode & 0x70) >> 4);
406 ipg_w8(physet, PHY_SET);
407}
408
409static int ipg_reset(struct net_device *dev, u32 resetflags)
410{
411 /* Assert functional resets via the IPG AsicCtrl
412 * register as specified by the 'resetflags' input
413 * parameter.
414 */
dea4a87c 415 void __iomem *ioaddr = ipg_ioaddr(dev);
1202d6ff
FR		 416 unsigned int timeout_count = 0;
417
418 IPG_DEBUG_MSG("_reset\n");
419
420 ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
421
422 /* Delay added to account for problem with 10Mbps reset. */
423 mdelay(IPG_AC_RESETWAIT);
424
425 while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
426 mdelay(IPG_AC_RESETWAIT);
427 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
428 return -ETIME;
429 }
dea4a87c 430 /* Set LED Mode in Asic Control */
1202d6ff
FR		 431 ipg_set_led_mode(dev);
432
dea4a87c 433 /* Set PHYSet Register Value */
1202d6ff
FR		 434 ipg_set_phy_set(dev);
435 return 0;
436}
437
438/* Find the GMII PHY address. */
439static int ipg_find_phyaddr(struct net_device *dev)
440{
441 unsigned int phyaddr, i;
442
443 for (i = 0; i < 32; i++) {
444 u32 status;
445
446 /* Search for the correct PHY address among 32 possible. */
447 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
448
449 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
450 GMII_PHY_ID1
451 */
452
453 status = mdio_read(dev, phyaddr, MII_BMSR);
454
455 if ((status != 0xFFFF) && (status != 0))
456 return phyaddr;
457 }
458
459 return 0x1f;
460}
461
462/*
463 * Configure IPG based on result of IEEE 802.3 PHY
464 * auto-negotiation.
465 */
466static int ipg_config_autoneg(struct net_device *dev)
467{
468 struct ipg_nic_private *sp = netdev_priv(dev);
469 void __iomem *ioaddr = sp->ioaddr;
470 unsigned int txflowcontrol;
471 unsigned int rxflowcontrol;
472 unsigned int fullduplex;
473 unsigned int gig;
474 u32 mac_ctrl_val;
475 u32 asicctrl;
476 u8 phyctrl;
477
478 IPG_DEBUG_MSG("_config_autoneg\n");
479
480 asicctrl = ipg_r32(ASIC_CTRL);
481 phyctrl = ipg_r8(PHY_CTRL);
482 mac_ctrl_val = ipg_r32(MAC_CTRL);
483
484 /* Set flags for use in resolving auto-negotation, assuming
485 * non-1000Mbps, half duplex, no flow control.
486 */
487 fullduplex = 0;
488 txflowcontrol = 0;
489 rxflowcontrol = 0;
490 gig = 0;
491
492 /* To accomodate a problem in 10Mbps operation,
493 * set a global flag if PHY running in 10Mbps mode.
494 */
495 sp->tenmbpsmode = 0;
496
497 printk(KERN_INFO "%s: Link speed = ", dev->name);
498
499 /* Determine actual speed of operation. */
500 switch (phyctrl & IPG_PC_LINK_SPEED) {
501 case IPG_PC_LINK_SPEED_10MBPS:
502 printk("10Mbps.\n");
503 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
504 dev->name);
505 sp->tenmbpsmode = 1;
506 break;
507 case IPG_PC_LINK_SPEED_100MBPS:
508 printk("100Mbps.\n");
509 break;
510 case IPG_PC_LINK_SPEED_1000MBPS:
511 printk("1000Mbps.\n");
512 gig = 1;
513 break;
514 default:
515 printk("undefined!\n");
516 return 0;
517 }
518
519 if (phyctrl & IPG_PC_DUPLEX_STATUS) {
520 fullduplex = 1;
521 txflowcontrol = 1;
522 rxflowcontrol = 1;
523 }
524
525 /* Configure full duplex, and flow control. */
526 if (fullduplex == 1) {
527 /* Configure IPG for full duplex operation. */
528 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
529
530 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
531
532 if (txflowcontrol == 1) {
533 printk("TX flow control");
534 mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
535 } else {
536 printk("no TX flow control");
537 mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
538 }
539
540 if (rxflowcontrol == 1) {
541 printk(", RX flow control.");
542 mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
543 } else {
544 printk(", no RX flow control.");
545 mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
546 }
547
548 printk("\n");
549 } else {
550 /* Configure IPG for half duplex operation. */
551 printk(KERN_INFO "%s: setting half duplex, "
552 "no TX flow control, no RX flow control.\n", dev->name);
553
554 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
555 ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
556 ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
557 }
558 ipg_w32(mac_ctrl_val, MAC_CTRL);
559 return 0;
560}
561
562/* Determine and configure multicast operation and set
563 * receive mode for IPG.
564 */
565static void ipg_nic_set_multicast_list(struct net_device *dev)
566{
567 void __iomem *ioaddr = ipg_ioaddr(dev);
568 struct dev_mc_list *mc_list_ptr;
569 unsigned int hashindex;
570 u32 hashtable[2];
571 u8 receivemode;
572
573 IPG_DEBUG_MSG("_nic_set_multicast_list\n");
574
575 receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
576
577 if (dev->flags & IFF_PROMISC) {
578 /* NIC to be configured in promiscuous mode. */
579 receivemode = IPG_RM_RECEIVEALLFRAMES;
580 } else if ((dev->flags & IFF_ALLMULTI) ||
581 (dev->flags & IFF_MULTICAST &
582 (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
583 /* NIC to be configured to receive all multicast
584 * frames. */
585 receivemode |= IPG_RM_RECEIVEMULTICAST;
586 } else if (dev->flags & IFF_MULTICAST & (dev->mc_count > 0)) {
587 /* NIC to be configured to receive selected
588 * multicast addresses. */
589 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
590 }
591
592 /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
593 * The IPG applies a cyclic-redundancy-check (the same CRC
594 * used to calculate the frame data FCS) to the destination
595 * address all incoming multicast frames whose destination
596 * address has the multicast bit set. The least significant
597 * 6 bits of the CRC result are used as an addressing index
598 * into the hash table. If the value of the bit addressed by
599 * this index is a 1, the frame is passed to the host system.
600 */
601
602 /* Clear hashtable. */
603 hashtable[0] = 0x00000000;
604 hashtable[1] = 0x00000000;
605
606 /* Cycle through all multicast addresses to filter. */
607 for (mc_list_ptr = dev->mc_list;
608 mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
609 /* Calculate CRC result for each multicast address. */
610 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
611 ETH_ALEN);
612
613 /* Use only the least significant 6 bits. */
614 hashindex = hashindex & 0x3F;
615
616 /* Within "hashtable", set bit number "hashindex"
617 * to a logic 1.
618 */
619 set_bit(hashindex, (void *)hashtable);
620 }
621
622 /* Write the value of the hashtable, to the 4, 16 bit
623 * HASHTABLE IPG registers.
624 */
625 ipg_w32(hashtable[0], HASHTABLE_0);
626 ipg_w32(hashtable[1], HASHTABLE_1);
627
628 ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
629
630 IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
631}
632
633static int ipg_io_config(struct net_device *dev)
634{
635 void __iomem *ioaddr = ipg_ioaddr(dev);
636 u32 origmacctrl;
637 u32 restoremacctrl;
638
639 IPG_DEBUG_MSG("_io_config\n");
640
641 origmacctrl = ipg_r32(MAC_CTRL);
642
643 restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
644
645 /* Based on compilation option, determine if FCS is to be
646 * stripped on receive frames by IPG.
647 */
648 if (!IPG_STRIP_FCS_ON_RX)
649 restoremacctrl |= IPG_MC_RCV_FCS;
650
651 /* Determine if transmitter and/or receiver are
652 * enabled so we may restore MACCTRL correctly.
653 */
654 if (origmacctrl & IPG_MC_TX_ENABLED)
655 restoremacctrl |= IPG_MC_TX_ENABLE;
656
657 if (origmacctrl & IPG_MC_RX_ENABLED)
658 restoremacctrl |= IPG_MC_RX_ENABLE;
659
660 /* Transmitter and receiver must be disabled before setting
661 * IFSSelect.
662 */
663 ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
664 IPG_MC_RSVD_MASK, MAC_CTRL);
665
666 /* Now that transmitter and receiver are disabled, write
667 * to IFSSelect.
668 */
669 ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
670
671 /* Set RECEIVEMODE register. */
672 ipg_nic_set_multicast_list(dev);
673
674 ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
675
676 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE, RX_DMA_POLL_PERIOD);
677 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
678 ipg_w8(IPG_RXDMABURSTTHRESH_VALUE, RX_DMA_BURST_THRESH);
679 ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE, TX_DMA_POLL_PERIOD);
680 ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
681 ipg_w8(IPG_TXDMABURSTTHRESH_VALUE, TX_DMA_BURST_THRESH);
682 ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
683 IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
684 IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
685 IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
686 ipg_w16(IPG_FLOWONTHRESH_VALUE, FLOW_ON_THRESH);
687 ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
688
689 /* IPG multi-frag frame bug workaround.
690 * Per silicon revision B3 eratta.
691 */
692 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
693
694 /* IPG TX poll now bug workaround.
695 * Per silicon revision B3 eratta.
696 */
697 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
698
699 /* IPG RX poll now bug workaround.
700 * Per silicon revision B3 eratta.
701 */
702 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
703
704 /* Now restore MACCTRL to original setting. */
705 ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
706
707 /* Disable unused RMON statistics. */
708 ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
709
710 /* Disable unused MIB statistics. */
711 ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
712 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
713 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
714 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
715 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
716 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
717
718 return 0;
719}
720
721/*
722 * Create a receive buffer within system memory and update
723 * NIC private structure appropriately.
724 */
725static int ipg_get_rxbuff(struct net_device *dev, int entry)
726{
727 struct ipg_nic_private *sp = netdev_priv(dev);
728 struct ipg_rx *rxfd = sp->rxd + entry;
729 struct sk_buff *skb;
730 u64 rxfragsize;
731
732 IPG_DEBUG_MSG("_get_rxbuff\n");
733
734 skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
735 if (!skb) {
736 sp->RxBuff[entry] = NULL;
737 return -ENOMEM;
738 }
739
740 /* Adjust the data start location within the buffer to
741 * align IP address field to a 16 byte boundary.
742 */
743 skb_reserve(skb, NET_IP_ALIGN);
744
745 /* Associate the receive buffer with the IPG NIC. */
746 skb->dev = dev;
747
748 /* Save the address of the sk_buff structure. */
749 sp->RxBuff[entry] = skb;
750
751 rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
752 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
753
754 /* Set the RFD fragment length. */
755 rxfragsize = IPG_RXFRAG_SIZE;
756 rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
757
758 return 0;
759}
760
761static int init_rfdlist(struct net_device *dev)
762{
763 struct ipg_nic_private *sp = netdev_priv(dev);
764 void __iomem *ioaddr = sp->ioaddr;
765 unsigned int i;
766
767 IPG_DEBUG_MSG("_init_rfdlist\n");
768
769 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
770 struct ipg_rx *rxfd = sp->rxd + i;
771
772 if (sp->RxBuff[i]) {
773 pci_unmap_single(sp->pdev,
325a8071 774 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff 775 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
85d68a58 776 dev_kfree_skb_irq(sp->RxBuff[i]);
1202d6ff
FR		 777 sp->RxBuff[i] = NULL;
778 }
779
780 /* Clear out the RFS field. */
781 rxfd->rfs = 0x0000000000000000;
782
783 if (ipg_get_rxbuff(dev, i) < 0) {
784 /*
785 * A receive buffer was not ready, break the
786 * RFD list here.
787 */
788 IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
789
790 /* Just in case we cannot allocate a single RFD.
791 * Should not occur.
792 */
793 if (i == 0) {
794 printk(KERN_ERR "%s: No memory available"
795 " for RFD list.\n", dev->name);
796 return -ENOMEM;
797 }
798 }
799
800 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
801 sizeof(struct ipg_rx)*(i + 1));
802 }
803 sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
804
805 sp->rx_current = 0;
806 sp->rx_dirty = 0;
807
808 /* Write the location of the RFDList to the IPG. */
809 ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
810 ipg_w32(0x00000000, RFD_LIST_PTR_1);
811
812 return 0;
813}
814
815static void init_tfdlist(struct net_device *dev)
816{
817 struct ipg_nic_private *sp = netdev_priv(dev);
818 void __iomem *ioaddr = sp->ioaddr;
819 unsigned int i;
820
821 IPG_DEBUG_MSG("_init_tfdlist\n");
822
823 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
824 struct ipg_tx *txfd = sp->txd + i;
825
826 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
827
828 if (sp->TxBuff[i]) {
85d68a58 829 dev_kfree_skb_irq(sp->TxBuff[i]);
1202d6ff
FR		 830 sp->TxBuff[i] = NULL;
831 }
832
833 txfd->next_desc = cpu_to_le64(sp->txd_map +
834 sizeof(struct ipg_tx)*(i + 1));
835 }
836 sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
837
838 sp->tx_current = 0;
839 sp->tx_dirty = 0;
840
841 /* Write the location of the TFDList to the IPG. */
842 IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
843 (u32) sp->txd_map);
844 ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
845 ipg_w32(0x00000000, TFD_LIST_PTR_1);
846
847 sp->ResetCurrentTFD = 1;
848}
849
850/*
851 * Free all transmit buffers which have already been transfered
852 * via DMA to the IPG.
853 */
854static void ipg_nic_txfree(struct net_device *dev)
855{
856 struct ipg_nic_private *sp = netdev_priv(dev);
0da1b995 857 unsigned int released, pending, dirty;
1dad939d 858
1202d6ff
FR		 859 IPG_DEBUG_MSG("_nic_txfree\n");
860
861 pending = sp->tx_current - sp->tx_dirty;
0da1b995 862 dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
1202d6ff
FR		 863
864 for (released = 0; released < pending; released++) {
1202d6ff
FR		 865 struct sk_buff *skb = sp->TxBuff[dirty];
866 struct ipg_tx *txfd = sp->txd + dirty;
867
868 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
869
870 /* Look at each TFD's TFC field beginning
871 * at the last freed TFD up to the current TFD.
872 * If the TFDDone bit is set, free the associated
873 * buffer.
874 */
0da1b995
FR		 875 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
876 break;
1202d6ff
FR		 877
878 /* Free the transmit buffer. */
879 if (skb) {
880 pci_unmap_single(sp->pdev,
325a8071 881 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1202d6ff
FR		 882 skb->len, PCI_DMA_TODEVICE);
883
85d68a58 884 dev_kfree_skb_irq(skb);
1202d6ff
FR		 885
886 sp->TxBuff[dirty] = NULL;
887 }
0da1b995 888 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
1202d6ff
FR		 889 }
890
891 sp->tx_dirty += released;
892
893 if (netif_queue_stopped(dev) &&
894 (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
895 netif_wake_queue(dev);
896 }
897}
898
899static void ipg_tx_timeout(struct net_device *dev)
900{
901 struct ipg_nic_private *sp = netdev_priv(dev);
902 void __iomem *ioaddr = sp->ioaddr;
903
904 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
905 IPG_AC_FIFO);
906
907 spin_lock_irq(&sp->lock);
908
909 /* Re-configure after DMA reset. */
910 if (ipg_io_config(dev) < 0) {
911 printk(KERN_INFO "%s: Error during re-configuration.\n",
912 dev->name);
913 }
914
915 init_tfdlist(dev);
916
917 spin_unlock_irq(&sp->lock);
918
919 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
920 MAC_CTRL);
921}
922
923/*
924 * For TxComplete interrupts, free all transmit
925 * buffers which have already been transfered via DMA
926 * to the IPG.
927 */
928static void ipg_nic_txcleanup(struct net_device *dev)
929{
930 struct ipg_nic_private *sp = netdev_priv(dev);
931 void __iomem *ioaddr = sp->ioaddr;
932 unsigned int i;
933
934 IPG_DEBUG_MSG("_nic_txcleanup\n");
935
936 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
937 /* Reading the TXSTATUS register clears the
938 * TX_COMPLETE interrupt.
939 */
940 u32 txstatusdword = ipg_r32(TX_STATUS);
941
942 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
943
944 /* Check for Transmit errors. Error bits only valid if
945 * TX_COMPLETE bit in the TXSTATUS register is a 1.
946 */
947 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
948 break;
949
950 /* If in 10Mbps mode, indicate transmit is ready. */
951 if (sp->tenmbpsmode) {
952 netif_wake_queue(dev);
953 }
954
955 /* Transmit error, increment stat counters. */
956 if (txstatusdword & IPG_TS_TX_ERROR) {
957 IPG_DEBUG_MSG("Transmit error.\n");
958 sp->stats.tx_errors++;
959 }
960
961 /* Late collision, re-enable transmitter. */
962 if (txstatusdword & IPG_TS_LATE_COLLISION) {
963 IPG_DEBUG_MSG("Late collision on transmit.\n");
964 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
965 IPG_MC_RSVD_MASK, MAC_CTRL);
966 }
967
968 /* Maximum collisions, re-enable transmitter. */
969 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
970 IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
971 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
972 IPG_MC_RSVD_MASK, MAC_CTRL);
973 }
974
975 /* Transmit underrun, reset and re-enable
976 * transmitter.
977 */
978 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
979 IPG_DEBUG_MSG("Transmitter underrun.\n");
980 sp->stats.tx_fifo_errors++;
981 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
982 IPG_AC_NETWORK | IPG_AC_FIFO);
983
984 /* Re-configure after DMA reset. */
985 if (ipg_io_config(dev) < 0) {
986 printk(KERN_INFO
987 "%s: Error during re-configuration.\n",
988 dev->name);
989 }
990 init_tfdlist(dev);
991
992 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
993 IPG_MC_RSVD_MASK, MAC_CTRL);
994 }
995 }
996
997 ipg_nic_txfree(dev);
998}
999
1000/* Provides statistical information about the IPG NIC. */
96fd74b2 1001static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1202d6ff
FR		 1002{
1003 struct ipg_nic_private *sp = netdev_priv(dev);
1004 void __iomem *ioaddr = sp->ioaddr;
1005 u16 temp1;
1006 u16 temp2;
1007
1008 IPG_DEBUG_MSG("_nic_get_stats\n");
1009
1010 /* Check to see if the NIC has been initialized via nic_open,
1011 * before trying to read statistic registers.
1012 */
1013 if (!test_bit(__LINK_STATE_START, &dev->state))
1014 return &sp->stats;
1015
1016 sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1017 sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1018 sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1019 sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1020 temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1021 sp->stats.rx_errors += temp1;
1022 sp->stats.rx_missed_errors += temp1;
1023 temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1024 ipg_r32(IPG_LATECOLLISIONS);
1025 temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1026 sp->stats.collisions += temp1;
1027 sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1028 sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1029 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1030 sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1031
1032 /* detailed tx_errors */
1033 sp->stats.tx_carrier_errors += temp2;
1034
1035 /* detailed rx_errors */
1036 sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1037 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1038 sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1039
1040 /* Unutilized IPG statistic registers. */
1041 ipg_r32(IPG_MCSTFRAMESRCVDOK);
1042
1043 return &sp->stats;
1044}
1045
1046/* Restore used receive buffers. */
1047static int ipg_nic_rxrestore(struct net_device *dev)
1048{
1049 struct ipg_nic_private *sp = netdev_priv(dev);
1050 const unsigned int curr = sp->rx_current;
1051 unsigned int dirty = sp->rx_dirty;
1052
1053 IPG_DEBUG_MSG("_nic_rxrestore\n");
1054
1055 for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1056 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1057
1058 /* rx_copybreak may poke hole here and there. */
1059 if (sp->RxBuff[entry])
1060 continue;
1061
1062 /* Generate a new receive buffer to replace the
1063 * current buffer (which will be released by the
1064 * Linux system).
1065 */
1066 if (ipg_get_rxbuff(dev, entry) < 0) {
1067 IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1068
1069 break;
1070 }
1071
1072 /* Reset the RFS field. */
1073 sp->rxd[entry].rfs = 0x0000000000000000;
1074 }
1075 sp->rx_dirty = dirty;
1076
1077 return 0;
1078}
1079
1080#ifdef JUMBO_FRAME
1081
1082/* use jumboindex and jumbosize to control jumbo frame status
1083 initial status is jumboindex=-1 and jumbosize=0
1084 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1085 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1086 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1087 previous receiving and need to continue dumping the current one
1088*/
1089enum {
1090 NormalPacket,
1091 ErrorPacket
1092};
1093
1094enum {
1095 Frame_NoStart_NoEnd = 0,
1096 Frame_WithStart = 1,
1097 Frame_WithEnd = 10,
1098 Frame_WithStart_WithEnd = 11
1099};
1100
1101inline void ipg_nic_rx_free_skb(struct net_device *dev)
1102{
1103 struct ipg_nic_private *sp = netdev_priv(dev);
1104 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1105
1106 if (sp->RxBuff[entry]) {
1107 struct ipg_rx *rxfd = sp->rxd + entry;
1108
1109 pci_unmap_single(sp->pdev,
1110 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1111 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
85d68a58 1112 dev_kfree_skb_irq(sp->RxBuff[entry]);
1202d6ff
FR		 1113 sp->RxBuff[entry] = NULL;
1114 }
1115}
1116
1117inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1118{
1119 struct ipg_nic_private *sp = netdev_priv(dev);
1120 struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1121 int type = Frame_NoStart_NoEnd;
1122
1123 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1124 type += Frame_WithStart;
1125 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1126 type += Frame_WithEnd;
1127 return type;
1128}
1129
1130inline int ipg_nic_rx_check_error(struct net_device *dev)
1131{
1132 struct ipg_nic_private *sp = netdev_priv(dev);
1133 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1134 struct ipg_rx *rxfd = sp->rxd + entry;
1135
1136 if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1137 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1138 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1139 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1140 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1141 (unsigned long) rxfd->rfs);
1142
1143 /* Increment general receive error statistic. */
1144 sp->stats.rx_errors++;
1145
1146 /* Increment detailed receive error statistics. */
1147 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1148 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1149
1150 sp->stats.rx_fifo_errors++;
1151 }
1152
1153 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1154 IPG_DEBUG_MSG("RX runt occured.\n");
1155 sp->stats.rx_length_errors++;
1156 }
1157
1158 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1159 * error count handled by a IPG statistic register.
1160 */
1161
1162 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1163 IPG_DEBUG_MSG("RX alignment error occured.\n");
1164 sp->stats.rx_frame_errors++;
1165 }
1166
1167 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1168 * handled by a IPG statistic register.
1169 */
1170
1171 /* Free the memory associated with the RX
1172 * buffer since it is erroneous and we will
1173 * not pass it to higher layer processes.
1174 */
1175 if (sp->RxBuff[entry]) {
1176 pci_unmap_single(sp->pdev,
1177 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1178 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1179
85d68a58 1180 dev_kfree_skb_irq(sp->RxBuff[entry]);
1202d6ff
FR		 1181 sp->RxBuff[entry] = NULL;
1182 }
1183 return ErrorPacket;
1184 }
1185 return NormalPacket;
1186}
1187
1188static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1189 struct ipg_nic_private *sp,
1190 struct ipg_rx *rxfd, unsigned entry)
1191{
1192 struct SJumbo *jumbo = &sp->Jumbo;
1193 struct sk_buff *skb;
1194 int framelen;
1195
1196 if (jumbo->FoundStart) {
85d68a58 1197 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1198 jumbo->FoundStart = 0;
1199 jumbo->CurrentSize = 0;
1200 jumbo->skb = NULL;
1201 }
1202
1203 // 1: found error, 0 no error
1204 if (ipg_nic_rx_check_error(dev) != NormalPacket)
1205 return;
1206
1207 skb = sp->RxBuff[entry];
1208 if (!skb)
1209 return;
1210
1211 // accept this frame and send to upper layer
1212 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1213 if (framelen > IPG_RXFRAG_SIZE)
1214 framelen = IPG_RXFRAG_SIZE;
1215
1216 skb_put(skb, framelen);
1217 skb->protocol = eth_type_trans(skb, dev);
1218 skb->ip_summed = CHECKSUM_NONE;
1219 netif_rx(skb);
1220 dev->last_rx = jiffies;
1221 sp->RxBuff[entry] = NULL;
1222}
1223
1224static void ipg_nic_rx_with_start(struct net_device *dev,
1225 struct ipg_nic_private *sp,
1226 struct ipg_rx *rxfd, unsigned entry)
1227{
1228 struct SJumbo *jumbo = &sp->Jumbo;
1229 struct pci_dev *pdev = sp->pdev;
1230 struct sk_buff *skb;
1231
1232 // 1: found error, 0 no error
1233 if (ipg_nic_rx_check_error(dev) != NormalPacket)
1234 return;
1235
1236 // accept this frame and send to upper layer
1237 skb = sp->RxBuff[entry];
1238 if (!skb)
1239 return;
1240
1241 if (jumbo->FoundStart)
85d68a58 1242 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1243
1244 pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1245 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1246
1247 skb_put(skb, IPG_RXFRAG_SIZE);
1248
1249 jumbo->FoundStart = 1;
1250 jumbo->CurrentSize = IPG_RXFRAG_SIZE;
1251 jumbo->skb = skb;
1252
1253 sp->RxBuff[entry] = NULL;
1254 dev->last_rx = jiffies;
1255}
1256
1257static void ipg_nic_rx_with_end(struct net_device *dev,
1258 struct ipg_nic_private *sp,
1259 struct ipg_rx *rxfd, unsigned entry)
1260{
1261 struct SJumbo *jumbo = &sp->Jumbo;
1262
1263 //1: found error, 0 no error
1264 if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1265 struct sk_buff *skb = sp->RxBuff[entry];
1266
1267 if (!skb)
1268 return;
1269
1270 if (jumbo->FoundStart) {
1271 int framelen, endframelen;
1272
1273 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1274
1275 endframeLen = framelen - jumbo->CurrentSize;
1276 /*
1277 if (framelen > IPG_RXFRAG_SIZE)
1278 framelen=IPG_RXFRAG_SIZE;
1279 */
1280 if (framelen > IPG_RXSUPPORT_SIZE)
85d68a58 1281 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1282 else {
1283 memcpy(skb_put(jumbo->skb, endframeLen),
1284 skb->data, endframeLen);
1285
1286 jumbo->skb->protocol =
1287 eth_type_trans(jumbo->skb, dev);
1288
1289 jumbo->skb->ip_summed = CHECKSUM_NONE;
1290 netif_rx(jumbo->skb);
1291 }
1292 }
1293
1294 dev->last_rx = jiffies;
1295 jumbo->FoundStart = 0;
1296 jumbo->CurrentSize = 0;
1297 jumbo->skb = NULL;
1298
1299 ipg_nic_rx_free_skb(dev);
1300 } else {
85d68a58 1301 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1302 jumbo->FoundStart = 0;
1303 jumbo->CurrentSize = 0;
1304 jumbo->skb = NULL;
1305 }
1306}
1307
1308static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1309 struct ipg_nic_private *sp,
1310 struct ipg_rx *rxfd, unsigned entry)
1311{
1312 struct SJumbo *jumbo = &sp->Jumbo;
1313
1314 //1: found error, 0 no error
1315 if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1316 struct sk_buff *skb = sp->RxBuff[entry];
1317
1318 if (skb) {
1319 if (jumbo->FoundStart) {
1320 jumbo->CurrentSize += IPG_RXFRAG_SIZE;
1321 if (jumbo->CurrentSize <= IPG_RXSUPPORT_SIZE) {
1322 memcpy(skb_put(jumbo->skb,
1323 IPG_RXFRAG_SIZE),
1324 skb->data, IPG_RXFRAG_SIZE);
1325 }
1326 }
1327 dev->last_rx = jiffies;
1328 ipg_nic_rx_free_skb(dev);
1329 }
1330 } else {
85d68a58 1331 dev_kfree_skb_irq(jumbo->skb);
1202d6ff
FR		 1332 jumbo->FoundStart = 0;
1333 jumbo->CurrentSize = 0;
1334 jumbo->skb = NULL;
1335 }
1336}
1337
1338static int ipg_nic_rx(struct net_device *dev)
1339{
1340 struct ipg_nic_private *sp = netdev_priv(dev);
1341 unsigned int curr = sp->rx_current;
1342 void __iomem *ioaddr = sp->ioaddr;
1343 unsigned int i;
1344
1345 IPG_DEBUG_MSG("_nic_rx\n");
1346
1347 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1348 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1349 struct ipg_rx *rxfd = sp->rxd + entry;
1350
1351 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1352 break;
1353
1354 switch (ipg_nic_rx_check_frame_type(dev)) {
1355 case Frame_WithStart_WithEnd:
1356 ipg_nic_rx_with_start_and_end(dev, tp, rxfd, entry);
1357 break;
1358 case Frame_WithStart:
1359 ipg_nic_rx_with_start(dev, tp, rxfd, entry);
1360 break;
1361 case Frame_WithEnd:
1362 ipg_nic_rx_with_end(dev, tp, rxfd, entry);
1363 break;
1364 case Frame_NoStart_NoEnd:
1365 ipg_nic_rx_no_start_no_end(dev, tp, rxfd, entry);
1366 break;
1367 }
1368 }
1369
1370 sp->rx_current = curr;
1371
1372 if (i == IPG_MAXRFDPROCESS_COUNT) {
1373 /* There are more RFDs to process, however the
1374 * allocated amount of RFD processing time has
1375 * expired. Assert Interrupt Requested to make
1376 * sure we come back to process the remaining RFDs.
1377 */
1378 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1379 }
1380
1381 ipg_nic_rxrestore(dev);
1382
1383 return 0;
1384}
1385
1386#else
1387static int ipg_nic_rx(struct net_device *dev)
1388{
1389 /* Transfer received Ethernet frames to higher network layers. */
1390 struct ipg_nic_private *sp = netdev_priv(dev);
1391 unsigned int curr = sp->rx_current;
1392 void __iomem *ioaddr = sp->ioaddr;
1393 struct ipg_rx *rxfd;
1394 unsigned int i;
1395
1396 IPG_DEBUG_MSG("_nic_rx\n");
1397
1398#define __RFS_MASK \
1399 cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1400
1401 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1402 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1403 struct sk_buff *skb = sp->RxBuff[entry];
1404 unsigned int framelen;
1405
1406 rxfd = sp->rxd + entry;
1407
1408 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1409 break;
1410
1411 /* Get received frame length. */
1412 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1413
1414 /* Check for jumbo frame arrival with too small
1415 * RXFRAG_SIZE.
1416 */
1417 if (framelen > IPG_RXFRAG_SIZE) {
1418 IPG_DEBUG_MSG
1419 ("RFS FrameLen > allocated fragment size.\n");
1420
1421 framelen = IPG_RXFRAG_SIZE;
1422 }
1423
325a8071 1424 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1202d6ff
FR		 1425 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1426 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
325a8071 1427 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1202d6ff
FR		 1428
1429 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1430 (unsigned long int) rxfd->rfs);
1431
1432 /* Increment general receive error statistic. */
1433 sp->stats.rx_errors++;
1434
1435 /* Increment detailed receive error statistics. */
325a8071 1436 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1202d6ff
FR		 1437 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1438 sp->stats.rx_fifo_errors++;
1439 }
1440
325a8071 1441 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1202d6ff
FR		 1442 IPG_DEBUG_MSG("RX runt occured.\n");
1443 sp->stats.rx_length_errors++;
1444 }
1445
325a8071 1446 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1202d6ff
FR		 1447 /* Do nothing, error count handled by a IPG
1448 * statistic register.
1449 */
1450
325a8071 1451 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1202d6ff
FR		 1452 IPG_DEBUG_MSG("RX alignment error occured.\n");
1453 sp->stats.rx_frame_errors++;
1454 }
1455
325a8071 1456 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1202d6ff
FR		 1457 /* Do nothing, error count handled by a IPG
1458 * statistic register.
1459 */
1460
1461 /* Free the memory associated with the RX
1462 * buffer since it is erroneous and we will
1463 * not pass it to higher layer processes.
1464 */
1465 if (skb) {
325a8071 1466 __le64 info = rxfd->frag_info;
1202d6ff
FR		 1467
1468 pci_unmap_single(sp->pdev,
325a8071 1469 le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1202d6ff
FR		 1470 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1471
85d68a58 1472 dev_kfree_skb_irq(skb);
1202d6ff
FR		 1473 }
1474 } else {
1475
1476 /* Adjust the new buffer length to accomodate the size
1477 * of the received frame.
1478 */
1479 skb_put(skb, framelen);
1480
1481 /* Set the buffer's protocol field to Ethernet. */
1482 skb->protocol = eth_type_trans(skb, dev);
1483
6d3b2cb9
PE		 1484 /* The IPG encountered an error with (or
1485 * there were no) IP/TCP/UDP checksums.
1486 * This may or may not indicate an invalid
1487 * IP/TCP/UDP frame was received. Let the
1488 * upper layer decide.
1202d6ff 1489 */
6d3b2cb9 1490 skb->ip_summed = CHECKSUM_NONE;
1202d6ff
FR		 1491
1492 /* Hand off frame for higher layer processing.
1493 * The function netif_rx() releases the sk_buff
1494 * when processing completes.
1495 */
1496 netif_rx(skb);
1497
1498 /* Record frame receive time (jiffies = Linux
1499 * kernel current time stamp).
1500 */
1501 dev->last_rx = jiffies;
1502 }
1503
1504 /* Assure RX buffer is not reused by IPG. */
1505 sp->RxBuff[entry] = NULL;
1506 }
1507
1508 /*
1509 * If there are more RFDs to proces and the allocated amount of RFD
1510 * processing time has expired, assert Interrupt Requested to make
1511 * sure we come back to process the remaining RFDs.
1512 */
1513 if (i == IPG_MAXRFDPROCESS_COUNT)
1514 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1515
1516#ifdef IPG_DEBUG
1517 /* Check if the RFD list contained no receive frame data. */
1518 if (!i)
1519 sp->EmptyRFDListCount++;
1520#endif
325a8071
AV		 1521 while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1522 !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1523 (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1202d6ff
FR		 1524 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1525
1526 rxfd = sp->rxd + entry;
1527
1528 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1529
1530 /* An unexpected event, additional code needed to handle
1531 * properly. So for the time being, just disregard the
1532 * frame.
1533 */
1534
1535 /* Free the memory associated with the RX
1536 * buffer since it is erroneous and we will
1537 * not pass it to higher layer processes.
1538 */
1539 if (sp->RxBuff[entry]) {
1540 pci_unmap_single(sp->pdev,
325a8071 1541 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff 1542 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
85d68a58 1543 dev_kfree_skb_irq(sp->RxBuff[entry]);
1202d6ff
FR		 1544 }
1545
1546 /* Assure RX buffer is not reused by IPG. */
1547 sp->RxBuff[entry] = NULL;
1548 }
1549
1550 sp->rx_current = curr;
1551
1552 /* Check to see if there are a minimum number of used
1553 * RFDs before restoring any (should improve performance.)
1554 */
1555 if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1556 ipg_nic_rxrestore(dev);
1557
1558 return 0;
1559}
1560#endif
1561
1562static void ipg_reset_after_host_error(struct work_struct *work)
1563{
1564 struct ipg_nic_private *sp =
1565 container_of(work, struct ipg_nic_private, task.work);
1566 struct net_device *dev = sp->dev;
1567
1568 IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1569
1570 /*
1571 * Acknowledge HostError interrupt by resetting
1572 * IPG DMA and HOST.
1573 */
1574 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1575
1576 init_rfdlist(dev);
1577 init_tfdlist(dev);
1578
1579 if (ipg_io_config(dev) < 0) {
1580 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1581 dev->name);
1582 schedule_delayed_work(&sp->task, HZ);
1583 }
1584}
1585
1586static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1587{
1588 struct net_device *dev = dev_inst;
1589 struct ipg_nic_private *sp = netdev_priv(dev);
1590 void __iomem *ioaddr = sp->ioaddr;
1591 unsigned int handled = 0;
1592 u16 status;
1593
1594 IPG_DEBUG_MSG("_interrupt_handler\n");
1595
1596#ifdef JUMBO_FRAME
1597 ipg_nic_rxrestore(dev);
1598#endif
227bc24d
FR		 1599 spin_lock(&sp->lock);
1600
1202d6ff
FR		 1601 /* Get interrupt source information, and acknowledge
1602 * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1603 * IntRequested, MacControlFrame, LinkEvent) interrupts
1604 * if issued. Also, all IPG interrupts are disabled by
1605 * reading IntStatusAck.
1606 */
1607 status = ipg_r16(INT_STATUS_ACK);
1608
1609 IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1610
1611 /* Shared IRQ of remove event. */
1612 if (!(status & IPG_IS_RSVD_MASK))
1613 goto out_enable;
1614
1615 handled = 1;
1616
1617 if (unlikely(!netif_running(dev)))
227bc24d 1618 goto out_unlock;
1202d6ff
FR		 1619
1620 /* If RFDListEnd interrupt, restore all used RFDs. */
1621 if (status & IPG_IS_RFD_LIST_END) {
1622 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1623
1624 /* The RFD list end indicates an RFD was encountered
1625 * with a 0 NextPtr, or with an RFDDone bit set to 1
1626 * (indicating the RFD is not read for use by the
1627 * IPG.) Try to restore all RFDs.
1628 */
1629 ipg_nic_rxrestore(dev);
1630
1631#ifdef IPG_DEBUG
1632 /* Increment the RFDlistendCount counter. */
1633 sp->RFDlistendCount++;
1634#endif
1635 }
1636
1637 /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1638 * IntRequested interrupt, process received frames. */
1639 if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1640 (status & IPG_IS_RFD_LIST_END) ||
1641 (status & IPG_IS_RX_DMA_COMPLETE) ||
1642 (status & IPG_IS_INT_REQUESTED)) {
1643#ifdef IPG_DEBUG
1644 /* Increment the RFD list checked counter if interrupted
1645 * only to check the RFD list. */
1646 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1647 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1648 (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1649 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1650 IPG_IS_UPDATE_STATS)))
1651 sp->RFDListCheckedCount++;
1652#endif
1653
1654 ipg_nic_rx(dev);
1655 }
1656
1657 /* If TxDMAComplete interrupt, free used TFDs. */
1658 if (status & IPG_IS_TX_DMA_COMPLETE)
1659 ipg_nic_txfree(dev);
1660
1661 /* TxComplete interrupts indicate one of numerous actions.
1662 * Determine what action to take based on TXSTATUS register.
1663 */
1664 if (status & IPG_IS_TX_COMPLETE)
1665 ipg_nic_txcleanup(dev);
1666
1667 /* If UpdateStats interrupt, update Linux Ethernet statistics */
1668 if (status & IPG_IS_UPDATE_STATS)
1669 ipg_nic_get_stats(dev);
1670
1671 /* If HostError interrupt, reset IPG. */
1672 if (status & IPG_IS_HOST_ERROR) {
1673 IPG_DDEBUG_MSG("HostError Interrupt\n");
1674
1675 schedule_delayed_work(&sp->task, 0);
1676 }
1677
1678 /* If LinkEvent interrupt, resolve autonegotiation. */
1679 if (status & IPG_IS_LINK_EVENT) {
1680 if (ipg_config_autoneg(dev) < 0)
1681 printk(KERN_INFO "%s: Auto-negotiation error.\n",
1682 dev->name);
1683 }
1684
1685 /* If MACCtrlFrame interrupt, do nothing. */
1686 if (status & IPG_IS_MAC_CTRL_FRAME)
1687 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1688
1689 /* If RxComplete interrupt, do nothing. */
1690 if (status & IPG_IS_RX_COMPLETE)
1691 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1692
1693 /* If RxEarly interrupt, do nothing. */
1694 if (status & IPG_IS_RX_EARLY)
1695 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1696
1697out_enable:
1698 /* Re-enable IPG interrupts. */
1699 ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1700 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1701 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
227bc24d 1702out_unlock:
1202d6ff 1703 spin_unlock(&sp->lock);
227bc24d 1704
1202d6ff
FR		 1705 return IRQ_RETVAL(handled);
1706}
1707
1708static void ipg_rx_clear(struct ipg_nic_private *sp)
1709{
1710 unsigned int i;
1711
1712 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1713 if (sp->RxBuff[i]) {
1714 struct ipg_rx *rxfd = sp->rxd + i;
1715
85d68a58 1716 dev_kfree_skb_irq(sp->RxBuff[i]);
1202d6ff
FR		 1717 sp->RxBuff[i] = NULL;
1718 pci_unmap_single(sp->pdev,
325a8071 1719 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff
FR		 1720 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1721 }
1722 }
1723}
1724
1725static void ipg_tx_clear(struct ipg_nic_private *sp)
1726{
1727 unsigned int i;
1728
1729 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1730 if (sp->TxBuff[i]) {
1731 struct ipg_tx *txfd = sp->txd + i;
1732
1733 pci_unmap_single(sp->pdev,
325a8071 1734 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1202d6ff
FR		 1735 sp->TxBuff[i]->len, PCI_DMA_TODEVICE);
1736
85d68a58 1737 dev_kfree_skb_irq(sp->TxBuff[i]);
1202d6ff
FR		 1738
1739 sp->TxBuff[i] = NULL;
1740 }
1741 }
1742}
1743
1744static int ipg_nic_open(struct net_device *dev)
1745{
1746 struct ipg_nic_private *sp = netdev_priv(dev);
1747 void __iomem *ioaddr = sp->ioaddr;
1748 struct pci_dev *pdev = sp->pdev;
1749 int rc;
1750
1751 IPG_DEBUG_MSG("_nic_open\n");
1752
1753 sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1754
1755 /* Check for interrupt line conflicts, and request interrupt
1756 * line for IPG.
1757 *
1758 * IMPORTANT: Disable IPG interrupts prior to registering
1759 * IRQ.
1760 */
1761 ipg_w16(0x0000, INT_ENABLE);
1762
1763 /* Register the interrupt line to be used by the IPG within
1764 * the Linux system.
1765 */
1766 rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1767 dev->name, dev);
1768 if (rc < 0) {
1769 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1770 dev->name);
1771 goto out;
1772 }
1773
1774 dev->irq = pdev->irq;
1775
1776 rc = -ENOMEM;
1777
1778 sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1779 &sp->rxd_map, GFP_KERNEL);
1780 if (!sp->rxd)
1781 goto err_free_irq_0;
1782
1783 sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1784 &sp->txd_map, GFP_KERNEL);
1785 if (!sp->txd)
1786 goto err_free_rx_1;
1787
1788 rc = init_rfdlist(dev);
1789 if (rc < 0) {
1790 printk(KERN_INFO "%s: Error during configuration.\n",
1791 dev->name);
1792 goto err_free_tx_2;
1793 }
1794
1795 init_tfdlist(dev);
1796
1797 rc = ipg_io_config(dev);
1798 if (rc < 0) {
1799 printk(KERN_INFO "%s: Error during configuration.\n",
1800 dev->name);
1801 goto err_release_tfdlist_3;
1802 }
1803
1804 /* Resolve autonegotiation. */
1805 if (ipg_config_autoneg(dev) < 0)
1806 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1807
1808#ifdef JUMBO_FRAME
1809 /* initialize JUMBO Frame control variable */
1810 sp->Jumbo.FoundStart = 0;
1811 sp->Jumbo.CurrentSize = 0;
1812 sp->Jumbo.skb = 0;
1813 dev->mtu = IPG_TXFRAG_SIZE;
1814#endif
1815
1816 /* Enable transmit and receive operation of the IPG. */
1817 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1818 IPG_MC_RSVD_MASK, MAC_CTRL);
1819
1820 netif_start_queue(dev);
1821out:
1822 return rc;
1823
1824err_release_tfdlist_3:
1825 ipg_tx_clear(sp);
1826 ipg_rx_clear(sp);
1827err_free_tx_2:
1828 dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1829err_free_rx_1:
1830 dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1831err_free_irq_0:
1832 free_irq(pdev->irq, dev);
1833 goto out;
1834}
1835
1836static int ipg_nic_stop(struct net_device *dev)
1837{
1838 struct ipg_nic_private *sp = netdev_priv(dev);
1839 void __iomem *ioaddr = sp->ioaddr;
1840 struct pci_dev *pdev = sp->pdev;
1841
1842 IPG_DEBUG_MSG("_nic_stop\n");
1843
1844 netif_stop_queue(dev);
1845
1846 IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1847 IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1848 IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1849 IPG_DUMPTFDLIST(dev);
1850
1851 do {
1852 (void) ipg_r16(INT_STATUS_ACK);
1853
1854 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1855
1856 synchronize_irq(pdev->irq);
1857 } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1858
1859 ipg_rx_clear(sp);
1860
1861 ipg_tx_clear(sp);
1862
1863 pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1864 pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1865
1866 free_irq(pdev->irq, dev);
1867
1868 return 0;
1869}
1870
1871static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1872{
1873 struct ipg_nic_private *sp = netdev_priv(dev);
1874 void __iomem *ioaddr = sp->ioaddr;
1875 unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1876 unsigned long flags;
1877 struct ipg_tx *txfd;
1878
1879 IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1880
1881 /* If in 10Mbps mode, stop the transmit queue so
1882 * no more transmit frames are accepted.
1883 */
1884 if (sp->tenmbpsmode)
1885 netif_stop_queue(dev);
1886
1887 if (sp->ResetCurrentTFD) {
1888 sp->ResetCurrentTFD = 0;
1889 entry = 0;
1890 }
1891
1892 txfd = sp->txd + entry;
1893
1894 sp->TxBuff[entry] = skb;
1895
1896 /* Clear all TFC fields, except TFDDONE. */
1897 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1898
1899 /* Specify the TFC field within the TFD. */
1900 txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1901 (IPG_TFC_FRAMEID & cpu_to_le64(sp->tx_current)) |
1902 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1903
1904 /* Request TxComplete interrupts at an interval defined
1905 * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1906 * Request TxComplete interrupt for every frame
1907 * if in 10Mbps mode to accomodate problem with 10Mbps
1908 * processing.
1909 */
1910 if (sp->tenmbpsmode)
1911 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
47cccd7d 1912 txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1202d6ff
FR		 1913 /* Based on compilation option, determine if FCS is to be
1914 * appended to transmit frame by IPG.
1915 */
1916 if (!(IPG_APPEND_FCS_ON_TX))
1917 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1918
1919 /* Based on compilation option, determine if IP, TCP and/or
1920 * UDP checksums are to be added to transmit frame by IPG.
1921 */
1922 if (IPG_ADD_IPCHECKSUM_ON_TX)
1923 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1924
1925 if (IPG_ADD_TCPCHECKSUM_ON_TX)
1926 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1927
1928 if (IPG_ADD_UDPCHECKSUM_ON_TX)
1929 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1930
1931 /* Based on compilation option, determine if VLAN tag info is to be
1932 * inserted into transmit frame by IPG.
1933 */
1934 if (IPG_INSERT_MANUAL_VLAN_TAG) {
1935 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1936 ((u64) IPG_MANUAL_VLAN_VID << 32) |
1937 ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1938 ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1939 }
1940
1941 /* The fragment start location within system memory is defined
1942 * by the sk_buff structure's data field. The physical address
1943 * of this location within the system's virtual memory space
1944 * is determined using the IPG_HOST2BUS_MAP function.
1945 */
1946 txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1947 skb->len, PCI_DMA_TODEVICE));
1948
1949 /* The length of the fragment within system memory is defined by
1950 * the sk_buff structure's len field.
1951 */
1952 txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1953 ((u64) (skb->len & 0xffff) << 48));
1954
1955 /* Clear the TFDDone bit last to indicate the TFD is ready
1956 * for transfer to the IPG.
1957 */
1958 txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1959
1960 spin_lock_irqsave(&sp->lock, flags);
1961
1962 sp->tx_current++;
1963
1964 mmiowb();
1965
1966 ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1967
1968 if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
dafdec74 1969 netif_stop_queue(dev);
1202d6ff
FR		 1970
1971 spin_unlock_irqrestore(&sp->lock, flags);
1972
1973 return NETDEV_TX_OK;
1974}
1975
1976static void ipg_set_phy_default_param(unsigned char rev,
1977 struct net_device *dev, int phy_address)
1978{
1979 unsigned short length;
1980 unsigned char revision;
1981 unsigned short *phy_param;
1982 unsigned short address, value;
1983
1984 phy_param = &DefaultPhyParam[0];
1985 length = *phy_param & 0x00FF;
1986 revision = (unsigned char)((*phy_param) >> 8);
1987 phy_param++;
1988 while (length != 0) {
1989 if (rev == revision) {
1990 while (length > 1) {
1991 address = *phy_param;
1992 value = *(phy_param + 1);
1993 phy_param += 2;
1994 mdio_write(dev, phy_address, address, value);
1995 length -= 4;
1996 }
1997 break;
1998 } else {
1999 phy_param += length / 2;
2000 length = *phy_param & 0x00FF;
2001 revision = (unsigned char)((*phy_param) >> 8);
2002 phy_param++;
2003 }
2004 }
2005}
2006
1202d6ff
FR		 2007static int read_eeprom(struct net_device *dev, int eep_addr)
2008{
2009 void __iomem *ioaddr = ipg_ioaddr(dev);
2010 unsigned int i;
2011 int ret = 0;
2012 u16 value;
2013
2014 value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2015 ipg_w16(value, EEPROM_CTRL);
2016
2017 for (i = 0; i < 1000; i++) {
2018 u16 data;
2019
2020 mdelay(10);
2021 data = ipg_r16(EEPROM_CTRL);
2022 if (!(data & IPG_EC_EEPROM_BUSY)) {
2023 ret = ipg_r16(EEPROM_DATA);
2024 break;
2025 }
2026 }
2027 return ret;
2028}
2029
2030static void ipg_init_mii(struct net_device *dev)
2031{
2032 struct ipg_nic_private *sp = netdev_priv(dev);
2033 struct mii_if_info *mii_if = &sp->mii_if;
2034 int phyaddr;
2035
2036 mii_if->dev = dev;
2037 mii_if->mdio_read = mdio_read;
2038 mii_if->mdio_write = mdio_write;
2039 mii_if->phy_id_mask = 0x1f;
2040 mii_if->reg_num_mask = 0x1f;
2041
2042 mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2043
2044 if (phyaddr != 0x1f) {
2045 u16 mii_phyctrl, mii_1000cr;
2046 u8 revisionid = 0;
2047
2048 mii_1000cr = mdio_read(dev, phyaddr, MII_CTRL1000);
2049 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2050 GMII_PHY_1000BASETCONTROL_PreferMaster;
2051 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2052
2053 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2054
2055 /* Set default phyparam */
2056 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2057 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2058
2059 /* Reset PHY */
2060 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2061 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2062
2063 }
2064}
2065
2066static int ipg_hw_init(struct net_device *dev)
2067{
2068 struct ipg_nic_private *sp = netdev_priv(dev);
2069 void __iomem *ioaddr = sp->ioaddr;
2070 unsigned int i;
2071 int rc;
2072
dea4a87c 2073 /* Read/Write and Reset EEPROM Value */
1202d6ff
FR		 2074 /* Read LED Mode Configuration from EEPROM */
2075 sp->LED_Mode = read_eeprom(dev, 6);
2076
2077 /* Reset all functions within the IPG. Do not assert
2078 * RST_OUT as not compatible with some PHYs.
2079 */
2080 rc = ipg_reset(dev, IPG_RESET_MASK);
2081 if (rc < 0)
2082 goto out;
2083
2084 ipg_init_mii(dev);
2085
2086 /* Read MAC Address from EEPROM */
2087 for (i = 0; i < 3; i++)
2088 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2089
2090 for (i = 0; i < 3; i++)
2091 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2092
2093 /* Set station address in ethernet_device structure. */
2094 dev->dev_addr[0] = ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2095 dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2096 dev->dev_addr[2] = ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2097 dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2098 dev->dev_addr[4] = ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2099 dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2100out:
2101 return rc;
2102}
2103
2104static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2105{
2106 struct ipg_nic_private *sp = netdev_priv(dev);
2107 int rc;
2108
2109 mutex_lock(&sp->mii_mutex);
2110 rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2111 mutex_unlock(&sp->mii_mutex);
2112
2113 return rc;
2114}
2115
2116static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2117{
2118 /* Function to accomodate changes to Maximum Transfer Unit
2119 * (or MTU) of IPG NIC. Cannot use default function since
2120 * the default will not allow for MTU > 1500 bytes.
2121 */
2122
2123 IPG_DEBUG_MSG("_nic_change_mtu\n");
2124
2125 /* Check that the new MTU value is between 68 (14 byte header, 46
2126 * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2127 * corresponds to the MAXFRAMESIZE register in the IPG.
2128 */
2129 if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2130 return -EINVAL;
2131
2132 dev->mtu = new_mtu;
2133
2134 return 0;
2135}
2136
2137static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2138{
2139 struct ipg_nic_private *sp = netdev_priv(dev);
2140 int rc;
2141
2142 mutex_lock(&sp->mii_mutex);
2143 rc = mii_ethtool_gset(&sp->mii_if, cmd);
2144 mutex_unlock(&sp->mii_mutex);
2145
2146 return rc;
2147}
2148
2149static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2150{
2151 struct ipg_nic_private *sp = netdev_priv(dev);
2152 int rc;
2153
2154 mutex_lock(&sp->mii_mutex);
2155 rc = mii_ethtool_sset(&sp->mii_if, cmd);
2156 mutex_unlock(&sp->mii_mutex);
2157
2158 return rc;
2159}
2160
2161static int ipg_nway_reset(struct net_device *dev)
2162{
2163 struct ipg_nic_private *sp = netdev_priv(dev);
2164 int rc;
2165
2166 mutex_lock(&sp->mii_mutex);
2167 rc = mii_nway_restart(&sp->mii_if);
2168 mutex_unlock(&sp->mii_mutex);
2169
2170 return rc;
2171}
2172
2173static struct ethtool_ops ipg_ethtool_ops = {
2174 .get_settings = ipg_get_settings,
2175 .set_settings = ipg_set_settings,
2176 .nway_reset = ipg_nway_reset,
2177};
2178
2179static void ipg_remove(struct pci_dev *pdev)
2180{
2181 struct net_device *dev = pci_get_drvdata(pdev);
2182 struct ipg_nic_private *sp = netdev_priv(dev);
2183
2184 IPG_DEBUG_MSG("_remove\n");
2185
2186 /* Un-register Ethernet device. */
2187 unregister_netdev(dev);
2188
2189 pci_iounmap(pdev, sp->ioaddr);
2190
2191 pci_release_regions(pdev);
2192
2193 free_netdev(dev);
2194 pci_disable_device(pdev);
2195 pci_set_drvdata(pdev, NULL);
2196}
2197
2198static int __devinit ipg_probe(struct pci_dev *pdev,
2199 const struct pci_device_id *id)
2200{
2201 unsigned int i = id->driver_data;
2202 struct ipg_nic_private *sp;
2203 struct net_device *dev;
2204 void __iomem *ioaddr;
2205 int rc;
2206
2207 rc = pci_enable_device(pdev);
2208 if (rc < 0)
2209 goto out;
2210
2211 printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2212
2213 pci_set_master(pdev);
2214
2215 rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2216 if (rc < 0) {
2217 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2218 if (rc < 0) {
2219 printk(KERN_ERR "%s: DMA config failed.\n",
2220 pci_name(pdev));
2221 goto err_disable_0;
2222 }
2223 }
2224
2225 /*
2226 * Initialize net device.
2227 */
2228 dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2229 if (!dev) {
2230 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2231 rc = -ENOMEM;
2232 goto err_disable_0;
2233 }
2234
2235 sp = netdev_priv(dev);
2236 spin_lock_init(&sp->lock);
2237 mutex_init(&sp->mii_mutex);
2238
2239 /* Declare IPG NIC functions for Ethernet device methods.
2240 */
2241 dev->open = &ipg_nic_open;
2242 dev->stop = &ipg_nic_stop;
2243 dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2244 dev->get_stats = &ipg_nic_get_stats;
2245 dev->set_multicast_list = &ipg_nic_set_multicast_list;
2246 dev->do_ioctl = ipg_ioctl;
2247 dev->tx_timeout = ipg_tx_timeout;
2248 dev->change_mtu = &ipg_nic_change_mtu;
2249
2250 SET_NETDEV_DEV(dev, &pdev->dev);
2251 SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2252
2253 rc = pci_request_regions(pdev, DRV_NAME);
2254 if (rc)
2255 goto err_free_dev_1;
2256
2257 ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2258 if (!ioaddr) {
2259 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2260 rc = -EIO;
2261 goto err_release_regions_2;
2262 }
2263
2264 /* Save the pointer to the PCI device information. */
2265 sp->ioaddr = ioaddr;
2266 sp->pdev = pdev;
2267 sp->dev = dev;
2268
2269 INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2270
2271 pci_set_drvdata(pdev, dev);
2272
2273 rc = ipg_hw_init(dev);
2274 if (rc < 0)
2275 goto err_unmap_3;
2276
2277 rc = register_netdev(dev);
2278 if (rc < 0)
2279 goto err_unmap_3;
2280
2281 printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2282out:
2283 return rc;
2284
2285err_unmap_3:
2286 pci_iounmap(pdev, ioaddr);
2287err_release_regions_2:
2288 pci_release_regions(pdev);
2289err_free_dev_1:
2290 free_netdev(dev);
2291err_disable_0:
2292 pci_disable_device(pdev);
2293 goto out;
2294}
2295
2296static struct pci_driver ipg_pci_driver = {
2297 .name = IPG_DRIVER_NAME,
2298 .id_table = ipg_pci_tbl,
2299 .probe = ipg_probe,
2300 .remove = __devexit_p(ipg_remove),
2301};
2302
2303static int __init ipg_init_module(void)
2304{
2305 return pci_register_driver(&ipg_pci_driver);
2306}
2307
2308static void __exit ipg_exit_module(void)
2309{
2310 pci_unregister_driver(&ipg_pci_driver);
2311}
2312
2313module_init(ipg_init_module);
2314module_exit(ipg_exit_module);
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