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drivers/net/: use DEFINE_PCI_DEVICE_TABLE()
[net-next-2.6.git] / drivers / net / ipg.c
CommitLineData
1202d6ff
FR		 1/*
2 * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
3 *
4 * Copyright (C) 2003, 2007 IC Plus Corp
5 *
6 * Original Author:
7 *
8 * Craig Rich
9 * Sundance Technology, Inc.
10 * www.sundanceti.com
11 * craig_rich@sundanceti.com
12 *
13 * Current Maintainer:
14 *
15 * Sorbica Shieh.
16 * http://www.icplus.com.tw
17 * sorbica@icplus.com.tw
18 *
19 * Jesse Huang
20 * http://www.icplus.com.tw
21 * jesse@icplus.com.tw
22 */
23#include <linux/crc32.h>
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/mutex.h>
27
1dad939d 28#include <asm/div64.h>
29
1202d6ff
FR		 30#define IPG_RX_RING_BYTES (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31#define IPG_TX_RING_BYTES (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32#define IPG_RESET_MASK \
33 (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34 IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
35 IPG_AC_AUTO_INIT)
36
8da5bb7a
PE		 37#define ipg_w32(val32, reg) iowrite32((val32), ioaddr + (reg))
38#define ipg_w16(val16, reg) iowrite16((val16), ioaddr + (reg))
39#define ipg_w8(val8, reg) iowrite8((val8), ioaddr + (reg))
1202d6ff
FR		 40
41#define ipg_r32(reg) ioread32(ioaddr + (reg))
42#define ipg_r16(reg) ioread16(ioaddr + (reg))
43#define ipg_r8(reg) ioread8(ioaddr + (reg))
44
1202d6ff
FR		 45enum {
46 netdev_io_size = 128
47};
48
49#include "ipg.h"
50#define DRV_NAME "ipg"
51
52MODULE_AUTHOR("IC Plus Corp. 2003");
1662e4b7 53MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
1202d6ff
FR		 54MODULE_LICENSE("GPL");
55
532f4aee
PE		 56/*
57 * Defaults
58 */
59#define IPG_MAX_RXFRAME_SIZE 0x0600
60#define IPG_RXFRAG_SIZE 0x0600
61#define IPG_RXSUPPORT_SIZE 0x0600
62#define IPG_IS_JUMBO false
63
8da5bb7a
PE		 64/*
65 * Variable record -- index by leading revision/length
66 * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
67 */
96fd74b2 68static unsigned short DefaultPhyParam[] = {
8da5bb7a 69 /* 11/12/03 IP1000A v1-3 rev=0x40 */
96fd74b2
AB		 70 /*--------------------------------------------------------------------------
71 (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
72 27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
73 31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7, 9, 0x0700,
74 --------------------------------------------------------------------------*/
8da5bb7a 75 /* 12/17/03 IP1000A v1-4 rev=0x40 */
96fd74b2
AB		 76 (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
77 0x0000,
78 30, 0x005e, 9, 0x0700,
8da5bb7a 79 /* 01/09/04 IP1000A v1-5 rev=0x41 */
96fd74b2
AB		 80 (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
81 0x0000,
82 30, 0x005e, 9, 0x0700,
83 0x0000
84};
85
1202d6ff
FR		 86static const char *ipg_brand_name[] = {
87 "IC PLUS IP1000 1000/100/10 based NIC",
88 "Sundance Technology ST2021 based NIC",
89 "Tamarack Microelectronics TC9020/9021 based NIC",
90 "Tamarack Microelectronics TC9020/9021 based NIC",
91 "D-Link NIC",
92 "D-Link NIC IP1000A"
93};
94
a3aa1884 95static DEFINE_PCI_DEVICE_TABLE(ipg_pci_tbl) = {
1202d6ff
FR		 96 { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
97 { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
98 { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
99 { PCI_VDEVICE(DLINK, 0x9021), 3 },
100 { PCI_VDEVICE(DLINK, 0x4000), 4 },
101 { PCI_VDEVICE(DLINK, 0x4020), 5 },
102 { 0, }
103};
104
105MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
106
107static inline void __iomem *ipg_ioaddr(struct net_device *dev)
108{
109 struct ipg_nic_private *sp = netdev_priv(dev);
110 return sp->ioaddr;
111}
112
113#ifdef IPG_DEBUG
114static void ipg_dump_rfdlist(struct net_device *dev)
115{
116 struct ipg_nic_private *sp = netdev_priv(dev);
117 void __iomem *ioaddr = sp->ioaddr;
118 unsigned int i;
119 u32 offset;
120
121 IPG_DEBUG_MSG("_dump_rfdlist\n");
122
123 printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
124 printk(KERN_INFO "rx_dirty = %2.2x\n", sp->rx_dirty);
125 printk(KERN_INFO "RFDList start address = %16.16lx\n",
126 (unsigned long) sp->rxd_map);
127 printk(KERN_INFO "RFDListPtr register = %8.8x%8.8x\n",
128 ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
129
130 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
131 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
132 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
133 offset, (unsigned long) sp->rxd[i].next_desc);
134 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
135 printk(KERN_INFO "%2.2x %4.4x RFS = %16.16lx\n", i,
136 offset, (unsigned long) sp->rxd[i].rfs);
137 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
138 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
139 offset, (unsigned long) sp->rxd[i].frag_info);
140 }
141}
142
143static void ipg_dump_tfdlist(struct net_device *dev)
144{
145 struct ipg_nic_private *sp = netdev_priv(dev);
146 void __iomem *ioaddr = sp->ioaddr;
147 unsigned int i;
148 u32 offset;
149
150 IPG_DEBUG_MSG("_dump_tfdlist\n");
151
152 printk(KERN_INFO "tx_current = %2.2x\n", sp->tx_current);
153 printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
154 printk(KERN_INFO "TFDList start address = %16.16lx\n",
155 (unsigned long) sp->txd_map);
156 printk(KERN_INFO "TFDListPtr register = %8.8x%8.8x\n",
157 ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
158
159 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
160 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
161 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
162 offset, (unsigned long) sp->txd[i].next_desc);
163
164 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
165 printk(KERN_INFO "%2.2x %4.4x TFC = %16.16lx\n", i,
166 offset, (unsigned long) sp->txd[i].tfc);
167 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
168 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
169 offset, (unsigned long) sp->txd[i].frag_info);
170 }
171}
172#endif
173
174static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
175{
176 ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
177 ndelay(IPG_PC_PHYCTRLWAIT_NS);
178}
179
180static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
181{
182 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
183 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
184}
185
186static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
187{
188 phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
189
190 ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
191}
192
193static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
194{
195 ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
196 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
197}
198
8da5bb7a 199static u16 read_phy_bit(void __iomem *ioaddr, u8 phyctrlpolarity)
1202d6ff
FR		 200{
201 u16 bit_data;
202
203 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
204
205 bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
206
207 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
208
209 return bit_data;
210}
211
212/*
213 * Read a register from the Physical Layer device located
214 * on the IPG NIC, using the IPG PHYCTRL register.
215 */
8da5bb7a 216static int mdio_read(struct net_device *dev, int phy_id, int phy_reg)
1202d6ff
FR		 217{
218 void __iomem *ioaddr = ipg_ioaddr(dev);
219 /*
220 * The GMII mangement frame structure for a read is as follows:
221 *
222 * |Preamble|st|op|phyad|regad|ta| data |idle|
223 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
224 *
225 * <32 1s> = 32 consecutive logic 1 values
226 * A = bit of Physical Layer device address (MSB first)
227 * R = bit of register address (MSB first)
228 * z = High impedance state
229 * D = bit of read data (MSB first)
230 *
231 * Transmission order is 'Preamble' field first, bits transmitted
232 * left to right (first to last).
233 */
234 struct {
235 u32 field;
236 unsigned int len;
237 } p[] = {
238 { GMII_PREAMBLE, 32 }, /* Preamble */
239 { GMII_ST, 2 }, /* ST */
240 { GMII_READ, 2 }, /* OP */
241 { phy_id, 5 }, /* PHYAD */
242 { phy_reg, 5 }, /* REGAD */
243 { 0x0000, 2 }, /* TA */
244 { 0x0000, 16 }, /* DATA */
245 { 0x0000, 1 } /* IDLE */
246 };
247 unsigned int i, j;
248 u8 polarity, data;
249
250 polarity = ipg_r8(PHY_CTRL);
251 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
252
253 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
254 for (j = 0; j < 5; j++) {
255 for (i = 0; i < p[j].len; i++) {
256 /* For each variable length field, the MSB must be
257 * transmitted first. Rotate through the field bits,
258 * starting with the MSB, and move each bit into the
259 * the 1st (2^1) bit position (this is the bit position
260 * corresponding to the MgmtData bit of the PhyCtrl
261 * register for the IPG).
262 *
263 * Example: ST = 01;
264 *
265 * First write a '0' to bit 1 of the PhyCtrl
266 * register, then write a '1' to bit 1 of the
267 * PhyCtrl register.
268 *
269 * To do this, right shift the MSB of ST by the value:
270 * [field length - 1 - #ST bits already written]
271 * then left shift this result by 1.
272 */
273 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
274 data &= IPG_PC_MGMTDATA;
275 data |= polarity | IPG_PC_MGMTDIR;
276
277 ipg_drive_phy_ctl_low_high(ioaddr, data);
278 }
279 }
280
281 send_three_state(ioaddr, polarity);
282
283 read_phy_bit(ioaddr, polarity);
284
285 /*
286 * For a read cycle, the bits for the next two fields (TA and
287 * DATA) are driven by the PHY (the IPG reads these bits).
288 */
289 for (i = 0; i < p[6].len; i++) {
290 p[6].field |=
291 (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
292 }
293
294 send_three_state(ioaddr, polarity);
295 send_three_state(ioaddr, polarity);
296 send_three_state(ioaddr, polarity);
297 send_end(ioaddr, polarity);
298
299 /* Return the value of the DATA field. */
300 return p[6].field;
301}
302
303/*
304 * Write to a register from the Physical Layer device located
305 * on the IPG NIC, using the IPG PHYCTRL register.
306 */
307static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
308{
309 void __iomem *ioaddr = ipg_ioaddr(dev);
310 /*
311 * The GMII mangement frame structure for a read is as follows:
312 *
313 * |Preamble|st|op|phyad|regad|ta| data |idle|
314 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
315 *
316 * <32 1s> = 32 consecutive logic 1 values
317 * A = bit of Physical Layer device address (MSB first)
318 * R = bit of register address (MSB first)
319 * z = High impedance state
320 * D = bit of write data (MSB first)
321 *
322 * Transmission order is 'Preamble' field first, bits transmitted
323 * left to right (first to last).
324 */
325 struct {
326 u32 field;
327 unsigned int len;
328 } p[] = {
329 { GMII_PREAMBLE, 32 }, /* Preamble */
330 { GMII_ST, 2 }, /* ST */
331 { GMII_WRITE, 2 }, /* OP */
332 { phy_id, 5 }, /* PHYAD */
333 { phy_reg, 5 }, /* REGAD */
334 { 0x0002, 2 }, /* TA */
335 { val & 0xffff, 16 }, /* DATA */
336 { 0x0000, 1 } /* IDLE */
337 };
338 unsigned int i, j;
339 u8 polarity, data;
340
341 polarity = ipg_r8(PHY_CTRL);
342 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
343
344 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
345 for (j = 0; j < 7; j++) {
346 for (i = 0; i < p[j].len; i++) {
347 /* For each variable length field, the MSB must be
348 * transmitted first. Rotate through the field bits,
349 * starting with the MSB, and move each bit into the
350 * the 1st (2^1) bit position (this is the bit position
351 * corresponding to the MgmtData bit of the PhyCtrl
352 * register for the IPG).
353 *
354 * Example: ST = 01;
355 *
356 * First write a '0' to bit 1 of the PhyCtrl
357 * register, then write a '1' to bit 1 of the
358 * PhyCtrl register.
359 *
360 * To do this, right shift the MSB of ST by the value:
361 * [field length - 1 - #ST bits already written]
362 * then left shift this result by 1.
363 */
364 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
365 data &= IPG_PC_MGMTDATA;
366 data |= polarity | IPG_PC_MGMTDIR;
367
368 ipg_drive_phy_ctl_low_high(ioaddr, data);
369 }
370 }
371
372 /* The last cycle is a tri-state, so read from the PHY. */
373 for (j = 7; j < 8; j++) {
374 for (i = 0; i < p[j].len; i++) {
375 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
376
377 p[j].field |= ((ipg_r8(PHY_CTRL) &
378 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
379
380 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
381 }
382 }
383}
384
1202d6ff
FR		 385static void ipg_set_led_mode(struct net_device *dev)
386{
387 struct ipg_nic_private *sp = netdev_priv(dev);
388 void __iomem *ioaddr = sp->ioaddr;
389 u32 mode;
390
391 mode = ipg_r32(ASIC_CTRL);
392 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
393
9893ba16 394 if ((sp->led_mode & 0x03) > 1)
1202d6ff
FR		 395 mode |= IPG_AC_LED_MODE_BIT_1; /* Write Asic Control Bit 29 */
396
9893ba16 397 if ((sp->led_mode & 0x01) == 1)
1202d6ff
FR		 398 mode |= IPG_AC_LED_MODE; /* Write Asic Control Bit 14 */
399
9893ba16 400 if ((sp->led_mode & 0x08) == 8)
1202d6ff
FR		 401 mode |= IPG_AC_LED_SPEED; /* Write Asic Control Bit 27 */
402
403 ipg_w32(mode, ASIC_CTRL);
404}
405
1202d6ff
FR		 406static void ipg_set_phy_set(struct net_device *dev)
407{
408 struct ipg_nic_private *sp = netdev_priv(dev);
409 void __iomem *ioaddr = sp->ioaddr;
410 int physet;
411
412 physet = ipg_r8(PHY_SET);
413 physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
9893ba16 414 physet |= ((sp->led_mode & 0x70) >> 4);
1202d6ff
FR		 415 ipg_w8(physet, PHY_SET);
416}
417
418static int ipg_reset(struct net_device *dev, u32 resetflags)
419{
420 /* Assert functional resets via the IPG AsicCtrl
421 * register as specified by the 'resetflags' input
422 * parameter.
423 */
dea4a87c 424 void __iomem *ioaddr = ipg_ioaddr(dev);
1202d6ff
FR		 425 unsigned int timeout_count = 0;
426
427 IPG_DEBUG_MSG("_reset\n");
428
429 ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
430
431 /* Delay added to account for problem with 10Mbps reset. */
432 mdelay(IPG_AC_RESETWAIT);
433
434 while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
435 mdelay(IPG_AC_RESETWAIT);
436 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
437 return -ETIME;
438 }
dea4a87c 439 /* Set LED Mode in Asic Control */
1202d6ff
FR		 440 ipg_set_led_mode(dev);
441
dea4a87c 442 /* Set PHYSet Register Value */
1202d6ff
FR		 443 ipg_set_phy_set(dev);
444 return 0;
445}
446
447/* Find the GMII PHY address. */
448static int ipg_find_phyaddr(struct net_device *dev)
449{
450 unsigned int phyaddr, i;
451
452 for (i = 0; i < 32; i++) {
453 u32 status;
454
455 /* Search for the correct PHY address among 32 possible. */
456 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
457
458 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
459 GMII_PHY_ID1
460 */
461
462 status = mdio_read(dev, phyaddr, MII_BMSR);
463
464 if ((status != 0xFFFF) && (status != 0))
465 return phyaddr;
466 }
467
468 return 0x1f;
469}
470
471/*
472 * Configure IPG based on result of IEEE 802.3 PHY
473 * auto-negotiation.
474 */
475static int ipg_config_autoneg(struct net_device *dev)
476{
477 struct ipg_nic_private *sp = netdev_priv(dev);
478 void __iomem *ioaddr = sp->ioaddr;
479 unsigned int txflowcontrol;
480 unsigned int rxflowcontrol;
481 unsigned int fullduplex;
1202d6ff
FR		 482 u32 mac_ctrl_val;
483 u32 asicctrl;
484 u8 phyctrl;
485
486 IPG_DEBUG_MSG("_config_autoneg\n");
487
488 asicctrl = ipg_r32(ASIC_CTRL);
489 phyctrl = ipg_r8(PHY_CTRL);
490 mac_ctrl_val = ipg_r32(MAC_CTRL);
491
492 /* Set flags for use in resolving auto-negotation, assuming
493 * non-1000Mbps, half duplex, no flow control.
494 */
495 fullduplex = 0;
496 txflowcontrol = 0;
497 rxflowcontrol = 0;
1202d6ff
FR		 498
499 /* To accomodate a problem in 10Mbps operation,
500 * set a global flag if PHY running in 10Mbps mode.
501 */
502 sp->tenmbpsmode = 0;
503
504 printk(KERN_INFO "%s: Link speed = ", dev->name);
505
506 /* Determine actual speed of operation. */
507 switch (phyctrl & IPG_PC_LINK_SPEED) {
508 case IPG_PC_LINK_SPEED_10MBPS:
509 printk("10Mbps.\n");
510 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
511 dev->name);
512 sp->tenmbpsmode = 1;
513 break;
514 case IPG_PC_LINK_SPEED_100MBPS:
515 printk("100Mbps.\n");
516 break;
517 case IPG_PC_LINK_SPEED_1000MBPS:
518 printk("1000Mbps.\n");
1202d6ff
FR		 519 break;
520 default:
521 printk("undefined!\n");
522 return 0;
523 }
524
525 if (phyctrl & IPG_PC_DUPLEX_STATUS) {
526 fullduplex = 1;
527 txflowcontrol = 1;
528 rxflowcontrol = 1;
529 }
530
531 /* Configure full duplex, and flow control. */
532 if (fullduplex == 1) {
533 /* Configure IPG for full duplex operation. */
534 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
535
536 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
537
538 if (txflowcontrol == 1) {
539 printk("TX flow control");
540 mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
541 } else {
542 printk("no TX flow control");
543 mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
544 }
545
546 if (rxflowcontrol == 1) {
547 printk(", RX flow control.");
548 mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
549 } else {
550 printk(", no RX flow control.");
551 mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
552 }
553
554 printk("\n");
555 } else {
556 /* Configure IPG for half duplex operation. */
8da5bb7a 557 printk(KERN_INFO "%s: setting half duplex, "
1202d6ff
FR		 558 "no TX flow control, no RX flow control.\n", dev->name);
559
560 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
561 ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
562 ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
563 }
564 ipg_w32(mac_ctrl_val, MAC_CTRL);
565 return 0;
566}
567
568/* Determine and configure multicast operation and set
569 * receive mode for IPG.
570 */
571static void ipg_nic_set_multicast_list(struct net_device *dev)
572{
573 void __iomem *ioaddr = ipg_ioaddr(dev);
574 struct dev_mc_list *mc_list_ptr;
575 unsigned int hashindex;
576 u32 hashtable[2];
577 u8 receivemode;
578
579 IPG_DEBUG_MSG("_nic_set_multicast_list\n");
580
581 receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
582
583 if (dev->flags & IFF_PROMISC) {
584 /* NIC to be configured in promiscuous mode. */
585 receivemode = IPG_RM_RECEIVEALLFRAMES;
586 } else if ((dev->flags & IFF_ALLMULTI) ||
0761248f 587 ((dev->flags & IFF_MULTICAST) &&
1202d6ff
FR		 588 (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
589 /* NIC to be configured to receive all multicast
590 * frames. */
591 receivemode |= IPG_RM_RECEIVEMULTICAST;
0761248f 592 } else if ((dev->flags & IFF_MULTICAST) && (dev->mc_count > 0)) {
1202d6ff
FR		 593 /* NIC to be configured to receive selected
594 * multicast addresses. */
595 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
596 }
597
598 /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
599 * The IPG applies a cyclic-redundancy-check (the same CRC
600 * used to calculate the frame data FCS) to the destination
601 * address all incoming multicast frames whose destination
602 * address has the multicast bit set. The least significant
603 * 6 bits of the CRC result are used as an addressing index
604 * into the hash table. If the value of the bit addressed by
605 * this index is a 1, the frame is passed to the host system.
606 */
607
608 /* Clear hashtable. */
609 hashtable[0] = 0x00000000;
610 hashtable[1] = 0x00000000;
611
612 /* Cycle through all multicast addresses to filter. */
613 for (mc_list_ptr = dev->mc_list;
614 mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
615 /* Calculate CRC result for each multicast address. */
616 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
617 ETH_ALEN);
618
619 /* Use only the least significant 6 bits. */
620 hashindex = hashindex & 0x3F;
621
622 /* Within "hashtable", set bit number "hashindex"
623 * to a logic 1.
624 */
625 set_bit(hashindex, (void *)hashtable);
626 }
627
628 /* Write the value of the hashtable, to the 4, 16 bit
629 * HASHTABLE IPG registers.
630 */
631 ipg_w32(hashtable[0], HASHTABLE_0);
632 ipg_w32(hashtable[1], HASHTABLE_1);
633
634 ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
635
636 IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
637}
638
639static int ipg_io_config(struct net_device *dev)
640{
da02b231 641 struct ipg_nic_private *sp = netdev_priv(dev);
1202d6ff
FR		 642 void __iomem *ioaddr = ipg_ioaddr(dev);
643 u32 origmacctrl;
644 u32 restoremacctrl;
645
646 IPG_DEBUG_MSG("_io_config\n");
647
648 origmacctrl = ipg_r32(MAC_CTRL);
649
650 restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
651
652 /* Based on compilation option, determine if FCS is to be
653 * stripped on receive frames by IPG.
654 */
655 if (!IPG_STRIP_FCS_ON_RX)
656 restoremacctrl |= IPG_MC_RCV_FCS;
657
658 /* Determine if transmitter and/or receiver are
659 * enabled so we may restore MACCTRL correctly.
660 */
661 if (origmacctrl & IPG_MC_TX_ENABLED)
662 restoremacctrl |= IPG_MC_TX_ENABLE;
663
664 if (origmacctrl & IPG_MC_RX_ENABLED)
665 restoremacctrl |= IPG_MC_RX_ENABLE;
666
667 /* Transmitter and receiver must be disabled before setting
668 * IFSSelect.
669 */
670 ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
671 IPG_MC_RSVD_MASK, MAC_CTRL);
672
673 /* Now that transmitter and receiver are disabled, write
674 * to IFSSelect.
675 */
676 ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
677
678 /* Set RECEIVEMODE register. */
679 ipg_nic_set_multicast_list(dev);
680
da02b231 681 ipg_w16(sp->max_rxframe_size, MAX_FRAME_SIZE);
1202d6ff
FR		 682
683 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE, RX_DMA_POLL_PERIOD);
684 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
685 ipg_w8(IPG_RXDMABURSTTHRESH_VALUE, RX_DMA_BURST_THRESH);
686 ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE, TX_DMA_POLL_PERIOD);
687 ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
688 ipg_w8(IPG_TXDMABURSTTHRESH_VALUE, TX_DMA_BURST_THRESH);
689 ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
690 IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
691 IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
692 IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
693 ipg_w16(IPG_FLOWONTHRESH_VALUE, FLOW_ON_THRESH);
694 ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
695
696 /* IPG multi-frag frame bug workaround.
697 * Per silicon revision B3 eratta.
698 */
699 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
700
701 /* IPG TX poll now bug workaround.
702 * Per silicon revision B3 eratta.
703 */
704 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
705
706 /* IPG RX poll now bug workaround.
707 * Per silicon revision B3 eratta.
708 */
709 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
710
711 /* Now restore MACCTRL to original setting. */
712 ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
713
714 /* Disable unused RMON statistics. */
715 ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
716
717 /* Disable unused MIB statistics. */
718 ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
719 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
720 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
721 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
722 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
723 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
724
725 return 0;
726}
727
728/*
729 * Create a receive buffer within system memory and update
730 * NIC private structure appropriately.
731 */
732static int ipg_get_rxbuff(struct net_device *dev, int entry)
733{
734 struct ipg_nic_private *sp = netdev_priv(dev);
735 struct ipg_rx *rxfd = sp->rxd + entry;
736 struct sk_buff *skb;
737 u64 rxfragsize;
738
739 IPG_DEBUG_MSG("_get_rxbuff\n");
740
89d71a66 741 skb = netdev_alloc_skb_ip_align(dev, sp->rxsupport_size);
1202d6ff 742 if (!skb) {
9893ba16 743 sp->rx_buff[entry] = NULL;
1202d6ff
FR		 744 return -ENOMEM;
745 }
746
1202d6ff
FR		 747 /* Associate the receive buffer with the IPG NIC. */
748 skb->dev = dev;
749
750 /* Save the address of the sk_buff structure. */
9893ba16 751 sp->rx_buff[entry] = skb;
1202d6ff
FR		 752
753 rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
754 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
755
756 /* Set the RFD fragment length. */
18a9cdb9 757 rxfragsize = sp->rxfrag_size;
1202d6ff
FR		 758 rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
759
760 return 0;
761}
762
763static int init_rfdlist(struct net_device *dev)
764{
765 struct ipg_nic_private *sp = netdev_priv(dev);
766 void __iomem *ioaddr = sp->ioaddr;
767 unsigned int i;
768
769 IPG_DEBUG_MSG("_init_rfdlist\n");
770
771 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
772 struct ipg_rx *rxfd = sp->rxd + i;
773
9893ba16 774 if (sp->rx_buff[i]) {
1202d6ff 775 pci_unmap_single(sp->pdev,
325a8071 776 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff 777 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
9893ba16
PE		 778 dev_kfree_skb_irq(sp->rx_buff[i]);
779 sp->rx_buff[i] = NULL;
1202d6ff
FR		 780 }
781
782 /* Clear out the RFS field. */
783 rxfd->rfs = 0x0000000000000000;
784
785 if (ipg_get_rxbuff(dev, i) < 0) {
786 /*
787 * A receive buffer was not ready, break the
788 * RFD list here.
789 */
790 IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
791
792 /* Just in case we cannot allocate a single RFD.
793 * Should not occur.
794 */
795 if (i == 0) {
796 printk(KERN_ERR "%s: No memory available"
797 " for RFD list.\n", dev->name);
798 return -ENOMEM;
799 }
800 }
801
802 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
803 sizeof(struct ipg_rx)*(i + 1));
804 }
805 sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
806
807 sp->rx_current = 0;
808 sp->rx_dirty = 0;
809
810 /* Write the location of the RFDList to the IPG. */
811 ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
812 ipg_w32(0x00000000, RFD_LIST_PTR_1);
813
814 return 0;
815}
816
817static void init_tfdlist(struct net_device *dev)
818{
819 struct ipg_nic_private *sp = netdev_priv(dev);
820 void __iomem *ioaddr = sp->ioaddr;
821 unsigned int i;
822
823 IPG_DEBUG_MSG("_init_tfdlist\n");
824
825 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
826 struct ipg_tx *txfd = sp->txd + i;
827
828 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
829
9893ba16
PE		 830 if (sp->tx_buff[i]) {
831 dev_kfree_skb_irq(sp->tx_buff[i]);
832 sp->tx_buff[i] = NULL;
1202d6ff
FR		 833 }
834
835 txfd->next_desc = cpu_to_le64(sp->txd_map +
836 sizeof(struct ipg_tx)*(i + 1));
837 }
838 sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
839
840 sp->tx_current = 0;
841 sp->tx_dirty = 0;
842
843 /* Write the location of the TFDList to the IPG. */
844 IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
845 (u32) sp->txd_map);
846 ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
847 ipg_w32(0x00000000, TFD_LIST_PTR_1);
848
9893ba16 849 sp->reset_current_tfd = 1;
1202d6ff
FR		 850}
851
852/*
853 * Free all transmit buffers which have already been transfered
854 * via DMA to the IPG.
855 */
856static void ipg_nic_txfree(struct net_device *dev)
857{
858 struct ipg_nic_private *sp = netdev_priv(dev);
0da1b995 859 unsigned int released, pending, dirty;
1dad939d 860
1202d6ff
FR		 861 IPG_DEBUG_MSG("_nic_txfree\n");
862
863 pending = sp->tx_current - sp->tx_dirty;
0da1b995 864 dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
1202d6ff
FR		 865
866 for (released = 0; released < pending; released++) {
9893ba16 867 struct sk_buff *skb = sp->tx_buff[dirty];
1202d6ff
FR		 868 struct ipg_tx *txfd = sp->txd + dirty;
869
870 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
871
872 /* Look at each TFD's TFC field beginning
873 * at the last freed TFD up to the current TFD.
874 * If the TFDDone bit is set, free the associated
875 * buffer.
876 */
0da1b995
FR		 877 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
878 break;
1202d6ff
FR		 879
880 /* Free the transmit buffer. */
881 if (skb) {
882 pci_unmap_single(sp->pdev,
325a8071 883 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1202d6ff
FR		 884 skb->len, PCI_DMA_TODEVICE);
885
85d68a58 886 dev_kfree_skb_irq(skb);
1202d6ff 887
9893ba16 888 sp->tx_buff[dirty] = NULL;
1202d6ff 889 }
0da1b995 890 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
1202d6ff
FR		 891 }
892
893 sp->tx_dirty += released;
894
895 if (netif_queue_stopped(dev) &&
896 (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
897 netif_wake_queue(dev);
898 }
899}
900
901static void ipg_tx_timeout(struct net_device *dev)
902{
903 struct ipg_nic_private *sp = netdev_priv(dev);
904 void __iomem *ioaddr = sp->ioaddr;
905
906 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
907 IPG_AC_FIFO);
908
909 spin_lock_irq(&sp->lock);
910
911 /* Re-configure after DMA reset. */
912 if (ipg_io_config(dev) < 0) {
913 printk(KERN_INFO "%s: Error during re-configuration.\n",
914 dev->name);
915 }
916
917 init_tfdlist(dev);
918
919 spin_unlock_irq(&sp->lock);
920
921 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
922 MAC_CTRL);
923}
924
925/*
926 * For TxComplete interrupts, free all transmit
927 * buffers which have already been transfered via DMA
928 * to the IPG.
929 */
930static void ipg_nic_txcleanup(struct net_device *dev)
931{
932 struct ipg_nic_private *sp = netdev_priv(dev);
933 void __iomem *ioaddr = sp->ioaddr;
934 unsigned int i;
935
936 IPG_DEBUG_MSG("_nic_txcleanup\n");
937
938 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
939 /* Reading the TXSTATUS register clears the
940 * TX_COMPLETE interrupt.
941 */
942 u32 txstatusdword = ipg_r32(TX_STATUS);
943
944 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
945
946 /* Check for Transmit errors. Error bits only valid if
947 * TX_COMPLETE bit in the TXSTATUS register is a 1.
948 */
949 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
950 break;
951
952 /* If in 10Mbps mode, indicate transmit is ready. */
953 if (sp->tenmbpsmode) {
954 netif_wake_queue(dev);
955 }
956
957 /* Transmit error, increment stat counters. */
958 if (txstatusdword & IPG_TS_TX_ERROR) {
959 IPG_DEBUG_MSG("Transmit error.\n");
960 sp->stats.tx_errors++;
961 }
962
963 /* Late collision, re-enable transmitter. */
964 if (txstatusdword & IPG_TS_LATE_COLLISION) {
965 IPG_DEBUG_MSG("Late collision on transmit.\n");
966 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
967 IPG_MC_RSVD_MASK, MAC_CTRL);
968 }
969
970 /* Maximum collisions, re-enable transmitter. */
971 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
972 IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
973 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
974 IPG_MC_RSVD_MASK, MAC_CTRL);
975 }
976
977 /* Transmit underrun, reset and re-enable
978 * transmitter.
979 */
980 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
981 IPG_DEBUG_MSG("Transmitter underrun.\n");
982 sp->stats.tx_fifo_errors++;
983 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
984 IPG_AC_NETWORK | IPG_AC_FIFO);
985
986 /* Re-configure after DMA reset. */
987 if (ipg_io_config(dev) < 0) {
988 printk(KERN_INFO
989 "%s: Error during re-configuration.\n",
990 dev->name);
991 }
992 init_tfdlist(dev);
993
994 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
995 IPG_MC_RSVD_MASK, MAC_CTRL);
996 }
997 }
998
999 ipg_nic_txfree(dev);
1000}
1001
1002/* Provides statistical information about the IPG NIC. */
96fd74b2 1003static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1202d6ff
FR		 1004{
1005 struct ipg_nic_private *sp = netdev_priv(dev);
1006 void __iomem *ioaddr = sp->ioaddr;
1007 u16 temp1;
1008 u16 temp2;
1009
1010 IPG_DEBUG_MSG("_nic_get_stats\n");
1011
1012 /* Check to see if the NIC has been initialized via nic_open,
1013 * before trying to read statistic registers.
1014 */
1015 if (!test_bit(__LINK_STATE_START, &dev->state))
1016 return &sp->stats;
1017
1018 sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1019 sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1020 sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1021 sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1022 temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1023 sp->stats.rx_errors += temp1;
1024 sp->stats.rx_missed_errors += temp1;
1025 temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1026 ipg_r32(IPG_LATECOLLISIONS);
1027 temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1028 sp->stats.collisions += temp1;
1029 sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1030 sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1031 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1032 sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1033
1034 /* detailed tx_errors */
1035 sp->stats.tx_carrier_errors += temp2;
1036
1037 /* detailed rx_errors */
1038 sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1039 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1040 sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1041
1042 /* Unutilized IPG statistic registers. */
1043 ipg_r32(IPG_MCSTFRAMESRCVDOK);
1044
1045 return &sp->stats;
1046}
1047
1048/* Restore used receive buffers. */
1049static int ipg_nic_rxrestore(struct net_device *dev)
1050{
1051 struct ipg_nic_private *sp = netdev_priv(dev);
1052 const unsigned int curr = sp->rx_current;
1053 unsigned int dirty = sp->rx_dirty;
1054
1055 IPG_DEBUG_MSG("_nic_rxrestore\n");
1056
1057 for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1058 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1059
1060 /* rx_copybreak may poke hole here and there. */
9893ba16 1061 if (sp->rx_buff[entry])
1202d6ff
FR		 1062 continue;
1063
1064 /* Generate a new receive buffer to replace the
1065 * current buffer (which will be released by the
1066 * Linux system).
1067 */
1068 if (ipg_get_rxbuff(dev, entry) < 0) {
1069 IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1070
1071 break;
1072 }
1073
1074 /* Reset the RFS field. */
1075 sp->rxd[entry].rfs = 0x0000000000000000;
1076 }
1077 sp->rx_dirty = dirty;
1078
1079 return 0;
1080}
1081
1202d6ff 1082/* use jumboindex and jumbosize to control jumbo frame status
8da5bb7a
PE		 1083 * initial status is jumboindex=-1 and jumbosize=0
1084 * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1085 * 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1086 * 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1087 * previous receiving and need to continue dumping the current one
1088 */
1202d6ff 1089enum {
9893ba16
PE		 1090 NORMAL_PACKET,
1091 ERROR_PACKET
1202d6ff
FR		 1092};
1093
1094enum {
9893ba16
PE		 1095 FRAME_NO_START_NO_END = 0,
1096 FRAME_WITH_START = 1,
1097 FRAME_WITH_END = 10,
1098 FRAME_WITH_START_WITH_END = 11
1202d6ff
FR		 1099};
1100
024f4d88 1101static void ipg_nic_rx_free_skb(struct net_device *dev)
1202d6ff
FR		 1102{
1103 struct ipg_nic_private *sp = netdev_priv(dev);
1104 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1105
9893ba16 1106 if (sp->rx_buff[entry]) {
1202d6ff
FR		 1107 struct ipg_rx *rxfd = sp->rxd + entry;
1108
1109 pci_unmap_single(sp->pdev,
b88ed5cc 1110 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff 1111 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
9893ba16
PE		 1112 dev_kfree_skb_irq(sp->rx_buff[entry]);
1113 sp->rx_buff[entry] = NULL;
1202d6ff
FR		 1114 }
1115}
1116
024f4d88 1117static int ipg_nic_rx_check_frame_type(struct net_device *dev)
1202d6ff
FR		 1118{
1119 struct ipg_nic_private *sp = netdev_priv(dev);
1120 struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
9893ba16 1121 int type = FRAME_NO_START_NO_END;
1202d6ff
FR		 1122
1123 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
9893ba16 1124 type += FRAME_WITH_START;
1202d6ff 1125 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
9893ba16 1126 type += FRAME_WITH_END;
1202d6ff
FR		 1127 return type;
1128}
1129
024f4d88 1130static int ipg_nic_rx_check_error(struct net_device *dev)
1202d6ff
FR		 1131{
1132 struct ipg_nic_private *sp = netdev_priv(dev);
1133 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1134 struct ipg_rx *rxfd = sp->rxd + entry;
1135
1136 if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1137 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1138 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1139 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1140 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1141 (unsigned long) rxfd->rfs);
1142
1143 /* Increment general receive error statistic. */
1144 sp->stats.rx_errors++;
1145
1146 /* Increment detailed receive error statistics. */
1147 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1148 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1149
1150 sp->stats.rx_fifo_errors++;
1151 }
1152
1153 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1154 IPG_DEBUG_MSG("RX runt occured.\n");
1155 sp->stats.rx_length_errors++;
1156 }
1157
1158 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1159 * error count handled by a IPG statistic register.
1160 */
1161
1162 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1163 IPG_DEBUG_MSG("RX alignment error occured.\n");
1164 sp->stats.rx_frame_errors++;
1165 }
1166
1167 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1168 * handled by a IPG statistic register.
1169 */
1170
1171 /* Free the memory associated with the RX
1172 * buffer since it is erroneous and we will
1173 * not pass it to higher layer processes.
1174 */
9893ba16 1175 if (sp->rx_buff[entry]) {
1202d6ff 1176 pci_unmap_single(sp->pdev,
b88ed5cc 1177 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff
FR		 1178 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1179
9893ba16
PE		 1180 dev_kfree_skb_irq(sp->rx_buff[entry]);
1181 sp->rx_buff[entry] = NULL;
1202d6ff 1182 }
9893ba16 1183 return ERROR_PACKET;
1202d6ff 1184 }
9893ba16 1185 return NORMAL_PACKET;
1202d6ff
FR		 1186}
1187
1188static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1189 struct ipg_nic_private *sp,
1190 struct ipg_rx *rxfd, unsigned entry)
1191{
9893ba16 1192 struct ipg_jumbo *jumbo = &sp->jumbo;
1202d6ff
FR		 1193 struct sk_buff *skb;
1194 int framelen;
1195
9893ba16 1196 if (jumbo->found_start) {
85d68a58 1197 dev_kfree_skb_irq(jumbo->skb);
9893ba16
PE		 1198 jumbo->found_start = 0;
1199 jumbo->current_size = 0;
1202d6ff
FR		 1200 jumbo->skb = NULL;
1201 }
1202
8da5bb7a 1203 /* 1: found error, 0 no error */
9893ba16 1204 if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1202d6ff
FR		 1205 return;
1206
9893ba16 1207 skb = sp->rx_buff[entry];
1202d6ff
FR		 1208 if (!skb)
1209 return;
1210
8da5bb7a 1211 /* accept this frame and send to upper layer */
1202d6ff 1212 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
18a9cdb9
PE		 1213 if (framelen > sp->rxfrag_size)
1214 framelen = sp->rxfrag_size;
1202d6ff
FR		 1215
1216 skb_put(skb, framelen);
1217 skb->protocol = eth_type_trans(skb, dev);
1218 skb->ip_summed = CHECKSUM_NONE;
1219 netif_rx(skb);
9893ba16 1220 sp->rx_buff[entry] = NULL;
1202d6ff
FR		 1221}
1222
1223static void ipg_nic_rx_with_start(struct net_device *dev,
1224 struct ipg_nic_private *sp,
1225 struct ipg_rx *rxfd, unsigned entry)
1226{
9893ba16 1227 struct ipg_jumbo *jumbo = &sp->jumbo;
1202d6ff
FR		 1228 struct pci_dev *pdev = sp->pdev;
1229 struct sk_buff *skb;
1230
8da5bb7a 1231 /* 1: found error, 0 no error */
9893ba16 1232 if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1202d6ff
FR		 1233 return;
1234
8da5bb7a 1235 /* accept this frame and send to upper layer */
9893ba16 1236 skb = sp->rx_buff[entry];
1202d6ff
FR		 1237 if (!skb)
1238 return;
1239
9893ba16 1240 if (jumbo->found_start)
85d68a58 1241 dev_kfree_skb_irq(jumbo->skb);
1202d6ff 1242
b88ed5cc 1243 pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff
FR		 1244 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1245
18a9cdb9 1246 skb_put(skb, sp->rxfrag_size);
1202d6ff 1247
9893ba16 1248 jumbo->found_start = 1;
18a9cdb9 1249 jumbo->current_size = sp->rxfrag_size;
1202d6ff
FR		 1250 jumbo->skb = skb;
1251
9893ba16 1252 sp->rx_buff[entry] = NULL;
1202d6ff
FR		 1253}
1254
1255static void ipg_nic_rx_with_end(struct net_device *dev,
1256 struct ipg_nic_private *sp,
1257 struct ipg_rx *rxfd, unsigned entry)
1258{
9893ba16 1259 struct ipg_jumbo *jumbo = &sp->jumbo;
1202d6ff 1260
8da5bb7a 1261 /* 1: found error, 0 no error */
9893ba16
PE		 1262 if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1263 struct sk_buff *skb = sp->rx_buff[entry];
1202d6ff
FR		 1264
1265 if (!skb)
1266 return;
1267
9893ba16 1268 if (jumbo->found_start) {
1202d6ff
FR		 1269 int framelen, endframelen;
1270
1271 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1272
ecfecfb5 1273 endframelen = framelen - jumbo->current_size;
39f20585 1274 if (framelen > sp->rxsupport_size)
85d68a58 1275 dev_kfree_skb_irq(jumbo->skb);
1202d6ff 1276 else {
ecfecfb5
PE		 1277 memcpy(skb_put(jumbo->skb, endframelen),
1278 skb->data, endframelen);
1202d6ff
FR		 1279
1280 jumbo->skb->protocol =
1281 eth_type_trans(jumbo->skb, dev);
1282
1283 jumbo->skb->ip_summed = CHECKSUM_NONE;
1284 netif_rx(jumbo->skb);
1285 }
1286 }
1287
9893ba16
PE		 1288 jumbo->found_start = 0;
1289 jumbo->current_size = 0;
1202d6ff
FR		 1290 jumbo->skb = NULL;
1291
1292 ipg_nic_rx_free_skb(dev);
1293 } else {
85d68a58 1294 dev_kfree_skb_irq(jumbo->skb);
9893ba16
PE		 1295 jumbo->found_start = 0;
1296 jumbo->current_size = 0;
1202d6ff
FR		 1297 jumbo->skb = NULL;
1298 }
1299}
1300
1301static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1302 struct ipg_nic_private *sp,
1303 struct ipg_rx *rxfd, unsigned entry)
1304{
9893ba16 1305 struct ipg_jumbo *jumbo = &sp->jumbo;
1202d6ff 1306
8da5bb7a 1307 /* 1: found error, 0 no error */
9893ba16
PE		 1308 if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1309 struct sk_buff *skb = sp->rx_buff[entry];
1202d6ff
FR		 1310
1311 if (skb) {
9893ba16 1312 if (jumbo->found_start) {
18a9cdb9 1313 jumbo->current_size += sp->rxfrag_size;
39f20585 1314 if (jumbo->current_size <= sp->rxsupport_size) {
1202d6ff 1315 memcpy(skb_put(jumbo->skb,
18a9cdb9
PE		 1316 sp->rxfrag_size),
1317 skb->data, sp->rxfrag_size);
1202d6ff
FR		 1318 }
1319 }
1202d6ff
FR		 1320 ipg_nic_rx_free_skb(dev);
1321 }
1322 } else {
85d68a58 1323 dev_kfree_skb_irq(jumbo->skb);
9893ba16
PE		 1324 jumbo->found_start = 0;
1325 jumbo->current_size = 0;
1202d6ff
FR		 1326 jumbo->skb = NULL;
1327 }
1328}
1329
024f4d88 1330static int ipg_nic_rx_jumbo(struct net_device *dev)
1202d6ff
FR		 1331{
1332 struct ipg_nic_private *sp = netdev_priv(dev);
1333 unsigned int curr = sp->rx_current;
1334 void __iomem *ioaddr = sp->ioaddr;
1335 unsigned int i;
1336
1337 IPG_DEBUG_MSG("_nic_rx\n");
1338
1339 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1340 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1341 struct ipg_rx *rxfd = sp->rxd + entry;
1342
b88ed5cc 1343 if (!(rxfd->rfs & cpu_to_le64(IPG_RFS_RFDDONE)))
1202d6ff
FR		 1344 break;
1345
1346 switch (ipg_nic_rx_check_frame_type(dev)) {
9893ba16 1347 case FRAME_WITH_START_WITH_END:
ecfecfb5 1348 ipg_nic_rx_with_start_and_end(dev, sp, rxfd, entry);
1202d6ff 1349 break;
9893ba16 1350 case FRAME_WITH_START:
ecfecfb5 1351 ipg_nic_rx_with_start(dev, sp, rxfd, entry);
1202d6ff 1352 break;
9893ba16 1353 case FRAME_WITH_END:
ecfecfb5 1354 ipg_nic_rx_with_end(dev, sp, rxfd, entry);
1202d6ff 1355 break;
9893ba16 1356 case FRAME_NO_START_NO_END:
ecfecfb5 1357 ipg_nic_rx_no_start_no_end(dev, sp, rxfd, entry);
1202d6ff
FR		 1358 break;
1359 }
1360 }
1361
1362 sp->rx_current = curr;
1363
1364 if (i == IPG_MAXRFDPROCESS_COUNT) {
1365 /* There are more RFDs to process, however the
1366 * allocated amount of RFD processing time has
1367 * expired. Assert Interrupt Requested to make
1368 * sure we come back to process the remaining RFDs.
1369 */
1370 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1371 }
1372
1373 ipg_nic_rxrestore(dev);
1374
1375 return 0;
1376}
1377
1202d6ff
FR		 1378static int ipg_nic_rx(struct net_device *dev)
1379{
1380 /* Transfer received Ethernet frames to higher network layers. */
1381 struct ipg_nic_private *sp = netdev_priv(dev);
1382 unsigned int curr = sp->rx_current;
1383 void __iomem *ioaddr = sp->ioaddr;
1384 struct ipg_rx *rxfd;
1385 unsigned int i;
1386
1387 IPG_DEBUG_MSG("_nic_rx\n");
1388
1389#define __RFS_MASK \
1390 cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1391
1392 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1393 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
9893ba16 1394 struct sk_buff *skb = sp->rx_buff[entry];
1202d6ff
FR		 1395 unsigned int framelen;
1396
1397 rxfd = sp->rxd + entry;
1398
1399 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1400 break;
1401
1402 /* Get received frame length. */
1403 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1404
1405 /* Check for jumbo frame arrival with too small
1406 * RXFRAG_SIZE.
1407 */
18a9cdb9 1408 if (framelen > sp->rxfrag_size) {
1202d6ff
FR		 1409 IPG_DEBUG_MSG
1410 ("RFS FrameLen > allocated fragment size.\n");
1411
18a9cdb9 1412 framelen = sp->rxfrag_size;
1202d6ff
FR		 1413 }
1414
325a8071 1415 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1202d6ff
FR		 1416 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1417 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
325a8071 1418 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1202d6ff
FR		 1419
1420 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1421 (unsigned long int) rxfd->rfs);
1422
1423 /* Increment general receive error statistic. */
1424 sp->stats.rx_errors++;
1425
1426 /* Increment detailed receive error statistics. */
325a8071 1427 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1202d6ff
FR		 1428 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1429 sp->stats.rx_fifo_errors++;
1430 }
1431
325a8071 1432 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1202d6ff
FR		 1433 IPG_DEBUG_MSG("RX runt occured.\n");
1434 sp->stats.rx_length_errors++;
1435 }
1436
325a8071 1437 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1202d6ff
FR		 1438 /* Do nothing, error count handled by a IPG
1439 * statistic register.
1440 */
1441
325a8071 1442 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1202d6ff
FR		 1443 IPG_DEBUG_MSG("RX alignment error occured.\n");
1444 sp->stats.rx_frame_errors++;
1445 }
1446
325a8071 1447 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1202d6ff
FR		 1448 /* Do nothing, error count handled by a IPG
1449 * statistic register.
1450 */
1451
1452 /* Free the memory associated with the RX
1453 * buffer since it is erroneous and we will
1454 * not pass it to higher layer processes.
1455 */
1456 if (skb) {
325a8071 1457 __le64 info = rxfd->frag_info;
1202d6ff
FR		 1458
1459 pci_unmap_single(sp->pdev,
325a8071 1460 le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1202d6ff
FR		 1461 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1462
85d68a58 1463 dev_kfree_skb_irq(skb);
1202d6ff
FR		 1464 }
1465 } else {
1466
1467 /* Adjust the new buffer length to accomodate the size
1468 * of the received frame.
1469 */
1470 skb_put(skb, framelen);
1471
1472 /* Set the buffer's protocol field to Ethernet. */
1473 skb->protocol = eth_type_trans(skb, dev);
1474
6d3b2cb9
PE		 1475 /* The IPG encountered an error with (or
1476 * there were no) IP/TCP/UDP checksums.
1477 * This may or may not indicate an invalid
1478 * IP/TCP/UDP frame was received. Let the
1479 * upper layer decide.
1202d6ff 1480 */
6d3b2cb9 1481 skb->ip_summed = CHECKSUM_NONE;
1202d6ff
FR		 1482
1483 /* Hand off frame for higher layer processing.
1484 * The function netif_rx() releases the sk_buff
1485 * when processing completes.
1486 */
1487 netif_rx(skb);
1202d6ff
FR		 1488 }
1489
1490 /* Assure RX buffer is not reused by IPG. */
9893ba16 1491 sp->rx_buff[entry] = NULL;
1202d6ff
FR		 1492 }
1493
1494 /*
1495 * If there are more RFDs to proces and the allocated amount of RFD
1496 * processing time has expired, assert Interrupt Requested to make
1497 * sure we come back to process the remaining RFDs.
1498 */
1499 if (i == IPG_MAXRFDPROCESS_COUNT)
1500 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1501
1502#ifdef IPG_DEBUG
1503 /* Check if the RFD list contained no receive frame data. */
1504 if (!i)
1505 sp->EmptyRFDListCount++;
1506#endif
325a8071
AV		 1507 while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1508 !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1509 (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1202d6ff
FR		 1510 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1511
1512 rxfd = sp->rxd + entry;
1513
1514 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1515
1516 /* An unexpected event, additional code needed to handle
1517 * properly. So for the time being, just disregard the
1518 * frame.
1519 */
1520
1521 /* Free the memory associated with the RX
1522 * buffer since it is erroneous and we will
1523 * not pass it to higher layer processes.
1524 */
9893ba16 1525 if (sp->rx_buff[entry]) {
1202d6ff 1526 pci_unmap_single(sp->pdev,
325a8071 1527 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff 1528 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
9893ba16 1529 dev_kfree_skb_irq(sp->rx_buff[entry]);
1202d6ff
FR		 1530 }
1531
1532 /* Assure RX buffer is not reused by IPG. */
9893ba16 1533 sp->rx_buff[entry] = NULL;
1202d6ff
FR		 1534 }
1535
1536 sp->rx_current = curr;
1537
1538 /* Check to see if there are a minimum number of used
1539 * RFDs before restoring any (should improve performance.)
1540 */
1541 if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1542 ipg_nic_rxrestore(dev);
1543
1544 return 0;
1545}
1202d6ff
FR		 1546
1547static void ipg_reset_after_host_error(struct work_struct *work)
1548{
1549 struct ipg_nic_private *sp =
1550 container_of(work, struct ipg_nic_private, task.work);
1551 struct net_device *dev = sp->dev;
1552
1553 IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1554
1555 /*
1556 * Acknowledge HostError interrupt by resetting
1557 * IPG DMA and HOST.
1558 */
1559 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1560
1561 init_rfdlist(dev);
1562 init_tfdlist(dev);
1563
1564 if (ipg_io_config(dev) < 0) {
1565 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1566 dev->name);
1567 schedule_delayed_work(&sp->task, HZ);
1568 }
1569}
1570
1571static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1572{
1573 struct net_device *dev = dev_inst;
1574 struct ipg_nic_private *sp = netdev_priv(dev);
1575 void __iomem *ioaddr = sp->ioaddr;
1576 unsigned int handled = 0;
1577 u16 status;
1578
1579 IPG_DEBUG_MSG("_interrupt_handler\n");
1580
024f4d88
PE		 1581 if (sp->is_jumbo)
1582 ipg_nic_rxrestore(dev);
1583
227bc24d
FR		 1584 spin_lock(&sp->lock);
1585
1202d6ff
FR		 1586 /* Get interrupt source information, and acknowledge
1587 * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1588 * IntRequested, MacControlFrame, LinkEvent) interrupts
1589 * if issued. Also, all IPG interrupts are disabled by
1590 * reading IntStatusAck.
1591 */
1592 status = ipg_r16(INT_STATUS_ACK);
1593
1594 IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1595
1596 /* Shared IRQ of remove event. */
1597 if (!(status & IPG_IS_RSVD_MASK))
1598 goto out_enable;
1599
1600 handled = 1;
1601
1602 if (unlikely(!netif_running(dev)))
227bc24d 1603 goto out_unlock;
1202d6ff
FR		 1604
1605 /* If RFDListEnd interrupt, restore all used RFDs. */
1606 if (status & IPG_IS_RFD_LIST_END) {
1607 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1608
1609 /* The RFD list end indicates an RFD was encountered
1610 * with a 0 NextPtr, or with an RFDDone bit set to 1
1611 * (indicating the RFD is not read for use by the
1612 * IPG.) Try to restore all RFDs.
1613 */
1614 ipg_nic_rxrestore(dev);
1615
1616#ifdef IPG_DEBUG
1617 /* Increment the RFDlistendCount counter. */
1618 sp->RFDlistendCount++;
1619#endif
1620 }
1621
1622 /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1623 * IntRequested interrupt, process received frames. */
1624 if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1625 (status & IPG_IS_RFD_LIST_END) ||
1626 (status & IPG_IS_RX_DMA_COMPLETE) ||
1627 (status & IPG_IS_INT_REQUESTED)) {
1628#ifdef IPG_DEBUG
1629 /* Increment the RFD list checked counter if interrupted
1630 * only to check the RFD list. */
1631 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1632 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1633 (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1634 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1635 IPG_IS_UPDATE_STATS)))
1636 sp->RFDListCheckedCount++;
1637#endif
1638
024f4d88
PE		 1639 if (sp->is_jumbo)
1640 ipg_nic_rx_jumbo(dev);
1641 else
1642 ipg_nic_rx(dev);
1202d6ff
FR		 1643 }
1644
1645 /* If TxDMAComplete interrupt, free used TFDs. */
1646 if (status & IPG_IS_TX_DMA_COMPLETE)
1647 ipg_nic_txfree(dev);
1648
1649 /* TxComplete interrupts indicate one of numerous actions.
1650 * Determine what action to take based on TXSTATUS register.
1651 */
1652 if (status & IPG_IS_TX_COMPLETE)
1653 ipg_nic_txcleanup(dev);
1654
1655 /* If UpdateStats interrupt, update Linux Ethernet statistics */
1656 if (status & IPG_IS_UPDATE_STATS)
1657 ipg_nic_get_stats(dev);
1658
1659 /* If HostError interrupt, reset IPG. */
1660 if (status & IPG_IS_HOST_ERROR) {
1661 IPG_DDEBUG_MSG("HostError Interrupt\n");
1662
1663 schedule_delayed_work(&sp->task, 0);
1664 }
1665
1666 /* If LinkEvent interrupt, resolve autonegotiation. */
1667 if (status & IPG_IS_LINK_EVENT) {
1668 if (ipg_config_autoneg(dev) < 0)
1669 printk(KERN_INFO "%s: Auto-negotiation error.\n",
1670 dev->name);
1671 }
1672
1673 /* If MACCtrlFrame interrupt, do nothing. */
1674 if (status & IPG_IS_MAC_CTRL_FRAME)
1675 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1676
1677 /* If RxComplete interrupt, do nothing. */
1678 if (status & IPG_IS_RX_COMPLETE)
1679 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1680
1681 /* If RxEarly interrupt, do nothing. */
1682 if (status & IPG_IS_RX_EARLY)
1683 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1684
1685out_enable:
1686 /* Re-enable IPG interrupts. */
1687 ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1688 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1689 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
227bc24d 1690out_unlock:
1202d6ff 1691 spin_unlock(&sp->lock);
227bc24d 1692
1202d6ff
FR		 1693 return IRQ_RETVAL(handled);
1694}
1695
1696static void ipg_rx_clear(struct ipg_nic_private *sp)
1697{
1698 unsigned int i;
1699
1700 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
9893ba16 1701 if (sp->rx_buff[i]) {
1202d6ff
FR		 1702 struct ipg_rx *rxfd = sp->rxd + i;
1703
9893ba16
PE		 1704 dev_kfree_skb_irq(sp->rx_buff[i]);
1705 sp->rx_buff[i] = NULL;
1202d6ff 1706 pci_unmap_single(sp->pdev,
325a8071 1707 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1202d6ff
FR		 1708 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1709 }
1710 }
1711}
1712
1713static void ipg_tx_clear(struct ipg_nic_private *sp)
1714{
1715 unsigned int i;
1716
1717 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
9893ba16 1718 if (sp->tx_buff[i]) {
1202d6ff
FR		 1719 struct ipg_tx *txfd = sp->txd + i;
1720
1721 pci_unmap_single(sp->pdev,
325a8071 1722 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
9893ba16 1723 sp->tx_buff[i]->len, PCI_DMA_TODEVICE);
1202d6ff 1724
9893ba16 1725 dev_kfree_skb_irq(sp->tx_buff[i]);
1202d6ff 1726
9893ba16 1727 sp->tx_buff[i] = NULL;
1202d6ff
FR		 1728 }
1729 }
1730}
1731
1732static int ipg_nic_open(struct net_device *dev)
1733{
1734 struct ipg_nic_private *sp = netdev_priv(dev);
1735 void __iomem *ioaddr = sp->ioaddr;
1736 struct pci_dev *pdev = sp->pdev;
1737 int rc;
1738
1739 IPG_DEBUG_MSG("_nic_open\n");
1740
39f20585 1741 sp->rx_buf_sz = sp->rxsupport_size;
1202d6ff
FR		 1742
1743 /* Check for interrupt line conflicts, and request interrupt
1744 * line for IPG.
1745 *
1746 * IMPORTANT: Disable IPG interrupts prior to registering
1747 * IRQ.
1748 */
1749 ipg_w16(0x0000, INT_ENABLE);
1750
1751 /* Register the interrupt line to be used by the IPG within
1752 * the Linux system.
1753 */
90145c9c 1754 rc = request_irq(pdev->irq, ipg_interrupt_handler, IRQF_SHARED,
1202d6ff
FR		 1755 dev->name, dev);
1756 if (rc < 0) {
1757 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1758 dev->name);
1759 goto out;
1760 }
1761
1762 dev->irq = pdev->irq;
1763
1764 rc = -ENOMEM;
1765
1766 sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1767 &sp->rxd_map, GFP_KERNEL);
1768 if (!sp->rxd)
1769 goto err_free_irq_0;
1770
1771 sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1772 &sp->txd_map, GFP_KERNEL);
1773 if (!sp->txd)
1774 goto err_free_rx_1;
1775
1776 rc = init_rfdlist(dev);
1777 if (rc < 0) {
1778 printk(KERN_INFO "%s: Error during configuration.\n",
1779 dev->name);
1780 goto err_free_tx_2;
1781 }
1782
1783 init_tfdlist(dev);
1784
1785 rc = ipg_io_config(dev);
1786 if (rc < 0) {
1787 printk(KERN_INFO "%s: Error during configuration.\n",
1788 dev->name);
1789 goto err_release_tfdlist_3;
1790 }
1791
1792 /* Resolve autonegotiation. */
1793 if (ipg_config_autoneg(dev) < 0)
1794 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1795
1202d6ff 1796 /* initialize JUMBO Frame control variable */
9893ba16
PE		 1797 sp->jumbo.found_start = 0;
1798 sp->jumbo.current_size = 0;
e8399fed 1799 sp->jumbo.skb = NULL;
83042955 1800
1202d6ff
FR		 1801 /* Enable transmit and receive operation of the IPG. */
1802 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1803 IPG_MC_RSVD_MASK, MAC_CTRL);
1804
1805 netif_start_queue(dev);
1806out:
1807 return rc;
1808
1809err_release_tfdlist_3:
1810 ipg_tx_clear(sp);
1811 ipg_rx_clear(sp);
1812err_free_tx_2:
1813 dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1814err_free_rx_1:
1815 dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1816err_free_irq_0:
1817 free_irq(pdev->irq, dev);
1818 goto out;
1819}
1820
1821static int ipg_nic_stop(struct net_device *dev)
1822{
1823 struct ipg_nic_private *sp = netdev_priv(dev);
1824 void __iomem *ioaddr = sp->ioaddr;
1825 struct pci_dev *pdev = sp->pdev;
1826
1827 IPG_DEBUG_MSG("_nic_stop\n");
1828
1829 netif_stop_queue(dev);
1830
1831 IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1832 IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1833 IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1834 IPG_DUMPTFDLIST(dev);
1835
1836 do {
1837 (void) ipg_r16(INT_STATUS_ACK);
1838
1839 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1840
1841 synchronize_irq(pdev->irq);
1842 } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1843
1844 ipg_rx_clear(sp);
1845
1846 ipg_tx_clear(sp);
1847
1848 pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1849 pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1850
1851 free_irq(pdev->irq, dev);
1852
1853 return 0;
1854}
1855
61357325
SH		 1856static netdev_tx_t ipg_nic_hard_start_xmit(struct sk_buff *skb,
1857 struct net_device *dev)
1202d6ff
FR		 1858{
1859 struct ipg_nic_private *sp = netdev_priv(dev);
1860 void __iomem *ioaddr = sp->ioaddr;
1861 unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1862 unsigned long flags;
1863 struct ipg_tx *txfd;
1864
1865 IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1866
1867 /* If in 10Mbps mode, stop the transmit queue so
1868 * no more transmit frames are accepted.
1869 */
1870 if (sp->tenmbpsmode)
1871 netif_stop_queue(dev);
1872
9893ba16
PE		 1873 if (sp->reset_current_tfd) {
1874 sp->reset_current_tfd = 0;
1202d6ff
FR		 1875 entry = 0;
1876 }
1877
1878 txfd = sp->txd + entry;
1879
9893ba16 1880 sp->tx_buff[entry] = skb;
1202d6ff
FR		 1881
1882 /* Clear all TFC fields, except TFDDONE. */
1883 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1884
1885 /* Specify the TFC field within the TFD. */
1886 txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
48f5fec5 1887 (IPG_TFC_FRAMEID & sp->tx_current) |
1202d6ff 1888 (IPG_TFC_FRAGCOUNT & (1 << 24)));
48f5fec5
AV		 1889 /*
1890 * 16--17 (WordAlign) <- 3 (disable),
1891 * 0--15 (FrameId) <- sp->tx_current,
1892 * 24--27 (FragCount) <- 1
1893 */
1202d6ff
FR		 1894
1895 /* Request TxComplete interrupts at an interval defined
1896 * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1897 * Request TxComplete interrupt for every frame
1898 * if in 10Mbps mode to accomodate problem with 10Mbps
1899 * processing.
1900 */
1901 if (sp->tenmbpsmode)
1902 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
47cccd7d 1903 txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1202d6ff
FR		 1904 /* Based on compilation option, determine if FCS is to be
1905 * appended to transmit frame by IPG.
1906 */
1907 if (!(IPG_APPEND_FCS_ON_TX))
1908 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1909
1910 /* Based on compilation option, determine if IP, TCP and/or
1911 * UDP checksums are to be added to transmit frame by IPG.
1912 */
1913 if (IPG_ADD_IPCHECKSUM_ON_TX)
1914 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1915
1916 if (IPG_ADD_TCPCHECKSUM_ON_TX)
1917 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1918
1919 if (IPG_ADD_UDPCHECKSUM_ON_TX)
1920 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1921
1922 /* Based on compilation option, determine if VLAN tag info is to be
1923 * inserted into transmit frame by IPG.
1924 */
1925 if (IPG_INSERT_MANUAL_VLAN_TAG) {
1926 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1927 ((u64) IPG_MANUAL_VLAN_VID << 32) |
1928 ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1929 ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1930 }
1931
1932 /* The fragment start location within system memory is defined
1933 * by the sk_buff structure's data field. The physical address
1934 * of this location within the system's virtual memory space
1935 * is determined using the IPG_HOST2BUS_MAP function.
1936 */
1937 txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1938 skb->len, PCI_DMA_TODEVICE));
1939
1940 /* The length of the fragment within system memory is defined by
1941 * the sk_buff structure's len field.
1942 */
1943 txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1944 ((u64) (skb->len & 0xffff) << 48));
1945
1946 /* Clear the TFDDone bit last to indicate the TFD is ready
1947 * for transfer to the IPG.
1948 */
1949 txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1950
1951 spin_lock_irqsave(&sp->lock, flags);
1952
1953 sp->tx_current++;
1954
1955 mmiowb();
1956
1957 ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1958
1959 if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
dafdec74 1960 netif_stop_queue(dev);
1202d6ff
FR		 1961
1962 spin_unlock_irqrestore(&sp->lock, flags);
1963
1964 return NETDEV_TX_OK;
1965}
1966
1967static void ipg_set_phy_default_param(unsigned char rev,
1968 struct net_device *dev, int phy_address)
1969{
1970 unsigned short length;
1971 unsigned char revision;
1972 unsigned short *phy_param;
1973 unsigned short address, value;
1974
1975 phy_param = &DefaultPhyParam[0];
1976 length = *phy_param & 0x00FF;
1977 revision = (unsigned char)((*phy_param) >> 8);
1978 phy_param++;
1979 while (length != 0) {
1980 if (rev == revision) {
1981 while (length > 1) {
1982 address = *phy_param;
1983 value = *(phy_param + 1);
1984 phy_param += 2;
1985 mdio_write(dev, phy_address, address, value);
1986 length -= 4;
1987 }
1988 break;
1989 } else {
1990 phy_param += length / 2;
1991 length = *phy_param & 0x00FF;
1992 revision = (unsigned char)((*phy_param) >> 8);
1993 phy_param++;
1994 }
1995 }
1996}
1997
1202d6ff
FR		 1998static int read_eeprom(struct net_device *dev, int eep_addr)
1999{
2000 void __iomem *ioaddr = ipg_ioaddr(dev);
2001 unsigned int i;
2002 int ret = 0;
2003 u16 value;
2004
2005 value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2006 ipg_w16(value, EEPROM_CTRL);
2007
2008 for (i = 0; i < 1000; i++) {
2009 u16 data;
2010
2011 mdelay(10);
2012 data = ipg_r16(EEPROM_CTRL);
2013 if (!(data & IPG_EC_EEPROM_BUSY)) {
2014 ret = ipg_r16(EEPROM_DATA);
2015 break;
2016 }
2017 }
2018 return ret;
2019}
2020
2021static void ipg_init_mii(struct net_device *dev)
2022{
2023 struct ipg_nic_private *sp = netdev_priv(dev);
2024 struct mii_if_info *mii_if = &sp->mii_if;
2025 int phyaddr;
2026
2027 mii_if->dev = dev;
2028 mii_if->mdio_read = mdio_read;
2029 mii_if->mdio_write = mdio_write;
2030 mii_if->phy_id_mask = 0x1f;
2031 mii_if->reg_num_mask = 0x1f;
2032
2033 mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2034
2035 if (phyaddr != 0x1f) {
2036 u16 mii_phyctrl, mii_1000cr;
2037 u8 revisionid = 0;
2038
2039 mii_1000cr = mdio_read(dev, phyaddr, MII_CTRL1000);
2040 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2041 GMII_PHY_1000BASETCONTROL_PreferMaster;
2042 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2043
2044 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2045
2046 /* Set default phyparam */
2047 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2048 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2049
2050 /* Reset PHY */
2051 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2052 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2053
2054 }
2055}
2056
2057static int ipg_hw_init(struct net_device *dev)
2058{
2059 struct ipg_nic_private *sp = netdev_priv(dev);
2060 void __iomem *ioaddr = sp->ioaddr;
2061 unsigned int i;
2062 int rc;
2063
dea4a87c 2064 /* Read/Write and Reset EEPROM Value */
1202d6ff 2065 /* Read LED Mode Configuration from EEPROM */
9893ba16 2066 sp->led_mode = read_eeprom(dev, 6);
1202d6ff
FR		 2067
2068 /* Reset all functions within the IPG. Do not assert
2069 * RST_OUT as not compatible with some PHYs.
2070 */
2071 rc = ipg_reset(dev, IPG_RESET_MASK);
2072 if (rc < 0)
2073 goto out;
2074
2075 ipg_init_mii(dev);
2076
2077 /* Read MAC Address from EEPROM */
2078 for (i = 0; i < 3; i++)
2079 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2080
2081 for (i = 0; i < 3; i++)
2082 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2083
2084 /* Set station address in ethernet_device structure. */
2085 dev->dev_addr[0] = ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2086 dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2087 dev->dev_addr[2] = ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2088 dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2089 dev->dev_addr[4] = ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2090 dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2091out:
2092 return rc;
2093}
2094
2095static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2096{
2097 struct ipg_nic_private *sp = netdev_priv(dev);
2098 int rc;
2099
2100 mutex_lock(&sp->mii_mutex);
2101 rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2102 mutex_unlock(&sp->mii_mutex);
2103
2104 return rc;
2105}
2106
2107static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2108{
da02b231 2109 struct ipg_nic_private *sp = netdev_priv(dev);
532f4aee 2110 int err;
da02b231 2111
1202d6ff
FR		 2112 /* Function to accomodate changes to Maximum Transfer Unit
2113 * (or MTU) of IPG NIC. Cannot use default function since
2114 * the default will not allow for MTU > 1500 bytes.
2115 */
2116
2117 IPG_DEBUG_MSG("_nic_change_mtu\n");
2118
532f4aee
PE		 2119 /*
2120 * Check that the new MTU value is between 68 (14 byte header, 46 byte
2121 * payload, 4 byte FCS) and 10 KB, which is the largest supported MTU.
1202d6ff 2122 */
532f4aee 2123 if (new_mtu < 68 || new_mtu > 10240)
1202d6ff
FR		 2124 return -EINVAL;
2125
532f4aee
PE		 2126 err = ipg_nic_stop(dev);
2127 if (err)
2128 return err;
2129
1202d6ff
FR		 2130 dev->mtu = new_mtu;
2131
532f4aee
PE		 2132 sp->max_rxframe_size = new_mtu;
2133
2134 sp->rxfrag_size = new_mtu;
2135 if (sp->rxfrag_size > 4088)
2136 sp->rxfrag_size = 4088;
2137
2138 sp->rxsupport_size = sp->max_rxframe_size;
2139
2140 if (new_mtu > 0x0600)
2141 sp->is_jumbo = true;
2142 else
2143 sp->is_jumbo = false;
2144
2145 return ipg_nic_open(dev);
1202d6ff
FR		 2146}
2147
2148static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2149{
2150 struct ipg_nic_private *sp = netdev_priv(dev);
2151 int rc;
2152
2153 mutex_lock(&sp->mii_mutex);
2154 rc = mii_ethtool_gset(&sp->mii_if, cmd);
2155 mutex_unlock(&sp->mii_mutex);
2156
2157 return rc;
2158}
2159
2160static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2161{
2162 struct ipg_nic_private *sp = netdev_priv(dev);
2163 int rc;
2164
2165 mutex_lock(&sp->mii_mutex);
2166 rc = mii_ethtool_sset(&sp->mii_if, cmd);
2167 mutex_unlock(&sp->mii_mutex);
2168
2169 return rc;
2170}
2171
2172static int ipg_nway_reset(struct net_device *dev)
2173{
2174 struct ipg_nic_private *sp = netdev_priv(dev);
2175 int rc;
2176
2177 mutex_lock(&sp->mii_mutex);
2178 rc = mii_nway_restart(&sp->mii_if);
2179 mutex_unlock(&sp->mii_mutex);
2180
2181 return rc;
2182}
2183
0fc0b732 2184static const struct ethtool_ops ipg_ethtool_ops = {
1202d6ff
FR		 2185 .get_settings = ipg_get_settings,
2186 .set_settings = ipg_set_settings,
2187 .nway_reset = ipg_nway_reset,
2188};
2189
ef312246 2190static void __devexit ipg_remove(struct pci_dev *pdev)
1202d6ff
FR		 2191{
2192 struct net_device *dev = pci_get_drvdata(pdev);
2193 struct ipg_nic_private *sp = netdev_priv(dev);
2194
2195 IPG_DEBUG_MSG("_remove\n");
2196
2197 /* Un-register Ethernet device. */
2198 unregister_netdev(dev);
2199
2200 pci_iounmap(pdev, sp->ioaddr);
2201
2202 pci_release_regions(pdev);
2203
2204 free_netdev(dev);
2205 pci_disable_device(pdev);
2206 pci_set_drvdata(pdev, NULL);
2207}
2208
04fb5f73
SH		 2209static const struct net_device_ops ipg_netdev_ops = {
2210 .ndo_open = ipg_nic_open,
2211 .ndo_stop = ipg_nic_stop,
2212 .ndo_start_xmit = ipg_nic_hard_start_xmit,
2213 .ndo_get_stats = ipg_nic_get_stats,
2214 .ndo_set_multicast_list = ipg_nic_set_multicast_list,
2215 .ndo_do_ioctl = ipg_ioctl,
2216 .ndo_tx_timeout = ipg_tx_timeout,
2217 .ndo_change_mtu = ipg_nic_change_mtu,
2218 .ndo_set_mac_address = eth_mac_addr,
2219 .ndo_validate_addr = eth_validate_addr,
2220};
2221
1202d6ff
FR		 2222static int __devinit ipg_probe(struct pci_dev *pdev,
2223 const struct pci_device_id *id)
2224{
2225 unsigned int i = id->driver_data;
2226 struct ipg_nic_private *sp;
2227 struct net_device *dev;
2228 void __iomem *ioaddr;
2229 int rc;
2230
2231 rc = pci_enable_device(pdev);
2232 if (rc < 0)
2233 goto out;
2234
2235 printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2236
2237 pci_set_master(pdev);
2238
50cf156a 2239 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
1202d6ff 2240 if (rc < 0) {
284901a9 2241 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1202d6ff
FR		 2242 if (rc < 0) {
2243 printk(KERN_ERR "%s: DMA config failed.\n",
2244 pci_name(pdev));
2245 goto err_disable_0;
2246 }
2247 }
2248
2249 /*
2250 * Initialize net device.
2251 */
2252 dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2253 if (!dev) {
2254 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2255 rc = -ENOMEM;
2256 goto err_disable_0;
2257 }
2258
2259 sp = netdev_priv(dev);
2260 spin_lock_init(&sp->lock);
2261 mutex_init(&sp->mii_mutex);
2262
532f4aee 2263 sp->is_jumbo = IPG_IS_JUMBO;
18a9cdb9 2264 sp->rxfrag_size = IPG_RXFRAG_SIZE;
39f20585 2265 sp->rxsupport_size = IPG_RXSUPPORT_SIZE;
da02b231 2266 sp->max_rxframe_size = IPG_MAX_RXFRAME_SIZE;
024f4d88 2267
1202d6ff
FR		 2268 /* Declare IPG NIC functions for Ethernet device methods.
2269 */
04fb5f73 2270 dev->netdev_ops = &ipg_netdev_ops;
1202d6ff
FR		 2271 SET_NETDEV_DEV(dev, &pdev->dev);
2272 SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2273
2274 rc = pci_request_regions(pdev, DRV_NAME);
2275 if (rc)
2276 goto err_free_dev_1;
2277
2278 ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2279 if (!ioaddr) {
2280 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2281 rc = -EIO;
2282 goto err_release_regions_2;
2283 }
2284
2285 /* Save the pointer to the PCI device information. */
2286 sp->ioaddr = ioaddr;
2287 sp->pdev = pdev;
2288 sp->dev = dev;
2289
2290 INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2291
2292 pci_set_drvdata(pdev, dev);
2293
2294 rc = ipg_hw_init(dev);
2295 if (rc < 0)
2296 goto err_unmap_3;
2297
2298 rc = register_netdev(dev);
2299 if (rc < 0)
2300 goto err_unmap_3;
2301
2302 printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2303out:
2304 return rc;
2305
2306err_unmap_3:
2307 pci_iounmap(pdev, ioaddr);
2308err_release_regions_2:
2309 pci_release_regions(pdev);
2310err_free_dev_1:
2311 free_netdev(dev);
2312err_disable_0:
2313 pci_disable_device(pdev);
2314 goto out;
2315}
2316
2317static struct pci_driver ipg_pci_driver = {
2318 .name = IPG_DRIVER_NAME,
2319 .id_table = ipg_pci_tbl,
2320 .probe = ipg_probe,
2321 .remove = __devexit_p(ipg_remove),
2322};
2323
2324static int __init ipg_init_module(void)
2325{
2326 return pci_register_driver(&ipg_pci_driver);
2327}
2328
2329static void __exit ipg_exit_module(void)
2330{
2331 pci_unregister_driver(&ipg_pci_driver);
2332}
2333
2334module_init(ipg_init_module);
2335module_exit(ipg_exit_module);
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