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igb: add support for set_rx_mode netdevice operation
[net-next-2.6.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
2d064c06
AD		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
73 /* required last entry */
74 {0, }
75};
76
77MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
78
79void igb_reset(struct igb_adapter *);
80static int igb_setup_all_tx_resources(struct igb_adapter *);
81static int igb_setup_all_rx_resources(struct igb_adapter *);
82static void igb_free_all_tx_resources(struct igb_adapter *);
83static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 84void igb_update_stats(struct igb_adapter *);
85static int igb_probe(struct pci_dev *, const struct pci_device_id *);
86static void __devexit igb_remove(struct pci_dev *pdev);
87static int igb_sw_init(struct igb_adapter *);
88static int igb_open(struct net_device *);
89static int igb_close(struct net_device *);
90static void igb_configure_tx(struct igb_adapter *);
91static void igb_configure_rx(struct igb_adapter *);
92static void igb_setup_rctl(struct igb_adapter *);
93static void igb_clean_all_tx_rings(struct igb_adapter *);
94static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 95static void igb_clean_tx_ring(struct igb_ring *);
96static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 97static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 98static void igb_update_phy_info(unsigned long);
99static void igb_watchdog(unsigned long);
100static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 101static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
102 struct net_device *,
103 struct igb_ring *);
104static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
105 struct net_device *);
9d5c8243
AK		 106static struct net_device_stats *igb_get_stats(struct net_device *);
107static int igb_change_mtu(struct net_device *, int);
108static int igb_set_mac(struct net_device *, void *);
109static irqreturn_t igb_intr(int irq, void *);
110static irqreturn_t igb_intr_msi(int irq, void *);
111static irqreturn_t igb_msix_other(int irq, void *);
112static irqreturn_t igb_msix_rx(int irq, void *);
113static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 114#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 115static void igb_update_rx_dca(struct igb_ring *);
116static void igb_update_tx_dca(struct igb_ring *);
117static void igb_setup_dca(struct igb_adapter *);
421e02f0 118#endif /* CONFIG_IGB_DCA */
3b644cf6 119static bool igb_clean_tx_irq(struct igb_ring *);
661086df 120static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 121static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
122static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 123static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
124static void igb_tx_timeout(struct net_device *);
125static void igb_reset_task(struct work_struct *);
126static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
127static void igb_vlan_rx_add_vid(struct net_device *, u16);
128static void igb_vlan_rx_kill_vid(struct net_device *, u16);
129static void igb_restore_vlan(struct igb_adapter *);
4ae196df
AD		 130static void igb_ping_all_vfs(struct igb_adapter *);
131static void igb_msg_task(struct igb_adapter *);
132static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
28fc06f5 133static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
4ae196df 134static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 135static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 137
c8159b2d
ED		 138static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
139{
140 u32 reg_data;
141
142 reg_data = rd32(E1000_VMOLR(vfn));
143 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
144 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
145 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
146 E1000_VMOLR_AUPE | /* Accept untagged packets */
147 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
148 wr32(E1000_VMOLR(vfn), reg_data);
149}
150
151static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
152 int vfn)
153{
154 struct e1000_hw *hw = &adapter->hw;
155 u32 vmolr;
156
157 vmolr = rd32(E1000_VMOLR(vfn));
158 vmolr &= ~E1000_VMOLR_RLPML_MASK;
159 vmolr |= size | E1000_VMOLR_LPE;
160 wr32(E1000_VMOLR(vfn), vmolr);
161
162 return 0;
163}
164
165static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
166{
167 u32 reg_data;
168
169 reg_data = rd32(E1000_RAH(entry));
170 reg_data &= ~E1000_RAH_POOL_MASK;
171 reg_data |= E1000_RAH_POOL_1 << pool;;
172 wr32(E1000_RAH(entry), reg_data);
173}
174
9d5c8243 175#ifdef CONFIG_PM
3fe7c4c9 176static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 177static int igb_resume(struct pci_dev *);
178#endif
179static void igb_shutdown(struct pci_dev *);
421e02f0 180#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 181static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
182static struct notifier_block dca_notifier = {
183 .notifier_call = igb_notify_dca,
184 .next = NULL,
185 .priority = 0
186};
187#endif
9d5c8243
AK		 188#ifdef CONFIG_NET_POLL_CONTROLLER
189/* for netdump / net console */
190static void igb_netpoll(struct net_device *);
191#endif
37680117 192#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 193static unsigned int max_vfs = 0;
194module_param(max_vfs, uint, 0);
195MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
196 "per physical function");
197#endif /* CONFIG_PCI_IOV */
198
9d5c8243
AK		 199static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
200 pci_channel_state_t);
201static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
202static void igb_io_resume(struct pci_dev *);
203
204static struct pci_error_handlers igb_err_handler = {
205 .error_detected = igb_io_error_detected,
206 .slot_reset = igb_io_slot_reset,
207 .resume = igb_io_resume,
208};
209
210
211static struct pci_driver igb_driver = {
212 .name = igb_driver_name,
213 .id_table = igb_pci_tbl,
214 .probe = igb_probe,
215 .remove = __devexit_p(igb_remove),
216#ifdef CONFIG_PM
217 /* Power Managment Hooks */
218 .suspend = igb_suspend,
219 .resume = igb_resume,
220#endif
221 .shutdown = igb_shutdown,
222 .err_handler = &igb_err_handler
223};
224
7dfc16fa
AD		 225static int global_quad_port_a; /* global quad port a indication */
226
9d5c8243
AK		 227MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
228MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
229MODULE_LICENSE("GPL");
230MODULE_VERSION(DRV_VERSION);
231
38c845c7
PO		 232/**
233 * Scale the NIC clock cycle by a large factor so that
234 * relatively small clock corrections can be added or
235 * substracted at each clock tick. The drawbacks of a
236 * large factor are a) that the clock register overflows
237 * more quickly (not such a big deal) and b) that the
238 * increment per tick has to fit into 24 bits.
239 *
240 * Note that
241 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
242 * IGB_TSYNC_SCALE
243 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
244 *
245 * The base scale factor is intentionally a power of two
246 * so that the division in %struct timecounter can be done with
247 * a shift.
248 */
249#define IGB_TSYNC_SHIFT (19)
250#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
251
252/**
253 * The duration of one clock cycle of the NIC.
254 *
255 * @todo This hard-coded value is part of the specification and might change
256 * in future hardware revisions. Add revision check.
257 */
258#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
259
260#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
261# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
262#endif
263
264/**
265 * igb_read_clock - read raw cycle counter (to be used by time counter)
266 */
267static cycle_t igb_read_clock(const struct cyclecounter *tc)
268{
269 struct igb_adapter *adapter =
270 container_of(tc, struct igb_adapter, cycles);
271 struct e1000_hw *hw = &adapter->hw;
272 u64 stamp;
273
274 stamp = rd32(E1000_SYSTIML);
275 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
276
277 return stamp;
278}
279
9d5c8243
AK		 280#ifdef DEBUG
281/**
282 * igb_get_hw_dev_name - return device name string
283 * used by hardware layer to print debugging information
284 **/
285char *igb_get_hw_dev_name(struct e1000_hw *hw)
286{
287 struct igb_adapter *adapter = hw->back;
288 return adapter->netdev->name;
289}
38c845c7
PO		 290
291/**
292 * igb_get_time_str - format current NIC and system time as string
293 */
294static char *igb_get_time_str(struct igb_adapter *adapter,
295 char buffer[160])
296{
297 cycle_t hw = adapter->cycles.read(&adapter->cycles);
298 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
299 struct timespec sys;
300 struct timespec delta;
301 getnstimeofday(&sys);
302
303 delta = timespec_sub(nic, sys);
304
305 sprintf(buffer,
33af6bcc
PO		 306 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
307 hw,
38c845c7
PO		 308 (long)nic.tv_sec, nic.tv_nsec,
309 (long)sys.tv_sec, sys.tv_nsec,
310 (long)delta.tv_sec, delta.tv_nsec);
311
312 return buffer;
313}
9d5c8243
AK		 314#endif
315
c493ea45
AD		 316/**
317 * igb_desc_unused - calculate if we have unused descriptors
318 **/
319static int igb_desc_unused(struct igb_ring *ring)
320{
321 if (ring->next_to_clean > ring->next_to_use)
322 return ring->next_to_clean - ring->next_to_use - 1;
323
324 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
325}
326
9d5c8243
AK		 327/**
328 * igb_init_module - Driver Registration Routine
329 *
330 * igb_init_module is the first routine called when the driver is
331 * loaded. All it does is register with the PCI subsystem.
332 **/
333static int __init igb_init_module(void)
334{
335 int ret;
336 printk(KERN_INFO "%s - version %s\n",
337 igb_driver_string, igb_driver_version);
338
339 printk(KERN_INFO "%s\n", igb_copyright);
340
7dfc16fa
AD		 341 global_quad_port_a = 0;
342
421e02f0 343#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 344 dca_register_notify(&dca_notifier);
345#endif
bbd98fe4
AD		 346
347 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 348 return ret;
349}
350
351module_init(igb_init_module);
352
353/**
354 * igb_exit_module - Driver Exit Cleanup Routine
355 *
356 * igb_exit_module is called just before the driver is removed
357 * from memory.
358 **/
359static void __exit igb_exit_module(void)
360{
421e02f0 361#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 362 dca_unregister_notify(&dca_notifier);
363#endif
9d5c8243
AK		 364 pci_unregister_driver(&igb_driver);
365}
366
367module_exit(igb_exit_module);
368
26bc19ec
AD		 369#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
370/**
371 * igb_cache_ring_register - Descriptor ring to register mapping
372 * @adapter: board private structure to initialize
373 *
374 * Once we know the feature-set enabled for the device, we'll cache
375 * the register offset the descriptor ring is assigned to.
376 **/
377static void igb_cache_ring_register(struct igb_adapter *adapter)
378{
379 int i;
1bfaf07b 380 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 381
382 switch (adapter->hw.mac.type) {
383 case e1000_82576:
384 /* The queues are allocated for virtualization such that VF 0
385 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
386 * In order to avoid collision we start at the first free queue
387 * and continue consuming queues in the same sequence
388 */
389 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 390 adapter->rx_ring[i].reg_idx = rbase_offset +
391 Q_IDX_82576(i);
26bc19ec 392 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 393 adapter->tx_ring[i].reg_idx = rbase_offset +
394 Q_IDX_82576(i);
26bc19ec
AD		 395 break;
396 case e1000_82575:
397 default:
398 for (i = 0; i < adapter->num_rx_queues; i++)
399 adapter->rx_ring[i].reg_idx = i;
400 for (i = 0; i < adapter->num_tx_queues; i++)
401 adapter->tx_ring[i].reg_idx = i;
402 break;
403 }
404}
405
9d5c8243
AK		 406/**
407 * igb_alloc_queues - Allocate memory for all rings
408 * @adapter: board private structure to initialize
409 *
410 * We allocate one ring per queue at run-time since we don't know the
411 * number of queues at compile-time.
412 **/
413static int igb_alloc_queues(struct igb_adapter *adapter)
414{
415 int i;
416
417 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
418 sizeof(struct igb_ring), GFP_KERNEL);
419 if (!adapter->tx_ring)
420 return -ENOMEM;
421
422 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
423 sizeof(struct igb_ring), GFP_KERNEL);
424 if (!adapter->rx_ring) {
425 kfree(adapter->tx_ring);
426 return -ENOMEM;
427 }
428
6eb5a7f1
AD		 429 adapter->rx_ring->buddy = adapter->tx_ring;
430
661086df
PWJ		 431 for (i = 0; i < adapter->num_tx_queues; i++) {
432 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 433 ring->count = adapter->tx_ring_count;
661086df
PWJ		 434 ring->adapter = adapter;
435 ring->queue_index = i;
436 }
9d5c8243
AK		 437 for (i = 0; i < adapter->num_rx_queues; i++) {
438 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 439 ring->count = adapter->rx_ring_count;
9d5c8243 440 ring->adapter = adapter;
844290e5 441 ring->queue_index = i;
9d5c8243
AK		 442 ring->itr_register = E1000_ITR;
443
844290e5 444 /* set a default napi handler for each rx_ring */
661086df 445 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 446 }
26bc19ec
AD		 447
448 igb_cache_ring_register(adapter);
9d5c8243
AK		 449 return 0;
450}
451
a88f10ec
AD		 452static void igb_free_queues(struct igb_adapter *adapter)
453{
454 int i;
455
456 for (i = 0; i < adapter->num_rx_queues; i++)
457 netif_napi_del(&adapter->rx_ring[i].napi);
458
d1a8c9e1
AD		 459 adapter->num_rx_queues = 0;
460 adapter->num_tx_queues = 0;
461
a88f10ec
AD		 462 kfree(adapter->tx_ring);
463 kfree(adapter->rx_ring);
464}
465
9d5c8243
AK		 466#define IGB_N0_QUEUE -1
467static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
468 int tx_queue, int msix_vector)
469{
470 u32 msixbm = 0;
471 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 472 u32 ivar, index;
473
474 switch (hw->mac.type) {
475 case e1000_82575:
9d5c8243
AK		 476 /* The 82575 assigns vectors using a bitmask, which matches the
477 bitmask for the EICR/EIMS/EIMC registers. To assign one
478 or more queues to a vector, we write the appropriate bits
479 into the MSIXBM register for that vector. */
480 if (rx_queue > IGB_N0_QUEUE) {
481 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
482 adapter->rx_ring[rx_queue].eims_value = msixbm;
483 }
484 if (tx_queue > IGB_N0_QUEUE) {
485 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
486 adapter->tx_ring[tx_queue].eims_value =
487 E1000_EICR_TX_QUEUE0 << tx_queue;
488 }
489 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 490 break;
491 case e1000_82576:
26bc19ec 492 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 493 Each queue has a single entry in the table to which we write
494 a vector number along with a "valid" bit. Sadly, the layout
495 of the table is somewhat counterintuitive. */
496 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 497 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 498 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 499 if (rx_queue & 0x1) {
2d064c06
AD		 500 /* vector goes into third byte of register */
501 ivar = ivar & 0xFF00FFFF;
502 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 503 } else {
504 /* vector goes into low byte of register */
505 ivar = ivar & 0xFFFFFF00;
506 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 507 }
508 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
509 array_wr32(E1000_IVAR0, index, ivar);
510 }
511 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 512 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 513 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 514 if (tx_queue & 0x1) {
2d064c06
AD		 515 /* vector goes into high byte of register */
516 ivar = ivar & 0x00FFFFFF;
517 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 518 } else {
519 /* vector goes into second byte of register */
520 ivar = ivar & 0xFFFF00FF;
521 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 522 }
523 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
524 array_wr32(E1000_IVAR0, index, ivar);
525 }
526 break;
527 default:
528 BUG();
529 break;
530 }
9d5c8243
AK		 531}
532
533/**
534 * igb_configure_msix - Configure MSI-X hardware
535 *
536 * igb_configure_msix sets up the hardware to properly
537 * generate MSI-X interrupts.
538 **/
539static void igb_configure_msix(struct igb_adapter *adapter)
540{
541 u32 tmp;
542 int i, vector = 0;
543 struct e1000_hw *hw = &adapter->hw;
544
545 adapter->eims_enable_mask = 0;
2d064c06
AD		 546 if (hw->mac.type == e1000_82576)
547 /* Turn on MSI-X capability first, or our settings
548 * won't stick. And it will take days to debug. */
549 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 550 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 551 E1000_GPIE_NSICR);
9d5c8243
AK		 552
553 for (i = 0; i < adapter->num_tx_queues; i++) {
554 struct igb_ring *tx_ring = &adapter->tx_ring[i];
555 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
556 adapter->eims_enable_mask |= tx_ring->eims_value;
557 if (tx_ring->itr_val)
6eb5a7f1 558 writel(tx_ring->itr_val,
9d5c8243
AK		 559 hw->hw_addr + tx_ring->itr_register);
560 else
561 writel(1, hw->hw_addr + tx_ring->itr_register);
562 }
563
564 for (i = 0; i < adapter->num_rx_queues; i++) {
565 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 566 rx_ring->buddy = NULL;
9d5c8243
AK		 567 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
568 adapter->eims_enable_mask |= rx_ring->eims_value;
569 if (rx_ring->itr_val)
6eb5a7f1 570 writel(rx_ring->itr_val,
9d5c8243
AK		 571 hw->hw_addr + rx_ring->itr_register);
572 else
573 writel(1, hw->hw_addr + rx_ring->itr_register);
574 }
575
576
577 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 578 switch (hw->mac.type) {
579 case e1000_82575:
9d5c8243
AK		 580 array_wr32(E1000_MSIXBM(0), vector++,
581 E1000_EIMS_OTHER);
582
9d5c8243
AK		 583 tmp = rd32(E1000_CTRL_EXT);
584 /* enable MSI-X PBA support*/
585 tmp |= E1000_CTRL_EXT_PBA_CLR;
586
587 /* Auto-Mask interrupts upon ICR read. */
588 tmp |= E1000_CTRL_EXT_EIAME;
589 tmp |= E1000_CTRL_EXT_IRCA;
590
591 wr32(E1000_CTRL_EXT, tmp);
592 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 593 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 594
2d064c06
AD		 595 break;
596
597 case e1000_82576:
598 tmp = (vector++ | E1000_IVAR_VALID) << 8;
599 wr32(E1000_IVAR_MISC, tmp);
600
601 adapter->eims_enable_mask = (1 << (vector)) - 1;
602 adapter->eims_other = 1 << (vector - 1);
603 break;
604 default:
605 /* do nothing, since nothing else supports MSI-X */
606 break;
607 } /* switch (hw->mac.type) */
9d5c8243
AK		 608 wrfl();
609}
610
611/**
612 * igb_request_msix - Initialize MSI-X interrupts
613 *
614 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
615 * kernel.
616 **/
617static int igb_request_msix(struct igb_adapter *adapter)
618{
619 struct net_device *netdev = adapter->netdev;
620 int i, err = 0, vector = 0;
621
622 vector = 0;
623
624 for (i = 0; i < adapter->num_tx_queues; i++) {
625 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 626 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 627 err = request_irq(adapter->msix_entries[vector].vector,
628 &igb_msix_tx, 0, ring->name,
629 &(adapter->tx_ring[i]));
630 if (err)
631 goto out;
632 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 633 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 634 vector++;
635 }
636 for (i = 0; i < adapter->num_rx_queues; i++) {
637 struct igb_ring *ring = &(adapter->rx_ring[i]);
638 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 639 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 640 else
641 memcpy(ring->name, netdev->name, IFNAMSIZ);
642 err = request_irq(adapter->msix_entries[vector].vector,
643 &igb_msix_rx, 0, ring->name,
644 &(adapter->rx_ring[i]));
645 if (err)
646 goto out;
647 ring->itr_register = E1000_EITR(0) + (vector << 2);
648 ring->itr_val = adapter->itr;
649 vector++;
650 }
651
652 err = request_irq(adapter->msix_entries[vector].vector,
653 &igb_msix_other, 0, netdev->name, netdev);
654 if (err)
655 goto out;
656
9d5c8243
AK		 657 igb_configure_msix(adapter);
658 return 0;
659out:
660 return err;
661}
662
663static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
664{
665 if (adapter->msix_entries) {
666 pci_disable_msix(adapter->pdev);
667 kfree(adapter->msix_entries);
668 adapter->msix_entries = NULL;
7dfc16fa 669 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 670 pci_disable_msi(adapter->pdev);
671 return;
672}
673
674
675/**
676 * igb_set_interrupt_capability - set MSI or MSI-X if supported
677 *
678 * Attempt to configure interrupts using the best available
679 * capabilities of the hardware and kernel.
680 **/
681static void igb_set_interrupt_capability(struct igb_adapter *adapter)
682{
683 int err;
684 int numvecs, i;
685
83b7180d
AD		 686 /* Number of supported queues. */
687 /* Having more queues than CPUs doesn't make sense. */
688 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
689 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
690
9d5c8243
AK		 691 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
692 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
693 GFP_KERNEL);
694 if (!adapter->msix_entries)
695 goto msi_only;
696
697 for (i = 0; i < numvecs; i++)
698 adapter->msix_entries[i].entry = i;
699
700 err = pci_enable_msix(adapter->pdev,
701 adapter->msix_entries,
702 numvecs);
703 if (err == 0)
34a20e89 704 goto out;
9d5c8243
AK		 705
706 igb_reset_interrupt_capability(adapter);
707
708 /* If we can't do MSI-X, try MSI */
709msi_only:
2a3abf6d
AD		 710#ifdef CONFIG_PCI_IOV
711 /* disable SR-IOV for non MSI-X configurations */
712 if (adapter->vf_data) {
713 struct e1000_hw *hw = &adapter->hw;
714 /* disable iov and allow time for transactions to clear */
715 pci_disable_sriov(adapter->pdev);
716 msleep(500);
717
718 kfree(adapter->vf_data);
719 adapter->vf_data = NULL;
720 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
721 msleep(100);
722 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
723 }
724#endif
9d5c8243 725 adapter->num_rx_queues = 1;
661086df 726 adapter->num_tx_queues = 1;
9d5c8243 727 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 728 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 729out:
661086df 730 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 731 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 732 return;
733}
734
735/**
736 * igb_request_irq - initialize interrupts
737 *
738 * Attempts to configure interrupts using the best available
739 * capabilities of the hardware and kernel.
740 **/
741static int igb_request_irq(struct igb_adapter *adapter)
742{
743 struct net_device *netdev = adapter->netdev;
744 struct e1000_hw *hw = &adapter->hw;
745 int err = 0;
746
747 if (adapter->msix_entries) {
748 err = igb_request_msix(adapter);
844290e5 749 if (!err)
9d5c8243 750 goto request_done;
9d5c8243
AK		 751 /* fall back to MSI */
752 igb_reset_interrupt_capability(adapter);
753 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 754 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 755 igb_free_all_tx_resources(adapter);
756 igb_free_all_rx_resources(adapter);
757 adapter->num_rx_queues = 1;
758 igb_alloc_queues(adapter);
844290e5 759 } else {
2d064c06
AD		 760 switch (hw->mac.type) {
761 case e1000_82575:
762 wr32(E1000_MSIXBM(0),
763 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
764 break;
765 case e1000_82576:
766 wr32(E1000_IVAR0, E1000_IVAR_VALID);
767 break;
768 default:
769 break;
770 }
9d5c8243 771 }
844290e5 772
7dfc16fa 773 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 774 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
775 netdev->name, netdev);
776 if (!err)
777 goto request_done;
778 /* fall back to legacy interrupts */
779 igb_reset_interrupt_capability(adapter);
7dfc16fa 780 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 781 }
782
783 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
784 netdev->name, netdev);
785
6cb5e577 786 if (err)
9d5c8243
AK		 787 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
788 err);
9d5c8243
AK		 789
790request_done:
791 return err;
792}
793
794static void igb_free_irq(struct igb_adapter *adapter)
795{
796 struct net_device *netdev = adapter->netdev;
797
798 if (adapter->msix_entries) {
799 int vector = 0, i;
800
801 for (i = 0; i < adapter->num_tx_queues; i++)
802 free_irq(adapter->msix_entries[vector++].vector,
803 &(adapter->tx_ring[i]));
804 for (i = 0; i < adapter->num_rx_queues; i++)
805 free_irq(adapter->msix_entries[vector++].vector,
806 &(adapter->rx_ring[i]));
807
808 free_irq(adapter->msix_entries[vector++].vector, netdev);
809 return;
810 }
811
812 free_irq(adapter->pdev->irq, netdev);
813}
814
815/**
816 * igb_irq_disable - Mask off interrupt generation on the NIC
817 * @adapter: board private structure
818 **/
819static void igb_irq_disable(struct igb_adapter *adapter)
820{
821 struct e1000_hw *hw = &adapter->hw;
822
823 if (adapter->msix_entries) {
844290e5 824 wr32(E1000_EIAM, 0);
9d5c8243
AK		 825 wr32(E1000_EIMC, ~0);
826 wr32(E1000_EIAC, 0);
827 }
844290e5
PW		 828
829 wr32(E1000_IAM, 0);
9d5c8243
AK		 830 wr32(E1000_IMC, ~0);
831 wrfl();
832 synchronize_irq(adapter->pdev->irq);
833}
834
835/**
836 * igb_irq_enable - Enable default interrupt generation settings
837 * @adapter: board private structure
838 **/
839static void igb_irq_enable(struct igb_adapter *adapter)
840{
841 struct e1000_hw *hw = &adapter->hw;
842
843 if (adapter->msix_entries) {
844290e5
PW		 844 wr32(E1000_EIAC, adapter->eims_enable_mask);
845 wr32(E1000_EIAM, adapter->eims_enable_mask);
846 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 847 if (adapter->vfs_allocated_count)
848 wr32(E1000_MBVFIMR, 0xFF);
849 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
850 E1000_IMS_DOUTSYNC));
844290e5
PW		 851 } else {
852 wr32(E1000_IMS, IMS_ENABLE_MASK);
853 wr32(E1000_IAM, IMS_ENABLE_MASK);
854 }
9d5c8243
AK		 855}
856
857static void igb_update_mng_vlan(struct igb_adapter *adapter)
858{
859 struct net_device *netdev = adapter->netdev;
860 u16 vid = adapter->hw.mng_cookie.vlan_id;
861 u16 old_vid = adapter->mng_vlan_id;
862 if (adapter->vlgrp) {
863 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
864 if (adapter->hw.mng_cookie.status &
865 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
866 igb_vlan_rx_add_vid(netdev, vid);
867 adapter->mng_vlan_id = vid;
868 } else
869 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
870
871 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
872 (vid != old_vid) &&
873 !vlan_group_get_device(adapter->vlgrp, old_vid))
874 igb_vlan_rx_kill_vid(netdev, old_vid);
875 } else
876 adapter->mng_vlan_id = vid;
877 }
878}
879
880/**
881 * igb_release_hw_control - release control of the h/w to f/w
882 * @adapter: address of board private structure
883 *
884 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
885 * For ASF and Pass Through versions of f/w this means that the
886 * driver is no longer loaded.
887 *
888 **/
889static void igb_release_hw_control(struct igb_adapter *adapter)
890{
891 struct e1000_hw *hw = &adapter->hw;
892 u32 ctrl_ext;
893
894 /* Let firmware take over control of h/w */
895 ctrl_ext = rd32(E1000_CTRL_EXT);
896 wr32(E1000_CTRL_EXT,
897 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
898}
899
900
901/**
902 * igb_get_hw_control - get control of the h/w from f/w
903 * @adapter: address of board private structure
904 *
905 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
906 * For ASF and Pass Through versions of f/w this means that
907 * the driver is loaded.
908 *
909 **/
910static void igb_get_hw_control(struct igb_adapter *adapter)
911{
912 struct e1000_hw *hw = &adapter->hw;
913 u32 ctrl_ext;
914
915 /* Let firmware know the driver has taken over */
916 ctrl_ext = rd32(E1000_CTRL_EXT);
917 wr32(E1000_CTRL_EXT,
918 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
919}
920
9d5c8243
AK		 921/**
922 * igb_configure - configure the hardware for RX and TX
923 * @adapter: private board structure
924 **/
925static void igb_configure(struct igb_adapter *adapter)
926{
927 struct net_device *netdev = adapter->netdev;
928 int i;
929
930 igb_get_hw_control(adapter);
ff41f8dc 931 igb_set_rx_mode(netdev);
9d5c8243
AK		 932
933 igb_restore_vlan(adapter);
9d5c8243
AK		 934
935 igb_configure_tx(adapter);
936 igb_setup_rctl(adapter);
937 igb_configure_rx(adapter);
662d7205
AD		 938
939 igb_rx_fifo_flush_82575(&adapter->hw);
940
c493ea45 941 /* call igb_desc_unused which always leaves
9d5c8243
AK		 942 * at least 1 descriptor unused to make sure
943 * next_to_use != next_to_clean */
944 for (i = 0; i < adapter->num_rx_queues; i++) {
945 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 946 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 947 }
948
949
950 adapter->tx_queue_len = netdev->tx_queue_len;
951}
952
953
954/**
955 * igb_up - Open the interface and prepare it to handle traffic
956 * @adapter: board private structure
957 **/
958
959int igb_up(struct igb_adapter *adapter)
960{
961 struct e1000_hw *hw = &adapter->hw;
962 int i;
963
964 /* hardware has been reset, we need to reload some things */
965 igb_configure(adapter);
966
967 clear_bit(__IGB_DOWN, &adapter->state);
968
844290e5
PW		 969 for (i = 0; i < adapter->num_rx_queues; i++)
970 napi_enable(&adapter->rx_ring[i].napi);
971 if (adapter->msix_entries)
9d5c8243 972 igb_configure_msix(adapter);
9d5c8243 973
4ae196df 974 igb_vmm_control(adapter);
e1739522
AD		 975 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
976 igb_set_vmolr(hw, adapter->vfs_allocated_count);
977
9d5c8243
AK		 978 /* Clear any pending interrupts. */
979 rd32(E1000_ICR);
980 igb_irq_enable(adapter);
981
4cb9be7a
JB		 982 netif_tx_start_all_queues(adapter->netdev);
983
9d5c8243
AK		 984 /* Fire a link change interrupt to start the watchdog. */
985 wr32(E1000_ICS, E1000_ICS_LSC);
986 return 0;
987}
988
989void igb_down(struct igb_adapter *adapter)
990{
991 struct e1000_hw *hw = &adapter->hw;
992 struct net_device *netdev = adapter->netdev;
993 u32 tctl, rctl;
994 int i;
995
996 /* signal that we're down so the interrupt handler does not
997 * reschedule our watchdog timer */
998 set_bit(__IGB_DOWN, &adapter->state);
999
1000 /* disable receives in the hardware */
1001 rctl = rd32(E1000_RCTL);
1002 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1003 /* flush and sleep below */
1004
fd2ea0a7 1005 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1006
1007 /* disable transmits in the hardware */
1008 tctl = rd32(E1000_TCTL);
1009 tctl &= ~E1000_TCTL_EN;
1010 wr32(E1000_TCTL, tctl);
1011 /* flush both disables and wait for them to finish */
1012 wrfl();
1013 msleep(10);
1014
844290e5
PW		 1015 for (i = 0; i < adapter->num_rx_queues; i++)
1016 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 1017
9d5c8243
AK		 1018 igb_irq_disable(adapter);
1019
1020 del_timer_sync(&adapter->watchdog_timer);
1021 del_timer_sync(&adapter->phy_info_timer);
1022
1023 netdev->tx_queue_len = adapter->tx_queue_len;
1024 netif_carrier_off(netdev);
04fe6358
AD		 1025
1026 /* record the stats before reset*/
1027 igb_update_stats(adapter);
1028
9d5c8243
AK		 1029 adapter->link_speed = 0;
1030 adapter->link_duplex = 0;
1031
3023682e
JK		 1032 if (!pci_channel_offline(adapter->pdev))
1033 igb_reset(adapter);
9d5c8243
AK		 1034 igb_clean_all_tx_rings(adapter);
1035 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1036#ifdef CONFIG_IGB_DCA
1037
1038 /* since we reset the hardware DCA settings were cleared */
1039 igb_setup_dca(adapter);
1040#endif
9d5c8243
AK		 1041}
1042
1043void igb_reinit_locked(struct igb_adapter *adapter)
1044{
1045 WARN_ON(in_interrupt());
1046 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1047 msleep(1);
1048 igb_down(adapter);
1049 igb_up(adapter);
1050 clear_bit(__IGB_RESETTING, &adapter->state);
1051}
1052
1053void igb_reset(struct igb_adapter *adapter)
1054{
1055 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1056 struct e1000_mac_info *mac = &hw->mac;
1057 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1058 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1059 u16 hwm;
1060
1061 /* Repartition Pba for greater than 9k mtu
1062 * To take effect CTRL.RST is required.
1063 */
fa4dfae0
AD		 1064 switch (mac->type) {
1065 case e1000_82576:
2d064c06 1066 pba = E1000_PBA_64K;
fa4dfae0
AD		 1067 break;
1068 case e1000_82575:
1069 default:
1070 pba = E1000_PBA_34K;
1071 break;
2d064c06 1072 }
9d5c8243 1073
2d064c06
AD		 1074 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1075 (mac->type < e1000_82576)) {
9d5c8243
AK		 1076 /* adjust PBA for jumbo frames */
1077 wr32(E1000_PBA, pba);
1078
1079 /* To maintain wire speed transmits, the Tx FIFO should be
1080 * large enough to accommodate two full transmit packets,
1081 * rounded up to the next 1KB and expressed in KB. Likewise,
1082 * the Rx FIFO should be large enough to accommodate at least
1083 * one full receive packet and is similarly rounded up and
1084 * expressed in KB. */
1085 pba = rd32(E1000_PBA);
1086 /* upper 16 bits has Tx packet buffer allocation size in KB */
1087 tx_space = pba >> 16;
1088 /* lower 16 bits has Rx packet buffer allocation size in KB */
1089 pba &= 0xffff;
1090 /* the tx fifo also stores 16 bytes of information about the tx
1091 * but don't include ethernet FCS because hardware appends it */
1092 min_tx_space = (adapter->max_frame_size +
85e8d004 1093 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1094 ETH_FCS_LEN) * 2;
1095 min_tx_space = ALIGN(min_tx_space, 1024);
1096 min_tx_space >>= 10;
1097 /* software strips receive CRC, so leave room for it */
1098 min_rx_space = adapter->max_frame_size;
1099 min_rx_space = ALIGN(min_rx_space, 1024);
1100 min_rx_space >>= 10;
1101
1102 /* If current Tx allocation is less than the min Tx FIFO size,
1103 * and the min Tx FIFO size is less than the current Rx FIFO
1104 * allocation, take space away from current Rx allocation */
1105 if (tx_space < min_tx_space &&
1106 ((min_tx_space - tx_space) < pba)) {
1107 pba = pba - (min_tx_space - tx_space);
1108
1109 /* if short on rx space, rx wins and must trump tx
1110 * adjustment */
1111 if (pba < min_rx_space)
1112 pba = min_rx_space;
1113 }
2d064c06 1114 wr32(E1000_PBA, pba);
9d5c8243 1115 }
9d5c8243
AK		 1116
1117 /* flow control settings */
1118 /* The high water mark must be low enough to fit one full frame
1119 * (or the size used for early receive) above it in the Rx FIFO.
1120 * Set it to the lower of:
1121 * - 90% of the Rx FIFO size, or
1122 * - the full Rx FIFO size minus one full frame */
1123 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1124 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1125
2d064c06
AD		 1126 if (mac->type < e1000_82576) {
1127 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1128 fc->low_water = fc->high_water - 8;
1129 } else {
1130 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1131 fc->low_water = fc->high_water - 16;
1132 }
9d5c8243
AK		 1133 fc->pause_time = 0xFFFF;
1134 fc->send_xon = 1;
0cce119a 1135 fc->current_mode = fc->requested_mode;
9d5c8243 1136
4ae196df
AD		 1137 /* disable receive for all VFs and wait one second */
1138 if (adapter->vfs_allocated_count) {
1139 int i;
1140 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1141 adapter->vf_data[i].clear_to_send = false;
1142
1143 /* ping all the active vfs to let them know we are going down */
1144 igb_ping_all_vfs(adapter);
1145
1146 /* disable transmits and receives */
1147 wr32(E1000_VFRE, 0);
1148 wr32(E1000_VFTE, 0);
1149 }
1150
9d5c8243
AK		 1151 /* Allow time for pending master requests to run */
1152 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1153 wr32(E1000_WUC, 0);
1154
1155 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1156 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1157
1158 igb_update_mng_vlan(adapter);
1159
1160 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1161 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1162
1163 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1164 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1165}
1166
2e5c6922
SH		 1167static const struct net_device_ops igb_netdev_ops = {
1168 .ndo_open = igb_open,
1169 .ndo_stop = igb_close,
00829823 1170 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1171 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1172 .ndo_set_rx_mode = igb_set_rx_mode,
1173 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1174 .ndo_set_mac_address = igb_set_mac,
1175 .ndo_change_mtu = igb_change_mtu,
1176 .ndo_do_ioctl = igb_ioctl,
1177 .ndo_tx_timeout = igb_tx_timeout,
1178 .ndo_validate_addr = eth_validate_addr,
1179 .ndo_vlan_rx_register = igb_vlan_rx_register,
1180 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1181 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1182#ifdef CONFIG_NET_POLL_CONTROLLER
1183 .ndo_poll_controller = igb_netpoll,
1184#endif
1185};
1186
9d5c8243
AK		 1187/**
1188 * igb_probe - Device Initialization Routine
1189 * @pdev: PCI device information struct
1190 * @ent: entry in igb_pci_tbl
1191 *
1192 * Returns 0 on success, negative on failure
1193 *
1194 * igb_probe initializes an adapter identified by a pci_dev structure.
1195 * The OS initialization, configuring of the adapter private structure,
1196 * and a hardware reset occur.
1197 **/
1198static int __devinit igb_probe(struct pci_dev *pdev,
1199 const struct pci_device_id *ent)
1200{
1201 struct net_device *netdev;
1202 struct igb_adapter *adapter;
1203 struct e1000_hw *hw;
1204 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1205 unsigned long mmio_start, mmio_len;
2d6a5e95 1206 int err, pci_using_dac;
682337fe 1207 u16 eeprom_data = 0;
9d5c8243
AK		 1208 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1209 u32 part_num;
1210
aed5dec3 1211 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1212 if (err)
1213 return err;
1214
1215 pci_using_dac = 0;
6a35528a 1216 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1217 if (!err) {
6a35528a 1218 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1219 if (!err)
1220 pci_using_dac = 1;
1221 } else {
284901a9 1222 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1223 if (err) {
284901a9 1224 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1225 if (err) {
1226 dev_err(&pdev->dev, "No usable DMA "
1227 "configuration, aborting\n");
1228 goto err_dma;
1229 }
1230 }
1231 }
1232
aed5dec3
AD		 1233 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1234 IORESOURCE_MEM),
1235 igb_driver_name);
9d5c8243
AK		 1236 if (err)
1237 goto err_pci_reg;
1238
ea943d41
JK		 1239 err = pci_enable_pcie_error_reporting(pdev);
1240 if (err) {
1241 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1242 "0x%x\n", err);
1243 /* non-fatal, continue */
1244 }
40a914fa 1245
9d5c8243 1246 pci_set_master(pdev);
c682fc23 1247 pci_save_state(pdev);
9d5c8243
AK		 1248
1249 err = -ENOMEM;
1bfaf07b
AD		 1250 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1251 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1252 if (!netdev)
1253 goto err_alloc_etherdev;
1254
1255 SET_NETDEV_DEV(netdev, &pdev->dev);
1256
1257 pci_set_drvdata(pdev, netdev);
1258 adapter = netdev_priv(netdev);
1259 adapter->netdev = netdev;
1260 adapter->pdev = pdev;
1261 hw = &adapter->hw;
1262 hw->back = adapter;
1263 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1264
1265 mmio_start = pci_resource_start(pdev, 0);
1266 mmio_len = pci_resource_len(pdev, 0);
1267
1268 err = -EIO;
28b0759c
AD		 1269 hw->hw_addr = ioremap(mmio_start, mmio_len);
1270 if (!hw->hw_addr)
9d5c8243
AK		 1271 goto err_ioremap;
1272
2e5c6922 1273 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1274 igb_set_ethtool_ops(netdev);
9d5c8243 1275 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1276
1277 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1278
1279 netdev->mem_start = mmio_start;
1280 netdev->mem_end = mmio_start + mmio_len;
1281
9d5c8243
AK		 1282 /* PCI config space info */
1283 hw->vendor_id = pdev->vendor;
1284 hw->device_id = pdev->device;
1285 hw->revision_id = pdev->revision;
1286 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1287 hw->subsystem_device_id = pdev->subsystem_device;
1288
1289 /* setup the private structure */
1290 hw->back = adapter;
1291 /* Copy the default MAC, PHY and NVM function pointers */
1292 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1293 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1294 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1295 /* Initialize skew-specific constants */
1296 err = ei->get_invariants(hw);
1297 if (err)
450c87c8 1298 goto err_sw_init;
9d5c8243 1299
2a3abf6d
AD		 1300#ifdef CONFIG_PCI_IOV
1301 /* since iov functionality isn't critical to base device function we
1302 * can accept failure. If it fails we don't allow iov to be enabled */
1303 if (hw->mac.type == e1000_82576) {
1304 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1305 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1306 int i;
1307 unsigned char mac_addr[ETH_ALEN];
1308
9ca046d5 1309 if (num_vfs) {
2a3abf6d
AD		 1310 adapter->vf_data = kcalloc(num_vfs,
1311 sizeof(struct vf_data_storage),
1312 GFP_KERNEL);
9ca046d5
AD		 1313 if (!adapter->vf_data) {
1314 dev_err(&pdev->dev,
1315 "Could not allocate VF private data - "
1316 "IOV enable failed\n");
2a3abf6d 1317 } else {
9ca046d5
AD		 1318 err = pci_enable_sriov(pdev, num_vfs);
1319 if (!err) {
1320 adapter->vfs_allocated_count = num_vfs;
1321 dev_info(&pdev->dev,
1322 "%d vfs allocated\n",
1323 num_vfs);
1324 for (i = 0;
1325 i < adapter->vfs_allocated_count;
1326 i++) {
1327 random_ether_addr(mac_addr);
1328 igb_set_vf_mac(adapter, i,
1329 mac_addr);
1330 }
1331 } else {
1332 kfree(adapter->vf_data);
1333 adapter->vf_data = NULL;
1334 }
2a3abf6d
AD		 1335 }
1336 }
1337 }
1338
1339#endif
450c87c8 1340 /* setup the private structure */
9d5c8243
AK		 1341 err = igb_sw_init(adapter);
1342 if (err)
1343 goto err_sw_init;
1344
1345 igb_get_bus_info_pcie(hw);
1346
7dfc16fa
AD		 1347 /* set flags */
1348 switch (hw->mac.type) {
7dfc16fa 1349 case e1000_82575:
7dfc16fa
AD		 1350 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1351 break;
bbd98fe4 1352 case e1000_82576:
7dfc16fa
AD		 1353 default:
1354 break;
1355 }
1356
9d5c8243
AK		 1357 hw->phy.autoneg_wait_to_complete = false;
1358 hw->mac.adaptive_ifs = true;
1359
1360 /* Copper options */
1361 if (hw->phy.media_type == e1000_media_type_copper) {
1362 hw->phy.mdix = AUTO_ALL_MODES;
1363 hw->phy.disable_polarity_correction = false;
1364 hw->phy.ms_type = e1000_ms_hw_default;
1365 }
1366
1367 if (igb_check_reset_block(hw))
1368 dev_info(&pdev->dev,
1369 "PHY reset is blocked due to SOL/IDER session.\n");
1370
1371 netdev->features = NETIF_F_SG |
7d8eb29e 1372 NETIF_F_IP_CSUM |
9d5c8243
AK		 1373 NETIF_F_HW_VLAN_TX |
1374 NETIF_F_HW_VLAN_RX |
1375 NETIF_F_HW_VLAN_FILTER;
1376
7d8eb29e 1377 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1378 netdev->features |= NETIF_F_TSO;
9d5c8243 1379 netdev->features |= NETIF_F_TSO6;
48f29ffc 1380
5c0999b7 1381 netdev->features |= NETIF_F_GRO;
d3352520 1382
48f29ffc
JK		 1383 netdev->vlan_features |= NETIF_F_TSO;
1384 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1385 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1386 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1387 netdev->vlan_features |= NETIF_F_SG;
1388
9d5c8243
AK		 1389 if (pci_using_dac)
1390 netdev->features |= NETIF_F_HIGHDMA;
1391
b9473560
JB		 1392 if (adapter->hw.mac.type == e1000_82576)
1393 netdev->features |= NETIF_F_SCTP_CSUM;
1394
9d5c8243
AK		 1395 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1396
1397 /* before reading the NVM, reset the controller to put the device in a
1398 * known good starting state */
1399 hw->mac.ops.reset_hw(hw);
1400
1401 /* make sure the NVM is good */
1402 if (igb_validate_nvm_checksum(hw) < 0) {
1403 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1404 err = -EIO;
1405 goto err_eeprom;
1406 }
1407
1408 /* copy the MAC address out of the NVM */
1409 if (hw->mac.ops.read_mac_addr(hw))
1410 dev_err(&pdev->dev, "NVM Read Error\n");
1411
1412 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1413 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1414
1415 if (!is_valid_ether_addr(netdev->perm_addr)) {
1416 dev_err(&pdev->dev, "Invalid MAC Address\n");
1417 err = -EIO;
1418 goto err_eeprom;
1419 }
1420
0e340485
AD		 1421 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1422 (unsigned long) adapter);
1423 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1424 (unsigned long) adapter);
9d5c8243
AK		 1425
1426 INIT_WORK(&adapter->reset_task, igb_reset_task);
1427 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1428
450c87c8 1429 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1430 adapter->fc_autoneg = true;
1431 hw->mac.autoneg = true;
1432 hw->phy.autoneg_advertised = 0x2f;
1433
0cce119a
AD		 1434 hw->fc.requested_mode = e1000_fc_default;
1435 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1436
cbd347ad 1437 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1438 adapter->itr = IGB_START_ITR;
1439
1440 igb_validate_mdi_setting(hw);
1441
9d5c8243
AK		 1442 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1443 * enable the ACPI Magic Packet filter
1444 */
1445
a2cf8b6c 1446 if (hw->bus.func == 0)
312c75ae 1447 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1448 else if (hw->bus.func == 1)
1449 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1450
1451 if (eeprom_data & eeprom_apme_mask)
1452 adapter->eeprom_wol |= E1000_WUFC_MAG;
1453
1454 /* now that we have the eeprom settings, apply the special cases where
1455 * the eeprom may be wrong or the board simply won't support wake on
1456 * lan on a particular port */
1457 switch (pdev->device) {
1458 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1459 adapter->eeprom_wol = 0;
1460 break;
1461 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1462 case E1000_DEV_ID_82576_FIBER:
1463 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1464 /* Wake events only supported on port A for dual fiber
1465 * regardless of eeprom setting */
1466 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1467 adapter->eeprom_wol = 0;
1468 break;
c8ea5ea9
AD		 1469 case E1000_DEV_ID_82576_QUAD_COPPER:
1470 /* if quad port adapter, disable WoL on all but port A */
1471 if (global_quad_port_a != 0)
1472 adapter->eeprom_wol = 0;
1473 else
1474 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1475 /* Reset for multiple quad port adapters */
1476 if (++global_quad_port_a == 4)
1477 global_quad_port_a = 0;
1478 break;
9d5c8243
AK		 1479 }
1480
1481 /* initialize the wol settings based on the eeprom settings */
1482 adapter->wol = adapter->eeprom_wol;
e1b86d84 1483 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1484
1485 /* reset the hardware with the new settings */
1486 igb_reset(adapter);
1487
1488 /* let the f/w know that the h/w is now under the control of the
1489 * driver. */
1490 igb_get_hw_control(adapter);
1491
9d5c8243
AK		 1492 strcpy(netdev->name, "eth%d");
1493 err = register_netdev(netdev);
1494 if (err)
1495 goto err_register;
1496
b168dfc5
JB		 1497 /* carrier off reporting is important to ethtool even BEFORE open */
1498 netif_carrier_off(netdev);
1499
421e02f0 1500#ifdef CONFIG_IGB_DCA
bbd98fe4 1501 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1502 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1503 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1504 igb_setup_dca(adapter);
1505 }
1506#endif
1507
38c845c7
PO		 1508 /*
1509 * Initialize hardware timer: we keep it running just in case
1510 * that some program needs it later on.
1511 */
1512 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1513 adapter->cycles.read = igb_read_clock;
1514 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1515 adapter->cycles.mult = 1;
1516 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1517 wr32(E1000_TIMINCA,
1518 (1<<24) |
1519 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1520#if 0
1521 /*
1522 * Avoid rollover while we initialize by resetting the time counter.
1523 */
1524 wr32(E1000_SYSTIML, 0x00000000);
1525 wr32(E1000_SYSTIMH, 0x00000000);
1526#else
1527 /*
1528 * Set registers so that rollover occurs soon to test this.
1529 */
1530 wr32(E1000_SYSTIML, 0x00000000);
1531 wr32(E1000_SYSTIMH, 0xFF800000);
1532#endif
1533 wrfl();
1534 timecounter_init(&adapter->clock,
1535 &adapter->cycles,
1536 ktime_to_ns(ktime_get_real()));
1537
33af6bcc
PO		 1538 /*
1539 * Synchronize our NIC clock against system wall clock. NIC
1540 * time stamp reading requires ~3us per sample, each sample
1541 * was pretty stable even under load => only require 10
1542 * samples for each offset comparison.
1543 */
1544 memset(&adapter->compare, 0, sizeof(adapter->compare));
1545 adapter->compare.source = &adapter->clock;
1546 adapter->compare.target = ktime_get_real;
1547 adapter->compare.num_samples = 10;
1548 timecompare_update(&adapter->compare, 0);
1549
38c845c7
PO		 1550#ifdef DEBUG
1551 {
1552 char buffer[160];
1553 printk(KERN_DEBUG
1554 "igb: %s: hw %p initialized timer\n",
1555 igb_get_time_str(adapter, buffer),
1556 &adapter->hw);
1557 }
1558#endif
1559
9d5c8243
AK		 1560 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1561 /* print bus type/speed/width info */
7c510e4b 1562 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1563 netdev->name,
1564 ((hw->bus.speed == e1000_bus_speed_2500)
1565 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1566 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1567 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1568 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1569 "unknown"),
7c510e4b 1570 netdev->dev_addr);
9d5c8243
AK		 1571
1572 igb_read_part_num(hw, &part_num);
1573 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1574 (part_num >> 8), (part_num & 0xff));
1575
1576 dev_info(&pdev->dev,
1577 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1578 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1579 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1580 adapter->num_rx_queues, adapter->num_tx_queues);
1581
9d5c8243
AK		 1582 return 0;
1583
1584err_register:
1585 igb_release_hw_control(adapter);
1586err_eeprom:
1587 if (!igb_check_reset_block(hw))
f5f4cf08 1588 igb_reset_phy(hw);
9d5c8243
AK		 1589
1590 if (hw->flash_address)
1591 iounmap(hw->flash_address);
1592
a88f10ec 1593 igb_free_queues(adapter);
9d5c8243 1594err_sw_init:
9d5c8243
AK		 1595 iounmap(hw->hw_addr);
1596err_ioremap:
1597 free_netdev(netdev);
1598err_alloc_etherdev:
aed5dec3
AD		 1599 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1600 IORESOURCE_MEM));
9d5c8243
AK		 1601err_pci_reg:
1602err_dma:
1603 pci_disable_device(pdev);
1604 return err;
1605}
1606
1607/**
1608 * igb_remove - Device Removal Routine
1609 * @pdev: PCI device information struct
1610 *
1611 * igb_remove is called by the PCI subsystem to alert the driver
1612 * that it should release a PCI device. The could be caused by a
1613 * Hot-Plug event, or because the driver is going to be removed from
1614 * memory.
1615 **/
1616static void __devexit igb_remove(struct pci_dev *pdev)
1617{
1618 struct net_device *netdev = pci_get_drvdata(pdev);
1619 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1620 struct e1000_hw *hw = &adapter->hw;
ea943d41 1621 int err;
9d5c8243
AK		 1622
1623 /* flush_scheduled work may reschedule our watchdog task, so
1624 * explicitly disable watchdog tasks from being rescheduled */
1625 set_bit(__IGB_DOWN, &adapter->state);
1626 del_timer_sync(&adapter->watchdog_timer);
1627 del_timer_sync(&adapter->phy_info_timer);
1628
1629 flush_scheduled_work();
1630
421e02f0 1631#ifdef CONFIG_IGB_DCA
7dfc16fa 1632 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1633 dev_info(&pdev->dev, "DCA disabled\n");
1634 dca_remove_requester(&pdev->dev);
7dfc16fa 1635 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1636 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1637 }
1638#endif
1639
9d5c8243
AK		 1640 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1641 * would have already happened in close and is redundant. */
1642 igb_release_hw_control(adapter);
1643
1644 unregister_netdev(netdev);
1645
f5f4cf08
AD		 1646 if (!igb_check_reset_block(&adapter->hw))
1647 igb_reset_phy(&adapter->hw);
9d5c8243 1648
9d5c8243
AK		 1649 igb_reset_interrupt_capability(adapter);
1650
a88f10ec 1651 igb_free_queues(adapter);
9d5c8243 1652
37680117
AD		 1653#ifdef CONFIG_PCI_IOV
1654 /* reclaim resources allocated to VFs */
1655 if (adapter->vf_data) {
1656 /* disable iov and allow time for transactions to clear */
1657 pci_disable_sriov(pdev);
1658 msleep(500);
1659
1660 kfree(adapter->vf_data);
1661 adapter->vf_data = NULL;
1662 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1663 msleep(100);
1664 dev_info(&pdev->dev, "IOV Disabled\n");
1665 }
1666#endif
28b0759c
AD		 1667 iounmap(hw->hw_addr);
1668 if (hw->flash_address)
1669 iounmap(hw->flash_address);
aed5dec3
AD		 1670 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1671 IORESOURCE_MEM));
9d5c8243
AK		 1672
1673 free_netdev(netdev);
1674
ea943d41
JK		 1675 err = pci_disable_pcie_error_reporting(pdev);
1676 if (err)
1677 dev_err(&pdev->dev,
1678 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1679
9d5c8243
AK		 1680 pci_disable_device(pdev);
1681}
1682
1683/**
1684 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1685 * @adapter: board private structure to initialize
1686 *
1687 * igb_sw_init initializes the Adapter private data structure.
1688 * Fields are initialized based on PCI device information and
1689 * OS network device settings (MTU size).
1690 **/
1691static int __devinit igb_sw_init(struct igb_adapter *adapter)
1692{
1693 struct e1000_hw *hw = &adapter->hw;
1694 struct net_device *netdev = adapter->netdev;
1695 struct pci_dev *pdev = adapter->pdev;
1696
1697 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1698
68fd9910
AD		 1699 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1700 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1701 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1702 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1703 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1704 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1705
661086df
PWJ		 1706 /* This call may decrease the number of queues depending on
1707 * interrupt mode. */
9d5c8243
AK		 1708 igb_set_interrupt_capability(adapter);
1709
1710 if (igb_alloc_queues(adapter)) {
1711 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1712 return -ENOMEM;
1713 }
1714
1715 /* Explicitly disable IRQ since the NIC can be in any state. */
1716 igb_irq_disable(adapter);
1717
1718 set_bit(__IGB_DOWN, &adapter->state);
1719 return 0;
1720}
1721
1722/**
1723 * igb_open - Called when a network interface is made active
1724 * @netdev: network interface device structure
1725 *
1726 * Returns 0 on success, negative value on failure
1727 *
1728 * The open entry point is called when a network interface is made
1729 * active by the system (IFF_UP). At this point all resources needed
1730 * for transmit and receive operations are allocated, the interrupt
1731 * handler is registered with the OS, the watchdog timer is started,
1732 * and the stack is notified that the interface is ready.
1733 **/
1734static int igb_open(struct net_device *netdev)
1735{
1736 struct igb_adapter *adapter = netdev_priv(netdev);
1737 struct e1000_hw *hw = &adapter->hw;
1738 int err;
1739 int i;
1740
1741 /* disallow open during test */
1742 if (test_bit(__IGB_TESTING, &adapter->state))
1743 return -EBUSY;
1744
b168dfc5
JB		 1745 netif_carrier_off(netdev);
1746
9d5c8243
AK		 1747 /* allocate transmit descriptors */
1748 err = igb_setup_all_tx_resources(adapter);
1749 if (err)
1750 goto err_setup_tx;
1751
1752 /* allocate receive descriptors */
1753 err = igb_setup_all_rx_resources(adapter);
1754 if (err)
1755 goto err_setup_rx;
1756
1757 /* e1000_power_up_phy(adapter); */
1758
1759 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1760 if ((adapter->hw.mng_cookie.status &
1761 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1762 igb_update_mng_vlan(adapter);
1763
1764 /* before we allocate an interrupt, we must be ready to handle it.
1765 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1766 * as soon as we call pci_request_irq, so we have to setup our
1767 * clean_rx handler before we do so. */
1768 igb_configure(adapter);
1769
4ae196df 1770 igb_vmm_control(adapter);
e1739522
AD		 1771 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1772 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1773
9d5c8243
AK		 1774 err = igb_request_irq(adapter);
1775 if (err)
1776 goto err_req_irq;
1777
1778 /* From here on the code is the same as igb_up() */
1779 clear_bit(__IGB_DOWN, &adapter->state);
1780
844290e5
PW		 1781 for (i = 0; i < adapter->num_rx_queues; i++)
1782 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1783
1784 /* Clear any pending interrupts. */
1785 rd32(E1000_ICR);
844290e5
PW		 1786
1787 igb_irq_enable(adapter);
1788
d55b53ff
JK		 1789 netif_tx_start_all_queues(netdev);
1790
9d5c8243
AK		 1791 /* Fire a link status change interrupt to start the watchdog. */
1792 wr32(E1000_ICS, E1000_ICS_LSC);
1793
1794 return 0;
1795
1796err_req_irq:
1797 igb_release_hw_control(adapter);
1798 /* e1000_power_down_phy(adapter); */
1799 igb_free_all_rx_resources(adapter);
1800err_setup_rx:
1801 igb_free_all_tx_resources(adapter);
1802err_setup_tx:
1803 igb_reset(adapter);
1804
1805 return err;
1806}
1807
1808/**
1809 * igb_close - Disables a network interface
1810 * @netdev: network interface device structure
1811 *
1812 * Returns 0, this is not allowed to fail
1813 *
1814 * The close entry point is called when an interface is de-activated
1815 * by the OS. The hardware is still under the driver's control, but
1816 * needs to be disabled. A global MAC reset is issued to stop the
1817 * hardware, and all transmit and receive resources are freed.
1818 **/
1819static int igb_close(struct net_device *netdev)
1820{
1821 struct igb_adapter *adapter = netdev_priv(netdev);
1822
1823 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1824 igb_down(adapter);
1825
1826 igb_free_irq(adapter);
1827
1828 igb_free_all_tx_resources(adapter);
1829 igb_free_all_rx_resources(adapter);
1830
1831 /* kill manageability vlan ID if supported, but not if a vlan with
1832 * the same ID is registered on the host OS (let 8021q kill it) */
1833 if ((adapter->hw.mng_cookie.status &
1834 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1835 !(adapter->vlgrp &&
1836 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1837 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1838
1839 return 0;
1840}
1841
1842/**
1843 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1844 * @adapter: board private structure
1845 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1846 *
1847 * Return 0 on success, negative on failure
1848 **/
9d5c8243
AK		 1849int igb_setup_tx_resources(struct igb_adapter *adapter,
1850 struct igb_ring *tx_ring)
1851{
1852 struct pci_dev *pdev = adapter->pdev;
1853 int size;
1854
1855 size = sizeof(struct igb_buffer) * tx_ring->count;
1856 tx_ring->buffer_info = vmalloc(size);
1857 if (!tx_ring->buffer_info)
1858 goto err;
1859 memset(tx_ring->buffer_info, 0, size);
1860
1861 /* round up to nearest 4K */
85e8d004 1862 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1863 tx_ring->size = ALIGN(tx_ring->size, 4096);
1864
1865 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1866 &tx_ring->dma);
1867
1868 if (!tx_ring->desc)
1869 goto err;
1870
1871 tx_ring->adapter = adapter;
1872 tx_ring->next_to_use = 0;
1873 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1874 return 0;
1875
1876err:
1877 vfree(tx_ring->buffer_info);
1878 dev_err(&adapter->pdev->dev,
1879 "Unable to allocate memory for the transmit descriptor ring\n");
1880 return -ENOMEM;
1881}
1882
1883/**
1884 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1885 * (Descriptors) for all queues
1886 * @adapter: board private structure
1887 *
1888 * Return 0 on success, negative on failure
1889 **/
1890static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1891{
1892 int i, err = 0;
661086df 1893 int r_idx;
9d5c8243
AK		 1894
1895 for (i = 0; i < adapter->num_tx_queues; i++) {
1896 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1897 if (err) {
1898 dev_err(&adapter->pdev->dev,
1899 "Allocation for Tx Queue %u failed\n", i);
1900 for (i--; i >= 0; i--)
3b644cf6 1901 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1902 break;
1903 }
1904 }
1905
661086df
PWJ		 1906 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1907 r_idx = i % adapter->num_tx_queues;
1908 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1909 }
9d5c8243
AK		 1910 return err;
1911}
1912
1913/**
1914 * igb_configure_tx - Configure transmit Unit after Reset
1915 * @adapter: board private structure
1916 *
1917 * Configure the Tx unit of the MAC after a reset.
1918 **/
1919static void igb_configure_tx(struct igb_adapter *adapter)
1920{
0e014cb1 1921 u64 tdba;
9d5c8243
AK		 1922 struct e1000_hw *hw = &adapter->hw;
1923 u32 tctl;
1924 u32 txdctl, txctrl;
26bc19ec 1925 int i, j;
9d5c8243
AK		 1926
1927 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1928 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1929 j = ring->reg_idx;
1930 wr32(E1000_TDLEN(j),
85e8d004 1931 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1932 tdba = ring->dma;
26bc19ec 1933 wr32(E1000_TDBAL(j),
73cd78f1 1934 tdba & 0x00000000ffffffffULL);
26bc19ec 1935 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1936
26bc19ec
AD		 1937 ring->head = E1000_TDH(j);
1938 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1939 writel(0, hw->hw_addr + ring->tail);
1940 writel(0, hw->hw_addr + ring->head);
26bc19ec 1941 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1942 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1943 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1944
1945 /* Turn off Relaxed Ordering on head write-backs. The
1946 * writebacks MUST be delivered in order or it will
1947 * completely screw up our bookeeping.
1948 */
26bc19ec 1949 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1950 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1951 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1952 }
1953
e1739522
AD		 1954 /* disable queue 0 to prevent tail bump w/o re-configuration */
1955 if (adapter->vfs_allocated_count)
1956 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1957
1958 /* Program the Transmit Control Register */
9d5c8243
AK		 1959 tctl = rd32(E1000_TCTL);
1960 tctl &= ~E1000_TCTL_CT;
1961 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1962 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1963
1964 igb_config_collision_dist(hw);
1965
1966 /* Setup Transmit Descriptor Settings for eop descriptor */
1967 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1968
1969 /* Enable transmits */
1970 tctl |= E1000_TCTL_EN;
1971
1972 wr32(E1000_TCTL, tctl);
1973}
1974
1975/**
1976 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1977 * @adapter: board private structure
1978 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1979 *
1980 * Returns 0 on success, negative on failure
1981 **/
9d5c8243
AK		 1982int igb_setup_rx_resources(struct igb_adapter *adapter,
1983 struct igb_ring *rx_ring)
1984{
1985 struct pci_dev *pdev = adapter->pdev;
1986 int size, desc_len;
1987
1988 size = sizeof(struct igb_buffer) * rx_ring->count;
1989 rx_ring->buffer_info = vmalloc(size);
1990 if (!rx_ring->buffer_info)
1991 goto err;
1992 memset(rx_ring->buffer_info, 0, size);
1993
1994 desc_len = sizeof(union e1000_adv_rx_desc);
1995
1996 /* Round up to nearest 4K */
1997 rx_ring->size = rx_ring->count * desc_len;
1998 rx_ring->size = ALIGN(rx_ring->size, 4096);
1999
2000 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2001 &rx_ring->dma);
2002
2003 if (!rx_ring->desc)
2004 goto err;
2005
2006 rx_ring->next_to_clean = 0;
2007 rx_ring->next_to_use = 0;
9d5c8243
AK		 2008
2009 rx_ring->adapter = adapter;
9d5c8243
AK		 2010
2011 return 0;
2012
2013err:
2014 vfree(rx_ring->buffer_info);
2015 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2016 "the receive descriptor ring\n");
2017 return -ENOMEM;
2018}
2019
2020/**
2021 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2022 * (Descriptors) for all queues
2023 * @adapter: board private structure
2024 *
2025 * Return 0 on success, negative on failure
2026 **/
2027static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2028{
2029 int i, err = 0;
2030
2031 for (i = 0; i < adapter->num_rx_queues; i++) {
2032 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2033 if (err) {
2034 dev_err(&adapter->pdev->dev,
2035 "Allocation for Rx Queue %u failed\n", i);
2036 for (i--; i >= 0; i--)
3b644cf6 2037 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2038 break;
2039 }
2040 }
2041
2042 return err;
2043}
2044
2045/**
2046 * igb_setup_rctl - configure the receive control registers
2047 * @adapter: Board private structure
2048 **/
2049static void igb_setup_rctl(struct igb_adapter *adapter)
2050{
2051 struct e1000_hw *hw = &adapter->hw;
2052 u32 rctl;
2053 u32 srrctl = 0;
77a22941 2054 int i;
9d5c8243
AK		 2055
2056 rctl = rd32(E1000_RCTL);
2057
2058 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2059 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2060
69d728ba 2061 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2062 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2063
87cb7e8c
AK		 2064 /*
2065 * enable stripping of CRC. It's unlikely this will break BMC
2066 * redirection as it did with e1000. Newer features require
2067 * that the HW strips the CRC.
73cd78f1 2068 */
87cb7e8c 2069 rctl |= E1000_RCTL_SECRC;
9d5c8243 2070
9b07f3d3 2071 /*
ec54d7d6 2072 * disable store bad packets and clear size bits.
9b07f3d3 2073 */
ec54d7d6 2074 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2075
ec54d7d6 2076 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 2077 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 2078
2079 /* Setup buffer sizes */
2080 switch (adapter->rx_buffer_len) {
2081 case IGB_RXBUFFER_256:
2082 rctl |= E1000_RCTL_SZ_256;
2083 break;
2084 case IGB_RXBUFFER_512:
2085 rctl |= E1000_RCTL_SZ_512;
2086 break;
2087 default:
2088 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2089 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2090 break;
9d5c8243
AK		 2091 }
2092
2093 /* 82575 and greater support packet-split where the protocol
2094 * header is placed in skb->data and the packet data is
2095 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2096 * In the case of a non-split, skb->data is linearly filled,
2097 * followed by the page buffers. Therefore, skb->data is
2098 * sized to hold the largest protocol header.
2099 */
2100 /* allocations using alloc_page take too long for regular MTU
2101 * so only enable packet split for jumbo frames */
ec54d7d6 2102 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2103 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2104 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2105 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2106 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2107 } else {
2108 adapter->rx_ps_hdr_size = 0;
2109 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2110 }
2111
e1739522
AD		 2112 /* Attention!!! For SR-IOV PF driver operations you must enable
2113 * queue drop for all VF and PF queues to prevent head of line blocking
2114 * if an un-trusted VF does not provide descriptors to hardware.
2115 */
2116 if (adapter->vfs_allocated_count) {
2117 u32 vmolr;
2118
e1739522
AD		 2119 /* set all queue drop enable bits */
2120 wr32(E1000_QDE, ALL_QUEUES);
2121 srrctl |= E1000_SRRCTL_DROP_EN;
2122
2123 /* disable queue 0 to prevent tail write w/o re-config */
2124 wr32(E1000_RXDCTL(0), 0);
2125
77a22941 2126 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2127 if (rctl & E1000_RCTL_LPE)
2128 vmolr |= E1000_VMOLR_LPE;
77a22941 2129 if (adapter->num_rx_queues > 1)
e1739522 2130 vmolr |= E1000_VMOLR_RSSE;
77a22941 2131 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2132 }
2133
26bc19ec 2134 for (i = 0; i < adapter->num_rx_queues; i++) {
77a22941 2135 int j = adapter->rx_ring[i].reg_idx;
26bc19ec
AD		 2136 wr32(E1000_SRRCTL(j), srrctl);
2137 }
9d5c8243
AK		 2138
2139 wr32(E1000_RCTL, rctl);
2140}
2141
e1739522
AD		 2142/**
2143 * igb_rlpml_set - set maximum receive packet size
2144 * @adapter: board private structure
2145 *
2146 * Configure maximum receivable packet size.
2147 **/
2148static void igb_rlpml_set(struct igb_adapter *adapter)
2149{
2150 u32 max_frame_size = adapter->max_frame_size;
2151 struct e1000_hw *hw = &adapter->hw;
2152 u16 pf_id = adapter->vfs_allocated_count;
2153
2154 if (adapter->vlgrp)
2155 max_frame_size += VLAN_TAG_SIZE;
2156
2157 /* if vfs are enabled we set RLPML to the largest possible request
2158 * size and set the VMOLR RLPML to the size we need */
2159 if (pf_id) {
2160 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2161 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2162 }
2163
2164 wr32(E1000_RLPML, max_frame_size);
2165}
2166
2167/**
2168 * igb_configure_vt_default_pool - Configure VT default pool
2169 * @adapter: board private structure
2170 *
2171 * Configure the default pool
2172 **/
2173static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2174{
2175 struct e1000_hw *hw = &adapter->hw;
2176 u16 pf_id = adapter->vfs_allocated_count;
2177 u32 vtctl;
2178
2179 /* not in sr-iov mode - do nothing */
2180 if (!pf_id)
2181 return;
2182
2183 vtctl = rd32(E1000_VT_CTL);
2184 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2185 E1000_VT_CTL_DISABLE_DEF_POOL);
2186 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2187 wr32(E1000_VT_CTL, vtctl);
2188}
2189
9d5c8243
AK		 2190/**
2191 * igb_configure_rx - Configure receive Unit after Reset
2192 * @adapter: board private structure
2193 *
2194 * Configure the Rx unit of the MAC after a reset.
2195 **/
2196static void igb_configure_rx(struct igb_adapter *adapter)
2197{
2198 u64 rdba;
2199 struct e1000_hw *hw = &adapter->hw;
2200 u32 rctl, rxcsum;
2201 u32 rxdctl;
9107584e 2202 int i;
9d5c8243
AK		 2203
2204 /* disable receives while setting up the descriptors */
2205 rctl = rd32(E1000_RCTL);
2206 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2207 wrfl();
2208 mdelay(10);
2209
2210 if (adapter->itr_setting > 3)
6eb5a7f1 2211 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2212
2213 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2214 * the Base and Length of the Rx Descriptor Ring */
2215 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2216 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2217 int j = ring->reg_idx;
9d5c8243 2218 rdba = ring->dma;
26bc19ec 2219 wr32(E1000_RDBAL(j),
73cd78f1 2220 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2221 wr32(E1000_RDBAH(j), rdba >> 32);
2222 wr32(E1000_RDLEN(j),
73cd78f1 2223 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2224
26bc19ec
AD		 2225 ring->head = E1000_RDH(j);
2226 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2227 writel(0, hw->hw_addr + ring->tail);
2228 writel(0, hw->hw_addr + ring->head);
2229
26bc19ec 2230 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2231 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2232 rxdctl &= 0xFFF00000;
2233 rxdctl |= IGB_RX_PTHRESH;
2234 rxdctl |= IGB_RX_HTHRESH << 8;
2235 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2236 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2237 }
2238
2239 if (adapter->num_rx_queues > 1) {
2240 u32 random[10];
2241 u32 mrqc;
2242 u32 j, shift;
2243 union e1000_reta {
2244 u32 dword;
2245 u8 bytes[4];
2246 } reta;
2247
2248 get_random_bytes(&random[0], 40);
2249
2d064c06
AD		 2250 if (hw->mac.type >= e1000_82576)
2251 shift = 0;
2252 else
2253 shift = 6;
9d5c8243
AK		 2254 for (j = 0; j < (32 * 4); j++) {
2255 reta.bytes[j & 3] =
26bc19ec 2256 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2257 if ((j & 3) == 3)
2258 writel(reta.dword,
2259 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2260 }
e1739522
AD		 2261 if (adapter->vfs_allocated_count)
2262 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2263 else
2264 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2265
2266 /* Fill out hash function seeds */
2267 for (j = 0; j < 10; j++)
2268 array_wr32(E1000_RSSRK(0), j, random[j]);
2269
2270 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2271 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2272 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2273 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2274 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2275 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2276 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2277 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2278
9d5c8243 2279 wr32(E1000_MRQC, mrqc);
2844f797 2280 } else if (adapter->vfs_allocated_count) {
e1739522 2281 /* Enable multi-queue for sr-iov */
2844f797 2282 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2283 }
2284
2844f797
AD		 2285 /* Enable Receive Checksum Offload for TCP and UDP */
2286 rxcsum = rd32(E1000_RXCSUM);
2287 /* Disable raw packet checksumming */
2288 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2289
2290 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2291 /* Enable Receive Checksum Offload for SCTP */
2292 rxcsum |= E1000_RXCSUM_CRCOFL;
2293
7beb0146 2294 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2295 wr32(E1000_RXCSUM, rxcsum);
2296
e1739522
AD		 2297 /* Set the default pool for the PF's first queue */
2298 igb_configure_vt_default_pool(adapter);
2299
2300 igb_rlpml_set(adapter);
9d5c8243
AK		 2301
2302 /* Enable Receives */
2303 wr32(E1000_RCTL, rctl);
2304}
2305
2306/**
2307 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2308 * @tx_ring: Tx descriptor ring for a specific queue
2309 *
2310 * Free all transmit software resources
2311 **/
68fd9910 2312void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2313{
3b644cf6 2314 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2315
3b644cf6 2316 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2317
2318 vfree(tx_ring->buffer_info);
2319 tx_ring->buffer_info = NULL;
2320
2321 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2322
2323 tx_ring->desc = NULL;
2324}
2325
2326/**
2327 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2328 * @adapter: board private structure
2329 *
2330 * Free all transmit software resources
2331 **/
2332static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2333{
2334 int i;
2335
2336 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2337 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2338}
2339
2340static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2341 struct igb_buffer *buffer_info)
2342{
65689fef 2343 buffer_info->dma = 0;
9d5c8243 2344 if (buffer_info->skb) {
65689fef
AD		 2345 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2346 DMA_TO_DEVICE);
9d5c8243
AK		 2347 dev_kfree_skb_any(buffer_info->skb);
2348 buffer_info->skb = NULL;
2349 }
2350 buffer_info->time_stamp = 0;
2351 /* buffer_info must be completely set up in the transmit path */
2352}
2353
2354/**
2355 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2356 * @tx_ring: ring to be cleaned
2357 **/
3b644cf6 2358static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2359{
3b644cf6 2360 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2361 struct igb_buffer *buffer_info;
2362 unsigned long size;
2363 unsigned int i;
2364
2365 if (!tx_ring->buffer_info)
2366 return;
2367 /* Free all the Tx ring sk_buffs */
2368
2369 for (i = 0; i < tx_ring->count; i++) {
2370 buffer_info = &tx_ring->buffer_info[i];
2371 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2372 }
2373
2374 size = sizeof(struct igb_buffer) * tx_ring->count;
2375 memset(tx_ring->buffer_info, 0, size);
2376
2377 /* Zero out the descriptor ring */
2378
2379 memset(tx_ring->desc, 0, tx_ring->size);
2380
2381 tx_ring->next_to_use = 0;
2382 tx_ring->next_to_clean = 0;
2383
2384 writel(0, adapter->hw.hw_addr + tx_ring->head);
2385 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2386}
2387
2388/**
2389 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2390 * @adapter: board private structure
2391 **/
2392static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2393{
2394 int i;
2395
2396 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2397 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2398}
2399
2400/**
2401 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2402 * @rx_ring: ring to clean the resources from
2403 *
2404 * Free all receive software resources
2405 **/
68fd9910 2406void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2407{
3b644cf6 2408 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2409
3b644cf6 2410 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2411
2412 vfree(rx_ring->buffer_info);
2413 rx_ring->buffer_info = NULL;
2414
2415 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2416
2417 rx_ring->desc = NULL;
2418}
2419
2420/**
2421 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2422 * @adapter: board private structure
2423 *
2424 * Free all receive software resources
2425 **/
2426static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2427{
2428 int i;
2429
2430 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2431 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2432}
2433
2434/**
2435 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2436 * @rx_ring: ring to free buffers from
2437 **/
3b644cf6 2438static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2439{
3b644cf6 2440 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2441 struct igb_buffer *buffer_info;
2442 struct pci_dev *pdev = adapter->pdev;
2443 unsigned long size;
2444 unsigned int i;
2445
2446 if (!rx_ring->buffer_info)
2447 return;
2448 /* Free all the Rx ring sk_buffs */
2449 for (i = 0; i < rx_ring->count; i++) {
2450 buffer_info = &rx_ring->buffer_info[i];
2451 if (buffer_info->dma) {
2452 if (adapter->rx_ps_hdr_size)
2453 pci_unmap_single(pdev, buffer_info->dma,
2454 adapter->rx_ps_hdr_size,
2455 PCI_DMA_FROMDEVICE);
2456 else
2457 pci_unmap_single(pdev, buffer_info->dma,
2458 adapter->rx_buffer_len,
2459 PCI_DMA_FROMDEVICE);
2460 buffer_info->dma = 0;
2461 }
2462
2463 if (buffer_info->skb) {
2464 dev_kfree_skb(buffer_info->skb);
2465 buffer_info->skb = NULL;
2466 }
2467 if (buffer_info->page) {
bf36c1a0
AD		 2468 if (buffer_info->page_dma)
2469 pci_unmap_page(pdev, buffer_info->page_dma,
2470 PAGE_SIZE / 2,
2471 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2472 put_page(buffer_info->page);
2473 buffer_info->page = NULL;
2474 buffer_info->page_dma = 0;
bf36c1a0 2475 buffer_info->page_offset = 0;
9d5c8243
AK		 2476 }
2477 }
2478
9d5c8243
AK		 2479 size = sizeof(struct igb_buffer) * rx_ring->count;
2480 memset(rx_ring->buffer_info, 0, size);
2481
2482 /* Zero out the descriptor ring */
2483 memset(rx_ring->desc, 0, rx_ring->size);
2484
2485 rx_ring->next_to_clean = 0;
2486 rx_ring->next_to_use = 0;
2487
2488 writel(0, adapter->hw.hw_addr + rx_ring->head);
2489 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2490}
2491
2492/**
2493 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2494 * @adapter: board private structure
2495 **/
2496static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2497{
2498 int i;
2499
2500 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2501 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2502}
2503
2504/**
2505 * igb_set_mac - Change the Ethernet Address of the NIC
2506 * @netdev: network interface device structure
2507 * @p: pointer to an address structure
2508 *
2509 * Returns 0 on success, negative on failure
2510 **/
2511static int igb_set_mac(struct net_device *netdev, void *p)
2512{
2513 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2514 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2515 struct sockaddr *addr = p;
2516
2517 if (!is_valid_ether_addr(addr->sa_data))
2518 return -EADDRNOTAVAIL;
2519
2520 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2521 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2522
ff41f8dc 2523 igb_rar_set(hw, hw->mac.addr, 0);
e1739522
AD		 2524 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2525
9d5c8243
AK		 2526 return 0;
2527}
2528
2529/**
ff41f8dc 2530 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
9d5c8243
AK		 2531 * @netdev: network interface device structure
2532 *
ff41f8dc
AD		 2533 * The set_rx_mode entry point is called whenever the unicast or multicast
2534 * address lists or the network interface flags are updated. This routine is
2535 * responsible for configuring the hardware for proper unicast, multicast,
9d5c8243
AK		 2536 * promiscuous mode, and all-multi behavior.
2537 **/
ff41f8dc 2538static void igb_set_rx_mode(struct net_device *netdev)
9d5c8243
AK		 2539{
2540 struct igb_adapter *adapter = netdev_priv(netdev);
2541 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 2542 unsigned int rar_entries = hw->mac.rar_entry_count -
2543 (adapter->vfs_allocated_count + 1);
2544 struct dev_mc_list *mc_ptr = netdev->mc_list;
c5cd11e3 2545 u8 *mta_list = NULL;
9d5c8243
AK		 2546 u32 rctl;
2547 int i;
2548
2549 /* Check for Promiscuous and All Multicast modes */
9d5c8243
AK		 2550 rctl = rd32(E1000_RCTL);
2551
746b9f02 2552 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2553 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2554 rctl &= ~E1000_RCTL_VFE;
2555 } else {
ff41f8dc 2556 if (netdev->flags & IFF_ALLMULTI)
746b9f02 2557 rctl |= E1000_RCTL_MPE;
ff41f8dc
AD		 2558 else
2559 rctl &= ~E1000_RCTL_MPE;
2560
2561 if (netdev->uc.count > rar_entries)
2562 rctl |= E1000_RCTL_UPE;
2563 else
746b9f02 2564 rctl &= ~E1000_RCTL_UPE;
78ed11a5 2565 rctl |= E1000_RCTL_VFE;
746b9f02 2566 }
9d5c8243
AK		 2567 wr32(E1000_RCTL, rctl);
2568
ff41f8dc
AD		 2569 if (netdev->uc.count && rar_entries) {
2570 struct netdev_hw_addr *ha;
2571 list_for_each_entry(ha, &netdev->uc.list, list) {
2572 if (!rar_entries)
2573 break;
2574 igb_rar_set(hw, ha->addr, rar_entries);
2575 igb_set_rah_pool(hw, adapter->vfs_allocated_count,
2576 rar_entries);
2577 rar_entries--;
2578 }
2579 }
2580 /* write the addresses in reverse order to avoid write combining */
2581 for (; rar_entries > 0 ; rar_entries--) {
2582 wr32(E1000_RAH(rar_entries), 0);
2583 wr32(E1000_RAL(rar_entries), 0);
2584 }
2585 wrfl();
2586
28fc06f5
AD		 2587 if (!netdev->mc_count) {
2588 /* nothing to program, so clear mc list */
2589 igb_update_mc_addr_list(hw, NULL, 0);
2590 igb_restore_vf_multicasts(adapter);
2591 return;
2592 }
2593
2594 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2595 if (!mta_list) {
2596 dev_err(&adapter->pdev->dev,
2597 "failed to allocate multicast filter list\n");
2598 return;
9d5c8243
AK		 2599 }
2600
9d5c8243 2601 /* The shared function expects a packed array of only addresses. */
9d5c8243
AK		 2602 for (i = 0; i < netdev->mc_count; i++) {
2603 if (!mc_ptr)
2604 break;
2605 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2606 mc_ptr = mc_ptr->next;
2607 }
28fc06f5 2608 igb_update_mc_addr_list(hw, mta_list, i);
9d5c8243 2609 kfree(mta_list);
28fc06f5 2610 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2611}
2612
2613/* Need to wait a few seconds after link up to get diagnostic information from
2614 * the phy */
2615static void igb_update_phy_info(unsigned long data)
2616{
2617 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2618 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2619}
2620
4d6b725e
AD		 2621/**
2622 * igb_has_link - check shared code for link and determine up/down
2623 * @adapter: pointer to driver private info
2624 **/
2625static bool igb_has_link(struct igb_adapter *adapter)
2626{
2627 struct e1000_hw *hw = &adapter->hw;
2628 bool link_active = false;
2629 s32 ret_val = 0;
2630
2631 /* get_link_status is set on LSC (link status) interrupt or
2632 * rx sequence error interrupt. get_link_status will stay
2633 * false until the e1000_check_for_link establishes link
2634 * for copper adapters ONLY
2635 */
2636 switch (hw->phy.media_type) {
2637 case e1000_media_type_copper:
2638 if (hw->mac.get_link_status) {
2639 ret_val = hw->mac.ops.check_for_link(hw);
2640 link_active = !hw->mac.get_link_status;
2641 } else {
2642 link_active = true;
2643 }
2644 break;
4d6b725e
AD		 2645 case e1000_media_type_internal_serdes:
2646 ret_val = hw->mac.ops.check_for_link(hw);
2647 link_active = hw->mac.serdes_has_link;
2648 break;
2649 default:
2650 case e1000_media_type_unknown:
2651 break;
2652 }
2653
2654 return link_active;
2655}
2656
9d5c8243
AK		 2657/**
2658 * igb_watchdog - Timer Call-back
2659 * @data: pointer to adapter cast into an unsigned long
2660 **/
2661static void igb_watchdog(unsigned long data)
2662{
2663 struct igb_adapter *adapter = (struct igb_adapter *)data;
2664 /* Do the rest outside of interrupt context */
2665 schedule_work(&adapter->watchdog_task);
2666}
2667
2668static void igb_watchdog_task(struct work_struct *work)
2669{
2670 struct igb_adapter *adapter = container_of(work,
2671 struct igb_adapter, watchdog_task);
2672 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2673 struct net_device *netdev = adapter->netdev;
2674 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2675 u32 link;
7a6ea550 2676 u32 eics = 0;
7a6ea550 2677 int i;
9d5c8243 2678
4d6b725e
AD		 2679 link = igb_has_link(adapter);
2680 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2681 goto link_up;
2682
9d5c8243
AK		 2683 if (link) {
2684 if (!netif_carrier_ok(netdev)) {
2685 u32 ctrl;
2686 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2687 &adapter->link_speed,
2688 &adapter->link_duplex);
2689
2690 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2691 /* Links status message must follow this format */
2692 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2693 "Flow Control: %s\n",
527d47c1 2694 netdev->name,
9d5c8243
AK		 2695 adapter->link_speed,
2696 adapter->link_duplex == FULL_DUPLEX ?
2697 "Full Duplex" : "Half Duplex",
2698 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2699 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2700 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2701 E1000_CTRL_TFCE) ? "TX" : "None")));
2702
2703 /* tweak tx_queue_len according to speed/duplex and
2704 * adjust the timeout factor */
2705 netdev->tx_queue_len = adapter->tx_queue_len;
2706 adapter->tx_timeout_factor = 1;
2707 switch (adapter->link_speed) {
2708 case SPEED_10:
2709 netdev->tx_queue_len = 10;
2710 adapter->tx_timeout_factor = 14;
2711 break;
2712 case SPEED_100:
2713 netdev->tx_queue_len = 100;
2714 /* maybe add some timeout factor ? */
2715 break;
2716 }
2717
2718 netif_carrier_on(netdev);
9d5c8243 2719
4ae196df
AD		 2720 igb_ping_all_vfs(adapter);
2721
4b1a9877 2722 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2723 if (!test_bit(__IGB_DOWN, &adapter->state))
2724 mod_timer(&adapter->phy_info_timer,
2725 round_jiffies(jiffies + 2 * HZ));
2726 }
2727 } else {
2728 if (netif_carrier_ok(netdev)) {
2729 adapter->link_speed = 0;
2730 adapter->link_duplex = 0;
527d47c1
AD		 2731 /* Links status message must follow this format */
2732 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2733 netdev->name);
9d5c8243 2734 netif_carrier_off(netdev);
4b1a9877 2735
4ae196df
AD		 2736 igb_ping_all_vfs(adapter);
2737
4b1a9877 2738 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2739 if (!test_bit(__IGB_DOWN, &adapter->state))
2740 mod_timer(&adapter->phy_info_timer,
2741 round_jiffies(jiffies + 2 * HZ));
2742 }
2743 }
2744
2745link_up:
2746 igb_update_stats(adapter);
2747
4b1a9877 2748 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2749 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2750 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2751 adapter->colc_old = adapter->stats.colc;
2752
2753 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2754 adapter->gorc_old = adapter->stats.gorc;
2755 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2756 adapter->gotc_old = adapter->stats.gotc;
2757
2758 igb_update_adaptive(&adapter->hw);
2759
2760 if (!netif_carrier_ok(netdev)) {
c493ea45 2761 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 2762 /* We've lost link, so the controller stops DMA,
2763 * but we've got queued Tx work that's never going
2764 * to get done, so reset controller to flush Tx.
2765 * (Do the reset outside of interrupt context). */
2766 adapter->tx_timeout_count++;
2767 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 2768 /* return immediately since reset is imminent */
2769 return;
9d5c8243
AK		 2770 }
2771 }
2772
2773 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2774 if (adapter->msix_entries) {
2775 for (i = 0; i < adapter->num_rx_queues; i++)
2776 eics |= adapter->rx_ring[i].eims_value;
2777 wr32(E1000_EICS, eics);
2778 } else {
2779 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2780 }
9d5c8243
AK		 2781
2782 /* Force detection of hung controller every watchdog period */
2783 tx_ring->detect_tx_hung = true;
2784
2785 /* Reset the timer */
2786 if (!test_bit(__IGB_DOWN, &adapter->state))
2787 mod_timer(&adapter->watchdog_timer,
2788 round_jiffies(jiffies + 2 * HZ));
2789}
2790
2791enum latency_range {
2792 lowest_latency = 0,
2793 low_latency = 1,
2794 bulk_latency = 2,
2795 latency_invalid = 255
2796};
2797
2798
6eb5a7f1
AD		 2799/**
2800 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2801 *
2802 * Stores a new ITR value based on strictly on packet size. This
2803 * algorithm is less sophisticated than that used in igb_update_itr,
2804 * due to the difficulty of synchronizing statistics across multiple
2805 * receive rings. The divisors and thresholds used by this fuction
2806 * were determined based on theoretical maximum wire speed and testing
2807 * data, in order to minimize response time while increasing bulk
2808 * throughput.
2809 * This functionality is controlled by the InterruptThrottleRate module
2810 * parameter (see igb_param.c)
2811 * NOTE: This function is called only when operating in a multiqueue
2812 * receive environment.
2813 * @rx_ring: pointer to ring
2814 **/
2815static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2816{
6eb5a7f1
AD		 2817 int new_val = rx_ring->itr_val;
2818 int avg_wire_size = 0;
2819 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2820
6eb5a7f1
AD		 2821 if (!rx_ring->total_packets)
2822 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2823
6eb5a7f1
AD		 2824 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2825 * ints/sec - ITR timer value of 120 ticks.
2826 */
2827 if (adapter->link_speed != SPEED_1000) {
2828 new_val = 120;
2829 goto set_itr_val;
9d5c8243 2830 }
6eb5a7f1 2831 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2832
6eb5a7f1
AD		 2833 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2834 avg_wire_size += 24;
2835
2836 /* Don't starve jumbo frames */
2837 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2838
6eb5a7f1
AD		 2839 /* Give a little boost to mid-size frames */
2840 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2841 new_val = avg_wire_size / 3;
2842 else
2843 new_val = avg_wire_size / 2;
9d5c8243 2844
6eb5a7f1 2845set_itr_val:
9d5c8243
AK		 2846 if (new_val != rx_ring->itr_val) {
2847 rx_ring->itr_val = new_val;
6eb5a7f1 2848 rx_ring->set_itr = 1;
9d5c8243 2849 }
6eb5a7f1
AD		 2850clear_counts:
2851 rx_ring->total_bytes = 0;
2852 rx_ring->total_packets = 0;
9d5c8243
AK		 2853}
2854
2855/**
2856 * igb_update_itr - update the dynamic ITR value based on statistics
2857 * Stores a new ITR value based on packets and byte
2858 * counts during the last interrupt. The advantage of per interrupt
2859 * computation is faster updates and more accurate ITR for the current
2860 * traffic pattern. Constants in this function were computed
2861 * based on theoretical maximum wire speed and thresholds were set based
2862 * on testing data as well as attempting to minimize response time
2863 * while increasing bulk throughput.
2864 * this functionality is controlled by the InterruptThrottleRate module
2865 * parameter (see igb_param.c)
2866 * NOTE: These calculations are only valid when operating in a single-
2867 * queue environment.
2868 * @adapter: pointer to adapter
2869 * @itr_setting: current adapter->itr
2870 * @packets: the number of packets during this measurement interval
2871 * @bytes: the number of bytes during this measurement interval
2872 **/
2873static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2874 int packets, int bytes)
2875{
2876 unsigned int retval = itr_setting;
2877
2878 if (packets == 0)
2879 goto update_itr_done;
2880
2881 switch (itr_setting) {
2882 case lowest_latency:
2883 /* handle TSO and jumbo frames */
2884 if (bytes/packets > 8000)
2885 retval = bulk_latency;
2886 else if ((packets < 5) && (bytes > 512))
2887 retval = low_latency;
2888 break;
2889 case low_latency: /* 50 usec aka 20000 ints/s */
2890 if (bytes > 10000) {
2891 /* this if handles the TSO accounting */
2892 if (bytes/packets > 8000) {
2893 retval = bulk_latency;
2894 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2895 retval = bulk_latency;
2896 } else if ((packets > 35)) {
2897 retval = lowest_latency;
2898 }
2899 } else if (bytes/packets > 2000) {
2900 retval = bulk_latency;
2901 } else if (packets <= 2 && bytes < 512) {
2902 retval = lowest_latency;
2903 }
2904 break;
2905 case bulk_latency: /* 250 usec aka 4000 ints/s */
2906 if (bytes > 25000) {
2907 if (packets > 35)
2908 retval = low_latency;
1e5c3d21 2909 } else if (bytes < 1500) {
9d5c8243
AK		 2910 retval = low_latency;
2911 }
2912 break;
2913 }
2914
2915update_itr_done:
2916 return retval;
2917}
2918
6eb5a7f1 2919static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2920{
2921 u16 current_itr;
2922 u32 new_itr = adapter->itr;
2923
2924 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2925 if (adapter->link_speed != SPEED_1000) {
2926 current_itr = 0;
2927 new_itr = 4000;
2928 goto set_itr_now;
2929 }
2930
2931 adapter->rx_itr = igb_update_itr(adapter,
2932 adapter->rx_itr,
2933 adapter->rx_ring->total_packets,
2934 adapter->rx_ring->total_bytes);
9d5c8243 2935
6eb5a7f1 2936 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2937 adapter->tx_itr = igb_update_itr(adapter,
2938 adapter->tx_itr,
2939 adapter->tx_ring->total_packets,
2940 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2941 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2942 } else {
2943 current_itr = adapter->rx_itr;
2944 }
2945
6eb5a7f1 2946 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2947 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2948 current_itr = low_latency;
2949
9d5c8243
AK		 2950 switch (current_itr) {
2951 /* counts and packets in update_itr are dependent on these numbers */
2952 case lowest_latency:
78b1f607 2953 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 2954 break;
2955 case low_latency:
78b1f607 2956 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 2957 break;
2958 case bulk_latency:
78b1f607 2959 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 2960 break;
2961 default:
2962 break;
2963 }
2964
2965set_itr_now:
6eb5a7f1
AD		 2966 adapter->rx_ring->total_bytes = 0;
2967 adapter->rx_ring->total_packets = 0;
2968 if (adapter->rx_ring->buddy) {
2969 adapter->rx_ring->buddy->total_bytes = 0;
2970 adapter->rx_ring->buddy->total_packets = 0;
2971 }
2972
9d5c8243
AK		 2973 if (new_itr != adapter->itr) {
2974 /* this attempts to bias the interrupt rate towards Bulk
2975 * by adding intermediate steps when interrupt rate is
2976 * increasing */
2977 new_itr = new_itr > adapter->itr ?
78b1f607
AD		 2978 max((new_itr * adapter->itr) /
2979 (new_itr + (adapter->itr >> 2)), new_itr) :
9d5c8243
AK		 2980 new_itr;
2981 /* Don't write the value here; it resets the adapter's
2982 * internal timer, and causes us to delay far longer than
2983 * we should between interrupts. Instead, we write the ITR
2984 * value at the beginning of the next interrupt so the timing
2985 * ends up being correct.
2986 */
2987 adapter->itr = new_itr;
78b1f607 2988 adapter->rx_ring->itr_val = new_itr;
6eb5a7f1 2989 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2990 }
2991
2992 return;
2993}
2994
2995
2996#define IGB_TX_FLAGS_CSUM 0x00000001
2997#define IGB_TX_FLAGS_VLAN 0x00000002
2998#define IGB_TX_FLAGS_TSO 0x00000004
2999#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3000#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3001#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3002#define IGB_TX_FLAGS_VLAN_SHIFT 16
3003
3004static inline int igb_tso_adv(struct igb_adapter *adapter,
3005 struct igb_ring *tx_ring,
3006 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3007{
3008 struct e1000_adv_tx_context_desc *context_desc;
3009 unsigned int i;
3010 int err;
3011 struct igb_buffer *buffer_info;
3012 u32 info = 0, tu_cmd = 0;
3013 u32 mss_l4len_idx, l4len;
3014 *hdr_len = 0;
3015
3016 if (skb_header_cloned(skb)) {
3017 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3018 if (err)
3019 return err;
3020 }
3021
3022 l4len = tcp_hdrlen(skb);
3023 *hdr_len += l4len;
3024
3025 if (skb->protocol == htons(ETH_P_IP)) {
3026 struct iphdr *iph = ip_hdr(skb);
3027 iph->tot_len = 0;
3028 iph->check = 0;
3029 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3030 iph->daddr, 0,
3031 IPPROTO_TCP,
3032 0);
3033 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3034 ipv6_hdr(skb)->payload_len = 0;
3035 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3036 &ipv6_hdr(skb)->daddr,
3037 0, IPPROTO_TCP, 0);
3038 }
3039
3040 i = tx_ring->next_to_use;
3041
3042 buffer_info = &tx_ring->buffer_info[i];
3043 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3044 /* VLAN MACLEN IPLEN */
3045 if (tx_flags & IGB_TX_FLAGS_VLAN)
3046 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3047 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3048 *hdr_len += skb_network_offset(skb);
3049 info |= skb_network_header_len(skb);
3050 *hdr_len += skb_network_header_len(skb);
3051 context_desc->vlan_macip_lens = cpu_to_le32(info);
3052
3053 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3054 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3055
3056 if (skb->protocol == htons(ETH_P_IP))
3057 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3058 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3059
3060 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3061
3062 /* MSS L4LEN IDX */
3063 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3064 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3065
73cd78f1 3066 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3067 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3068 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3069
3070 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3071 context_desc->seqnum_seed = 0;
3072
3073 buffer_info->time_stamp = jiffies;
0e014cb1 3074 buffer_info->next_to_watch = i;
9d5c8243
AK		 3075 buffer_info->dma = 0;
3076 i++;
3077 if (i == tx_ring->count)
3078 i = 0;
3079
3080 tx_ring->next_to_use = i;
3081
3082 return true;
3083}
3084
3085static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3086 struct igb_ring *tx_ring,
3087 struct sk_buff *skb, u32 tx_flags)
3088{
3089 struct e1000_adv_tx_context_desc *context_desc;
3090 unsigned int i;
3091 struct igb_buffer *buffer_info;
3092 u32 info = 0, tu_cmd = 0;
3093
3094 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3095 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3096 i = tx_ring->next_to_use;
3097 buffer_info = &tx_ring->buffer_info[i];
3098 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3099
3100 if (tx_flags & IGB_TX_FLAGS_VLAN)
3101 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3102 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3103 if (skb->ip_summed == CHECKSUM_PARTIAL)
3104 info |= skb_network_header_len(skb);
3105
3106 context_desc->vlan_macip_lens = cpu_to_le32(info);
3107
3108 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3109
3110 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3111 __be16 protocol;
3112
3113 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3114 const struct vlan_ethhdr *vhdr =
3115 (const struct vlan_ethhdr*)skb->data;
3116
3117 protocol = vhdr->h_vlan_encapsulated_proto;
3118 } else {
3119 protocol = skb->protocol;
3120 }
3121
3122 switch (protocol) {
09640e63 3123 case cpu_to_be16(ETH_P_IP):
9d5c8243 3124 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3125 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3126 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3127 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3128 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3129 break;
09640e63 3130 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3131 /* XXX what about other V6 headers?? */
3132 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3133 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3134 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3135 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3136 break;
3137 default:
3138 if (unlikely(net_ratelimit()))
3139 dev_warn(&adapter->pdev->dev,
3140 "partial checksum but proto=%x!\n",
3141 skb->protocol);
3142 break;
3143 }
9d5c8243
AK		 3144 }
3145
3146 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3147 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3148 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3149 context_desc->mss_l4len_idx =
3150 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3151 else
3152 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3153
3154 buffer_info->time_stamp = jiffies;
0e014cb1 3155 buffer_info->next_to_watch = i;
9d5c8243
AK		 3156 buffer_info->dma = 0;
3157
3158 i++;
3159 if (i == tx_ring->count)
3160 i = 0;
3161 tx_ring->next_to_use = i;
3162
3163 return true;
3164 }
9d5c8243
AK		 3165 return false;
3166}
3167
3168#define IGB_MAX_TXD_PWR 16
3169#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3170
3171static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3172 struct igb_ring *tx_ring, struct sk_buff *skb,
3173 unsigned int first)
9d5c8243
AK		 3174{
3175 struct igb_buffer *buffer_info;
3176 unsigned int len = skb_headlen(skb);
3177 unsigned int count = 0, i;
3178 unsigned int f;
65689fef 3179 dma_addr_t *map;
9d5c8243
AK		 3180
3181 i = tx_ring->next_to_use;
3182
65689fef
AD		 3183 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3184 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3185 return 0;
3186 }
3187
3188 map = skb_shinfo(skb)->dma_maps;
3189
9d5c8243
AK		 3190 buffer_info = &tx_ring->buffer_info[i];
3191 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3192 buffer_info->length = len;
3193 /* set time_stamp *before* dma to help avoid a possible race */
3194 buffer_info->time_stamp = jiffies;
0e014cb1 3195 buffer_info->next_to_watch = i;
042a53a9 3196 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3197
3198 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3199 struct skb_frag_struct *frag;
3200
65689fef
AD		 3201 i++;
3202 if (i == tx_ring->count)
3203 i = 0;
3204
9d5c8243
AK		 3205 frag = &skb_shinfo(skb)->frags[f];
3206 len = frag->size;
3207
3208 buffer_info = &tx_ring->buffer_info[i];
3209 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3210 buffer_info->length = len;
3211 buffer_info->time_stamp = jiffies;
0e014cb1 3212 buffer_info->next_to_watch = i;
65689fef 3213 buffer_info->dma = map[count];
9d5c8243 3214 count++;
9d5c8243
AK		 3215 }
3216
9d5c8243 3217 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3218 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3219
042a53a9 3220 return count + 1;
9d5c8243
AK		 3221}
3222
3223static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3224 struct igb_ring *tx_ring,
3225 int tx_flags, int count, u32 paylen,
3226 u8 hdr_len)
3227{
3228 union e1000_adv_tx_desc *tx_desc = NULL;
3229 struct igb_buffer *buffer_info;
3230 u32 olinfo_status = 0, cmd_type_len;
3231 unsigned int i;
3232
3233 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3234 E1000_ADVTXD_DCMD_DEXT);
3235
3236 if (tx_flags & IGB_TX_FLAGS_VLAN)
3237 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3238
33af6bcc
PO		 3239 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3240 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3241
9d5c8243
AK		 3242 if (tx_flags & IGB_TX_FLAGS_TSO) {
3243 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3244
3245 /* insert tcp checksum */
3246 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3247
3248 /* insert ip checksum */
3249 if (tx_flags & IGB_TX_FLAGS_IPV4)
3250 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3251
3252 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3253 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3254 }
3255
7dfc16fa
AD		 3256 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3257 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3258 IGB_TX_FLAGS_VLAN)))
661086df 3259 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3260
3261 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3262
3263 i = tx_ring->next_to_use;
3264 while (count--) {
3265 buffer_info = &tx_ring->buffer_info[i];
3266 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3267 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3268 tx_desc->read.cmd_type_len =
3269 cpu_to_le32(cmd_type_len | buffer_info->length);
3270 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3271 i++;
3272 if (i == tx_ring->count)
3273 i = 0;
3274 }
3275
3276 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3277 /* Force memory writes to complete before letting h/w
3278 * know there are new descriptors to fetch. (Only
3279 * applicable for weak-ordered memory model archs,
3280 * such as IA-64). */
3281 wmb();
3282
3283 tx_ring->next_to_use = i;
3284 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3285 /* we need this if more than one processor can write to our tail
3286 * at a time, it syncronizes IO on IA64/Altix systems */
3287 mmiowb();
3288}
3289
3290static int __igb_maybe_stop_tx(struct net_device *netdev,
3291 struct igb_ring *tx_ring, int size)
3292{
3293 struct igb_adapter *adapter = netdev_priv(netdev);
3294
661086df 3295 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3296
9d5c8243
AK		 3297 /* Herbert's original patch had:
3298 * smp_mb__after_netif_stop_queue();
3299 * but since that doesn't exist yet, just open code it. */
3300 smp_mb();
3301
3302 /* We need to check again in a case another CPU has just
3303 * made room available. */
c493ea45 3304 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3305 return -EBUSY;
3306
3307 /* A reprieve! */
661086df 3308 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3309 ++adapter->restart_queue;
3310 return 0;
3311}
3312
3313static int igb_maybe_stop_tx(struct net_device *netdev,
3314 struct igb_ring *tx_ring, int size)
3315{
c493ea45 3316 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3317 return 0;
3318 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3319}
3320
3b29a56d
SH		 3321static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3322 struct net_device *netdev,
3323 struct igb_ring *tx_ring)
9d5c8243
AK		 3324{
3325 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3326 unsigned int first;
9d5c8243 3327 unsigned int tx_flags = 0;
9d5c8243 3328 u8 hdr_len = 0;
65689fef 3329 int count = 0;
9d5c8243 3330 int tso = 0;
33af6bcc 3331 union skb_shared_tx *shtx;
9d5c8243 3332
9d5c8243
AK		 3333 if (test_bit(__IGB_DOWN, &adapter->state)) {
3334 dev_kfree_skb_any(skb);
3335 return NETDEV_TX_OK;
3336 }
3337
3338 if (skb->len <= 0) {
3339 dev_kfree_skb_any(skb);
3340 return NETDEV_TX_OK;
3341 }
3342
9d5c8243
AK		 3343 /* need: 1 descriptor per page,
3344 * + 2 desc gap to keep tail from touching head,
3345 * + 1 desc for skb->data,
3346 * + 1 desc for context descriptor,
3347 * otherwise try next time */
3348 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3349 /* this is a hard error */
9d5c8243
AK		 3350 return NETDEV_TX_BUSY;
3351 }
33af6bcc
PO		 3352
3353 /*
3354 * TODO: check that there currently is no other packet with
3355 * time stamping in the queue
3356 *
3357 * When doing time stamping, keep the connection to the socket
3358 * a while longer: it is still needed by skb_hwtstamp_tx(),
3359 * called either in igb_tx_hwtstamp() or by our caller when
3360 * doing software time stamping.
3361 */
3362 shtx = skb_tx(skb);
3363 if (unlikely(shtx->hardware)) {
3364 shtx->in_progress = 1;
3365 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3366 }
9d5c8243
AK		 3367
3368 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3369 tx_flags |= IGB_TX_FLAGS_VLAN;
3370 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3371 }
3372
661086df
PWJ		 3373 if (skb->protocol == htons(ETH_P_IP))
3374 tx_flags |= IGB_TX_FLAGS_IPV4;
3375
0e014cb1 3376 first = tx_ring->next_to_use;
9d5c8243
AK		 3377 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3378 &hdr_len) : 0;
3379
3380 if (tso < 0) {
3381 dev_kfree_skb_any(skb);
9d5c8243
AK		 3382 return NETDEV_TX_OK;
3383 }
3384
3385 if (tso)
3386 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3387 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3388 (skb->ip_summed == CHECKSUM_PARTIAL))
3389 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3390
65689fef
AD		 3391 /*
3392 * count reflects descriptors mapped, if 0 then mapping error
3393 * has occured and we need to rewind the descriptor queue
3394 */
3395 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3396
3397 if (count) {
3398 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3399 skb->len, hdr_len);
65689fef
AD		 3400 /* Make sure there is space in the ring for the next send. */
3401 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3402 } else {
3403 dev_kfree_skb_any(skb);
3404 tx_ring->buffer_info[first].time_stamp = 0;
3405 tx_ring->next_to_use = first;
3406 }
9d5c8243 3407
9d5c8243
AK		 3408 return NETDEV_TX_OK;
3409}
3410
3b29a56d
SH		 3411static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3412 struct net_device *netdev)
9d5c8243
AK		 3413{
3414 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3415 struct igb_ring *tx_ring;
3416
661086df 3417 int r_idx = 0;
1bfaf07b 3418 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3419 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3420
3421 /* This goes back to the question of how to logically map a tx queue
3422 * to a flow. Right now, performance is impacted slightly negatively
3423 * if using multiple tx queues. If the stack breaks away from a
3424 * single qdisc implementation, we can look at this again. */
3b29a56d 3425 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3426}
3427
3428/**
3429 * igb_tx_timeout - Respond to a Tx Hang
3430 * @netdev: network interface device structure
3431 **/
3432static void igb_tx_timeout(struct net_device *netdev)
3433{
3434 struct igb_adapter *adapter = netdev_priv(netdev);
3435 struct e1000_hw *hw = &adapter->hw;
3436
3437 /* Do the reset outside of interrupt context */
3438 adapter->tx_timeout_count++;
3439 schedule_work(&adapter->reset_task);
265de409
AD		 3440 wr32(E1000_EICS,
3441 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3442}
3443
3444static void igb_reset_task(struct work_struct *work)
3445{
3446 struct igb_adapter *adapter;
3447 adapter = container_of(work, struct igb_adapter, reset_task);
3448
3449 igb_reinit_locked(adapter);
3450}
3451
3452/**
3453 * igb_get_stats - Get System Network Statistics
3454 * @netdev: network interface device structure
3455 *
3456 * Returns the address of the device statistics structure.
3457 * The statistics are actually updated from the timer callback.
3458 **/
73cd78f1 3459static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3460{
3461 struct igb_adapter *adapter = netdev_priv(netdev);
3462
3463 /* only return the current stats */
3464 return &adapter->net_stats;
3465}
3466
3467/**
3468 * igb_change_mtu - Change the Maximum Transfer Unit
3469 * @netdev: network interface device structure
3470 * @new_mtu: new value for maximum frame size
3471 *
3472 * Returns 0 on success, negative on failure
3473 **/
3474static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3475{
3476 struct igb_adapter *adapter = netdev_priv(netdev);
3477 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3478
3479 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3480 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3481 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3482 return -EINVAL;
3483 }
3484
9d5c8243
AK		 3485 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3486 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3487 return -EINVAL;
3488 }
3489
3490 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3491 msleep(1);
73cd78f1 3492
9d5c8243
AK		 3493 /* igb_down has a dependency on max_frame_size */
3494 adapter->max_frame_size = max_frame;
3495 if (netif_running(netdev))
3496 igb_down(adapter);
3497
3498 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3499 * means we reserve 2 more, this pushes us to allocate from the next
3500 * larger slab size.
3501 * i.e. RXBUFFER_2048 --> size-4096 slab
3502 */
3503
3504 if (max_frame <= IGB_RXBUFFER_256)
3505 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3506 else if (max_frame <= IGB_RXBUFFER_512)
3507 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3508 else if (max_frame <= IGB_RXBUFFER_1024)
3509 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3510 else if (max_frame <= IGB_RXBUFFER_2048)
3511 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3512 else
bf36c1a0
AD		 3513#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3514 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3515#else
3516 adapter->rx_buffer_len = PAGE_SIZE / 2;
3517#endif
e1739522
AD		 3518
3519 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3520 if (adapter->vfs_allocated_count &&
3521 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3522 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3523
9d5c8243
AK		 3524 /* adjust allocation if LPE protects us, and we aren't using SBP */
3525 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3526 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3527 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3528
3529 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3530 netdev->mtu, new_mtu);
3531 netdev->mtu = new_mtu;
3532
3533 if (netif_running(netdev))
3534 igb_up(adapter);
3535 else
3536 igb_reset(adapter);
3537
3538 clear_bit(__IGB_RESETTING, &adapter->state);
3539
3540 return 0;
3541}
3542
3543/**
3544 * igb_update_stats - Update the board statistics counters
3545 * @adapter: board private structure
3546 **/
3547
3548void igb_update_stats(struct igb_adapter *adapter)
3549{
3550 struct e1000_hw *hw = &adapter->hw;
3551 struct pci_dev *pdev = adapter->pdev;
3552 u16 phy_tmp;
3553
3554#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3555
3556 /*
3557 * Prevent stats update while adapter is being reset, or if the pci
3558 * connection is down.
3559 */
3560 if (adapter->link_speed == 0)
3561 return;
3562 if (pci_channel_offline(pdev))
3563 return;
3564
3565 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3566 adapter->stats.gprc += rd32(E1000_GPRC);
3567 adapter->stats.gorc += rd32(E1000_GORCL);
3568 rd32(E1000_GORCH); /* clear GORCL */
3569 adapter->stats.bprc += rd32(E1000_BPRC);
3570 adapter->stats.mprc += rd32(E1000_MPRC);
3571 adapter->stats.roc += rd32(E1000_ROC);
3572
3573 adapter->stats.prc64 += rd32(E1000_PRC64);
3574 adapter->stats.prc127 += rd32(E1000_PRC127);
3575 adapter->stats.prc255 += rd32(E1000_PRC255);
3576 adapter->stats.prc511 += rd32(E1000_PRC511);
3577 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3578 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3579 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3580 adapter->stats.sec += rd32(E1000_SEC);
3581
3582 adapter->stats.mpc += rd32(E1000_MPC);
3583 adapter->stats.scc += rd32(E1000_SCC);
3584 adapter->stats.ecol += rd32(E1000_ECOL);
3585 adapter->stats.mcc += rd32(E1000_MCC);
3586 adapter->stats.latecol += rd32(E1000_LATECOL);
3587 adapter->stats.dc += rd32(E1000_DC);
3588 adapter->stats.rlec += rd32(E1000_RLEC);
3589 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3590 adapter->stats.xontxc += rd32(E1000_XONTXC);
3591 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3592 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3593 adapter->stats.fcruc += rd32(E1000_FCRUC);
3594 adapter->stats.gptc += rd32(E1000_GPTC);
3595 adapter->stats.gotc += rd32(E1000_GOTCL);
3596 rd32(E1000_GOTCH); /* clear GOTCL */
3597 adapter->stats.rnbc += rd32(E1000_RNBC);
3598 adapter->stats.ruc += rd32(E1000_RUC);
3599 adapter->stats.rfc += rd32(E1000_RFC);
3600 adapter->stats.rjc += rd32(E1000_RJC);
3601 adapter->stats.tor += rd32(E1000_TORH);
3602 adapter->stats.tot += rd32(E1000_TOTH);
3603 adapter->stats.tpr += rd32(E1000_TPR);
3604
3605 adapter->stats.ptc64 += rd32(E1000_PTC64);
3606 adapter->stats.ptc127 += rd32(E1000_PTC127);
3607 adapter->stats.ptc255 += rd32(E1000_PTC255);
3608 adapter->stats.ptc511 += rd32(E1000_PTC511);
3609 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3610 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3611
3612 adapter->stats.mptc += rd32(E1000_MPTC);
3613 adapter->stats.bptc += rd32(E1000_BPTC);
3614
3615 /* used for adaptive IFS */
3616
3617 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3618 adapter->stats.tpt += hw->mac.tx_packet_delta;
3619 hw->mac.collision_delta = rd32(E1000_COLC);
3620 adapter->stats.colc += hw->mac.collision_delta;
3621
3622 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3623 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3624 adapter->stats.tncrs += rd32(E1000_TNCRS);
3625 adapter->stats.tsctc += rd32(E1000_TSCTC);
3626 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3627
3628 adapter->stats.iac += rd32(E1000_IAC);
3629 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3630 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3631 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3632 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3633 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3634 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3635 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3636 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3637
3638 /* Fill out the OS statistics structure */
3639 adapter->net_stats.multicast = adapter->stats.mprc;
3640 adapter->net_stats.collisions = adapter->stats.colc;
3641
3642 /* Rx Errors */
3643
8c0ab70a
JDB		 3644 if (hw->mac.type != e1000_82575) {
3645 u32 rqdpc_tmp;
3ea73afa 3646 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3647 int i;
3648 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3649 * Queue Drop Packet Count) stats only gets incremented, if
3650 * the DROP_EN but it set (in the SRRCTL register for that
3651 * queue). If DROP_EN bit is NOT set, then the some what
3652 * equivalent count is stored in RNBC (not per queue basis).
3653 * Also note the drop count is due to lack of available
3654 * descriptors.
3655 */
3656 for (i = 0; i < adapter->num_rx_queues; i++) {
3657 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3658 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3659 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3660 }
3ea73afa 3661 adapter->net_stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3662 }
3663
3ea73afa
JDB		 3664 /* Note RNBC (Receive No Buffers Count) is an not an exact
3665 * drop count as the hardware FIFO might save the day. Thats
3666 * one of the reason for saving it in rx_fifo_errors, as its
3667 * potentially not a true drop.
3668 */
3669 adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3670
9d5c8243 3671 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3672 * our own version based on RUC and ROC */
9d5c8243
AK		 3673 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3674 adapter->stats.crcerrs + adapter->stats.algnerrc +
3675 adapter->stats.ruc + adapter->stats.roc +
3676 adapter->stats.cexterr;
3677 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3678 adapter->stats.roc;
3679 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3680 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3681 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3682
3683 /* Tx Errors */
3684 adapter->net_stats.tx_errors = adapter->stats.ecol +
3685 adapter->stats.latecol;
3686 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3687 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3688 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3689
3690 /* Tx Dropped needs to be maintained elsewhere */
3691
3692 /* Phy Stats */
3693 if (hw->phy.media_type == e1000_media_type_copper) {
3694 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3695 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3696 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3697 adapter->phy_stats.idle_errors += phy_tmp;
3698 }
3699 }
3700
3701 /* Management Stats */
3702 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3703 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3704 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3705}
3706
9d5c8243
AK		 3707static irqreturn_t igb_msix_other(int irq, void *data)
3708{
3709 struct net_device *netdev = data;
3710 struct igb_adapter *adapter = netdev_priv(netdev);
3711 struct e1000_hw *hw = &adapter->hw;
844290e5 3712 u32 icr = rd32(E1000_ICR);
9d5c8243 3713
844290e5 3714 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3715
3716 if(icr & E1000_ICR_DOUTSYNC) {
3717 /* HW is reporting DMA is out of sync */
3718 adapter->stats.doosync++;
3719 }
eebbbdba 3720
4ae196df
AD		 3721 /* Check for a mailbox event */
3722 if (icr & E1000_ICR_VMMB)
3723 igb_msg_task(adapter);
3724
3725 if (icr & E1000_ICR_LSC) {
3726 hw->mac.get_link_status = 1;
3727 /* guard against interrupt when we're going down */
3728 if (!test_bit(__IGB_DOWN, &adapter->state))
3729 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3730 }
3731
3732 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3733 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3734
3735 return IRQ_HANDLED;
3736}
3737
3738static irqreturn_t igb_msix_tx(int irq, void *data)
3739{
3740 struct igb_ring *tx_ring = data;
3741 struct igb_adapter *adapter = tx_ring->adapter;
3742 struct e1000_hw *hw = &adapter->hw;
3743
421e02f0 3744#ifdef CONFIG_IGB_DCA
7dfc16fa 3745 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3746 igb_update_tx_dca(tx_ring);
3747#endif
73cd78f1 3748
9d5c8243
AK		 3749 tx_ring->total_bytes = 0;
3750 tx_ring->total_packets = 0;
661086df
PWJ		 3751
3752 /* auto mask will automatically reenable the interrupt when we write
3753 * EICS */
3b644cf6 3754 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3755 /* Ring was not completely cleaned, so fire another interrupt */
3756 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3757 else
9d5c8243 3758 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3759
9d5c8243
AK		 3760 return IRQ_HANDLED;
3761}
3762
6eb5a7f1
AD		 3763static void igb_write_itr(struct igb_ring *ring)
3764{
3765 struct e1000_hw *hw = &ring->adapter->hw;
3766 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3767 switch (hw->mac.type) {
3768 case e1000_82576:
73cd78f1 3769 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3770 0x80000000);
3771 break;
3772 default:
73cd78f1 3773 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3774 (ring->itr_val << 16));
3775 break;
3776 }
3777 ring->set_itr = 0;
3778 }
3779}
3780
9d5c8243
AK		 3781static irqreturn_t igb_msix_rx(int irq, void *data)
3782{
3783 struct igb_ring *rx_ring = data;
9d5c8243 3784
844290e5
PW		 3785 /* Write the ITR value calculated at the end of the
3786 * previous interrupt.
3787 */
9d5c8243 3788
6eb5a7f1 3789 igb_write_itr(rx_ring);
9d5c8243 3790
288379f0
BH		 3791 if (napi_schedule_prep(&rx_ring->napi))
3792 __napi_schedule(&rx_ring->napi);
844290e5 3793
421e02f0 3794#ifdef CONFIG_IGB_DCA
8d253320 3795 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3796 igb_update_rx_dca(rx_ring);
3797#endif
3798 return IRQ_HANDLED;
3799}
3800
421e02f0 3801#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3802static void igb_update_rx_dca(struct igb_ring *rx_ring)
3803{
3804 u32 dca_rxctrl;
3805 struct igb_adapter *adapter = rx_ring->adapter;
3806 struct e1000_hw *hw = &adapter->hw;
3807 int cpu = get_cpu();
26bc19ec 3808 int q = rx_ring->reg_idx;
fe4506b6
JC		 3809
3810 if (rx_ring->cpu != cpu) {
3811 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3812 if (hw->mac.type == e1000_82576) {
3813 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
92be7917 3814 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3815 E1000_DCA_RXCTRL_CPUID_SHIFT;
3816 } else {
3817 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 3818 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3819 }
fe4506b6
JC		 3820 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3821 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3822 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3823 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3824 rx_ring->cpu = cpu;
3825 }
3826 put_cpu();
3827}
3828
3829static void igb_update_tx_dca(struct igb_ring *tx_ring)
3830{
3831 u32 dca_txctrl;
3832 struct igb_adapter *adapter = tx_ring->adapter;
3833 struct e1000_hw *hw = &adapter->hw;
3834 int cpu = get_cpu();
26bc19ec 3835 int q = tx_ring->reg_idx;
fe4506b6
JC		 3836
3837 if (tx_ring->cpu != cpu) {
3838 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3839 if (hw->mac.type == e1000_82576) {
3840 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
92be7917 3841 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3842 E1000_DCA_TXCTRL_CPUID_SHIFT;
3843 } else {
3844 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
92be7917 3845 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3846 }
fe4506b6
JC		 3847 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3848 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3849 tx_ring->cpu = cpu;
3850 }
3851 put_cpu();
3852}
3853
3854static void igb_setup_dca(struct igb_adapter *adapter)
3855{
7e0e99ef 3856 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 3857 int i;
3858
7dfc16fa 3859 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3860 return;
3861
7e0e99ef
AD		 3862 /* Always use CB2 mode, difference is masked in the CB driver. */
3863 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3864
fe4506b6
JC		 3865 for (i = 0; i < adapter->num_tx_queues; i++) {
3866 adapter->tx_ring[i].cpu = -1;
3867 igb_update_tx_dca(&adapter->tx_ring[i]);
3868 }
3869 for (i = 0; i < adapter->num_rx_queues; i++) {
3870 adapter->rx_ring[i].cpu = -1;
3871 igb_update_rx_dca(&adapter->rx_ring[i]);
3872 }
3873}
3874
3875static int __igb_notify_dca(struct device *dev, void *data)
3876{
3877 struct net_device *netdev = dev_get_drvdata(dev);
3878 struct igb_adapter *adapter = netdev_priv(netdev);
3879 struct e1000_hw *hw = &adapter->hw;
3880 unsigned long event = *(unsigned long *)data;
3881
3882 switch (event) {
3883 case DCA_PROVIDER_ADD:
3884 /* if already enabled, don't do it again */
7dfc16fa 3885 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3886 break;
fe4506b6
JC		 3887 /* Always use CB2 mode, difference is masked
3888 * in the CB driver. */
cbd347ad 3889 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3890 if (dca_add_requester(dev) == 0) {
bbd98fe4 3891 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3892 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3893 igb_setup_dca(adapter);
3894 break;
3895 }
3896 /* Fall Through since DCA is disabled. */
3897 case DCA_PROVIDER_REMOVE:
7dfc16fa 3898 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3899 /* without this a class_device is left
3900 * hanging around in the sysfs model */
3901 dca_remove_requester(dev);
3902 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3903 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3904 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3905 }
3906 break;
3907 }
bbd98fe4 3908
fe4506b6 3909 return 0;
9d5c8243
AK		 3910}
3911
fe4506b6
JC		 3912static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3913 void *p)
3914{
3915 int ret_val;
3916
3917 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3918 __igb_notify_dca);
3919
3920 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3921}
421e02f0 3922#endif /* CONFIG_IGB_DCA */
9d5c8243 3923
4ae196df
AD		 3924static void igb_ping_all_vfs(struct igb_adapter *adapter)
3925{
3926 struct e1000_hw *hw = &adapter->hw;
3927 u32 ping;
3928 int i;
3929
3930 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3931 ping = E1000_PF_CONTROL_MSG;
3932 if (adapter->vf_data[i].clear_to_send)
3933 ping |= E1000_VT_MSGTYPE_CTS;
3934 igb_write_mbx(hw, &ping, 1, i);
3935 }
3936}
3937
3938static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3939 u32 *msgbuf, u32 vf)
3940{
3941 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3942 u16 *hash_list = (u16 *)&msgbuf[1];
3943 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3944 int i;
3945
3946 /* only up to 30 hash values supported */
3947 if (n > 30)
3948 n = 30;
3949
3950 /* salt away the number of multi cast addresses assigned
3951 * to this VF for later use to restore when the PF multi cast
3952 * list changes
3953 */
3954 vf_data->num_vf_mc_hashes = n;
3955
3956 /* VFs are limited to using the MTA hash table for their multicast
3957 * addresses */
3958 for (i = 0; i < n; i++)
3959 vf_data->vf_mc_hashes[i] = hash_list[i];;
3960
3961 /* Flush and reset the mta with the new values */
ff41f8dc 3962 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 3963
3964 return 0;
3965}
3966
3967static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3968{
3969 struct e1000_hw *hw = &adapter->hw;
3970 struct vf_data_storage *vf_data;
3971 int i, j;
3972
3973 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3974 vf_data = &adapter->vf_data[i];
75f4f382 3975 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 3976 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3977 }
3978}
3979
3980static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3981{
3982 struct e1000_hw *hw = &adapter->hw;
3983 u32 pool_mask, reg, vid;
3984 int i;
3985
3986 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3987
3988 /* Find the vlan filter for this id */
3989 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3990 reg = rd32(E1000_VLVF(i));
3991
3992 /* remove the vf from the pool */
3993 reg &= ~pool_mask;
3994
3995 /* if pool is empty then remove entry from vfta */
3996 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3997 (reg & E1000_VLVF_VLANID_ENABLE)) {
3998 reg = 0;
3999 vid = reg & E1000_VLVF_VLANID_MASK;
4000 igb_vfta_set(hw, vid, false);
4001 }
4002
4003 wr32(E1000_VLVF(i), reg);
4004 }
4005}
4006
4007static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4008{
4009 struct e1000_hw *hw = &adapter->hw;
4010 u32 reg, i;
4011
4012 /* It is an error to call this function when VFs are not enabled */
4013 if (!adapter->vfs_allocated_count)
4014 return -1;
4015
4016 /* Find the vlan filter for this id */
4017 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4018 reg = rd32(E1000_VLVF(i));
4019 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4020 vid == (reg & E1000_VLVF_VLANID_MASK))
4021 break;
4022 }
4023
4024 if (add) {
4025 if (i == E1000_VLVF_ARRAY_SIZE) {
4026 /* Did not find a matching VLAN ID entry that was
4027 * enabled. Search for a free filter entry, i.e.
4028 * one without the enable bit set
4029 */
4030 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4031 reg = rd32(E1000_VLVF(i));
4032 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4033 break;
4034 }
4035 }
4036 if (i < E1000_VLVF_ARRAY_SIZE) {
4037 /* Found an enabled/available entry */
4038 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4039
4040 /* if !enabled we need to set this up in vfta */
4041 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4042 /* add VID to filter table, if bit already set
4043 * PF must have added it outside of table */
4044 if (igb_vfta_set(hw, vid, true))
4045 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4046 adapter->vfs_allocated_count);
4ae196df
AD		 4047 reg |= E1000_VLVF_VLANID_ENABLE;
4048 }
cad6d05f
AD		 4049 reg &= ~E1000_VLVF_VLANID_MASK;
4050 reg |= vid;
4ae196df
AD		 4051
4052 wr32(E1000_VLVF(i), reg);
4053 return 0;
4054 }
4055 } else {
4056 if (i < E1000_VLVF_ARRAY_SIZE) {
4057 /* remove vf from the pool */
4058 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4059 /* if pool is empty then remove entry from vfta */
4060 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4061 reg = 0;
4062 igb_vfta_set(hw, vid, false);
4063 }
4064 wr32(E1000_VLVF(i), reg);
4065 return 0;
4066 }
4067 }
4068 return -1;
4069}
4070
4071static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4072{
4073 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4074 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4075
4076 return igb_vlvf_set(adapter, vid, add, vf);
4077}
4078
4079static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4080{
4081 struct e1000_hw *hw = &adapter->hw;
4082
4083 /* disable mailbox functionality for vf */
4084 adapter->vf_data[vf].clear_to_send = false;
4085
4086 /* reset offloads to defaults */
4087 igb_set_vmolr(hw, vf);
4088
4089 /* reset vlans for device */
4090 igb_clear_vf_vfta(adapter, vf);
4091
4092 /* reset multicast table array for vf */
4093 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4094
4095 /* Flush and reset the mta with the new values */
ff41f8dc 4096 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4097}
4098
4099static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4100{
4101 struct e1000_hw *hw = &adapter->hw;
4102 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4103 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4104 u32 reg, msgbuf[3];
4105 u8 *addr = (u8 *)(&msgbuf[1]);
4106
4107 /* process all the same items cleared in a function level reset */
4108 igb_vf_reset_event(adapter, vf);
4109
4110 /* set vf mac address */
ff41f8dc
AD		 4111 igb_rar_set(hw, vf_mac, rar_entry);
4112 igb_set_rah_pool(hw, vf, rar_entry);
4ae196df
AD		 4113
4114 /* enable transmit and receive for vf */
4115 reg = rd32(E1000_VFTE);
4116 wr32(E1000_VFTE, reg | (1 << vf));
4117 reg = rd32(E1000_VFRE);
4118 wr32(E1000_VFRE, reg | (1 << vf));
4119
4120 /* enable mailbox functionality for vf */
4121 adapter->vf_data[vf].clear_to_send = true;
4122
4123 /* reply to reset with ack and vf mac address */
4124 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4125 memcpy(addr, vf_mac, 6);
4126 igb_write_mbx(hw, msgbuf, 3, vf);
4127}
4128
4129static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4130{
4131 unsigned char *addr = (char *)&msg[1];
4132 int err = -1;
4133
4134 if (is_valid_ether_addr(addr))
4135 err = igb_set_vf_mac(adapter, vf, addr);
4136
4137 return err;
4138
4139}
4140
4141static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4142{
4143 struct e1000_hw *hw = &adapter->hw;
4144 u32 msg = E1000_VT_MSGTYPE_NACK;
4145
4146 /* if device isn't clear to send it shouldn't be reading either */
4147 if (!adapter->vf_data[vf].clear_to_send)
4148 igb_write_mbx(hw, &msg, 1, vf);
4149}
4150
4151
4152static void igb_msg_task(struct igb_adapter *adapter)
4153{
4154 struct e1000_hw *hw = &adapter->hw;
4155 u32 vf;
4156
4157 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4158 /* process any reset requests */
4159 if (!igb_check_for_rst(hw, vf)) {
4160 adapter->vf_data[vf].clear_to_send = false;
4161 igb_vf_reset_event(adapter, vf);
4162 }
4163
4164 /* process any messages pending */
4165 if (!igb_check_for_msg(hw, vf))
4166 igb_rcv_msg_from_vf(adapter, vf);
4167
4168 /* process any acks */
4169 if (!igb_check_for_ack(hw, vf))
4170 igb_rcv_ack_from_vf(adapter, vf);
4171
4172 }
4173}
4174
4175static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4176{
4177 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4178 u32 msgbuf[mbx_size];
4179 struct e1000_hw *hw = &adapter->hw;
4180 s32 retval;
4181
4182 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4183
4184 if (retval)
4185 dev_err(&adapter->pdev->dev,
4186 "Error receiving message from VF\n");
4187
4188 /* this is a message we already processed, do nothing */
4189 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4190 return retval;
4191
4192 /*
4193 * until the vf completes a reset it should not be
4194 * allowed to start any configuration.
4195 */
4196
4197 if (msgbuf[0] == E1000_VF_RESET) {
4198 igb_vf_reset_msg(adapter, vf);
4199
4200 return retval;
4201 }
4202
4203 if (!adapter->vf_data[vf].clear_to_send) {
4204 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4205 igb_write_mbx(hw, msgbuf, 1, vf);
4206 return retval;
4207 }
4208
4209 switch ((msgbuf[0] & 0xFFFF)) {
4210 case E1000_VF_SET_MAC_ADDR:
4211 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4212 break;
4213 case E1000_VF_SET_MULTICAST:
4214 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4215 break;
4216 case E1000_VF_SET_LPE:
4217 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4218 break;
4219 case E1000_VF_SET_VLAN:
4220 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4221 break;
4222 default:
4223 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4224 retval = -1;
4225 break;
4226 }
4227
4228 /* notify the VF of the results of what it sent us */
4229 if (retval)
4230 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4231 else
4232 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4233
4234 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4235
4236 igb_write_mbx(hw, msgbuf, 1, vf);
4237
4238 return retval;
4239}
4240
9d5c8243
AK		 4241/**
4242 * igb_intr_msi - Interrupt Handler
4243 * @irq: interrupt number
4244 * @data: pointer to a network interface device structure
4245 **/
4246static irqreturn_t igb_intr_msi(int irq, void *data)
4247{
4248 struct net_device *netdev = data;
4249 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4250 struct e1000_hw *hw = &adapter->hw;
4251 /* read ICR disables interrupts using IAM */
4252 u32 icr = rd32(E1000_ICR);
4253
6eb5a7f1 4254 igb_write_itr(adapter->rx_ring);
9d5c8243 4255
dda0e083
AD		 4256 if(icr & E1000_ICR_DOUTSYNC) {
4257 /* HW is reporting DMA is out of sync */
4258 adapter->stats.doosync++;
4259 }
4260
9d5c8243
AK		 4261 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4262 hw->mac.get_link_status = 1;
4263 if (!test_bit(__IGB_DOWN, &adapter->state))
4264 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4265 }
4266
288379f0 4267 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4268
4269 return IRQ_HANDLED;
4270}
4271
4272/**
4a3c6433 4273 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4274 * @irq: interrupt number
4275 * @data: pointer to a network interface device structure
4276 **/
4277static irqreturn_t igb_intr(int irq, void *data)
4278{
4279 struct net_device *netdev = data;
4280 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4281 struct e1000_hw *hw = &adapter->hw;
4282 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4283 * need for the IMC write */
4284 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4285 if (!icr)
4286 return IRQ_NONE; /* Not our interrupt */
4287
6eb5a7f1 4288 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 4289
4290 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4291 * not set, then the adapter didn't send an interrupt */
4292 if (!(icr & E1000_ICR_INT_ASSERTED))
4293 return IRQ_NONE;
4294
dda0e083
AD		 4295 if(icr & E1000_ICR_DOUTSYNC) {
4296 /* HW is reporting DMA is out of sync */
4297 adapter->stats.doosync++;
4298 }
4299
9d5c8243
AK		 4300 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4301 hw->mac.get_link_status = 1;
4302 /* guard against interrupt when we're going down */
4303 if (!test_bit(__IGB_DOWN, &adapter->state))
4304 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4305 }
4306
288379f0 4307 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4308
4309 return IRQ_HANDLED;
4310}
4311
46544258 4312static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 4313{
661086df 4314 struct igb_adapter *adapter = rx_ring->adapter;
46544258 4315 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4316
46544258
AD		 4317 if (adapter->itr_setting & 3) {
4318 if (adapter->num_rx_queues == 1)
6eb5a7f1 4319 igb_set_itr(adapter);
46544258
AD		 4320 else
4321 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 4322 }
4323
46544258
AD		 4324 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4325 if (adapter->msix_entries)
4326 wr32(E1000_EIMS, rx_ring->eims_value);
4327 else
4328 igb_irq_enable(adapter);
4329 }
9d5c8243
AK		 4330}
4331
46544258
AD		 4332/**
4333 * igb_poll - NAPI Rx polling callback
4334 * @napi: napi polling structure
4335 * @budget: count of how many packets we should handle
4336 **/
4337static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 4338{
4339 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
9d5c8243
AK		 4340 int work_done = 0;
4341
421e02f0 4342#ifdef CONFIG_IGB_DCA
bd38e5d1 4343 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 4344 igb_update_rx_dca(rx_ring);
4345#endif
3b644cf6 4346 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 4347
46544258
AD		 4348 if (rx_ring->buddy) {
4349#ifdef CONFIG_IGB_DCA
bd38e5d1 4350 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
46544258
AD		 4351 igb_update_tx_dca(rx_ring->buddy);
4352#endif
4353 if (!igb_clean_tx_irq(rx_ring->buddy))
4354 work_done = budget;
4355 }
4356
9d5c8243 4357 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4358 if (work_done < budget) {
288379f0 4359 napi_complete(napi);
46544258 4360 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 4361 }
4362
46544258 4363 return work_done;
9d5c8243 4364}
6d8126f9 4365
33af6bcc
PO		 4366/**
4367 * igb_hwtstamp - utility function which checks for TX time stamp
4368 * @adapter: board private structure
4369 * @skb: packet that was just sent
4370 *
4371 * If we were asked to do hardware stamping and such a time stamp is
4372 * available, then it must have been for this skb here because we only
4373 * allow only one such packet into the queue.
4374 */
4375static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4376{
4377 union skb_shared_tx *shtx = skb_tx(skb);
4378 struct e1000_hw *hw = &adapter->hw;
4379
4380 if (unlikely(shtx->hardware)) {
4381 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4382 if (valid) {
4383 u64 regval = rd32(E1000_TXSTMPL);
4384 u64 ns;
4385 struct skb_shared_hwtstamps shhwtstamps;
4386
4387 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4388 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4389 ns = timecounter_cyc2time(&adapter->clock,
4390 regval);
4391 timecompare_update(&adapter->compare, ns);
4392 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4393 shhwtstamps.syststamp =
4394 timecompare_transform(&adapter->compare, ns);
4395 skb_tstamp_tx(skb, &shhwtstamps);
4396 }
33af6bcc
PO		 4397 }
4398}
4399
9d5c8243
AK		 4400/**
4401 * igb_clean_tx_irq - Reclaim resources after transmit completes
4402 * @adapter: board private structure
4403 * returns true if ring is completely cleaned
4404 **/
3b644cf6 4405static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 4406{
3b644cf6 4407 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 4408 struct net_device *netdev = adapter->netdev;
0e014cb1 4409 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4410 struct igb_buffer *buffer_info;
4411 struct sk_buff *skb;
0e014cb1 4412 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4413 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4414 unsigned int i, eop, count = 0;
4415 bool cleaned = false;
9d5c8243 4416
9d5c8243 4417 i = tx_ring->next_to_clean;
0e014cb1
AD		 4418 eop = tx_ring->buffer_info[i].next_to_watch;
4419 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4420
4421 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4422 (count < tx_ring->count)) {
4423 for (cleaned = false; !cleaned; count++) {
4424 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4425 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4426 cleaned = (i == eop);
9d5c8243
AK		 4427 skb = buffer_info->skb;
4428
4429 if (skb) {
4430 unsigned int segs, bytecount;
4431 /* gso_segs is currently only valid for tcp */
4432 segs = skb_shinfo(skb)->gso_segs ?: 1;
4433 /* multiply data chunks by size of headers */
4434 bytecount = ((segs - 1) * skb_headlen(skb)) +
4435 skb->len;
4436 total_packets += segs;
4437 total_bytes += bytecount;
33af6bcc
PO		 4438
4439 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4440 }
4441
4442 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4443 tx_desc->wb.status = 0;
9d5c8243
AK		 4444
4445 i++;
4446 if (i == tx_ring->count)
4447 i = 0;
9d5c8243 4448 }
0e014cb1
AD		 4449 eop = tx_ring->buffer_info[i].next_to_watch;
4450 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4451 }
4452
9d5c8243
AK		 4453 tx_ring->next_to_clean = i;
4454
fc7d345d 4455 if (unlikely(count &&
9d5c8243 4456 netif_carrier_ok(netdev) &&
c493ea45 4457 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4458 /* Make sure that anybody stopping the queue after this
4459 * sees the new next_to_clean.
4460 */
4461 smp_mb();
661086df
PWJ		 4462 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4463 !(test_bit(__IGB_DOWN, &adapter->state))) {
4464 netif_wake_subqueue(netdev, tx_ring->queue_index);
4465 ++adapter->restart_queue;
4466 }
9d5c8243
AK		 4467 }
4468
4469 if (tx_ring->detect_tx_hung) {
4470 /* Detect a transmit hang in hardware, this serializes the
4471 * check with the clearing of time_stamp and movement of i */
4472 tx_ring->detect_tx_hung = false;
4473 if (tx_ring->buffer_info[i].time_stamp &&
4474 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4475 (adapter->tx_timeout_factor * HZ))
4476 && !(rd32(E1000_STATUS) &
4477 E1000_STATUS_TXOFF)) {
4478
9d5c8243
AK		 4479 /* detected Tx unit hang */
4480 dev_err(&adapter->pdev->dev,
4481 "Detected Tx Unit Hang\n"
2d064c06 4482 " Tx Queue <%d>\n"
9d5c8243
AK		 4483 " TDH <%x>\n"
4484 " TDT <%x>\n"
4485 " next_to_use <%x>\n"
4486 " next_to_clean <%x>\n"
9d5c8243
AK		 4487 "buffer_info[next_to_clean]\n"
4488 " time_stamp <%lx>\n"
0e014cb1 4489 " next_to_watch <%x>\n"
9d5c8243
AK		 4490 " jiffies <%lx>\n"
4491 " desc.status <%x>\n",
2d064c06 4492 tx_ring->queue_index,
9d5c8243
AK		 4493 readl(adapter->hw.hw_addr + tx_ring->head),
4494 readl(adapter->hw.hw_addr + tx_ring->tail),
4495 tx_ring->next_to_use,
4496 tx_ring->next_to_clean,
9d5c8243 4497 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4498 eop,
9d5c8243 4499 jiffies,
0e014cb1 4500 eop_desc->wb.status);
661086df 4501 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4502 }
4503 }
4504 tx_ring->total_bytes += total_bytes;
4505 tx_ring->total_packets += total_packets;
e21ed353
AD		 4506 tx_ring->tx_stats.bytes += total_bytes;
4507 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 4508 adapter->net_stats.tx_bytes += total_bytes;
4509 adapter->net_stats.tx_packets += total_packets;
0e014cb1 4510 return (count < tx_ring->count);
9d5c8243
AK		 4511}
4512
9d5c8243
AK		 4513/**
4514 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4515 * @ring: pointer to receive ring receving this packet
9d5c8243 4516 * @status: descriptor status field as written by hardware
73cd78f1 4517 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4518 * @skb: pointer to sk_buff to be indicated to stack
4519 **/
d3352520
AD		 4520static void igb_receive_skb(struct igb_ring *ring, u8 status,
4521 union e1000_adv_rx_desc * rx_desc,
4522 struct sk_buff *skb)
4523{
4524 struct igb_adapter * adapter = ring->adapter;
4525 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4526
0c8dfc83 4527 skb_record_rx_queue(skb, ring->queue_index);
182ff8df
AD		 4528 if (vlan_extracted)
4529 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4530 le16_to_cpu(rx_desc->wb.upper.vlan),
4531 skb);
4532 else
4533 napi_gro_receive(&ring->napi, skb);
9d5c8243
AK		 4534}
4535
9d5c8243
AK		 4536static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4537 u32 status_err, struct sk_buff *skb)
4538{
4539 skb->ip_summed = CHECKSUM_NONE;
4540
4541 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4542 if ((status_err & E1000_RXD_STAT_IXSM) ||
4543 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4544 return;
4545 /* TCP/UDP checksum error bit is set */
4546 if (status_err &
4547 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4548 /*
4549 * work around errata with sctp packets where the TCPE aka
4550 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4551 * packets, (aka let the stack check the crc32c)
4552 */
4553 if (!((adapter->hw.mac.type == e1000_82576) &&
4554 (skb->len == 60)))
4555 adapter->hw_csum_err++;
9d5c8243 4556 /* let the stack verify checksum errors */
9d5c8243
AK		 4557 return;
4558 }
4559 /* It must be a TCP or UDP packet with a valid checksum */
4560 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4561 skb->ip_summed = CHECKSUM_UNNECESSARY;
4562
b9473560 4563 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4564 adapter->hw_csum_good++;
4565}
4566
2d94d8ab
AD		 4567static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4568 union e1000_adv_rx_desc *rx_desc)
4569{
4570 /* HW will not DMA in data larger than the given buffer, even if it
4571 * parses the (NFS, of course) header to be larger. In that case, it
4572 * fills the header buffer and spills the rest into the page.
4573 */
4574 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4575 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4576 if (hlen > adapter->rx_ps_hdr_size)
4577 hlen = adapter->rx_ps_hdr_size;
4578 return hlen;
4579}
4580
3b644cf6
MW		 4581static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4582 int *work_done, int budget)
9d5c8243 4583{
3b644cf6 4584 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4585 struct net_device *netdev = adapter->netdev;
33af6bcc 4586 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4587 struct pci_dev *pdev = adapter->pdev;
4588 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4589 struct igb_buffer *buffer_info , *next_buffer;
4590 struct sk_buff *skb;
9d5c8243
AK		 4591 bool cleaned = false;
4592 int cleaned_count = 0;
4593 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4594 unsigned int i;
2d94d8ab
AD		 4595 u32 staterr;
4596 u16 length;
9d5c8243
AK		 4597
4598 i = rx_ring->next_to_clean;
69d3ca53 4599 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4600 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4601 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4602
4603 while (staterr & E1000_RXD_STAT_DD) {
4604 if (*work_done >= budget)
4605 break;
4606 (*work_done)++;
9d5c8243 4607
69d3ca53
AD		 4608 skb = buffer_info->skb;
4609 prefetch(skb->data - NET_IP_ALIGN);
4610 buffer_info->skb = NULL;
4611
4612 i++;
4613 if (i == rx_ring->count)
4614 i = 0;
4615 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4616 prefetch(next_rxd);
4617 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4618
4619 length = le16_to_cpu(rx_desc->wb.upper.length);
4620 cleaned = true;
4621 cleaned_count++;
4622
91615f76 4623 /* this is the fast path for the non-packet split case */
bf36c1a0
AD		 4624 if (!adapter->rx_ps_hdr_size) {
4625 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4626 adapter->rx_buffer_len,
bf36c1a0 4627 PCI_DMA_FROMDEVICE);
91615f76 4628 buffer_info->dma = 0;
bf36c1a0
AD		 4629 skb_put(skb, length);
4630 goto send_up;
9d5c8243
AK		 4631 }
4632
2d94d8ab
AD		 4633 if (buffer_info->dma) {
4634 u16 hlen = igb_get_hlen(adapter, rx_desc);
bf36c1a0 4635 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4636 adapter->rx_ps_hdr_size,
bf36c1a0 4637 PCI_DMA_FROMDEVICE);
91615f76 4638 buffer_info->dma = 0;
bf36c1a0
AD		 4639 skb_put(skb, hlen);
4640 }
4641
4642 if (length) {
9d5c8243 4643 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4644 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4645 buffer_info->page_dma = 0;
bf36c1a0
AD		 4646
4647 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4648 buffer_info->page,
4649 buffer_info->page_offset,
4650 length);
4651
4652 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4653 (page_count(buffer_info->page) != 1))
4654 buffer_info->page = NULL;
4655 else
4656 get_page(buffer_info->page);
9d5c8243
AK		 4657
4658 skb->len += length;
4659 skb->data_len += length;
9d5c8243 4660
bf36c1a0 4661 skb->truesize += length;
9d5c8243 4662 }
9d5c8243 4663
bf36c1a0 4664 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4665 buffer_info->skb = next_buffer->skb;
4666 buffer_info->dma = next_buffer->dma;
4667 next_buffer->skb = skb;
4668 next_buffer->dma = 0;
bf36c1a0
AD		 4669 goto next_desc;
4670 }
69d3ca53 4671send_up:
33af6bcc
PO		 4672 /*
4673 * If this bit is set, then the RX registers contain
4674 * the time stamp. No other packet will be time
4675 * stamped until we read these registers, so read the
4676 * registers to make them available again. Because
4677 * only one packet can be time stamped at a time, we
4678 * know that the register values must belong to this
4679 * one here and therefore we don't need to compare
4680 * any of the additional attributes stored for it.
4681 *
4682 * If nothing went wrong, then it should have a
4683 * skb_shared_tx that we can turn into a
4684 * skb_shared_hwtstamps.
4685 *
4686 * TODO: can time stamping be triggered (thus locking
4687 * the registers) without the packet reaching this point
4688 * here? In that case RX time stamping would get stuck.
4689 *
4690 * TODO: in "time stamp all packets" mode this bit is
4691 * not set. Need a global flag for this mode and then
4692 * always read the registers. Cannot be done without
4693 * a race condition.
4694 */
4695 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4696 u64 regval;
4697 u64 ns;
4698 struct skb_shared_hwtstamps *shhwtstamps =
4699 skb_hwtstamps(skb);
4700
4701 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4702 "igb: no RX time stamp available for time stamped packet");
4703 regval = rd32(E1000_RXSTMPL);
4704 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4705 ns = timecounter_cyc2time(&adapter->clock, regval);
4706 timecompare_update(&adapter->compare, ns);
4707 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4708 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4709 shhwtstamps->syststamp =
4710 timecompare_transform(&adapter->compare, ns);
4711 }
4712
9d5c8243
AK		 4713 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4714 dev_kfree_skb_irq(skb);
4715 goto next_desc;
4716 }
9d5c8243
AK		 4717
4718 total_bytes += skb->len;
4719 total_packets++;
4720
4721 igb_rx_checksum_adv(adapter, staterr, skb);
4722
4723 skb->protocol = eth_type_trans(skb, netdev);
4724
d3352520 4725 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4726
9d5c8243
AK		 4727next_desc:
4728 rx_desc->wb.upper.status_error = 0;
4729
4730 /* return some buffers to hardware, one at a time is too slow */
4731 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4732 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4733 cleaned_count = 0;
4734 }
4735
4736 /* use prefetched values */
4737 rx_desc = next_rxd;
4738 buffer_info = next_buffer;
9d5c8243
AK		 4739 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4740 }
bf36c1a0 4741
9d5c8243 4742 rx_ring->next_to_clean = i;
c493ea45 4743 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 4744
4745 if (cleaned_count)
3b644cf6 4746 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4747
4748 rx_ring->total_packets += total_packets;
4749 rx_ring->total_bytes += total_bytes;
4750 rx_ring->rx_stats.packets += total_packets;
4751 rx_ring->rx_stats.bytes += total_bytes;
4752 adapter->net_stats.rx_bytes += total_bytes;
4753 adapter->net_stats.rx_packets += total_packets;
4754 return cleaned;
4755}
4756
9d5c8243
AK		 4757/**
4758 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4759 * @adapter: address of board private structure
4760 **/
3b644cf6 4761static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4762 int cleaned_count)
4763{
3b644cf6 4764 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4765 struct net_device *netdev = adapter->netdev;
4766 struct pci_dev *pdev = adapter->pdev;
4767 union e1000_adv_rx_desc *rx_desc;
4768 struct igb_buffer *buffer_info;
4769 struct sk_buff *skb;
4770 unsigned int i;
db761762 4771 int bufsz;
9d5c8243
AK		 4772
4773 i = rx_ring->next_to_use;
4774 buffer_info = &rx_ring->buffer_info[i];
4775
db761762
AD		 4776 if (adapter->rx_ps_hdr_size)
4777 bufsz = adapter->rx_ps_hdr_size;
4778 else
4779 bufsz = adapter->rx_buffer_len;
db761762 4780
9d5c8243
AK		 4781 while (cleaned_count--) {
4782 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4783
bf36c1a0 4784 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4785 if (!buffer_info->page) {
bf36c1a0
AD		 4786 buffer_info->page = alloc_page(GFP_ATOMIC);
4787 if (!buffer_info->page) {
4788 adapter->alloc_rx_buff_failed++;
4789 goto no_buffers;
4790 }
4791 buffer_info->page_offset = 0;
4792 } else {
4793 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4794 }
4795 buffer_info->page_dma =
db761762 4796 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4797 buffer_info->page_offset,
4798 PAGE_SIZE / 2,
9d5c8243
AK		 4799 PCI_DMA_FROMDEVICE);
4800 }
4801
4802 if (!buffer_info->skb) {
91615f76 4803 skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
9d5c8243
AK		 4804 if (!skb) {
4805 adapter->alloc_rx_buff_failed++;
4806 goto no_buffers;
4807 }
4808
4809 /* Make buffer alignment 2 beyond a 16 byte boundary
4810 * this will result in a 16 byte aligned IP header after
4811 * the 14 byte MAC header is removed
4812 */
4813 skb_reserve(skb, NET_IP_ALIGN);
4814
4815 buffer_info->skb = skb;
4816 buffer_info->dma = pci_map_single(pdev, skb->data,
4817 bufsz,
4818 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4819 }
4820 /* Refresh the desc even if buffer_addrs didn't change because
4821 * each write-back erases this info. */
4822 if (adapter->rx_ps_hdr_size) {
4823 rx_desc->read.pkt_addr =
4824 cpu_to_le64(buffer_info->page_dma);
4825 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4826 } else {
4827 rx_desc->read.pkt_addr =
4828 cpu_to_le64(buffer_info->dma);
4829 rx_desc->read.hdr_addr = 0;
4830 }
4831
4832 i++;
4833 if (i == rx_ring->count)
4834 i = 0;
4835 buffer_info = &rx_ring->buffer_info[i];
4836 }
4837
4838no_buffers:
4839 if (rx_ring->next_to_use != i) {
4840 rx_ring->next_to_use = i;
4841 if (i == 0)
4842 i = (rx_ring->count - 1);
4843 else
4844 i--;
4845
4846 /* Force memory writes to complete before letting h/w
4847 * know there are new descriptors to fetch. (Only
4848 * applicable for weak-ordered memory model archs,
4849 * such as IA-64). */
4850 wmb();
4851 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4852 }
4853}
4854
4855/**
4856 * igb_mii_ioctl -
4857 * @netdev:
4858 * @ifreq:
4859 * @cmd:
4860 **/
4861static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4862{
4863 struct igb_adapter *adapter = netdev_priv(netdev);
4864 struct mii_ioctl_data *data = if_mii(ifr);
4865
4866 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4867 return -EOPNOTSUPP;
4868
4869 switch (cmd) {
4870 case SIOCGMIIPHY:
4871 data->phy_id = adapter->hw.phy.addr;
4872 break;
4873 case SIOCGMIIREG:
4874 if (!capable(CAP_NET_ADMIN))
4875 return -EPERM;
f5f4cf08
AD		 4876 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4877 &data->val_out))
9d5c8243
AK		 4878 return -EIO;
4879 break;
4880 case SIOCSMIIREG:
4881 default:
4882 return -EOPNOTSUPP;
4883 }
4884 return 0;
4885}
4886
c6cb090b
PO		 4887/**
4888 * igb_hwtstamp_ioctl - control hardware time stamping
4889 * @netdev:
4890 * @ifreq:
4891 * @cmd:
4892 *
33af6bcc
PO		 4893 * Outgoing time stamping can be enabled and disabled. Play nice and
4894 * disable it when requested, although it shouldn't case any overhead
4895 * when no packet needs it. At most one packet in the queue may be
4896 * marked for time stamping, otherwise it would be impossible to tell
4897 * for sure to which packet the hardware time stamp belongs.
4898 *
4899 * Incoming time stamping has to be configured via the hardware
4900 * filters. Not all combinations are supported, in particular event
4901 * type has to be specified. Matching the kind of event packet is
4902 * not supported, with the exception of "all V2 events regardless of
4903 * level 2 or 4".
4904 *
c6cb090b
PO		 4905 **/
4906static int igb_hwtstamp_ioctl(struct net_device *netdev,
4907 struct ifreq *ifr, int cmd)
4908{
33af6bcc
PO		 4909 struct igb_adapter *adapter = netdev_priv(netdev);
4910 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4911 struct hwtstamp_config config;
33af6bcc
PO		 4912 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4913 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4914 u32 tsync_rx_ctl_type = 0;
4915 u32 tsync_rx_cfg = 0;
4916 int is_l4 = 0;
4917 int is_l2 = 0;
4918 short port = 319; /* PTP */
4919 u32 regval;
c6cb090b
PO		 4920
4921 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4922 return -EFAULT;
4923
4924 /* reserved for future extensions */
4925 if (config.flags)
4926 return -EINVAL;
4927
33af6bcc
PO		 4928 switch (config.tx_type) {
4929 case HWTSTAMP_TX_OFF:
4930 tsync_tx_ctl_bit = 0;
4931 break;
4932 case HWTSTAMP_TX_ON:
4933 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4934 break;
4935 default:
4936 return -ERANGE;
4937 }
4938
4939 switch (config.rx_filter) {
4940 case HWTSTAMP_FILTER_NONE:
4941 tsync_rx_ctl_bit = 0;
4942 break;
4943 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4944 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4945 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4946 case HWTSTAMP_FILTER_ALL:
4947 /*
4948 * register TSYNCRXCFG must be set, therefore it is not
4949 * possible to time stamp both Sync and Delay_Req messages
4950 * => fall back to time stamping all packets
4951 */
4952 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4953 config.rx_filter = HWTSTAMP_FILTER_ALL;
4954 break;
4955 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4956 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4957 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4958 is_l4 = 1;
4959 break;
4960 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4961 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4962 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4963 is_l4 = 1;
4964 break;
4965 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4966 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4967 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4968 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4969 is_l2 = 1;
4970 is_l4 = 1;
4971 config.rx_filter = HWTSTAMP_FILTER_SOME;
4972 break;
4973 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4974 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4975 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4976 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4977 is_l2 = 1;
4978 is_l4 = 1;
4979 config.rx_filter = HWTSTAMP_FILTER_SOME;
4980 break;
4981 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4982 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4983 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4984 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4985 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4986 is_l2 = 1;
4987 break;
4988 default:
4989 return -ERANGE;
4990 }
4991
4992 /* enable/disable TX */
4993 regval = rd32(E1000_TSYNCTXCTL);
4994 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4995 wr32(E1000_TSYNCTXCTL, regval);
4996
4997 /* enable/disable RX, define which PTP packets are time stamped */
4998 regval = rd32(E1000_TSYNCRXCTL);
4999 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5000 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5001 wr32(E1000_TSYNCRXCTL, regval);
5002 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5003
5004 /*
5005 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5006 * (Ethertype to filter on)
5007 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5008 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5009 */
5010 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5011
5012 /* L4 Queue Filter[0]: only filter by source and destination port */
5013 wr32(E1000_SPQF0, htons(port));
5014 wr32(E1000_IMIREXT(0), is_l4 ?
5015 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5016 wr32(E1000_IMIR(0), is_l4 ?
5017 (htons(port)
5018 | (0<<16) /* immediate interrupt disabled */
5019 | 0 /* (1<<17) bit cleared: do not bypass
5020 destination port check */)
5021 : 0);
5022 wr32(E1000_FTQF0, is_l4 ?
5023 (0x11 /* UDP */
5024 | (1<<15) /* VF not compared */
5025 | (1<<27) /* Enable Timestamping */
5026 | (7<<28) /* only source port filter enabled,
5027 source/target address and protocol
5028 masked */)
5029 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5030 enabled */));
5031
5032 wrfl();
5033
5034 adapter->hwtstamp_config = config;
5035
5036 /* clear TX/RX time stamp registers, just to be sure */
5037 regval = rd32(E1000_TXSTMPH);
5038 regval = rd32(E1000_RXSTMPH);
c6cb090b 5039
33af6bcc
PO		 5040 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5041 -EFAULT : 0;
c6cb090b
PO		 5042}
5043
9d5c8243
AK		 5044/**
5045 * igb_ioctl -
5046 * @netdev:
5047 * @ifreq:
5048 * @cmd:
5049 **/
5050static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5051{
5052 switch (cmd) {
5053 case SIOCGMIIPHY:
5054 case SIOCGMIIREG:
5055 case SIOCSMIIREG:
5056 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5057 case SIOCSHWTSTAMP:
5058 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5059 default:
5060 return -EOPNOTSUPP;
5061 }
5062}
5063
009bc06e
AD		 5064s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5065{
5066 struct igb_adapter *adapter = hw->back;
5067 u16 cap_offset;
5068
5069 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5070 if (!cap_offset)
5071 return -E1000_ERR_CONFIG;
5072
5073 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5074
5075 return 0;
5076}
5077
5078s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5079{
5080 struct igb_adapter *adapter = hw->back;
5081 u16 cap_offset;
5082
5083 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5084 if (!cap_offset)
5085 return -E1000_ERR_CONFIG;
5086
5087 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5088
5089 return 0;
5090}
5091
9d5c8243
AK		 5092static void igb_vlan_rx_register(struct net_device *netdev,
5093 struct vlan_group *grp)
5094{
5095 struct igb_adapter *adapter = netdev_priv(netdev);
5096 struct e1000_hw *hw = &adapter->hw;
5097 u32 ctrl, rctl;
5098
5099 igb_irq_disable(adapter);
5100 adapter->vlgrp = grp;
5101
5102 if (grp) {
5103 /* enable VLAN tag insert/strip */
5104 ctrl = rd32(E1000_CTRL);
5105 ctrl |= E1000_CTRL_VME;
5106 wr32(E1000_CTRL, ctrl);
5107
5108 /* enable VLAN receive filtering */
5109 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5110 rctl &= ~E1000_RCTL_CFIEN;
5111 wr32(E1000_RCTL, rctl);
5112 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5113 } else {
5114 /* disable VLAN tag insert/strip */
5115 ctrl = rd32(E1000_CTRL);
5116 ctrl &= ~E1000_CTRL_VME;
5117 wr32(E1000_CTRL, ctrl);
5118
9d5c8243
AK		 5119 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5120 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5121 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5122 }
9d5c8243
AK		 5123 }
5124
e1739522
AD		 5125 igb_rlpml_set(adapter);
5126
9d5c8243
AK		 5127 if (!test_bit(__IGB_DOWN, &adapter->state))
5128 igb_irq_enable(adapter);
5129}
5130
5131static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5132{
5133 struct igb_adapter *adapter = netdev_priv(netdev);
5134 struct e1000_hw *hw = &adapter->hw;
4ae196df 5135 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5136
28b0759c 5137 if ((hw->mng_cookie.status &
9d5c8243
AK		 5138 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5139 (vid == adapter->mng_vlan_id))
5140 return;
4ae196df
AD		 5141
5142 /* add vid to vlvf if sr-iov is enabled,
5143 * if that fails add directly to filter table */
5144 if (igb_vlvf_set(adapter, vid, true, pf_id))
5145 igb_vfta_set(hw, vid, true);
5146
9d5c8243
AK		 5147}
5148
5149static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5150{
5151 struct igb_adapter *adapter = netdev_priv(netdev);
5152 struct e1000_hw *hw = &adapter->hw;
4ae196df 5153 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5154
5155 igb_irq_disable(adapter);
5156 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5157
5158 if (!test_bit(__IGB_DOWN, &adapter->state))
5159 igb_irq_enable(adapter);
5160
5161 if ((adapter->hw.mng_cookie.status &
5162 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5163 (vid == adapter->mng_vlan_id)) {
5164 /* release control to f/w */
5165 igb_release_hw_control(adapter);
5166 return;
5167 }
5168
4ae196df
AD		 5169 /* remove vid from vlvf if sr-iov is enabled,
5170 * if not in vlvf remove from vfta */
5171 if (igb_vlvf_set(adapter, vid, false, pf_id))
5172 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5173}
5174
5175static void igb_restore_vlan(struct igb_adapter *adapter)
5176{
5177 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5178
5179 if (adapter->vlgrp) {
5180 u16 vid;
5181 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5182 if (!vlan_group_get_device(adapter->vlgrp, vid))
5183 continue;
5184 igb_vlan_rx_add_vid(adapter->netdev, vid);
5185 }
5186 }
5187}
5188
5189int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5190{
5191 struct e1000_mac_info *mac = &adapter->hw.mac;
5192
5193 mac->autoneg = 0;
5194
9d5c8243
AK		 5195 switch (spddplx) {
5196 case SPEED_10 + DUPLEX_HALF:
5197 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5198 break;
5199 case SPEED_10 + DUPLEX_FULL:
5200 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5201 break;
5202 case SPEED_100 + DUPLEX_HALF:
5203 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5204 break;
5205 case SPEED_100 + DUPLEX_FULL:
5206 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5207 break;
5208 case SPEED_1000 + DUPLEX_FULL:
5209 mac->autoneg = 1;
5210 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5211 break;
5212 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5213 default:
5214 dev_err(&adapter->pdev->dev,
5215 "Unsupported Speed/Duplex configuration\n");
5216 return -EINVAL;
5217 }
5218 return 0;
5219}
5220
3fe7c4c9 5221static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5222{
5223 struct net_device *netdev = pci_get_drvdata(pdev);
5224 struct igb_adapter *adapter = netdev_priv(netdev);
5225 struct e1000_hw *hw = &adapter->hw;
2d064c06 5226 u32 ctrl, rctl, status;
9d5c8243
AK		 5227 u32 wufc = adapter->wol;
5228#ifdef CONFIG_PM
5229 int retval = 0;
5230#endif
5231
5232 netif_device_detach(netdev);
5233
a88f10ec
AD		 5234 if (netif_running(netdev))
5235 igb_close(netdev);
5236
5237 igb_reset_interrupt_capability(adapter);
5238
5239 igb_free_queues(adapter);
9d5c8243
AK		 5240
5241#ifdef CONFIG_PM
5242 retval = pci_save_state(pdev);
5243 if (retval)
5244 return retval;
5245#endif
5246
5247 status = rd32(E1000_STATUS);
5248 if (status & E1000_STATUS_LU)
5249 wufc &= ~E1000_WUFC_LNKC;
5250
5251 if (wufc) {
5252 igb_setup_rctl(adapter);
ff41f8dc 5253 igb_set_rx_mode(netdev);
9d5c8243
AK		 5254
5255 /* turn on all-multi mode if wake on multicast is enabled */
5256 if (wufc & E1000_WUFC_MC) {
5257 rctl = rd32(E1000_RCTL);
5258 rctl |= E1000_RCTL_MPE;
5259 wr32(E1000_RCTL, rctl);
5260 }
5261
5262 ctrl = rd32(E1000_CTRL);
5263 /* advertise wake from D3Cold */
5264 #define E1000_CTRL_ADVD3WUC 0x00100000
5265 /* phy power management enable */
5266 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5267 ctrl |= E1000_CTRL_ADVD3WUC;
5268 wr32(E1000_CTRL, ctrl);
5269
9d5c8243
AK		 5270 /* Allow time for pending master requests to run */
5271 igb_disable_pcie_master(&adapter->hw);
5272
5273 wr32(E1000_WUC, E1000_WUC_PME_EN);
5274 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5275 } else {
5276 wr32(E1000_WUC, 0);
5277 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5278 }
5279
3fe7c4c9
RW		 5280 *enable_wake = wufc || adapter->en_mng_pt;
5281 if (!*enable_wake)
2d064c06 5282 igb_shutdown_fiber_serdes_link_82575(hw);
9d5c8243
AK		 5283
5284 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5285 * would have already happened in close and is redundant. */
5286 igb_release_hw_control(adapter);
5287
5288 pci_disable_device(pdev);
5289
9d5c8243
AK		 5290 return 0;
5291}
5292
5293#ifdef CONFIG_PM
3fe7c4c9
RW		 5294static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5295{
5296 int retval;
5297 bool wake;
5298
5299 retval = __igb_shutdown(pdev, &wake);
5300 if (retval)
5301 return retval;
5302
5303 if (wake) {
5304 pci_prepare_to_sleep(pdev);
5305 } else {
5306 pci_wake_from_d3(pdev, false);
5307 pci_set_power_state(pdev, PCI_D3hot);
5308 }
5309
5310 return 0;
5311}
5312
9d5c8243
AK		 5313static int igb_resume(struct pci_dev *pdev)
5314{
5315 struct net_device *netdev = pci_get_drvdata(pdev);
5316 struct igb_adapter *adapter = netdev_priv(netdev);
5317 struct e1000_hw *hw = &adapter->hw;
5318 u32 err;
5319
5320 pci_set_power_state(pdev, PCI_D0);
5321 pci_restore_state(pdev);
42bfd33a 5322
aed5dec3 5323 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5324 if (err) {
5325 dev_err(&pdev->dev,
5326 "igb: Cannot enable PCI device from suspend\n");
5327 return err;
5328 }
5329 pci_set_master(pdev);
5330
5331 pci_enable_wake(pdev, PCI_D3hot, 0);
5332 pci_enable_wake(pdev, PCI_D3cold, 0);
5333
a88f10ec
AD		 5334 igb_set_interrupt_capability(adapter);
5335
5336 if (igb_alloc_queues(adapter)) {
5337 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5338 return -ENOMEM;
9d5c8243
AK		 5339 }
5340
5341 /* e1000_power_up_phy(adapter); */
5342
5343 igb_reset(adapter);
a8564f03
AD		 5344
5345 /* let the f/w know that the h/w is now under the control of the
5346 * driver. */
5347 igb_get_hw_control(adapter);
5348
9d5c8243
AK		 5349 wr32(E1000_WUS, ~0);
5350
a88f10ec
AD		 5351 if (netif_running(netdev)) {
5352 err = igb_open(netdev);
5353 if (err)
5354 return err;
5355 }
9d5c8243
AK		 5356
5357 netif_device_attach(netdev);
5358
9d5c8243
AK		 5359 return 0;
5360}
5361#endif
5362
5363static void igb_shutdown(struct pci_dev *pdev)
5364{
3fe7c4c9
RW		 5365 bool wake;
5366
5367 __igb_shutdown(pdev, &wake);
5368
5369 if (system_state == SYSTEM_POWER_OFF) {
5370 pci_wake_from_d3(pdev, wake);
5371 pci_set_power_state(pdev, PCI_D3hot);
5372 }
9d5c8243
AK		 5373}
5374
5375#ifdef CONFIG_NET_POLL_CONTROLLER
5376/*
5377 * Polling 'interrupt' - used by things like netconsole to send skbs
5378 * without having to re-enable interrupts. It's not called while
5379 * the interrupt routine is executing.
5380 */
5381static void igb_netpoll(struct net_device *netdev)
5382{
5383 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5384 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5385 int i;
9d5c8243 5386
eebbbdba
AD		 5387 if (!adapter->msix_entries) {
5388 igb_irq_disable(adapter);
5389 napi_schedule(&adapter->rx_ring[0].napi);
5390 return;
5391 }
9d5c8243 5392
eebbbdba
AD		 5393 for (i = 0; i < adapter->num_tx_queues; i++) {
5394 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5395 wr32(E1000_EIMC, tx_ring->eims_value);
5396 igb_clean_tx_irq(tx_ring);
5397 wr32(E1000_EIMS, tx_ring->eims_value);
5398 }
9d5c8243 5399
eebbbdba
AD		 5400 for (i = 0; i < adapter->num_rx_queues; i++) {
5401 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5402 wr32(E1000_EIMC, rx_ring->eims_value);
5403 napi_schedule(&rx_ring->napi);
5404 }
9d5c8243
AK		 5405}
5406#endif /* CONFIG_NET_POLL_CONTROLLER */
5407
5408/**
5409 * igb_io_error_detected - called when PCI error is detected
5410 * @pdev: Pointer to PCI device
5411 * @state: The current pci connection state
5412 *
5413 * This function is called after a PCI bus error affecting
5414 * this device has been detected.
5415 */
5416static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5417 pci_channel_state_t state)
5418{
5419 struct net_device *netdev = pci_get_drvdata(pdev);
5420 struct igb_adapter *adapter = netdev_priv(netdev);
5421
5422 netif_device_detach(netdev);
5423
59ed6eec
AD		 5424 if (state == pci_channel_io_perm_failure)
5425 return PCI_ERS_RESULT_DISCONNECT;
5426
9d5c8243
AK		 5427 if (netif_running(netdev))
5428 igb_down(adapter);
5429 pci_disable_device(pdev);
5430
5431 /* Request a slot slot reset. */
5432 return PCI_ERS_RESULT_NEED_RESET;
5433}
5434
5435/**
5436 * igb_io_slot_reset - called after the pci bus has been reset.
5437 * @pdev: Pointer to PCI device
5438 *
5439 * Restart the card from scratch, as if from a cold-boot. Implementation
5440 * resembles the first-half of the igb_resume routine.
5441 */
5442static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5443{
5444 struct net_device *netdev = pci_get_drvdata(pdev);
5445 struct igb_adapter *adapter = netdev_priv(netdev);
5446 struct e1000_hw *hw = &adapter->hw;
40a914fa 5447 pci_ers_result_t result;
42bfd33a 5448 int err;
9d5c8243 5449
aed5dec3 5450 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5451 dev_err(&pdev->dev,
5452 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5453 result = PCI_ERS_RESULT_DISCONNECT;
5454 } else {
5455 pci_set_master(pdev);
5456 pci_restore_state(pdev);
9d5c8243 5457
40a914fa
AD		 5458 pci_enable_wake(pdev, PCI_D3hot, 0);
5459 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5460
40a914fa
AD		 5461 igb_reset(adapter);
5462 wr32(E1000_WUS, ~0);
5463 result = PCI_ERS_RESULT_RECOVERED;
5464 }
9d5c8243 5465
ea943d41
JK		 5466 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5467 if (err) {
5468 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5469 "failed 0x%0x\n", err);
5470 /* non-fatal, continue */
5471 }
40a914fa
AD		 5472
5473 return result;
9d5c8243
AK		 5474}
5475
5476/**
5477 * igb_io_resume - called when traffic can start flowing again.
5478 * @pdev: Pointer to PCI device
5479 *
5480 * This callback is called when the error recovery driver tells us that
5481 * its OK to resume normal operation. Implementation resembles the
5482 * second-half of the igb_resume routine.
5483 */
5484static void igb_io_resume(struct pci_dev *pdev)
5485{
5486 struct net_device *netdev = pci_get_drvdata(pdev);
5487 struct igb_adapter *adapter = netdev_priv(netdev);
5488
9d5c8243
AK		 5489 if (netif_running(netdev)) {
5490 if (igb_up(adapter)) {
5491 dev_err(&pdev->dev, "igb_up failed after reset\n");
5492 return;
5493 }
5494 }
5495
5496 netif_device_attach(netdev);
5497
5498 /* let the f/w know that the h/w is now under the control of the
5499 * driver. */
5500 igb_get_hw_control(adapter);
9d5c8243
AK		 5501}
5502
4ae196df
AD		 5503static int igb_set_vf_mac(struct igb_adapter *adapter,
5504 int vf, unsigned char *mac_addr)
5505{
5506 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5507 /* VF MAC addresses start at end of receive addresses and moves
5508 * torwards the first, as a result a collision should not be possible */
5509 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5510
37680117 5511 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5512
ff41f8dc 5513 igb_rar_set(hw, mac_addr, rar_entry);
4ae196df
AD		 5514 igb_set_rah_pool(hw, vf, rar_entry);
5515
5516 return 0;
5517}
5518
5519static void igb_vmm_control(struct igb_adapter *adapter)
5520{
5521 struct e1000_hw *hw = &adapter->hw;
5522 u32 reg_data;
5523
5524 if (!adapter->vfs_allocated_count)
5525 return;
5526
5527 /* VF's need PF reset indication before they
5528 * can send/receive mail */
5529 reg_data = rd32(E1000_CTRL_EXT);
5530 reg_data |= E1000_CTRL_EXT_PFRSTD;
5531 wr32(E1000_CTRL_EXT, reg_data);
5532
5533 igb_vmdq_set_loopback_pf(hw, true);
5534 igb_vmdq_set_replication_pf(hw, true);
5535}
5536
9d5c8243 5537/* igb_main.c */
Clone of davem's net-next-2.6 tree