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CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
fe4506b6
JC		 44#ifdef CONFIG_DCA
45#include <linux/dca.h>
46#endif
9d5c8243
AK		 47#include "igb.h"
48
0024fd00 49#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 50char igb_driver_name[] = "igb";
51char igb_driver_version[] = DRV_VERSION;
52static const char igb_driver_string[] =
53 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 54static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 55
9d5c8243
AK		 56static const struct e1000_info *igb_info_tbl[] = {
57 [board_82575] = &e1000_82575_info,
58};
59
60static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
68 /* required last entry */
69 {0, }
70};
71
72MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
73
74void igb_reset(struct igb_adapter *);
75static int igb_setup_all_tx_resources(struct igb_adapter *);
76static int igb_setup_all_rx_resources(struct igb_adapter *);
77static void igb_free_all_tx_resources(struct igb_adapter *);
78static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 79static void igb_free_tx_resources(struct igb_ring *);
80static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
fe4506b6
JC		 110#ifdef CONFIG_DCA
111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
114#endif /* CONFIG_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
d3352520
AD		 119#ifdef CONFIG_IGB_LRO
120static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
121#endif
9d5c8243
AK		 122static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
123static void igb_tx_timeout(struct net_device *);
124static void igb_reset_task(struct work_struct *);
125static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
126static void igb_vlan_rx_add_vid(struct net_device *, u16);
127static void igb_vlan_rx_kill_vid(struct net_device *, u16);
128static void igb_restore_vlan(struct igb_adapter *);
129
130static int igb_suspend(struct pci_dev *, pm_message_t);
131#ifdef CONFIG_PM
132static int igb_resume(struct pci_dev *);
133#endif
134static void igb_shutdown(struct pci_dev *);
fe4506b6
JC		 135#ifdef CONFIG_DCA
136static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
137static struct notifier_block dca_notifier = {
138 .notifier_call = igb_notify_dca,
139 .next = NULL,
140 .priority = 0
141};
142#endif
9d5c8243
AK		 143
144#ifdef CONFIG_NET_POLL_CONTROLLER
145/* for netdump / net console */
146static void igb_netpoll(struct net_device *);
147#endif
148
149static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
150 pci_channel_state_t);
151static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
152static void igb_io_resume(struct pci_dev *);
153
154static struct pci_error_handlers igb_err_handler = {
155 .error_detected = igb_io_error_detected,
156 .slot_reset = igb_io_slot_reset,
157 .resume = igb_io_resume,
158};
159
160
161static struct pci_driver igb_driver = {
162 .name = igb_driver_name,
163 .id_table = igb_pci_tbl,
164 .probe = igb_probe,
165 .remove = __devexit_p(igb_remove),
166#ifdef CONFIG_PM
167 /* Power Managment Hooks */
168 .suspend = igb_suspend,
169 .resume = igb_resume,
170#endif
171 .shutdown = igb_shutdown,
172 .err_handler = &igb_err_handler
173};
174
7dfc16fa
AD		 175static int global_quad_port_a; /* global quad port a indication */
176
9d5c8243
AK		 177MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
178MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
179MODULE_LICENSE("GPL");
180MODULE_VERSION(DRV_VERSION);
181
182#ifdef DEBUG
183/**
184 * igb_get_hw_dev_name - return device name string
185 * used by hardware layer to print debugging information
186 **/
187char *igb_get_hw_dev_name(struct e1000_hw *hw)
188{
189 struct igb_adapter *adapter = hw->back;
190 return adapter->netdev->name;
191}
192#endif
193
194/**
195 * igb_init_module - Driver Registration Routine
196 *
197 * igb_init_module is the first routine called when the driver is
198 * loaded. All it does is register with the PCI subsystem.
199 **/
200static int __init igb_init_module(void)
201{
202 int ret;
203 printk(KERN_INFO "%s - version %s\n",
204 igb_driver_string, igb_driver_version);
205
206 printk(KERN_INFO "%s\n", igb_copyright);
207
7dfc16fa
AD		 208 global_quad_port_a = 0;
209
9d5c8243 210 ret = pci_register_driver(&igb_driver);
fe4506b6
JC		 211#ifdef CONFIG_DCA
212 dca_register_notify(&dca_notifier);
213#endif
9d5c8243
AK		 214 return ret;
215}
216
217module_init(igb_init_module);
218
219/**
220 * igb_exit_module - Driver Exit Cleanup Routine
221 *
222 * igb_exit_module is called just before the driver is removed
223 * from memory.
224 **/
225static void __exit igb_exit_module(void)
226{
fe4506b6
JC		 227#ifdef CONFIG_DCA
228 dca_unregister_notify(&dca_notifier);
229#endif
9d5c8243
AK		 230 pci_unregister_driver(&igb_driver);
231}
232
233module_exit(igb_exit_module);
234
235/**
236 * igb_alloc_queues - Allocate memory for all rings
237 * @adapter: board private structure to initialize
238 *
239 * We allocate one ring per queue at run-time since we don't know the
240 * number of queues at compile-time.
241 **/
242static int igb_alloc_queues(struct igb_adapter *adapter)
243{
244 int i;
245
246 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
247 sizeof(struct igb_ring), GFP_KERNEL);
248 if (!adapter->tx_ring)
249 return -ENOMEM;
250
251 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
252 sizeof(struct igb_ring), GFP_KERNEL);
253 if (!adapter->rx_ring) {
254 kfree(adapter->tx_ring);
255 return -ENOMEM;
256 }
257
6eb5a7f1
AD		 258 adapter->rx_ring->buddy = adapter->tx_ring;
259
661086df
PWJ		 260 for (i = 0; i < adapter->num_tx_queues; i++) {
261 struct igb_ring *ring = &(adapter->tx_ring[i]);
262 ring->adapter = adapter;
263 ring->queue_index = i;
264 }
9d5c8243
AK		 265 for (i = 0; i < adapter->num_rx_queues; i++) {
266 struct igb_ring *ring = &(adapter->rx_ring[i]);
267 ring->adapter = adapter;
844290e5 268 ring->queue_index = i;
9d5c8243
AK		 269 ring->itr_register = E1000_ITR;
270
844290e5 271 /* set a default napi handler for each rx_ring */
661086df 272 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 273 }
274 return 0;
275}
276
a88f10ec
AD		 277static void igb_free_queues(struct igb_adapter *adapter)
278{
279 int i;
280
281 for (i = 0; i < adapter->num_rx_queues; i++)
282 netif_napi_del(&adapter->rx_ring[i].napi);
283
284 kfree(adapter->tx_ring);
285 kfree(adapter->rx_ring);
286}
287
9d5c8243
AK		 288#define IGB_N0_QUEUE -1
289static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
290 int tx_queue, int msix_vector)
291{
292 u32 msixbm = 0;
293 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 294 u32 ivar, index;
295
296 switch (hw->mac.type) {
297 case e1000_82575:
9d5c8243
AK		 298 /* The 82575 assigns vectors using a bitmask, which matches the
299 bitmask for the EICR/EIMS/EIMC registers. To assign one
300 or more queues to a vector, we write the appropriate bits
301 into the MSIXBM register for that vector. */
302 if (rx_queue > IGB_N0_QUEUE) {
303 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
304 adapter->rx_ring[rx_queue].eims_value = msixbm;
305 }
306 if (tx_queue > IGB_N0_QUEUE) {
307 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
308 adapter->tx_ring[tx_queue].eims_value =
309 E1000_EICR_TX_QUEUE0 << tx_queue;
310 }
311 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 312 break;
313 case e1000_82576:
314 /* Kawela uses a table-based method for assigning vectors.
315 Each queue has a single entry in the table to which we write
316 a vector number along with a "valid" bit. Sadly, the layout
317 of the table is somewhat counterintuitive. */
318 if (rx_queue > IGB_N0_QUEUE) {
319 index = (rx_queue & 0x7);
320 ivar = array_rd32(E1000_IVAR0, index);
321 if (rx_queue < 8) {
322 /* vector goes into low byte of register */
323 ivar = ivar & 0xFFFFFF00;
324 ivar |= msix_vector | E1000_IVAR_VALID;
325 } else {
326 /* vector goes into third byte of register */
327 ivar = ivar & 0xFF00FFFF;
328 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
329 }
330 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
331 array_wr32(E1000_IVAR0, index, ivar);
332 }
333 if (tx_queue > IGB_N0_QUEUE) {
334 index = (tx_queue & 0x7);
335 ivar = array_rd32(E1000_IVAR0, index);
336 if (tx_queue < 8) {
337 /* vector goes into second byte of register */
338 ivar = ivar & 0xFFFF00FF;
339 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
340 } else {
341 /* vector goes into high byte of register */
342 ivar = ivar & 0x00FFFFFF;
343 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
344 }
345 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
346 array_wr32(E1000_IVAR0, index, ivar);
347 }
348 break;
349 default:
350 BUG();
351 break;
352 }
9d5c8243
AK		 353}
354
355/**
356 * igb_configure_msix - Configure MSI-X hardware
357 *
358 * igb_configure_msix sets up the hardware to properly
359 * generate MSI-X interrupts.
360 **/
361static void igb_configure_msix(struct igb_adapter *adapter)
362{
363 u32 tmp;
364 int i, vector = 0;
365 struct e1000_hw *hw = &adapter->hw;
366
367 adapter->eims_enable_mask = 0;
2d064c06
AD		 368 if (hw->mac.type == e1000_82576)
369 /* Turn on MSI-X capability first, or our settings
370 * won't stick. And it will take days to debug. */
371 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
372 E1000_GPIE_PBA | E1000_GPIE_EIAME |
373 E1000_GPIE_NSICR);
9d5c8243
AK		 374
375 for (i = 0; i < adapter->num_tx_queues; i++) {
376 struct igb_ring *tx_ring = &adapter->tx_ring[i];
377 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
378 adapter->eims_enable_mask |= tx_ring->eims_value;
379 if (tx_ring->itr_val)
6eb5a7f1 380 writel(tx_ring->itr_val,
9d5c8243
AK		 381 hw->hw_addr + tx_ring->itr_register);
382 else
383 writel(1, hw->hw_addr + tx_ring->itr_register);
384 }
385
386 for (i = 0; i < adapter->num_rx_queues; i++) {
387 struct igb_ring *rx_ring = &adapter->rx_ring[i];
6eb5a7f1 388 rx_ring->buddy = 0;
9d5c8243
AK		 389 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
390 adapter->eims_enable_mask |= rx_ring->eims_value;
391 if (rx_ring->itr_val)
6eb5a7f1 392 writel(rx_ring->itr_val,
9d5c8243
AK		 393 hw->hw_addr + rx_ring->itr_register);
394 else
395 writel(1, hw->hw_addr + rx_ring->itr_register);
396 }
397
398
399 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 400 switch (hw->mac.type) {
401 case e1000_82575:
9d5c8243
AK		 402 array_wr32(E1000_MSIXBM(0), vector++,
403 E1000_EIMS_OTHER);
404
9d5c8243
AK		 405 tmp = rd32(E1000_CTRL_EXT);
406 /* enable MSI-X PBA support*/
407 tmp |= E1000_CTRL_EXT_PBA_CLR;
408
409 /* Auto-Mask interrupts upon ICR read. */
410 tmp |= E1000_CTRL_EXT_EIAME;
411 tmp |= E1000_CTRL_EXT_IRCA;
412
413 wr32(E1000_CTRL_EXT, tmp);
414 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 415 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 416
2d064c06
AD		 417 break;
418
419 case e1000_82576:
420 tmp = (vector++ | E1000_IVAR_VALID) << 8;
421 wr32(E1000_IVAR_MISC, tmp);
422
423 adapter->eims_enable_mask = (1 << (vector)) - 1;
424 adapter->eims_other = 1 << (vector - 1);
425 break;
426 default:
427 /* do nothing, since nothing else supports MSI-X */
428 break;
429 } /* switch (hw->mac.type) */
9d5c8243
AK		 430 wrfl();
431}
432
433/**
434 * igb_request_msix - Initialize MSI-X interrupts
435 *
436 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
437 * kernel.
438 **/
439static int igb_request_msix(struct igb_adapter *adapter)
440{
441 struct net_device *netdev = adapter->netdev;
442 int i, err = 0, vector = 0;
443
444 vector = 0;
445
446 for (i = 0; i < adapter->num_tx_queues; i++) {
447 struct igb_ring *ring = &(adapter->tx_ring[i]);
448 sprintf(ring->name, "%s-tx%d", netdev->name, i);
449 err = request_irq(adapter->msix_entries[vector].vector,
450 &igb_msix_tx, 0, ring->name,
451 &(adapter->tx_ring[i]));
452 if (err)
453 goto out;
454 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 455 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 456 vector++;
457 }
458 for (i = 0; i < adapter->num_rx_queues; i++) {
459 struct igb_ring *ring = &(adapter->rx_ring[i]);
460 if (strlen(netdev->name) < (IFNAMSIZ - 5))
461 sprintf(ring->name, "%s-rx%d", netdev->name, i);
462 else
463 memcpy(ring->name, netdev->name, IFNAMSIZ);
464 err = request_irq(adapter->msix_entries[vector].vector,
465 &igb_msix_rx, 0, ring->name,
466 &(adapter->rx_ring[i]));
467 if (err)
468 goto out;
469 ring->itr_register = E1000_EITR(0) + (vector << 2);
470 ring->itr_val = adapter->itr;
844290e5
PW		 471 /* overwrite the poll routine for MSIX, we've already done
472 * netif_napi_add */
473 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 474 vector++;
475 }
476
477 err = request_irq(adapter->msix_entries[vector].vector,
478 &igb_msix_other, 0, netdev->name, netdev);
479 if (err)
480 goto out;
481
9d5c8243
AK		 482 igb_configure_msix(adapter);
483 return 0;
484out:
485 return err;
486}
487
488static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
489{
490 if (adapter->msix_entries) {
491 pci_disable_msix(adapter->pdev);
492 kfree(adapter->msix_entries);
493 adapter->msix_entries = NULL;
7dfc16fa 494 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 495 pci_disable_msi(adapter->pdev);
496 return;
497}
498
499
500/**
501 * igb_set_interrupt_capability - set MSI or MSI-X if supported
502 *
503 * Attempt to configure interrupts using the best available
504 * capabilities of the hardware and kernel.
505 **/
506static void igb_set_interrupt_capability(struct igb_adapter *adapter)
507{
508 int err;
509 int numvecs, i;
510
511 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
512 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
513 GFP_KERNEL);
514 if (!adapter->msix_entries)
515 goto msi_only;
516
517 for (i = 0; i < numvecs; i++)
518 adapter->msix_entries[i].entry = i;
519
520 err = pci_enable_msix(adapter->pdev,
521 adapter->msix_entries,
522 numvecs);
523 if (err == 0)
524 return;
525
526 igb_reset_interrupt_capability(adapter);
527
528 /* If we can't do MSI-X, try MSI */
529msi_only:
530 adapter->num_rx_queues = 1;
661086df 531 adapter->num_tx_queues = 1;
9d5c8243 532 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 533 adapter->flags |= IGB_FLAG_HAS_MSI;
661086df 534
661086df 535 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 536 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 537 return;
538}
539
540/**
541 * igb_request_irq - initialize interrupts
542 *
543 * Attempts to configure interrupts using the best available
544 * capabilities of the hardware and kernel.
545 **/
546static int igb_request_irq(struct igb_adapter *adapter)
547{
548 struct net_device *netdev = adapter->netdev;
549 struct e1000_hw *hw = &adapter->hw;
550 int err = 0;
551
552 if (adapter->msix_entries) {
553 err = igb_request_msix(adapter);
844290e5 554 if (!err)
9d5c8243 555 goto request_done;
9d5c8243
AK		 556 /* fall back to MSI */
557 igb_reset_interrupt_capability(adapter);
558 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 559 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 560 igb_free_all_tx_resources(adapter);
561 igb_free_all_rx_resources(adapter);
562 adapter->num_rx_queues = 1;
563 igb_alloc_queues(adapter);
844290e5 564 } else {
2d064c06
AD		 565 switch (hw->mac.type) {
566 case e1000_82575:
567 wr32(E1000_MSIXBM(0),
568 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
569 break;
570 case e1000_82576:
571 wr32(E1000_IVAR0, E1000_IVAR_VALID);
572 break;
573 default:
574 break;
575 }
9d5c8243 576 }
844290e5 577
7dfc16fa 578 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 579 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
580 netdev->name, netdev);
581 if (!err)
582 goto request_done;
583 /* fall back to legacy interrupts */
584 igb_reset_interrupt_capability(adapter);
7dfc16fa 585 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 586 }
587
588 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
589 netdev->name, netdev);
590
6cb5e577 591 if (err)
9d5c8243
AK		 592 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
593 err);
9d5c8243
AK		 594
595request_done:
596 return err;
597}
598
599static void igb_free_irq(struct igb_adapter *adapter)
600{
601 struct net_device *netdev = adapter->netdev;
602
603 if (adapter->msix_entries) {
604 int vector = 0, i;
605
606 for (i = 0; i < adapter->num_tx_queues; i++)
607 free_irq(adapter->msix_entries[vector++].vector,
608 &(adapter->tx_ring[i]));
609 for (i = 0; i < adapter->num_rx_queues; i++)
610 free_irq(adapter->msix_entries[vector++].vector,
611 &(adapter->rx_ring[i]));
612
613 free_irq(adapter->msix_entries[vector++].vector, netdev);
614 return;
615 }
616
617 free_irq(adapter->pdev->irq, netdev);
618}
619
620/**
621 * igb_irq_disable - Mask off interrupt generation on the NIC
622 * @adapter: board private structure
623 **/
624static void igb_irq_disable(struct igb_adapter *adapter)
625{
626 struct e1000_hw *hw = &adapter->hw;
627
628 if (adapter->msix_entries) {
844290e5 629 wr32(E1000_EIAM, 0);
9d5c8243
AK		 630 wr32(E1000_EIMC, ~0);
631 wr32(E1000_EIAC, 0);
632 }
844290e5
PW		 633
634 wr32(E1000_IAM, 0);
9d5c8243
AK		 635 wr32(E1000_IMC, ~0);
636 wrfl();
637 synchronize_irq(adapter->pdev->irq);
638}
639
640/**
641 * igb_irq_enable - Enable default interrupt generation settings
642 * @adapter: board private structure
643 **/
644static void igb_irq_enable(struct igb_adapter *adapter)
645{
646 struct e1000_hw *hw = &adapter->hw;
647
648 if (adapter->msix_entries) {
844290e5
PW		 649 wr32(E1000_EIAC, adapter->eims_enable_mask);
650 wr32(E1000_EIAM, adapter->eims_enable_mask);
651 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 652 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 653 } else {
654 wr32(E1000_IMS, IMS_ENABLE_MASK);
655 wr32(E1000_IAM, IMS_ENABLE_MASK);
656 }
9d5c8243
AK		 657}
658
659static void igb_update_mng_vlan(struct igb_adapter *adapter)
660{
661 struct net_device *netdev = adapter->netdev;
662 u16 vid = adapter->hw.mng_cookie.vlan_id;
663 u16 old_vid = adapter->mng_vlan_id;
664 if (adapter->vlgrp) {
665 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
666 if (adapter->hw.mng_cookie.status &
667 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
668 igb_vlan_rx_add_vid(netdev, vid);
669 adapter->mng_vlan_id = vid;
670 } else
671 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
672
673 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
674 (vid != old_vid) &&
675 !vlan_group_get_device(adapter->vlgrp, old_vid))
676 igb_vlan_rx_kill_vid(netdev, old_vid);
677 } else
678 adapter->mng_vlan_id = vid;
679 }
680}
681
682/**
683 * igb_release_hw_control - release control of the h/w to f/w
684 * @adapter: address of board private structure
685 *
686 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
687 * For ASF and Pass Through versions of f/w this means that the
688 * driver is no longer loaded.
689 *
690 **/
691static void igb_release_hw_control(struct igb_adapter *adapter)
692{
693 struct e1000_hw *hw = &adapter->hw;
694 u32 ctrl_ext;
695
696 /* Let firmware take over control of h/w */
697 ctrl_ext = rd32(E1000_CTRL_EXT);
698 wr32(E1000_CTRL_EXT,
699 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
700}
701
702
703/**
704 * igb_get_hw_control - get control of the h/w from f/w
705 * @adapter: address of board private structure
706 *
707 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
708 * For ASF and Pass Through versions of f/w this means that
709 * the driver is loaded.
710 *
711 **/
712static void igb_get_hw_control(struct igb_adapter *adapter)
713{
714 struct e1000_hw *hw = &adapter->hw;
715 u32 ctrl_ext;
716
717 /* Let firmware know the driver has taken over */
718 ctrl_ext = rd32(E1000_CTRL_EXT);
719 wr32(E1000_CTRL_EXT,
720 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
721}
722
723static void igb_init_manageability(struct igb_adapter *adapter)
724{
725 struct e1000_hw *hw = &adapter->hw;
726
727 if (adapter->en_mng_pt) {
728 u32 manc2h = rd32(E1000_MANC2H);
729 u32 manc = rd32(E1000_MANC);
730
9d5c8243
AK		 731 /* enable receiving management packets to the host */
732 /* this will probably generate destination unreachable messages
733 * from the host OS, but the packets will be handled on SMBUS */
734 manc |= E1000_MANC_EN_MNG2HOST;
735#define E1000_MNG2HOST_PORT_623 (1 << 5)
736#define E1000_MNG2HOST_PORT_664 (1 << 6)
737 manc2h |= E1000_MNG2HOST_PORT_623;
738 manc2h |= E1000_MNG2HOST_PORT_664;
739 wr32(E1000_MANC2H, manc2h);
740
741 wr32(E1000_MANC, manc);
742 }
743}
744
9d5c8243
AK		 745/**
746 * igb_configure - configure the hardware for RX and TX
747 * @adapter: private board structure
748 **/
749static void igb_configure(struct igb_adapter *adapter)
750{
751 struct net_device *netdev = adapter->netdev;
752 int i;
753
754 igb_get_hw_control(adapter);
755 igb_set_multi(netdev);
756
757 igb_restore_vlan(adapter);
758 igb_init_manageability(adapter);
759
760 igb_configure_tx(adapter);
761 igb_setup_rctl(adapter);
762 igb_configure_rx(adapter);
662d7205
AD		 763
764 igb_rx_fifo_flush_82575(&adapter->hw);
765
9d5c8243
AK		 766 /* call IGB_DESC_UNUSED which always leaves
767 * at least 1 descriptor unused to make sure
768 * next_to_use != next_to_clean */
769 for (i = 0; i < adapter->num_rx_queues; i++) {
770 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 771 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 772 }
773
774
775 adapter->tx_queue_len = netdev->tx_queue_len;
776}
777
778
779/**
780 * igb_up - Open the interface and prepare it to handle traffic
781 * @adapter: board private structure
782 **/
783
784int igb_up(struct igb_adapter *adapter)
785{
786 struct e1000_hw *hw = &adapter->hw;
787 int i;
788
789 /* hardware has been reset, we need to reload some things */
790 igb_configure(adapter);
791
792 clear_bit(__IGB_DOWN, &adapter->state);
793
844290e5
PW		 794 for (i = 0; i < adapter->num_rx_queues; i++)
795 napi_enable(&adapter->rx_ring[i].napi);
796 if (adapter->msix_entries)
9d5c8243 797 igb_configure_msix(adapter);
9d5c8243
AK		 798
799 /* Clear any pending interrupts. */
800 rd32(E1000_ICR);
801 igb_irq_enable(adapter);
802
803 /* Fire a link change interrupt to start the watchdog. */
804 wr32(E1000_ICS, E1000_ICS_LSC);
805 return 0;
806}
807
808void igb_down(struct igb_adapter *adapter)
809{
810 struct e1000_hw *hw = &adapter->hw;
811 struct net_device *netdev = adapter->netdev;
812 u32 tctl, rctl;
813 int i;
814
815 /* signal that we're down so the interrupt handler does not
816 * reschedule our watchdog timer */
817 set_bit(__IGB_DOWN, &adapter->state);
818
819 /* disable receives in the hardware */
820 rctl = rd32(E1000_RCTL);
821 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
822 /* flush and sleep below */
823
fd2ea0a7 824 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 825
826 /* disable transmits in the hardware */
827 tctl = rd32(E1000_TCTL);
828 tctl &= ~E1000_TCTL_EN;
829 wr32(E1000_TCTL, tctl);
830 /* flush both disables and wait for them to finish */
831 wrfl();
832 msleep(10);
833
844290e5
PW		 834 for (i = 0; i < adapter->num_rx_queues; i++)
835 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 836
9d5c8243
AK		 837 igb_irq_disable(adapter);
838
839 del_timer_sync(&adapter->watchdog_timer);
840 del_timer_sync(&adapter->phy_info_timer);
841
842 netdev->tx_queue_len = adapter->tx_queue_len;
843 netif_carrier_off(netdev);
844 adapter->link_speed = 0;
845 adapter->link_duplex = 0;
846
3023682e
JK		 847 if (!pci_channel_offline(adapter->pdev))
848 igb_reset(adapter);
9d5c8243
AK		 849 igb_clean_all_tx_rings(adapter);
850 igb_clean_all_rx_rings(adapter);
851}
852
853void igb_reinit_locked(struct igb_adapter *adapter)
854{
855 WARN_ON(in_interrupt());
856 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
857 msleep(1);
858 igb_down(adapter);
859 igb_up(adapter);
860 clear_bit(__IGB_RESETTING, &adapter->state);
861}
862
863void igb_reset(struct igb_adapter *adapter)
864{
865 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 866 struct e1000_mac_info *mac = &hw->mac;
867 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 868 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
869 u16 hwm;
870
871 /* Repartition Pba for greater than 9k mtu
872 * To take effect CTRL.RST is required.
873 */
2d064c06 874 if (mac->type != e1000_82576) {
9d5c8243 875 pba = E1000_PBA_34K;
2d064c06
AD		 876 }
877 else {
878 pba = E1000_PBA_64K;
879 }
9d5c8243 880
2d064c06
AD		 881 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
882 (mac->type < e1000_82576)) {
9d5c8243
AK		 883 /* adjust PBA for jumbo frames */
884 wr32(E1000_PBA, pba);
885
886 /* To maintain wire speed transmits, the Tx FIFO should be
887 * large enough to accommodate two full transmit packets,
888 * rounded up to the next 1KB and expressed in KB. Likewise,
889 * the Rx FIFO should be large enough to accommodate at least
890 * one full receive packet and is similarly rounded up and
891 * expressed in KB. */
892 pba = rd32(E1000_PBA);
893 /* upper 16 bits has Tx packet buffer allocation size in KB */
894 tx_space = pba >> 16;
895 /* lower 16 bits has Rx packet buffer allocation size in KB */
896 pba &= 0xffff;
897 /* the tx fifo also stores 16 bytes of information about the tx
898 * but don't include ethernet FCS because hardware appends it */
899 min_tx_space = (adapter->max_frame_size +
900 sizeof(struct e1000_tx_desc) -
901 ETH_FCS_LEN) * 2;
902 min_tx_space = ALIGN(min_tx_space, 1024);
903 min_tx_space >>= 10;
904 /* software strips receive CRC, so leave room for it */
905 min_rx_space = adapter->max_frame_size;
906 min_rx_space = ALIGN(min_rx_space, 1024);
907 min_rx_space >>= 10;
908
909 /* If current Tx allocation is less than the min Tx FIFO size,
910 * and the min Tx FIFO size is less than the current Rx FIFO
911 * allocation, take space away from current Rx allocation */
912 if (tx_space < min_tx_space &&
913 ((min_tx_space - tx_space) < pba)) {
914 pba = pba - (min_tx_space - tx_space);
915
916 /* if short on rx space, rx wins and must trump tx
917 * adjustment */
918 if (pba < min_rx_space)
919 pba = min_rx_space;
920 }
2d064c06 921 wr32(E1000_PBA, pba);
9d5c8243 922 }
9d5c8243
AK		 923
924 /* flow control settings */
925 /* The high water mark must be low enough to fit one full frame
926 * (or the size used for early receive) above it in the Rx FIFO.
927 * Set it to the lower of:
928 * - 90% of the Rx FIFO size, or
929 * - the full Rx FIFO size minus one full frame */
930 hwm = min(((pba << 10) * 9 / 10),
2d064c06 931 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 932
2d064c06
AD		 933 if (mac->type < e1000_82576) {
934 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
935 fc->low_water = fc->high_water - 8;
936 } else {
937 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
938 fc->low_water = fc->high_water - 16;
939 }
9d5c8243
AK		 940 fc->pause_time = 0xFFFF;
941 fc->send_xon = 1;
942 fc->type = fc->original_type;
943
944 /* Allow time for pending master requests to run */
945 adapter->hw.mac.ops.reset_hw(&adapter->hw);
946 wr32(E1000_WUC, 0);
947
948 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
949 dev_err(&adapter->pdev->dev, "Hardware Error\n");
950
951 igb_update_mng_vlan(adapter);
952
953 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
954 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
955
956 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 957 if (adapter->hw.phy.ops.get_phy_info)
958 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 959}
960
42bfd33a
TI		 961/**
962 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
963 * @pdev: PCI device information struct
964 *
965 * Returns true if an adapter needs ioport resources
966 **/
967static int igb_is_need_ioport(struct pci_dev *pdev)
968{
969 switch (pdev->device) {
970 /* Currently there are no adapters that need ioport resources */
971 default:
972 return false;
973 }
974}
975
9d5c8243
AK		 976/**
977 * igb_probe - Device Initialization Routine
978 * @pdev: PCI device information struct
979 * @ent: entry in igb_pci_tbl
980 *
981 * Returns 0 on success, negative on failure
982 *
983 * igb_probe initializes an adapter identified by a pci_dev structure.
984 * The OS initialization, configuring of the adapter private structure,
985 * and a hardware reset occur.
986 **/
987static int __devinit igb_probe(struct pci_dev *pdev,
988 const struct pci_device_id *ent)
989{
990 struct net_device *netdev;
991 struct igb_adapter *adapter;
992 struct e1000_hw *hw;
993 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
994 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 995 int i, err, pci_using_dac;
996 u16 eeprom_data = 0;
997 u16 eeprom_apme_mask = IGB_EEPROM_APME;
998 u32 part_num;
42bfd33a 999 int bars, need_ioport;
9d5c8243 1000
42bfd33a
TI		 1001 /* do not allocate ioport bars when not needed */
1002 need_ioport = igb_is_need_ioport(pdev);
1003 if (need_ioport) {
1004 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1005 err = pci_enable_device(pdev);
1006 } else {
1007 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1008 err = pci_enable_device_mem(pdev);
1009 }
9d5c8243
AK		 1010 if (err)
1011 return err;
1012
1013 pci_using_dac = 0;
1014 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1015 if (!err) {
1016 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1017 if (!err)
1018 pci_using_dac = 1;
1019 } else {
1020 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1021 if (err) {
1022 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1023 if (err) {
1024 dev_err(&pdev->dev, "No usable DMA "
1025 "configuration, aborting\n");
1026 goto err_dma;
1027 }
1028 }
1029 }
1030
42bfd33a 1031 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1032 if (err)
1033 goto err_pci_reg;
1034
1035 pci_set_master(pdev);
c682fc23 1036 pci_save_state(pdev);
9d5c8243
AK		 1037
1038 err = -ENOMEM;
661086df 1039 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1040 if (!netdev)
1041 goto err_alloc_etherdev;
1042
1043 SET_NETDEV_DEV(netdev, &pdev->dev);
1044
1045 pci_set_drvdata(pdev, netdev);
1046 adapter = netdev_priv(netdev);
1047 adapter->netdev = netdev;
1048 adapter->pdev = pdev;
1049 hw = &adapter->hw;
1050 hw->back = adapter;
1051 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1052 adapter->bars = bars;
1053 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1054
1055 mmio_start = pci_resource_start(pdev, 0);
1056 mmio_len = pci_resource_len(pdev, 0);
1057
1058 err = -EIO;
1059 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1060 if (!adapter->hw.hw_addr)
1061 goto err_ioremap;
1062
1063 netdev->open = &igb_open;
1064 netdev->stop = &igb_close;
1065 netdev->get_stats = &igb_get_stats;
1066 netdev->set_multicast_list = &igb_set_multi;
1067 netdev->set_mac_address = &igb_set_mac;
1068 netdev->change_mtu = &igb_change_mtu;
1069 netdev->do_ioctl = &igb_ioctl;
1070 igb_set_ethtool_ops(netdev);
1071 netdev->tx_timeout = &igb_tx_timeout;
1072 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1073 netdev->vlan_rx_register = igb_vlan_rx_register;
1074 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
1075 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
1076#ifdef CONFIG_NET_POLL_CONTROLLER
1077 netdev->poll_controller = igb_netpoll;
1078#endif
1079 netdev->hard_start_xmit = &igb_xmit_frame_adv;
1080
1081 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1082
1083 netdev->mem_start = mmio_start;
1084 netdev->mem_end = mmio_start + mmio_len;
1085
9d5c8243
AK		 1086 /* PCI config space info */
1087 hw->vendor_id = pdev->vendor;
1088 hw->device_id = pdev->device;
1089 hw->revision_id = pdev->revision;
1090 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1091 hw->subsystem_device_id = pdev->subsystem_device;
1092
1093 /* setup the private structure */
1094 hw->back = adapter;
1095 /* Copy the default MAC, PHY and NVM function pointers */
1096 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1097 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1098 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1099 /* Initialize skew-specific constants */
1100 err = ei->get_invariants(hw);
1101 if (err)
1102 goto err_hw_init;
1103
1104 err = igb_sw_init(adapter);
1105 if (err)
1106 goto err_sw_init;
1107
1108 igb_get_bus_info_pcie(hw);
1109
7dfc16fa
AD		 1110 /* set flags */
1111 switch (hw->mac.type) {
1112 case e1000_82576:
1113 case e1000_82575:
1114 adapter->flags |= IGB_FLAG_HAS_DCA;
1115 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1116 break;
1117 default:
1118 break;
1119 }
1120
9d5c8243
AK		 1121 hw->phy.autoneg_wait_to_complete = false;
1122 hw->mac.adaptive_ifs = true;
1123
1124 /* Copper options */
1125 if (hw->phy.media_type == e1000_media_type_copper) {
1126 hw->phy.mdix = AUTO_ALL_MODES;
1127 hw->phy.disable_polarity_correction = false;
1128 hw->phy.ms_type = e1000_ms_hw_default;
1129 }
1130
1131 if (igb_check_reset_block(hw))
1132 dev_info(&pdev->dev,
1133 "PHY reset is blocked due to SOL/IDER session.\n");
1134
1135 netdev->features = NETIF_F_SG |
1136 NETIF_F_HW_CSUM |
1137 NETIF_F_HW_VLAN_TX |
1138 NETIF_F_HW_VLAN_RX |
1139 NETIF_F_HW_VLAN_FILTER;
1140
1141 netdev->features |= NETIF_F_TSO;
9d5c8243 1142 netdev->features |= NETIF_F_TSO6;
48f29ffc 1143
d3352520
AD		 1144#ifdef CONFIG_IGB_LRO
1145 netdev->features |= NETIF_F_LRO;
1146#endif
1147
48f29ffc
JK		 1148 netdev->vlan_features |= NETIF_F_TSO;
1149 netdev->vlan_features |= NETIF_F_TSO6;
1150 netdev->vlan_features |= NETIF_F_HW_CSUM;
1151 netdev->vlan_features |= NETIF_F_SG;
1152
9d5c8243
AK		 1153 if (pci_using_dac)
1154 netdev->features |= NETIF_F_HIGHDMA;
1155
1156 netdev->features |= NETIF_F_LLTX;
1157 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1158
1159 /* before reading the NVM, reset the controller to put the device in a
1160 * known good starting state */
1161 hw->mac.ops.reset_hw(hw);
1162
1163 /* make sure the NVM is good */
1164 if (igb_validate_nvm_checksum(hw) < 0) {
1165 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1166 err = -EIO;
1167 goto err_eeprom;
1168 }
1169
1170 /* copy the MAC address out of the NVM */
1171 if (hw->mac.ops.read_mac_addr(hw))
1172 dev_err(&pdev->dev, "NVM Read Error\n");
1173
1174 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1175 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1176
1177 if (!is_valid_ether_addr(netdev->perm_addr)) {
1178 dev_err(&pdev->dev, "Invalid MAC Address\n");
1179 err = -EIO;
1180 goto err_eeprom;
1181 }
1182
1183 init_timer(&adapter->watchdog_timer);
1184 adapter->watchdog_timer.function = &igb_watchdog;
1185 adapter->watchdog_timer.data = (unsigned long) adapter;
1186
1187 init_timer(&adapter->phy_info_timer);
1188 adapter->phy_info_timer.function = &igb_update_phy_info;
1189 adapter->phy_info_timer.data = (unsigned long) adapter;
1190
1191 INIT_WORK(&adapter->reset_task, igb_reset_task);
1192 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1193
1194 /* Initialize link & ring properties that are user-changeable */
1195 adapter->tx_ring->count = 256;
1196 for (i = 0; i < adapter->num_tx_queues; i++)
1197 adapter->tx_ring[i].count = adapter->tx_ring->count;
1198 adapter->rx_ring->count = 256;
1199 for (i = 0; i < adapter->num_rx_queues; i++)
1200 adapter->rx_ring[i].count = adapter->rx_ring->count;
1201
1202 adapter->fc_autoneg = true;
1203 hw->mac.autoneg = true;
1204 hw->phy.autoneg_advertised = 0x2f;
1205
1206 hw->fc.original_type = e1000_fc_default;
1207 hw->fc.type = e1000_fc_default;
1208
1209 adapter->itr_setting = 3;
1210 adapter->itr = IGB_START_ITR;
1211
1212 igb_validate_mdi_setting(hw);
1213
1214 adapter->rx_csum = 1;
1215
1216 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1217 * enable the ACPI Magic Packet filter
1218 */
1219
1220 if (hw->bus.func == 0 ||
1221 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1222 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1223 &eeprom_data);
1224
1225 if (eeprom_data & eeprom_apme_mask)
1226 adapter->eeprom_wol |= E1000_WUFC_MAG;
1227
1228 /* now that we have the eeprom settings, apply the special cases where
1229 * the eeprom may be wrong or the board simply won't support wake on
1230 * lan on a particular port */
1231 switch (pdev->device) {
1232 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1233 adapter->eeprom_wol = 0;
1234 break;
1235 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1236 case E1000_DEV_ID_82576_FIBER:
1237 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1238 /* Wake events only supported on port A for dual fiber
1239 * regardless of eeprom setting */
1240 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1241 adapter->eeprom_wol = 0;
1242 break;
7dfc16fa
AD		 1243 case E1000_DEV_ID_82576_QUAD_COPPER:
1244 /* if quad port adapter, disable WoL on all but port A */
1245 if (global_quad_port_a != 0)
1246 adapter->eeprom_wol = 0;
1247 else
1248 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1249 /* Reset for multiple quad port adapters */
1250 if (++global_quad_port_a == 4)
1251 global_quad_port_a = 0;
1252 break;
9d5c8243
AK		 1253 }
1254
1255 /* initialize the wol settings based on the eeprom settings */
1256 adapter->wol = adapter->eeprom_wol;
1257
1258 /* reset the hardware with the new settings */
1259 igb_reset(adapter);
1260
1261 /* let the f/w know that the h/w is now under the control of the
1262 * driver. */
1263 igb_get_hw_control(adapter);
1264
1265 /* tell the stack to leave us alone until igb_open() is called */
1266 netif_carrier_off(netdev);
fd2ea0a7 1267 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1268
1269 strcpy(netdev->name, "eth%d");
1270 err = register_netdev(netdev);
1271 if (err)
1272 goto err_register;
1273
fe4506b6 1274#ifdef CONFIG_DCA
7dfc16fa
AD		 1275 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1276 (dca_add_requester(&pdev->dev) == 0)) {
1277 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1278 dev_info(&pdev->dev, "DCA enabled\n");
1279 /* Always use CB2 mode, difference is masked
1280 * in the CB driver. */
1281 wr32(E1000_DCA_CTRL, 2);
1282 igb_setup_dca(adapter);
1283 }
1284#endif
1285
9d5c8243
AK		 1286 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1287 /* print bus type/speed/width info */
1288 dev_info(&pdev->dev,
1289 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1290 netdev->name,
1291 ((hw->bus.speed == e1000_bus_speed_2500)
1292 ? "2.5Gb/s" : "unknown"),
1293 ((hw->bus.width == e1000_bus_width_pcie_x4)
1294 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1295 ? "Width x1" : "unknown"),
1296 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1297 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1298
1299 igb_read_part_num(hw, &part_num);
1300 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1301 (part_num >> 8), (part_num & 0xff));
1302
1303 dev_info(&pdev->dev,
1304 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1305 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1306 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1307 adapter->num_rx_queues, adapter->num_tx_queues);
1308
9d5c8243
AK		 1309 return 0;
1310
1311err_register:
1312 igb_release_hw_control(adapter);
1313err_eeprom:
1314 if (!igb_check_reset_block(hw))
1315 hw->phy.ops.reset_phy(hw);
1316
1317 if (hw->flash_address)
1318 iounmap(hw->flash_address);
1319
1320 igb_remove_device(hw);
a88f10ec 1321 igb_free_queues(adapter);
9d5c8243
AK		 1322err_sw_init:
1323err_hw_init:
1324 iounmap(hw->hw_addr);
1325err_ioremap:
1326 free_netdev(netdev);
1327err_alloc_etherdev:
42bfd33a 1328 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1329err_pci_reg:
1330err_dma:
1331 pci_disable_device(pdev);
1332 return err;
1333}
1334
1335/**
1336 * igb_remove - Device Removal Routine
1337 * @pdev: PCI device information struct
1338 *
1339 * igb_remove is called by the PCI subsystem to alert the driver
1340 * that it should release a PCI device. The could be caused by a
1341 * Hot-Plug event, or because the driver is going to be removed from
1342 * memory.
1343 **/
1344static void __devexit igb_remove(struct pci_dev *pdev)
1345{
1346 struct net_device *netdev = pci_get_drvdata(pdev);
1347 struct igb_adapter *adapter = netdev_priv(netdev);
9280fa52 1348#ifdef CONFIG_DCA
fe4506b6 1349 struct e1000_hw *hw = &adapter->hw;
9280fa52 1350#endif
9d5c8243
AK		 1351
1352 /* flush_scheduled work may reschedule our watchdog task, so
1353 * explicitly disable watchdog tasks from being rescheduled */
1354 set_bit(__IGB_DOWN, &adapter->state);
1355 del_timer_sync(&adapter->watchdog_timer);
1356 del_timer_sync(&adapter->phy_info_timer);
1357
1358 flush_scheduled_work();
1359
fe4506b6 1360#ifdef CONFIG_DCA
7dfc16fa 1361 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1362 dev_info(&pdev->dev, "DCA disabled\n");
1363 dca_remove_requester(&pdev->dev);
7dfc16fa 1364 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1365 wr32(E1000_DCA_CTRL, 1);
1366 }
1367#endif
1368
9d5c8243
AK		 1369 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1370 * would have already happened in close and is redundant. */
1371 igb_release_hw_control(adapter);
1372
1373 unregister_netdev(netdev);
1374
1375 if (!igb_check_reset_block(&adapter->hw))
1376 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1377
1378 igb_remove_device(&adapter->hw);
1379 igb_reset_interrupt_capability(adapter);
1380
a88f10ec 1381 igb_free_queues(adapter);
9d5c8243
AK		 1382
1383 iounmap(adapter->hw.hw_addr);
1384 if (adapter->hw.flash_address)
1385 iounmap(adapter->hw.flash_address);
42bfd33a 1386 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1387
1388 free_netdev(netdev);
1389
1390 pci_disable_device(pdev);
1391}
1392
1393/**
1394 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1395 * @adapter: board private structure to initialize
1396 *
1397 * igb_sw_init initializes the Adapter private data structure.
1398 * Fields are initialized based on PCI device information and
1399 * OS network device settings (MTU size).
1400 **/
1401static int __devinit igb_sw_init(struct igb_adapter *adapter)
1402{
1403 struct e1000_hw *hw = &adapter->hw;
1404 struct net_device *netdev = adapter->netdev;
1405 struct pci_dev *pdev = adapter->pdev;
1406
1407 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1408
1409 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1410 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1411 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1412 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1413
1414 /* Number of supported queues. */
1415 /* Having more queues than CPUs doesn't make sense. */
661086df 1416 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
661086df 1417 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
9d5c8243 1418
661086df
PWJ		 1419 /* This call may decrease the number of queues depending on
1420 * interrupt mode. */
9d5c8243
AK		 1421 igb_set_interrupt_capability(adapter);
1422
1423 if (igb_alloc_queues(adapter)) {
1424 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1425 return -ENOMEM;
1426 }
1427
1428 /* Explicitly disable IRQ since the NIC can be in any state. */
1429 igb_irq_disable(adapter);
1430
1431 set_bit(__IGB_DOWN, &adapter->state);
1432 return 0;
1433}
1434
1435/**
1436 * igb_open - Called when a network interface is made active
1437 * @netdev: network interface device structure
1438 *
1439 * Returns 0 on success, negative value on failure
1440 *
1441 * The open entry point is called when a network interface is made
1442 * active by the system (IFF_UP). At this point all resources needed
1443 * for transmit and receive operations are allocated, the interrupt
1444 * handler is registered with the OS, the watchdog timer is started,
1445 * and the stack is notified that the interface is ready.
1446 **/
1447static int igb_open(struct net_device *netdev)
1448{
1449 struct igb_adapter *adapter = netdev_priv(netdev);
1450 struct e1000_hw *hw = &adapter->hw;
1451 int err;
1452 int i;
1453
1454 /* disallow open during test */
1455 if (test_bit(__IGB_TESTING, &adapter->state))
1456 return -EBUSY;
1457
1458 /* allocate transmit descriptors */
1459 err = igb_setup_all_tx_resources(adapter);
1460 if (err)
1461 goto err_setup_tx;
1462
1463 /* allocate receive descriptors */
1464 err = igb_setup_all_rx_resources(adapter);
1465 if (err)
1466 goto err_setup_rx;
1467
1468 /* e1000_power_up_phy(adapter); */
1469
1470 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1471 if ((adapter->hw.mng_cookie.status &
1472 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1473 igb_update_mng_vlan(adapter);
1474
1475 /* before we allocate an interrupt, we must be ready to handle it.
1476 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1477 * as soon as we call pci_request_irq, so we have to setup our
1478 * clean_rx handler before we do so. */
1479 igb_configure(adapter);
1480
1481 err = igb_request_irq(adapter);
1482 if (err)
1483 goto err_req_irq;
1484
1485 /* From here on the code is the same as igb_up() */
1486 clear_bit(__IGB_DOWN, &adapter->state);
1487
844290e5
PW		 1488 for (i = 0; i < adapter->num_rx_queues; i++)
1489 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1490
1491 /* Clear any pending interrupts. */
1492 rd32(E1000_ICR);
844290e5
PW		 1493
1494 igb_irq_enable(adapter);
1495
9d5c8243
AK		 1496 /* Fire a link status change interrupt to start the watchdog. */
1497 wr32(E1000_ICS, E1000_ICS_LSC);
1498
1499 return 0;
1500
1501err_req_irq:
1502 igb_release_hw_control(adapter);
1503 /* e1000_power_down_phy(adapter); */
1504 igb_free_all_rx_resources(adapter);
1505err_setup_rx:
1506 igb_free_all_tx_resources(adapter);
1507err_setup_tx:
1508 igb_reset(adapter);
1509
1510 return err;
1511}
1512
1513/**
1514 * igb_close - Disables a network interface
1515 * @netdev: network interface device structure
1516 *
1517 * Returns 0, this is not allowed to fail
1518 *
1519 * The close entry point is called when an interface is de-activated
1520 * by the OS. The hardware is still under the driver's control, but
1521 * needs to be disabled. A global MAC reset is issued to stop the
1522 * hardware, and all transmit and receive resources are freed.
1523 **/
1524static int igb_close(struct net_device *netdev)
1525{
1526 struct igb_adapter *adapter = netdev_priv(netdev);
1527
1528 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1529 igb_down(adapter);
1530
1531 igb_free_irq(adapter);
1532
1533 igb_free_all_tx_resources(adapter);
1534 igb_free_all_rx_resources(adapter);
1535
1536 /* kill manageability vlan ID if supported, but not if a vlan with
1537 * the same ID is registered on the host OS (let 8021q kill it) */
1538 if ((adapter->hw.mng_cookie.status &
1539 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1540 !(adapter->vlgrp &&
1541 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1542 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1543
1544 return 0;
1545}
1546
1547/**
1548 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1549 * @adapter: board private structure
1550 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1551 *
1552 * Return 0 on success, negative on failure
1553 **/
1554
1555int igb_setup_tx_resources(struct igb_adapter *adapter,
1556 struct igb_ring *tx_ring)
1557{
1558 struct pci_dev *pdev = adapter->pdev;
1559 int size;
1560
1561 size = sizeof(struct igb_buffer) * tx_ring->count;
1562 tx_ring->buffer_info = vmalloc(size);
1563 if (!tx_ring->buffer_info)
1564 goto err;
1565 memset(tx_ring->buffer_info, 0, size);
1566
1567 /* round up to nearest 4K */
1568 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1569 + sizeof(u32);
1570 tx_ring->size = ALIGN(tx_ring->size, 4096);
1571
1572 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1573 &tx_ring->dma);
1574
1575 if (!tx_ring->desc)
1576 goto err;
1577
1578 tx_ring->adapter = adapter;
1579 tx_ring->next_to_use = 0;
1580 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1581 return 0;
1582
1583err:
1584 vfree(tx_ring->buffer_info);
1585 dev_err(&adapter->pdev->dev,
1586 "Unable to allocate memory for the transmit descriptor ring\n");
1587 return -ENOMEM;
1588}
1589
1590/**
1591 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1592 * (Descriptors) for all queues
1593 * @adapter: board private structure
1594 *
1595 * Return 0 on success, negative on failure
1596 **/
1597static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1598{
1599 int i, err = 0;
661086df 1600 int r_idx;
9d5c8243
AK		 1601
1602 for (i = 0; i < adapter->num_tx_queues; i++) {
1603 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1604 if (err) {
1605 dev_err(&adapter->pdev->dev,
1606 "Allocation for Tx Queue %u failed\n", i);
1607 for (i--; i >= 0; i--)
3b644cf6 1608 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1609 break;
1610 }
1611 }
1612
661086df
PWJ		 1613 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1614 r_idx = i % adapter->num_tx_queues;
1615 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1616 }
9d5c8243
AK		 1617 return err;
1618}
1619
1620/**
1621 * igb_configure_tx - Configure transmit Unit after Reset
1622 * @adapter: board private structure
1623 *
1624 * Configure the Tx unit of the MAC after a reset.
1625 **/
1626static void igb_configure_tx(struct igb_adapter *adapter)
1627{
1628 u64 tdba, tdwba;
1629 struct e1000_hw *hw = &adapter->hw;
1630 u32 tctl;
1631 u32 txdctl, txctrl;
1632 int i;
1633
1634 for (i = 0; i < adapter->num_tx_queues; i++) {
1635 struct igb_ring *ring = &(adapter->tx_ring[i]);
1636
1637 wr32(E1000_TDLEN(i),
1638 ring->count * sizeof(struct e1000_tx_desc));
1639 tdba = ring->dma;
1640 wr32(E1000_TDBAL(i),
1641 tdba & 0x00000000ffffffffULL);
1642 wr32(E1000_TDBAH(i), tdba >> 32);
1643
1644 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1645 tdwba |= 1; /* enable head wb */
1646 wr32(E1000_TDWBAL(i),
1647 tdwba & 0x00000000ffffffffULL);
1648 wr32(E1000_TDWBAH(i), tdwba >> 32);
1649
1650 ring->head = E1000_TDH(i);
1651 ring->tail = E1000_TDT(i);
1652 writel(0, hw->hw_addr + ring->tail);
1653 writel(0, hw->hw_addr + ring->head);
1654 txdctl = rd32(E1000_TXDCTL(i));
1655 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1656 wr32(E1000_TXDCTL(i), txdctl);
1657
1658 /* Turn off Relaxed Ordering on head write-backs. The
1659 * writebacks MUST be delivered in order or it will
1660 * completely screw up our bookeeping.
1661 */
1662 txctrl = rd32(E1000_DCA_TXCTRL(i));
1663 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1664 wr32(E1000_DCA_TXCTRL(i), txctrl);
1665 }
1666
1667
1668
1669 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1670
1671 /* Program the Transmit Control Register */
1672
1673 tctl = rd32(E1000_TCTL);
1674 tctl &= ~E1000_TCTL_CT;
1675 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1676 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1677
1678 igb_config_collision_dist(hw);
1679
1680 /* Setup Transmit Descriptor Settings for eop descriptor */
1681 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1682
1683 /* Enable transmits */
1684 tctl |= E1000_TCTL_EN;
1685
1686 wr32(E1000_TCTL, tctl);
1687}
1688
1689/**
1690 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1691 * @adapter: board private structure
1692 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1693 *
1694 * Returns 0 on success, negative on failure
1695 **/
1696
1697int igb_setup_rx_resources(struct igb_adapter *adapter,
1698 struct igb_ring *rx_ring)
1699{
1700 struct pci_dev *pdev = adapter->pdev;
1701 int size, desc_len;
1702
d3352520
AD		 1703#ifdef CONFIG_IGB_LRO
1704 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1705 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1706 if (!rx_ring->lro_mgr.lro_arr)
1707 goto err;
1708 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1709#endif
1710
9d5c8243
AK		 1711 size = sizeof(struct igb_buffer) * rx_ring->count;
1712 rx_ring->buffer_info = vmalloc(size);
1713 if (!rx_ring->buffer_info)
1714 goto err;
1715 memset(rx_ring->buffer_info, 0, size);
1716
1717 desc_len = sizeof(union e1000_adv_rx_desc);
1718
1719 /* Round up to nearest 4K */
1720 rx_ring->size = rx_ring->count * desc_len;
1721 rx_ring->size = ALIGN(rx_ring->size, 4096);
1722
1723 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1724 &rx_ring->dma);
1725
1726 if (!rx_ring->desc)
1727 goto err;
1728
1729 rx_ring->next_to_clean = 0;
1730 rx_ring->next_to_use = 0;
9d5c8243
AK		 1731
1732 rx_ring->adapter = adapter;
9d5c8243
AK		 1733
1734 return 0;
1735
1736err:
d3352520
AD		 1737#ifdef CONFIG_IGB_LRO
1738 vfree(rx_ring->lro_mgr.lro_arr);
1739 rx_ring->lro_mgr.lro_arr = NULL;
1740#endif
9d5c8243
AK		 1741 vfree(rx_ring->buffer_info);
1742 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1743 "the receive descriptor ring\n");
1744 return -ENOMEM;
1745}
1746
1747/**
1748 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1749 * (Descriptors) for all queues
1750 * @adapter: board private structure
1751 *
1752 * Return 0 on success, negative on failure
1753 **/
1754static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1755{
1756 int i, err = 0;
1757
1758 for (i = 0; i < adapter->num_rx_queues; i++) {
1759 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1760 if (err) {
1761 dev_err(&adapter->pdev->dev,
1762 "Allocation for Rx Queue %u failed\n", i);
1763 for (i--; i >= 0; i--)
3b644cf6 1764 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1765 break;
1766 }
1767 }
1768
1769 return err;
1770}
1771
1772/**
1773 * igb_setup_rctl - configure the receive control registers
1774 * @adapter: Board private structure
1775 **/
1776static void igb_setup_rctl(struct igb_adapter *adapter)
1777{
1778 struct e1000_hw *hw = &adapter->hw;
1779 u32 rctl;
1780 u32 srrctl = 0;
1781 int i;
1782
1783 rctl = rd32(E1000_RCTL);
1784
1785 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1786
1787 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1788 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1789 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1790
87cb7e8c
AK		 1791 /*
1792 * enable stripping of CRC. It's unlikely this will break BMC
1793 * redirection as it did with e1000. Newer features require
1794 * that the HW strips the CRC.
9d5c8243 1795 */
87cb7e8c 1796 rctl |= E1000_RCTL_SECRC;
9d5c8243
AK		 1797
1798 rctl &= ~E1000_RCTL_SBP;
1799
1800 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1801 rctl &= ~E1000_RCTL_LPE;
1802 else
1803 rctl |= E1000_RCTL_LPE;
1804 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1805 /* Setup buffer sizes */
1806 rctl &= ~E1000_RCTL_SZ_4096;
1807 rctl |= E1000_RCTL_BSEX;
1808 switch (adapter->rx_buffer_len) {
1809 case IGB_RXBUFFER_256:
1810 rctl |= E1000_RCTL_SZ_256;
1811 rctl &= ~E1000_RCTL_BSEX;
1812 break;
1813 case IGB_RXBUFFER_512:
1814 rctl |= E1000_RCTL_SZ_512;
1815 rctl &= ~E1000_RCTL_BSEX;
1816 break;
1817 case IGB_RXBUFFER_1024:
1818 rctl |= E1000_RCTL_SZ_1024;
1819 rctl &= ~E1000_RCTL_BSEX;
1820 break;
1821 case IGB_RXBUFFER_2048:
1822 default:
1823 rctl |= E1000_RCTL_SZ_2048;
1824 rctl &= ~E1000_RCTL_BSEX;
1825 break;
9d5c8243
AK		 1826 }
1827 } else {
1828 rctl &= ~E1000_RCTL_BSEX;
1829 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1830 }
1831
1832 /* 82575 and greater support packet-split where the protocol
1833 * header is placed in skb->data and the packet data is
1834 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1835 * In the case of a non-split, skb->data is linearly filled,
1836 * followed by the page buffers. Therefore, skb->data is
1837 * sized to hold the largest protocol header.
1838 */
1839 /* allocations using alloc_page take too long for regular MTU
1840 * so only enable packet split for jumbo frames */
1841 if (rctl & E1000_RCTL_LPE) {
1842 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1843 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1844 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1845 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1846 } else {
1847 adapter->rx_ps_hdr_size = 0;
1848 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1849 }
1850
1851 for (i = 0; i < adapter->num_rx_queues; i++)
1852 wr32(E1000_SRRCTL(i), srrctl);
1853
1854 wr32(E1000_RCTL, rctl);
1855}
1856
1857/**
1858 * igb_configure_rx - Configure receive Unit after Reset
1859 * @adapter: board private structure
1860 *
1861 * Configure the Rx unit of the MAC after a reset.
1862 **/
1863static void igb_configure_rx(struct igb_adapter *adapter)
1864{
1865 u64 rdba;
1866 struct e1000_hw *hw = &adapter->hw;
1867 u32 rctl, rxcsum;
1868 u32 rxdctl;
1869 int i;
1870
1871 /* disable receives while setting up the descriptors */
1872 rctl = rd32(E1000_RCTL);
1873 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1874 wrfl();
1875 mdelay(10);
1876
1877 if (adapter->itr_setting > 3)
6eb5a7f1 1878 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1879
1880 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1881 * the Base and Length of the Rx Descriptor Ring */
1882 for (i = 0; i < adapter->num_rx_queues; i++) {
1883 struct igb_ring *ring = &(adapter->rx_ring[i]);
1884 rdba = ring->dma;
1885 wr32(E1000_RDBAL(i),
1886 rdba & 0x00000000ffffffffULL);
1887 wr32(E1000_RDBAH(i), rdba >> 32);
1888 wr32(E1000_RDLEN(i),
1889 ring->count * sizeof(union e1000_adv_rx_desc));
1890
1891 ring->head = E1000_RDH(i);
1892 ring->tail = E1000_RDT(i);
1893 writel(0, hw->hw_addr + ring->tail);
1894 writel(0, hw->hw_addr + ring->head);
1895
1896 rxdctl = rd32(E1000_RXDCTL(i));
1897 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1898 rxdctl &= 0xFFF00000;
1899 rxdctl |= IGB_RX_PTHRESH;
1900 rxdctl |= IGB_RX_HTHRESH << 8;
1901 rxdctl |= IGB_RX_WTHRESH << 16;
1902 wr32(E1000_RXDCTL(i), rxdctl);
d3352520
AD		 1903#ifdef CONFIG_IGB_LRO
1904 /* Intitial LRO Settings */
1905 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1906 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1907 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1908 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1909 ring->lro_mgr.dev = adapter->netdev;
1910 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1911 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1912#endif
9d5c8243
AK		 1913 }
1914
1915 if (adapter->num_rx_queues > 1) {
1916 u32 random[10];
1917 u32 mrqc;
1918 u32 j, shift;
1919 union e1000_reta {
1920 u32 dword;
1921 u8 bytes[4];
1922 } reta;
1923
1924 get_random_bytes(&random[0], 40);
1925
2d064c06
AD		 1926 if (hw->mac.type >= e1000_82576)
1927 shift = 0;
1928 else
1929 shift = 6;
9d5c8243
AK		 1930 for (j = 0; j < (32 * 4); j++) {
1931 reta.bytes[j & 3] =
1932 (j % adapter->num_rx_queues) << shift;
1933 if ((j & 3) == 3)
1934 writel(reta.dword,
1935 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1936 }
1937 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1938
1939 /* Fill out hash function seeds */
1940 for (j = 0; j < 10; j++)
1941 array_wr32(E1000_RSSRK(0), j, random[j]);
1942
1943 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1944 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1945 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1946 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1947 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1948 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1949 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1950 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1951
1952
1953 wr32(E1000_MRQC, mrqc);
1954
1955 /* Multiqueue and raw packet checksumming are mutually
1956 * exclusive. Note that this not the same as TCP/IP
1957 * checksumming, which works fine. */
1958 rxcsum = rd32(E1000_RXCSUM);
1959 rxcsum |= E1000_RXCSUM_PCSD;
1960 wr32(E1000_RXCSUM, rxcsum);
1961 } else {
1962 /* Enable Receive Checksum Offload for TCP and UDP */
1963 rxcsum = rd32(E1000_RXCSUM);
1964 if (adapter->rx_csum) {
1965 rxcsum |= E1000_RXCSUM_TUOFL;
1966
1967 /* Enable IPv4 payload checksum for UDP fragments
1968 * Must be used in conjunction with packet-split. */
1969 if (adapter->rx_ps_hdr_size)
1970 rxcsum |= E1000_RXCSUM_IPPCSE;
1971 } else {
1972 rxcsum &= ~E1000_RXCSUM_TUOFL;
1973 /* don't need to clear IPPCSE as it defaults to 0 */
1974 }
1975 wr32(E1000_RXCSUM, rxcsum);
1976 }
1977
1978 if (adapter->vlgrp)
1979 wr32(E1000_RLPML,
1980 adapter->max_frame_size + VLAN_TAG_SIZE);
1981 else
1982 wr32(E1000_RLPML, adapter->max_frame_size);
1983
1984 /* Enable Receives */
1985 wr32(E1000_RCTL, rctl);
1986}
1987
1988/**
1989 * igb_free_tx_resources - Free Tx Resources per Queue
1990 * @adapter: board private structure
1991 * @tx_ring: Tx descriptor ring for a specific queue
1992 *
1993 * Free all transmit software resources
1994 **/
3b644cf6 1995static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1996{
3b644cf6 1997 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1998
3b644cf6 1999 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2000
2001 vfree(tx_ring->buffer_info);
2002 tx_ring->buffer_info = NULL;
2003
2004 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2005
2006 tx_ring->desc = NULL;
2007}
2008
2009/**
2010 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2011 * @adapter: board private structure
2012 *
2013 * Free all transmit software resources
2014 **/
2015static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2016{
2017 int i;
2018
2019 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2020 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2021}
2022
2023static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2024 struct igb_buffer *buffer_info)
2025{
2026 if (buffer_info->dma) {
2027 pci_unmap_page(adapter->pdev,
2028 buffer_info->dma,
2029 buffer_info->length,
2030 PCI_DMA_TODEVICE);
2031 buffer_info->dma = 0;
2032 }
2033 if (buffer_info->skb) {
2034 dev_kfree_skb_any(buffer_info->skb);
2035 buffer_info->skb = NULL;
2036 }
2037 buffer_info->time_stamp = 0;
2038 /* buffer_info must be completely set up in the transmit path */
2039}
2040
2041/**
2042 * igb_clean_tx_ring - Free Tx Buffers
2043 * @adapter: board private structure
2044 * @tx_ring: ring to be cleaned
2045 **/
3b644cf6 2046static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2047{
3b644cf6 2048 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2049 struct igb_buffer *buffer_info;
2050 unsigned long size;
2051 unsigned int i;
2052
2053 if (!tx_ring->buffer_info)
2054 return;
2055 /* Free all the Tx ring sk_buffs */
2056
2057 for (i = 0; i < tx_ring->count; i++) {
2058 buffer_info = &tx_ring->buffer_info[i];
2059 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2060 }
2061
2062 size = sizeof(struct igb_buffer) * tx_ring->count;
2063 memset(tx_ring->buffer_info, 0, size);
2064
2065 /* Zero out the descriptor ring */
2066
2067 memset(tx_ring->desc, 0, tx_ring->size);
2068
2069 tx_ring->next_to_use = 0;
2070 tx_ring->next_to_clean = 0;
2071
2072 writel(0, adapter->hw.hw_addr + tx_ring->head);
2073 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2074}
2075
2076/**
2077 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2078 * @adapter: board private structure
2079 **/
2080static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2081{
2082 int i;
2083
2084 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2085 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2086}
2087
2088/**
2089 * igb_free_rx_resources - Free Rx Resources
2090 * @adapter: board private structure
2091 * @rx_ring: ring to clean the resources from
2092 *
2093 * Free all receive software resources
2094 **/
3b644cf6 2095static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2096{
3b644cf6 2097 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2098
3b644cf6 2099 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2100
2101 vfree(rx_ring->buffer_info);
2102 rx_ring->buffer_info = NULL;
2103
d3352520
AD		 2104#ifdef CONFIG_IGB_LRO
2105 vfree(rx_ring->lro_mgr.lro_arr);
2106 rx_ring->lro_mgr.lro_arr = NULL;
2107#endif
2108
9d5c8243
AK		 2109 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2110
2111 rx_ring->desc = NULL;
2112}
2113
2114/**
2115 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2116 * @adapter: board private structure
2117 *
2118 * Free all receive software resources
2119 **/
2120static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2121{
2122 int i;
2123
2124 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2125 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2126}
2127
2128/**
2129 * igb_clean_rx_ring - Free Rx Buffers per Queue
2130 * @adapter: board private structure
2131 * @rx_ring: ring to free buffers from
2132 **/
3b644cf6 2133static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2134{
3b644cf6 2135 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2136 struct igb_buffer *buffer_info;
2137 struct pci_dev *pdev = adapter->pdev;
2138 unsigned long size;
2139 unsigned int i;
2140
2141 if (!rx_ring->buffer_info)
2142 return;
2143 /* Free all the Rx ring sk_buffs */
2144 for (i = 0; i < rx_ring->count; i++) {
2145 buffer_info = &rx_ring->buffer_info[i];
2146 if (buffer_info->dma) {
2147 if (adapter->rx_ps_hdr_size)
2148 pci_unmap_single(pdev, buffer_info->dma,
2149 adapter->rx_ps_hdr_size,
2150 PCI_DMA_FROMDEVICE);
2151 else
2152 pci_unmap_single(pdev, buffer_info->dma,
2153 adapter->rx_buffer_len,
2154 PCI_DMA_FROMDEVICE);
2155 buffer_info->dma = 0;
2156 }
2157
2158 if (buffer_info->skb) {
2159 dev_kfree_skb(buffer_info->skb);
2160 buffer_info->skb = NULL;
2161 }
2162 if (buffer_info->page) {
bf36c1a0
AD		 2163 if (buffer_info->page_dma)
2164 pci_unmap_page(pdev, buffer_info->page_dma,
2165 PAGE_SIZE / 2,
2166 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2167 put_page(buffer_info->page);
2168 buffer_info->page = NULL;
2169 buffer_info->page_dma = 0;
bf36c1a0 2170 buffer_info->page_offset = 0;
9d5c8243
AK		 2171 }
2172 }
2173
9d5c8243
AK		 2174 size = sizeof(struct igb_buffer) * rx_ring->count;
2175 memset(rx_ring->buffer_info, 0, size);
2176
2177 /* Zero out the descriptor ring */
2178 memset(rx_ring->desc, 0, rx_ring->size);
2179
2180 rx_ring->next_to_clean = 0;
2181 rx_ring->next_to_use = 0;
2182
2183 writel(0, adapter->hw.hw_addr + rx_ring->head);
2184 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2185}
2186
2187/**
2188 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2189 * @adapter: board private structure
2190 **/
2191static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2192{
2193 int i;
2194
2195 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2196 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2197}
2198
2199/**
2200 * igb_set_mac - Change the Ethernet Address of the NIC
2201 * @netdev: network interface device structure
2202 * @p: pointer to an address structure
2203 *
2204 * Returns 0 on success, negative on failure
2205 **/
2206static int igb_set_mac(struct net_device *netdev, void *p)
2207{
2208 struct igb_adapter *adapter = netdev_priv(netdev);
2209 struct sockaddr *addr = p;
2210
2211 if (!is_valid_ether_addr(addr->sa_data))
2212 return -EADDRNOTAVAIL;
2213
2214 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2215 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2216
2217 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2218
2219 return 0;
2220}
2221
2222/**
2223 * igb_set_multi - Multicast and Promiscuous mode set
2224 * @netdev: network interface device structure
2225 *
2226 * The set_multi entry point is called whenever the multicast address
2227 * list or the network interface flags are updated. This routine is
2228 * responsible for configuring the hardware for proper multicast,
2229 * promiscuous mode, and all-multi behavior.
2230 **/
2231static void igb_set_multi(struct net_device *netdev)
2232{
2233 struct igb_adapter *adapter = netdev_priv(netdev);
2234 struct e1000_hw *hw = &adapter->hw;
2235 struct e1000_mac_info *mac = &hw->mac;
2236 struct dev_mc_list *mc_ptr;
2237 u8 *mta_list;
2238 u32 rctl;
2239 int i;
2240
2241 /* Check for Promiscuous and All Multicast modes */
2242
2243 rctl = rd32(E1000_RCTL);
2244
746b9f02 2245 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2246 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2247 rctl &= ~E1000_RCTL_VFE;
2248 } else {
2249 if (netdev->flags & IFF_ALLMULTI) {
2250 rctl |= E1000_RCTL_MPE;
2251 rctl &= ~E1000_RCTL_UPE;
2252 } else
2253 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2254 rctl |= E1000_RCTL_VFE;
746b9f02 2255 }
9d5c8243
AK		 2256 wr32(E1000_RCTL, rctl);
2257
2258 if (!netdev->mc_count) {
2259 /* nothing to program, so clear mc list */
2d064c06 2260 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2261 mac->rar_entry_count);
2262 return;
2263 }
2264
2265 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2266 if (!mta_list)
2267 return;
2268
2269 /* The shared function expects a packed array of only addresses. */
2270 mc_ptr = netdev->mc_list;
2271
2272 for (i = 0; i < netdev->mc_count; i++) {
2273 if (!mc_ptr)
2274 break;
2275 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2276 mc_ptr = mc_ptr->next;
2277 }
2d064c06
AD		 2278 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2279 mac->rar_entry_count);
9d5c8243
AK		 2280 kfree(mta_list);
2281}
2282
2283/* Need to wait a few seconds after link up to get diagnostic information from
2284 * the phy */
2285static void igb_update_phy_info(unsigned long data)
2286{
2287 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2288 if (adapter->hw.phy.ops.get_phy_info)
2289 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2290}
2291
2292/**
2293 * igb_watchdog - Timer Call-back
2294 * @data: pointer to adapter cast into an unsigned long
2295 **/
2296static void igb_watchdog(unsigned long data)
2297{
2298 struct igb_adapter *adapter = (struct igb_adapter *)data;
2299 /* Do the rest outside of interrupt context */
2300 schedule_work(&adapter->watchdog_task);
2301}
2302
2303static void igb_watchdog_task(struct work_struct *work)
2304{
2305 struct igb_adapter *adapter = container_of(work,
2306 struct igb_adapter, watchdog_task);
2307 struct e1000_hw *hw = &adapter->hw;
2308
2309 struct net_device *netdev = adapter->netdev;
2310 struct igb_ring *tx_ring = adapter->tx_ring;
2311 struct e1000_mac_info *mac = &adapter->hw.mac;
2312 u32 link;
2313 s32 ret_val;
2314
2315 if ((netif_carrier_ok(netdev)) &&
2316 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2317 goto link_up;
2318
2319 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2320 if ((ret_val == E1000_ERR_PHY) &&
2321 (hw->phy.type == e1000_phy_igp_3) &&
2322 (rd32(E1000_CTRL) &
2323 E1000_PHY_CTRL_GBE_DISABLE))
2324 dev_info(&adapter->pdev->dev,
2325 "Gigabit has been disabled, downgrading speed\n");
2326
2327 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2328 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2329 link = mac->serdes_has_link;
2330 else
2331 link = rd32(E1000_STATUS) &
2332 E1000_STATUS_LU;
2333
2334 if (link) {
2335 if (!netif_carrier_ok(netdev)) {
2336 u32 ctrl;
2337 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2338 &adapter->link_speed,
2339 &adapter->link_duplex);
2340
2341 ctrl = rd32(E1000_CTRL);
2342 dev_info(&adapter->pdev->dev,
2343 "NIC Link is Up %d Mbps %s, "
2344 "Flow Control: %s\n",
2345 adapter->link_speed,
2346 adapter->link_duplex == FULL_DUPLEX ?
2347 "Full Duplex" : "Half Duplex",
2348 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2349 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2350 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2351 E1000_CTRL_TFCE) ? "TX" : "None")));
2352
2353 /* tweak tx_queue_len according to speed/duplex and
2354 * adjust the timeout factor */
2355 netdev->tx_queue_len = adapter->tx_queue_len;
2356 adapter->tx_timeout_factor = 1;
2357 switch (adapter->link_speed) {
2358 case SPEED_10:
2359 netdev->tx_queue_len = 10;
2360 adapter->tx_timeout_factor = 14;
2361 break;
2362 case SPEED_100:
2363 netdev->tx_queue_len = 100;
2364 /* maybe add some timeout factor ? */
2365 break;
2366 }
2367
2368 netif_carrier_on(netdev);
fd2ea0a7 2369 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2370
2371 if (!test_bit(__IGB_DOWN, &adapter->state))
2372 mod_timer(&adapter->phy_info_timer,
2373 round_jiffies(jiffies + 2 * HZ));
2374 }
2375 } else {
2376 if (netif_carrier_ok(netdev)) {
2377 adapter->link_speed = 0;
2378 adapter->link_duplex = 0;
2379 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2380 netif_carrier_off(netdev);
fd2ea0a7 2381 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2382 if (!test_bit(__IGB_DOWN, &adapter->state))
2383 mod_timer(&adapter->phy_info_timer,
2384 round_jiffies(jiffies + 2 * HZ));
2385 }
2386 }
2387
2388link_up:
2389 igb_update_stats(adapter);
2390
2391 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2392 adapter->tpt_old = adapter->stats.tpt;
2393 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2394 adapter->colc_old = adapter->stats.colc;
2395
2396 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2397 adapter->gorc_old = adapter->stats.gorc;
2398 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2399 adapter->gotc_old = adapter->stats.gotc;
2400
2401 igb_update_adaptive(&adapter->hw);
2402
2403 if (!netif_carrier_ok(netdev)) {
2404 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2405 /* We've lost link, so the controller stops DMA,
2406 * but we've got queued Tx work that's never going
2407 * to get done, so reset controller to flush Tx.
2408 * (Do the reset outside of interrupt context). */
2409 adapter->tx_timeout_count++;
2410 schedule_work(&adapter->reset_task);
2411 }
2412 }
2413
2414 /* Cause software interrupt to ensure rx ring is cleaned */
2415 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2416
2417 /* Force detection of hung controller every watchdog period */
2418 tx_ring->detect_tx_hung = true;
2419
2420 /* Reset the timer */
2421 if (!test_bit(__IGB_DOWN, &adapter->state))
2422 mod_timer(&adapter->watchdog_timer,
2423 round_jiffies(jiffies + 2 * HZ));
2424}
2425
2426enum latency_range {
2427 lowest_latency = 0,
2428 low_latency = 1,
2429 bulk_latency = 2,
2430 latency_invalid = 255
2431};
2432
2433
6eb5a7f1
AD		 2434/**
2435 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2436 *
2437 * Stores a new ITR value based on strictly on packet size. This
2438 * algorithm is less sophisticated than that used in igb_update_itr,
2439 * due to the difficulty of synchronizing statistics across multiple
2440 * receive rings. The divisors and thresholds used by this fuction
2441 * were determined based on theoretical maximum wire speed and testing
2442 * data, in order to minimize response time while increasing bulk
2443 * throughput.
2444 * This functionality is controlled by the InterruptThrottleRate module
2445 * parameter (see igb_param.c)
2446 * NOTE: This function is called only when operating in a multiqueue
2447 * receive environment.
2448 * @rx_ring: pointer to ring
2449 **/
2450static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2451{
6eb5a7f1
AD		 2452 int new_val = rx_ring->itr_val;
2453 int avg_wire_size = 0;
2454 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2455
6eb5a7f1
AD		 2456 if (!rx_ring->total_packets)
2457 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2458
6eb5a7f1
AD		 2459 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2460 * ints/sec - ITR timer value of 120 ticks.
2461 */
2462 if (adapter->link_speed != SPEED_1000) {
2463 new_val = 120;
2464 goto set_itr_val;
9d5c8243 2465 }
6eb5a7f1 2466 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2467
6eb5a7f1
AD		 2468 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2469 avg_wire_size += 24;
2470
2471 /* Don't starve jumbo frames */
2472 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2473
6eb5a7f1
AD		 2474 /* Give a little boost to mid-size frames */
2475 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2476 new_val = avg_wire_size / 3;
2477 else
2478 new_val = avg_wire_size / 2;
9d5c8243 2479
6eb5a7f1 2480set_itr_val:
9d5c8243
AK		 2481 if (new_val != rx_ring->itr_val) {
2482 rx_ring->itr_val = new_val;
6eb5a7f1 2483 rx_ring->set_itr = 1;
9d5c8243 2484 }
6eb5a7f1
AD		 2485clear_counts:
2486 rx_ring->total_bytes = 0;
2487 rx_ring->total_packets = 0;
9d5c8243
AK		 2488}
2489
2490/**
2491 * igb_update_itr - update the dynamic ITR value based on statistics
2492 * Stores a new ITR value based on packets and byte
2493 * counts during the last interrupt. The advantage of per interrupt
2494 * computation is faster updates and more accurate ITR for the current
2495 * traffic pattern. Constants in this function were computed
2496 * based on theoretical maximum wire speed and thresholds were set based
2497 * on testing data as well as attempting to minimize response time
2498 * while increasing bulk throughput.
2499 * this functionality is controlled by the InterruptThrottleRate module
2500 * parameter (see igb_param.c)
2501 * NOTE: These calculations are only valid when operating in a single-
2502 * queue environment.
2503 * @adapter: pointer to adapter
2504 * @itr_setting: current adapter->itr
2505 * @packets: the number of packets during this measurement interval
2506 * @bytes: the number of bytes during this measurement interval
2507 **/
2508static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2509 int packets, int bytes)
2510{
2511 unsigned int retval = itr_setting;
2512
2513 if (packets == 0)
2514 goto update_itr_done;
2515
2516 switch (itr_setting) {
2517 case lowest_latency:
2518 /* handle TSO and jumbo frames */
2519 if (bytes/packets > 8000)
2520 retval = bulk_latency;
2521 else if ((packets < 5) && (bytes > 512))
2522 retval = low_latency;
2523 break;
2524 case low_latency: /* 50 usec aka 20000 ints/s */
2525 if (bytes > 10000) {
2526 /* this if handles the TSO accounting */
2527 if (bytes/packets > 8000) {
2528 retval = bulk_latency;
2529 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2530 retval = bulk_latency;
2531 } else if ((packets > 35)) {
2532 retval = lowest_latency;
2533 }
2534 } else if (bytes/packets > 2000) {
2535 retval = bulk_latency;
2536 } else if (packets <= 2 && bytes < 512) {
2537 retval = lowest_latency;
2538 }
2539 break;
2540 case bulk_latency: /* 250 usec aka 4000 ints/s */
2541 if (bytes > 25000) {
2542 if (packets > 35)
2543 retval = low_latency;
2544 } else if (bytes < 6000) {
2545 retval = low_latency;
2546 }
2547 break;
2548 }
2549
2550update_itr_done:
2551 return retval;
2552}
2553
6eb5a7f1 2554static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2555{
2556 u16 current_itr;
2557 u32 new_itr = adapter->itr;
2558
2559 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2560 if (adapter->link_speed != SPEED_1000) {
2561 current_itr = 0;
2562 new_itr = 4000;
2563 goto set_itr_now;
2564 }
2565
2566 adapter->rx_itr = igb_update_itr(adapter,
2567 adapter->rx_itr,
2568 adapter->rx_ring->total_packets,
2569 adapter->rx_ring->total_bytes);
9d5c8243 2570
6eb5a7f1 2571 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2572 adapter->tx_itr = igb_update_itr(adapter,
2573 adapter->tx_itr,
2574 adapter->tx_ring->total_packets,
2575 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2576
2577 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2578 } else {
2579 current_itr = adapter->rx_itr;
2580 }
2581
6eb5a7f1
AD		 2582 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2583 if (adapter->itr_setting == 3 &&
2584 current_itr == lowest_latency)
2585 current_itr = low_latency;
2586
9d5c8243
AK		 2587 switch (current_itr) {
2588 /* counts and packets in update_itr are dependent on these numbers */
2589 case lowest_latency:
2590 new_itr = 70000;
2591 break;
2592 case low_latency:
2593 new_itr = 20000; /* aka hwitr = ~200 */
2594 break;
2595 case bulk_latency:
2596 new_itr = 4000;
2597 break;
2598 default:
2599 break;
2600 }
2601
2602set_itr_now:
6eb5a7f1
AD		 2603 adapter->rx_ring->total_bytes = 0;
2604 adapter->rx_ring->total_packets = 0;
2605 if (adapter->rx_ring->buddy) {
2606 adapter->rx_ring->buddy->total_bytes = 0;
2607 adapter->rx_ring->buddy->total_packets = 0;
2608 }
2609
9d5c8243
AK		 2610 if (new_itr != adapter->itr) {
2611 /* this attempts to bias the interrupt rate towards Bulk
2612 * by adding intermediate steps when interrupt rate is
2613 * increasing */
2614 new_itr = new_itr > adapter->itr ?
2615 min(adapter->itr + (new_itr >> 2), new_itr) :
2616 new_itr;
2617 /* Don't write the value here; it resets the adapter's
2618 * internal timer, and causes us to delay far longer than
2619 * we should between interrupts. Instead, we write the ITR
2620 * value at the beginning of the next interrupt so the timing
2621 * ends up being correct.
2622 */
2623 adapter->itr = new_itr;
6eb5a7f1
AD		 2624 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2625 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2626 }
2627
2628 return;
2629}
2630
2631
2632#define IGB_TX_FLAGS_CSUM 0x00000001
2633#define IGB_TX_FLAGS_VLAN 0x00000002
2634#define IGB_TX_FLAGS_TSO 0x00000004
2635#define IGB_TX_FLAGS_IPV4 0x00000008
2636#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2637#define IGB_TX_FLAGS_VLAN_SHIFT 16
2638
2639static inline int igb_tso_adv(struct igb_adapter *adapter,
2640 struct igb_ring *tx_ring,
2641 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2642{
2643 struct e1000_adv_tx_context_desc *context_desc;
2644 unsigned int i;
2645 int err;
2646 struct igb_buffer *buffer_info;
2647 u32 info = 0, tu_cmd = 0;
2648 u32 mss_l4len_idx, l4len;
2649 *hdr_len = 0;
2650
2651 if (skb_header_cloned(skb)) {
2652 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2653 if (err)
2654 return err;
2655 }
2656
2657 l4len = tcp_hdrlen(skb);
2658 *hdr_len += l4len;
2659
2660 if (skb->protocol == htons(ETH_P_IP)) {
2661 struct iphdr *iph = ip_hdr(skb);
2662 iph->tot_len = 0;
2663 iph->check = 0;
2664 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2665 iph->daddr, 0,
2666 IPPROTO_TCP,
2667 0);
2668 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2669 ipv6_hdr(skb)->payload_len = 0;
2670 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2671 &ipv6_hdr(skb)->daddr,
2672 0, IPPROTO_TCP, 0);
2673 }
2674
2675 i = tx_ring->next_to_use;
2676
2677 buffer_info = &tx_ring->buffer_info[i];
2678 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2679 /* VLAN MACLEN IPLEN */
2680 if (tx_flags & IGB_TX_FLAGS_VLAN)
2681 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2682 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2683 *hdr_len += skb_network_offset(skb);
2684 info |= skb_network_header_len(skb);
2685 *hdr_len += skb_network_header_len(skb);
2686 context_desc->vlan_macip_lens = cpu_to_le32(info);
2687
2688 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2689 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2690
2691 if (skb->protocol == htons(ETH_P_IP))
2692 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2693 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2694
2695 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2696
2697 /* MSS L4LEN IDX */
2698 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2699 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2700
7dfc16fa
AD		 2701 /* Context index must be unique per ring. */
2702 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2703 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2704
2705 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2706 context_desc->seqnum_seed = 0;
2707
2708 buffer_info->time_stamp = jiffies;
2709 buffer_info->dma = 0;
2710 i++;
2711 if (i == tx_ring->count)
2712 i = 0;
2713
2714 tx_ring->next_to_use = i;
2715
2716 return true;
2717}
2718
2719static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2720 struct igb_ring *tx_ring,
2721 struct sk_buff *skb, u32 tx_flags)
2722{
2723 struct e1000_adv_tx_context_desc *context_desc;
2724 unsigned int i;
2725 struct igb_buffer *buffer_info;
2726 u32 info = 0, tu_cmd = 0;
2727
2728 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2729 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2730 i = tx_ring->next_to_use;
2731 buffer_info = &tx_ring->buffer_info[i];
2732 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2733
2734 if (tx_flags & IGB_TX_FLAGS_VLAN)
2735 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2736 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2737 if (skb->ip_summed == CHECKSUM_PARTIAL)
2738 info |= skb_network_header_len(skb);
2739
2740 context_desc->vlan_macip_lens = cpu_to_le32(info);
2741
2742 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2743
2744 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2745 switch (skb->protocol) {
2746 case __constant_htons(ETH_P_IP):
9d5c8243 2747 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2748 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2749 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2750 break;
2751 case __constant_htons(ETH_P_IPV6):
2752 /* XXX what about other V6 headers?? */
2753 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2754 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2755 break;
2756 default:
2757 if (unlikely(net_ratelimit()))
2758 dev_warn(&adapter->pdev->dev,
2759 "partial checksum but proto=%x!\n",
2760 skb->protocol);
2761 break;
2762 }
9d5c8243
AK		 2763 }
2764
2765 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2766 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2767 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2768 context_desc->mss_l4len_idx =
2769 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2770
2771 buffer_info->time_stamp = jiffies;
2772 buffer_info->dma = 0;
2773
2774 i++;
2775 if (i == tx_ring->count)
2776 i = 0;
2777 tx_ring->next_to_use = i;
2778
2779 return true;
2780 }
2781
2782
2783 return false;
2784}
2785
2786#define IGB_MAX_TXD_PWR 16
2787#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2788
2789static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2790 struct igb_ring *tx_ring,
2791 struct sk_buff *skb)
2792{
2793 struct igb_buffer *buffer_info;
2794 unsigned int len = skb_headlen(skb);
2795 unsigned int count = 0, i;
2796 unsigned int f;
2797
2798 i = tx_ring->next_to_use;
2799
2800 buffer_info = &tx_ring->buffer_info[i];
2801 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2802 buffer_info->length = len;
2803 /* set time_stamp *before* dma to help avoid a possible race */
2804 buffer_info->time_stamp = jiffies;
2805 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2806 PCI_DMA_TODEVICE);
2807 count++;
2808 i++;
2809 if (i == tx_ring->count)
2810 i = 0;
2811
2812 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2813 struct skb_frag_struct *frag;
2814
2815 frag = &skb_shinfo(skb)->frags[f];
2816 len = frag->size;
2817
2818 buffer_info = &tx_ring->buffer_info[i];
2819 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2820 buffer_info->length = len;
2821 buffer_info->time_stamp = jiffies;
2822 buffer_info->dma = pci_map_page(adapter->pdev,
2823 frag->page,
2824 frag->page_offset,
2825 len,
2826 PCI_DMA_TODEVICE);
2827
2828 count++;
2829 i++;
2830 if (i == tx_ring->count)
2831 i = 0;
2832 }
2833
2834 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2835 tx_ring->buffer_info[i].skb = skb;
2836
2837 return count;
2838}
2839
2840static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2841 struct igb_ring *tx_ring,
2842 int tx_flags, int count, u32 paylen,
2843 u8 hdr_len)
2844{
2845 union e1000_adv_tx_desc *tx_desc = NULL;
2846 struct igb_buffer *buffer_info;
2847 u32 olinfo_status = 0, cmd_type_len;
2848 unsigned int i;
2849
2850 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2851 E1000_ADVTXD_DCMD_DEXT);
2852
2853 if (tx_flags & IGB_TX_FLAGS_VLAN)
2854 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2855
2856 if (tx_flags & IGB_TX_FLAGS_TSO) {
2857 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2858
2859 /* insert tcp checksum */
2860 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2861
2862 /* insert ip checksum */
2863 if (tx_flags & IGB_TX_FLAGS_IPV4)
2864 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2865
2866 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2867 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2868 }
2869
7dfc16fa
AD		 2870 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2871 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2872 IGB_TX_FLAGS_VLAN)))
661086df 2873 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2874
2875 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2876
2877 i = tx_ring->next_to_use;
2878 while (count--) {
2879 buffer_info = &tx_ring->buffer_info[i];
2880 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2881 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2882 tx_desc->read.cmd_type_len =
2883 cpu_to_le32(cmd_type_len | buffer_info->length);
2884 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2885 i++;
2886 if (i == tx_ring->count)
2887 i = 0;
2888 }
2889
2890 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2891 /* Force memory writes to complete before letting h/w
2892 * know there are new descriptors to fetch. (Only
2893 * applicable for weak-ordered memory model archs,
2894 * such as IA-64). */
2895 wmb();
2896
2897 tx_ring->next_to_use = i;
2898 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2899 /* we need this if more than one processor can write to our tail
2900 * at a time, it syncronizes IO on IA64/Altix systems */
2901 mmiowb();
2902}
2903
2904static int __igb_maybe_stop_tx(struct net_device *netdev,
2905 struct igb_ring *tx_ring, int size)
2906{
2907 struct igb_adapter *adapter = netdev_priv(netdev);
2908
661086df 2909 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2910
9d5c8243
AK		 2911 /* Herbert's original patch had:
2912 * smp_mb__after_netif_stop_queue();
2913 * but since that doesn't exist yet, just open code it. */
2914 smp_mb();
2915
2916 /* We need to check again in a case another CPU has just
2917 * made room available. */
2918 if (IGB_DESC_UNUSED(tx_ring) < size)
2919 return -EBUSY;
2920
2921 /* A reprieve! */
661086df 2922 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2923 ++adapter->restart_queue;
2924 return 0;
2925}
2926
2927static int igb_maybe_stop_tx(struct net_device *netdev,
2928 struct igb_ring *tx_ring, int size)
2929{
2930 if (IGB_DESC_UNUSED(tx_ring) >= size)
2931 return 0;
2932 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2933}
2934
2935#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2936
2937static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2938 struct net_device *netdev,
2939 struct igb_ring *tx_ring)
2940{
2941 struct igb_adapter *adapter = netdev_priv(netdev);
2942 unsigned int tx_flags = 0;
2943 unsigned int len;
9d5c8243
AK		 2944 u8 hdr_len = 0;
2945 int tso = 0;
2946
2947 len = skb_headlen(skb);
2948
2949 if (test_bit(__IGB_DOWN, &adapter->state)) {
2950 dev_kfree_skb_any(skb);
2951 return NETDEV_TX_OK;
2952 }
2953
2954 if (skb->len <= 0) {
2955 dev_kfree_skb_any(skb);
2956 return NETDEV_TX_OK;
2957 }
2958
9d5c8243
AK		 2959 /* need: 1 descriptor per page,
2960 * + 2 desc gap to keep tail from touching head,
2961 * + 1 desc for skb->data,
2962 * + 1 desc for context descriptor,
2963 * otherwise try next time */
2964 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2965 /* this is a hard error */
9d5c8243
AK		 2966 return NETDEV_TX_BUSY;
2967 }
6eb5a7f1 2968 skb_orphan(skb);
9d5c8243
AK		 2969
2970 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2971 tx_flags |= IGB_TX_FLAGS_VLAN;
2972 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2973 }
2974
661086df
PWJ		 2975 if (skb->protocol == htons(ETH_P_IP))
2976 tx_flags |= IGB_TX_FLAGS_IPV4;
2977
9d5c8243
AK		 2978 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2979 &hdr_len) : 0;
2980
2981 if (tso < 0) {
2982 dev_kfree_skb_any(skb);
9d5c8243
AK		 2983 return NETDEV_TX_OK;
2984 }
2985
2986 if (tso)
2987 tx_flags |= IGB_TX_FLAGS_TSO;
2988 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2989 if (skb->ip_summed == CHECKSUM_PARTIAL)
2990 tx_flags |= IGB_TX_FLAGS_CSUM;
2991
9d5c8243
AK		 2992 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2993 igb_tx_map_adv(adapter, tx_ring, skb),
2994 skb->len, hdr_len);
2995
2996 netdev->trans_start = jiffies;
2997
2998 /* Make sure there is space in the ring for the next send. */
2999 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3000
9d5c8243
AK		 3001 return NETDEV_TX_OK;
3002}
3003
3004static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3005{
3006 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3007 struct igb_ring *tx_ring;
3008
661086df
PWJ		 3009 int r_idx = 0;
3010 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3011 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3012
3013 /* This goes back to the question of how to logically map a tx queue
3014 * to a flow. Right now, performance is impacted slightly negatively
3015 * if using multiple tx queues. If the stack breaks away from a
3016 * single qdisc implementation, we can look at this again. */
3017 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3018}
3019
3020/**
3021 * igb_tx_timeout - Respond to a Tx Hang
3022 * @netdev: network interface device structure
3023 **/
3024static void igb_tx_timeout(struct net_device *netdev)
3025{
3026 struct igb_adapter *adapter = netdev_priv(netdev);
3027 struct e1000_hw *hw = &adapter->hw;
3028
3029 /* Do the reset outside of interrupt context */
3030 adapter->tx_timeout_count++;
3031 schedule_work(&adapter->reset_task);
3032 wr32(E1000_EICS, adapter->eims_enable_mask &
3033 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3034}
3035
3036static void igb_reset_task(struct work_struct *work)
3037{
3038 struct igb_adapter *adapter;
3039 adapter = container_of(work, struct igb_adapter, reset_task);
3040
3041 igb_reinit_locked(adapter);
3042}
3043
3044/**
3045 * igb_get_stats - Get System Network Statistics
3046 * @netdev: network interface device structure
3047 *
3048 * Returns the address of the device statistics structure.
3049 * The statistics are actually updated from the timer callback.
3050 **/
3051static struct net_device_stats *
3052igb_get_stats(struct net_device *netdev)
3053{
3054 struct igb_adapter *adapter = netdev_priv(netdev);
3055
3056 /* only return the current stats */
3057 return &adapter->net_stats;
3058}
3059
3060/**
3061 * igb_change_mtu - Change the Maximum Transfer Unit
3062 * @netdev: network interface device structure
3063 * @new_mtu: new value for maximum frame size
3064 *
3065 * Returns 0 on success, negative on failure
3066 **/
3067static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3068{
3069 struct igb_adapter *adapter = netdev_priv(netdev);
3070 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3071
3072 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3073 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3074 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3075 return -EINVAL;
3076 }
3077
3078#define MAX_STD_JUMBO_FRAME_SIZE 9234
3079 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3080 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3081 return -EINVAL;
3082 }
3083
3084 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3085 msleep(1);
3086 /* igb_down has a dependency on max_frame_size */
3087 adapter->max_frame_size = max_frame;
3088 if (netif_running(netdev))
3089 igb_down(adapter);
3090
3091 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3092 * means we reserve 2 more, this pushes us to allocate from the next
3093 * larger slab size.
3094 * i.e. RXBUFFER_2048 --> size-4096 slab
3095 */
3096
3097 if (max_frame <= IGB_RXBUFFER_256)
3098 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3099 else if (max_frame <= IGB_RXBUFFER_512)
3100 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3101 else if (max_frame <= IGB_RXBUFFER_1024)
3102 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3103 else if (max_frame <= IGB_RXBUFFER_2048)
3104 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3105 else
bf36c1a0
AD		 3106#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3107 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3108#else
3109 adapter->rx_buffer_len = PAGE_SIZE / 2;
3110#endif
9d5c8243
AK		 3111 /* adjust allocation if LPE protects us, and we aren't using SBP */
3112 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3113 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3114 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3115
3116 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3117 netdev->mtu, new_mtu);
3118 netdev->mtu = new_mtu;
3119
3120 if (netif_running(netdev))
3121 igb_up(adapter);
3122 else
3123 igb_reset(adapter);
3124
3125 clear_bit(__IGB_RESETTING, &adapter->state);
3126
3127 return 0;
3128}
3129
3130/**
3131 * igb_update_stats - Update the board statistics counters
3132 * @adapter: board private structure
3133 **/
3134
3135void igb_update_stats(struct igb_adapter *adapter)
3136{
3137 struct e1000_hw *hw = &adapter->hw;
3138 struct pci_dev *pdev = adapter->pdev;
3139 u16 phy_tmp;
3140
3141#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3142
3143 /*
3144 * Prevent stats update while adapter is being reset, or if the pci
3145 * connection is down.
3146 */
3147 if (adapter->link_speed == 0)
3148 return;
3149 if (pci_channel_offline(pdev))
3150 return;
3151
3152 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3153 adapter->stats.gprc += rd32(E1000_GPRC);
3154 adapter->stats.gorc += rd32(E1000_GORCL);
3155 rd32(E1000_GORCH); /* clear GORCL */
3156 adapter->stats.bprc += rd32(E1000_BPRC);
3157 adapter->stats.mprc += rd32(E1000_MPRC);
3158 adapter->stats.roc += rd32(E1000_ROC);
3159
3160 adapter->stats.prc64 += rd32(E1000_PRC64);
3161 adapter->stats.prc127 += rd32(E1000_PRC127);
3162 adapter->stats.prc255 += rd32(E1000_PRC255);
3163 adapter->stats.prc511 += rd32(E1000_PRC511);
3164 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3165 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3166 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3167 adapter->stats.sec += rd32(E1000_SEC);
3168
3169 adapter->stats.mpc += rd32(E1000_MPC);
3170 adapter->stats.scc += rd32(E1000_SCC);
3171 adapter->stats.ecol += rd32(E1000_ECOL);
3172 adapter->stats.mcc += rd32(E1000_MCC);
3173 adapter->stats.latecol += rd32(E1000_LATECOL);
3174 adapter->stats.dc += rd32(E1000_DC);
3175 adapter->stats.rlec += rd32(E1000_RLEC);
3176 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3177 adapter->stats.xontxc += rd32(E1000_XONTXC);
3178 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3179 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3180 adapter->stats.fcruc += rd32(E1000_FCRUC);
3181 adapter->stats.gptc += rd32(E1000_GPTC);
3182 adapter->stats.gotc += rd32(E1000_GOTCL);
3183 rd32(E1000_GOTCH); /* clear GOTCL */
3184 adapter->stats.rnbc += rd32(E1000_RNBC);
3185 adapter->stats.ruc += rd32(E1000_RUC);
3186 adapter->stats.rfc += rd32(E1000_RFC);
3187 adapter->stats.rjc += rd32(E1000_RJC);
3188 adapter->stats.tor += rd32(E1000_TORH);
3189 adapter->stats.tot += rd32(E1000_TOTH);
3190 adapter->stats.tpr += rd32(E1000_TPR);
3191
3192 adapter->stats.ptc64 += rd32(E1000_PTC64);
3193 adapter->stats.ptc127 += rd32(E1000_PTC127);
3194 adapter->stats.ptc255 += rd32(E1000_PTC255);
3195 adapter->stats.ptc511 += rd32(E1000_PTC511);
3196 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3197 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3198
3199 adapter->stats.mptc += rd32(E1000_MPTC);
3200 adapter->stats.bptc += rd32(E1000_BPTC);
3201
3202 /* used for adaptive IFS */
3203
3204 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3205 adapter->stats.tpt += hw->mac.tx_packet_delta;
3206 hw->mac.collision_delta = rd32(E1000_COLC);
3207 adapter->stats.colc += hw->mac.collision_delta;
3208
3209 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3210 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3211 adapter->stats.tncrs += rd32(E1000_TNCRS);
3212 adapter->stats.tsctc += rd32(E1000_TSCTC);
3213 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3214
3215 adapter->stats.iac += rd32(E1000_IAC);
3216 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3217 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3218 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3219 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3220 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3221 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3222 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3223 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3224
3225 /* Fill out the OS statistics structure */
3226 adapter->net_stats.multicast = adapter->stats.mprc;
3227 adapter->net_stats.collisions = adapter->stats.colc;
3228
3229 /* Rx Errors */
3230
3231 /* RLEC on some newer hardware can be incorrect so build
3232 * our own version based on RUC and ROC */
3233 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3234 adapter->stats.crcerrs + adapter->stats.algnerrc +
3235 adapter->stats.ruc + adapter->stats.roc +
3236 adapter->stats.cexterr;
3237 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3238 adapter->stats.roc;
3239 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3240 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3241 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3242
3243 /* Tx Errors */
3244 adapter->net_stats.tx_errors = adapter->stats.ecol +
3245 adapter->stats.latecol;
3246 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3247 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3248 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3249
3250 /* Tx Dropped needs to be maintained elsewhere */
3251
3252 /* Phy Stats */
3253 if (hw->phy.media_type == e1000_media_type_copper) {
3254 if ((adapter->link_speed == SPEED_1000) &&
3255 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3256 &phy_tmp))) {
3257 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3258 adapter->phy_stats.idle_errors += phy_tmp;
3259 }
3260 }
3261
3262 /* Management Stats */
3263 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3264 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3265 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3266}
3267
3268
3269static irqreturn_t igb_msix_other(int irq, void *data)
3270{
3271 struct net_device *netdev = data;
3272 struct igb_adapter *adapter = netdev_priv(netdev);
3273 struct e1000_hw *hw = &adapter->hw;
844290e5 3274 u32 icr = rd32(E1000_ICR);
9d5c8243 3275
844290e5
PW		 3276 /* reading ICR causes bit 31 of EICR to be cleared */
3277 if (!(icr & E1000_ICR_LSC))
3278 goto no_link_interrupt;
3279 hw->mac.get_link_status = 1;
3280 /* guard against interrupt when we're going down */
3281 if (!test_bit(__IGB_DOWN, &adapter->state))
3282 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3283
9d5c8243
AK		 3284no_link_interrupt:
3285 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3286 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3287
3288 return IRQ_HANDLED;
3289}
3290
3291static irqreturn_t igb_msix_tx(int irq, void *data)
3292{
3293 struct igb_ring *tx_ring = data;
3294 struct igb_adapter *adapter = tx_ring->adapter;
3295 struct e1000_hw *hw = &adapter->hw;
3296
fe4506b6 3297#ifdef CONFIG_DCA
7dfc16fa 3298 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3299 igb_update_tx_dca(tx_ring);
3300#endif
9d5c8243
AK		 3301 tx_ring->total_bytes = 0;
3302 tx_ring->total_packets = 0;
661086df
PWJ		 3303
3304 /* auto mask will automatically reenable the interrupt when we write
3305 * EICS */
3b644cf6 3306 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3307 /* Ring was not completely cleaned, so fire another interrupt */
3308 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3309 else
9d5c8243 3310 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3311
9d5c8243
AK		 3312 return IRQ_HANDLED;
3313}
3314
6eb5a7f1
AD		 3315static void igb_write_itr(struct igb_ring *ring)
3316{
3317 struct e1000_hw *hw = &ring->adapter->hw;
3318 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3319 switch (hw->mac.type) {
3320 case e1000_82576:
3321 wr32(ring->itr_register,
3322 ring->itr_val |
3323 0x80000000);
3324 break;
3325 default:
3326 wr32(ring->itr_register,
3327 ring->itr_val |
3328 (ring->itr_val << 16));
3329 break;
3330 }
3331 ring->set_itr = 0;
3332 }
3333}
3334
9d5c8243
AK		 3335static irqreturn_t igb_msix_rx(int irq, void *data)
3336{
3337 struct igb_ring *rx_ring = data;
3338 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3339
844290e5
PW		 3340 /* Write the ITR value calculated at the end of the
3341 * previous interrupt.
3342 */
9d5c8243 3343
6eb5a7f1 3344 igb_write_itr(rx_ring);
9d5c8243 3345
844290e5
PW		 3346 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3347 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3348
fe4506b6 3349#ifdef CONFIG_DCA
7dfc16fa 3350 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3351 igb_update_rx_dca(rx_ring);
3352#endif
3353 return IRQ_HANDLED;
3354}
3355
3356#ifdef CONFIG_DCA
3357static void igb_update_rx_dca(struct igb_ring *rx_ring)
3358{
3359 u32 dca_rxctrl;
3360 struct igb_adapter *adapter = rx_ring->adapter;
3361 struct e1000_hw *hw = &adapter->hw;
3362 int cpu = get_cpu();
3363 int q = rx_ring - adapter->rx_ring;
3364
3365 if (rx_ring->cpu != cpu) {
3366 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3367 if (hw->mac.type == e1000_82576) {
3368 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3369 dca_rxctrl |= dca_get_tag(cpu) <<
3370 E1000_DCA_RXCTRL_CPUID_SHIFT;
3371 } else {
3372 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3373 dca_rxctrl |= dca_get_tag(cpu);
3374 }
fe4506b6
JC		 3375 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3376 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3377 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3378 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3379 rx_ring->cpu = cpu;
3380 }
3381 put_cpu();
3382}
3383
3384static void igb_update_tx_dca(struct igb_ring *tx_ring)
3385{
3386 u32 dca_txctrl;
3387 struct igb_adapter *adapter = tx_ring->adapter;
3388 struct e1000_hw *hw = &adapter->hw;
3389 int cpu = get_cpu();
3390 int q = tx_ring - adapter->tx_ring;
3391
3392 if (tx_ring->cpu != cpu) {
3393 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3394 if (hw->mac.type == e1000_82576) {
3395 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3396 dca_txctrl |= dca_get_tag(cpu) <<
3397 E1000_DCA_TXCTRL_CPUID_SHIFT;
3398 } else {
3399 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3400 dca_txctrl |= dca_get_tag(cpu);
3401 }
fe4506b6
JC		 3402 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3403 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3404 tx_ring->cpu = cpu;
3405 }
3406 put_cpu();
3407}
3408
3409static void igb_setup_dca(struct igb_adapter *adapter)
3410{
3411 int i;
3412
7dfc16fa 3413 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3414 return;
3415
3416 for (i = 0; i < adapter->num_tx_queues; i++) {
3417 adapter->tx_ring[i].cpu = -1;
3418 igb_update_tx_dca(&adapter->tx_ring[i]);
3419 }
3420 for (i = 0; i < adapter->num_rx_queues; i++) {
3421 adapter->rx_ring[i].cpu = -1;
3422 igb_update_rx_dca(&adapter->rx_ring[i]);
3423 }
3424}
3425
3426static int __igb_notify_dca(struct device *dev, void *data)
3427{
3428 struct net_device *netdev = dev_get_drvdata(dev);
3429 struct igb_adapter *adapter = netdev_priv(netdev);
3430 struct e1000_hw *hw = &adapter->hw;
3431 unsigned long event = *(unsigned long *)data;
3432
7dfc16fa
AD		 3433 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3434 goto out;
3435
fe4506b6
JC		 3436 switch (event) {
3437 case DCA_PROVIDER_ADD:
3438 /* if already enabled, don't do it again */
7dfc16fa 3439 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3440 break;
7dfc16fa 3441 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3442 /* Always use CB2 mode, difference is masked
3443 * in the CB driver. */
3444 wr32(E1000_DCA_CTRL, 2);
3445 if (dca_add_requester(dev) == 0) {
3446 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3447 igb_setup_dca(adapter);
3448 break;
3449 }
3450 /* Fall Through since DCA is disabled. */
3451 case DCA_PROVIDER_REMOVE:
7dfc16fa 3452 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3453 /* without this a class_device is left
3454 * hanging around in the sysfs model */
3455 dca_remove_requester(dev);
3456 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3457 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3458 wr32(E1000_DCA_CTRL, 1);
3459 }
3460 break;
3461 }
7dfc16fa 3462out:
fe4506b6 3463 return 0;
9d5c8243
AK		 3464}
3465
fe4506b6
JC		 3466static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3467 void *p)
3468{
3469 int ret_val;
3470
3471 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3472 __igb_notify_dca);
3473
3474 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3475}
3476#endif /* CONFIG_DCA */
9d5c8243
AK		 3477
3478/**
3479 * igb_intr_msi - Interrupt Handler
3480 * @irq: interrupt number
3481 * @data: pointer to a network interface device structure
3482 **/
3483static irqreturn_t igb_intr_msi(int irq, void *data)
3484{
3485 struct net_device *netdev = data;
3486 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3487 struct e1000_hw *hw = &adapter->hw;
3488 /* read ICR disables interrupts using IAM */
3489 u32 icr = rd32(E1000_ICR);
3490
6eb5a7f1 3491 igb_write_itr(adapter->rx_ring);
9d5c8243 3492
9d5c8243
AK		 3493 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3494 hw->mac.get_link_status = 1;
3495 if (!test_bit(__IGB_DOWN, &adapter->state))
3496 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3497 }
3498
844290e5 3499 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3500
3501 return IRQ_HANDLED;
3502}
3503
3504/**
3505 * igb_intr - Interrupt Handler
3506 * @irq: interrupt number
3507 * @data: pointer to a network interface device structure
3508 **/
3509static irqreturn_t igb_intr(int irq, void *data)
3510{
3511 struct net_device *netdev = data;
3512 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3513 struct e1000_hw *hw = &adapter->hw;
3514 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3515 * need for the IMC write */
3516 u32 icr = rd32(E1000_ICR);
3517 u32 eicr = 0;
3518 if (!icr)
3519 return IRQ_NONE; /* Not our interrupt */
3520
6eb5a7f1 3521 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3522
3523 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3524 * not set, then the adapter didn't send an interrupt */
3525 if (!(icr & E1000_ICR_INT_ASSERTED))
3526 return IRQ_NONE;
3527
3528 eicr = rd32(E1000_EICR);
3529
3530 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3531 hw->mac.get_link_status = 1;
3532 /* guard against interrupt when we're going down */
3533 if (!test_bit(__IGB_DOWN, &adapter->state))
3534 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3535 }
3536
844290e5 3537 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3538
3539 return IRQ_HANDLED;
3540}
3541
3542/**
661086df
PWJ		 3543 * igb_poll - NAPI Rx polling callback
3544 * @napi: napi polling structure
3545 * @budget: count of how many packets we should handle
9d5c8243 3546 **/
661086df 3547static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3548{
661086df
PWJ		 3549 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3550 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3551 struct net_device *netdev = adapter->netdev;
661086df 3552 int tx_clean_complete, work_done = 0;
9d5c8243 3553
661086df 3554 /* this poll routine only supports one tx and one rx queue */
fe4506b6 3555#ifdef CONFIG_DCA
7dfc16fa 3556 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3557 igb_update_tx_dca(&adapter->tx_ring[0]);
3558#endif
661086df 3559 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6
JC		 3560
3561#ifdef CONFIG_DCA
7dfc16fa 3562 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3563 igb_update_rx_dca(&adapter->rx_ring[0]);
3564#endif
661086df 3565 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3566
3567 /* If no Tx and not enough Rx work done, exit the polling mode */
3568 if ((tx_clean_complete && (work_done < budget)) ||
3569 !netif_running(netdev)) {
9d5c8243 3570 if (adapter->itr_setting & 3)
6eb5a7f1 3571 igb_set_itr(adapter);
9d5c8243
AK		 3572 netif_rx_complete(netdev, napi);
3573 if (!test_bit(__IGB_DOWN, &adapter->state))
3574 igb_irq_enable(adapter);
3575 return 0;
3576 }
3577
3578 return 1;
3579}
3580
3581static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3582{
3583 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3584 struct igb_adapter *adapter = rx_ring->adapter;
3585 struct e1000_hw *hw = &adapter->hw;
3586 struct net_device *netdev = adapter->netdev;
3587 int work_done = 0;
3588
3589 /* Keep link state information with original netdev */
3590 if (!netif_carrier_ok(netdev))
3591 goto quit_polling;
3592
fe4506b6 3593#ifdef CONFIG_DCA
7dfc16fa 3594 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3595 igb_update_rx_dca(rx_ring);
3596#endif
3b644cf6 3597 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3598
3599
3600 /* If not enough Rx work done, exit the polling mode */
3601 if ((work_done == 0) || !netif_running(netdev)) {
3602quit_polling:
3603 netif_rx_complete(netdev, napi);
3604
6eb5a7f1
AD		 3605 if (adapter->itr_setting & 3) {
3606 if (adapter->num_rx_queues == 1)
3607 igb_set_itr(adapter);
3608 else
3609 igb_update_ring_itr(rx_ring);
9d5c8243 3610 }
844290e5
PW		 3611
3612 if (!test_bit(__IGB_DOWN, &adapter->state))
3613 wr32(E1000_EIMS, rx_ring->eims_value);
3614
9d5c8243
AK		 3615 return 0;
3616 }
3617
3618 return 1;
3619}
6d8126f9
AV		 3620
3621static inline u32 get_head(struct igb_ring *tx_ring)
3622{
3623 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3624 return le32_to_cpu(*(volatile __le32 *)end);
3625}
3626
9d5c8243
AK		 3627/**
3628 * igb_clean_tx_irq - Reclaim resources after transmit completes
3629 * @adapter: board private structure
3630 * returns true if ring is completely cleaned
3631 **/
3b644cf6 3632static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3633{
3b644cf6 3634 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3635 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3636 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3637 struct e1000_tx_desc *tx_desc;
3638 struct igb_buffer *buffer_info;
3639 struct sk_buff *skb;
3640 unsigned int i;
3641 u32 head, oldhead;
3642 unsigned int count = 0;
3643 bool cleaned = false;
3644 bool retval = true;
3645 unsigned int total_bytes = 0, total_packets = 0;
3646
3647 rmb();
6d8126f9 3648 head = get_head(tx_ring);
9d5c8243
AK		 3649 i = tx_ring->next_to_clean;
3650 while (1) {
3651 while (i != head) {
3652 cleaned = true;
3653 tx_desc = E1000_TX_DESC(*tx_ring, i);
3654 buffer_info = &tx_ring->buffer_info[i];
3655 skb = buffer_info->skb;
3656
3657 if (skb) {
3658 unsigned int segs, bytecount;
3659 /* gso_segs is currently only valid for tcp */
3660 segs = skb_shinfo(skb)->gso_segs ?: 1;
3661 /* multiply data chunks by size of headers */
3662 bytecount = ((segs - 1) * skb_headlen(skb)) +
3663 skb->len;
3664 total_packets += segs;
3665 total_bytes += bytecount;
3666 }
3667
3668 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3669 tx_desc->upper.data = 0;
3670
3671 i++;
3672 if (i == tx_ring->count)
3673 i = 0;
3674
3675 count++;
3676 if (count == IGB_MAX_TX_CLEAN) {
3677 retval = false;
3678 goto done_cleaning;
3679 }
3680 }
3681 oldhead = head;
3682 rmb();
6d8126f9 3683 head = get_head(tx_ring);
9d5c8243
AK		 3684 if (head == oldhead)
3685 goto done_cleaning;
3686 } /* while (1) */
3687
3688done_cleaning:
3689 tx_ring->next_to_clean = i;
3690
3691 if (unlikely(cleaned &&
3692 netif_carrier_ok(netdev) &&
3693 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3694 /* Make sure that anybody stopping the queue after this
3695 * sees the new next_to_clean.
3696 */
3697 smp_mb();
661086df
PWJ		 3698 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3699 !(test_bit(__IGB_DOWN, &adapter->state))) {
3700 netif_wake_subqueue(netdev, tx_ring->queue_index);
3701 ++adapter->restart_queue;
3702 }
9d5c8243
AK		 3703 }
3704
3705 if (tx_ring->detect_tx_hung) {
3706 /* Detect a transmit hang in hardware, this serializes the
3707 * check with the clearing of time_stamp and movement of i */
3708 tx_ring->detect_tx_hung = false;
3709 if (tx_ring->buffer_info[i].time_stamp &&
3710 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3711 (adapter->tx_timeout_factor * HZ))
3712 && !(rd32(E1000_STATUS) &
3713 E1000_STATUS_TXOFF)) {
3714
3715 tx_desc = E1000_TX_DESC(*tx_ring, i);
3716 /* detected Tx unit hang */
3717 dev_err(&adapter->pdev->dev,
3718 "Detected Tx Unit Hang\n"
2d064c06 3719 " Tx Queue <%d>\n"
9d5c8243
AK		 3720 " TDH <%x>\n"
3721 " TDT <%x>\n"
3722 " next_to_use <%x>\n"
3723 " next_to_clean <%x>\n"
3724 " head (WB) <%x>\n"
3725 "buffer_info[next_to_clean]\n"
3726 " time_stamp <%lx>\n"
3727 " jiffies <%lx>\n"
3728 " desc.status <%x>\n",
2d064c06 3729 tx_ring->queue_index,
9d5c8243
AK		 3730 readl(adapter->hw.hw_addr + tx_ring->head),
3731 readl(adapter->hw.hw_addr + tx_ring->tail),
3732 tx_ring->next_to_use,
3733 tx_ring->next_to_clean,
3734 head,
3735 tx_ring->buffer_info[i].time_stamp,
3736 jiffies,
3737 tx_desc->upper.fields.status);
661086df 3738 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3739 }
3740 }
3741 tx_ring->total_bytes += total_bytes;
3742 tx_ring->total_packets += total_packets;
e21ed353
AD		 3743 tx_ring->tx_stats.bytes += total_bytes;
3744 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3745 adapter->net_stats.tx_bytes += total_bytes;
3746 adapter->net_stats.tx_packets += total_packets;
3747 return retval;
3748}
3749
d3352520
AD		 3750#ifdef CONFIG_IGB_LRO
3751 /**
3752 * igb_get_skb_hdr - helper function for LRO header processing
3753 * @skb: pointer to sk_buff to be added to LRO packet
3754 * @iphdr: pointer to ip header structure
3755 * @tcph: pointer to tcp header structure
3756 * @hdr_flags: pointer to header flags
3757 * @priv: pointer to the receive descriptor for the current sk_buff
3758 **/
3759static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3760 u64 *hdr_flags, void *priv)
3761{
3762 union e1000_adv_rx_desc *rx_desc = priv;
3763 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3764 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3765
3766 /* Verify that this is a valid IPv4 TCP packet */
3767 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3768 E1000_RXDADV_PKTTYPE_TCP))
3769 return -1;
3770
3771 /* Set network headers */
3772 skb_reset_network_header(skb);
3773 skb_set_transport_header(skb, ip_hdrlen(skb));
3774 *iphdr = ip_hdr(skb);
3775 *tcph = tcp_hdr(skb);
3776 *hdr_flags = LRO_IPV4 | LRO_TCP;
3777
3778 return 0;
3779
3780}
3781#endif /* CONFIG_IGB_LRO */
9d5c8243
AK		 3782
3783/**
3784 * igb_receive_skb - helper function to handle rx indications
d3352520 3785 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3786 * @status: descriptor status field as written by hardware
3787 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3788 * @skb: pointer to sk_buff to be indicated to stack
3789 **/
d3352520
AD		 3790static void igb_receive_skb(struct igb_ring *ring, u8 status,
3791 union e1000_adv_rx_desc * rx_desc,
3792 struct sk_buff *skb)
3793{
3794 struct igb_adapter * adapter = ring->adapter;
3795 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3796
3797#ifdef CONFIG_IGB_LRO
3798 if (adapter->netdev->features & NETIF_F_LRO &&
3799 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3800 if (vlan_extracted)
3801 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3802 adapter->vlgrp,
3803 le16_to_cpu(rx_desc->wb.upper.vlan),
3804 rx_desc);
3805 else
3806 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3807 ring->lro_used = 1;
3808 } else {
3809#endif
3810 if (vlan_extracted)
3811 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3812 le16_to_cpu(rx_desc->wb.upper.vlan));
3813 else
3814
3815 netif_receive_skb(skb);
3816#ifdef CONFIG_IGB_LRO
3817 }
3818#endif
9d5c8243
AK		 3819}
3820
3821
3822static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3823 u32 status_err, struct sk_buff *skb)
3824{
3825 skb->ip_summed = CHECKSUM_NONE;
3826
3827 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3828 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3829 return;
3830 /* TCP/UDP checksum error bit is set */
3831 if (status_err &
3832 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3833 /* let the stack verify checksum errors */
3834 adapter->hw_csum_err++;
3835 return;
3836 }
3837 /* It must be a TCP or UDP packet with a valid checksum */
3838 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3839 skb->ip_summed = CHECKSUM_UNNECESSARY;
3840
3841 adapter->hw_csum_good++;
3842}
3843
3b644cf6
MW		 3844static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3845 int *work_done, int budget)
9d5c8243 3846{
3b644cf6 3847 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3848 struct net_device *netdev = adapter->netdev;
3849 struct pci_dev *pdev = adapter->pdev;
3850 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3851 struct igb_buffer *buffer_info , *next_buffer;
3852 struct sk_buff *skb;
bf36c1a0 3853 unsigned int i;
9d5c8243
AK		 3854 u32 length, hlen, staterr;
3855 bool cleaned = false;
3856 int cleaned_count = 0;
3857 unsigned int total_bytes = 0, total_packets = 0;
3858
3859 i = rx_ring->next_to_clean;
3860 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3861 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3862
3863 while (staterr & E1000_RXD_STAT_DD) {
3864 if (*work_done >= budget)
3865 break;
3866 (*work_done)++;
3867 buffer_info = &rx_ring->buffer_info[i];
3868
3869 /* HW will not DMA in data larger than the given buffer, even
3870 * if it parses the (NFS, of course) header to be larger. In
3871 * that case, it fills the header buffer and spills the rest
3872 * into the page.
3873 */
7deb07b1
AV		 3874 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3875 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3876 if (hlen > adapter->rx_ps_hdr_size)
3877 hlen = adapter->rx_ps_hdr_size;
3878
3879 length = le16_to_cpu(rx_desc->wb.upper.length);
3880 cleaned = true;
3881 cleaned_count++;
3882
bf36c1a0
AD		 3883 skb = buffer_info->skb;
3884 prefetch(skb->data - NET_IP_ALIGN);
3885 buffer_info->skb = NULL;
3886 if (!adapter->rx_ps_hdr_size) {
3887 pci_unmap_single(pdev, buffer_info->dma,
3888 adapter->rx_buffer_len +
3889 NET_IP_ALIGN,
3890 PCI_DMA_FROMDEVICE);
3891 skb_put(skb, length);
3892 goto send_up;
9d5c8243
AK		 3893 }
3894
bf36c1a0
AD		 3895 if (!skb_shinfo(skb)->nr_frags) {
3896 pci_unmap_single(pdev, buffer_info->dma,
3897 adapter->rx_ps_hdr_size +
3898 NET_IP_ALIGN,
3899 PCI_DMA_FROMDEVICE);
3900 skb_put(skb, hlen);
3901 }
3902
3903 if (length) {
9d5c8243 3904 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3905 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3906 buffer_info->page_dma = 0;
bf36c1a0
AD		 3907
3908 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3909 buffer_info->page,
3910 buffer_info->page_offset,
3911 length);
3912
3913 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3914 (page_count(buffer_info->page) != 1))
3915 buffer_info->page = NULL;
3916 else
3917 get_page(buffer_info->page);
9d5c8243
AK		 3918
3919 skb->len += length;
3920 skb->data_len += length;
9d5c8243 3921
bf36c1a0 3922 skb->truesize += length;
9d5c8243
AK		 3923 }
3924send_up:
9d5c8243
AK		 3925 i++;
3926 if (i == rx_ring->count)
3927 i = 0;
3928 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3929 prefetch(next_rxd);
3930 next_buffer = &rx_ring->buffer_info[i];
3931
bf36c1a0
AD		 3932 if (!(staterr & E1000_RXD_STAT_EOP)) {
3933 buffer_info->skb = xchg(&next_buffer->skb, skb);
3934 buffer_info->dma = xchg(&next_buffer->dma, 0);
3935 goto next_desc;
3936 }
3937
9d5c8243
AK		 3938 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3939 dev_kfree_skb_irq(skb);
3940 goto next_desc;
3941 }
9d5c8243
AK		 3942
3943 total_bytes += skb->len;
3944 total_packets++;
3945
3946 igb_rx_checksum_adv(adapter, staterr, skb);
3947
3948 skb->protocol = eth_type_trans(skb, netdev);
3949
d3352520 3950 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243
AK		 3951
3952 netdev->last_rx = jiffies;
3953
3954next_desc:
3955 rx_desc->wb.upper.status_error = 0;
3956
3957 /* return some buffers to hardware, one at a time is too slow */
3958 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3959 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3960 cleaned_count = 0;
3961 }
3962
3963 /* use prefetched values */
3964 rx_desc = next_rxd;
3965 buffer_info = next_buffer;
3966
3967 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3968 }
bf36c1a0 3969
9d5c8243
AK		 3970 rx_ring->next_to_clean = i;
3971 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3972
d3352520
AD		 3973#ifdef CONFIG_IGB_LRO
3974 if (rx_ring->lro_used) {
3975 lro_flush_all(&rx_ring->lro_mgr);
3976 rx_ring->lro_used = 0;
3977 }
3978#endif
3979
9d5c8243 3980 if (cleaned_count)
3b644cf6 3981 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3982
3983 rx_ring->total_packets += total_packets;
3984 rx_ring->total_bytes += total_bytes;
3985 rx_ring->rx_stats.packets += total_packets;
3986 rx_ring->rx_stats.bytes += total_bytes;
3987 adapter->net_stats.rx_bytes += total_bytes;
3988 adapter->net_stats.rx_packets += total_packets;
3989 return cleaned;
3990}
3991
3992
3993/**
3994 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3995 * @adapter: address of board private structure
3996 **/
3b644cf6 3997static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3998 int cleaned_count)
3999{
3b644cf6 4000 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4001 struct net_device *netdev = adapter->netdev;
4002 struct pci_dev *pdev = adapter->pdev;
4003 union e1000_adv_rx_desc *rx_desc;
4004 struct igb_buffer *buffer_info;
4005 struct sk_buff *skb;
4006 unsigned int i;
4007
4008 i = rx_ring->next_to_use;
4009 buffer_info = &rx_ring->buffer_info[i];
4010
4011 while (cleaned_count--) {
4012 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4013
bf36c1a0 4014 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4015 if (!buffer_info->page) {
bf36c1a0
AD		 4016 buffer_info->page = alloc_page(GFP_ATOMIC);
4017 if (!buffer_info->page) {
4018 adapter->alloc_rx_buff_failed++;
4019 goto no_buffers;
4020 }
4021 buffer_info->page_offset = 0;
4022 } else {
4023 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4024 }
4025 buffer_info->page_dma =
4026 pci_map_page(pdev,
4027 buffer_info->page,
bf36c1a0
AD		 4028 buffer_info->page_offset,
4029 PAGE_SIZE / 2,
9d5c8243
AK		 4030 PCI_DMA_FROMDEVICE);
4031 }
4032
4033 if (!buffer_info->skb) {
4034 int bufsz;
4035
4036 if (adapter->rx_ps_hdr_size)
4037 bufsz = adapter->rx_ps_hdr_size;
4038 else
4039 bufsz = adapter->rx_buffer_len;
4040 bufsz += NET_IP_ALIGN;
4041 skb = netdev_alloc_skb(netdev, bufsz);
4042
4043 if (!skb) {
4044 adapter->alloc_rx_buff_failed++;
4045 goto no_buffers;
4046 }
4047
4048 /* Make buffer alignment 2 beyond a 16 byte boundary
4049 * this will result in a 16 byte aligned IP header after
4050 * the 14 byte MAC header is removed
4051 */
4052 skb_reserve(skb, NET_IP_ALIGN);
4053
4054 buffer_info->skb = skb;
4055 buffer_info->dma = pci_map_single(pdev, skb->data,
4056 bufsz,
4057 PCI_DMA_FROMDEVICE);
4058
4059 }
4060 /* Refresh the desc even if buffer_addrs didn't change because
4061 * each write-back erases this info. */
4062 if (adapter->rx_ps_hdr_size) {
4063 rx_desc->read.pkt_addr =
4064 cpu_to_le64(buffer_info->page_dma);
4065 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4066 } else {
4067 rx_desc->read.pkt_addr =
4068 cpu_to_le64(buffer_info->dma);
4069 rx_desc->read.hdr_addr = 0;
4070 }
4071
4072 i++;
4073 if (i == rx_ring->count)
4074 i = 0;
4075 buffer_info = &rx_ring->buffer_info[i];
4076 }
4077
4078no_buffers:
4079 if (rx_ring->next_to_use != i) {
4080 rx_ring->next_to_use = i;
4081 if (i == 0)
4082 i = (rx_ring->count - 1);
4083 else
4084 i--;
4085
4086 /* Force memory writes to complete before letting h/w
4087 * know there are new descriptors to fetch. (Only
4088 * applicable for weak-ordered memory model archs,
4089 * such as IA-64). */
4090 wmb();
4091 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4092 }
4093}
4094
4095/**
4096 * igb_mii_ioctl -
4097 * @netdev:
4098 * @ifreq:
4099 * @cmd:
4100 **/
4101static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4102{
4103 struct igb_adapter *adapter = netdev_priv(netdev);
4104 struct mii_ioctl_data *data = if_mii(ifr);
4105
4106 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4107 return -EOPNOTSUPP;
4108
4109 switch (cmd) {
4110 case SIOCGMIIPHY:
4111 data->phy_id = adapter->hw.phy.addr;
4112 break;
4113 case SIOCGMIIREG:
4114 if (!capable(CAP_NET_ADMIN))
4115 return -EPERM;
4116 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
4117 data->reg_num
4118 & 0x1F, &data->val_out))
4119 return -EIO;
4120 break;
4121 case SIOCSMIIREG:
4122 default:
4123 return -EOPNOTSUPP;
4124 }
4125 return 0;
4126}
4127
4128/**
4129 * igb_ioctl -
4130 * @netdev:
4131 * @ifreq:
4132 * @cmd:
4133 **/
4134static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4135{
4136 switch (cmd) {
4137 case SIOCGMIIPHY:
4138 case SIOCGMIIREG:
4139 case SIOCSMIIREG:
4140 return igb_mii_ioctl(netdev, ifr, cmd);
4141 default:
4142 return -EOPNOTSUPP;
4143 }
4144}
4145
4146static void igb_vlan_rx_register(struct net_device *netdev,
4147 struct vlan_group *grp)
4148{
4149 struct igb_adapter *adapter = netdev_priv(netdev);
4150 struct e1000_hw *hw = &adapter->hw;
4151 u32 ctrl, rctl;
4152
4153 igb_irq_disable(adapter);
4154 adapter->vlgrp = grp;
4155
4156 if (grp) {
4157 /* enable VLAN tag insert/strip */
4158 ctrl = rd32(E1000_CTRL);
4159 ctrl |= E1000_CTRL_VME;
4160 wr32(E1000_CTRL, ctrl);
4161
4162 /* enable VLAN receive filtering */
4163 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4164 rctl &= ~E1000_RCTL_CFIEN;
4165 wr32(E1000_RCTL, rctl);
4166 igb_update_mng_vlan(adapter);
4167 wr32(E1000_RLPML,
4168 adapter->max_frame_size + VLAN_TAG_SIZE);
4169 } else {
4170 /* disable VLAN tag insert/strip */
4171 ctrl = rd32(E1000_CTRL);
4172 ctrl &= ~E1000_CTRL_VME;
4173 wr32(E1000_CTRL, ctrl);
4174
9d5c8243
AK		 4175 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4176 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4177 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4178 }
4179 wr32(E1000_RLPML,
4180 adapter->max_frame_size);
4181 }
4182
4183 if (!test_bit(__IGB_DOWN, &adapter->state))
4184 igb_irq_enable(adapter);
4185}
4186
4187static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4188{
4189 struct igb_adapter *adapter = netdev_priv(netdev);
4190 struct e1000_hw *hw = &adapter->hw;
4191 u32 vfta, index;
4192
4193 if ((adapter->hw.mng_cookie.status &
4194 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4195 (vid == adapter->mng_vlan_id))
4196 return;
4197 /* add VID to filter table */
4198 index = (vid >> 5) & 0x7F;
4199 vfta = array_rd32(E1000_VFTA, index);
4200 vfta |= (1 << (vid & 0x1F));
4201 igb_write_vfta(&adapter->hw, index, vfta);
4202}
4203
4204static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4205{
4206 struct igb_adapter *adapter = netdev_priv(netdev);
4207 struct e1000_hw *hw = &adapter->hw;
4208 u32 vfta, index;
4209
4210 igb_irq_disable(adapter);
4211 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4212
4213 if (!test_bit(__IGB_DOWN, &adapter->state))
4214 igb_irq_enable(adapter);
4215
4216 if ((adapter->hw.mng_cookie.status &
4217 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4218 (vid == adapter->mng_vlan_id)) {
4219 /* release control to f/w */
4220 igb_release_hw_control(adapter);
4221 return;
4222 }
4223
4224 /* remove VID from filter table */
4225 index = (vid >> 5) & 0x7F;
4226 vfta = array_rd32(E1000_VFTA, index);
4227 vfta &= ~(1 << (vid & 0x1F));
4228 igb_write_vfta(&adapter->hw, index, vfta);
4229}
4230
4231static void igb_restore_vlan(struct igb_adapter *adapter)
4232{
4233 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4234
4235 if (adapter->vlgrp) {
4236 u16 vid;
4237 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4238 if (!vlan_group_get_device(adapter->vlgrp, vid))
4239 continue;
4240 igb_vlan_rx_add_vid(adapter->netdev, vid);
4241 }
4242 }
4243}
4244
4245int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4246{
4247 struct e1000_mac_info *mac = &adapter->hw.mac;
4248
4249 mac->autoneg = 0;
4250
4251 /* Fiber NICs only allow 1000 gbps Full duplex */
4252 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4253 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4254 dev_err(&adapter->pdev->dev,
4255 "Unsupported Speed/Duplex configuration\n");
4256 return -EINVAL;
4257 }
4258
4259 switch (spddplx) {
4260 case SPEED_10 + DUPLEX_HALF:
4261 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4262 break;
4263 case SPEED_10 + DUPLEX_FULL:
4264 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4265 break;
4266 case SPEED_100 + DUPLEX_HALF:
4267 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4268 break;
4269 case SPEED_100 + DUPLEX_FULL:
4270 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4271 break;
4272 case SPEED_1000 + DUPLEX_FULL:
4273 mac->autoneg = 1;
4274 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4275 break;
4276 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4277 default:
4278 dev_err(&adapter->pdev->dev,
4279 "Unsupported Speed/Duplex configuration\n");
4280 return -EINVAL;
4281 }
4282 return 0;
4283}
4284
4285
4286static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4287{
4288 struct net_device *netdev = pci_get_drvdata(pdev);
4289 struct igb_adapter *adapter = netdev_priv(netdev);
4290 struct e1000_hw *hw = &adapter->hw;
2d064c06 4291 u32 ctrl, rctl, status;
9d5c8243
AK		 4292 u32 wufc = adapter->wol;
4293#ifdef CONFIG_PM
4294 int retval = 0;
4295#endif
4296
4297 netif_device_detach(netdev);
4298
a88f10ec
AD		 4299 if (netif_running(netdev))
4300 igb_close(netdev);
4301
4302 igb_reset_interrupt_capability(adapter);
4303
4304 igb_free_queues(adapter);
9d5c8243
AK		 4305
4306#ifdef CONFIG_PM
4307 retval = pci_save_state(pdev);
4308 if (retval)
4309 return retval;
4310#endif
4311
4312 status = rd32(E1000_STATUS);
4313 if (status & E1000_STATUS_LU)
4314 wufc &= ~E1000_WUFC_LNKC;
4315
4316 if (wufc) {
4317 igb_setup_rctl(adapter);
4318 igb_set_multi(netdev);
4319
4320 /* turn on all-multi mode if wake on multicast is enabled */
4321 if (wufc & E1000_WUFC_MC) {
4322 rctl = rd32(E1000_RCTL);
4323 rctl |= E1000_RCTL_MPE;
4324 wr32(E1000_RCTL, rctl);
4325 }
4326
4327 ctrl = rd32(E1000_CTRL);
4328 /* advertise wake from D3Cold */
4329 #define E1000_CTRL_ADVD3WUC 0x00100000
4330 /* phy power management enable */
4331 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4332 ctrl |= E1000_CTRL_ADVD3WUC;
4333 wr32(E1000_CTRL, ctrl);
4334
9d5c8243
AK		 4335 /* Allow time for pending master requests to run */
4336 igb_disable_pcie_master(&adapter->hw);
4337
4338 wr32(E1000_WUC, E1000_WUC_PME_EN);
4339 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4340 } else {
4341 wr32(E1000_WUC, 0);
4342 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4343 }
4344
2d064c06
AD		 4345 /* make sure adapter isn't asleep if manageability/wol is enabled */
4346 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4347 pci_enable_wake(pdev, PCI_D3hot, 1);
4348 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4349 } else {
4350 igb_shutdown_fiber_serdes_link_82575(hw);
4351 pci_enable_wake(pdev, PCI_D3hot, 0);
4352 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4353 }
4354
4355 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4356 * would have already happened in close and is redundant. */
4357 igb_release_hw_control(adapter);
4358
4359 pci_disable_device(pdev);
4360
4361 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4362
4363 return 0;
4364}
4365
4366#ifdef CONFIG_PM
4367static int igb_resume(struct pci_dev *pdev)
4368{
4369 struct net_device *netdev = pci_get_drvdata(pdev);
4370 struct igb_adapter *adapter = netdev_priv(netdev);
4371 struct e1000_hw *hw = &adapter->hw;
4372 u32 err;
4373
4374 pci_set_power_state(pdev, PCI_D0);
4375 pci_restore_state(pdev);
42bfd33a
TI		 4376
4377 if (adapter->need_ioport)
4378 err = pci_enable_device(pdev);
4379 else
4380 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4381 if (err) {
4382 dev_err(&pdev->dev,
4383 "igb: Cannot enable PCI device from suspend\n");
4384 return err;
4385 }
4386 pci_set_master(pdev);
4387
4388 pci_enable_wake(pdev, PCI_D3hot, 0);
4389 pci_enable_wake(pdev, PCI_D3cold, 0);
4390
a88f10ec
AD		 4391 igb_set_interrupt_capability(adapter);
4392
4393 if (igb_alloc_queues(adapter)) {
4394 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4395 return -ENOMEM;
9d5c8243
AK		 4396 }
4397
4398 /* e1000_power_up_phy(adapter); */
4399
4400 igb_reset(adapter);
4401 wr32(E1000_WUS, ~0);
4402
a88f10ec
AD		 4403 if (netif_running(netdev)) {
4404 err = igb_open(netdev);
4405 if (err)
4406 return err;
4407 }
9d5c8243
AK		 4408
4409 netif_device_attach(netdev);
4410
4411 /* let the f/w know that the h/w is now under the control of the
4412 * driver. */
4413 igb_get_hw_control(adapter);
4414
4415 return 0;
4416}
4417#endif
4418
4419static void igb_shutdown(struct pci_dev *pdev)
4420{
4421 igb_suspend(pdev, PMSG_SUSPEND);
4422}
4423
4424#ifdef CONFIG_NET_POLL_CONTROLLER
4425/*
4426 * Polling 'interrupt' - used by things like netconsole to send skbs
4427 * without having to re-enable interrupts. It's not called while
4428 * the interrupt routine is executing.
4429 */
4430static void igb_netpoll(struct net_device *netdev)
4431{
4432 struct igb_adapter *adapter = netdev_priv(netdev);
4433 int i;
4434 int work_done = 0;
4435
4436 igb_irq_disable(adapter);
7dfc16fa
AD		 4437 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4438
9d5c8243 4439 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4440 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4441
4442 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4443 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4444 &work_done,
4445 adapter->rx_ring[i].napi.weight);
4446
7dfc16fa 4447 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4448 igb_irq_enable(adapter);
4449}
4450#endif /* CONFIG_NET_POLL_CONTROLLER */
4451
4452/**
4453 * igb_io_error_detected - called when PCI error is detected
4454 * @pdev: Pointer to PCI device
4455 * @state: The current pci connection state
4456 *
4457 * This function is called after a PCI bus error affecting
4458 * this device has been detected.
4459 */
4460static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4461 pci_channel_state_t state)
4462{
4463 struct net_device *netdev = pci_get_drvdata(pdev);
4464 struct igb_adapter *adapter = netdev_priv(netdev);
4465
4466 netif_device_detach(netdev);
4467
4468 if (netif_running(netdev))
4469 igb_down(adapter);
4470 pci_disable_device(pdev);
4471
4472 /* Request a slot slot reset. */
4473 return PCI_ERS_RESULT_NEED_RESET;
4474}
4475
4476/**
4477 * igb_io_slot_reset - called after the pci bus has been reset.
4478 * @pdev: Pointer to PCI device
4479 *
4480 * Restart the card from scratch, as if from a cold-boot. Implementation
4481 * resembles the first-half of the igb_resume routine.
4482 */
4483static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4484{
4485 struct net_device *netdev = pci_get_drvdata(pdev);
4486 struct igb_adapter *adapter = netdev_priv(netdev);
4487 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4488 int err;
9d5c8243 4489
42bfd33a
TI		 4490 if (adapter->need_ioport)
4491 err = pci_enable_device(pdev);
4492 else
4493 err = pci_enable_device_mem(pdev);
4494 if (err) {
9d5c8243
AK		 4495 dev_err(&pdev->dev,
4496 "Cannot re-enable PCI device after reset.\n");
4497 return PCI_ERS_RESULT_DISCONNECT;
4498 }
4499 pci_set_master(pdev);
c682fc23 4500 pci_restore_state(pdev);
9d5c8243
AK		 4501
4502 pci_enable_wake(pdev, PCI_D3hot, 0);
4503 pci_enable_wake(pdev, PCI_D3cold, 0);
4504
4505 igb_reset(adapter);
4506 wr32(E1000_WUS, ~0);
4507
4508 return PCI_ERS_RESULT_RECOVERED;
4509}
4510
4511/**
4512 * igb_io_resume - called when traffic can start flowing again.
4513 * @pdev: Pointer to PCI device
4514 *
4515 * This callback is called when the error recovery driver tells us that
4516 * its OK to resume normal operation. Implementation resembles the
4517 * second-half of the igb_resume routine.
4518 */
4519static void igb_io_resume(struct pci_dev *pdev)
4520{
4521 struct net_device *netdev = pci_get_drvdata(pdev);
4522 struct igb_adapter *adapter = netdev_priv(netdev);
4523
4524 igb_init_manageability(adapter);
4525
4526 if (netif_running(netdev)) {
4527 if (igb_up(adapter)) {
4528 dev_err(&pdev->dev, "igb_up failed after reset\n");
4529 return;
4530 }
4531 }
4532
4533 netif_device_attach(netdev);
4534
4535 /* let the f/w know that the h/w is now under the control of the
4536 * driver. */
4537 igb_get_hw_control(adapter);
4538
4539}
4540
4541/* igb_main.c */
Clone of davem's net-next-2.6 tree