]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/igb/igb_main.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: remove unneeded bit refrence when enabling jumbo frames
[net-next-2.6.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
421e02f0 45#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 46#include <linux/dca.h>
47#endif
9d5c8243
AK		 48#include "igb.h"
49
0024fd00 50#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 51char igb_driver_name[] = "igb";
52char igb_driver_version[] = DRV_VERSION;
53static const char igb_driver_string[] =
54 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 55static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 56
9d5c8243
AK		 57static const struct e1000_info *igb_info_tbl[] = {
58 [board_82575] = &e1000_82575_info,
59};
60
61static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
68 /* required last entry */
69 {0, }
70};
71
72MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
73
74void igb_reset(struct igb_adapter *);
75static int igb_setup_all_tx_resources(struct igb_adapter *);
76static int igb_setup_all_rx_resources(struct igb_adapter *);
77static void igb_free_all_tx_resources(struct igb_adapter *);
78static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 79void igb_update_stats(struct igb_adapter *);
80static int igb_probe(struct pci_dev *, const struct pci_device_id *);
81static void __devexit igb_remove(struct pci_dev *pdev);
82static int igb_sw_init(struct igb_adapter *);
83static int igb_open(struct net_device *);
84static int igb_close(struct net_device *);
85static void igb_configure_tx(struct igb_adapter *);
86static void igb_configure_rx(struct igb_adapter *);
87static void igb_setup_rctl(struct igb_adapter *);
88static void igb_clean_all_tx_rings(struct igb_adapter *);
89static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 90static void igb_clean_tx_ring(struct igb_ring *);
91static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 92static void igb_set_multi(struct net_device *);
93static void igb_update_phy_info(unsigned long);
94static void igb_watchdog(unsigned long);
95static void igb_watchdog_task(struct work_struct *);
96static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
97 struct igb_ring *);
98static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
99static struct net_device_stats *igb_get_stats(struct net_device *);
100static int igb_change_mtu(struct net_device *, int);
101static int igb_set_mac(struct net_device *, void *);
102static irqreturn_t igb_intr(int irq, void *);
103static irqreturn_t igb_intr_msi(int irq, void *);
104static irqreturn_t igb_msix_other(int irq, void *);
105static irqreturn_t igb_msix_rx(int irq, void *);
106static irqreturn_t igb_msix_tx(int irq, void *);
107static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 108#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 109static void igb_update_rx_dca(struct igb_ring *);
110static void igb_update_tx_dca(struct igb_ring *);
111static void igb_setup_dca(struct igb_adapter *);
421e02f0 112#endif /* CONFIG_IGB_DCA */
3b644cf6 113static bool igb_clean_tx_irq(struct igb_ring *);
661086df 114static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 115static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
116static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
d3352520
AD		 117#ifdef CONFIG_IGB_LRO
118static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
119#endif
9d5c8243
AK		 120static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
121static void igb_tx_timeout(struct net_device *);
122static void igb_reset_task(struct work_struct *);
123static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
124static void igb_vlan_rx_add_vid(struct net_device *, u16);
125static void igb_vlan_rx_kill_vid(struct net_device *, u16);
126static void igb_restore_vlan(struct igb_adapter *);
127
128static int igb_suspend(struct pci_dev *, pm_message_t);
129#ifdef CONFIG_PM
130static int igb_resume(struct pci_dev *);
131#endif
132static void igb_shutdown(struct pci_dev *);
421e02f0 133#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 134static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
135static struct notifier_block dca_notifier = {
136 .notifier_call = igb_notify_dca,
137 .next = NULL,
138 .priority = 0
139};
140#endif
9d5c8243
AK		 141
142#ifdef CONFIG_NET_POLL_CONTROLLER
143/* for netdump / net console */
144static void igb_netpoll(struct net_device *);
145#endif
146
147static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
148 pci_channel_state_t);
149static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
150static void igb_io_resume(struct pci_dev *);
151
152static struct pci_error_handlers igb_err_handler = {
153 .error_detected = igb_io_error_detected,
154 .slot_reset = igb_io_slot_reset,
155 .resume = igb_io_resume,
156};
157
158
159static struct pci_driver igb_driver = {
160 .name = igb_driver_name,
161 .id_table = igb_pci_tbl,
162 .probe = igb_probe,
163 .remove = __devexit_p(igb_remove),
164#ifdef CONFIG_PM
165 /* Power Managment Hooks */
166 .suspend = igb_suspend,
167 .resume = igb_resume,
168#endif
169 .shutdown = igb_shutdown,
170 .err_handler = &igb_err_handler
171};
172
7dfc16fa
AD		 173static int global_quad_port_a; /* global quad port a indication */
174
9d5c8243
AK		 175MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
176MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
177MODULE_LICENSE("GPL");
178MODULE_VERSION(DRV_VERSION);
179
180#ifdef DEBUG
181/**
182 * igb_get_hw_dev_name - return device name string
183 * used by hardware layer to print debugging information
184 **/
185char *igb_get_hw_dev_name(struct e1000_hw *hw)
186{
187 struct igb_adapter *adapter = hw->back;
188 return adapter->netdev->name;
189}
190#endif
191
192/**
193 * igb_init_module - Driver Registration Routine
194 *
195 * igb_init_module is the first routine called when the driver is
196 * loaded. All it does is register with the PCI subsystem.
197 **/
198static int __init igb_init_module(void)
199{
200 int ret;
201 printk(KERN_INFO "%s - version %s\n",
202 igb_driver_string, igb_driver_version);
203
204 printk(KERN_INFO "%s\n", igb_copyright);
205
7dfc16fa
AD		 206 global_quad_port_a = 0;
207
9d5c8243 208 ret = pci_register_driver(&igb_driver);
421e02f0 209#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 210 dca_register_notify(&dca_notifier);
211#endif
9d5c8243
AK		 212 return ret;
213}
214
215module_init(igb_init_module);
216
217/**
218 * igb_exit_module - Driver Exit Cleanup Routine
219 *
220 * igb_exit_module is called just before the driver is removed
221 * from memory.
222 **/
223static void __exit igb_exit_module(void)
224{
421e02f0 225#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 226 dca_unregister_notify(&dca_notifier);
227#endif
9d5c8243
AK		 228 pci_unregister_driver(&igb_driver);
229}
230
231module_exit(igb_exit_module);
232
233/**
234 * igb_alloc_queues - Allocate memory for all rings
235 * @adapter: board private structure to initialize
236 *
237 * We allocate one ring per queue at run-time since we don't know the
238 * number of queues at compile-time.
239 **/
240static int igb_alloc_queues(struct igb_adapter *adapter)
241{
242 int i;
243
244 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
245 sizeof(struct igb_ring), GFP_KERNEL);
246 if (!adapter->tx_ring)
247 return -ENOMEM;
248
249 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
250 sizeof(struct igb_ring), GFP_KERNEL);
251 if (!adapter->rx_ring) {
252 kfree(adapter->tx_ring);
253 return -ENOMEM;
254 }
255
6eb5a7f1
AD		 256 adapter->rx_ring->buddy = adapter->tx_ring;
257
661086df
PWJ		 258 for (i = 0; i < adapter->num_tx_queues; i++) {
259 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 260 ring->count = adapter->tx_ring_count;
661086df
PWJ		 261 ring->adapter = adapter;
262 ring->queue_index = i;
263 }
9d5c8243
AK		 264 for (i = 0; i < adapter->num_rx_queues; i++) {
265 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 266 ring->count = adapter->rx_ring_count;
9d5c8243 267 ring->adapter = adapter;
844290e5 268 ring->queue_index = i;
9d5c8243
AK		 269 ring->itr_register = E1000_ITR;
270
844290e5 271 /* set a default napi handler for each rx_ring */
661086df 272 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 273 }
274 return 0;
275}
276
a88f10ec
AD		 277static void igb_free_queues(struct igb_adapter *adapter)
278{
279 int i;
280
281 for (i = 0; i < adapter->num_rx_queues; i++)
282 netif_napi_del(&adapter->rx_ring[i].napi);
283
284 kfree(adapter->tx_ring);
285 kfree(adapter->rx_ring);
286}
287
9d5c8243
AK		 288#define IGB_N0_QUEUE -1
289static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
290 int tx_queue, int msix_vector)
291{
292 u32 msixbm = 0;
293 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 294 u32 ivar, index;
295
296 switch (hw->mac.type) {
297 case e1000_82575:
9d5c8243
AK		 298 /* The 82575 assigns vectors using a bitmask, which matches the
299 bitmask for the EICR/EIMS/EIMC registers. To assign one
300 or more queues to a vector, we write the appropriate bits
301 into the MSIXBM register for that vector. */
302 if (rx_queue > IGB_N0_QUEUE) {
303 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
304 adapter->rx_ring[rx_queue].eims_value = msixbm;
305 }
306 if (tx_queue > IGB_N0_QUEUE) {
307 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
308 adapter->tx_ring[tx_queue].eims_value =
309 E1000_EICR_TX_QUEUE0 << tx_queue;
310 }
311 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 312 break;
313 case e1000_82576:
106ef2fe 314 /* The 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 315 Each queue has a single entry in the table to which we write
316 a vector number along with a "valid" bit. Sadly, the layout
317 of the table is somewhat counterintuitive. */
318 if (rx_queue > IGB_N0_QUEUE) {
319 index = (rx_queue & 0x7);
320 ivar = array_rd32(E1000_IVAR0, index);
321 if (rx_queue < 8) {
322 /* vector goes into low byte of register */
323 ivar = ivar & 0xFFFFFF00;
324 ivar |= msix_vector | E1000_IVAR_VALID;
325 } else {
326 /* vector goes into third byte of register */
327 ivar = ivar & 0xFF00FFFF;
328 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
329 }
330 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
331 array_wr32(E1000_IVAR0, index, ivar);
332 }
333 if (tx_queue > IGB_N0_QUEUE) {
334 index = (tx_queue & 0x7);
335 ivar = array_rd32(E1000_IVAR0, index);
336 if (tx_queue < 8) {
337 /* vector goes into second byte of register */
338 ivar = ivar & 0xFFFF00FF;
339 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
340 } else {
341 /* vector goes into high byte of register */
342 ivar = ivar & 0x00FFFFFF;
343 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
344 }
345 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
346 array_wr32(E1000_IVAR0, index, ivar);
347 }
348 break;
349 default:
350 BUG();
351 break;
352 }
9d5c8243
AK		 353}
354
355/**
356 * igb_configure_msix - Configure MSI-X hardware
357 *
358 * igb_configure_msix sets up the hardware to properly
359 * generate MSI-X interrupts.
360 **/
361static void igb_configure_msix(struct igb_adapter *adapter)
362{
363 u32 tmp;
364 int i, vector = 0;
365 struct e1000_hw *hw = &adapter->hw;
366
367 adapter->eims_enable_mask = 0;
2d064c06
AD		 368 if (hw->mac.type == e1000_82576)
369 /* Turn on MSI-X capability first, or our settings
370 * won't stick. And it will take days to debug. */
371 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
372 E1000_GPIE_PBA | E1000_GPIE_EIAME |
373 E1000_GPIE_NSICR);
9d5c8243
AK		 374
375 for (i = 0; i < adapter->num_tx_queues; i++) {
376 struct igb_ring *tx_ring = &adapter->tx_ring[i];
377 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
378 adapter->eims_enable_mask |= tx_ring->eims_value;
379 if (tx_ring->itr_val)
6eb5a7f1 380 writel(tx_ring->itr_val,
9d5c8243
AK		 381 hw->hw_addr + tx_ring->itr_register);
382 else
383 writel(1, hw->hw_addr + tx_ring->itr_register);
384 }
385
386 for (i = 0; i < adapter->num_rx_queues; i++) {
387 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 388 rx_ring->buddy = NULL;
9d5c8243
AK		 389 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
390 adapter->eims_enable_mask |= rx_ring->eims_value;
391 if (rx_ring->itr_val)
6eb5a7f1 392 writel(rx_ring->itr_val,
9d5c8243
AK		 393 hw->hw_addr + rx_ring->itr_register);
394 else
395 writel(1, hw->hw_addr + rx_ring->itr_register);
396 }
397
398
399 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 400 switch (hw->mac.type) {
401 case e1000_82575:
9d5c8243
AK		 402 array_wr32(E1000_MSIXBM(0), vector++,
403 E1000_EIMS_OTHER);
404
9d5c8243
AK		 405 tmp = rd32(E1000_CTRL_EXT);
406 /* enable MSI-X PBA support*/
407 tmp |= E1000_CTRL_EXT_PBA_CLR;
408
409 /* Auto-Mask interrupts upon ICR read. */
410 tmp |= E1000_CTRL_EXT_EIAME;
411 tmp |= E1000_CTRL_EXT_IRCA;
412
413 wr32(E1000_CTRL_EXT, tmp);
414 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 415 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 416
2d064c06
AD		 417 break;
418
419 case e1000_82576:
420 tmp = (vector++ | E1000_IVAR_VALID) << 8;
421 wr32(E1000_IVAR_MISC, tmp);
422
423 adapter->eims_enable_mask = (1 << (vector)) - 1;
424 adapter->eims_other = 1 << (vector - 1);
425 break;
426 default:
427 /* do nothing, since nothing else supports MSI-X */
428 break;
429 } /* switch (hw->mac.type) */
9d5c8243
AK		 430 wrfl();
431}
432
433/**
434 * igb_request_msix - Initialize MSI-X interrupts
435 *
436 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
437 * kernel.
438 **/
439static int igb_request_msix(struct igb_adapter *adapter)
440{
441 struct net_device *netdev = adapter->netdev;
442 int i, err = 0, vector = 0;
443
444 vector = 0;
445
446 for (i = 0; i < adapter->num_tx_queues; i++) {
447 struct igb_ring *ring = &(adapter->tx_ring[i]);
448 sprintf(ring->name, "%s-tx%d", netdev->name, i);
449 err = request_irq(adapter->msix_entries[vector].vector,
450 &igb_msix_tx, 0, ring->name,
451 &(adapter->tx_ring[i]));
452 if (err)
453 goto out;
454 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 455 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 456 vector++;
457 }
458 for (i = 0; i < adapter->num_rx_queues; i++) {
459 struct igb_ring *ring = &(adapter->rx_ring[i]);
460 if (strlen(netdev->name) < (IFNAMSIZ - 5))
461 sprintf(ring->name, "%s-rx%d", netdev->name, i);
462 else
463 memcpy(ring->name, netdev->name, IFNAMSIZ);
464 err = request_irq(adapter->msix_entries[vector].vector,
465 &igb_msix_rx, 0, ring->name,
466 &(adapter->rx_ring[i]));
467 if (err)
468 goto out;
469 ring->itr_register = E1000_EITR(0) + (vector << 2);
470 ring->itr_val = adapter->itr;
844290e5
PW		 471 /* overwrite the poll routine for MSIX, we've already done
472 * netif_napi_add */
473 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 474 vector++;
475 }
476
477 err = request_irq(adapter->msix_entries[vector].vector,
478 &igb_msix_other, 0, netdev->name, netdev);
479 if (err)
480 goto out;
481
9d5c8243
AK		 482 igb_configure_msix(adapter);
483 return 0;
484out:
485 return err;
486}
487
488static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
489{
490 if (adapter->msix_entries) {
491 pci_disable_msix(adapter->pdev);
492 kfree(adapter->msix_entries);
493 adapter->msix_entries = NULL;
7dfc16fa 494 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 495 pci_disable_msi(adapter->pdev);
496 return;
497}
498
499
500/**
501 * igb_set_interrupt_capability - set MSI or MSI-X if supported
502 *
503 * Attempt to configure interrupts using the best available
504 * capabilities of the hardware and kernel.
505 **/
506static void igb_set_interrupt_capability(struct igb_adapter *adapter)
507{
508 int err;
509 int numvecs, i;
510
511 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
512 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
513 GFP_KERNEL);
514 if (!adapter->msix_entries)
515 goto msi_only;
516
517 for (i = 0; i < numvecs; i++)
518 adapter->msix_entries[i].entry = i;
519
520 err = pci_enable_msix(adapter->pdev,
521 adapter->msix_entries,
522 numvecs);
523 if (err == 0)
34a20e89 524 goto out;
9d5c8243
AK		 525
526 igb_reset_interrupt_capability(adapter);
527
528 /* If we can't do MSI-X, try MSI */
529msi_only:
530 adapter->num_rx_queues = 1;
661086df 531 adapter->num_tx_queues = 1;
9d5c8243 532 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 533 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 534out:
661086df 535 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 536 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 537 return;
538}
539
540/**
541 * igb_request_irq - initialize interrupts
542 *
543 * Attempts to configure interrupts using the best available
544 * capabilities of the hardware and kernel.
545 **/
546static int igb_request_irq(struct igb_adapter *adapter)
547{
548 struct net_device *netdev = adapter->netdev;
549 struct e1000_hw *hw = &adapter->hw;
550 int err = 0;
551
552 if (adapter->msix_entries) {
553 err = igb_request_msix(adapter);
844290e5 554 if (!err)
9d5c8243 555 goto request_done;
9d5c8243
AK		 556 /* fall back to MSI */
557 igb_reset_interrupt_capability(adapter);
558 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 559 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 560 igb_free_all_tx_resources(adapter);
561 igb_free_all_rx_resources(adapter);
562 adapter->num_rx_queues = 1;
563 igb_alloc_queues(adapter);
844290e5 564 } else {
2d064c06
AD		 565 switch (hw->mac.type) {
566 case e1000_82575:
567 wr32(E1000_MSIXBM(0),
568 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
569 break;
570 case e1000_82576:
571 wr32(E1000_IVAR0, E1000_IVAR_VALID);
572 break;
573 default:
574 break;
575 }
9d5c8243 576 }
844290e5 577
7dfc16fa 578 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 579 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
580 netdev->name, netdev);
581 if (!err)
582 goto request_done;
583 /* fall back to legacy interrupts */
584 igb_reset_interrupt_capability(adapter);
7dfc16fa 585 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 586 }
587
588 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
589 netdev->name, netdev);
590
6cb5e577 591 if (err)
9d5c8243
AK		 592 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
593 err);
9d5c8243
AK		 594
595request_done:
596 return err;
597}
598
599static void igb_free_irq(struct igb_adapter *adapter)
600{
601 struct net_device *netdev = adapter->netdev;
602
603 if (adapter->msix_entries) {
604 int vector = 0, i;
605
606 for (i = 0; i < adapter->num_tx_queues; i++)
607 free_irq(adapter->msix_entries[vector++].vector,
608 &(adapter->tx_ring[i]));
609 for (i = 0; i < adapter->num_rx_queues; i++)
610 free_irq(adapter->msix_entries[vector++].vector,
611 &(adapter->rx_ring[i]));
612
613 free_irq(adapter->msix_entries[vector++].vector, netdev);
614 return;
615 }
616
617 free_irq(adapter->pdev->irq, netdev);
618}
619
620/**
621 * igb_irq_disable - Mask off interrupt generation on the NIC
622 * @adapter: board private structure
623 **/
624static void igb_irq_disable(struct igb_adapter *adapter)
625{
626 struct e1000_hw *hw = &adapter->hw;
627
628 if (adapter->msix_entries) {
844290e5 629 wr32(E1000_EIAM, 0);
9d5c8243
AK		 630 wr32(E1000_EIMC, ~0);
631 wr32(E1000_EIAC, 0);
632 }
844290e5
PW		 633
634 wr32(E1000_IAM, 0);
9d5c8243
AK		 635 wr32(E1000_IMC, ~0);
636 wrfl();
637 synchronize_irq(adapter->pdev->irq);
638}
639
640/**
641 * igb_irq_enable - Enable default interrupt generation settings
642 * @adapter: board private structure
643 **/
644static void igb_irq_enable(struct igb_adapter *adapter)
645{
646 struct e1000_hw *hw = &adapter->hw;
647
648 if (adapter->msix_entries) {
844290e5
PW		 649 wr32(E1000_EIAC, adapter->eims_enable_mask);
650 wr32(E1000_EIAM, adapter->eims_enable_mask);
651 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 652 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 653 } else {
654 wr32(E1000_IMS, IMS_ENABLE_MASK);
655 wr32(E1000_IAM, IMS_ENABLE_MASK);
656 }
9d5c8243
AK		 657}
658
659static void igb_update_mng_vlan(struct igb_adapter *adapter)
660{
661 struct net_device *netdev = adapter->netdev;
662 u16 vid = adapter->hw.mng_cookie.vlan_id;
663 u16 old_vid = adapter->mng_vlan_id;
664 if (adapter->vlgrp) {
665 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
666 if (adapter->hw.mng_cookie.status &
667 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
668 igb_vlan_rx_add_vid(netdev, vid);
669 adapter->mng_vlan_id = vid;
670 } else
671 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
672
673 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
674 (vid != old_vid) &&
675 !vlan_group_get_device(adapter->vlgrp, old_vid))
676 igb_vlan_rx_kill_vid(netdev, old_vid);
677 } else
678 adapter->mng_vlan_id = vid;
679 }
680}
681
682/**
683 * igb_release_hw_control - release control of the h/w to f/w
684 * @adapter: address of board private structure
685 *
686 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
687 * For ASF and Pass Through versions of f/w this means that the
688 * driver is no longer loaded.
689 *
690 **/
691static void igb_release_hw_control(struct igb_adapter *adapter)
692{
693 struct e1000_hw *hw = &adapter->hw;
694 u32 ctrl_ext;
695
696 /* Let firmware take over control of h/w */
697 ctrl_ext = rd32(E1000_CTRL_EXT);
698 wr32(E1000_CTRL_EXT,
699 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
700}
701
702
703/**
704 * igb_get_hw_control - get control of the h/w from f/w
705 * @adapter: address of board private structure
706 *
707 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
708 * For ASF and Pass Through versions of f/w this means that
709 * the driver is loaded.
710 *
711 **/
712static void igb_get_hw_control(struct igb_adapter *adapter)
713{
714 struct e1000_hw *hw = &adapter->hw;
715 u32 ctrl_ext;
716
717 /* Let firmware know the driver has taken over */
718 ctrl_ext = rd32(E1000_CTRL_EXT);
719 wr32(E1000_CTRL_EXT,
720 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
721}
722
9d5c8243
AK		 723/**
724 * igb_configure - configure the hardware for RX and TX
725 * @adapter: private board structure
726 **/
727static void igb_configure(struct igb_adapter *adapter)
728{
729 struct net_device *netdev = adapter->netdev;
730 int i;
731
732 igb_get_hw_control(adapter);
733 igb_set_multi(netdev);
734
735 igb_restore_vlan(adapter);
9d5c8243
AK		 736
737 igb_configure_tx(adapter);
738 igb_setup_rctl(adapter);
739 igb_configure_rx(adapter);
662d7205
AD		 740
741 igb_rx_fifo_flush_82575(&adapter->hw);
742
9d5c8243
AK		 743 /* call IGB_DESC_UNUSED which always leaves
744 * at least 1 descriptor unused to make sure
745 * next_to_use != next_to_clean */
746 for (i = 0; i < adapter->num_rx_queues; i++) {
747 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 748 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 749 }
750
751
752 adapter->tx_queue_len = netdev->tx_queue_len;
753}
754
755
756/**
757 * igb_up - Open the interface and prepare it to handle traffic
758 * @adapter: board private structure
759 **/
760
761int igb_up(struct igb_adapter *adapter)
762{
763 struct e1000_hw *hw = &adapter->hw;
764 int i;
765
766 /* hardware has been reset, we need to reload some things */
767 igb_configure(adapter);
768
769 clear_bit(__IGB_DOWN, &adapter->state);
770
844290e5
PW		 771 for (i = 0; i < adapter->num_rx_queues; i++)
772 napi_enable(&adapter->rx_ring[i].napi);
773 if (adapter->msix_entries)
9d5c8243 774 igb_configure_msix(adapter);
9d5c8243
AK		 775
776 /* Clear any pending interrupts. */
777 rd32(E1000_ICR);
778 igb_irq_enable(adapter);
779
780 /* Fire a link change interrupt to start the watchdog. */
781 wr32(E1000_ICS, E1000_ICS_LSC);
782 return 0;
783}
784
785void igb_down(struct igb_adapter *adapter)
786{
787 struct e1000_hw *hw = &adapter->hw;
788 struct net_device *netdev = adapter->netdev;
789 u32 tctl, rctl;
790 int i;
791
792 /* signal that we're down so the interrupt handler does not
793 * reschedule our watchdog timer */
794 set_bit(__IGB_DOWN, &adapter->state);
795
796 /* disable receives in the hardware */
797 rctl = rd32(E1000_RCTL);
798 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
799 /* flush and sleep below */
800
fd2ea0a7 801 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 802
803 /* disable transmits in the hardware */
804 tctl = rd32(E1000_TCTL);
805 tctl &= ~E1000_TCTL_EN;
806 wr32(E1000_TCTL, tctl);
807 /* flush both disables and wait for them to finish */
808 wrfl();
809 msleep(10);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 813
9d5c8243
AK		 814 igb_irq_disable(adapter);
815
816 del_timer_sync(&adapter->watchdog_timer);
817 del_timer_sync(&adapter->phy_info_timer);
818
819 netdev->tx_queue_len = adapter->tx_queue_len;
820 netif_carrier_off(netdev);
821 adapter->link_speed = 0;
822 adapter->link_duplex = 0;
823
3023682e
JK		 824 if (!pci_channel_offline(adapter->pdev))
825 igb_reset(adapter);
9d5c8243
AK		 826 igb_clean_all_tx_rings(adapter);
827 igb_clean_all_rx_rings(adapter);
828}
829
830void igb_reinit_locked(struct igb_adapter *adapter)
831{
832 WARN_ON(in_interrupt());
833 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
834 msleep(1);
835 igb_down(adapter);
836 igb_up(adapter);
837 clear_bit(__IGB_RESETTING, &adapter->state);
838}
839
840void igb_reset(struct igb_adapter *adapter)
841{
842 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 843 struct e1000_mac_info *mac = &hw->mac;
844 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 845 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
846 u16 hwm;
847
848 /* Repartition Pba for greater than 9k mtu
849 * To take effect CTRL.RST is required.
850 */
2d064c06 851 if (mac->type != e1000_82576) {
9d5c8243 852 pba = E1000_PBA_34K;
2d064c06
AD		 853 }
854 else {
855 pba = E1000_PBA_64K;
856 }
9d5c8243 857
2d064c06
AD		 858 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
859 (mac->type < e1000_82576)) {
9d5c8243
AK		 860 /* adjust PBA for jumbo frames */
861 wr32(E1000_PBA, pba);
862
863 /* To maintain wire speed transmits, the Tx FIFO should be
864 * large enough to accommodate two full transmit packets,
865 * rounded up to the next 1KB and expressed in KB. Likewise,
866 * the Rx FIFO should be large enough to accommodate at least
867 * one full receive packet and is similarly rounded up and
868 * expressed in KB. */
869 pba = rd32(E1000_PBA);
870 /* upper 16 bits has Tx packet buffer allocation size in KB */
871 tx_space = pba >> 16;
872 /* lower 16 bits has Rx packet buffer allocation size in KB */
873 pba &= 0xffff;
874 /* the tx fifo also stores 16 bytes of information about the tx
875 * but don't include ethernet FCS because hardware appends it */
876 min_tx_space = (adapter->max_frame_size +
877 sizeof(struct e1000_tx_desc) -
878 ETH_FCS_LEN) * 2;
879 min_tx_space = ALIGN(min_tx_space, 1024);
880 min_tx_space >>= 10;
881 /* software strips receive CRC, so leave room for it */
882 min_rx_space = adapter->max_frame_size;
883 min_rx_space = ALIGN(min_rx_space, 1024);
884 min_rx_space >>= 10;
885
886 /* If current Tx allocation is less than the min Tx FIFO size,
887 * and the min Tx FIFO size is less than the current Rx FIFO
888 * allocation, take space away from current Rx allocation */
889 if (tx_space < min_tx_space &&
890 ((min_tx_space - tx_space) < pba)) {
891 pba = pba - (min_tx_space - tx_space);
892
893 /* if short on rx space, rx wins and must trump tx
894 * adjustment */
895 if (pba < min_rx_space)
896 pba = min_rx_space;
897 }
2d064c06 898 wr32(E1000_PBA, pba);
9d5c8243 899 }
9d5c8243
AK		 900
901 /* flow control settings */
902 /* The high water mark must be low enough to fit one full frame
903 * (or the size used for early receive) above it in the Rx FIFO.
904 * Set it to the lower of:
905 * - 90% of the Rx FIFO size, or
906 * - the full Rx FIFO size minus one full frame */
907 hwm = min(((pba << 10) * 9 / 10),
2d064c06 908 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 909
2d064c06
AD		 910 if (mac->type < e1000_82576) {
911 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
912 fc->low_water = fc->high_water - 8;
913 } else {
914 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
915 fc->low_water = fc->high_water - 16;
916 }
9d5c8243
AK		 917 fc->pause_time = 0xFFFF;
918 fc->send_xon = 1;
919 fc->type = fc->original_type;
920
921 /* Allow time for pending master requests to run */
922 adapter->hw.mac.ops.reset_hw(&adapter->hw);
923 wr32(E1000_WUC, 0);
924
925 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
926 dev_err(&adapter->pdev->dev, "Hardware Error\n");
927
928 igb_update_mng_vlan(adapter);
929
930 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
931 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
932
933 igb_reset_adaptive(&adapter->hw);
f5f4cf08 934 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 935}
936
42bfd33a
TI		 937/**
938 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
939 * @pdev: PCI device information struct
940 *
941 * Returns true if an adapter needs ioport resources
942 **/
943static int igb_is_need_ioport(struct pci_dev *pdev)
944{
945 switch (pdev->device) {
946 /* Currently there are no adapters that need ioport resources */
947 default:
948 return false;
949 }
950}
951
2e5c6922
SH		 952static const struct net_device_ops igb_netdev_ops = {
953 .ndo_open = igb_open,
954 .ndo_stop = igb_close,
00829823 955 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 956 .ndo_get_stats = igb_get_stats,
957 .ndo_set_multicast_list = igb_set_multi,
958 .ndo_set_mac_address = igb_set_mac,
959 .ndo_change_mtu = igb_change_mtu,
960 .ndo_do_ioctl = igb_ioctl,
961 .ndo_tx_timeout = igb_tx_timeout,
962 .ndo_validate_addr = eth_validate_addr,
963 .ndo_vlan_rx_register = igb_vlan_rx_register,
964 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
965 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
966#ifdef CONFIG_NET_POLL_CONTROLLER
967 .ndo_poll_controller = igb_netpoll,
968#endif
969};
970
9d5c8243
AK		 971/**
972 * igb_probe - Device Initialization Routine
973 * @pdev: PCI device information struct
974 * @ent: entry in igb_pci_tbl
975 *
976 * Returns 0 on success, negative on failure
977 *
978 * igb_probe initializes an adapter identified by a pci_dev structure.
979 * The OS initialization, configuring of the adapter private structure,
980 * and a hardware reset occur.
981 **/
982static int __devinit igb_probe(struct pci_dev *pdev,
983 const struct pci_device_id *ent)
984{
985 struct net_device *netdev;
986 struct igb_adapter *adapter;
987 struct e1000_hw *hw;
c54106bb 988 struct pci_dev *us_dev;
9d5c8243
AK		 989 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
990 unsigned long mmio_start, mmio_len;
c54106bb
AD		 991 int i, err, pci_using_dac, pos;
992 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 993 u16 eeprom_apme_mask = IGB_EEPROM_APME;
994 u32 part_num;
42bfd33a 995 int bars, need_ioport;
9d5c8243 996
42bfd33a
TI		 997 /* do not allocate ioport bars when not needed */
998 need_ioport = igb_is_need_ioport(pdev);
999 if (need_ioport) {
1000 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1001 err = pci_enable_device(pdev);
1002 } else {
1003 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1004 err = pci_enable_device_mem(pdev);
1005 }
9d5c8243
AK		 1006 if (err)
1007 return err;
1008
1009 pci_using_dac = 0;
1010 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1011 if (!err) {
1012 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1013 if (!err)
1014 pci_using_dac = 1;
1015 } else {
1016 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1017 if (err) {
1018 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1019 if (err) {
1020 dev_err(&pdev->dev, "No usable DMA "
1021 "configuration, aborting\n");
1022 goto err_dma;
1023 }
1024 }
1025 }
1026
c54106bb
AD		 1027 /* 82575 requires that the pci-e link partner disable the L0s state */
1028 switch (pdev->device) {
1029 case E1000_DEV_ID_82575EB_COPPER:
1030 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1031 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1032 us_dev = pdev->bus->self;
1033 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1034 if (pos) {
1035 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1036 &state);
1037 state &= ~PCIE_LINK_STATE_L0S;
1038 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1039 state);
ac450208
BH		 1040 dev_info(&pdev->dev,
1041 "Disabling ASPM L0s upstream switch port %s\n",
1042 pci_name(us_dev));
c54106bb
AD		 1043 }
1044 default:
1045 break;
1046 }
1047
42bfd33a 1048 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1049 if (err)
1050 goto err_pci_reg;
1051
1052 pci_set_master(pdev);
c682fc23 1053 pci_save_state(pdev);
9d5c8243
AK		 1054
1055 err = -ENOMEM;
661086df 1056 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1057 if (!netdev)
1058 goto err_alloc_etherdev;
1059
1060 SET_NETDEV_DEV(netdev, &pdev->dev);
1061
1062 pci_set_drvdata(pdev, netdev);
1063 adapter = netdev_priv(netdev);
1064 adapter->netdev = netdev;
1065 adapter->pdev = pdev;
1066 hw = &adapter->hw;
1067 hw->back = adapter;
1068 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1069 adapter->bars = bars;
1070 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1071
1072 mmio_start = pci_resource_start(pdev, 0);
1073 mmio_len = pci_resource_len(pdev, 0);
1074
1075 err = -EIO;
1076 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1077 if (!adapter->hw.hw_addr)
1078 goto err_ioremap;
1079
2e5c6922 1080 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1081 igb_set_ethtool_ops(netdev);
9d5c8243 1082 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1083
1084 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1085
1086 netdev->mem_start = mmio_start;
1087 netdev->mem_end = mmio_start + mmio_len;
1088
9d5c8243
AK		 1089 /* PCI config space info */
1090 hw->vendor_id = pdev->vendor;
1091 hw->device_id = pdev->device;
1092 hw->revision_id = pdev->revision;
1093 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1094 hw->subsystem_device_id = pdev->subsystem_device;
1095
1096 /* setup the private structure */
1097 hw->back = adapter;
1098 /* Copy the default MAC, PHY and NVM function pointers */
1099 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1100 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1101 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1102 /* Initialize skew-specific constants */
1103 err = ei->get_invariants(hw);
1104 if (err)
1105 goto err_hw_init;
1106
1107 err = igb_sw_init(adapter);
1108 if (err)
1109 goto err_sw_init;
1110
1111 igb_get_bus_info_pcie(hw);
1112
7dfc16fa
AD		 1113 /* set flags */
1114 switch (hw->mac.type) {
1115 case e1000_82576:
1116 case e1000_82575:
1117 adapter->flags |= IGB_FLAG_HAS_DCA;
1118 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1119 break;
1120 default:
1121 break;
1122 }
1123
9d5c8243
AK		 1124 hw->phy.autoneg_wait_to_complete = false;
1125 hw->mac.adaptive_ifs = true;
1126
1127 /* Copper options */
1128 if (hw->phy.media_type == e1000_media_type_copper) {
1129 hw->phy.mdix = AUTO_ALL_MODES;
1130 hw->phy.disable_polarity_correction = false;
1131 hw->phy.ms_type = e1000_ms_hw_default;
1132 }
1133
1134 if (igb_check_reset_block(hw))
1135 dev_info(&pdev->dev,
1136 "PHY reset is blocked due to SOL/IDER session.\n");
1137
1138 netdev->features = NETIF_F_SG |
1139 NETIF_F_HW_CSUM |
1140 NETIF_F_HW_VLAN_TX |
1141 NETIF_F_HW_VLAN_RX |
1142 NETIF_F_HW_VLAN_FILTER;
1143
1144 netdev->features |= NETIF_F_TSO;
9d5c8243 1145 netdev->features |= NETIF_F_TSO6;
48f29ffc 1146
d3352520
AD		 1147#ifdef CONFIG_IGB_LRO
1148 netdev->features |= NETIF_F_LRO;
1149#endif
1150
48f29ffc
JK		 1151 netdev->vlan_features |= NETIF_F_TSO;
1152 netdev->vlan_features |= NETIF_F_TSO6;
1153 netdev->vlan_features |= NETIF_F_HW_CSUM;
1154 netdev->vlan_features |= NETIF_F_SG;
1155
9d5c8243
AK		 1156 if (pci_using_dac)
1157 netdev->features |= NETIF_F_HIGHDMA;
1158
1159 netdev->features |= NETIF_F_LLTX;
1160 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1161
1162 /* before reading the NVM, reset the controller to put the device in a
1163 * known good starting state */
1164 hw->mac.ops.reset_hw(hw);
1165
1166 /* make sure the NVM is good */
1167 if (igb_validate_nvm_checksum(hw) < 0) {
1168 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1169 err = -EIO;
1170 goto err_eeprom;
1171 }
1172
1173 /* copy the MAC address out of the NVM */
1174 if (hw->mac.ops.read_mac_addr(hw))
1175 dev_err(&pdev->dev, "NVM Read Error\n");
1176
1177 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1178 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1179
1180 if (!is_valid_ether_addr(netdev->perm_addr)) {
1181 dev_err(&pdev->dev, "Invalid MAC Address\n");
1182 err = -EIO;
1183 goto err_eeprom;
1184 }
1185
1186 init_timer(&adapter->watchdog_timer);
1187 adapter->watchdog_timer.function = &igb_watchdog;
1188 adapter->watchdog_timer.data = (unsigned long) adapter;
1189
1190 init_timer(&adapter->phy_info_timer);
1191 adapter->phy_info_timer.function = &igb_update_phy_info;
1192 adapter->phy_info_timer.data = (unsigned long) adapter;
1193
1194 INIT_WORK(&adapter->reset_task, igb_reset_task);
1195 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1196
1197 /* Initialize link & ring properties that are user-changeable */
1198 adapter->tx_ring->count = 256;
1199 for (i = 0; i < adapter->num_tx_queues; i++)
1200 adapter->tx_ring[i].count = adapter->tx_ring->count;
1201 adapter->rx_ring->count = 256;
1202 for (i = 0; i < adapter->num_rx_queues; i++)
1203 adapter->rx_ring[i].count = adapter->rx_ring->count;
1204
1205 adapter->fc_autoneg = true;
1206 hw->mac.autoneg = true;
1207 hw->phy.autoneg_advertised = 0x2f;
1208
1209 hw->fc.original_type = e1000_fc_default;
1210 hw->fc.type = e1000_fc_default;
1211
1212 adapter->itr_setting = 3;
1213 adapter->itr = IGB_START_ITR;
1214
1215 igb_validate_mdi_setting(hw);
1216
1217 adapter->rx_csum = 1;
1218
1219 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1220 * enable the ACPI Magic Packet filter
1221 */
1222
1223 if (hw->bus.func == 0 ||
1224 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1225 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1226 &eeprom_data);
1227
1228 if (eeprom_data & eeprom_apme_mask)
1229 adapter->eeprom_wol |= E1000_WUFC_MAG;
1230
1231 /* now that we have the eeprom settings, apply the special cases where
1232 * the eeprom may be wrong or the board simply won't support wake on
1233 * lan on a particular port */
1234 switch (pdev->device) {
1235 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1236 adapter->eeprom_wol = 0;
1237 break;
1238 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1239 case E1000_DEV_ID_82576_FIBER:
1240 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1241 /* Wake events only supported on port A for dual fiber
1242 * regardless of eeprom setting */
1243 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1244 adapter->eeprom_wol = 0;
1245 break;
1246 }
1247
1248 /* initialize the wol settings based on the eeprom settings */
1249 adapter->wol = adapter->eeprom_wol;
e1b86d84 1250 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1251
1252 /* reset the hardware with the new settings */
1253 igb_reset(adapter);
1254
1255 /* let the f/w know that the h/w is now under the control of the
1256 * driver. */
1257 igb_get_hw_control(adapter);
1258
1259 /* tell the stack to leave us alone until igb_open() is called */
1260 netif_carrier_off(netdev);
fd2ea0a7 1261 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1262
1263 strcpy(netdev->name, "eth%d");
1264 err = register_netdev(netdev);
1265 if (err)
1266 goto err_register;
1267
421e02f0 1268#ifdef CONFIG_IGB_DCA
7dfc16fa
AD		 1269 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1270 (dca_add_requester(&pdev->dev) == 0)) {
1271 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1272 dev_info(&pdev->dev, "DCA enabled\n");
1273 /* Always use CB2 mode, difference is masked
1274 * in the CB driver. */
1275 wr32(E1000_DCA_CTRL, 2);
1276 igb_setup_dca(adapter);
1277 }
1278#endif
1279
9d5c8243
AK		 1280 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1281 /* print bus type/speed/width info */
7c510e4b 1282 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1283 netdev->name,
1284 ((hw->bus.speed == e1000_bus_speed_2500)
1285 ? "2.5Gb/s" : "unknown"),
1286 ((hw->bus.width == e1000_bus_width_pcie_x4)
1287 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1288 ? "Width x1" : "unknown"),
7c510e4b 1289 netdev->dev_addr);
9d5c8243
AK		 1290
1291 igb_read_part_num(hw, &part_num);
1292 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1293 (part_num >> 8), (part_num & 0xff));
1294
1295 dev_info(&pdev->dev,
1296 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1297 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1298 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1299 adapter->num_rx_queues, adapter->num_tx_queues);
1300
9d5c8243
AK		 1301 return 0;
1302
1303err_register:
1304 igb_release_hw_control(adapter);
1305err_eeprom:
1306 if (!igb_check_reset_block(hw))
f5f4cf08 1307 igb_reset_phy(hw);
9d5c8243
AK		 1308
1309 if (hw->flash_address)
1310 iounmap(hw->flash_address);
1311
1312 igb_remove_device(hw);
a88f10ec 1313 igb_free_queues(adapter);
9d5c8243
AK		 1314err_sw_init:
1315err_hw_init:
1316 iounmap(hw->hw_addr);
1317err_ioremap:
1318 free_netdev(netdev);
1319err_alloc_etherdev:
42bfd33a 1320 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1321err_pci_reg:
1322err_dma:
1323 pci_disable_device(pdev);
1324 return err;
1325}
1326
1327/**
1328 * igb_remove - Device Removal Routine
1329 * @pdev: PCI device information struct
1330 *
1331 * igb_remove is called by the PCI subsystem to alert the driver
1332 * that it should release a PCI device. The could be caused by a
1333 * Hot-Plug event, or because the driver is going to be removed from
1334 * memory.
1335 **/
1336static void __devexit igb_remove(struct pci_dev *pdev)
1337{
1338 struct net_device *netdev = pci_get_drvdata(pdev);
1339 struct igb_adapter *adapter = netdev_priv(netdev);
421e02f0 1340#ifdef CONFIG_IGB_DCA
fe4506b6 1341 struct e1000_hw *hw = &adapter->hw;
9280fa52 1342#endif
9d5c8243
AK		 1343
1344 /* flush_scheduled work may reschedule our watchdog task, so
1345 * explicitly disable watchdog tasks from being rescheduled */
1346 set_bit(__IGB_DOWN, &adapter->state);
1347 del_timer_sync(&adapter->watchdog_timer);
1348 del_timer_sync(&adapter->phy_info_timer);
1349
1350 flush_scheduled_work();
1351
421e02f0 1352#ifdef CONFIG_IGB_DCA
7dfc16fa 1353 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1354 dev_info(&pdev->dev, "DCA disabled\n");
1355 dca_remove_requester(&pdev->dev);
7dfc16fa 1356 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1357 wr32(E1000_DCA_CTRL, 1);
1358 }
1359#endif
1360
9d5c8243
AK		 1361 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1362 * would have already happened in close and is redundant. */
1363 igb_release_hw_control(adapter);
1364
1365 unregister_netdev(netdev);
1366
f5f4cf08
AD		 1367 if (!igb_check_reset_block(&adapter->hw))
1368 igb_reset_phy(&adapter->hw);
9d5c8243
AK		 1369
1370 igb_remove_device(&adapter->hw);
1371 igb_reset_interrupt_capability(adapter);
1372
a88f10ec 1373 igb_free_queues(adapter);
9d5c8243
AK		 1374
1375 iounmap(adapter->hw.hw_addr);
1376 if (adapter->hw.flash_address)
1377 iounmap(adapter->hw.flash_address);
42bfd33a 1378 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1379
1380 free_netdev(netdev);
1381
1382 pci_disable_device(pdev);
1383}
1384
1385/**
1386 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1387 * @adapter: board private structure to initialize
1388 *
1389 * igb_sw_init initializes the Adapter private data structure.
1390 * Fields are initialized based on PCI device information and
1391 * OS network device settings (MTU size).
1392 **/
1393static int __devinit igb_sw_init(struct igb_adapter *adapter)
1394{
1395 struct e1000_hw *hw = &adapter->hw;
1396 struct net_device *netdev = adapter->netdev;
1397 struct pci_dev *pdev = adapter->pdev;
1398
1399 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1400
68fd9910
AD		 1401 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1402 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1403 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1404 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1405 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1406 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1407
1408 /* Number of supported queues. */
1409 /* Having more queues than CPUs doesn't make sense. */
661086df 1410 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
661086df 1411 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
9d5c8243 1412
661086df
PWJ		 1413 /* This call may decrease the number of queues depending on
1414 * interrupt mode. */
9d5c8243
AK		 1415 igb_set_interrupt_capability(adapter);
1416
1417 if (igb_alloc_queues(adapter)) {
1418 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1419 return -ENOMEM;
1420 }
1421
1422 /* Explicitly disable IRQ since the NIC can be in any state. */
1423 igb_irq_disable(adapter);
1424
1425 set_bit(__IGB_DOWN, &adapter->state);
1426 return 0;
1427}
1428
1429/**
1430 * igb_open - Called when a network interface is made active
1431 * @netdev: network interface device structure
1432 *
1433 * Returns 0 on success, negative value on failure
1434 *
1435 * The open entry point is called when a network interface is made
1436 * active by the system (IFF_UP). At this point all resources needed
1437 * for transmit and receive operations are allocated, the interrupt
1438 * handler is registered with the OS, the watchdog timer is started,
1439 * and the stack is notified that the interface is ready.
1440 **/
1441static int igb_open(struct net_device *netdev)
1442{
1443 struct igb_adapter *adapter = netdev_priv(netdev);
1444 struct e1000_hw *hw = &adapter->hw;
1445 int err;
1446 int i;
1447
1448 /* disallow open during test */
1449 if (test_bit(__IGB_TESTING, &adapter->state))
1450 return -EBUSY;
1451
1452 /* allocate transmit descriptors */
1453 err = igb_setup_all_tx_resources(adapter);
1454 if (err)
1455 goto err_setup_tx;
1456
1457 /* allocate receive descriptors */
1458 err = igb_setup_all_rx_resources(adapter);
1459 if (err)
1460 goto err_setup_rx;
1461
1462 /* e1000_power_up_phy(adapter); */
1463
1464 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1465 if ((adapter->hw.mng_cookie.status &
1466 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1467 igb_update_mng_vlan(adapter);
1468
1469 /* before we allocate an interrupt, we must be ready to handle it.
1470 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1471 * as soon as we call pci_request_irq, so we have to setup our
1472 * clean_rx handler before we do so. */
1473 igb_configure(adapter);
1474
1475 err = igb_request_irq(adapter);
1476 if (err)
1477 goto err_req_irq;
1478
1479 /* From here on the code is the same as igb_up() */
1480 clear_bit(__IGB_DOWN, &adapter->state);
1481
844290e5
PW		 1482 for (i = 0; i < adapter->num_rx_queues; i++)
1483 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1484
1485 /* Clear any pending interrupts. */
1486 rd32(E1000_ICR);
844290e5
PW		 1487
1488 igb_irq_enable(adapter);
1489
d55b53ff
JK		 1490 netif_tx_start_all_queues(netdev);
1491
9d5c8243
AK		 1492 /* Fire a link status change interrupt to start the watchdog. */
1493 wr32(E1000_ICS, E1000_ICS_LSC);
1494
1495 return 0;
1496
1497err_req_irq:
1498 igb_release_hw_control(adapter);
1499 /* e1000_power_down_phy(adapter); */
1500 igb_free_all_rx_resources(adapter);
1501err_setup_rx:
1502 igb_free_all_tx_resources(adapter);
1503err_setup_tx:
1504 igb_reset(adapter);
1505
1506 return err;
1507}
1508
1509/**
1510 * igb_close - Disables a network interface
1511 * @netdev: network interface device structure
1512 *
1513 * Returns 0, this is not allowed to fail
1514 *
1515 * The close entry point is called when an interface is de-activated
1516 * by the OS. The hardware is still under the driver's control, but
1517 * needs to be disabled. A global MAC reset is issued to stop the
1518 * hardware, and all transmit and receive resources are freed.
1519 **/
1520static int igb_close(struct net_device *netdev)
1521{
1522 struct igb_adapter *adapter = netdev_priv(netdev);
1523
1524 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1525 igb_down(adapter);
1526
1527 igb_free_irq(adapter);
1528
1529 igb_free_all_tx_resources(adapter);
1530 igb_free_all_rx_resources(adapter);
1531
1532 /* kill manageability vlan ID if supported, but not if a vlan with
1533 * the same ID is registered on the host OS (let 8021q kill it) */
1534 if ((adapter->hw.mng_cookie.status &
1535 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1536 !(adapter->vlgrp &&
1537 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1538 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1539
1540 return 0;
1541}
1542
1543/**
1544 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1545 * @adapter: board private structure
1546 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1547 *
1548 * Return 0 on success, negative on failure
1549 **/
1550
1551int igb_setup_tx_resources(struct igb_adapter *adapter,
1552 struct igb_ring *tx_ring)
1553{
1554 struct pci_dev *pdev = adapter->pdev;
1555 int size;
1556
1557 size = sizeof(struct igb_buffer) * tx_ring->count;
1558 tx_ring->buffer_info = vmalloc(size);
1559 if (!tx_ring->buffer_info)
1560 goto err;
1561 memset(tx_ring->buffer_info, 0, size);
1562
1563 /* round up to nearest 4K */
1564 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1565 + sizeof(u32);
1566 tx_ring->size = ALIGN(tx_ring->size, 4096);
1567
1568 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1569 &tx_ring->dma);
1570
1571 if (!tx_ring->desc)
1572 goto err;
1573
1574 tx_ring->adapter = adapter;
1575 tx_ring->next_to_use = 0;
1576 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1577 return 0;
1578
1579err:
1580 vfree(tx_ring->buffer_info);
1581 dev_err(&adapter->pdev->dev,
1582 "Unable to allocate memory for the transmit descriptor ring\n");
1583 return -ENOMEM;
1584}
1585
1586/**
1587 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1588 * (Descriptors) for all queues
1589 * @adapter: board private structure
1590 *
1591 * Return 0 on success, negative on failure
1592 **/
1593static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1594{
1595 int i, err = 0;
661086df 1596 int r_idx;
9d5c8243
AK		 1597
1598 for (i = 0; i < adapter->num_tx_queues; i++) {
1599 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1600 if (err) {
1601 dev_err(&adapter->pdev->dev,
1602 "Allocation for Tx Queue %u failed\n", i);
1603 for (i--; i >= 0; i--)
3b644cf6 1604 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1605 break;
1606 }
1607 }
1608
661086df
PWJ		 1609 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1610 r_idx = i % adapter->num_tx_queues;
1611 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1612 }
9d5c8243
AK		 1613 return err;
1614}
1615
1616/**
1617 * igb_configure_tx - Configure transmit Unit after Reset
1618 * @adapter: board private structure
1619 *
1620 * Configure the Tx unit of the MAC after a reset.
1621 **/
1622static void igb_configure_tx(struct igb_adapter *adapter)
1623{
1624 u64 tdba, tdwba;
1625 struct e1000_hw *hw = &adapter->hw;
1626 u32 tctl;
1627 u32 txdctl, txctrl;
1628 int i;
1629
1630 for (i = 0; i < adapter->num_tx_queues; i++) {
1631 struct igb_ring *ring = &(adapter->tx_ring[i]);
1632
1633 wr32(E1000_TDLEN(i),
1634 ring->count * sizeof(struct e1000_tx_desc));
1635 tdba = ring->dma;
1636 wr32(E1000_TDBAL(i),
1637 tdba & 0x00000000ffffffffULL);
1638 wr32(E1000_TDBAH(i), tdba >> 32);
1639
1640 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1641 tdwba |= 1; /* enable head wb */
1642 wr32(E1000_TDWBAL(i),
1643 tdwba & 0x00000000ffffffffULL);
1644 wr32(E1000_TDWBAH(i), tdwba >> 32);
1645
1646 ring->head = E1000_TDH(i);
1647 ring->tail = E1000_TDT(i);
1648 writel(0, hw->hw_addr + ring->tail);
1649 writel(0, hw->hw_addr + ring->head);
1650 txdctl = rd32(E1000_TXDCTL(i));
1651 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1652 wr32(E1000_TXDCTL(i), txdctl);
1653
1654 /* Turn off Relaxed Ordering on head write-backs. The
1655 * writebacks MUST be delivered in order or it will
1656 * completely screw up our bookeeping.
1657 */
1658 txctrl = rd32(E1000_DCA_TXCTRL(i));
1659 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1660 wr32(E1000_DCA_TXCTRL(i), txctrl);
1661 }
1662
1663
1664
1665 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1666
1667 /* Program the Transmit Control Register */
1668
1669 tctl = rd32(E1000_TCTL);
1670 tctl &= ~E1000_TCTL_CT;
1671 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1672 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1673
1674 igb_config_collision_dist(hw);
1675
1676 /* Setup Transmit Descriptor Settings for eop descriptor */
1677 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1678
1679 /* Enable transmits */
1680 tctl |= E1000_TCTL_EN;
1681
1682 wr32(E1000_TCTL, tctl);
1683}
1684
1685/**
1686 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1687 * @adapter: board private structure
1688 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1689 *
1690 * Returns 0 on success, negative on failure
1691 **/
1692
1693int igb_setup_rx_resources(struct igb_adapter *adapter,
1694 struct igb_ring *rx_ring)
1695{
1696 struct pci_dev *pdev = adapter->pdev;
1697 int size, desc_len;
1698
d3352520
AD		 1699#ifdef CONFIG_IGB_LRO
1700 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1701 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1702 if (!rx_ring->lro_mgr.lro_arr)
1703 goto err;
1704 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1705#endif
1706
9d5c8243
AK		 1707 size = sizeof(struct igb_buffer) * rx_ring->count;
1708 rx_ring->buffer_info = vmalloc(size);
1709 if (!rx_ring->buffer_info)
1710 goto err;
1711 memset(rx_ring->buffer_info, 0, size);
1712
1713 desc_len = sizeof(union e1000_adv_rx_desc);
1714
1715 /* Round up to nearest 4K */
1716 rx_ring->size = rx_ring->count * desc_len;
1717 rx_ring->size = ALIGN(rx_ring->size, 4096);
1718
1719 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1720 &rx_ring->dma);
1721
1722 if (!rx_ring->desc)
1723 goto err;
1724
1725 rx_ring->next_to_clean = 0;
1726 rx_ring->next_to_use = 0;
9d5c8243
AK		 1727
1728 rx_ring->adapter = adapter;
9d5c8243
AK		 1729
1730 return 0;
1731
1732err:
d3352520
AD		 1733#ifdef CONFIG_IGB_LRO
1734 vfree(rx_ring->lro_mgr.lro_arr);
1735 rx_ring->lro_mgr.lro_arr = NULL;
1736#endif
9d5c8243
AK		 1737 vfree(rx_ring->buffer_info);
1738 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1739 "the receive descriptor ring\n");
1740 return -ENOMEM;
1741}
1742
1743/**
1744 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1745 * (Descriptors) for all queues
1746 * @adapter: board private structure
1747 *
1748 * Return 0 on success, negative on failure
1749 **/
1750static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1751{
1752 int i, err = 0;
1753
1754 for (i = 0; i < adapter->num_rx_queues; i++) {
1755 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1756 if (err) {
1757 dev_err(&adapter->pdev->dev,
1758 "Allocation for Rx Queue %u failed\n", i);
1759 for (i--; i >= 0; i--)
3b644cf6 1760 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1761 break;
1762 }
1763 }
1764
1765 return err;
1766}
1767
1768/**
1769 * igb_setup_rctl - configure the receive control registers
1770 * @adapter: Board private structure
1771 **/
1772static void igb_setup_rctl(struct igb_adapter *adapter)
1773{
1774 struct e1000_hw *hw = &adapter->hw;
1775 u32 rctl;
1776 u32 srrctl = 0;
1777 int i;
1778
1779 rctl = rd32(E1000_RCTL);
1780
1781 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1782
1783 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1784 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1785 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1786
87cb7e8c
AK		 1787 /*
1788 * enable stripping of CRC. It's unlikely this will break BMC
1789 * redirection as it did with e1000. Newer features require
1790 * that the HW strips the CRC.
9d5c8243 1791 */
87cb7e8c 1792 rctl |= E1000_RCTL_SECRC;
9d5c8243 1793
9b07f3d3
AD		 1794 /*
1795 * disable store bad packets, long packet enable, and clear size bits.
1796 */
1797 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_LPE | E1000_RCTL_SZ_256);
9d5c8243 1798
9b07f3d3 1799 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
9d5c8243 1800 /* Setup buffer sizes */
9d5c8243
AK		 1801 switch (adapter->rx_buffer_len) {
1802 case IGB_RXBUFFER_256:
1803 rctl |= E1000_RCTL_SZ_256;
9d5c8243
AK		 1804 break;
1805 case IGB_RXBUFFER_512:
1806 rctl |= E1000_RCTL_SZ_512;
9d5c8243
AK		 1807 break;
1808 case IGB_RXBUFFER_1024:
1809 rctl |= E1000_RCTL_SZ_1024;
9d5c8243 1810 break;
9d5c8243
AK		 1811 default:
1812 rctl |= E1000_RCTL_SZ_2048;
9d5c8243 1813 break;
9d5c8243
AK		 1814 }
1815 } else {
9b07f3d3 1816 rctl |= E1000_RCTL_LPE;
9d5c8243
AK		 1817 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1818 }
1819
1820 /* 82575 and greater support packet-split where the protocol
1821 * header is placed in skb->data and the packet data is
1822 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1823 * In the case of a non-split, skb->data is linearly filled,
1824 * followed by the page buffers. Therefore, skb->data is
1825 * sized to hold the largest protocol header.
1826 */
1827 /* allocations using alloc_page take too long for regular MTU
1828 * so only enable packet split for jumbo frames */
1829 if (rctl & E1000_RCTL_LPE) {
1830 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1831 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1832 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1833 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1834 } else {
1835 adapter->rx_ps_hdr_size = 0;
1836 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1837 }
1838
1839 for (i = 0; i < adapter->num_rx_queues; i++)
1840 wr32(E1000_SRRCTL(i), srrctl);
1841
1842 wr32(E1000_RCTL, rctl);
1843}
1844
1845/**
1846 * igb_configure_rx - Configure receive Unit after Reset
1847 * @adapter: board private structure
1848 *
1849 * Configure the Rx unit of the MAC after a reset.
1850 **/
1851static void igb_configure_rx(struct igb_adapter *adapter)
1852{
1853 u64 rdba;
1854 struct e1000_hw *hw = &adapter->hw;
1855 u32 rctl, rxcsum;
1856 u32 rxdctl;
1857 int i;
1858
1859 /* disable receives while setting up the descriptors */
1860 rctl = rd32(E1000_RCTL);
1861 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1862 wrfl();
1863 mdelay(10);
1864
1865 if (adapter->itr_setting > 3)
6eb5a7f1 1866 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1867
1868 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1869 * the Base and Length of the Rx Descriptor Ring */
1870 for (i = 0; i < adapter->num_rx_queues; i++) {
1871 struct igb_ring *ring = &(adapter->rx_ring[i]);
1872 rdba = ring->dma;
1873 wr32(E1000_RDBAL(i),
1874 rdba & 0x00000000ffffffffULL);
1875 wr32(E1000_RDBAH(i), rdba >> 32);
1876 wr32(E1000_RDLEN(i),
1877 ring->count * sizeof(union e1000_adv_rx_desc));
1878
1879 ring->head = E1000_RDH(i);
1880 ring->tail = E1000_RDT(i);
1881 writel(0, hw->hw_addr + ring->tail);
1882 writel(0, hw->hw_addr + ring->head);
1883
1884 rxdctl = rd32(E1000_RXDCTL(i));
1885 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1886 rxdctl &= 0xFFF00000;
1887 rxdctl |= IGB_RX_PTHRESH;
1888 rxdctl |= IGB_RX_HTHRESH << 8;
1889 rxdctl |= IGB_RX_WTHRESH << 16;
1890 wr32(E1000_RXDCTL(i), rxdctl);
d3352520
AD		 1891#ifdef CONFIG_IGB_LRO
1892 /* Intitial LRO Settings */
1893 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1894 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1895 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1896 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1897 ring->lro_mgr.dev = adapter->netdev;
1898 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1899 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1900#endif
9d5c8243
AK		 1901 }
1902
1903 if (adapter->num_rx_queues > 1) {
1904 u32 random[10];
1905 u32 mrqc;
1906 u32 j, shift;
1907 union e1000_reta {
1908 u32 dword;
1909 u8 bytes[4];
1910 } reta;
1911
1912 get_random_bytes(&random[0], 40);
1913
2d064c06
AD		 1914 if (hw->mac.type >= e1000_82576)
1915 shift = 0;
1916 else
1917 shift = 6;
9d5c8243
AK		 1918 for (j = 0; j < (32 * 4); j++) {
1919 reta.bytes[j & 3] =
1920 (j % adapter->num_rx_queues) << shift;
1921 if ((j & 3) == 3)
1922 writel(reta.dword,
1923 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1924 }
1925 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1926
1927 /* Fill out hash function seeds */
1928 for (j = 0; j < 10; j++)
1929 array_wr32(E1000_RSSRK(0), j, random[j]);
1930
1931 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1932 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1933 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1934 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1935 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1936 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1937 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1938 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1939
1940
1941 wr32(E1000_MRQC, mrqc);
1942
1943 /* Multiqueue and raw packet checksumming are mutually
1944 * exclusive. Note that this not the same as TCP/IP
1945 * checksumming, which works fine. */
1946 rxcsum = rd32(E1000_RXCSUM);
1947 rxcsum |= E1000_RXCSUM_PCSD;
1948 wr32(E1000_RXCSUM, rxcsum);
1949 } else {
1950 /* Enable Receive Checksum Offload for TCP and UDP */
1951 rxcsum = rd32(E1000_RXCSUM);
1952 if (adapter->rx_csum) {
1953 rxcsum |= E1000_RXCSUM_TUOFL;
1954
1955 /* Enable IPv4 payload checksum for UDP fragments
1956 * Must be used in conjunction with packet-split. */
1957 if (adapter->rx_ps_hdr_size)
1958 rxcsum |= E1000_RXCSUM_IPPCSE;
1959 } else {
1960 rxcsum &= ~E1000_RXCSUM_TUOFL;
1961 /* don't need to clear IPPCSE as it defaults to 0 */
1962 }
1963 wr32(E1000_RXCSUM, rxcsum);
1964 }
1965
1966 if (adapter->vlgrp)
1967 wr32(E1000_RLPML,
1968 adapter->max_frame_size + VLAN_TAG_SIZE);
1969 else
1970 wr32(E1000_RLPML, adapter->max_frame_size);
1971
1972 /* Enable Receives */
1973 wr32(E1000_RCTL, rctl);
1974}
1975
1976/**
1977 * igb_free_tx_resources - Free Tx Resources per Queue
1978 * @adapter: board private structure
1979 * @tx_ring: Tx descriptor ring for a specific queue
1980 *
1981 * Free all transmit software resources
1982 **/
68fd9910 1983void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1984{
3b644cf6 1985 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1986
3b644cf6 1987 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1988
1989 vfree(tx_ring->buffer_info);
1990 tx_ring->buffer_info = NULL;
1991
1992 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1993
1994 tx_ring->desc = NULL;
1995}
1996
1997/**
1998 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1999 * @adapter: board private structure
2000 *
2001 * Free all transmit software resources
2002 **/
2003static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2004{
2005 int i;
2006
2007 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2008 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2009}
2010
2011static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2012 struct igb_buffer *buffer_info)
2013{
2014 if (buffer_info->dma) {
2015 pci_unmap_page(adapter->pdev,
2016 buffer_info->dma,
2017 buffer_info->length,
2018 PCI_DMA_TODEVICE);
2019 buffer_info->dma = 0;
2020 }
2021 if (buffer_info->skb) {
2022 dev_kfree_skb_any(buffer_info->skb);
2023 buffer_info->skb = NULL;
2024 }
2025 buffer_info->time_stamp = 0;
2026 /* buffer_info must be completely set up in the transmit path */
2027}
2028
2029/**
2030 * igb_clean_tx_ring - Free Tx Buffers
2031 * @adapter: board private structure
2032 * @tx_ring: ring to be cleaned
2033 **/
3b644cf6 2034static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2035{
3b644cf6 2036 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2037 struct igb_buffer *buffer_info;
2038 unsigned long size;
2039 unsigned int i;
2040
2041 if (!tx_ring->buffer_info)
2042 return;
2043 /* Free all the Tx ring sk_buffs */
2044
2045 for (i = 0; i < tx_ring->count; i++) {
2046 buffer_info = &tx_ring->buffer_info[i];
2047 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2048 }
2049
2050 size = sizeof(struct igb_buffer) * tx_ring->count;
2051 memset(tx_ring->buffer_info, 0, size);
2052
2053 /* Zero out the descriptor ring */
2054
2055 memset(tx_ring->desc, 0, tx_ring->size);
2056
2057 tx_ring->next_to_use = 0;
2058 tx_ring->next_to_clean = 0;
2059
2060 writel(0, adapter->hw.hw_addr + tx_ring->head);
2061 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2062}
2063
2064/**
2065 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2066 * @adapter: board private structure
2067 **/
2068static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2069{
2070 int i;
2071
2072 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2073 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2074}
2075
2076/**
2077 * igb_free_rx_resources - Free Rx Resources
2078 * @adapter: board private structure
2079 * @rx_ring: ring to clean the resources from
2080 *
2081 * Free all receive software resources
2082 **/
68fd9910 2083void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2084{
3b644cf6 2085 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2086
3b644cf6 2087 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2088
2089 vfree(rx_ring->buffer_info);
2090 rx_ring->buffer_info = NULL;
2091
d3352520
AD		 2092#ifdef CONFIG_IGB_LRO
2093 vfree(rx_ring->lro_mgr.lro_arr);
2094 rx_ring->lro_mgr.lro_arr = NULL;
2095#endif
2096
9d5c8243
AK		 2097 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2098
2099 rx_ring->desc = NULL;
2100}
2101
2102/**
2103 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2104 * @adapter: board private structure
2105 *
2106 * Free all receive software resources
2107 **/
2108static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2109{
2110 int i;
2111
2112 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2113 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2114}
2115
2116/**
2117 * igb_clean_rx_ring - Free Rx Buffers per Queue
2118 * @adapter: board private structure
2119 * @rx_ring: ring to free buffers from
2120 **/
3b644cf6 2121static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2122{
3b644cf6 2123 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2124 struct igb_buffer *buffer_info;
2125 struct pci_dev *pdev = adapter->pdev;
2126 unsigned long size;
2127 unsigned int i;
2128
2129 if (!rx_ring->buffer_info)
2130 return;
2131 /* Free all the Rx ring sk_buffs */
2132 for (i = 0; i < rx_ring->count; i++) {
2133 buffer_info = &rx_ring->buffer_info[i];
2134 if (buffer_info->dma) {
2135 if (adapter->rx_ps_hdr_size)
2136 pci_unmap_single(pdev, buffer_info->dma,
2137 adapter->rx_ps_hdr_size,
2138 PCI_DMA_FROMDEVICE);
2139 else
2140 pci_unmap_single(pdev, buffer_info->dma,
2141 adapter->rx_buffer_len,
2142 PCI_DMA_FROMDEVICE);
2143 buffer_info->dma = 0;
2144 }
2145
2146 if (buffer_info->skb) {
2147 dev_kfree_skb(buffer_info->skb);
2148 buffer_info->skb = NULL;
2149 }
2150 if (buffer_info->page) {
bf36c1a0
AD		 2151 if (buffer_info->page_dma)
2152 pci_unmap_page(pdev, buffer_info->page_dma,
2153 PAGE_SIZE / 2,
2154 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2155 put_page(buffer_info->page);
2156 buffer_info->page = NULL;
2157 buffer_info->page_dma = 0;
bf36c1a0 2158 buffer_info->page_offset = 0;
9d5c8243
AK		 2159 }
2160 }
2161
9d5c8243
AK		 2162 size = sizeof(struct igb_buffer) * rx_ring->count;
2163 memset(rx_ring->buffer_info, 0, size);
2164
2165 /* Zero out the descriptor ring */
2166 memset(rx_ring->desc, 0, rx_ring->size);
2167
2168 rx_ring->next_to_clean = 0;
2169 rx_ring->next_to_use = 0;
2170
2171 writel(0, adapter->hw.hw_addr + rx_ring->head);
2172 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2173}
2174
2175/**
2176 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2177 * @adapter: board private structure
2178 **/
2179static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2180{
2181 int i;
2182
2183 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2184 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2185}
2186
2187/**
2188 * igb_set_mac - Change the Ethernet Address of the NIC
2189 * @netdev: network interface device structure
2190 * @p: pointer to an address structure
2191 *
2192 * Returns 0 on success, negative on failure
2193 **/
2194static int igb_set_mac(struct net_device *netdev, void *p)
2195{
2196 struct igb_adapter *adapter = netdev_priv(netdev);
2197 struct sockaddr *addr = p;
2198
2199 if (!is_valid_ether_addr(addr->sa_data))
2200 return -EADDRNOTAVAIL;
2201
2202 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2203 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2204
2205 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2206
2207 return 0;
2208}
2209
2210/**
2211 * igb_set_multi - Multicast and Promiscuous mode set
2212 * @netdev: network interface device structure
2213 *
2214 * The set_multi entry point is called whenever the multicast address
2215 * list or the network interface flags are updated. This routine is
2216 * responsible for configuring the hardware for proper multicast,
2217 * promiscuous mode, and all-multi behavior.
2218 **/
2219static void igb_set_multi(struct net_device *netdev)
2220{
2221 struct igb_adapter *adapter = netdev_priv(netdev);
2222 struct e1000_hw *hw = &adapter->hw;
2223 struct e1000_mac_info *mac = &hw->mac;
2224 struct dev_mc_list *mc_ptr;
2225 u8 *mta_list;
2226 u32 rctl;
2227 int i;
2228
2229 /* Check for Promiscuous and All Multicast modes */
2230
2231 rctl = rd32(E1000_RCTL);
2232
746b9f02 2233 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2234 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2235 rctl &= ~E1000_RCTL_VFE;
2236 } else {
2237 if (netdev->flags & IFF_ALLMULTI) {
2238 rctl |= E1000_RCTL_MPE;
2239 rctl &= ~E1000_RCTL_UPE;
2240 } else
2241 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2242 rctl |= E1000_RCTL_VFE;
746b9f02 2243 }
9d5c8243
AK		 2244 wr32(E1000_RCTL, rctl);
2245
2246 if (!netdev->mc_count) {
2247 /* nothing to program, so clear mc list */
2d064c06 2248 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2249 mac->rar_entry_count);
2250 return;
2251 }
2252
2253 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2254 if (!mta_list)
2255 return;
2256
2257 /* The shared function expects a packed array of only addresses. */
2258 mc_ptr = netdev->mc_list;
2259
2260 for (i = 0; i < netdev->mc_count; i++) {
2261 if (!mc_ptr)
2262 break;
2263 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2264 mc_ptr = mc_ptr->next;
2265 }
2d064c06
AD		 2266 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2267 mac->rar_entry_count);
9d5c8243
AK		 2268 kfree(mta_list);
2269}
2270
2271/* Need to wait a few seconds after link up to get diagnostic information from
2272 * the phy */
2273static void igb_update_phy_info(unsigned long data)
2274{
2275 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2276 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2277}
2278
2279/**
2280 * igb_watchdog - Timer Call-back
2281 * @data: pointer to adapter cast into an unsigned long
2282 **/
2283static void igb_watchdog(unsigned long data)
2284{
2285 struct igb_adapter *adapter = (struct igb_adapter *)data;
2286 /* Do the rest outside of interrupt context */
2287 schedule_work(&adapter->watchdog_task);
2288}
2289
2290static void igb_watchdog_task(struct work_struct *work)
2291{
2292 struct igb_adapter *adapter = container_of(work,
2293 struct igb_adapter, watchdog_task);
2294 struct e1000_hw *hw = &adapter->hw;
2295
2296 struct net_device *netdev = adapter->netdev;
2297 struct igb_ring *tx_ring = adapter->tx_ring;
2298 struct e1000_mac_info *mac = &adapter->hw.mac;
2299 u32 link;
7a6ea550 2300 u32 eics = 0;
9d5c8243 2301 s32 ret_val;
7a6ea550 2302 int i;
9d5c8243
AK		 2303
2304 if ((netif_carrier_ok(netdev)) &&
2305 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2306 goto link_up;
2307
2308 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2309 if ((ret_val == E1000_ERR_PHY) &&
2310 (hw->phy.type == e1000_phy_igp_3) &&
2311 (rd32(E1000_CTRL) &
2312 E1000_PHY_CTRL_GBE_DISABLE))
2313 dev_info(&adapter->pdev->dev,
2314 "Gigabit has been disabled, downgrading speed\n");
2315
2316 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2317 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2318 link = mac->serdes_has_link;
2319 else
2320 link = rd32(E1000_STATUS) &
2321 E1000_STATUS_LU;
2322
2323 if (link) {
2324 if (!netif_carrier_ok(netdev)) {
2325 u32 ctrl;
2326 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2327 &adapter->link_speed,
2328 &adapter->link_duplex);
2329
2330 ctrl = rd32(E1000_CTRL);
2331 dev_info(&adapter->pdev->dev,
2332 "NIC Link is Up %d Mbps %s, "
2333 "Flow Control: %s\n",
2334 adapter->link_speed,
2335 adapter->link_duplex == FULL_DUPLEX ?
2336 "Full Duplex" : "Half Duplex",
2337 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2338 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2339 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2340 E1000_CTRL_TFCE) ? "TX" : "None")));
2341
2342 /* tweak tx_queue_len according to speed/duplex and
2343 * adjust the timeout factor */
2344 netdev->tx_queue_len = adapter->tx_queue_len;
2345 adapter->tx_timeout_factor = 1;
2346 switch (adapter->link_speed) {
2347 case SPEED_10:
2348 netdev->tx_queue_len = 10;
2349 adapter->tx_timeout_factor = 14;
2350 break;
2351 case SPEED_100:
2352 netdev->tx_queue_len = 100;
2353 /* maybe add some timeout factor ? */
2354 break;
2355 }
2356
2357 netif_carrier_on(netdev);
fd2ea0a7 2358 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2359
2360 if (!test_bit(__IGB_DOWN, &adapter->state))
2361 mod_timer(&adapter->phy_info_timer,
2362 round_jiffies(jiffies + 2 * HZ));
2363 }
2364 } else {
2365 if (netif_carrier_ok(netdev)) {
2366 adapter->link_speed = 0;
2367 adapter->link_duplex = 0;
2368 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2369 netif_carrier_off(netdev);
fd2ea0a7 2370 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2371 if (!test_bit(__IGB_DOWN, &adapter->state))
2372 mod_timer(&adapter->phy_info_timer,
2373 round_jiffies(jiffies + 2 * HZ));
2374 }
2375 }
2376
2377link_up:
2378 igb_update_stats(adapter);
2379
2380 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2381 adapter->tpt_old = adapter->stats.tpt;
2382 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2383 adapter->colc_old = adapter->stats.colc;
2384
2385 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2386 adapter->gorc_old = adapter->stats.gorc;
2387 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2388 adapter->gotc_old = adapter->stats.gotc;
2389
2390 igb_update_adaptive(&adapter->hw);
2391
2392 if (!netif_carrier_ok(netdev)) {
2393 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2394 /* We've lost link, so the controller stops DMA,
2395 * but we've got queued Tx work that's never going
2396 * to get done, so reset controller to flush Tx.
2397 * (Do the reset outside of interrupt context). */
2398 adapter->tx_timeout_count++;
2399 schedule_work(&adapter->reset_task);
2400 }
2401 }
2402
2403 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2404 if (adapter->msix_entries) {
2405 for (i = 0; i < adapter->num_rx_queues; i++)
2406 eics |= adapter->rx_ring[i].eims_value;
2407 wr32(E1000_EICS, eics);
2408 } else {
2409 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2410 }
9d5c8243
AK		 2411
2412 /* Force detection of hung controller every watchdog period */
2413 tx_ring->detect_tx_hung = true;
2414
2415 /* Reset the timer */
2416 if (!test_bit(__IGB_DOWN, &adapter->state))
2417 mod_timer(&adapter->watchdog_timer,
2418 round_jiffies(jiffies + 2 * HZ));
2419}
2420
2421enum latency_range {
2422 lowest_latency = 0,
2423 low_latency = 1,
2424 bulk_latency = 2,
2425 latency_invalid = 255
2426};
2427
2428
6eb5a7f1
AD		 2429/**
2430 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2431 *
2432 * Stores a new ITR value based on strictly on packet size. This
2433 * algorithm is less sophisticated than that used in igb_update_itr,
2434 * due to the difficulty of synchronizing statistics across multiple
2435 * receive rings. The divisors and thresholds used by this fuction
2436 * were determined based on theoretical maximum wire speed and testing
2437 * data, in order to minimize response time while increasing bulk
2438 * throughput.
2439 * This functionality is controlled by the InterruptThrottleRate module
2440 * parameter (see igb_param.c)
2441 * NOTE: This function is called only when operating in a multiqueue
2442 * receive environment.
2443 * @rx_ring: pointer to ring
2444 **/
2445static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2446{
6eb5a7f1
AD		 2447 int new_val = rx_ring->itr_val;
2448 int avg_wire_size = 0;
2449 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2450
6eb5a7f1
AD		 2451 if (!rx_ring->total_packets)
2452 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2453
6eb5a7f1
AD		 2454 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2455 * ints/sec - ITR timer value of 120 ticks.
2456 */
2457 if (adapter->link_speed != SPEED_1000) {
2458 new_val = 120;
2459 goto set_itr_val;
9d5c8243 2460 }
6eb5a7f1 2461 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2462
6eb5a7f1
AD		 2463 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2464 avg_wire_size += 24;
2465
2466 /* Don't starve jumbo frames */
2467 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2468
6eb5a7f1
AD		 2469 /* Give a little boost to mid-size frames */
2470 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2471 new_val = avg_wire_size / 3;
2472 else
2473 new_val = avg_wire_size / 2;
9d5c8243 2474
6eb5a7f1 2475set_itr_val:
9d5c8243
AK		 2476 if (new_val != rx_ring->itr_val) {
2477 rx_ring->itr_val = new_val;
6eb5a7f1 2478 rx_ring->set_itr = 1;
9d5c8243 2479 }
6eb5a7f1
AD		 2480clear_counts:
2481 rx_ring->total_bytes = 0;
2482 rx_ring->total_packets = 0;
9d5c8243
AK		 2483}
2484
2485/**
2486 * igb_update_itr - update the dynamic ITR value based on statistics
2487 * Stores a new ITR value based on packets and byte
2488 * counts during the last interrupt. The advantage of per interrupt
2489 * computation is faster updates and more accurate ITR for the current
2490 * traffic pattern. Constants in this function were computed
2491 * based on theoretical maximum wire speed and thresholds were set based
2492 * on testing data as well as attempting to minimize response time
2493 * while increasing bulk throughput.
2494 * this functionality is controlled by the InterruptThrottleRate module
2495 * parameter (see igb_param.c)
2496 * NOTE: These calculations are only valid when operating in a single-
2497 * queue environment.
2498 * @adapter: pointer to adapter
2499 * @itr_setting: current adapter->itr
2500 * @packets: the number of packets during this measurement interval
2501 * @bytes: the number of bytes during this measurement interval
2502 **/
2503static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2504 int packets, int bytes)
2505{
2506 unsigned int retval = itr_setting;
2507
2508 if (packets == 0)
2509 goto update_itr_done;
2510
2511 switch (itr_setting) {
2512 case lowest_latency:
2513 /* handle TSO and jumbo frames */
2514 if (bytes/packets > 8000)
2515 retval = bulk_latency;
2516 else if ((packets < 5) && (bytes > 512))
2517 retval = low_latency;
2518 break;
2519 case low_latency: /* 50 usec aka 20000 ints/s */
2520 if (bytes > 10000) {
2521 /* this if handles the TSO accounting */
2522 if (bytes/packets > 8000) {
2523 retval = bulk_latency;
2524 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2525 retval = bulk_latency;
2526 } else if ((packets > 35)) {
2527 retval = lowest_latency;
2528 }
2529 } else if (bytes/packets > 2000) {
2530 retval = bulk_latency;
2531 } else if (packets <= 2 && bytes < 512) {
2532 retval = lowest_latency;
2533 }
2534 break;
2535 case bulk_latency: /* 250 usec aka 4000 ints/s */
2536 if (bytes > 25000) {
2537 if (packets > 35)
2538 retval = low_latency;
2539 } else if (bytes < 6000) {
2540 retval = low_latency;
2541 }
2542 break;
2543 }
2544
2545update_itr_done:
2546 return retval;
2547}
2548
6eb5a7f1 2549static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2550{
2551 u16 current_itr;
2552 u32 new_itr = adapter->itr;
2553
2554 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2555 if (adapter->link_speed != SPEED_1000) {
2556 current_itr = 0;
2557 new_itr = 4000;
2558 goto set_itr_now;
2559 }
2560
2561 adapter->rx_itr = igb_update_itr(adapter,
2562 adapter->rx_itr,
2563 adapter->rx_ring->total_packets,
2564 adapter->rx_ring->total_bytes);
9d5c8243 2565
6eb5a7f1 2566 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2567 adapter->tx_itr = igb_update_itr(adapter,
2568 adapter->tx_itr,
2569 adapter->tx_ring->total_packets,
2570 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2571
2572 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2573 } else {
2574 current_itr = adapter->rx_itr;
2575 }
2576
6eb5a7f1
AD		 2577 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2578 if (adapter->itr_setting == 3 &&
2579 current_itr == lowest_latency)
2580 current_itr = low_latency;
2581
9d5c8243
AK		 2582 switch (current_itr) {
2583 /* counts and packets in update_itr are dependent on these numbers */
2584 case lowest_latency:
2585 new_itr = 70000;
2586 break;
2587 case low_latency:
2588 new_itr = 20000; /* aka hwitr = ~200 */
2589 break;
2590 case bulk_latency:
2591 new_itr = 4000;
2592 break;
2593 default:
2594 break;
2595 }
2596
2597set_itr_now:
6eb5a7f1
AD		 2598 adapter->rx_ring->total_bytes = 0;
2599 adapter->rx_ring->total_packets = 0;
2600 if (adapter->rx_ring->buddy) {
2601 adapter->rx_ring->buddy->total_bytes = 0;
2602 adapter->rx_ring->buddy->total_packets = 0;
2603 }
2604
9d5c8243
AK		 2605 if (new_itr != adapter->itr) {
2606 /* this attempts to bias the interrupt rate towards Bulk
2607 * by adding intermediate steps when interrupt rate is
2608 * increasing */
2609 new_itr = new_itr > adapter->itr ?
2610 min(adapter->itr + (new_itr >> 2), new_itr) :
2611 new_itr;
2612 /* Don't write the value here; it resets the adapter's
2613 * internal timer, and causes us to delay far longer than
2614 * we should between interrupts. Instead, we write the ITR
2615 * value at the beginning of the next interrupt so the timing
2616 * ends up being correct.
2617 */
2618 adapter->itr = new_itr;
6eb5a7f1
AD		 2619 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2620 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2621 }
2622
2623 return;
2624}
2625
2626
2627#define IGB_TX_FLAGS_CSUM 0x00000001
2628#define IGB_TX_FLAGS_VLAN 0x00000002
2629#define IGB_TX_FLAGS_TSO 0x00000004
2630#define IGB_TX_FLAGS_IPV4 0x00000008
2631#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2632#define IGB_TX_FLAGS_VLAN_SHIFT 16
2633
2634static inline int igb_tso_adv(struct igb_adapter *adapter,
2635 struct igb_ring *tx_ring,
2636 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2637{
2638 struct e1000_adv_tx_context_desc *context_desc;
2639 unsigned int i;
2640 int err;
2641 struct igb_buffer *buffer_info;
2642 u32 info = 0, tu_cmd = 0;
2643 u32 mss_l4len_idx, l4len;
2644 *hdr_len = 0;
2645
2646 if (skb_header_cloned(skb)) {
2647 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2648 if (err)
2649 return err;
2650 }
2651
2652 l4len = tcp_hdrlen(skb);
2653 *hdr_len += l4len;
2654
2655 if (skb->protocol == htons(ETH_P_IP)) {
2656 struct iphdr *iph = ip_hdr(skb);
2657 iph->tot_len = 0;
2658 iph->check = 0;
2659 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2660 iph->daddr, 0,
2661 IPPROTO_TCP,
2662 0);
2663 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2664 ipv6_hdr(skb)->payload_len = 0;
2665 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2666 &ipv6_hdr(skb)->daddr,
2667 0, IPPROTO_TCP, 0);
2668 }
2669
2670 i = tx_ring->next_to_use;
2671
2672 buffer_info = &tx_ring->buffer_info[i];
2673 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2674 /* VLAN MACLEN IPLEN */
2675 if (tx_flags & IGB_TX_FLAGS_VLAN)
2676 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2677 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2678 *hdr_len += skb_network_offset(skb);
2679 info |= skb_network_header_len(skb);
2680 *hdr_len += skb_network_header_len(skb);
2681 context_desc->vlan_macip_lens = cpu_to_le32(info);
2682
2683 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2684 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2685
2686 if (skb->protocol == htons(ETH_P_IP))
2687 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2688 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2689
2690 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2691
2692 /* MSS L4LEN IDX */
2693 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2694 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2695
7dfc16fa
AD		 2696 /* Context index must be unique per ring. */
2697 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2698 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2699
2700 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2701 context_desc->seqnum_seed = 0;
2702
2703 buffer_info->time_stamp = jiffies;
2704 buffer_info->dma = 0;
2705 i++;
2706 if (i == tx_ring->count)
2707 i = 0;
2708
2709 tx_ring->next_to_use = i;
2710
2711 return true;
2712}
2713
2714static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2715 struct igb_ring *tx_ring,
2716 struct sk_buff *skb, u32 tx_flags)
2717{
2718 struct e1000_adv_tx_context_desc *context_desc;
2719 unsigned int i;
2720 struct igb_buffer *buffer_info;
2721 u32 info = 0, tu_cmd = 0;
2722
2723 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2724 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2725 i = tx_ring->next_to_use;
2726 buffer_info = &tx_ring->buffer_info[i];
2727 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2728
2729 if (tx_flags & IGB_TX_FLAGS_VLAN)
2730 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2731 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2732 if (skb->ip_summed == CHECKSUM_PARTIAL)
2733 info |= skb_network_header_len(skb);
2734
2735 context_desc->vlan_macip_lens = cpu_to_le32(info);
2736
2737 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2738
2739 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2740 switch (skb->protocol) {
2741 case __constant_htons(ETH_P_IP):
9d5c8243 2742 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2743 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2744 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2745 break;
2746 case __constant_htons(ETH_P_IPV6):
2747 /* XXX what about other V6 headers?? */
2748 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2749 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2750 break;
2751 default:
2752 if (unlikely(net_ratelimit()))
2753 dev_warn(&adapter->pdev->dev,
2754 "partial checksum but proto=%x!\n",
2755 skb->protocol);
2756 break;
2757 }
9d5c8243
AK		 2758 }
2759
2760 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2761 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2762 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2763 context_desc->mss_l4len_idx =
2764 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2765
2766 buffer_info->time_stamp = jiffies;
2767 buffer_info->dma = 0;
2768
2769 i++;
2770 if (i == tx_ring->count)
2771 i = 0;
2772 tx_ring->next_to_use = i;
2773
2774 return true;
2775 }
2776
2777
2778 return false;
2779}
2780
2781#define IGB_MAX_TXD_PWR 16
2782#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2783
2784static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2785 struct igb_ring *tx_ring,
2786 struct sk_buff *skb)
2787{
2788 struct igb_buffer *buffer_info;
2789 unsigned int len = skb_headlen(skb);
2790 unsigned int count = 0, i;
2791 unsigned int f;
2792
2793 i = tx_ring->next_to_use;
2794
2795 buffer_info = &tx_ring->buffer_info[i];
2796 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2797 buffer_info->length = len;
2798 /* set time_stamp *before* dma to help avoid a possible race */
2799 buffer_info->time_stamp = jiffies;
2800 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2801 PCI_DMA_TODEVICE);
2802 count++;
2803 i++;
2804 if (i == tx_ring->count)
2805 i = 0;
2806
2807 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2808 struct skb_frag_struct *frag;
2809
2810 frag = &skb_shinfo(skb)->frags[f];
2811 len = frag->size;
2812
2813 buffer_info = &tx_ring->buffer_info[i];
2814 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2815 buffer_info->length = len;
2816 buffer_info->time_stamp = jiffies;
2817 buffer_info->dma = pci_map_page(adapter->pdev,
2818 frag->page,
2819 frag->page_offset,
2820 len,
2821 PCI_DMA_TODEVICE);
2822
2823 count++;
2824 i++;
2825 if (i == tx_ring->count)
2826 i = 0;
2827 }
2828
2829 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2830 tx_ring->buffer_info[i].skb = skb;
2831
2832 return count;
2833}
2834
2835static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2836 struct igb_ring *tx_ring,
2837 int tx_flags, int count, u32 paylen,
2838 u8 hdr_len)
2839{
2840 union e1000_adv_tx_desc *tx_desc = NULL;
2841 struct igb_buffer *buffer_info;
2842 u32 olinfo_status = 0, cmd_type_len;
2843 unsigned int i;
2844
2845 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2846 E1000_ADVTXD_DCMD_DEXT);
2847
2848 if (tx_flags & IGB_TX_FLAGS_VLAN)
2849 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2850
2851 if (tx_flags & IGB_TX_FLAGS_TSO) {
2852 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2853
2854 /* insert tcp checksum */
2855 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2856
2857 /* insert ip checksum */
2858 if (tx_flags & IGB_TX_FLAGS_IPV4)
2859 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2860
2861 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2862 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2863 }
2864
7dfc16fa
AD		 2865 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2866 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2867 IGB_TX_FLAGS_VLAN)))
661086df 2868 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2869
2870 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2871
2872 i = tx_ring->next_to_use;
2873 while (count--) {
2874 buffer_info = &tx_ring->buffer_info[i];
2875 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2876 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2877 tx_desc->read.cmd_type_len =
2878 cpu_to_le32(cmd_type_len | buffer_info->length);
2879 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2880 i++;
2881 if (i == tx_ring->count)
2882 i = 0;
2883 }
2884
2885 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2886 /* Force memory writes to complete before letting h/w
2887 * know there are new descriptors to fetch. (Only
2888 * applicable for weak-ordered memory model archs,
2889 * such as IA-64). */
2890 wmb();
2891
2892 tx_ring->next_to_use = i;
2893 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2894 /* we need this if more than one processor can write to our tail
2895 * at a time, it syncronizes IO on IA64/Altix systems */
2896 mmiowb();
2897}
2898
2899static int __igb_maybe_stop_tx(struct net_device *netdev,
2900 struct igb_ring *tx_ring, int size)
2901{
2902 struct igb_adapter *adapter = netdev_priv(netdev);
2903
661086df 2904 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2905
9d5c8243
AK		 2906 /* Herbert's original patch had:
2907 * smp_mb__after_netif_stop_queue();
2908 * but since that doesn't exist yet, just open code it. */
2909 smp_mb();
2910
2911 /* We need to check again in a case another CPU has just
2912 * made room available. */
2913 if (IGB_DESC_UNUSED(tx_ring) < size)
2914 return -EBUSY;
2915
2916 /* A reprieve! */
661086df 2917 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2918 ++adapter->restart_queue;
2919 return 0;
2920}
2921
2922static int igb_maybe_stop_tx(struct net_device *netdev,
2923 struct igb_ring *tx_ring, int size)
2924{
2925 if (IGB_DESC_UNUSED(tx_ring) >= size)
2926 return 0;
2927 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2928}
2929
2930#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2931
2932static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2933 struct net_device *netdev,
2934 struct igb_ring *tx_ring)
2935{
2936 struct igb_adapter *adapter = netdev_priv(netdev);
2937 unsigned int tx_flags = 0;
2938 unsigned int len;
9d5c8243
AK		 2939 u8 hdr_len = 0;
2940 int tso = 0;
2941
2942 len = skb_headlen(skb);
2943
2944 if (test_bit(__IGB_DOWN, &adapter->state)) {
2945 dev_kfree_skb_any(skb);
2946 return NETDEV_TX_OK;
2947 }
2948
2949 if (skb->len <= 0) {
2950 dev_kfree_skb_any(skb);
2951 return NETDEV_TX_OK;
2952 }
2953
9d5c8243
AK		 2954 /* need: 1 descriptor per page,
2955 * + 2 desc gap to keep tail from touching head,
2956 * + 1 desc for skb->data,
2957 * + 1 desc for context descriptor,
2958 * otherwise try next time */
2959 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2960 /* this is a hard error */
9d5c8243
AK		 2961 return NETDEV_TX_BUSY;
2962 }
6eb5a7f1 2963 skb_orphan(skb);
9d5c8243
AK		 2964
2965 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2966 tx_flags |= IGB_TX_FLAGS_VLAN;
2967 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2968 }
2969
661086df
PWJ		 2970 if (skb->protocol == htons(ETH_P_IP))
2971 tx_flags |= IGB_TX_FLAGS_IPV4;
2972
9d5c8243
AK		 2973 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2974 &hdr_len) : 0;
2975
2976 if (tso < 0) {
2977 dev_kfree_skb_any(skb);
9d5c8243
AK		 2978 return NETDEV_TX_OK;
2979 }
2980
2981 if (tso)
2982 tx_flags |= IGB_TX_FLAGS_TSO;
2983 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2984 if (skb->ip_summed == CHECKSUM_PARTIAL)
2985 tx_flags |= IGB_TX_FLAGS_CSUM;
2986
9d5c8243
AK		 2987 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2988 igb_tx_map_adv(adapter, tx_ring, skb),
2989 skb->len, hdr_len);
2990
2991 netdev->trans_start = jiffies;
2992
2993 /* Make sure there is space in the ring for the next send. */
2994 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2995
9d5c8243
AK		 2996 return NETDEV_TX_OK;
2997}
2998
2999static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3000{
3001 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3002 struct igb_ring *tx_ring;
3003
661086df
PWJ		 3004 int r_idx = 0;
3005 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3006 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3007
3008 /* This goes back to the question of how to logically map a tx queue
3009 * to a flow. Right now, performance is impacted slightly negatively
3010 * if using multiple tx queues. If the stack breaks away from a
3011 * single qdisc implementation, we can look at this again. */
3012 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3013}
3014
3015/**
3016 * igb_tx_timeout - Respond to a Tx Hang
3017 * @netdev: network interface device structure
3018 **/
3019static void igb_tx_timeout(struct net_device *netdev)
3020{
3021 struct igb_adapter *adapter = netdev_priv(netdev);
3022 struct e1000_hw *hw = &adapter->hw;
3023
3024 /* Do the reset outside of interrupt context */
3025 adapter->tx_timeout_count++;
3026 schedule_work(&adapter->reset_task);
3027 wr32(E1000_EICS, adapter->eims_enable_mask &
3028 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3029}
3030
3031static void igb_reset_task(struct work_struct *work)
3032{
3033 struct igb_adapter *adapter;
3034 adapter = container_of(work, struct igb_adapter, reset_task);
3035
3036 igb_reinit_locked(adapter);
3037}
3038
3039/**
3040 * igb_get_stats - Get System Network Statistics
3041 * @netdev: network interface device structure
3042 *
3043 * Returns the address of the device statistics structure.
3044 * The statistics are actually updated from the timer callback.
3045 **/
3046static struct net_device_stats *
3047igb_get_stats(struct net_device *netdev)
3048{
3049 struct igb_adapter *adapter = netdev_priv(netdev);
3050
3051 /* only return the current stats */
3052 return &adapter->net_stats;
3053}
3054
3055/**
3056 * igb_change_mtu - Change the Maximum Transfer Unit
3057 * @netdev: network interface device structure
3058 * @new_mtu: new value for maximum frame size
3059 *
3060 * Returns 0 on success, negative on failure
3061 **/
3062static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3063{
3064 struct igb_adapter *adapter = netdev_priv(netdev);
3065 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3066
3067 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3068 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3069 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3070 return -EINVAL;
3071 }
3072
3073#define MAX_STD_JUMBO_FRAME_SIZE 9234
3074 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3075 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3076 return -EINVAL;
3077 }
3078
3079 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3080 msleep(1);
3081 /* igb_down has a dependency on max_frame_size */
3082 adapter->max_frame_size = max_frame;
3083 if (netif_running(netdev))
3084 igb_down(adapter);
3085
3086 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3087 * means we reserve 2 more, this pushes us to allocate from the next
3088 * larger slab size.
3089 * i.e. RXBUFFER_2048 --> size-4096 slab
3090 */
3091
3092 if (max_frame <= IGB_RXBUFFER_256)
3093 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3094 else if (max_frame <= IGB_RXBUFFER_512)
3095 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3096 else if (max_frame <= IGB_RXBUFFER_1024)
3097 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3098 else if (max_frame <= IGB_RXBUFFER_2048)
3099 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3100 else
bf36c1a0
AD		 3101#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3102 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3103#else
3104 adapter->rx_buffer_len = PAGE_SIZE / 2;
3105#endif
9d5c8243
AK		 3106 /* adjust allocation if LPE protects us, and we aren't using SBP */
3107 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3108 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3109 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3110
3111 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3112 netdev->mtu, new_mtu);
3113 netdev->mtu = new_mtu;
3114
3115 if (netif_running(netdev))
3116 igb_up(adapter);
3117 else
3118 igb_reset(adapter);
3119
3120 clear_bit(__IGB_RESETTING, &adapter->state);
3121
3122 return 0;
3123}
3124
3125/**
3126 * igb_update_stats - Update the board statistics counters
3127 * @adapter: board private structure
3128 **/
3129
3130void igb_update_stats(struct igb_adapter *adapter)
3131{
3132 struct e1000_hw *hw = &adapter->hw;
3133 struct pci_dev *pdev = adapter->pdev;
3134 u16 phy_tmp;
3135
3136#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3137
3138 /*
3139 * Prevent stats update while adapter is being reset, or if the pci
3140 * connection is down.
3141 */
3142 if (adapter->link_speed == 0)
3143 return;
3144 if (pci_channel_offline(pdev))
3145 return;
3146
3147 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3148 adapter->stats.gprc += rd32(E1000_GPRC);
3149 adapter->stats.gorc += rd32(E1000_GORCL);
3150 rd32(E1000_GORCH); /* clear GORCL */
3151 adapter->stats.bprc += rd32(E1000_BPRC);
3152 adapter->stats.mprc += rd32(E1000_MPRC);
3153 adapter->stats.roc += rd32(E1000_ROC);
3154
3155 adapter->stats.prc64 += rd32(E1000_PRC64);
3156 adapter->stats.prc127 += rd32(E1000_PRC127);
3157 adapter->stats.prc255 += rd32(E1000_PRC255);
3158 adapter->stats.prc511 += rd32(E1000_PRC511);
3159 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3160 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3161 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3162 adapter->stats.sec += rd32(E1000_SEC);
3163
3164 adapter->stats.mpc += rd32(E1000_MPC);
3165 adapter->stats.scc += rd32(E1000_SCC);
3166 adapter->stats.ecol += rd32(E1000_ECOL);
3167 adapter->stats.mcc += rd32(E1000_MCC);
3168 adapter->stats.latecol += rd32(E1000_LATECOL);
3169 adapter->stats.dc += rd32(E1000_DC);
3170 adapter->stats.rlec += rd32(E1000_RLEC);
3171 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3172 adapter->stats.xontxc += rd32(E1000_XONTXC);
3173 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3174 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3175 adapter->stats.fcruc += rd32(E1000_FCRUC);
3176 adapter->stats.gptc += rd32(E1000_GPTC);
3177 adapter->stats.gotc += rd32(E1000_GOTCL);
3178 rd32(E1000_GOTCH); /* clear GOTCL */
3179 adapter->stats.rnbc += rd32(E1000_RNBC);
3180 adapter->stats.ruc += rd32(E1000_RUC);
3181 adapter->stats.rfc += rd32(E1000_RFC);
3182 adapter->stats.rjc += rd32(E1000_RJC);
3183 adapter->stats.tor += rd32(E1000_TORH);
3184 adapter->stats.tot += rd32(E1000_TOTH);
3185 adapter->stats.tpr += rd32(E1000_TPR);
3186
3187 adapter->stats.ptc64 += rd32(E1000_PTC64);
3188 adapter->stats.ptc127 += rd32(E1000_PTC127);
3189 adapter->stats.ptc255 += rd32(E1000_PTC255);
3190 adapter->stats.ptc511 += rd32(E1000_PTC511);
3191 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3192 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3193
3194 adapter->stats.mptc += rd32(E1000_MPTC);
3195 adapter->stats.bptc += rd32(E1000_BPTC);
3196
3197 /* used for adaptive IFS */
3198
3199 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3200 adapter->stats.tpt += hw->mac.tx_packet_delta;
3201 hw->mac.collision_delta = rd32(E1000_COLC);
3202 adapter->stats.colc += hw->mac.collision_delta;
3203
3204 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3205 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3206 adapter->stats.tncrs += rd32(E1000_TNCRS);
3207 adapter->stats.tsctc += rd32(E1000_TSCTC);
3208 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3209
3210 adapter->stats.iac += rd32(E1000_IAC);
3211 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3212 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3213 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3214 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3215 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3216 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3217 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3218 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3219
3220 /* Fill out the OS statistics structure */
3221 adapter->net_stats.multicast = adapter->stats.mprc;
3222 adapter->net_stats.collisions = adapter->stats.colc;
3223
3224 /* Rx Errors */
3225
3226 /* RLEC on some newer hardware can be incorrect so build
3227 * our own version based on RUC and ROC */
3228 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3229 adapter->stats.crcerrs + adapter->stats.algnerrc +
3230 adapter->stats.ruc + adapter->stats.roc +
3231 adapter->stats.cexterr;
3232 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3233 adapter->stats.roc;
3234 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3235 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3236 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3237
3238 /* Tx Errors */
3239 adapter->net_stats.tx_errors = adapter->stats.ecol +
3240 adapter->stats.latecol;
3241 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3242 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3243 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3244
3245 /* Tx Dropped needs to be maintained elsewhere */
3246
3247 /* Phy Stats */
3248 if (hw->phy.media_type == e1000_media_type_copper) {
3249 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3250 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3251 &phy_tmp))) {
3252 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3253 adapter->phy_stats.idle_errors += phy_tmp;
3254 }
3255 }
3256
3257 /* Management Stats */
3258 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3259 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3260 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3261}
3262
3263
3264static irqreturn_t igb_msix_other(int irq, void *data)
3265{
3266 struct net_device *netdev = data;
3267 struct igb_adapter *adapter = netdev_priv(netdev);
3268 struct e1000_hw *hw = &adapter->hw;
844290e5 3269 u32 icr = rd32(E1000_ICR);
9d5c8243 3270
844290e5
PW		 3271 /* reading ICR causes bit 31 of EICR to be cleared */
3272 if (!(icr & E1000_ICR_LSC))
3273 goto no_link_interrupt;
3274 hw->mac.get_link_status = 1;
3275 /* guard against interrupt when we're going down */
3276 if (!test_bit(__IGB_DOWN, &adapter->state))
3277 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3278
9d5c8243
AK		 3279no_link_interrupt:
3280 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3281 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3282
3283 return IRQ_HANDLED;
3284}
3285
3286static irqreturn_t igb_msix_tx(int irq, void *data)
3287{
3288 struct igb_ring *tx_ring = data;
3289 struct igb_adapter *adapter = tx_ring->adapter;
3290 struct e1000_hw *hw = &adapter->hw;
3291
421e02f0 3292#ifdef CONFIG_IGB_DCA
7dfc16fa 3293 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3294 igb_update_tx_dca(tx_ring);
3295#endif
9d5c8243
AK		 3296 tx_ring->total_bytes = 0;
3297 tx_ring->total_packets = 0;
661086df
PWJ		 3298
3299 /* auto mask will automatically reenable the interrupt when we write
3300 * EICS */
3b644cf6 3301 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3302 /* Ring was not completely cleaned, so fire another interrupt */
3303 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3304 else
9d5c8243 3305 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3306
9d5c8243
AK		 3307 return IRQ_HANDLED;
3308}
3309
6eb5a7f1
AD		 3310static void igb_write_itr(struct igb_ring *ring)
3311{
3312 struct e1000_hw *hw = &ring->adapter->hw;
3313 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3314 switch (hw->mac.type) {
3315 case e1000_82576:
3316 wr32(ring->itr_register,
3317 ring->itr_val |
3318 0x80000000);
3319 break;
3320 default:
3321 wr32(ring->itr_register,
3322 ring->itr_val |
3323 (ring->itr_val << 16));
3324 break;
3325 }
3326 ring->set_itr = 0;
3327 }
3328}
3329
9d5c8243
AK		 3330static irqreturn_t igb_msix_rx(int irq, void *data)
3331{
3332 struct igb_ring *rx_ring = data;
3333 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3334
844290e5
PW		 3335 /* Write the ITR value calculated at the end of the
3336 * previous interrupt.
3337 */
9d5c8243 3338
6eb5a7f1 3339 igb_write_itr(rx_ring);
9d5c8243 3340
844290e5
PW		 3341 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3342 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3343
421e02f0 3344#ifdef CONFIG_IGB_DCA
7dfc16fa 3345 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3346 igb_update_rx_dca(rx_ring);
3347#endif
3348 return IRQ_HANDLED;
3349}
3350
421e02f0 3351#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3352static void igb_update_rx_dca(struct igb_ring *rx_ring)
3353{
3354 u32 dca_rxctrl;
3355 struct igb_adapter *adapter = rx_ring->adapter;
3356 struct e1000_hw *hw = &adapter->hw;
3357 int cpu = get_cpu();
3358 int q = rx_ring - adapter->rx_ring;
3359
3360 if (rx_ring->cpu != cpu) {
3361 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3362 if (hw->mac.type == e1000_82576) {
3363 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3364 dca_rxctrl |= dca_get_tag(cpu) <<
3365 E1000_DCA_RXCTRL_CPUID_SHIFT;
3366 } else {
3367 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3368 dca_rxctrl |= dca_get_tag(cpu);
3369 }
fe4506b6
JC		 3370 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3371 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3372 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3373 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3374 rx_ring->cpu = cpu;
3375 }
3376 put_cpu();
3377}
3378
3379static void igb_update_tx_dca(struct igb_ring *tx_ring)
3380{
3381 u32 dca_txctrl;
3382 struct igb_adapter *adapter = tx_ring->adapter;
3383 struct e1000_hw *hw = &adapter->hw;
3384 int cpu = get_cpu();
3385 int q = tx_ring - adapter->tx_ring;
3386
3387 if (tx_ring->cpu != cpu) {
3388 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3389 if (hw->mac.type == e1000_82576) {
3390 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3391 dca_txctrl |= dca_get_tag(cpu) <<
3392 E1000_DCA_TXCTRL_CPUID_SHIFT;
3393 } else {
3394 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3395 dca_txctrl |= dca_get_tag(cpu);
3396 }
fe4506b6
JC		 3397 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3398 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3399 tx_ring->cpu = cpu;
3400 }
3401 put_cpu();
3402}
3403
3404static void igb_setup_dca(struct igb_adapter *adapter)
3405{
3406 int i;
3407
7dfc16fa 3408 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3409 return;
3410
3411 for (i = 0; i < adapter->num_tx_queues; i++) {
3412 adapter->tx_ring[i].cpu = -1;
3413 igb_update_tx_dca(&adapter->tx_ring[i]);
3414 }
3415 for (i = 0; i < adapter->num_rx_queues; i++) {
3416 adapter->rx_ring[i].cpu = -1;
3417 igb_update_rx_dca(&adapter->rx_ring[i]);
3418 }
3419}
3420
3421static int __igb_notify_dca(struct device *dev, void *data)
3422{
3423 struct net_device *netdev = dev_get_drvdata(dev);
3424 struct igb_adapter *adapter = netdev_priv(netdev);
3425 struct e1000_hw *hw = &adapter->hw;
3426 unsigned long event = *(unsigned long *)data;
3427
7dfc16fa
AD		 3428 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3429 goto out;
3430
fe4506b6
JC		 3431 switch (event) {
3432 case DCA_PROVIDER_ADD:
3433 /* if already enabled, don't do it again */
7dfc16fa 3434 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3435 break;
7dfc16fa 3436 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3437 /* Always use CB2 mode, difference is masked
3438 * in the CB driver. */
3439 wr32(E1000_DCA_CTRL, 2);
3440 if (dca_add_requester(dev) == 0) {
3441 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3442 igb_setup_dca(adapter);
3443 break;
3444 }
3445 /* Fall Through since DCA is disabled. */
3446 case DCA_PROVIDER_REMOVE:
7dfc16fa 3447 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3448 /* without this a class_device is left
3449 * hanging around in the sysfs model */
3450 dca_remove_requester(dev);
3451 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3452 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3453 wr32(E1000_DCA_CTRL, 1);
3454 }
3455 break;
3456 }
7dfc16fa 3457out:
fe4506b6 3458 return 0;
9d5c8243
AK		 3459}
3460
fe4506b6
JC		 3461static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3462 void *p)
3463{
3464 int ret_val;
3465
3466 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3467 __igb_notify_dca);
3468
3469 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3470}
421e02f0 3471#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3472
3473/**
3474 * igb_intr_msi - Interrupt Handler
3475 * @irq: interrupt number
3476 * @data: pointer to a network interface device structure
3477 **/
3478static irqreturn_t igb_intr_msi(int irq, void *data)
3479{
3480 struct net_device *netdev = data;
3481 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3482 struct e1000_hw *hw = &adapter->hw;
3483 /* read ICR disables interrupts using IAM */
3484 u32 icr = rd32(E1000_ICR);
3485
6eb5a7f1 3486 igb_write_itr(adapter->rx_ring);
9d5c8243 3487
9d5c8243
AK		 3488 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3489 hw->mac.get_link_status = 1;
3490 if (!test_bit(__IGB_DOWN, &adapter->state))
3491 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3492 }
3493
844290e5 3494 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3495
3496 return IRQ_HANDLED;
3497}
3498
3499/**
3500 * igb_intr - Interrupt Handler
3501 * @irq: interrupt number
3502 * @data: pointer to a network interface device structure
3503 **/
3504static irqreturn_t igb_intr(int irq, void *data)
3505{
3506 struct net_device *netdev = data;
3507 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3508 struct e1000_hw *hw = &adapter->hw;
3509 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3510 * need for the IMC write */
3511 u32 icr = rd32(E1000_ICR);
3512 u32 eicr = 0;
3513 if (!icr)
3514 return IRQ_NONE; /* Not our interrupt */
3515
6eb5a7f1 3516 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3517
3518 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3519 * not set, then the adapter didn't send an interrupt */
3520 if (!(icr & E1000_ICR_INT_ASSERTED))
3521 return IRQ_NONE;
3522
3523 eicr = rd32(E1000_EICR);
3524
3525 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3526 hw->mac.get_link_status = 1;
3527 /* guard against interrupt when we're going down */
3528 if (!test_bit(__IGB_DOWN, &adapter->state))
3529 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3530 }
3531
844290e5 3532 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3533
3534 return IRQ_HANDLED;
3535}
3536
3537/**
661086df
PWJ		 3538 * igb_poll - NAPI Rx polling callback
3539 * @napi: napi polling structure
3540 * @budget: count of how many packets we should handle
9d5c8243 3541 **/
661086df 3542static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3543{
661086df
PWJ		 3544 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3545 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3546 struct net_device *netdev = adapter->netdev;
661086df 3547 int tx_clean_complete, work_done = 0;
9d5c8243 3548
661086df 3549 /* this poll routine only supports one tx and one rx queue */
421e02f0 3550#ifdef CONFIG_IGB_DCA
7dfc16fa 3551 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3552 igb_update_tx_dca(&adapter->tx_ring[0]);
3553#endif
661086df 3554 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3555
421e02f0 3556#ifdef CONFIG_IGB_DCA
7dfc16fa 3557 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3558 igb_update_rx_dca(&adapter->rx_ring[0]);
3559#endif
661086df 3560 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3561
3562 /* If no Tx and not enough Rx work done, exit the polling mode */
3563 if ((tx_clean_complete && (work_done < budget)) ||
3564 !netif_running(netdev)) {
9d5c8243 3565 if (adapter->itr_setting & 3)
6eb5a7f1 3566 igb_set_itr(adapter);
9d5c8243
AK		 3567 netif_rx_complete(netdev, napi);
3568 if (!test_bit(__IGB_DOWN, &adapter->state))
3569 igb_irq_enable(adapter);
3570 return 0;
3571 }
3572
3573 return 1;
3574}
3575
3576static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3577{
3578 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3579 struct igb_adapter *adapter = rx_ring->adapter;
3580 struct e1000_hw *hw = &adapter->hw;
3581 struct net_device *netdev = adapter->netdev;
3582 int work_done = 0;
3583
421e02f0 3584#ifdef CONFIG_IGB_DCA
7dfc16fa 3585 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3586 igb_update_rx_dca(rx_ring);
3587#endif
3b644cf6 3588 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3589
3590
3591 /* If not enough Rx work done, exit the polling mode */
3592 if ((work_done == 0) || !netif_running(netdev)) {
9d5c8243
AK		 3593 netif_rx_complete(netdev, napi);
3594
6eb5a7f1
AD		 3595 if (adapter->itr_setting & 3) {
3596 if (adapter->num_rx_queues == 1)
3597 igb_set_itr(adapter);
3598 else
3599 igb_update_ring_itr(rx_ring);
9d5c8243 3600 }
844290e5
PW		 3601
3602 if (!test_bit(__IGB_DOWN, &adapter->state))
3603 wr32(E1000_EIMS, rx_ring->eims_value);
3604
9d5c8243
AK		 3605 return 0;
3606 }
3607
3608 return 1;
3609}
6d8126f9
AV		 3610
3611static inline u32 get_head(struct igb_ring *tx_ring)
3612{
3613 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3614 return le32_to_cpu(*(volatile __le32 *)end);
3615}
3616
9d5c8243
AK		 3617/**
3618 * igb_clean_tx_irq - Reclaim resources after transmit completes
3619 * @adapter: board private structure
3620 * returns true if ring is completely cleaned
3621 **/
3b644cf6 3622static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3623{
3b644cf6 3624 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3625 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3626 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3627 struct e1000_tx_desc *tx_desc;
3628 struct igb_buffer *buffer_info;
3629 struct sk_buff *skb;
3630 unsigned int i;
3631 u32 head, oldhead;
3632 unsigned int count = 0;
9d5c8243 3633 unsigned int total_bytes = 0, total_packets = 0;
fc7d345d 3634 bool retval = true;
9d5c8243
AK		 3635
3636 rmb();
6d8126f9 3637 head = get_head(tx_ring);
9d5c8243
AK		 3638 i = tx_ring->next_to_clean;
3639 while (1) {
3640 while (i != head) {
9d5c8243
AK		 3641 tx_desc = E1000_TX_DESC(*tx_ring, i);
3642 buffer_info = &tx_ring->buffer_info[i];
3643 skb = buffer_info->skb;
3644
3645 if (skb) {
3646 unsigned int segs, bytecount;
3647 /* gso_segs is currently only valid for tcp */
3648 segs = skb_shinfo(skb)->gso_segs ?: 1;
3649 /* multiply data chunks by size of headers */
3650 bytecount = ((segs - 1) * skb_headlen(skb)) +
3651 skb->len;
3652 total_packets += segs;
3653 total_bytes += bytecount;
3654 }
3655
3656 igb_unmap_and_free_tx_resource(adapter, buffer_info);
9d5c8243
AK		 3657
3658 i++;
3659 if (i == tx_ring->count)
3660 i = 0;
3661
3662 count++;
3663 if (count == IGB_MAX_TX_CLEAN) {
3664 retval = false;
3665 goto done_cleaning;
3666 }
3667 }
3668 oldhead = head;
3669 rmb();
6d8126f9 3670 head = get_head(tx_ring);
9d5c8243
AK		 3671 if (head == oldhead)
3672 goto done_cleaning;
3673 } /* while (1) */
3674
3675done_cleaning:
3676 tx_ring->next_to_clean = i;
3677
fc7d345d 3678 if (unlikely(count &&
9d5c8243
AK		 3679 netif_carrier_ok(netdev) &&
3680 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3681 /* Make sure that anybody stopping the queue after this
3682 * sees the new next_to_clean.
3683 */
3684 smp_mb();
661086df
PWJ		 3685 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3686 !(test_bit(__IGB_DOWN, &adapter->state))) {
3687 netif_wake_subqueue(netdev, tx_ring->queue_index);
3688 ++adapter->restart_queue;
3689 }
9d5c8243
AK		 3690 }
3691
3692 if (tx_ring->detect_tx_hung) {
3693 /* Detect a transmit hang in hardware, this serializes the
3694 * check with the clearing of time_stamp and movement of i */
3695 tx_ring->detect_tx_hung = false;
3696 if (tx_ring->buffer_info[i].time_stamp &&
3697 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3698 (adapter->tx_timeout_factor * HZ))
3699 && !(rd32(E1000_STATUS) &
3700 E1000_STATUS_TXOFF)) {
3701
3702 tx_desc = E1000_TX_DESC(*tx_ring, i);
3703 /* detected Tx unit hang */
3704 dev_err(&adapter->pdev->dev,
3705 "Detected Tx Unit Hang\n"
2d064c06 3706 " Tx Queue <%d>\n"
9d5c8243
AK		 3707 " TDH <%x>\n"
3708 " TDT <%x>\n"
3709 " next_to_use <%x>\n"
3710 " next_to_clean <%x>\n"
3711 " head (WB) <%x>\n"
3712 "buffer_info[next_to_clean]\n"
3713 " time_stamp <%lx>\n"
3714 " jiffies <%lx>\n"
3715 " desc.status <%x>\n",
2d064c06 3716 tx_ring->queue_index,
9d5c8243
AK		 3717 readl(adapter->hw.hw_addr + tx_ring->head),
3718 readl(adapter->hw.hw_addr + tx_ring->tail),
3719 tx_ring->next_to_use,
3720 tx_ring->next_to_clean,
3721 head,
3722 tx_ring->buffer_info[i].time_stamp,
3723 jiffies,
3724 tx_desc->upper.fields.status);
661086df 3725 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3726 }
3727 }
3728 tx_ring->total_bytes += total_bytes;
3729 tx_ring->total_packets += total_packets;
e21ed353
AD		 3730 tx_ring->tx_stats.bytes += total_bytes;
3731 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3732 adapter->net_stats.tx_bytes += total_bytes;
3733 adapter->net_stats.tx_packets += total_packets;
3734 return retval;
3735}
3736
d3352520
AD		 3737#ifdef CONFIG_IGB_LRO
3738 /**
3739 * igb_get_skb_hdr - helper function for LRO header processing
3740 * @skb: pointer to sk_buff to be added to LRO packet
3741 * @iphdr: pointer to ip header structure
3742 * @tcph: pointer to tcp header structure
3743 * @hdr_flags: pointer to header flags
3744 * @priv: pointer to the receive descriptor for the current sk_buff
3745 **/
3746static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3747 u64 *hdr_flags, void *priv)
3748{
3749 union e1000_adv_rx_desc *rx_desc = priv;
3750 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3751 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3752
3753 /* Verify that this is a valid IPv4 TCP packet */
3754 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3755 E1000_RXDADV_PKTTYPE_TCP))
3756 return -1;
3757
3758 /* Set network headers */
3759 skb_reset_network_header(skb);
3760 skb_set_transport_header(skb, ip_hdrlen(skb));
3761 *iphdr = ip_hdr(skb);
3762 *tcph = tcp_hdr(skb);
3763 *hdr_flags = LRO_IPV4 | LRO_TCP;
3764
3765 return 0;
3766
3767}
3768#endif /* CONFIG_IGB_LRO */
9d5c8243
AK		 3769
3770/**
3771 * igb_receive_skb - helper function to handle rx indications
d3352520 3772 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3773 * @status: descriptor status field as written by hardware
3774 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3775 * @skb: pointer to sk_buff to be indicated to stack
3776 **/
d3352520
AD		 3777static void igb_receive_skb(struct igb_ring *ring, u8 status,
3778 union e1000_adv_rx_desc * rx_desc,
3779 struct sk_buff *skb)
3780{
3781 struct igb_adapter * adapter = ring->adapter;
3782 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3783
3784#ifdef CONFIG_IGB_LRO
3785 if (adapter->netdev->features & NETIF_F_LRO &&
3786 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3787 if (vlan_extracted)
3788 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3789 adapter->vlgrp,
3790 le16_to_cpu(rx_desc->wb.upper.vlan),
3791 rx_desc);
3792 else
3793 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3794 ring->lro_used = 1;
3795 } else {
3796#endif
3797 if (vlan_extracted)
3798 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3799 le16_to_cpu(rx_desc->wb.upper.vlan));
3800 else
3801
3802 netif_receive_skb(skb);
3803#ifdef CONFIG_IGB_LRO
3804 }
3805#endif
9d5c8243
AK		 3806}
3807
3808
3809static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3810 u32 status_err, struct sk_buff *skb)
3811{
3812 skb->ip_summed = CHECKSUM_NONE;
3813
3814 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3815 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3816 return;
3817 /* TCP/UDP checksum error bit is set */
3818 if (status_err &
3819 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3820 /* let the stack verify checksum errors */
3821 adapter->hw_csum_err++;
3822 return;
3823 }
3824 /* It must be a TCP or UDP packet with a valid checksum */
3825 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3826 skb->ip_summed = CHECKSUM_UNNECESSARY;
3827
3828 adapter->hw_csum_good++;
3829}
3830
3b644cf6
MW		 3831static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3832 int *work_done, int budget)
9d5c8243 3833{
3b644cf6 3834 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3835 struct net_device *netdev = adapter->netdev;
3836 struct pci_dev *pdev = adapter->pdev;
3837 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3838 struct igb_buffer *buffer_info , *next_buffer;
3839 struct sk_buff *skb;
bf36c1a0 3840 unsigned int i;
9d5c8243
AK		 3841 u32 length, hlen, staterr;
3842 bool cleaned = false;
3843 int cleaned_count = 0;
3844 unsigned int total_bytes = 0, total_packets = 0;
3845
3846 i = rx_ring->next_to_clean;
3847 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3848 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3849
3850 while (staterr & E1000_RXD_STAT_DD) {
3851 if (*work_done >= budget)
3852 break;
3853 (*work_done)++;
3854 buffer_info = &rx_ring->buffer_info[i];
3855
3856 /* HW will not DMA in data larger than the given buffer, even
3857 * if it parses the (NFS, of course) header to be larger. In
3858 * that case, it fills the header buffer and spills the rest
3859 * into the page.
3860 */
7deb07b1
AV		 3861 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3862 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3863 if (hlen > adapter->rx_ps_hdr_size)
3864 hlen = adapter->rx_ps_hdr_size;
3865
3866 length = le16_to_cpu(rx_desc->wb.upper.length);
3867 cleaned = true;
3868 cleaned_count++;
3869
bf36c1a0
AD		 3870 skb = buffer_info->skb;
3871 prefetch(skb->data - NET_IP_ALIGN);
3872 buffer_info->skb = NULL;
3873 if (!adapter->rx_ps_hdr_size) {
3874 pci_unmap_single(pdev, buffer_info->dma,
3875 adapter->rx_buffer_len +
3876 NET_IP_ALIGN,
3877 PCI_DMA_FROMDEVICE);
3878 skb_put(skb, length);
3879 goto send_up;
9d5c8243
AK		 3880 }
3881
bf36c1a0
AD		 3882 if (!skb_shinfo(skb)->nr_frags) {
3883 pci_unmap_single(pdev, buffer_info->dma,
3884 adapter->rx_ps_hdr_size +
3885 NET_IP_ALIGN,
3886 PCI_DMA_FROMDEVICE);
3887 skb_put(skb, hlen);
3888 }
3889
3890 if (length) {
9d5c8243 3891 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3892 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3893 buffer_info->page_dma = 0;
bf36c1a0
AD		 3894
3895 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3896 buffer_info->page,
3897 buffer_info->page_offset,
3898 length);
3899
3900 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3901 (page_count(buffer_info->page) != 1))
3902 buffer_info->page = NULL;
3903 else
3904 get_page(buffer_info->page);
9d5c8243
AK		 3905
3906 skb->len += length;
3907 skb->data_len += length;
9d5c8243 3908
bf36c1a0 3909 skb->truesize += length;
9d5c8243
AK		 3910 }
3911send_up:
9d5c8243
AK		 3912 i++;
3913 if (i == rx_ring->count)
3914 i = 0;
3915 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3916 prefetch(next_rxd);
3917 next_buffer = &rx_ring->buffer_info[i];
3918
bf36c1a0 3919 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3920 buffer_info->skb = next_buffer->skb;
3921 buffer_info->dma = next_buffer->dma;
3922 next_buffer->skb = skb;
3923 next_buffer->dma = 0;
bf36c1a0
AD		 3924 goto next_desc;
3925 }
3926
9d5c8243
AK		 3927 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3928 dev_kfree_skb_irq(skb);
3929 goto next_desc;
3930 }
9d5c8243
AK		 3931
3932 total_bytes += skb->len;
3933 total_packets++;
3934
3935 igb_rx_checksum_adv(adapter, staterr, skb);
3936
3937 skb->protocol = eth_type_trans(skb, netdev);
3938
d3352520 3939 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3940
9d5c8243
AK		 3941next_desc:
3942 rx_desc->wb.upper.status_error = 0;
3943
3944 /* return some buffers to hardware, one at a time is too slow */
3945 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3946 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3947 cleaned_count = 0;
3948 }
3949
3950 /* use prefetched values */
3951 rx_desc = next_rxd;
3952 buffer_info = next_buffer;
3953
3954 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3955 }
bf36c1a0 3956
9d5c8243
AK		 3957 rx_ring->next_to_clean = i;
3958 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3959
d3352520
AD		 3960#ifdef CONFIG_IGB_LRO
3961 if (rx_ring->lro_used) {
3962 lro_flush_all(&rx_ring->lro_mgr);
3963 rx_ring->lro_used = 0;
3964 }
3965#endif
3966
9d5c8243 3967 if (cleaned_count)
3b644cf6 3968 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3969
3970 rx_ring->total_packets += total_packets;
3971 rx_ring->total_bytes += total_bytes;
3972 rx_ring->rx_stats.packets += total_packets;
3973 rx_ring->rx_stats.bytes += total_bytes;
3974 adapter->net_stats.rx_bytes += total_bytes;
3975 adapter->net_stats.rx_packets += total_packets;
3976 return cleaned;
3977}
3978
3979
3980/**
3981 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3982 * @adapter: address of board private structure
3983 **/
3b644cf6 3984static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3985 int cleaned_count)
3986{
3b644cf6 3987 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3988 struct net_device *netdev = adapter->netdev;
3989 struct pci_dev *pdev = adapter->pdev;
3990 union e1000_adv_rx_desc *rx_desc;
3991 struct igb_buffer *buffer_info;
3992 struct sk_buff *skb;
3993 unsigned int i;
3994
3995 i = rx_ring->next_to_use;
3996 buffer_info = &rx_ring->buffer_info[i];
3997
3998 while (cleaned_count--) {
3999 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4000
bf36c1a0 4001 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4002 if (!buffer_info->page) {
bf36c1a0
AD		 4003 buffer_info->page = alloc_page(GFP_ATOMIC);
4004 if (!buffer_info->page) {
4005 adapter->alloc_rx_buff_failed++;
4006 goto no_buffers;
4007 }
4008 buffer_info->page_offset = 0;
4009 } else {
4010 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4011 }
4012 buffer_info->page_dma =
4013 pci_map_page(pdev,
4014 buffer_info->page,
bf36c1a0
AD		 4015 buffer_info->page_offset,
4016 PAGE_SIZE / 2,
9d5c8243
AK		 4017 PCI_DMA_FROMDEVICE);
4018 }
4019
4020 if (!buffer_info->skb) {
4021 int bufsz;
4022
4023 if (adapter->rx_ps_hdr_size)
4024 bufsz = adapter->rx_ps_hdr_size;
4025 else
4026 bufsz = adapter->rx_buffer_len;
4027 bufsz += NET_IP_ALIGN;
4028 skb = netdev_alloc_skb(netdev, bufsz);
4029
4030 if (!skb) {
4031 adapter->alloc_rx_buff_failed++;
4032 goto no_buffers;
4033 }
4034
4035 /* Make buffer alignment 2 beyond a 16 byte boundary
4036 * this will result in a 16 byte aligned IP header after
4037 * the 14 byte MAC header is removed
4038 */
4039 skb_reserve(skb, NET_IP_ALIGN);
4040
4041 buffer_info->skb = skb;
4042 buffer_info->dma = pci_map_single(pdev, skb->data,
4043 bufsz,
4044 PCI_DMA_FROMDEVICE);
4045
4046 }
4047 /* Refresh the desc even if buffer_addrs didn't change because
4048 * each write-back erases this info. */
4049 if (adapter->rx_ps_hdr_size) {
4050 rx_desc->read.pkt_addr =
4051 cpu_to_le64(buffer_info->page_dma);
4052 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4053 } else {
4054 rx_desc->read.pkt_addr =
4055 cpu_to_le64(buffer_info->dma);
4056 rx_desc->read.hdr_addr = 0;
4057 }
4058
4059 i++;
4060 if (i == rx_ring->count)
4061 i = 0;
4062 buffer_info = &rx_ring->buffer_info[i];
4063 }
4064
4065no_buffers:
4066 if (rx_ring->next_to_use != i) {
4067 rx_ring->next_to_use = i;
4068 if (i == 0)
4069 i = (rx_ring->count - 1);
4070 else
4071 i--;
4072
4073 /* Force memory writes to complete before letting h/w
4074 * know there are new descriptors to fetch. (Only
4075 * applicable for weak-ordered memory model archs,
4076 * such as IA-64). */
4077 wmb();
4078 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4079 }
4080}
4081
4082/**
4083 * igb_mii_ioctl -
4084 * @netdev:
4085 * @ifreq:
4086 * @cmd:
4087 **/
4088static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4089{
4090 struct igb_adapter *adapter = netdev_priv(netdev);
4091 struct mii_ioctl_data *data = if_mii(ifr);
4092
4093 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4094 return -EOPNOTSUPP;
4095
4096 switch (cmd) {
4097 case SIOCGMIIPHY:
4098 data->phy_id = adapter->hw.phy.addr;
4099 break;
4100 case SIOCGMIIREG:
4101 if (!capable(CAP_NET_ADMIN))
4102 return -EPERM;
f5f4cf08
AD		 4103 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4104 &data->val_out))
9d5c8243
AK		 4105 return -EIO;
4106 break;
4107 case SIOCSMIIREG:
4108 default:
4109 return -EOPNOTSUPP;
4110 }
4111 return 0;
4112}
4113
4114/**
4115 * igb_ioctl -
4116 * @netdev:
4117 * @ifreq:
4118 * @cmd:
4119 **/
4120static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4121{
4122 switch (cmd) {
4123 case SIOCGMIIPHY:
4124 case SIOCGMIIREG:
4125 case SIOCSMIIREG:
4126 return igb_mii_ioctl(netdev, ifr, cmd);
4127 default:
4128 return -EOPNOTSUPP;
4129 }
4130}
4131
4132static void igb_vlan_rx_register(struct net_device *netdev,
4133 struct vlan_group *grp)
4134{
4135 struct igb_adapter *adapter = netdev_priv(netdev);
4136 struct e1000_hw *hw = &adapter->hw;
4137 u32 ctrl, rctl;
4138
4139 igb_irq_disable(adapter);
4140 adapter->vlgrp = grp;
4141
4142 if (grp) {
4143 /* enable VLAN tag insert/strip */
4144 ctrl = rd32(E1000_CTRL);
4145 ctrl |= E1000_CTRL_VME;
4146 wr32(E1000_CTRL, ctrl);
4147
4148 /* enable VLAN receive filtering */
4149 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4150 rctl &= ~E1000_RCTL_CFIEN;
4151 wr32(E1000_RCTL, rctl);
4152 igb_update_mng_vlan(adapter);
4153 wr32(E1000_RLPML,
4154 adapter->max_frame_size + VLAN_TAG_SIZE);
4155 } else {
4156 /* disable VLAN tag insert/strip */
4157 ctrl = rd32(E1000_CTRL);
4158 ctrl &= ~E1000_CTRL_VME;
4159 wr32(E1000_CTRL, ctrl);
4160
9d5c8243
AK		 4161 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4162 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4163 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4164 }
4165 wr32(E1000_RLPML,
4166 adapter->max_frame_size);
4167 }
4168
4169 if (!test_bit(__IGB_DOWN, &adapter->state))
4170 igb_irq_enable(adapter);
4171}
4172
4173static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4174{
4175 struct igb_adapter *adapter = netdev_priv(netdev);
4176 struct e1000_hw *hw = &adapter->hw;
4177 u32 vfta, index;
4178
4179 if ((adapter->hw.mng_cookie.status &
4180 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4181 (vid == adapter->mng_vlan_id))
4182 return;
4183 /* add VID to filter table */
4184 index = (vid >> 5) & 0x7F;
4185 vfta = array_rd32(E1000_VFTA, index);
4186 vfta |= (1 << (vid & 0x1F));
4187 igb_write_vfta(&adapter->hw, index, vfta);
4188}
4189
4190static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4191{
4192 struct igb_adapter *adapter = netdev_priv(netdev);
4193 struct e1000_hw *hw = &adapter->hw;
4194 u32 vfta, index;
4195
4196 igb_irq_disable(adapter);
4197 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4198
4199 if (!test_bit(__IGB_DOWN, &adapter->state))
4200 igb_irq_enable(adapter);
4201
4202 if ((adapter->hw.mng_cookie.status &
4203 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4204 (vid == adapter->mng_vlan_id)) {
4205 /* release control to f/w */
4206 igb_release_hw_control(adapter);
4207 return;
4208 }
4209
4210 /* remove VID from filter table */
4211 index = (vid >> 5) & 0x7F;
4212 vfta = array_rd32(E1000_VFTA, index);
4213 vfta &= ~(1 << (vid & 0x1F));
4214 igb_write_vfta(&adapter->hw, index, vfta);
4215}
4216
4217static void igb_restore_vlan(struct igb_adapter *adapter)
4218{
4219 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4220
4221 if (adapter->vlgrp) {
4222 u16 vid;
4223 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4224 if (!vlan_group_get_device(adapter->vlgrp, vid))
4225 continue;
4226 igb_vlan_rx_add_vid(adapter->netdev, vid);
4227 }
4228 }
4229}
4230
4231int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4232{
4233 struct e1000_mac_info *mac = &adapter->hw.mac;
4234
4235 mac->autoneg = 0;
4236
4237 /* Fiber NICs only allow 1000 gbps Full duplex */
4238 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4239 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4240 dev_err(&adapter->pdev->dev,
4241 "Unsupported Speed/Duplex configuration\n");
4242 return -EINVAL;
4243 }
4244
4245 switch (spddplx) {
4246 case SPEED_10 + DUPLEX_HALF:
4247 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4248 break;
4249 case SPEED_10 + DUPLEX_FULL:
4250 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4251 break;
4252 case SPEED_100 + DUPLEX_HALF:
4253 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4254 break;
4255 case SPEED_100 + DUPLEX_FULL:
4256 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4257 break;
4258 case SPEED_1000 + DUPLEX_FULL:
4259 mac->autoneg = 1;
4260 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4261 break;
4262 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4263 default:
4264 dev_err(&adapter->pdev->dev,
4265 "Unsupported Speed/Duplex configuration\n");
4266 return -EINVAL;
4267 }
4268 return 0;
4269}
4270
4271
4272static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4273{
4274 struct net_device *netdev = pci_get_drvdata(pdev);
4275 struct igb_adapter *adapter = netdev_priv(netdev);
4276 struct e1000_hw *hw = &adapter->hw;
2d064c06 4277 u32 ctrl, rctl, status;
9d5c8243
AK		 4278 u32 wufc = adapter->wol;
4279#ifdef CONFIG_PM
4280 int retval = 0;
4281#endif
4282
4283 netif_device_detach(netdev);
4284
a88f10ec
AD		 4285 if (netif_running(netdev))
4286 igb_close(netdev);
4287
4288 igb_reset_interrupt_capability(adapter);
4289
4290 igb_free_queues(adapter);
9d5c8243
AK		 4291
4292#ifdef CONFIG_PM
4293 retval = pci_save_state(pdev);
4294 if (retval)
4295 return retval;
4296#endif
4297
4298 status = rd32(E1000_STATUS);
4299 if (status & E1000_STATUS_LU)
4300 wufc &= ~E1000_WUFC_LNKC;
4301
4302 if (wufc) {
4303 igb_setup_rctl(adapter);
4304 igb_set_multi(netdev);
4305
4306 /* turn on all-multi mode if wake on multicast is enabled */
4307 if (wufc & E1000_WUFC_MC) {
4308 rctl = rd32(E1000_RCTL);
4309 rctl |= E1000_RCTL_MPE;
4310 wr32(E1000_RCTL, rctl);
4311 }
4312
4313 ctrl = rd32(E1000_CTRL);
4314 /* advertise wake from D3Cold */
4315 #define E1000_CTRL_ADVD3WUC 0x00100000
4316 /* phy power management enable */
4317 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4318 ctrl |= E1000_CTRL_ADVD3WUC;
4319 wr32(E1000_CTRL, ctrl);
4320
9d5c8243
AK		 4321 /* Allow time for pending master requests to run */
4322 igb_disable_pcie_master(&adapter->hw);
4323
4324 wr32(E1000_WUC, E1000_WUC_PME_EN);
4325 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4326 } else {
4327 wr32(E1000_WUC, 0);
4328 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4329 }
4330
2d064c06
AD		 4331 /* make sure adapter isn't asleep if manageability/wol is enabled */
4332 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4333 pci_enable_wake(pdev, PCI_D3hot, 1);
4334 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4335 } else {
4336 igb_shutdown_fiber_serdes_link_82575(hw);
4337 pci_enable_wake(pdev, PCI_D3hot, 0);
4338 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4339 }
4340
4341 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4342 * would have already happened in close and is redundant. */
4343 igb_release_hw_control(adapter);
4344
4345 pci_disable_device(pdev);
4346
4347 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4348
4349 return 0;
4350}
4351
4352#ifdef CONFIG_PM
4353static int igb_resume(struct pci_dev *pdev)
4354{
4355 struct net_device *netdev = pci_get_drvdata(pdev);
4356 struct igb_adapter *adapter = netdev_priv(netdev);
4357 struct e1000_hw *hw = &adapter->hw;
4358 u32 err;
4359
4360 pci_set_power_state(pdev, PCI_D0);
4361 pci_restore_state(pdev);
42bfd33a
TI		 4362
4363 if (adapter->need_ioport)
4364 err = pci_enable_device(pdev);
4365 else
4366 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4367 if (err) {
4368 dev_err(&pdev->dev,
4369 "igb: Cannot enable PCI device from suspend\n");
4370 return err;
4371 }
4372 pci_set_master(pdev);
4373
4374 pci_enable_wake(pdev, PCI_D3hot, 0);
4375 pci_enable_wake(pdev, PCI_D3cold, 0);
4376
a88f10ec
AD		 4377 igb_set_interrupt_capability(adapter);
4378
4379 if (igb_alloc_queues(adapter)) {
4380 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4381 return -ENOMEM;
9d5c8243
AK		 4382 }
4383
4384 /* e1000_power_up_phy(adapter); */
4385
4386 igb_reset(adapter);
4387 wr32(E1000_WUS, ~0);
4388
a88f10ec
AD		 4389 if (netif_running(netdev)) {
4390 err = igb_open(netdev);
4391 if (err)
4392 return err;
4393 }
9d5c8243
AK		 4394
4395 netif_device_attach(netdev);
4396
4397 /* let the f/w know that the h/w is now under the control of the
4398 * driver. */
4399 igb_get_hw_control(adapter);
4400
4401 return 0;
4402}
4403#endif
4404
4405static void igb_shutdown(struct pci_dev *pdev)
4406{
4407 igb_suspend(pdev, PMSG_SUSPEND);
4408}
4409
4410#ifdef CONFIG_NET_POLL_CONTROLLER
4411/*
4412 * Polling 'interrupt' - used by things like netconsole to send skbs
4413 * without having to re-enable interrupts. It's not called while
4414 * the interrupt routine is executing.
4415 */
4416static void igb_netpoll(struct net_device *netdev)
4417{
4418 struct igb_adapter *adapter = netdev_priv(netdev);
4419 int i;
4420 int work_done = 0;
4421
4422 igb_irq_disable(adapter);
7dfc16fa
AD		 4423 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4424
9d5c8243 4425 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4426 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4427
4428 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4429 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4430 &work_done,
4431 adapter->rx_ring[i].napi.weight);
4432
7dfc16fa 4433 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4434 igb_irq_enable(adapter);
4435}
4436#endif /* CONFIG_NET_POLL_CONTROLLER */
4437
4438/**
4439 * igb_io_error_detected - called when PCI error is detected
4440 * @pdev: Pointer to PCI device
4441 * @state: The current pci connection state
4442 *
4443 * This function is called after a PCI bus error affecting
4444 * this device has been detected.
4445 */
4446static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4447 pci_channel_state_t state)
4448{
4449 struct net_device *netdev = pci_get_drvdata(pdev);
4450 struct igb_adapter *adapter = netdev_priv(netdev);
4451
4452 netif_device_detach(netdev);
4453
4454 if (netif_running(netdev))
4455 igb_down(adapter);
4456 pci_disable_device(pdev);
4457
4458 /* Request a slot slot reset. */
4459 return PCI_ERS_RESULT_NEED_RESET;
4460}
4461
4462/**
4463 * igb_io_slot_reset - called after the pci bus has been reset.
4464 * @pdev: Pointer to PCI device
4465 *
4466 * Restart the card from scratch, as if from a cold-boot. Implementation
4467 * resembles the first-half of the igb_resume routine.
4468 */
4469static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4470{
4471 struct net_device *netdev = pci_get_drvdata(pdev);
4472 struct igb_adapter *adapter = netdev_priv(netdev);
4473 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4474 int err;
9d5c8243 4475
42bfd33a
TI		 4476 if (adapter->need_ioport)
4477 err = pci_enable_device(pdev);
4478 else
4479 err = pci_enable_device_mem(pdev);
4480 if (err) {
9d5c8243
AK		 4481 dev_err(&pdev->dev,
4482 "Cannot re-enable PCI device after reset.\n");
4483 return PCI_ERS_RESULT_DISCONNECT;
4484 }
4485 pci_set_master(pdev);
c682fc23 4486 pci_restore_state(pdev);
9d5c8243
AK		 4487
4488 pci_enable_wake(pdev, PCI_D3hot, 0);
4489 pci_enable_wake(pdev, PCI_D3cold, 0);
4490
4491 igb_reset(adapter);
4492 wr32(E1000_WUS, ~0);
4493
4494 return PCI_ERS_RESULT_RECOVERED;
4495}
4496
4497/**
4498 * igb_io_resume - called when traffic can start flowing again.
4499 * @pdev: Pointer to PCI device
4500 *
4501 * This callback is called when the error recovery driver tells us that
4502 * its OK to resume normal operation. Implementation resembles the
4503 * second-half of the igb_resume routine.
4504 */
4505static void igb_io_resume(struct pci_dev *pdev)
4506{
4507 struct net_device *netdev = pci_get_drvdata(pdev);
4508 struct igb_adapter *adapter = netdev_priv(netdev);
4509
9d5c8243
AK		 4510 if (netif_running(netdev)) {
4511 if (igb_up(adapter)) {
4512 dev_err(&pdev->dev, "igb_up failed after reset\n");
4513 return;
4514 }
4515 }
4516
4517 netif_device_attach(netdev);
4518
4519 /* let the f/w know that the h/w is now under the control of the
4520 * driver. */
4521 igb_get_hw_control(adapter);
4522
4523}
4524
4525/* igb_main.c */
Clone of davem's net-next-2.6 tree