]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/igb/igb_main.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: unused variable warning in igb remove
[net-next-2.6.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
fe4506b6
JC		 44#ifdef CONFIG_DCA
45#include <linux/dca.h>
46#endif
9d5c8243
AK		 47#include "igb.h"
48
0024fd00 49#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 50char igb_driver_name[] = "igb";
51char igb_driver_version[] = DRV_VERSION;
52static const char igb_driver_string[] =
53 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 54static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 55
9d5c8243
AK		 56static const struct e1000_info *igb_info_tbl[] = {
57 [board_82575] = &e1000_82575_info,
58};
59
60static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
68 /* required last entry */
69 {0, }
70};
71
72MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
73
74void igb_reset(struct igb_adapter *);
75static int igb_setup_all_tx_resources(struct igb_adapter *);
76static int igb_setup_all_rx_resources(struct igb_adapter *);
77static void igb_free_all_tx_resources(struct igb_adapter *);
78static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 79static void igb_free_tx_resources(struct igb_ring *);
80static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
fe4506b6
JC		 110#ifdef CONFIG_DCA
111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
114#endif /* CONFIG_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
d3352520
AD		 119#ifdef CONFIG_IGB_LRO
120static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
121#endif
9d5c8243
AK		 122static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
123static void igb_tx_timeout(struct net_device *);
124static void igb_reset_task(struct work_struct *);
125static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
126static void igb_vlan_rx_add_vid(struct net_device *, u16);
127static void igb_vlan_rx_kill_vid(struct net_device *, u16);
128static void igb_restore_vlan(struct igb_adapter *);
129
130static int igb_suspend(struct pci_dev *, pm_message_t);
131#ifdef CONFIG_PM
132static int igb_resume(struct pci_dev *);
133#endif
134static void igb_shutdown(struct pci_dev *);
fe4506b6
JC		 135#ifdef CONFIG_DCA
136static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
137static struct notifier_block dca_notifier = {
138 .notifier_call = igb_notify_dca,
139 .next = NULL,
140 .priority = 0
141};
142#endif
9d5c8243
AK		 143
144#ifdef CONFIG_NET_POLL_CONTROLLER
145/* for netdump / net console */
146static void igb_netpoll(struct net_device *);
147#endif
148
149static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
150 pci_channel_state_t);
151static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
152static void igb_io_resume(struct pci_dev *);
153
154static struct pci_error_handlers igb_err_handler = {
155 .error_detected = igb_io_error_detected,
156 .slot_reset = igb_io_slot_reset,
157 .resume = igb_io_resume,
158};
159
160
161static struct pci_driver igb_driver = {
162 .name = igb_driver_name,
163 .id_table = igb_pci_tbl,
164 .probe = igb_probe,
165 .remove = __devexit_p(igb_remove),
166#ifdef CONFIG_PM
167 /* Power Managment Hooks */
168 .suspend = igb_suspend,
169 .resume = igb_resume,
170#endif
171 .shutdown = igb_shutdown,
172 .err_handler = &igb_err_handler
173};
174
7dfc16fa
AD		 175static int global_quad_port_a; /* global quad port a indication */
176
9d5c8243
AK		 177MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
178MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
179MODULE_LICENSE("GPL");
180MODULE_VERSION(DRV_VERSION);
181
182#ifdef DEBUG
183/**
184 * igb_get_hw_dev_name - return device name string
185 * used by hardware layer to print debugging information
186 **/
187char *igb_get_hw_dev_name(struct e1000_hw *hw)
188{
189 struct igb_adapter *adapter = hw->back;
190 return adapter->netdev->name;
191}
192#endif
193
194/**
195 * igb_init_module - Driver Registration Routine
196 *
197 * igb_init_module is the first routine called when the driver is
198 * loaded. All it does is register with the PCI subsystem.
199 **/
200static int __init igb_init_module(void)
201{
202 int ret;
203 printk(KERN_INFO "%s - version %s\n",
204 igb_driver_string, igb_driver_version);
205
206 printk(KERN_INFO "%s\n", igb_copyright);
207
7dfc16fa
AD		 208 global_quad_port_a = 0;
209
9d5c8243 210 ret = pci_register_driver(&igb_driver);
fe4506b6
JC		 211#ifdef CONFIG_DCA
212 dca_register_notify(&dca_notifier);
213#endif
9d5c8243
AK		 214 return ret;
215}
216
217module_init(igb_init_module);
218
219/**
220 * igb_exit_module - Driver Exit Cleanup Routine
221 *
222 * igb_exit_module is called just before the driver is removed
223 * from memory.
224 **/
225static void __exit igb_exit_module(void)
226{
fe4506b6
JC		 227#ifdef CONFIG_DCA
228 dca_unregister_notify(&dca_notifier);
229#endif
9d5c8243
AK		 230 pci_unregister_driver(&igb_driver);
231}
232
233module_exit(igb_exit_module);
234
235/**
236 * igb_alloc_queues - Allocate memory for all rings
237 * @adapter: board private structure to initialize
238 *
239 * We allocate one ring per queue at run-time since we don't know the
240 * number of queues at compile-time.
241 **/
242static int igb_alloc_queues(struct igb_adapter *adapter)
243{
244 int i;
245
246 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
247 sizeof(struct igb_ring), GFP_KERNEL);
248 if (!adapter->tx_ring)
249 return -ENOMEM;
250
251 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
252 sizeof(struct igb_ring), GFP_KERNEL);
253 if (!adapter->rx_ring) {
254 kfree(adapter->tx_ring);
255 return -ENOMEM;
256 }
257
661086df
PWJ		 258 for (i = 0; i < adapter->num_tx_queues; i++) {
259 struct igb_ring *ring = &(adapter->tx_ring[i]);
260 ring->adapter = adapter;
261 ring->queue_index = i;
262 }
9d5c8243
AK		 263 for (i = 0; i < adapter->num_rx_queues; i++) {
264 struct igb_ring *ring = &(adapter->rx_ring[i]);
265 ring->adapter = adapter;
844290e5 266 ring->queue_index = i;
9d5c8243
AK		 267 ring->itr_register = E1000_ITR;
268
844290e5 269 /* set a default napi handler for each rx_ring */
661086df 270 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 271 }
272 return 0;
273}
274
a88f10ec
AD		 275static void igb_free_queues(struct igb_adapter *adapter)
276{
277 int i;
278
279 for (i = 0; i < adapter->num_rx_queues; i++)
280 netif_napi_del(&adapter->rx_ring[i].napi);
281
282 kfree(adapter->tx_ring);
283 kfree(adapter->rx_ring);
284}
285
9d5c8243
AK		 286#define IGB_N0_QUEUE -1
287static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
288 int tx_queue, int msix_vector)
289{
290 u32 msixbm = 0;
291 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 292 u32 ivar, index;
293
294 switch (hw->mac.type) {
295 case e1000_82575:
9d5c8243
AK		 296 /* The 82575 assigns vectors using a bitmask, which matches the
297 bitmask for the EICR/EIMS/EIMC registers. To assign one
298 or more queues to a vector, we write the appropriate bits
299 into the MSIXBM register for that vector. */
300 if (rx_queue > IGB_N0_QUEUE) {
301 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
302 adapter->rx_ring[rx_queue].eims_value = msixbm;
303 }
304 if (tx_queue > IGB_N0_QUEUE) {
305 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
306 adapter->tx_ring[tx_queue].eims_value =
307 E1000_EICR_TX_QUEUE0 << tx_queue;
308 }
309 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 310 break;
311 case e1000_82576:
312 /* Kawela uses a table-based method for assigning vectors.
313 Each queue has a single entry in the table to which we write
314 a vector number along with a "valid" bit. Sadly, the layout
315 of the table is somewhat counterintuitive. */
316 if (rx_queue > IGB_N0_QUEUE) {
317 index = (rx_queue & 0x7);
318 ivar = array_rd32(E1000_IVAR0, index);
319 if (rx_queue < 8) {
320 /* vector goes into low byte of register */
321 ivar = ivar & 0xFFFFFF00;
322 ivar |= msix_vector | E1000_IVAR_VALID;
323 } else {
324 /* vector goes into third byte of register */
325 ivar = ivar & 0xFF00FFFF;
326 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
327 }
328 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
329 array_wr32(E1000_IVAR0, index, ivar);
330 }
331 if (tx_queue > IGB_N0_QUEUE) {
332 index = (tx_queue & 0x7);
333 ivar = array_rd32(E1000_IVAR0, index);
334 if (tx_queue < 8) {
335 /* vector goes into second byte of register */
336 ivar = ivar & 0xFFFF00FF;
337 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
338 } else {
339 /* vector goes into high byte of register */
340 ivar = ivar & 0x00FFFFFF;
341 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
342 }
343 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
344 array_wr32(E1000_IVAR0, index, ivar);
345 }
346 break;
347 default:
348 BUG();
349 break;
350 }
9d5c8243
AK		 351}
352
353/**
354 * igb_configure_msix - Configure MSI-X hardware
355 *
356 * igb_configure_msix sets up the hardware to properly
357 * generate MSI-X interrupts.
358 **/
359static void igb_configure_msix(struct igb_adapter *adapter)
360{
361 u32 tmp;
362 int i, vector = 0;
363 struct e1000_hw *hw = &adapter->hw;
364
365 adapter->eims_enable_mask = 0;
2d064c06
AD		 366 if (hw->mac.type == e1000_82576)
367 /* Turn on MSI-X capability first, or our settings
368 * won't stick. And it will take days to debug. */
369 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
370 E1000_GPIE_PBA | E1000_GPIE_EIAME |
371 E1000_GPIE_NSICR);
9d5c8243
AK		 372
373 for (i = 0; i < adapter->num_tx_queues; i++) {
374 struct igb_ring *tx_ring = &adapter->tx_ring[i];
375 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
376 adapter->eims_enable_mask |= tx_ring->eims_value;
377 if (tx_ring->itr_val)
378 writel(1000000000 / (tx_ring->itr_val * 256),
379 hw->hw_addr + tx_ring->itr_register);
380 else
381 writel(1, hw->hw_addr + tx_ring->itr_register);
382 }
383
384 for (i = 0; i < adapter->num_rx_queues; i++) {
385 struct igb_ring *rx_ring = &adapter->rx_ring[i];
386 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
387 adapter->eims_enable_mask |= rx_ring->eims_value;
388 if (rx_ring->itr_val)
389 writel(1000000000 / (rx_ring->itr_val * 256),
390 hw->hw_addr + rx_ring->itr_register);
391 else
392 writel(1, hw->hw_addr + rx_ring->itr_register);
393 }
394
395
396 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 397 switch (hw->mac.type) {
398 case e1000_82575:
9d5c8243
AK		 399 array_wr32(E1000_MSIXBM(0), vector++,
400 E1000_EIMS_OTHER);
401
9d5c8243
AK		 402 tmp = rd32(E1000_CTRL_EXT);
403 /* enable MSI-X PBA support*/
404 tmp |= E1000_CTRL_EXT_PBA_CLR;
405
406 /* Auto-Mask interrupts upon ICR read. */
407 tmp |= E1000_CTRL_EXT_EIAME;
408 tmp |= E1000_CTRL_EXT_IRCA;
409
410 wr32(E1000_CTRL_EXT, tmp);
411 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 412 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 413
2d064c06
AD		 414 break;
415
416 case e1000_82576:
417 tmp = (vector++ | E1000_IVAR_VALID) << 8;
418 wr32(E1000_IVAR_MISC, tmp);
419
420 adapter->eims_enable_mask = (1 << (vector)) - 1;
421 adapter->eims_other = 1 << (vector - 1);
422 break;
423 default:
424 /* do nothing, since nothing else supports MSI-X */
425 break;
426 } /* switch (hw->mac.type) */
9d5c8243
AK		 427 wrfl();
428}
429
430/**
431 * igb_request_msix - Initialize MSI-X interrupts
432 *
433 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
434 * kernel.
435 **/
436static int igb_request_msix(struct igb_adapter *adapter)
437{
438 struct net_device *netdev = adapter->netdev;
439 int i, err = 0, vector = 0;
440
441 vector = 0;
442
443 for (i = 0; i < adapter->num_tx_queues; i++) {
444 struct igb_ring *ring = &(adapter->tx_ring[i]);
445 sprintf(ring->name, "%s-tx%d", netdev->name, i);
446 err = request_irq(adapter->msix_entries[vector].vector,
447 &igb_msix_tx, 0, ring->name,
448 &(adapter->tx_ring[i]));
449 if (err)
450 goto out;
451 ring->itr_register = E1000_EITR(0) + (vector << 2);
452 ring->itr_val = adapter->itr;
453 vector++;
454 }
455 for (i = 0; i < adapter->num_rx_queues; i++) {
456 struct igb_ring *ring = &(adapter->rx_ring[i]);
457 if (strlen(netdev->name) < (IFNAMSIZ - 5))
458 sprintf(ring->name, "%s-rx%d", netdev->name, i);
459 else
460 memcpy(ring->name, netdev->name, IFNAMSIZ);
461 err = request_irq(adapter->msix_entries[vector].vector,
462 &igb_msix_rx, 0, ring->name,
463 &(adapter->rx_ring[i]));
464 if (err)
465 goto out;
466 ring->itr_register = E1000_EITR(0) + (vector << 2);
467 ring->itr_val = adapter->itr;
844290e5
PW		 468 /* overwrite the poll routine for MSIX, we've already done
469 * netif_napi_add */
470 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 471 vector++;
472 }
473
474 err = request_irq(adapter->msix_entries[vector].vector,
475 &igb_msix_other, 0, netdev->name, netdev);
476 if (err)
477 goto out;
478
9d5c8243
AK		 479 igb_configure_msix(adapter);
480 return 0;
481out:
482 return err;
483}
484
485static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
486{
487 if (adapter->msix_entries) {
488 pci_disable_msix(adapter->pdev);
489 kfree(adapter->msix_entries);
490 adapter->msix_entries = NULL;
7dfc16fa 491 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 492 pci_disable_msi(adapter->pdev);
493 return;
494}
495
496
497/**
498 * igb_set_interrupt_capability - set MSI or MSI-X if supported
499 *
500 * Attempt to configure interrupts using the best available
501 * capabilities of the hardware and kernel.
502 **/
503static void igb_set_interrupt_capability(struct igb_adapter *adapter)
504{
505 int err;
506 int numvecs, i;
507
508 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
509 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
510 GFP_KERNEL);
511 if (!adapter->msix_entries)
512 goto msi_only;
513
514 for (i = 0; i < numvecs; i++)
515 adapter->msix_entries[i].entry = i;
516
517 err = pci_enable_msix(adapter->pdev,
518 adapter->msix_entries,
519 numvecs);
520 if (err == 0)
521 return;
522
523 igb_reset_interrupt_capability(adapter);
524
525 /* If we can't do MSI-X, try MSI */
526msi_only:
527 adapter->num_rx_queues = 1;
661086df 528 adapter->num_tx_queues = 1;
9d5c8243 529 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 530 adapter->flags |= IGB_FLAG_HAS_MSI;
661086df
PWJ		 531
532#ifdef CONFIG_NETDEVICES_MULTIQUEUE
533 /* Notify the stack of the (possibly) reduced Tx Queue count. */
534 adapter->netdev->egress_subqueue_count = adapter->num_tx_queues;
535#endif
9d5c8243
AK		 536 return;
537}
538
539/**
540 * igb_request_irq - initialize interrupts
541 *
542 * Attempts to configure interrupts using the best available
543 * capabilities of the hardware and kernel.
544 **/
545static int igb_request_irq(struct igb_adapter *adapter)
546{
547 struct net_device *netdev = adapter->netdev;
548 struct e1000_hw *hw = &adapter->hw;
549 int err = 0;
550
551 if (adapter->msix_entries) {
552 err = igb_request_msix(adapter);
844290e5 553 if (!err)
9d5c8243 554 goto request_done;
9d5c8243
AK		 555 /* fall back to MSI */
556 igb_reset_interrupt_capability(adapter);
557 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 558 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 559 igb_free_all_tx_resources(adapter);
560 igb_free_all_rx_resources(adapter);
561 adapter->num_rx_queues = 1;
562 igb_alloc_queues(adapter);
844290e5 563 } else {
2d064c06
AD		 564 switch (hw->mac.type) {
565 case e1000_82575:
566 wr32(E1000_MSIXBM(0),
567 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
568 break;
569 case e1000_82576:
570 wr32(E1000_IVAR0, E1000_IVAR_VALID);
571 break;
572 default:
573 break;
574 }
9d5c8243 575 }
844290e5 576
7dfc16fa 577 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 578 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
579 netdev->name, netdev);
580 if (!err)
581 goto request_done;
582 /* fall back to legacy interrupts */
583 igb_reset_interrupt_capability(adapter);
7dfc16fa 584 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 585 }
586
587 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
588 netdev->name, netdev);
589
6cb5e577 590 if (err)
9d5c8243
AK		 591 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
592 err);
9d5c8243
AK		 593
594request_done:
595 return err;
596}
597
598static void igb_free_irq(struct igb_adapter *adapter)
599{
600 struct net_device *netdev = adapter->netdev;
601
602 if (adapter->msix_entries) {
603 int vector = 0, i;
604
605 for (i = 0; i < adapter->num_tx_queues; i++)
606 free_irq(adapter->msix_entries[vector++].vector,
607 &(adapter->tx_ring[i]));
608 for (i = 0; i < adapter->num_rx_queues; i++)
609 free_irq(adapter->msix_entries[vector++].vector,
610 &(adapter->rx_ring[i]));
611
612 free_irq(adapter->msix_entries[vector++].vector, netdev);
613 return;
614 }
615
616 free_irq(adapter->pdev->irq, netdev);
617}
618
619/**
620 * igb_irq_disable - Mask off interrupt generation on the NIC
621 * @adapter: board private structure
622 **/
623static void igb_irq_disable(struct igb_adapter *adapter)
624{
625 struct e1000_hw *hw = &adapter->hw;
626
627 if (adapter->msix_entries) {
844290e5 628 wr32(E1000_EIAM, 0);
9d5c8243
AK		 629 wr32(E1000_EIMC, ~0);
630 wr32(E1000_EIAC, 0);
631 }
844290e5
PW		 632
633 wr32(E1000_IAM, 0);
9d5c8243
AK		 634 wr32(E1000_IMC, ~0);
635 wrfl();
636 synchronize_irq(adapter->pdev->irq);
637}
638
639/**
640 * igb_irq_enable - Enable default interrupt generation settings
641 * @adapter: board private structure
642 **/
643static void igb_irq_enable(struct igb_adapter *adapter)
644{
645 struct e1000_hw *hw = &adapter->hw;
646
647 if (adapter->msix_entries) {
844290e5
PW		 648 wr32(E1000_EIAC, adapter->eims_enable_mask);
649 wr32(E1000_EIAM, adapter->eims_enable_mask);
650 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 651 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 652 } else {
653 wr32(E1000_IMS, IMS_ENABLE_MASK);
654 wr32(E1000_IAM, IMS_ENABLE_MASK);
655 }
9d5c8243
AK		 656}
657
658static void igb_update_mng_vlan(struct igb_adapter *adapter)
659{
660 struct net_device *netdev = adapter->netdev;
661 u16 vid = adapter->hw.mng_cookie.vlan_id;
662 u16 old_vid = adapter->mng_vlan_id;
663 if (adapter->vlgrp) {
664 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
665 if (adapter->hw.mng_cookie.status &
666 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
667 igb_vlan_rx_add_vid(netdev, vid);
668 adapter->mng_vlan_id = vid;
669 } else
670 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
671
672 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
673 (vid != old_vid) &&
674 !vlan_group_get_device(adapter->vlgrp, old_vid))
675 igb_vlan_rx_kill_vid(netdev, old_vid);
676 } else
677 adapter->mng_vlan_id = vid;
678 }
679}
680
681/**
682 * igb_release_hw_control - release control of the h/w to f/w
683 * @adapter: address of board private structure
684 *
685 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
686 * For ASF and Pass Through versions of f/w this means that the
687 * driver is no longer loaded.
688 *
689 **/
690static void igb_release_hw_control(struct igb_adapter *adapter)
691{
692 struct e1000_hw *hw = &adapter->hw;
693 u32 ctrl_ext;
694
695 /* Let firmware take over control of h/w */
696 ctrl_ext = rd32(E1000_CTRL_EXT);
697 wr32(E1000_CTRL_EXT,
698 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
699}
700
701
702/**
703 * igb_get_hw_control - get control of the h/w from f/w
704 * @adapter: address of board private structure
705 *
706 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
707 * For ASF and Pass Through versions of f/w this means that
708 * the driver is loaded.
709 *
710 **/
711static void igb_get_hw_control(struct igb_adapter *adapter)
712{
713 struct e1000_hw *hw = &adapter->hw;
714 u32 ctrl_ext;
715
716 /* Let firmware know the driver has taken over */
717 ctrl_ext = rd32(E1000_CTRL_EXT);
718 wr32(E1000_CTRL_EXT,
719 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
720}
721
722static void igb_init_manageability(struct igb_adapter *adapter)
723{
724 struct e1000_hw *hw = &adapter->hw;
725
726 if (adapter->en_mng_pt) {
727 u32 manc2h = rd32(E1000_MANC2H);
728 u32 manc = rd32(E1000_MANC);
729
9d5c8243
AK		 730 /* enable receiving management packets to the host */
731 /* this will probably generate destination unreachable messages
732 * from the host OS, but the packets will be handled on SMBUS */
733 manc |= E1000_MANC_EN_MNG2HOST;
734#define E1000_MNG2HOST_PORT_623 (1 << 5)
735#define E1000_MNG2HOST_PORT_664 (1 << 6)
736 manc2h |= E1000_MNG2HOST_PORT_623;
737 manc2h |= E1000_MNG2HOST_PORT_664;
738 wr32(E1000_MANC2H, manc2h);
739
740 wr32(E1000_MANC, manc);
741 }
742}
743
9d5c8243
AK		 744/**
745 * igb_configure - configure the hardware for RX and TX
746 * @adapter: private board structure
747 **/
748static void igb_configure(struct igb_adapter *adapter)
749{
750 struct net_device *netdev = adapter->netdev;
751 int i;
752
753 igb_get_hw_control(adapter);
754 igb_set_multi(netdev);
755
756 igb_restore_vlan(adapter);
757 igb_init_manageability(adapter);
758
759 igb_configure_tx(adapter);
760 igb_setup_rctl(adapter);
761 igb_configure_rx(adapter);
662d7205
AD		 762
763 igb_rx_fifo_flush_82575(&adapter->hw);
764
9d5c8243
AK		 765 /* call IGB_DESC_UNUSED which always leaves
766 * at least 1 descriptor unused to make sure
767 * next_to_use != next_to_clean */
768 for (i = 0; i < adapter->num_rx_queues; i++) {
769 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 770 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 771 }
772
773
774 adapter->tx_queue_len = netdev->tx_queue_len;
775}
776
777
778/**
779 * igb_up - Open the interface and prepare it to handle traffic
780 * @adapter: board private structure
781 **/
782
783int igb_up(struct igb_adapter *adapter)
784{
785 struct e1000_hw *hw = &adapter->hw;
786 int i;
787
788 /* hardware has been reset, we need to reload some things */
789 igb_configure(adapter);
790
791 clear_bit(__IGB_DOWN, &adapter->state);
792
844290e5
PW		 793 for (i = 0; i < adapter->num_rx_queues; i++)
794 napi_enable(&adapter->rx_ring[i].napi);
795 if (adapter->msix_entries)
9d5c8243 796 igb_configure_msix(adapter);
9d5c8243
AK		 797
798 /* Clear any pending interrupts. */
799 rd32(E1000_ICR);
800 igb_irq_enable(adapter);
801
802 /* Fire a link change interrupt to start the watchdog. */
803 wr32(E1000_ICS, E1000_ICS_LSC);
804 return 0;
805}
806
807void igb_down(struct igb_adapter *adapter)
808{
809 struct e1000_hw *hw = &adapter->hw;
810 struct net_device *netdev = adapter->netdev;
811 u32 tctl, rctl;
812 int i;
813
814 /* signal that we're down so the interrupt handler does not
815 * reschedule our watchdog timer */
816 set_bit(__IGB_DOWN, &adapter->state);
817
818 /* disable receives in the hardware */
819 rctl = rd32(E1000_RCTL);
820 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
821 /* flush and sleep below */
822
823 netif_stop_queue(netdev);
661086df
PWJ		 824#ifdef CONFIG_NETDEVICES_MULTIQUEUE
825 for (i = 0; i < adapter->num_tx_queues; i++)
826 netif_stop_subqueue(netdev, i);
827#endif
9d5c8243
AK		 828
829 /* disable transmits in the hardware */
830 tctl = rd32(E1000_TCTL);
831 tctl &= ~E1000_TCTL_EN;
832 wr32(E1000_TCTL, tctl);
833 /* flush both disables and wait for them to finish */
834 wrfl();
835 msleep(10);
836
844290e5
PW		 837 for (i = 0; i < adapter->num_rx_queues; i++)
838 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 839
9d5c8243
AK		 840 igb_irq_disable(adapter);
841
842 del_timer_sync(&adapter->watchdog_timer);
843 del_timer_sync(&adapter->phy_info_timer);
844
845 netdev->tx_queue_len = adapter->tx_queue_len;
846 netif_carrier_off(netdev);
847 adapter->link_speed = 0;
848 adapter->link_duplex = 0;
849
3023682e
JK		 850 if (!pci_channel_offline(adapter->pdev))
851 igb_reset(adapter);
9d5c8243
AK		 852 igb_clean_all_tx_rings(adapter);
853 igb_clean_all_rx_rings(adapter);
854}
855
856void igb_reinit_locked(struct igb_adapter *adapter)
857{
858 WARN_ON(in_interrupt());
859 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
860 msleep(1);
861 igb_down(adapter);
862 igb_up(adapter);
863 clear_bit(__IGB_RESETTING, &adapter->state);
864}
865
866void igb_reset(struct igb_adapter *adapter)
867{
868 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 869 struct e1000_mac_info *mac = &hw->mac;
870 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 871 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
872 u16 hwm;
873
874 /* Repartition Pba for greater than 9k mtu
875 * To take effect CTRL.RST is required.
876 */
2d064c06 877 if (mac->type != e1000_82576) {
9d5c8243 878 pba = E1000_PBA_34K;
2d064c06
AD		 879 }
880 else {
881 pba = E1000_PBA_64K;
882 }
9d5c8243 883
2d064c06
AD		 884 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
885 (mac->type < e1000_82576)) {
9d5c8243
AK		 886 /* adjust PBA for jumbo frames */
887 wr32(E1000_PBA, pba);
888
889 /* To maintain wire speed transmits, the Tx FIFO should be
890 * large enough to accommodate two full transmit packets,
891 * rounded up to the next 1KB and expressed in KB. Likewise,
892 * the Rx FIFO should be large enough to accommodate at least
893 * one full receive packet and is similarly rounded up and
894 * expressed in KB. */
895 pba = rd32(E1000_PBA);
896 /* upper 16 bits has Tx packet buffer allocation size in KB */
897 tx_space = pba >> 16;
898 /* lower 16 bits has Rx packet buffer allocation size in KB */
899 pba &= 0xffff;
900 /* the tx fifo also stores 16 bytes of information about the tx
901 * but don't include ethernet FCS because hardware appends it */
902 min_tx_space = (adapter->max_frame_size +
903 sizeof(struct e1000_tx_desc) -
904 ETH_FCS_LEN) * 2;
905 min_tx_space = ALIGN(min_tx_space, 1024);
906 min_tx_space >>= 10;
907 /* software strips receive CRC, so leave room for it */
908 min_rx_space = adapter->max_frame_size;
909 min_rx_space = ALIGN(min_rx_space, 1024);
910 min_rx_space >>= 10;
911
912 /* If current Tx allocation is less than the min Tx FIFO size,
913 * and the min Tx FIFO size is less than the current Rx FIFO
914 * allocation, take space away from current Rx allocation */
915 if (tx_space < min_tx_space &&
916 ((min_tx_space - tx_space) < pba)) {
917 pba = pba - (min_tx_space - tx_space);
918
919 /* if short on rx space, rx wins and must trump tx
920 * adjustment */
921 if (pba < min_rx_space)
922 pba = min_rx_space;
923 }
2d064c06 924 wr32(E1000_PBA, pba);
9d5c8243 925 }
9d5c8243
AK		 926
927 /* flow control settings */
928 /* The high water mark must be low enough to fit one full frame
929 * (or the size used for early receive) above it in the Rx FIFO.
930 * Set it to the lower of:
931 * - 90% of the Rx FIFO size, or
932 * - the full Rx FIFO size minus one full frame */
933 hwm = min(((pba << 10) * 9 / 10),
2d064c06 934 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 935
2d064c06
AD		 936 if (mac->type < e1000_82576) {
937 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
938 fc->low_water = fc->high_water - 8;
939 } else {
940 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
941 fc->low_water = fc->high_water - 16;
942 }
9d5c8243
AK		 943 fc->pause_time = 0xFFFF;
944 fc->send_xon = 1;
945 fc->type = fc->original_type;
946
947 /* Allow time for pending master requests to run */
948 adapter->hw.mac.ops.reset_hw(&adapter->hw);
949 wr32(E1000_WUC, 0);
950
951 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
952 dev_err(&adapter->pdev->dev, "Hardware Error\n");
953
954 igb_update_mng_vlan(adapter);
955
956 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
957 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
958
959 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 960 if (adapter->hw.phy.ops.get_phy_info)
961 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 962}
963
42bfd33a
TI		 964/**
965 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
966 * @pdev: PCI device information struct
967 *
968 * Returns true if an adapter needs ioport resources
969 **/
970static int igb_is_need_ioport(struct pci_dev *pdev)
971{
972 switch (pdev->device) {
973 /* Currently there are no adapters that need ioport resources */
974 default:
975 return false;
976 }
977}
978
9d5c8243
AK		 979/**
980 * igb_probe - Device Initialization Routine
981 * @pdev: PCI device information struct
982 * @ent: entry in igb_pci_tbl
983 *
984 * Returns 0 on success, negative on failure
985 *
986 * igb_probe initializes an adapter identified by a pci_dev structure.
987 * The OS initialization, configuring of the adapter private structure,
988 * and a hardware reset occur.
989 **/
990static int __devinit igb_probe(struct pci_dev *pdev,
991 const struct pci_device_id *ent)
992{
993 struct net_device *netdev;
994 struct igb_adapter *adapter;
995 struct e1000_hw *hw;
996 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
997 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 998 int i, err, pci_using_dac;
999 u16 eeprom_data = 0;
1000 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1001 u32 part_num;
42bfd33a 1002 int bars, need_ioport;
9d5c8243 1003
42bfd33a
TI		 1004 /* do not allocate ioport bars when not needed */
1005 need_ioport = igb_is_need_ioport(pdev);
1006 if (need_ioport) {
1007 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1008 err = pci_enable_device(pdev);
1009 } else {
1010 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1011 err = pci_enable_device_mem(pdev);
1012 }
9d5c8243
AK		 1013 if (err)
1014 return err;
1015
1016 pci_using_dac = 0;
1017 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1018 if (!err) {
1019 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1020 if (!err)
1021 pci_using_dac = 1;
1022 } else {
1023 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1024 if (err) {
1025 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1026 if (err) {
1027 dev_err(&pdev->dev, "No usable DMA "
1028 "configuration, aborting\n");
1029 goto err_dma;
1030 }
1031 }
1032 }
1033
42bfd33a 1034 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1035 if (err)
1036 goto err_pci_reg;
1037
1038 pci_set_master(pdev);
c682fc23 1039 pci_save_state(pdev);
9d5c8243
AK		 1040
1041 err = -ENOMEM;
661086df
PWJ		 1042#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1043 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1044#else
9d5c8243 1045 netdev = alloc_etherdev(sizeof(struct igb_adapter));
661086df 1046#endif /* CONFIG_NETDEVICES_MULTIQUEUE */
9d5c8243
AK		 1047 if (!netdev)
1048 goto err_alloc_etherdev;
1049
1050 SET_NETDEV_DEV(netdev, &pdev->dev);
1051
1052 pci_set_drvdata(pdev, netdev);
1053 adapter = netdev_priv(netdev);
1054 adapter->netdev = netdev;
1055 adapter->pdev = pdev;
1056 hw = &adapter->hw;
1057 hw->back = adapter;
1058 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1059 adapter->bars = bars;
1060 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1061
1062 mmio_start = pci_resource_start(pdev, 0);
1063 mmio_len = pci_resource_len(pdev, 0);
1064
1065 err = -EIO;
1066 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1067 if (!adapter->hw.hw_addr)
1068 goto err_ioremap;
1069
1070 netdev->open = &igb_open;
1071 netdev->stop = &igb_close;
1072 netdev->get_stats = &igb_get_stats;
1073 netdev->set_multicast_list = &igb_set_multi;
1074 netdev->set_mac_address = &igb_set_mac;
1075 netdev->change_mtu = &igb_change_mtu;
1076 netdev->do_ioctl = &igb_ioctl;
1077 igb_set_ethtool_ops(netdev);
1078 netdev->tx_timeout = &igb_tx_timeout;
1079 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1080 netdev->vlan_rx_register = igb_vlan_rx_register;
1081 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
1082 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
1083#ifdef CONFIG_NET_POLL_CONTROLLER
1084 netdev->poll_controller = igb_netpoll;
1085#endif
1086 netdev->hard_start_xmit = &igb_xmit_frame_adv;
1087
1088 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1089
1090 netdev->mem_start = mmio_start;
1091 netdev->mem_end = mmio_start + mmio_len;
1092
9d5c8243
AK		 1093 /* PCI config space info */
1094 hw->vendor_id = pdev->vendor;
1095 hw->device_id = pdev->device;
1096 hw->revision_id = pdev->revision;
1097 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1098 hw->subsystem_device_id = pdev->subsystem_device;
1099
1100 /* setup the private structure */
1101 hw->back = adapter;
1102 /* Copy the default MAC, PHY and NVM function pointers */
1103 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1104 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1105 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1106 /* Initialize skew-specific constants */
1107 err = ei->get_invariants(hw);
1108 if (err)
1109 goto err_hw_init;
1110
1111 err = igb_sw_init(adapter);
1112 if (err)
1113 goto err_sw_init;
1114
1115 igb_get_bus_info_pcie(hw);
1116
7dfc16fa
AD		 1117 /* set flags */
1118 switch (hw->mac.type) {
1119 case e1000_82576:
1120 case e1000_82575:
1121 adapter->flags |= IGB_FLAG_HAS_DCA;
1122 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1123 break;
1124 default:
1125 break;
1126 }
1127
9d5c8243
AK		 1128 hw->phy.autoneg_wait_to_complete = false;
1129 hw->mac.adaptive_ifs = true;
1130
1131 /* Copper options */
1132 if (hw->phy.media_type == e1000_media_type_copper) {
1133 hw->phy.mdix = AUTO_ALL_MODES;
1134 hw->phy.disable_polarity_correction = false;
1135 hw->phy.ms_type = e1000_ms_hw_default;
1136 }
1137
1138 if (igb_check_reset_block(hw))
1139 dev_info(&pdev->dev,
1140 "PHY reset is blocked due to SOL/IDER session.\n");
1141
1142 netdev->features = NETIF_F_SG |
1143 NETIF_F_HW_CSUM |
1144 NETIF_F_HW_VLAN_TX |
1145 NETIF_F_HW_VLAN_RX |
1146 NETIF_F_HW_VLAN_FILTER;
1147
1148 netdev->features |= NETIF_F_TSO;
9d5c8243 1149 netdev->features |= NETIF_F_TSO6;
48f29ffc 1150
d3352520
AD		 1151#ifdef CONFIG_IGB_LRO
1152 netdev->features |= NETIF_F_LRO;
1153#endif
1154
48f29ffc
JK		 1155 netdev->vlan_features |= NETIF_F_TSO;
1156 netdev->vlan_features |= NETIF_F_TSO6;
1157 netdev->vlan_features |= NETIF_F_HW_CSUM;
1158 netdev->vlan_features |= NETIF_F_SG;
1159
9d5c8243
AK		 1160 if (pci_using_dac)
1161 netdev->features |= NETIF_F_HIGHDMA;
1162
661086df
PWJ		 1163#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1164 netdev->features |= NETIF_F_MULTI_QUEUE;
1165#endif
1166
9d5c8243
AK		 1167 netdev->features |= NETIF_F_LLTX;
1168 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1169
1170 /* before reading the NVM, reset the controller to put the device in a
1171 * known good starting state */
1172 hw->mac.ops.reset_hw(hw);
1173
1174 /* make sure the NVM is good */
1175 if (igb_validate_nvm_checksum(hw) < 0) {
1176 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1177 err = -EIO;
1178 goto err_eeprom;
1179 }
1180
1181 /* copy the MAC address out of the NVM */
1182 if (hw->mac.ops.read_mac_addr(hw))
1183 dev_err(&pdev->dev, "NVM Read Error\n");
1184
1185 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1186 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1187
1188 if (!is_valid_ether_addr(netdev->perm_addr)) {
1189 dev_err(&pdev->dev, "Invalid MAC Address\n");
1190 err = -EIO;
1191 goto err_eeprom;
1192 }
1193
1194 init_timer(&adapter->watchdog_timer);
1195 adapter->watchdog_timer.function = &igb_watchdog;
1196 adapter->watchdog_timer.data = (unsigned long) adapter;
1197
1198 init_timer(&adapter->phy_info_timer);
1199 adapter->phy_info_timer.function = &igb_update_phy_info;
1200 adapter->phy_info_timer.data = (unsigned long) adapter;
1201
1202 INIT_WORK(&adapter->reset_task, igb_reset_task);
1203 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1204
1205 /* Initialize link & ring properties that are user-changeable */
1206 adapter->tx_ring->count = 256;
1207 for (i = 0; i < adapter->num_tx_queues; i++)
1208 adapter->tx_ring[i].count = adapter->tx_ring->count;
1209 adapter->rx_ring->count = 256;
1210 for (i = 0; i < adapter->num_rx_queues; i++)
1211 adapter->rx_ring[i].count = adapter->rx_ring->count;
1212
1213 adapter->fc_autoneg = true;
1214 hw->mac.autoneg = true;
1215 hw->phy.autoneg_advertised = 0x2f;
1216
1217 hw->fc.original_type = e1000_fc_default;
1218 hw->fc.type = e1000_fc_default;
1219
1220 adapter->itr_setting = 3;
1221 adapter->itr = IGB_START_ITR;
1222
1223 igb_validate_mdi_setting(hw);
1224
1225 adapter->rx_csum = 1;
1226
1227 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1228 * enable the ACPI Magic Packet filter
1229 */
1230
1231 if (hw->bus.func == 0 ||
1232 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1233 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1234 &eeprom_data);
1235
1236 if (eeprom_data & eeprom_apme_mask)
1237 adapter->eeprom_wol |= E1000_WUFC_MAG;
1238
1239 /* now that we have the eeprom settings, apply the special cases where
1240 * the eeprom may be wrong or the board simply won't support wake on
1241 * lan on a particular port */
1242 switch (pdev->device) {
1243 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1244 adapter->eeprom_wol = 0;
1245 break;
1246 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1247 case E1000_DEV_ID_82576_FIBER:
1248 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1249 /* Wake events only supported on port A for dual fiber
1250 * regardless of eeprom setting */
1251 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1252 adapter->eeprom_wol = 0;
1253 break;
7dfc16fa
AD		 1254 case E1000_DEV_ID_82576_QUAD_COPPER:
1255 /* if quad port adapter, disable WoL on all but port A */
1256 if (global_quad_port_a != 0)
1257 adapter->eeprom_wol = 0;
1258 else
1259 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1260 /* Reset for multiple quad port adapters */
1261 if (++global_quad_port_a == 4)
1262 global_quad_port_a = 0;
1263 break;
9d5c8243
AK		 1264 }
1265
1266 /* initialize the wol settings based on the eeprom settings */
1267 adapter->wol = adapter->eeprom_wol;
1268
1269 /* reset the hardware with the new settings */
1270 igb_reset(adapter);
1271
1272 /* let the f/w know that the h/w is now under the control of the
1273 * driver. */
1274 igb_get_hw_control(adapter);
1275
1276 /* tell the stack to leave us alone until igb_open() is called */
1277 netif_carrier_off(netdev);
1278 netif_stop_queue(netdev);
661086df
PWJ		 1279#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1280 for (i = 0; i < adapter->num_tx_queues; i++)
1281 netif_stop_subqueue(netdev, i);
1282#endif
9d5c8243
AK		 1283
1284 strcpy(netdev->name, "eth%d");
1285 err = register_netdev(netdev);
1286 if (err)
1287 goto err_register;
1288
fe4506b6 1289#ifdef CONFIG_DCA
7dfc16fa
AD		 1290 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1291 (dca_add_requester(&pdev->dev) == 0)) {
1292 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1293 dev_info(&pdev->dev, "DCA enabled\n");
1294 /* Always use CB2 mode, difference is masked
1295 * in the CB driver. */
1296 wr32(E1000_DCA_CTRL, 2);
1297 igb_setup_dca(adapter);
1298 }
1299#endif
1300
9d5c8243
AK		 1301 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1302 /* print bus type/speed/width info */
1303 dev_info(&pdev->dev,
1304 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1305 netdev->name,
1306 ((hw->bus.speed == e1000_bus_speed_2500)
1307 ? "2.5Gb/s" : "unknown"),
1308 ((hw->bus.width == e1000_bus_width_pcie_x4)
1309 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1310 ? "Width x1" : "unknown"),
1311 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1312 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1313
1314 igb_read_part_num(hw, &part_num);
1315 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1316 (part_num >> 8), (part_num & 0xff));
1317
1318 dev_info(&pdev->dev,
1319 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1320 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1321 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1322 adapter->num_rx_queues, adapter->num_tx_queues);
1323
9d5c8243
AK		 1324 return 0;
1325
1326err_register:
1327 igb_release_hw_control(adapter);
1328err_eeprom:
1329 if (!igb_check_reset_block(hw))
1330 hw->phy.ops.reset_phy(hw);
1331
1332 if (hw->flash_address)
1333 iounmap(hw->flash_address);
1334
1335 igb_remove_device(hw);
a88f10ec 1336 igb_free_queues(adapter);
9d5c8243
AK		 1337err_sw_init:
1338err_hw_init:
1339 iounmap(hw->hw_addr);
1340err_ioremap:
1341 free_netdev(netdev);
1342err_alloc_etherdev:
42bfd33a 1343 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1344err_pci_reg:
1345err_dma:
1346 pci_disable_device(pdev);
1347 return err;
1348}
1349
1350/**
1351 * igb_remove - Device Removal Routine
1352 * @pdev: PCI device information struct
1353 *
1354 * igb_remove is called by the PCI subsystem to alert the driver
1355 * that it should release a PCI device. The could be caused by a
1356 * Hot-Plug event, or because the driver is going to be removed from
1357 * memory.
1358 **/
1359static void __devexit igb_remove(struct pci_dev *pdev)
1360{
1361 struct net_device *netdev = pci_get_drvdata(pdev);
1362 struct igb_adapter *adapter = netdev_priv(netdev);
9280fa52 1363#ifdef CONFIG_DCA
fe4506b6 1364 struct e1000_hw *hw = &adapter->hw;
9280fa52 1365#endif
9d5c8243
AK		 1366
1367 /* flush_scheduled work may reschedule our watchdog task, so
1368 * explicitly disable watchdog tasks from being rescheduled */
1369 set_bit(__IGB_DOWN, &adapter->state);
1370 del_timer_sync(&adapter->watchdog_timer);
1371 del_timer_sync(&adapter->phy_info_timer);
1372
1373 flush_scheduled_work();
1374
fe4506b6 1375#ifdef CONFIG_DCA
7dfc16fa 1376 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1377 dev_info(&pdev->dev, "DCA disabled\n");
1378 dca_remove_requester(&pdev->dev);
7dfc16fa 1379 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1380 wr32(E1000_DCA_CTRL, 1);
1381 }
1382#endif
1383
9d5c8243
AK		 1384 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1385 * would have already happened in close and is redundant. */
1386 igb_release_hw_control(adapter);
1387
1388 unregister_netdev(netdev);
1389
1390 if (!igb_check_reset_block(&adapter->hw))
1391 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1392
1393 igb_remove_device(&adapter->hw);
1394 igb_reset_interrupt_capability(adapter);
1395
a88f10ec 1396 igb_free_queues(adapter);
9d5c8243
AK		 1397
1398 iounmap(adapter->hw.hw_addr);
1399 if (adapter->hw.flash_address)
1400 iounmap(adapter->hw.flash_address);
42bfd33a 1401 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1402
1403 free_netdev(netdev);
1404
1405 pci_disable_device(pdev);
1406}
1407
1408/**
1409 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1410 * @adapter: board private structure to initialize
1411 *
1412 * igb_sw_init initializes the Adapter private data structure.
1413 * Fields are initialized based on PCI device information and
1414 * OS network device settings (MTU size).
1415 **/
1416static int __devinit igb_sw_init(struct igb_adapter *adapter)
1417{
1418 struct e1000_hw *hw = &adapter->hw;
1419 struct net_device *netdev = adapter->netdev;
1420 struct pci_dev *pdev = adapter->pdev;
1421
1422 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1423
1424 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1425 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1426 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1427 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1428
1429 /* Number of supported queues. */
1430 /* Having more queues than CPUs doesn't make sense. */
661086df
PWJ		 1431 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
1432#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1433 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
1434#else
9d5c8243 1435 adapter->num_tx_queues = 1;
661086df 1436#endif /* CONFIG_NET_MULTI_QUEUE_DEVICE */
9d5c8243 1437
661086df
PWJ		 1438 /* This call may decrease the number of queues depending on
1439 * interrupt mode. */
9d5c8243
AK		 1440 igb_set_interrupt_capability(adapter);
1441
1442 if (igb_alloc_queues(adapter)) {
1443 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1444 return -ENOMEM;
1445 }
1446
1447 /* Explicitly disable IRQ since the NIC can be in any state. */
1448 igb_irq_disable(adapter);
1449
1450 set_bit(__IGB_DOWN, &adapter->state);
1451 return 0;
1452}
1453
1454/**
1455 * igb_open - Called when a network interface is made active
1456 * @netdev: network interface device structure
1457 *
1458 * Returns 0 on success, negative value on failure
1459 *
1460 * The open entry point is called when a network interface is made
1461 * active by the system (IFF_UP). At this point all resources needed
1462 * for transmit and receive operations are allocated, the interrupt
1463 * handler is registered with the OS, the watchdog timer is started,
1464 * and the stack is notified that the interface is ready.
1465 **/
1466static int igb_open(struct net_device *netdev)
1467{
1468 struct igb_adapter *adapter = netdev_priv(netdev);
1469 struct e1000_hw *hw = &adapter->hw;
1470 int err;
1471 int i;
1472
1473 /* disallow open during test */
1474 if (test_bit(__IGB_TESTING, &adapter->state))
1475 return -EBUSY;
1476
1477 /* allocate transmit descriptors */
1478 err = igb_setup_all_tx_resources(adapter);
1479 if (err)
1480 goto err_setup_tx;
1481
1482 /* allocate receive descriptors */
1483 err = igb_setup_all_rx_resources(adapter);
1484 if (err)
1485 goto err_setup_rx;
1486
1487 /* e1000_power_up_phy(adapter); */
1488
1489 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1490 if ((adapter->hw.mng_cookie.status &
1491 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1492 igb_update_mng_vlan(adapter);
1493
1494 /* before we allocate an interrupt, we must be ready to handle it.
1495 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1496 * as soon as we call pci_request_irq, so we have to setup our
1497 * clean_rx handler before we do so. */
1498 igb_configure(adapter);
1499
1500 err = igb_request_irq(adapter);
1501 if (err)
1502 goto err_req_irq;
1503
1504 /* From here on the code is the same as igb_up() */
1505 clear_bit(__IGB_DOWN, &adapter->state);
1506
844290e5
PW		 1507 for (i = 0; i < adapter->num_rx_queues; i++)
1508 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1509
1510 /* Clear any pending interrupts. */
1511 rd32(E1000_ICR);
844290e5
PW		 1512
1513 igb_irq_enable(adapter);
1514
9d5c8243
AK		 1515 /* Fire a link status change interrupt to start the watchdog. */
1516 wr32(E1000_ICS, E1000_ICS_LSC);
1517
1518 return 0;
1519
1520err_req_irq:
1521 igb_release_hw_control(adapter);
1522 /* e1000_power_down_phy(adapter); */
1523 igb_free_all_rx_resources(adapter);
1524err_setup_rx:
1525 igb_free_all_tx_resources(adapter);
1526err_setup_tx:
1527 igb_reset(adapter);
1528
1529 return err;
1530}
1531
1532/**
1533 * igb_close - Disables a network interface
1534 * @netdev: network interface device structure
1535 *
1536 * Returns 0, this is not allowed to fail
1537 *
1538 * The close entry point is called when an interface is de-activated
1539 * by the OS. The hardware is still under the driver's control, but
1540 * needs to be disabled. A global MAC reset is issued to stop the
1541 * hardware, and all transmit and receive resources are freed.
1542 **/
1543static int igb_close(struct net_device *netdev)
1544{
1545 struct igb_adapter *adapter = netdev_priv(netdev);
1546
1547 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1548 igb_down(adapter);
1549
1550 igb_free_irq(adapter);
1551
1552 igb_free_all_tx_resources(adapter);
1553 igb_free_all_rx_resources(adapter);
1554
1555 /* kill manageability vlan ID if supported, but not if a vlan with
1556 * the same ID is registered on the host OS (let 8021q kill it) */
1557 if ((adapter->hw.mng_cookie.status &
1558 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1559 !(adapter->vlgrp &&
1560 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1561 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1562
1563 return 0;
1564}
1565
1566/**
1567 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1568 * @adapter: board private structure
1569 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1570 *
1571 * Return 0 on success, negative on failure
1572 **/
1573
1574int igb_setup_tx_resources(struct igb_adapter *adapter,
1575 struct igb_ring *tx_ring)
1576{
1577 struct pci_dev *pdev = adapter->pdev;
1578 int size;
1579
1580 size = sizeof(struct igb_buffer) * tx_ring->count;
1581 tx_ring->buffer_info = vmalloc(size);
1582 if (!tx_ring->buffer_info)
1583 goto err;
1584 memset(tx_ring->buffer_info, 0, size);
1585
1586 /* round up to nearest 4K */
1587 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1588 + sizeof(u32);
1589 tx_ring->size = ALIGN(tx_ring->size, 4096);
1590
1591 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1592 &tx_ring->dma);
1593
1594 if (!tx_ring->desc)
1595 goto err;
1596
1597 tx_ring->adapter = adapter;
1598 tx_ring->next_to_use = 0;
1599 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1600 return 0;
1601
1602err:
1603 vfree(tx_ring->buffer_info);
1604 dev_err(&adapter->pdev->dev,
1605 "Unable to allocate memory for the transmit descriptor ring\n");
1606 return -ENOMEM;
1607}
1608
1609/**
1610 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1611 * (Descriptors) for all queues
1612 * @adapter: board private structure
1613 *
1614 * Return 0 on success, negative on failure
1615 **/
1616static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1617{
1618 int i, err = 0;
661086df
PWJ		 1619#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1620 int r_idx;
1621#endif
9d5c8243
AK		 1622
1623 for (i = 0; i < adapter->num_tx_queues; i++) {
1624 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1625 if (err) {
1626 dev_err(&adapter->pdev->dev,
1627 "Allocation for Tx Queue %u failed\n", i);
1628 for (i--; i >= 0; i--)
3b644cf6 1629 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1630 break;
1631 }
1632 }
1633
661086df
PWJ		 1634#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1635 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1636 r_idx = i % adapter->num_tx_queues;
1637 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1638 }
1639#endif
9d5c8243
AK		 1640 return err;
1641}
1642
1643/**
1644 * igb_configure_tx - Configure transmit Unit after Reset
1645 * @adapter: board private structure
1646 *
1647 * Configure the Tx unit of the MAC after a reset.
1648 **/
1649static void igb_configure_tx(struct igb_adapter *adapter)
1650{
1651 u64 tdba, tdwba;
1652 struct e1000_hw *hw = &adapter->hw;
1653 u32 tctl;
1654 u32 txdctl, txctrl;
1655 int i;
1656
1657 for (i = 0; i < adapter->num_tx_queues; i++) {
1658 struct igb_ring *ring = &(adapter->tx_ring[i]);
1659
1660 wr32(E1000_TDLEN(i),
1661 ring->count * sizeof(struct e1000_tx_desc));
1662 tdba = ring->dma;
1663 wr32(E1000_TDBAL(i),
1664 tdba & 0x00000000ffffffffULL);
1665 wr32(E1000_TDBAH(i), tdba >> 32);
1666
1667 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1668 tdwba |= 1; /* enable head wb */
1669 wr32(E1000_TDWBAL(i),
1670 tdwba & 0x00000000ffffffffULL);
1671 wr32(E1000_TDWBAH(i), tdwba >> 32);
1672
1673 ring->head = E1000_TDH(i);
1674 ring->tail = E1000_TDT(i);
1675 writel(0, hw->hw_addr + ring->tail);
1676 writel(0, hw->hw_addr + ring->head);
1677 txdctl = rd32(E1000_TXDCTL(i));
1678 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1679 wr32(E1000_TXDCTL(i), txdctl);
1680
1681 /* Turn off Relaxed Ordering on head write-backs. The
1682 * writebacks MUST be delivered in order or it will
1683 * completely screw up our bookeeping.
1684 */
1685 txctrl = rd32(E1000_DCA_TXCTRL(i));
1686 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1687 wr32(E1000_DCA_TXCTRL(i), txctrl);
1688 }
1689
1690
1691
1692 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1693
1694 /* Program the Transmit Control Register */
1695
1696 tctl = rd32(E1000_TCTL);
1697 tctl &= ~E1000_TCTL_CT;
1698 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1699 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1700
1701 igb_config_collision_dist(hw);
1702
1703 /* Setup Transmit Descriptor Settings for eop descriptor */
1704 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1705
1706 /* Enable transmits */
1707 tctl |= E1000_TCTL_EN;
1708
1709 wr32(E1000_TCTL, tctl);
1710}
1711
1712/**
1713 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1714 * @adapter: board private structure
1715 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1716 *
1717 * Returns 0 on success, negative on failure
1718 **/
1719
1720int igb_setup_rx_resources(struct igb_adapter *adapter,
1721 struct igb_ring *rx_ring)
1722{
1723 struct pci_dev *pdev = adapter->pdev;
1724 int size, desc_len;
1725
d3352520
AD		 1726#ifdef CONFIG_IGB_LRO
1727 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1728 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1729 if (!rx_ring->lro_mgr.lro_arr)
1730 goto err;
1731 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1732#endif
1733
9d5c8243
AK		 1734 size = sizeof(struct igb_buffer) * rx_ring->count;
1735 rx_ring->buffer_info = vmalloc(size);
1736 if (!rx_ring->buffer_info)
1737 goto err;
1738 memset(rx_ring->buffer_info, 0, size);
1739
1740 desc_len = sizeof(union e1000_adv_rx_desc);
1741
1742 /* Round up to nearest 4K */
1743 rx_ring->size = rx_ring->count * desc_len;
1744 rx_ring->size = ALIGN(rx_ring->size, 4096);
1745
1746 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1747 &rx_ring->dma);
1748
1749 if (!rx_ring->desc)
1750 goto err;
1751
1752 rx_ring->next_to_clean = 0;
1753 rx_ring->next_to_use = 0;
9d5c8243
AK		 1754
1755 rx_ring->adapter = adapter;
9d5c8243
AK		 1756
1757 return 0;
1758
1759err:
d3352520
AD		 1760#ifdef CONFIG_IGB_LRO
1761 vfree(rx_ring->lro_mgr.lro_arr);
1762 rx_ring->lro_mgr.lro_arr = NULL;
1763#endif
9d5c8243
AK		 1764 vfree(rx_ring->buffer_info);
1765 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1766 "the receive descriptor ring\n");
1767 return -ENOMEM;
1768}
1769
1770/**
1771 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1772 * (Descriptors) for all queues
1773 * @adapter: board private structure
1774 *
1775 * Return 0 on success, negative on failure
1776 **/
1777static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1778{
1779 int i, err = 0;
1780
1781 for (i = 0; i < adapter->num_rx_queues; i++) {
1782 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1783 if (err) {
1784 dev_err(&adapter->pdev->dev,
1785 "Allocation for Rx Queue %u failed\n", i);
1786 for (i--; i >= 0; i--)
3b644cf6 1787 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1788 break;
1789 }
1790 }
1791
1792 return err;
1793}
1794
1795/**
1796 * igb_setup_rctl - configure the receive control registers
1797 * @adapter: Board private structure
1798 **/
1799static void igb_setup_rctl(struct igb_adapter *adapter)
1800{
1801 struct e1000_hw *hw = &adapter->hw;
1802 u32 rctl;
1803 u32 srrctl = 0;
1804 int i;
1805
1806 rctl = rd32(E1000_RCTL);
1807
1808 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1809
1810 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1811 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1812 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1813
87cb7e8c
AK		 1814 /*
1815 * enable stripping of CRC. It's unlikely this will break BMC
1816 * redirection as it did with e1000. Newer features require
1817 * that the HW strips the CRC.
9d5c8243 1818 */
87cb7e8c 1819 rctl |= E1000_RCTL_SECRC;
9d5c8243
AK		 1820
1821 rctl &= ~E1000_RCTL_SBP;
1822
1823 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1824 rctl &= ~E1000_RCTL_LPE;
1825 else
1826 rctl |= E1000_RCTL_LPE;
1827 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1828 /* Setup buffer sizes */
1829 rctl &= ~E1000_RCTL_SZ_4096;
1830 rctl |= E1000_RCTL_BSEX;
1831 switch (adapter->rx_buffer_len) {
1832 case IGB_RXBUFFER_256:
1833 rctl |= E1000_RCTL_SZ_256;
1834 rctl &= ~E1000_RCTL_BSEX;
1835 break;
1836 case IGB_RXBUFFER_512:
1837 rctl |= E1000_RCTL_SZ_512;
1838 rctl &= ~E1000_RCTL_BSEX;
1839 break;
1840 case IGB_RXBUFFER_1024:
1841 rctl |= E1000_RCTL_SZ_1024;
1842 rctl &= ~E1000_RCTL_BSEX;
1843 break;
1844 case IGB_RXBUFFER_2048:
1845 default:
1846 rctl |= E1000_RCTL_SZ_2048;
1847 rctl &= ~E1000_RCTL_BSEX;
1848 break;
9d5c8243
AK		 1849 }
1850 } else {
1851 rctl &= ~E1000_RCTL_BSEX;
1852 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1853 }
1854
1855 /* 82575 and greater support packet-split where the protocol
1856 * header is placed in skb->data and the packet data is
1857 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1858 * In the case of a non-split, skb->data is linearly filled,
1859 * followed by the page buffers. Therefore, skb->data is
1860 * sized to hold the largest protocol header.
1861 */
1862 /* allocations using alloc_page take too long for regular MTU
1863 * so only enable packet split for jumbo frames */
1864 if (rctl & E1000_RCTL_LPE) {
1865 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1866 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1867 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1868 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1869 } else {
1870 adapter->rx_ps_hdr_size = 0;
1871 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1872 }
1873
1874 for (i = 0; i < adapter->num_rx_queues; i++)
1875 wr32(E1000_SRRCTL(i), srrctl);
1876
1877 wr32(E1000_RCTL, rctl);
1878}
1879
1880/**
1881 * igb_configure_rx - Configure receive Unit after Reset
1882 * @adapter: board private structure
1883 *
1884 * Configure the Rx unit of the MAC after a reset.
1885 **/
1886static void igb_configure_rx(struct igb_adapter *adapter)
1887{
1888 u64 rdba;
1889 struct e1000_hw *hw = &adapter->hw;
1890 u32 rctl, rxcsum;
1891 u32 rxdctl;
1892 int i;
1893
1894 /* disable receives while setting up the descriptors */
1895 rctl = rd32(E1000_RCTL);
1896 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1897 wrfl();
1898 mdelay(10);
1899
1900 if (adapter->itr_setting > 3)
1901 wr32(E1000_ITR,
1902 1000000000 / (adapter->itr * 256));
1903
1904 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1905 * the Base and Length of the Rx Descriptor Ring */
1906 for (i = 0; i < adapter->num_rx_queues; i++) {
1907 struct igb_ring *ring = &(adapter->rx_ring[i]);
1908 rdba = ring->dma;
1909 wr32(E1000_RDBAL(i),
1910 rdba & 0x00000000ffffffffULL);
1911 wr32(E1000_RDBAH(i), rdba >> 32);
1912 wr32(E1000_RDLEN(i),
1913 ring->count * sizeof(union e1000_adv_rx_desc));
1914
1915 ring->head = E1000_RDH(i);
1916 ring->tail = E1000_RDT(i);
1917 writel(0, hw->hw_addr + ring->tail);
1918 writel(0, hw->hw_addr + ring->head);
1919
1920 rxdctl = rd32(E1000_RXDCTL(i));
1921 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1922 rxdctl &= 0xFFF00000;
1923 rxdctl |= IGB_RX_PTHRESH;
1924 rxdctl |= IGB_RX_HTHRESH << 8;
1925 rxdctl |= IGB_RX_WTHRESH << 16;
1926 wr32(E1000_RXDCTL(i), rxdctl);
d3352520
AD		 1927#ifdef CONFIG_IGB_LRO
1928 /* Intitial LRO Settings */
1929 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1930 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1931 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1932 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1933 ring->lro_mgr.dev = adapter->netdev;
1934 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1935 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1936#endif
9d5c8243
AK		 1937 }
1938
1939 if (adapter->num_rx_queues > 1) {
1940 u32 random[10];
1941 u32 mrqc;
1942 u32 j, shift;
1943 union e1000_reta {
1944 u32 dword;
1945 u8 bytes[4];
1946 } reta;
1947
1948 get_random_bytes(&random[0], 40);
1949
2d064c06
AD		 1950 if (hw->mac.type >= e1000_82576)
1951 shift = 0;
1952 else
1953 shift = 6;
9d5c8243
AK		 1954 for (j = 0; j < (32 * 4); j++) {
1955 reta.bytes[j & 3] =
1956 (j % adapter->num_rx_queues) << shift;
1957 if ((j & 3) == 3)
1958 writel(reta.dword,
1959 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1960 }
1961 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1962
1963 /* Fill out hash function seeds */
1964 for (j = 0; j < 10; j++)
1965 array_wr32(E1000_RSSRK(0), j, random[j]);
1966
1967 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1968 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1969 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1970 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1971 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1972 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1973 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1974 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1975
1976
1977 wr32(E1000_MRQC, mrqc);
1978
1979 /* Multiqueue and raw packet checksumming are mutually
1980 * exclusive. Note that this not the same as TCP/IP
1981 * checksumming, which works fine. */
1982 rxcsum = rd32(E1000_RXCSUM);
1983 rxcsum |= E1000_RXCSUM_PCSD;
1984 wr32(E1000_RXCSUM, rxcsum);
1985 } else {
1986 /* Enable Receive Checksum Offload for TCP and UDP */
1987 rxcsum = rd32(E1000_RXCSUM);
1988 if (adapter->rx_csum) {
1989 rxcsum |= E1000_RXCSUM_TUOFL;
1990
1991 /* Enable IPv4 payload checksum for UDP fragments
1992 * Must be used in conjunction with packet-split. */
1993 if (adapter->rx_ps_hdr_size)
1994 rxcsum |= E1000_RXCSUM_IPPCSE;
1995 } else {
1996 rxcsum &= ~E1000_RXCSUM_TUOFL;
1997 /* don't need to clear IPPCSE as it defaults to 0 */
1998 }
1999 wr32(E1000_RXCSUM, rxcsum);
2000 }
2001
2002 if (adapter->vlgrp)
2003 wr32(E1000_RLPML,
2004 adapter->max_frame_size + VLAN_TAG_SIZE);
2005 else
2006 wr32(E1000_RLPML, adapter->max_frame_size);
2007
2008 /* Enable Receives */
2009 wr32(E1000_RCTL, rctl);
2010}
2011
2012/**
2013 * igb_free_tx_resources - Free Tx Resources per Queue
2014 * @adapter: board private structure
2015 * @tx_ring: Tx descriptor ring for a specific queue
2016 *
2017 * Free all transmit software resources
2018 **/
3b644cf6 2019static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2020{
3b644cf6 2021 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2022
3b644cf6 2023 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2024
2025 vfree(tx_ring->buffer_info);
2026 tx_ring->buffer_info = NULL;
2027
2028 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2029
2030 tx_ring->desc = NULL;
2031}
2032
2033/**
2034 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2035 * @adapter: board private structure
2036 *
2037 * Free all transmit software resources
2038 **/
2039static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2040{
2041 int i;
2042
2043 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2044 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2045}
2046
2047static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2048 struct igb_buffer *buffer_info)
2049{
2050 if (buffer_info->dma) {
2051 pci_unmap_page(adapter->pdev,
2052 buffer_info->dma,
2053 buffer_info->length,
2054 PCI_DMA_TODEVICE);
2055 buffer_info->dma = 0;
2056 }
2057 if (buffer_info->skb) {
2058 dev_kfree_skb_any(buffer_info->skb);
2059 buffer_info->skb = NULL;
2060 }
2061 buffer_info->time_stamp = 0;
2062 /* buffer_info must be completely set up in the transmit path */
2063}
2064
2065/**
2066 * igb_clean_tx_ring - Free Tx Buffers
2067 * @adapter: board private structure
2068 * @tx_ring: ring to be cleaned
2069 **/
3b644cf6 2070static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2071{
3b644cf6 2072 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2073 struct igb_buffer *buffer_info;
2074 unsigned long size;
2075 unsigned int i;
2076
2077 if (!tx_ring->buffer_info)
2078 return;
2079 /* Free all the Tx ring sk_buffs */
2080
2081 for (i = 0; i < tx_ring->count; i++) {
2082 buffer_info = &tx_ring->buffer_info[i];
2083 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2084 }
2085
2086 size = sizeof(struct igb_buffer) * tx_ring->count;
2087 memset(tx_ring->buffer_info, 0, size);
2088
2089 /* Zero out the descriptor ring */
2090
2091 memset(tx_ring->desc, 0, tx_ring->size);
2092
2093 tx_ring->next_to_use = 0;
2094 tx_ring->next_to_clean = 0;
2095
2096 writel(0, adapter->hw.hw_addr + tx_ring->head);
2097 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2098}
2099
2100/**
2101 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2102 * @adapter: board private structure
2103 **/
2104static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2105{
2106 int i;
2107
2108 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2109 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2110}
2111
2112/**
2113 * igb_free_rx_resources - Free Rx Resources
2114 * @adapter: board private structure
2115 * @rx_ring: ring to clean the resources from
2116 *
2117 * Free all receive software resources
2118 **/
3b644cf6 2119static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2120{
3b644cf6 2121 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2122
3b644cf6 2123 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2124
2125 vfree(rx_ring->buffer_info);
2126 rx_ring->buffer_info = NULL;
2127
d3352520
AD		 2128#ifdef CONFIG_IGB_LRO
2129 vfree(rx_ring->lro_mgr.lro_arr);
2130 rx_ring->lro_mgr.lro_arr = NULL;
2131#endif
2132
9d5c8243
AK		 2133 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2134
2135 rx_ring->desc = NULL;
2136}
2137
2138/**
2139 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2140 * @adapter: board private structure
2141 *
2142 * Free all receive software resources
2143 **/
2144static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2145{
2146 int i;
2147
2148 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2149 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2150}
2151
2152/**
2153 * igb_clean_rx_ring - Free Rx Buffers per Queue
2154 * @adapter: board private structure
2155 * @rx_ring: ring to free buffers from
2156 **/
3b644cf6 2157static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2158{
3b644cf6 2159 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2160 struct igb_buffer *buffer_info;
2161 struct pci_dev *pdev = adapter->pdev;
2162 unsigned long size;
2163 unsigned int i;
2164
2165 if (!rx_ring->buffer_info)
2166 return;
2167 /* Free all the Rx ring sk_buffs */
2168 for (i = 0; i < rx_ring->count; i++) {
2169 buffer_info = &rx_ring->buffer_info[i];
2170 if (buffer_info->dma) {
2171 if (adapter->rx_ps_hdr_size)
2172 pci_unmap_single(pdev, buffer_info->dma,
2173 adapter->rx_ps_hdr_size,
2174 PCI_DMA_FROMDEVICE);
2175 else
2176 pci_unmap_single(pdev, buffer_info->dma,
2177 adapter->rx_buffer_len,
2178 PCI_DMA_FROMDEVICE);
2179 buffer_info->dma = 0;
2180 }
2181
2182 if (buffer_info->skb) {
2183 dev_kfree_skb(buffer_info->skb);
2184 buffer_info->skb = NULL;
2185 }
2186 if (buffer_info->page) {
bf36c1a0
AD		 2187 if (buffer_info->page_dma)
2188 pci_unmap_page(pdev, buffer_info->page_dma,
2189 PAGE_SIZE / 2,
2190 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2191 put_page(buffer_info->page);
2192 buffer_info->page = NULL;
2193 buffer_info->page_dma = 0;
bf36c1a0 2194 buffer_info->page_offset = 0;
9d5c8243
AK		 2195 }
2196 }
2197
9d5c8243
AK		 2198 size = sizeof(struct igb_buffer) * rx_ring->count;
2199 memset(rx_ring->buffer_info, 0, size);
2200
2201 /* Zero out the descriptor ring */
2202 memset(rx_ring->desc, 0, rx_ring->size);
2203
2204 rx_ring->next_to_clean = 0;
2205 rx_ring->next_to_use = 0;
2206
2207 writel(0, adapter->hw.hw_addr + rx_ring->head);
2208 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2209}
2210
2211/**
2212 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2213 * @adapter: board private structure
2214 **/
2215static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2216{
2217 int i;
2218
2219 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2220 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2221}
2222
2223/**
2224 * igb_set_mac - Change the Ethernet Address of the NIC
2225 * @netdev: network interface device structure
2226 * @p: pointer to an address structure
2227 *
2228 * Returns 0 on success, negative on failure
2229 **/
2230static int igb_set_mac(struct net_device *netdev, void *p)
2231{
2232 struct igb_adapter *adapter = netdev_priv(netdev);
2233 struct sockaddr *addr = p;
2234
2235 if (!is_valid_ether_addr(addr->sa_data))
2236 return -EADDRNOTAVAIL;
2237
2238 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2239 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2240
2241 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2242
2243 return 0;
2244}
2245
2246/**
2247 * igb_set_multi - Multicast and Promiscuous mode set
2248 * @netdev: network interface device structure
2249 *
2250 * The set_multi entry point is called whenever the multicast address
2251 * list or the network interface flags are updated. This routine is
2252 * responsible for configuring the hardware for proper multicast,
2253 * promiscuous mode, and all-multi behavior.
2254 **/
2255static void igb_set_multi(struct net_device *netdev)
2256{
2257 struct igb_adapter *adapter = netdev_priv(netdev);
2258 struct e1000_hw *hw = &adapter->hw;
2259 struct e1000_mac_info *mac = &hw->mac;
2260 struct dev_mc_list *mc_ptr;
2261 u8 *mta_list;
2262 u32 rctl;
2263 int i;
2264
2265 /* Check for Promiscuous and All Multicast modes */
2266
2267 rctl = rd32(E1000_RCTL);
2268
2269 if (netdev->flags & IFF_PROMISC)
2270 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2271 else if (netdev->flags & IFF_ALLMULTI) {
2272 rctl |= E1000_RCTL_MPE;
2273 rctl &= ~E1000_RCTL_UPE;
2274 } else
2275 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2276
2277 wr32(E1000_RCTL, rctl);
2278
2279 if (!netdev->mc_count) {
2280 /* nothing to program, so clear mc list */
2d064c06 2281 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2282 mac->rar_entry_count);
2283 return;
2284 }
2285
2286 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2287 if (!mta_list)
2288 return;
2289
2290 /* The shared function expects a packed array of only addresses. */
2291 mc_ptr = netdev->mc_list;
2292
2293 for (i = 0; i < netdev->mc_count; i++) {
2294 if (!mc_ptr)
2295 break;
2296 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2297 mc_ptr = mc_ptr->next;
2298 }
2d064c06
AD		 2299 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2300 mac->rar_entry_count);
9d5c8243
AK		 2301 kfree(mta_list);
2302}
2303
2304/* Need to wait a few seconds after link up to get diagnostic information from
2305 * the phy */
2306static void igb_update_phy_info(unsigned long data)
2307{
2308 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2309 if (adapter->hw.phy.ops.get_phy_info)
2310 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2311}
2312
2313/**
2314 * igb_watchdog - Timer Call-back
2315 * @data: pointer to adapter cast into an unsigned long
2316 **/
2317static void igb_watchdog(unsigned long data)
2318{
2319 struct igb_adapter *adapter = (struct igb_adapter *)data;
2320 /* Do the rest outside of interrupt context */
2321 schedule_work(&adapter->watchdog_task);
2322}
2323
2324static void igb_watchdog_task(struct work_struct *work)
2325{
2326 struct igb_adapter *adapter = container_of(work,
2327 struct igb_adapter, watchdog_task);
2328 struct e1000_hw *hw = &adapter->hw;
2329
2330 struct net_device *netdev = adapter->netdev;
2331 struct igb_ring *tx_ring = adapter->tx_ring;
2332 struct e1000_mac_info *mac = &adapter->hw.mac;
2333 u32 link;
2334 s32 ret_val;
661086df
PWJ		 2335#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2336 int i;
2337#endif
9d5c8243
AK		 2338
2339 if ((netif_carrier_ok(netdev)) &&
2340 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2341 goto link_up;
2342
2343 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2344 if ((ret_val == E1000_ERR_PHY) &&
2345 (hw->phy.type == e1000_phy_igp_3) &&
2346 (rd32(E1000_CTRL) &
2347 E1000_PHY_CTRL_GBE_DISABLE))
2348 dev_info(&adapter->pdev->dev,
2349 "Gigabit has been disabled, downgrading speed\n");
2350
2351 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2352 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2353 link = mac->serdes_has_link;
2354 else
2355 link = rd32(E1000_STATUS) &
2356 E1000_STATUS_LU;
2357
2358 if (link) {
2359 if (!netif_carrier_ok(netdev)) {
2360 u32 ctrl;
2361 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2362 &adapter->link_speed,
2363 &adapter->link_duplex);
2364
2365 ctrl = rd32(E1000_CTRL);
2366 dev_info(&adapter->pdev->dev,
2367 "NIC Link is Up %d Mbps %s, "
2368 "Flow Control: %s\n",
2369 adapter->link_speed,
2370 adapter->link_duplex == FULL_DUPLEX ?
2371 "Full Duplex" : "Half Duplex",
2372 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2373 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2374 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2375 E1000_CTRL_TFCE) ? "TX" : "None")));
2376
2377 /* tweak tx_queue_len according to speed/duplex and
2378 * adjust the timeout factor */
2379 netdev->tx_queue_len = adapter->tx_queue_len;
2380 adapter->tx_timeout_factor = 1;
2381 switch (adapter->link_speed) {
2382 case SPEED_10:
2383 netdev->tx_queue_len = 10;
2384 adapter->tx_timeout_factor = 14;
2385 break;
2386 case SPEED_100:
2387 netdev->tx_queue_len = 100;
2388 /* maybe add some timeout factor ? */
2389 break;
2390 }
2391
2392 netif_carrier_on(netdev);
2393 netif_wake_queue(netdev);
661086df
PWJ		 2394#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2395 for (i = 0; i < adapter->num_tx_queues; i++)
2396 netif_wake_subqueue(netdev, i);
2397#endif
9d5c8243
AK		 2398
2399 if (!test_bit(__IGB_DOWN, &adapter->state))
2400 mod_timer(&adapter->phy_info_timer,
2401 round_jiffies(jiffies + 2 * HZ));
2402 }
2403 } else {
2404 if (netif_carrier_ok(netdev)) {
2405 adapter->link_speed = 0;
2406 adapter->link_duplex = 0;
2407 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2408 netif_carrier_off(netdev);
2409 netif_stop_queue(netdev);
661086df
PWJ		 2410#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2411 for (i = 0; i < adapter->num_tx_queues; i++)
2412 netif_stop_subqueue(netdev, i);
2413#endif
9d5c8243
AK		 2414 if (!test_bit(__IGB_DOWN, &adapter->state))
2415 mod_timer(&adapter->phy_info_timer,
2416 round_jiffies(jiffies + 2 * HZ));
2417 }
2418 }
2419
2420link_up:
2421 igb_update_stats(adapter);
2422
2423 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2424 adapter->tpt_old = adapter->stats.tpt;
2425 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2426 adapter->colc_old = adapter->stats.colc;
2427
2428 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2429 adapter->gorc_old = adapter->stats.gorc;
2430 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2431 adapter->gotc_old = adapter->stats.gotc;
2432
2433 igb_update_adaptive(&adapter->hw);
2434
2435 if (!netif_carrier_ok(netdev)) {
2436 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2437 /* We've lost link, so the controller stops DMA,
2438 * but we've got queued Tx work that's never going
2439 * to get done, so reset controller to flush Tx.
2440 * (Do the reset outside of interrupt context). */
2441 adapter->tx_timeout_count++;
2442 schedule_work(&adapter->reset_task);
2443 }
2444 }
2445
2446 /* Cause software interrupt to ensure rx ring is cleaned */
2447 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2448
2449 /* Force detection of hung controller every watchdog period */
2450 tx_ring->detect_tx_hung = true;
2451
2452 /* Reset the timer */
2453 if (!test_bit(__IGB_DOWN, &adapter->state))
2454 mod_timer(&adapter->watchdog_timer,
2455 round_jiffies(jiffies + 2 * HZ));
2456}
2457
2458enum latency_range {
2459 lowest_latency = 0,
2460 low_latency = 1,
2461 bulk_latency = 2,
2462 latency_invalid = 255
2463};
2464
2465
2466static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2467 struct igb_ring *rx_ring)
2468{
2469 struct e1000_hw *hw = &adapter->hw;
2470 int new_val;
2471
2472 new_val = rx_ring->itr_val / 2;
2473 if (new_val < IGB_MIN_DYN_ITR)
2474 new_val = IGB_MIN_DYN_ITR;
2475
2476 if (new_val != rx_ring->itr_val) {
2477 rx_ring->itr_val = new_val;
2478 wr32(rx_ring->itr_register,
2479 1000000000 / (new_val * 256));
2480 }
2481}
2482
2483static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2484 struct igb_ring *rx_ring)
2485{
2486 struct e1000_hw *hw = &adapter->hw;
2487 int new_val;
2488
2489 new_val = rx_ring->itr_val * 2;
2490 if (new_val > IGB_MAX_DYN_ITR)
2491 new_val = IGB_MAX_DYN_ITR;
2492
2493 if (new_val != rx_ring->itr_val) {
2494 rx_ring->itr_val = new_val;
2495 wr32(rx_ring->itr_register,
2496 1000000000 / (new_val * 256));
2497 }
2498}
2499
2500/**
2501 * igb_update_itr - update the dynamic ITR value based on statistics
2502 * Stores a new ITR value based on packets and byte
2503 * counts during the last interrupt. The advantage of per interrupt
2504 * computation is faster updates and more accurate ITR for the current
2505 * traffic pattern. Constants in this function were computed
2506 * based on theoretical maximum wire speed and thresholds were set based
2507 * on testing data as well as attempting to minimize response time
2508 * while increasing bulk throughput.
2509 * this functionality is controlled by the InterruptThrottleRate module
2510 * parameter (see igb_param.c)
2511 * NOTE: These calculations are only valid when operating in a single-
2512 * queue environment.
2513 * @adapter: pointer to adapter
2514 * @itr_setting: current adapter->itr
2515 * @packets: the number of packets during this measurement interval
2516 * @bytes: the number of bytes during this measurement interval
2517 **/
2518static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2519 int packets, int bytes)
2520{
2521 unsigned int retval = itr_setting;
2522
2523 if (packets == 0)
2524 goto update_itr_done;
2525
2526 switch (itr_setting) {
2527 case lowest_latency:
2528 /* handle TSO and jumbo frames */
2529 if (bytes/packets > 8000)
2530 retval = bulk_latency;
2531 else if ((packets < 5) && (bytes > 512))
2532 retval = low_latency;
2533 break;
2534 case low_latency: /* 50 usec aka 20000 ints/s */
2535 if (bytes > 10000) {
2536 /* this if handles the TSO accounting */
2537 if (bytes/packets > 8000) {
2538 retval = bulk_latency;
2539 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2540 retval = bulk_latency;
2541 } else if ((packets > 35)) {
2542 retval = lowest_latency;
2543 }
2544 } else if (bytes/packets > 2000) {
2545 retval = bulk_latency;
2546 } else if (packets <= 2 && bytes < 512) {
2547 retval = lowest_latency;
2548 }
2549 break;
2550 case bulk_latency: /* 250 usec aka 4000 ints/s */
2551 if (bytes > 25000) {
2552 if (packets > 35)
2553 retval = low_latency;
2554 } else if (bytes < 6000) {
2555 retval = low_latency;
2556 }
2557 break;
2558 }
2559
2560update_itr_done:
2561 return retval;
2562}
2563
2564static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2565 int rx_only)
2566{
2567 u16 current_itr;
2568 u32 new_itr = adapter->itr;
2569
2570 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2571 if (adapter->link_speed != SPEED_1000) {
2572 current_itr = 0;
2573 new_itr = 4000;
2574 goto set_itr_now;
2575 }
2576
2577 adapter->rx_itr = igb_update_itr(adapter,
2578 adapter->rx_itr,
2579 adapter->rx_ring->total_packets,
2580 adapter->rx_ring->total_bytes);
2581 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2582 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2583 adapter->rx_itr = low_latency;
2584
2585 if (!rx_only) {
2586 adapter->tx_itr = igb_update_itr(adapter,
2587 adapter->tx_itr,
2588 adapter->tx_ring->total_packets,
2589 adapter->tx_ring->total_bytes);
2590 /* conservative mode (itr 3) eliminates the
2591 * lowest_latency setting */
2592 if (adapter->itr_setting == 3 &&
2593 adapter->tx_itr == lowest_latency)
2594 adapter->tx_itr = low_latency;
2595
2596 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2597 } else {
2598 current_itr = adapter->rx_itr;
2599 }
2600
2601 switch (current_itr) {
2602 /* counts and packets in update_itr are dependent on these numbers */
2603 case lowest_latency:
2604 new_itr = 70000;
2605 break;
2606 case low_latency:
2607 new_itr = 20000; /* aka hwitr = ~200 */
2608 break;
2609 case bulk_latency:
2610 new_itr = 4000;
2611 break;
2612 default:
2613 break;
2614 }
2615
2616set_itr_now:
2617 if (new_itr != adapter->itr) {
2618 /* this attempts to bias the interrupt rate towards Bulk
2619 * by adding intermediate steps when interrupt rate is
2620 * increasing */
2621 new_itr = new_itr > adapter->itr ?
2622 min(adapter->itr + (new_itr >> 2), new_itr) :
2623 new_itr;
2624 /* Don't write the value here; it resets the adapter's
2625 * internal timer, and causes us to delay far longer than
2626 * we should between interrupts. Instead, we write the ITR
2627 * value at the beginning of the next interrupt so the timing
2628 * ends up being correct.
2629 */
2630 adapter->itr = new_itr;
2631 adapter->set_itr = 1;
2632 }
2633
2634 return;
2635}
2636
2637
2638#define IGB_TX_FLAGS_CSUM 0x00000001
2639#define IGB_TX_FLAGS_VLAN 0x00000002
2640#define IGB_TX_FLAGS_TSO 0x00000004
2641#define IGB_TX_FLAGS_IPV4 0x00000008
2642#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2643#define IGB_TX_FLAGS_VLAN_SHIFT 16
2644
2645static inline int igb_tso_adv(struct igb_adapter *adapter,
2646 struct igb_ring *tx_ring,
2647 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2648{
2649 struct e1000_adv_tx_context_desc *context_desc;
2650 unsigned int i;
2651 int err;
2652 struct igb_buffer *buffer_info;
2653 u32 info = 0, tu_cmd = 0;
2654 u32 mss_l4len_idx, l4len;
2655 *hdr_len = 0;
2656
2657 if (skb_header_cloned(skb)) {
2658 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2659 if (err)
2660 return err;
2661 }
2662
2663 l4len = tcp_hdrlen(skb);
2664 *hdr_len += l4len;
2665
2666 if (skb->protocol == htons(ETH_P_IP)) {
2667 struct iphdr *iph = ip_hdr(skb);
2668 iph->tot_len = 0;
2669 iph->check = 0;
2670 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2671 iph->daddr, 0,
2672 IPPROTO_TCP,
2673 0);
2674 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2675 ipv6_hdr(skb)->payload_len = 0;
2676 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2677 &ipv6_hdr(skb)->daddr,
2678 0, IPPROTO_TCP, 0);
2679 }
2680
2681 i = tx_ring->next_to_use;
2682
2683 buffer_info = &tx_ring->buffer_info[i];
2684 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2685 /* VLAN MACLEN IPLEN */
2686 if (tx_flags & IGB_TX_FLAGS_VLAN)
2687 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2688 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2689 *hdr_len += skb_network_offset(skb);
2690 info |= skb_network_header_len(skb);
2691 *hdr_len += skb_network_header_len(skb);
2692 context_desc->vlan_macip_lens = cpu_to_le32(info);
2693
2694 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2695 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2696
2697 if (skb->protocol == htons(ETH_P_IP))
2698 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2699 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2700
2701 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2702
2703 /* MSS L4LEN IDX */
2704 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2705 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2706
7dfc16fa
AD		 2707 /* Context index must be unique per ring. */
2708 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2709 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2710
2711 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2712 context_desc->seqnum_seed = 0;
2713
2714 buffer_info->time_stamp = jiffies;
2715 buffer_info->dma = 0;
2716 i++;
2717 if (i == tx_ring->count)
2718 i = 0;
2719
2720 tx_ring->next_to_use = i;
2721
2722 return true;
2723}
2724
2725static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2726 struct igb_ring *tx_ring,
2727 struct sk_buff *skb, u32 tx_flags)
2728{
2729 struct e1000_adv_tx_context_desc *context_desc;
2730 unsigned int i;
2731 struct igb_buffer *buffer_info;
2732 u32 info = 0, tu_cmd = 0;
2733
2734 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2735 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2736 i = tx_ring->next_to_use;
2737 buffer_info = &tx_ring->buffer_info[i];
2738 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2739
2740 if (tx_flags & IGB_TX_FLAGS_VLAN)
2741 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2742 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2743 if (skb->ip_summed == CHECKSUM_PARTIAL)
2744 info |= skb_network_header_len(skb);
2745
2746 context_desc->vlan_macip_lens = cpu_to_le32(info);
2747
2748 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2749
2750 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2751 switch (skb->protocol) {
2752 case __constant_htons(ETH_P_IP):
9d5c8243 2753 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2754 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2755 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2756 break;
2757 case __constant_htons(ETH_P_IPV6):
2758 /* XXX what about other V6 headers?? */
2759 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2760 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2761 break;
2762 default:
2763 if (unlikely(net_ratelimit()))
2764 dev_warn(&adapter->pdev->dev,
2765 "partial checksum but proto=%x!\n",
2766 skb->protocol);
2767 break;
2768 }
9d5c8243
AK		 2769 }
2770
2771 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2772 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2773 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2774 context_desc->mss_l4len_idx =
2775 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2776
2777 buffer_info->time_stamp = jiffies;
2778 buffer_info->dma = 0;
2779
2780 i++;
2781 if (i == tx_ring->count)
2782 i = 0;
2783 tx_ring->next_to_use = i;
2784
2785 return true;
2786 }
2787
2788
2789 return false;
2790}
2791
2792#define IGB_MAX_TXD_PWR 16
2793#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2794
2795static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2796 struct igb_ring *tx_ring,
2797 struct sk_buff *skb)
2798{
2799 struct igb_buffer *buffer_info;
2800 unsigned int len = skb_headlen(skb);
2801 unsigned int count = 0, i;
2802 unsigned int f;
2803
2804 i = tx_ring->next_to_use;
2805
2806 buffer_info = &tx_ring->buffer_info[i];
2807 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2808 buffer_info->length = len;
2809 /* set time_stamp *before* dma to help avoid a possible race */
2810 buffer_info->time_stamp = jiffies;
2811 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2812 PCI_DMA_TODEVICE);
2813 count++;
2814 i++;
2815 if (i == tx_ring->count)
2816 i = 0;
2817
2818 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2819 struct skb_frag_struct *frag;
2820
2821 frag = &skb_shinfo(skb)->frags[f];
2822 len = frag->size;
2823
2824 buffer_info = &tx_ring->buffer_info[i];
2825 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2826 buffer_info->length = len;
2827 buffer_info->time_stamp = jiffies;
2828 buffer_info->dma = pci_map_page(adapter->pdev,
2829 frag->page,
2830 frag->page_offset,
2831 len,
2832 PCI_DMA_TODEVICE);
2833
2834 count++;
2835 i++;
2836 if (i == tx_ring->count)
2837 i = 0;
2838 }
2839
2840 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2841 tx_ring->buffer_info[i].skb = skb;
2842
2843 return count;
2844}
2845
2846static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2847 struct igb_ring *tx_ring,
2848 int tx_flags, int count, u32 paylen,
2849 u8 hdr_len)
2850{
2851 union e1000_adv_tx_desc *tx_desc = NULL;
2852 struct igb_buffer *buffer_info;
2853 u32 olinfo_status = 0, cmd_type_len;
2854 unsigned int i;
2855
2856 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2857 E1000_ADVTXD_DCMD_DEXT);
2858
2859 if (tx_flags & IGB_TX_FLAGS_VLAN)
2860 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2861
2862 if (tx_flags & IGB_TX_FLAGS_TSO) {
2863 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2864
2865 /* insert tcp checksum */
2866 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2867
2868 /* insert ip checksum */
2869 if (tx_flags & IGB_TX_FLAGS_IPV4)
2870 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2871
2872 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2873 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2874 }
2875
7dfc16fa
AD		 2876 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2877 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2878 IGB_TX_FLAGS_VLAN)))
661086df 2879 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2880
2881 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2882
2883 i = tx_ring->next_to_use;
2884 while (count--) {
2885 buffer_info = &tx_ring->buffer_info[i];
2886 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2887 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2888 tx_desc->read.cmd_type_len =
2889 cpu_to_le32(cmd_type_len | buffer_info->length);
2890 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2891 i++;
2892 if (i == tx_ring->count)
2893 i = 0;
2894 }
2895
2896 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2897 /* Force memory writes to complete before letting h/w
2898 * know there are new descriptors to fetch. (Only
2899 * applicable for weak-ordered memory model archs,
2900 * such as IA-64). */
2901 wmb();
2902
2903 tx_ring->next_to_use = i;
2904 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2905 /* we need this if more than one processor can write to our tail
2906 * at a time, it syncronizes IO on IA64/Altix systems */
2907 mmiowb();
2908}
2909
2910static int __igb_maybe_stop_tx(struct net_device *netdev,
2911 struct igb_ring *tx_ring, int size)
2912{
2913 struct igb_adapter *adapter = netdev_priv(netdev);
2914
661086df
PWJ		 2915#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2916 netif_stop_subqueue(netdev, tx_ring->queue_index);
2917#else
9d5c8243 2918 netif_stop_queue(netdev);
661086df
PWJ		 2919#endif
2920
9d5c8243
AK		 2921 /* Herbert's original patch had:
2922 * smp_mb__after_netif_stop_queue();
2923 * but since that doesn't exist yet, just open code it. */
2924 smp_mb();
2925
2926 /* We need to check again in a case another CPU has just
2927 * made room available. */
2928 if (IGB_DESC_UNUSED(tx_ring) < size)
2929 return -EBUSY;
2930
2931 /* A reprieve! */
661086df
PWJ		 2932#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2933 netif_wake_subqueue(netdev, tx_ring->queue_index);
2934#else
2935 netif_wake_queue(netdev);
2936#endif
9d5c8243
AK		 2937 ++adapter->restart_queue;
2938 return 0;
2939}
2940
2941static int igb_maybe_stop_tx(struct net_device *netdev,
2942 struct igb_ring *tx_ring, int size)
2943{
2944 if (IGB_DESC_UNUSED(tx_ring) >= size)
2945 return 0;
2946 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2947}
2948
2949#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2950
2951static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2952 struct net_device *netdev,
2953 struct igb_ring *tx_ring)
2954{
2955 struct igb_adapter *adapter = netdev_priv(netdev);
2956 unsigned int tx_flags = 0;
2957 unsigned int len;
9d5c8243
AK		 2958 u8 hdr_len = 0;
2959 int tso = 0;
2960
2961 len = skb_headlen(skb);
2962
2963 if (test_bit(__IGB_DOWN, &adapter->state)) {
2964 dev_kfree_skb_any(skb);
2965 return NETDEV_TX_OK;
2966 }
2967
2968 if (skb->len <= 0) {
2969 dev_kfree_skb_any(skb);
2970 return NETDEV_TX_OK;
2971 }
2972
9d5c8243
AK		 2973 /* need: 1 descriptor per page,
2974 * + 2 desc gap to keep tail from touching head,
2975 * + 1 desc for skb->data,
2976 * + 1 desc for context descriptor,
2977 * otherwise try next time */
2978 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2979 /* this is a hard error */
9d5c8243
AK		 2980 return NETDEV_TX_BUSY;
2981 }
2982
2983 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2984 tx_flags |= IGB_TX_FLAGS_VLAN;
2985 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2986 }
2987
661086df
PWJ		 2988 if (skb->protocol == htons(ETH_P_IP))
2989 tx_flags |= IGB_TX_FLAGS_IPV4;
2990
9d5c8243
AK		 2991 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2992 &hdr_len) : 0;
2993
2994 if (tso < 0) {
2995 dev_kfree_skb_any(skb);
9d5c8243
AK		 2996 return NETDEV_TX_OK;
2997 }
2998
2999 if (tso)
3000 tx_flags |= IGB_TX_FLAGS_TSO;
3001 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3002 if (skb->ip_summed == CHECKSUM_PARTIAL)
3003 tx_flags |= IGB_TX_FLAGS_CSUM;
3004
9d5c8243
AK		 3005 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3006 igb_tx_map_adv(adapter, tx_ring, skb),
3007 skb->len, hdr_len);
3008
3009 netdev->trans_start = jiffies;
3010
3011 /* Make sure there is space in the ring for the next send. */
3012 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3013
9d5c8243
AK		 3014 return NETDEV_TX_OK;
3015}
3016
3017static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3018{
3019 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3020 struct igb_ring *tx_ring;
3021
3022#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3023 int r_idx = 0;
3024 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3025 tx_ring = adapter->multi_tx_table[r_idx];
3026#else
3027 tx_ring = &adapter->tx_ring[0];
3028#endif
3029
9d5c8243
AK		 3030
3031 /* This goes back to the question of how to logically map a tx queue
3032 * to a flow. Right now, performance is impacted slightly negatively
3033 * if using multiple tx queues. If the stack breaks away from a
3034 * single qdisc implementation, we can look at this again. */
3035 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3036}
3037
3038/**
3039 * igb_tx_timeout - Respond to a Tx Hang
3040 * @netdev: network interface device structure
3041 **/
3042static void igb_tx_timeout(struct net_device *netdev)
3043{
3044 struct igb_adapter *adapter = netdev_priv(netdev);
3045 struct e1000_hw *hw = &adapter->hw;
3046
3047 /* Do the reset outside of interrupt context */
3048 adapter->tx_timeout_count++;
3049 schedule_work(&adapter->reset_task);
3050 wr32(E1000_EICS, adapter->eims_enable_mask &
3051 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3052}
3053
3054static void igb_reset_task(struct work_struct *work)
3055{
3056 struct igb_adapter *adapter;
3057 adapter = container_of(work, struct igb_adapter, reset_task);
3058
3059 igb_reinit_locked(adapter);
3060}
3061
3062/**
3063 * igb_get_stats - Get System Network Statistics
3064 * @netdev: network interface device structure
3065 *
3066 * Returns the address of the device statistics structure.
3067 * The statistics are actually updated from the timer callback.
3068 **/
3069static struct net_device_stats *
3070igb_get_stats(struct net_device *netdev)
3071{
3072 struct igb_adapter *adapter = netdev_priv(netdev);
3073
3074 /* only return the current stats */
3075 return &adapter->net_stats;
3076}
3077
3078/**
3079 * igb_change_mtu - Change the Maximum Transfer Unit
3080 * @netdev: network interface device structure
3081 * @new_mtu: new value for maximum frame size
3082 *
3083 * Returns 0 on success, negative on failure
3084 **/
3085static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3086{
3087 struct igb_adapter *adapter = netdev_priv(netdev);
3088 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3089
3090 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3091 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3092 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3093 return -EINVAL;
3094 }
3095
3096#define MAX_STD_JUMBO_FRAME_SIZE 9234
3097 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3098 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3099 return -EINVAL;
3100 }
3101
3102 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3103 msleep(1);
3104 /* igb_down has a dependency on max_frame_size */
3105 adapter->max_frame_size = max_frame;
3106 if (netif_running(netdev))
3107 igb_down(adapter);
3108
3109 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3110 * means we reserve 2 more, this pushes us to allocate from the next
3111 * larger slab size.
3112 * i.e. RXBUFFER_2048 --> size-4096 slab
3113 */
3114
3115 if (max_frame <= IGB_RXBUFFER_256)
3116 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3117 else if (max_frame <= IGB_RXBUFFER_512)
3118 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3119 else if (max_frame <= IGB_RXBUFFER_1024)
3120 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3121 else if (max_frame <= IGB_RXBUFFER_2048)
3122 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3123 else
bf36c1a0
AD		 3124#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3125 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3126#else
3127 adapter->rx_buffer_len = PAGE_SIZE / 2;
3128#endif
9d5c8243
AK		 3129 /* adjust allocation if LPE protects us, and we aren't using SBP */
3130 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3131 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3132 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3133
3134 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3135 netdev->mtu, new_mtu);
3136 netdev->mtu = new_mtu;
3137
3138 if (netif_running(netdev))
3139 igb_up(adapter);
3140 else
3141 igb_reset(adapter);
3142
3143 clear_bit(__IGB_RESETTING, &adapter->state);
3144
3145 return 0;
3146}
3147
3148/**
3149 * igb_update_stats - Update the board statistics counters
3150 * @adapter: board private structure
3151 **/
3152
3153void igb_update_stats(struct igb_adapter *adapter)
3154{
3155 struct e1000_hw *hw = &adapter->hw;
3156 struct pci_dev *pdev = adapter->pdev;
3157 u16 phy_tmp;
3158
3159#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3160
3161 /*
3162 * Prevent stats update while adapter is being reset, or if the pci
3163 * connection is down.
3164 */
3165 if (adapter->link_speed == 0)
3166 return;
3167 if (pci_channel_offline(pdev))
3168 return;
3169
3170 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3171 adapter->stats.gprc += rd32(E1000_GPRC);
3172 adapter->stats.gorc += rd32(E1000_GORCL);
3173 rd32(E1000_GORCH); /* clear GORCL */
3174 adapter->stats.bprc += rd32(E1000_BPRC);
3175 adapter->stats.mprc += rd32(E1000_MPRC);
3176 adapter->stats.roc += rd32(E1000_ROC);
3177
3178 adapter->stats.prc64 += rd32(E1000_PRC64);
3179 adapter->stats.prc127 += rd32(E1000_PRC127);
3180 adapter->stats.prc255 += rd32(E1000_PRC255);
3181 adapter->stats.prc511 += rd32(E1000_PRC511);
3182 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3183 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3184 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3185 adapter->stats.sec += rd32(E1000_SEC);
3186
3187 adapter->stats.mpc += rd32(E1000_MPC);
3188 adapter->stats.scc += rd32(E1000_SCC);
3189 adapter->stats.ecol += rd32(E1000_ECOL);
3190 adapter->stats.mcc += rd32(E1000_MCC);
3191 adapter->stats.latecol += rd32(E1000_LATECOL);
3192 adapter->stats.dc += rd32(E1000_DC);
3193 adapter->stats.rlec += rd32(E1000_RLEC);
3194 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3195 adapter->stats.xontxc += rd32(E1000_XONTXC);
3196 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3197 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3198 adapter->stats.fcruc += rd32(E1000_FCRUC);
3199 adapter->stats.gptc += rd32(E1000_GPTC);
3200 adapter->stats.gotc += rd32(E1000_GOTCL);
3201 rd32(E1000_GOTCH); /* clear GOTCL */
3202 adapter->stats.rnbc += rd32(E1000_RNBC);
3203 adapter->stats.ruc += rd32(E1000_RUC);
3204 adapter->stats.rfc += rd32(E1000_RFC);
3205 adapter->stats.rjc += rd32(E1000_RJC);
3206 adapter->stats.tor += rd32(E1000_TORH);
3207 adapter->stats.tot += rd32(E1000_TOTH);
3208 adapter->stats.tpr += rd32(E1000_TPR);
3209
3210 adapter->stats.ptc64 += rd32(E1000_PTC64);
3211 adapter->stats.ptc127 += rd32(E1000_PTC127);
3212 adapter->stats.ptc255 += rd32(E1000_PTC255);
3213 adapter->stats.ptc511 += rd32(E1000_PTC511);
3214 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3215 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3216
3217 adapter->stats.mptc += rd32(E1000_MPTC);
3218 adapter->stats.bptc += rd32(E1000_BPTC);
3219
3220 /* used for adaptive IFS */
3221
3222 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3223 adapter->stats.tpt += hw->mac.tx_packet_delta;
3224 hw->mac.collision_delta = rd32(E1000_COLC);
3225 adapter->stats.colc += hw->mac.collision_delta;
3226
3227 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3228 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3229 adapter->stats.tncrs += rd32(E1000_TNCRS);
3230 adapter->stats.tsctc += rd32(E1000_TSCTC);
3231 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3232
3233 adapter->stats.iac += rd32(E1000_IAC);
3234 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3235 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3236 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3237 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3238 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3239 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3240 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3241 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3242
3243 /* Fill out the OS statistics structure */
3244 adapter->net_stats.multicast = adapter->stats.mprc;
3245 adapter->net_stats.collisions = adapter->stats.colc;
3246
3247 /* Rx Errors */
3248
3249 /* RLEC on some newer hardware can be incorrect so build
3250 * our own version based on RUC and ROC */
3251 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3252 adapter->stats.crcerrs + adapter->stats.algnerrc +
3253 adapter->stats.ruc + adapter->stats.roc +
3254 adapter->stats.cexterr;
3255 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3256 adapter->stats.roc;
3257 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3258 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3259 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3260
3261 /* Tx Errors */
3262 adapter->net_stats.tx_errors = adapter->stats.ecol +
3263 adapter->stats.latecol;
3264 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3265 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3266 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3267
3268 /* Tx Dropped needs to be maintained elsewhere */
3269
3270 /* Phy Stats */
3271 if (hw->phy.media_type == e1000_media_type_copper) {
3272 if ((adapter->link_speed == SPEED_1000) &&
3273 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3274 &phy_tmp))) {
3275 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3276 adapter->phy_stats.idle_errors += phy_tmp;
3277 }
3278 }
3279
3280 /* Management Stats */
3281 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3282 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3283 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3284}
3285
3286
3287static irqreturn_t igb_msix_other(int irq, void *data)
3288{
3289 struct net_device *netdev = data;
3290 struct igb_adapter *adapter = netdev_priv(netdev);
3291 struct e1000_hw *hw = &adapter->hw;
844290e5 3292 u32 icr = rd32(E1000_ICR);
9d5c8243 3293
844290e5
PW		 3294 /* reading ICR causes bit 31 of EICR to be cleared */
3295 if (!(icr & E1000_ICR_LSC))
3296 goto no_link_interrupt;
3297 hw->mac.get_link_status = 1;
3298 /* guard against interrupt when we're going down */
3299 if (!test_bit(__IGB_DOWN, &adapter->state))
3300 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3301
9d5c8243
AK		 3302no_link_interrupt:
3303 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3304 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3305
3306 return IRQ_HANDLED;
3307}
3308
3309static irqreturn_t igb_msix_tx(int irq, void *data)
3310{
3311 struct igb_ring *tx_ring = data;
3312 struct igb_adapter *adapter = tx_ring->adapter;
3313 struct e1000_hw *hw = &adapter->hw;
3314
3315 if (!tx_ring->itr_val)
3316 wr32(E1000_EIMC, tx_ring->eims_value);
fe4506b6 3317#ifdef CONFIG_DCA
7dfc16fa 3318 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3319 igb_update_tx_dca(tx_ring);
3320#endif
9d5c8243
AK		 3321 tx_ring->total_bytes = 0;
3322 tx_ring->total_packets = 0;
661086df
PWJ		 3323
3324 /* auto mask will automatically reenable the interrupt when we write
3325 * EICS */
3b644cf6 3326 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3327 /* Ring was not completely cleaned, so fire another interrupt */
3328 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3329 else
9d5c8243 3330 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3331
9d5c8243
AK		 3332 return IRQ_HANDLED;
3333}
3334
3335static irqreturn_t igb_msix_rx(int irq, void *data)
3336{
3337 struct igb_ring *rx_ring = data;
3338 struct igb_adapter *adapter = rx_ring->adapter;
3339 struct e1000_hw *hw = &adapter->hw;
3340
844290e5
PW		 3341 /* Write the ITR value calculated at the end of the
3342 * previous interrupt.
3343 */
9d5c8243 3344
844290e5
PW		 3345 if (adapter->set_itr) {
3346 wr32(rx_ring->itr_register,
3347 1000000000 / (rx_ring->itr_val * 256));
3348 adapter->set_itr = 0;
9d5c8243
AK		 3349 }
3350
844290e5
PW		 3351 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3352 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3353
fe4506b6 3354#ifdef CONFIG_DCA
7dfc16fa 3355 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3356 igb_update_rx_dca(rx_ring);
3357#endif
3358 return IRQ_HANDLED;
3359}
3360
3361#ifdef CONFIG_DCA
3362static void igb_update_rx_dca(struct igb_ring *rx_ring)
3363{
3364 u32 dca_rxctrl;
3365 struct igb_adapter *adapter = rx_ring->adapter;
3366 struct e1000_hw *hw = &adapter->hw;
3367 int cpu = get_cpu();
3368 int q = rx_ring - adapter->rx_ring;
3369
3370 if (rx_ring->cpu != cpu) {
3371 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3372 if (hw->mac.type == e1000_82576) {
3373 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3374 dca_rxctrl |= dca_get_tag(cpu) <<
3375 E1000_DCA_RXCTRL_CPUID_SHIFT;
3376 } else {
3377 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3378 dca_rxctrl |= dca_get_tag(cpu);
3379 }
fe4506b6
JC		 3380 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3381 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3382 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3383 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3384 rx_ring->cpu = cpu;
3385 }
3386 put_cpu();
3387}
3388
3389static void igb_update_tx_dca(struct igb_ring *tx_ring)
3390{
3391 u32 dca_txctrl;
3392 struct igb_adapter *adapter = tx_ring->adapter;
3393 struct e1000_hw *hw = &adapter->hw;
3394 int cpu = get_cpu();
3395 int q = tx_ring - adapter->tx_ring;
3396
3397 if (tx_ring->cpu != cpu) {
3398 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3399 if (hw->mac.type == e1000_82576) {
3400 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3401 dca_txctrl |= dca_get_tag(cpu) <<
3402 E1000_DCA_TXCTRL_CPUID_SHIFT;
3403 } else {
3404 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3405 dca_txctrl |= dca_get_tag(cpu);
3406 }
fe4506b6
JC		 3407 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3408 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3409 tx_ring->cpu = cpu;
3410 }
3411 put_cpu();
3412}
3413
3414static void igb_setup_dca(struct igb_adapter *adapter)
3415{
3416 int i;
3417
7dfc16fa 3418 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3419 return;
3420
3421 for (i = 0; i < adapter->num_tx_queues; i++) {
3422 adapter->tx_ring[i].cpu = -1;
3423 igb_update_tx_dca(&adapter->tx_ring[i]);
3424 }
3425 for (i = 0; i < adapter->num_rx_queues; i++) {
3426 adapter->rx_ring[i].cpu = -1;
3427 igb_update_rx_dca(&adapter->rx_ring[i]);
3428 }
3429}
3430
3431static int __igb_notify_dca(struct device *dev, void *data)
3432{
3433 struct net_device *netdev = dev_get_drvdata(dev);
3434 struct igb_adapter *adapter = netdev_priv(netdev);
3435 struct e1000_hw *hw = &adapter->hw;
3436 unsigned long event = *(unsigned long *)data;
3437
7dfc16fa
AD		 3438 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3439 goto out;
3440
fe4506b6
JC		 3441 switch (event) {
3442 case DCA_PROVIDER_ADD:
3443 /* if already enabled, don't do it again */
7dfc16fa 3444 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3445 break;
7dfc16fa 3446 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3447 /* Always use CB2 mode, difference is masked
3448 * in the CB driver. */
3449 wr32(E1000_DCA_CTRL, 2);
3450 if (dca_add_requester(dev) == 0) {
3451 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3452 igb_setup_dca(adapter);
3453 break;
3454 }
3455 /* Fall Through since DCA is disabled. */
3456 case DCA_PROVIDER_REMOVE:
7dfc16fa 3457 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3458 /* without this a class_device is left
3459 * hanging around in the sysfs model */
3460 dca_remove_requester(dev);
3461 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3462 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3463 wr32(E1000_DCA_CTRL, 1);
3464 }
3465 break;
3466 }
7dfc16fa 3467out:
fe4506b6 3468 return 0;
9d5c8243
AK		 3469}
3470
fe4506b6
JC		 3471static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3472 void *p)
3473{
3474 int ret_val;
3475
3476 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3477 __igb_notify_dca);
3478
3479 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3480}
3481#endif /* CONFIG_DCA */
9d5c8243
AK		 3482
3483/**
3484 * igb_intr_msi - Interrupt Handler
3485 * @irq: interrupt number
3486 * @data: pointer to a network interface device structure
3487 **/
3488static irqreturn_t igb_intr_msi(int irq, void *data)
3489{
3490 struct net_device *netdev = data;
3491 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3492 struct e1000_hw *hw = &adapter->hw;
3493 /* read ICR disables interrupts using IAM */
3494 u32 icr = rd32(E1000_ICR);
3495
3496 /* Write the ITR value calculated at the end of the
3497 * previous interrupt.
3498 */
3499 if (adapter->set_itr) {
844290e5 3500 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
9d5c8243
AK		 3501 adapter->set_itr = 0;
3502 }
3503
9d5c8243
AK		 3504 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3505 hw->mac.get_link_status = 1;
3506 if (!test_bit(__IGB_DOWN, &adapter->state))
3507 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3508 }
3509
844290e5 3510 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3511
3512 return IRQ_HANDLED;
3513}
3514
3515/**
3516 * igb_intr - Interrupt Handler
3517 * @irq: interrupt number
3518 * @data: pointer to a network interface device structure
3519 **/
3520static irqreturn_t igb_intr(int irq, void *data)
3521{
3522 struct net_device *netdev = data;
3523 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3524 struct e1000_hw *hw = &adapter->hw;
3525 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3526 * need for the IMC write */
3527 u32 icr = rd32(E1000_ICR);
3528 u32 eicr = 0;
3529 if (!icr)
3530 return IRQ_NONE; /* Not our interrupt */
3531
3532 /* Write the ITR value calculated at the end of the
3533 * previous interrupt.
3534 */
3535 if (adapter->set_itr) {
844290e5 3536 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
9d5c8243
AK		 3537 adapter->set_itr = 0;
3538 }
3539
3540 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3541 * not set, then the adapter didn't send an interrupt */
3542 if (!(icr & E1000_ICR_INT_ASSERTED))
3543 return IRQ_NONE;
3544
3545 eicr = rd32(E1000_EICR);
3546
3547 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3548 hw->mac.get_link_status = 1;
3549 /* guard against interrupt when we're going down */
3550 if (!test_bit(__IGB_DOWN, &adapter->state))
3551 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3552 }
3553
844290e5 3554 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3555
3556 return IRQ_HANDLED;
3557}
3558
3559/**
661086df
PWJ		 3560 * igb_poll - NAPI Rx polling callback
3561 * @napi: napi polling structure
3562 * @budget: count of how many packets we should handle
9d5c8243 3563 **/
661086df 3564static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3565{
661086df
PWJ		 3566 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3567 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3568 struct net_device *netdev = adapter->netdev;
661086df 3569 int tx_clean_complete, work_done = 0;
9d5c8243 3570
661086df 3571 /* this poll routine only supports one tx and one rx queue */
fe4506b6 3572#ifdef CONFIG_DCA
7dfc16fa 3573 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3574 igb_update_tx_dca(&adapter->tx_ring[0]);
3575#endif
661086df 3576 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6
JC		 3577
3578#ifdef CONFIG_DCA
7dfc16fa 3579 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3580 igb_update_rx_dca(&adapter->rx_ring[0]);
3581#endif
661086df 3582 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3583
3584 /* If no Tx and not enough Rx work done, exit the polling mode */
3585 if ((tx_clean_complete && (work_done < budget)) ||
3586 !netif_running(netdev)) {
9d5c8243
AK		 3587 if (adapter->itr_setting & 3)
3588 igb_set_itr(adapter, E1000_ITR, false);
3589 netif_rx_complete(netdev, napi);
3590 if (!test_bit(__IGB_DOWN, &adapter->state))
3591 igb_irq_enable(adapter);
3592 return 0;
3593 }
3594
3595 return 1;
3596}
3597
3598static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3599{
3600 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3601 struct igb_adapter *adapter = rx_ring->adapter;
3602 struct e1000_hw *hw = &adapter->hw;
3603 struct net_device *netdev = adapter->netdev;
3604 int work_done = 0;
3605
3606 /* Keep link state information with original netdev */
3607 if (!netif_carrier_ok(netdev))
3608 goto quit_polling;
3609
fe4506b6 3610#ifdef CONFIG_DCA
7dfc16fa 3611 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3612 igb_update_rx_dca(rx_ring);
3613#endif
3b644cf6 3614 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3615
3616
3617 /* If not enough Rx work done, exit the polling mode */
3618 if ((work_done == 0) || !netif_running(netdev)) {
3619quit_polling:
3620 netif_rx_complete(netdev, napi);
3621
3622 wr32(E1000_EIMS, rx_ring->eims_value);
3623 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3624 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3625 int mean_size = rx_ring->total_bytes /
3626 rx_ring->total_packets;
3627 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3628 igb_raise_rx_eitr(adapter, rx_ring);
3629 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3630 igb_lower_rx_eitr(adapter, rx_ring);
3631 }
844290e5
PW		 3632
3633 if (!test_bit(__IGB_DOWN, &adapter->state))
3634 wr32(E1000_EIMS, rx_ring->eims_value);
3635
9d5c8243
AK		 3636 return 0;
3637 }
3638
3639 return 1;
3640}
6d8126f9
AV		 3641
3642static inline u32 get_head(struct igb_ring *tx_ring)
3643{
3644 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3645 return le32_to_cpu(*(volatile __le32 *)end);
3646}
3647
9d5c8243
AK		 3648/**
3649 * igb_clean_tx_irq - Reclaim resources after transmit completes
3650 * @adapter: board private structure
3651 * returns true if ring is completely cleaned
3652 **/
3b644cf6 3653static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3654{
3b644cf6 3655 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3656 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3657 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3658 struct e1000_tx_desc *tx_desc;
3659 struct igb_buffer *buffer_info;
3660 struct sk_buff *skb;
3661 unsigned int i;
3662 u32 head, oldhead;
3663 unsigned int count = 0;
3664 bool cleaned = false;
3665 bool retval = true;
3666 unsigned int total_bytes = 0, total_packets = 0;
3667
3668 rmb();
6d8126f9 3669 head = get_head(tx_ring);
9d5c8243
AK		 3670 i = tx_ring->next_to_clean;
3671 while (1) {
3672 while (i != head) {
3673 cleaned = true;
3674 tx_desc = E1000_TX_DESC(*tx_ring, i);
3675 buffer_info = &tx_ring->buffer_info[i];
3676 skb = buffer_info->skb;
3677
3678 if (skb) {
3679 unsigned int segs, bytecount;
3680 /* gso_segs is currently only valid for tcp */
3681 segs = skb_shinfo(skb)->gso_segs ?: 1;
3682 /* multiply data chunks by size of headers */
3683 bytecount = ((segs - 1) * skb_headlen(skb)) +
3684 skb->len;
3685 total_packets += segs;
3686 total_bytes += bytecount;
3687 }
3688
3689 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3690 tx_desc->upper.data = 0;
3691
3692 i++;
3693 if (i == tx_ring->count)
3694 i = 0;
3695
3696 count++;
3697 if (count == IGB_MAX_TX_CLEAN) {
3698 retval = false;
3699 goto done_cleaning;
3700 }
3701 }
3702 oldhead = head;
3703 rmb();
6d8126f9 3704 head = get_head(tx_ring);
9d5c8243
AK		 3705 if (head == oldhead)
3706 goto done_cleaning;
3707 } /* while (1) */
3708
3709done_cleaning:
3710 tx_ring->next_to_clean = i;
3711
3712 if (unlikely(cleaned &&
3713 netif_carrier_ok(netdev) &&
3714 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3715 /* Make sure that anybody stopping the queue after this
3716 * sees the new next_to_clean.
3717 */
3718 smp_mb();
661086df
PWJ		 3719#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3720 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3721 !(test_bit(__IGB_DOWN, &adapter->state))) {
3722 netif_wake_subqueue(netdev, tx_ring->queue_index);
3723 ++adapter->restart_queue;
3724 }
3725#else
9d5c8243
AK		 3726 if (netif_queue_stopped(netdev) &&
3727 !(test_bit(__IGB_DOWN, &adapter->state))) {
3728 netif_wake_queue(netdev);
3729 ++adapter->restart_queue;
3730 }
661086df 3731#endif
9d5c8243
AK		 3732 }
3733
3734 if (tx_ring->detect_tx_hung) {
3735 /* Detect a transmit hang in hardware, this serializes the
3736 * check with the clearing of time_stamp and movement of i */
3737 tx_ring->detect_tx_hung = false;
3738 if (tx_ring->buffer_info[i].time_stamp &&
3739 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3740 (adapter->tx_timeout_factor * HZ))
3741 && !(rd32(E1000_STATUS) &
3742 E1000_STATUS_TXOFF)) {
3743
3744 tx_desc = E1000_TX_DESC(*tx_ring, i);
3745 /* detected Tx unit hang */
3746 dev_err(&adapter->pdev->dev,
3747 "Detected Tx Unit Hang\n"
2d064c06 3748 " Tx Queue <%d>\n"
9d5c8243
AK		 3749 " TDH <%x>\n"
3750 " TDT <%x>\n"
3751 " next_to_use <%x>\n"
3752 " next_to_clean <%x>\n"
3753 " head (WB) <%x>\n"
3754 "buffer_info[next_to_clean]\n"
3755 " time_stamp <%lx>\n"
3756 " jiffies <%lx>\n"
3757 " desc.status <%x>\n",
2d064c06 3758 tx_ring->queue_index,
9d5c8243
AK		 3759 readl(adapter->hw.hw_addr + tx_ring->head),
3760 readl(adapter->hw.hw_addr + tx_ring->tail),
3761 tx_ring->next_to_use,
3762 tx_ring->next_to_clean,
3763 head,
3764 tx_ring->buffer_info[i].time_stamp,
3765 jiffies,
3766 tx_desc->upper.fields.status);
661086df
PWJ		 3767#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3768 netif_stop_subqueue(netdev, tx_ring->queue_index);
3769#else
9d5c8243 3770 netif_stop_queue(netdev);
661086df 3771#endif
9d5c8243
AK		 3772 }
3773 }
3774 tx_ring->total_bytes += total_bytes;
3775 tx_ring->total_packets += total_packets;
e21ed353
AD		 3776 tx_ring->tx_stats.bytes += total_bytes;
3777 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3778 adapter->net_stats.tx_bytes += total_bytes;
3779 adapter->net_stats.tx_packets += total_packets;
3780 return retval;
3781}
3782
d3352520
AD		 3783#ifdef CONFIG_IGB_LRO
3784 /**
3785 * igb_get_skb_hdr - helper function for LRO header processing
3786 * @skb: pointer to sk_buff to be added to LRO packet
3787 * @iphdr: pointer to ip header structure
3788 * @tcph: pointer to tcp header structure
3789 * @hdr_flags: pointer to header flags
3790 * @priv: pointer to the receive descriptor for the current sk_buff
3791 **/
3792static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3793 u64 *hdr_flags, void *priv)
3794{
3795 union e1000_adv_rx_desc *rx_desc = priv;
3796 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3797 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3798
3799 /* Verify that this is a valid IPv4 TCP packet */
3800 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3801 E1000_RXDADV_PKTTYPE_TCP))
3802 return -1;
3803
3804 /* Set network headers */
3805 skb_reset_network_header(skb);
3806 skb_set_transport_header(skb, ip_hdrlen(skb));
3807 *iphdr = ip_hdr(skb);
3808 *tcph = tcp_hdr(skb);
3809 *hdr_flags = LRO_IPV4 | LRO_TCP;
3810
3811 return 0;
3812
3813}
3814#endif /* CONFIG_IGB_LRO */
9d5c8243
AK		 3815
3816/**
3817 * igb_receive_skb - helper function to handle rx indications
d3352520 3818 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3819 * @status: descriptor status field as written by hardware
3820 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3821 * @skb: pointer to sk_buff to be indicated to stack
3822 **/
d3352520
AD		 3823static void igb_receive_skb(struct igb_ring *ring, u8 status,
3824 union e1000_adv_rx_desc * rx_desc,
3825 struct sk_buff *skb)
3826{
3827 struct igb_adapter * adapter = ring->adapter;
3828 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3829
3830#ifdef CONFIG_IGB_LRO
3831 if (adapter->netdev->features & NETIF_F_LRO &&
3832 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3833 if (vlan_extracted)
3834 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3835 adapter->vlgrp,
3836 le16_to_cpu(rx_desc->wb.upper.vlan),
3837 rx_desc);
3838 else
3839 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3840 ring->lro_used = 1;
3841 } else {
3842#endif
3843 if (vlan_extracted)
3844 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3845 le16_to_cpu(rx_desc->wb.upper.vlan));
3846 else
3847
3848 netif_receive_skb(skb);
3849#ifdef CONFIG_IGB_LRO
3850 }
3851#endif
9d5c8243
AK		 3852}
3853
3854
3855static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3856 u32 status_err, struct sk_buff *skb)
3857{
3858 skb->ip_summed = CHECKSUM_NONE;
3859
3860 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3861 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3862 return;
3863 /* TCP/UDP checksum error bit is set */
3864 if (status_err &
3865 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3866 /* let the stack verify checksum errors */
3867 adapter->hw_csum_err++;
3868 return;
3869 }
3870 /* It must be a TCP or UDP packet with a valid checksum */
3871 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3872 skb->ip_summed = CHECKSUM_UNNECESSARY;
3873
3874 adapter->hw_csum_good++;
3875}
3876
3b644cf6
MW		 3877static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3878 int *work_done, int budget)
9d5c8243 3879{
3b644cf6 3880 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3881 struct net_device *netdev = adapter->netdev;
3882 struct pci_dev *pdev = adapter->pdev;
3883 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3884 struct igb_buffer *buffer_info , *next_buffer;
3885 struct sk_buff *skb;
bf36c1a0 3886 unsigned int i;
9d5c8243
AK		 3887 u32 length, hlen, staterr;
3888 bool cleaned = false;
3889 int cleaned_count = 0;
3890 unsigned int total_bytes = 0, total_packets = 0;
3891
3892 i = rx_ring->next_to_clean;
3893 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3894 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3895
3896 while (staterr & E1000_RXD_STAT_DD) {
3897 if (*work_done >= budget)
3898 break;
3899 (*work_done)++;
3900 buffer_info = &rx_ring->buffer_info[i];
3901
3902 /* HW will not DMA in data larger than the given buffer, even
3903 * if it parses the (NFS, of course) header to be larger. In
3904 * that case, it fills the header buffer and spills the rest
3905 * into the page.
3906 */
7deb07b1
AV		 3907 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3908 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3909 if (hlen > adapter->rx_ps_hdr_size)
3910 hlen = adapter->rx_ps_hdr_size;
3911
3912 length = le16_to_cpu(rx_desc->wb.upper.length);
3913 cleaned = true;
3914 cleaned_count++;
3915
bf36c1a0
AD		 3916 skb = buffer_info->skb;
3917 prefetch(skb->data - NET_IP_ALIGN);
3918 buffer_info->skb = NULL;
3919 if (!adapter->rx_ps_hdr_size) {
3920 pci_unmap_single(pdev, buffer_info->dma,
3921 adapter->rx_buffer_len +
3922 NET_IP_ALIGN,
3923 PCI_DMA_FROMDEVICE);
3924 skb_put(skb, length);
3925 goto send_up;
9d5c8243
AK		 3926 }
3927
bf36c1a0
AD		 3928 if (!skb_shinfo(skb)->nr_frags) {
3929 pci_unmap_single(pdev, buffer_info->dma,
3930 adapter->rx_ps_hdr_size +
3931 NET_IP_ALIGN,
3932 PCI_DMA_FROMDEVICE);
3933 skb_put(skb, hlen);
3934 }
3935
3936 if (length) {
9d5c8243 3937 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3938 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3939 buffer_info->page_dma = 0;
bf36c1a0
AD		 3940
3941 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3942 buffer_info->page,
3943 buffer_info->page_offset,
3944 length);
3945
3946 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3947 (page_count(buffer_info->page) != 1))
3948 buffer_info->page = NULL;
3949 else
3950 get_page(buffer_info->page);
9d5c8243
AK		 3951
3952 skb->len += length;
3953 skb->data_len += length;
9d5c8243 3954
bf36c1a0 3955 skb->truesize += length;
9d5c8243
AK		 3956 }
3957send_up:
9d5c8243
AK		 3958 i++;
3959 if (i == rx_ring->count)
3960 i = 0;
3961 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3962 prefetch(next_rxd);
3963 next_buffer = &rx_ring->buffer_info[i];
3964
bf36c1a0
AD		 3965 if (!(staterr & E1000_RXD_STAT_EOP)) {
3966 buffer_info->skb = xchg(&next_buffer->skb, skb);
3967 buffer_info->dma = xchg(&next_buffer->dma, 0);
3968 goto next_desc;
3969 }
3970
9d5c8243
AK		 3971 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3972 dev_kfree_skb_irq(skb);
3973 goto next_desc;
3974 }
3975 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3976
3977 total_bytes += skb->len;
3978 total_packets++;
3979
3980 igb_rx_checksum_adv(adapter, staterr, skb);
3981
3982 skb->protocol = eth_type_trans(skb, netdev);
3983
d3352520 3984 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243
AK		 3985
3986 netdev->last_rx = jiffies;
3987
3988next_desc:
3989 rx_desc->wb.upper.status_error = 0;
3990
3991 /* return some buffers to hardware, one at a time is too slow */
3992 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3993 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3994 cleaned_count = 0;
3995 }
3996
3997 /* use prefetched values */
3998 rx_desc = next_rxd;
3999 buffer_info = next_buffer;
4000
4001 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4002 }
bf36c1a0 4003
9d5c8243
AK		 4004 rx_ring->next_to_clean = i;
4005 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4006
d3352520
AD		 4007#ifdef CONFIG_IGB_LRO
4008 if (rx_ring->lro_used) {
4009 lro_flush_all(&rx_ring->lro_mgr);
4010 rx_ring->lro_used = 0;
4011 }
4012#endif
4013
9d5c8243 4014 if (cleaned_count)
3b644cf6 4015 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4016
4017 rx_ring->total_packets += total_packets;
4018 rx_ring->total_bytes += total_bytes;
4019 rx_ring->rx_stats.packets += total_packets;
4020 rx_ring->rx_stats.bytes += total_bytes;
4021 adapter->net_stats.rx_bytes += total_bytes;
4022 adapter->net_stats.rx_packets += total_packets;
4023 return cleaned;
4024}
4025
4026
4027/**
4028 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4029 * @adapter: address of board private structure
4030 **/
3b644cf6 4031static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4032 int cleaned_count)
4033{
3b644cf6 4034 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4035 struct net_device *netdev = adapter->netdev;
4036 struct pci_dev *pdev = adapter->pdev;
4037 union e1000_adv_rx_desc *rx_desc;
4038 struct igb_buffer *buffer_info;
4039 struct sk_buff *skb;
4040 unsigned int i;
4041
4042 i = rx_ring->next_to_use;
4043 buffer_info = &rx_ring->buffer_info[i];
4044
4045 while (cleaned_count--) {
4046 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4047
bf36c1a0 4048 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4049 if (!buffer_info->page) {
bf36c1a0
AD		 4050 buffer_info->page = alloc_page(GFP_ATOMIC);
4051 if (!buffer_info->page) {
4052 adapter->alloc_rx_buff_failed++;
4053 goto no_buffers;
4054 }
4055 buffer_info->page_offset = 0;
4056 } else {
4057 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4058 }
4059 buffer_info->page_dma =
4060 pci_map_page(pdev,
4061 buffer_info->page,
bf36c1a0
AD		 4062 buffer_info->page_offset,
4063 PAGE_SIZE / 2,
9d5c8243
AK		 4064 PCI_DMA_FROMDEVICE);
4065 }
4066
4067 if (!buffer_info->skb) {
4068 int bufsz;
4069
4070 if (adapter->rx_ps_hdr_size)
4071 bufsz = adapter->rx_ps_hdr_size;
4072 else
4073 bufsz = adapter->rx_buffer_len;
4074 bufsz += NET_IP_ALIGN;
4075 skb = netdev_alloc_skb(netdev, bufsz);
4076
4077 if (!skb) {
4078 adapter->alloc_rx_buff_failed++;
4079 goto no_buffers;
4080 }
4081
4082 /* Make buffer alignment 2 beyond a 16 byte boundary
4083 * this will result in a 16 byte aligned IP header after
4084 * the 14 byte MAC header is removed
4085 */
4086 skb_reserve(skb, NET_IP_ALIGN);
4087
4088 buffer_info->skb = skb;
4089 buffer_info->dma = pci_map_single(pdev, skb->data,
4090 bufsz,
4091 PCI_DMA_FROMDEVICE);
4092
4093 }
4094 /* Refresh the desc even if buffer_addrs didn't change because
4095 * each write-back erases this info. */
4096 if (adapter->rx_ps_hdr_size) {
4097 rx_desc->read.pkt_addr =
4098 cpu_to_le64(buffer_info->page_dma);
4099 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4100 } else {
4101 rx_desc->read.pkt_addr =
4102 cpu_to_le64(buffer_info->dma);
4103 rx_desc->read.hdr_addr = 0;
4104 }
4105
4106 i++;
4107 if (i == rx_ring->count)
4108 i = 0;
4109 buffer_info = &rx_ring->buffer_info[i];
4110 }
4111
4112no_buffers:
4113 if (rx_ring->next_to_use != i) {
4114 rx_ring->next_to_use = i;
4115 if (i == 0)
4116 i = (rx_ring->count - 1);
4117 else
4118 i--;
4119
4120 /* Force memory writes to complete before letting h/w
4121 * know there are new descriptors to fetch. (Only
4122 * applicable for weak-ordered memory model archs,
4123 * such as IA-64). */
4124 wmb();
4125 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4126 }
4127}
4128
4129/**
4130 * igb_mii_ioctl -
4131 * @netdev:
4132 * @ifreq:
4133 * @cmd:
4134 **/
4135static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4136{
4137 struct igb_adapter *adapter = netdev_priv(netdev);
4138 struct mii_ioctl_data *data = if_mii(ifr);
4139
4140 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4141 return -EOPNOTSUPP;
4142
4143 switch (cmd) {
4144 case SIOCGMIIPHY:
4145 data->phy_id = adapter->hw.phy.addr;
4146 break;
4147 case SIOCGMIIREG:
4148 if (!capable(CAP_NET_ADMIN))
4149 return -EPERM;
4150 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
4151 data->reg_num
4152 & 0x1F, &data->val_out))
4153 return -EIO;
4154 break;
4155 case SIOCSMIIREG:
4156 default:
4157 return -EOPNOTSUPP;
4158 }
4159 return 0;
4160}
4161
4162/**
4163 * igb_ioctl -
4164 * @netdev:
4165 * @ifreq:
4166 * @cmd:
4167 **/
4168static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4169{
4170 switch (cmd) {
4171 case SIOCGMIIPHY:
4172 case SIOCGMIIREG:
4173 case SIOCSMIIREG:
4174 return igb_mii_ioctl(netdev, ifr, cmd);
4175 default:
4176 return -EOPNOTSUPP;
4177 }
4178}
4179
4180static void igb_vlan_rx_register(struct net_device *netdev,
4181 struct vlan_group *grp)
4182{
4183 struct igb_adapter *adapter = netdev_priv(netdev);
4184 struct e1000_hw *hw = &adapter->hw;
4185 u32 ctrl, rctl;
4186
4187 igb_irq_disable(adapter);
4188 adapter->vlgrp = grp;
4189
4190 if (grp) {
4191 /* enable VLAN tag insert/strip */
4192 ctrl = rd32(E1000_CTRL);
4193 ctrl |= E1000_CTRL_VME;
4194 wr32(E1000_CTRL, ctrl);
4195
4196 /* enable VLAN receive filtering */
4197 rctl = rd32(E1000_RCTL);
4198 rctl |= E1000_RCTL_VFE;
4199 rctl &= ~E1000_RCTL_CFIEN;
4200 wr32(E1000_RCTL, rctl);
4201 igb_update_mng_vlan(adapter);
4202 wr32(E1000_RLPML,
4203 adapter->max_frame_size + VLAN_TAG_SIZE);
4204 } else {
4205 /* disable VLAN tag insert/strip */
4206 ctrl = rd32(E1000_CTRL);
4207 ctrl &= ~E1000_CTRL_VME;
4208 wr32(E1000_CTRL, ctrl);
4209
4210 /* disable VLAN filtering */
4211 rctl = rd32(E1000_RCTL);
4212 rctl &= ~E1000_RCTL_VFE;
4213 wr32(E1000_RCTL, rctl);
4214 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4215 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4216 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4217 }
4218 wr32(E1000_RLPML,
4219 adapter->max_frame_size);
4220 }
4221
4222 if (!test_bit(__IGB_DOWN, &adapter->state))
4223 igb_irq_enable(adapter);
4224}
4225
4226static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4227{
4228 struct igb_adapter *adapter = netdev_priv(netdev);
4229 struct e1000_hw *hw = &adapter->hw;
4230 u32 vfta, index;
4231
4232 if ((adapter->hw.mng_cookie.status &
4233 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4234 (vid == adapter->mng_vlan_id))
4235 return;
4236 /* add VID to filter table */
4237 index = (vid >> 5) & 0x7F;
4238 vfta = array_rd32(E1000_VFTA, index);
4239 vfta |= (1 << (vid & 0x1F));
4240 igb_write_vfta(&adapter->hw, index, vfta);
4241}
4242
4243static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4244{
4245 struct igb_adapter *adapter = netdev_priv(netdev);
4246 struct e1000_hw *hw = &adapter->hw;
4247 u32 vfta, index;
4248
4249 igb_irq_disable(adapter);
4250 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4251
4252 if (!test_bit(__IGB_DOWN, &adapter->state))
4253 igb_irq_enable(adapter);
4254
4255 if ((adapter->hw.mng_cookie.status &
4256 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4257 (vid == adapter->mng_vlan_id)) {
4258 /* release control to f/w */
4259 igb_release_hw_control(adapter);
4260 return;
4261 }
4262
4263 /* remove VID from filter table */
4264 index = (vid >> 5) & 0x7F;
4265 vfta = array_rd32(E1000_VFTA, index);
4266 vfta &= ~(1 << (vid & 0x1F));
4267 igb_write_vfta(&adapter->hw, index, vfta);
4268}
4269
4270static void igb_restore_vlan(struct igb_adapter *adapter)
4271{
4272 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4273
4274 if (adapter->vlgrp) {
4275 u16 vid;
4276 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4277 if (!vlan_group_get_device(adapter->vlgrp, vid))
4278 continue;
4279 igb_vlan_rx_add_vid(adapter->netdev, vid);
4280 }
4281 }
4282}
4283
4284int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4285{
4286 struct e1000_mac_info *mac = &adapter->hw.mac;
4287
4288 mac->autoneg = 0;
4289
4290 /* Fiber NICs only allow 1000 gbps Full duplex */
4291 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4292 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4293 dev_err(&adapter->pdev->dev,
4294 "Unsupported Speed/Duplex configuration\n");
4295 return -EINVAL;
4296 }
4297
4298 switch (spddplx) {
4299 case SPEED_10 + DUPLEX_HALF:
4300 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4301 break;
4302 case SPEED_10 + DUPLEX_FULL:
4303 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4304 break;
4305 case SPEED_100 + DUPLEX_HALF:
4306 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4307 break;
4308 case SPEED_100 + DUPLEX_FULL:
4309 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4310 break;
4311 case SPEED_1000 + DUPLEX_FULL:
4312 mac->autoneg = 1;
4313 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4314 break;
4315 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4316 default:
4317 dev_err(&adapter->pdev->dev,
4318 "Unsupported Speed/Duplex configuration\n");
4319 return -EINVAL;
4320 }
4321 return 0;
4322}
4323
4324
4325static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4326{
4327 struct net_device *netdev = pci_get_drvdata(pdev);
4328 struct igb_adapter *adapter = netdev_priv(netdev);
4329 struct e1000_hw *hw = &adapter->hw;
2d064c06 4330 u32 ctrl, rctl, status;
9d5c8243
AK		 4331 u32 wufc = adapter->wol;
4332#ifdef CONFIG_PM
4333 int retval = 0;
4334#endif
4335
4336 netif_device_detach(netdev);
4337
a88f10ec
AD		 4338 if (netif_running(netdev))
4339 igb_close(netdev);
4340
4341 igb_reset_interrupt_capability(adapter);
4342
4343 igb_free_queues(adapter);
9d5c8243
AK		 4344
4345#ifdef CONFIG_PM
4346 retval = pci_save_state(pdev);
4347 if (retval)
4348 return retval;
4349#endif
4350
4351 status = rd32(E1000_STATUS);
4352 if (status & E1000_STATUS_LU)
4353 wufc &= ~E1000_WUFC_LNKC;
4354
4355 if (wufc) {
4356 igb_setup_rctl(adapter);
4357 igb_set_multi(netdev);
4358
4359 /* turn on all-multi mode if wake on multicast is enabled */
4360 if (wufc & E1000_WUFC_MC) {
4361 rctl = rd32(E1000_RCTL);
4362 rctl |= E1000_RCTL_MPE;
4363 wr32(E1000_RCTL, rctl);
4364 }
4365
4366 ctrl = rd32(E1000_CTRL);
4367 /* advertise wake from D3Cold */
4368 #define E1000_CTRL_ADVD3WUC 0x00100000
4369 /* phy power management enable */
4370 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4371 ctrl |= E1000_CTRL_ADVD3WUC;
4372 wr32(E1000_CTRL, ctrl);
4373
9d5c8243
AK		 4374 /* Allow time for pending master requests to run */
4375 igb_disable_pcie_master(&adapter->hw);
4376
4377 wr32(E1000_WUC, E1000_WUC_PME_EN);
4378 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4379 } else {
4380 wr32(E1000_WUC, 0);
4381 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4382 }
4383
2d064c06
AD		 4384 /* make sure adapter isn't asleep if manageability/wol is enabled */
4385 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4386 pci_enable_wake(pdev, PCI_D3hot, 1);
4387 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4388 } else {
4389 igb_shutdown_fiber_serdes_link_82575(hw);
4390 pci_enable_wake(pdev, PCI_D3hot, 0);
4391 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4392 }
4393
4394 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4395 * would have already happened in close and is redundant. */
4396 igb_release_hw_control(adapter);
4397
4398 pci_disable_device(pdev);
4399
4400 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4401
4402 return 0;
4403}
4404
4405#ifdef CONFIG_PM
4406static int igb_resume(struct pci_dev *pdev)
4407{
4408 struct net_device *netdev = pci_get_drvdata(pdev);
4409 struct igb_adapter *adapter = netdev_priv(netdev);
4410 struct e1000_hw *hw = &adapter->hw;
4411 u32 err;
4412
4413 pci_set_power_state(pdev, PCI_D0);
4414 pci_restore_state(pdev);
42bfd33a
TI		 4415
4416 if (adapter->need_ioport)
4417 err = pci_enable_device(pdev);
4418 else
4419 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4420 if (err) {
4421 dev_err(&pdev->dev,
4422 "igb: Cannot enable PCI device from suspend\n");
4423 return err;
4424 }
4425 pci_set_master(pdev);
4426
4427 pci_enable_wake(pdev, PCI_D3hot, 0);
4428 pci_enable_wake(pdev, PCI_D3cold, 0);
4429
a88f10ec
AD		 4430 igb_set_interrupt_capability(adapter);
4431
4432 if (igb_alloc_queues(adapter)) {
4433 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4434 return -ENOMEM;
9d5c8243
AK		 4435 }
4436
4437 /* e1000_power_up_phy(adapter); */
4438
4439 igb_reset(adapter);
4440 wr32(E1000_WUS, ~0);
4441
a88f10ec
AD		 4442 if (netif_running(netdev)) {
4443 err = igb_open(netdev);
4444 if (err)
4445 return err;
4446 }
9d5c8243
AK		 4447
4448 netif_device_attach(netdev);
4449
4450 /* let the f/w know that the h/w is now under the control of the
4451 * driver. */
4452 igb_get_hw_control(adapter);
4453
4454 return 0;
4455}
4456#endif
4457
4458static void igb_shutdown(struct pci_dev *pdev)
4459{
4460 igb_suspend(pdev, PMSG_SUSPEND);
4461}
4462
4463#ifdef CONFIG_NET_POLL_CONTROLLER
4464/*
4465 * Polling 'interrupt' - used by things like netconsole to send skbs
4466 * without having to re-enable interrupts. It's not called while
4467 * the interrupt routine is executing.
4468 */
4469static void igb_netpoll(struct net_device *netdev)
4470{
4471 struct igb_adapter *adapter = netdev_priv(netdev);
4472 int i;
4473 int work_done = 0;
4474
4475 igb_irq_disable(adapter);
7dfc16fa
AD		 4476 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4477
9d5c8243 4478 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4479 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4480
4481 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4482 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4483 &work_done,
4484 adapter->rx_ring[i].napi.weight);
4485
7dfc16fa 4486 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4487 igb_irq_enable(adapter);
4488}
4489#endif /* CONFIG_NET_POLL_CONTROLLER */
4490
4491/**
4492 * igb_io_error_detected - called when PCI error is detected
4493 * @pdev: Pointer to PCI device
4494 * @state: The current pci connection state
4495 *
4496 * This function is called after a PCI bus error affecting
4497 * this device has been detected.
4498 */
4499static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4500 pci_channel_state_t state)
4501{
4502 struct net_device *netdev = pci_get_drvdata(pdev);
4503 struct igb_adapter *adapter = netdev_priv(netdev);
4504
4505 netif_device_detach(netdev);
4506
4507 if (netif_running(netdev))
4508 igb_down(adapter);
4509 pci_disable_device(pdev);
4510
4511 /* Request a slot slot reset. */
4512 return PCI_ERS_RESULT_NEED_RESET;
4513}
4514
4515/**
4516 * igb_io_slot_reset - called after the pci bus has been reset.
4517 * @pdev: Pointer to PCI device
4518 *
4519 * Restart the card from scratch, as if from a cold-boot. Implementation
4520 * resembles the first-half of the igb_resume routine.
4521 */
4522static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4523{
4524 struct net_device *netdev = pci_get_drvdata(pdev);
4525 struct igb_adapter *adapter = netdev_priv(netdev);
4526 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4527 int err;
9d5c8243 4528
42bfd33a
TI		 4529 if (adapter->need_ioport)
4530 err = pci_enable_device(pdev);
4531 else
4532 err = pci_enable_device_mem(pdev);
4533 if (err) {
9d5c8243
AK		 4534 dev_err(&pdev->dev,
4535 "Cannot re-enable PCI device after reset.\n");
4536 return PCI_ERS_RESULT_DISCONNECT;
4537 }
4538 pci_set_master(pdev);
c682fc23 4539 pci_restore_state(pdev);
9d5c8243
AK		 4540
4541 pci_enable_wake(pdev, PCI_D3hot, 0);
4542 pci_enable_wake(pdev, PCI_D3cold, 0);
4543
4544 igb_reset(adapter);
4545 wr32(E1000_WUS, ~0);
4546
4547 return PCI_ERS_RESULT_RECOVERED;
4548}
4549
4550/**
4551 * igb_io_resume - called when traffic can start flowing again.
4552 * @pdev: Pointer to PCI device
4553 *
4554 * This callback is called when the error recovery driver tells us that
4555 * its OK to resume normal operation. Implementation resembles the
4556 * second-half of the igb_resume routine.
4557 */
4558static void igb_io_resume(struct pci_dev *pdev)
4559{
4560 struct net_device *netdev = pci_get_drvdata(pdev);
4561 struct igb_adapter *adapter = netdev_priv(netdev);
4562
4563 igb_init_manageability(adapter);
4564
4565 if (netif_running(netdev)) {
4566 if (igb_up(adapter)) {
4567 dev_err(&pdev->dev, "igb_up failed after reset\n");
4568 return;
4569 }
4570 }
4571
4572 netif_device_attach(netdev);
4573
4574 /* let the f/w know that the h/w is now under the control of the
4575 * driver. */
4576 igb_get_hw_control(adapter);
4577
4578}
4579
4580/* igb_main.c */
Clone of davem's net-next-2.6 tree