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igb: add pci device pointer to ring structure
[net-next-2.6.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76};
77
78MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80void igb_reset(struct igb_adapter *);
81static int igb_setup_all_tx_resources(struct igb_adapter *);
82static int igb_setup_all_rx_resources(struct igb_adapter *);
83static void igb_free_all_tx_resources(struct igb_adapter *);
84static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 85void igb_update_stats(struct igb_adapter *);
86static int igb_probe(struct pci_dev *, const struct pci_device_id *);
87static void __devexit igb_remove(struct pci_dev *pdev);
88static int igb_sw_init(struct igb_adapter *);
89static int igb_open(struct net_device *);
90static int igb_close(struct net_device *);
91static void igb_configure_tx(struct igb_adapter *);
92static void igb_configure_rx(struct igb_adapter *);
85b430b4 93static void igb_setup_tctl(struct igb_adapter *);
9d5c8243
AK		 94static void igb_setup_rctl(struct igb_adapter *);
95static void igb_clean_all_tx_rings(struct igb_adapter *);
96static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 97static void igb_clean_tx_ring(struct igb_ring *);
98static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 99static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 100static void igb_update_phy_info(unsigned long);
101static void igb_watchdog(unsigned long);
102static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 103static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
104 struct net_device *,
105 struct igb_ring *);
106static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
107 struct net_device *);
9d5c8243
AK		 108static struct net_device_stats *igb_get_stats(struct net_device *);
109static int igb_change_mtu(struct net_device *, int);
110static int igb_set_mac(struct net_device *, void *);
68d480c4 111static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 112static irqreturn_t igb_intr(int irq, void *);
113static irqreturn_t igb_intr_msi(int irq, void *);
114static irqreturn_t igb_msix_other(int irq, void *);
047e0030 115static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 116#ifdef CONFIG_IGB_DCA
047e0030 117static void igb_update_dca(struct igb_q_vector *);
fe4506b6 118static void igb_setup_dca(struct igb_adapter *);
421e02f0 119#endif /* CONFIG_IGB_DCA */
047e0030 120static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 121static int igb_poll(struct napi_struct *, int);
047e0030 122static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
3b644cf6 123static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 124static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
125static void igb_tx_timeout(struct net_device *);
126static void igb_reset_task(struct work_struct *);
127static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
128static void igb_vlan_rx_add_vid(struct net_device *, u16);
129static void igb_vlan_rx_kill_vid(struct net_device *, u16);
130static void igb_restore_vlan(struct igb_adapter *);
26ad9178 131static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 132static void igb_ping_all_vfs(struct igb_adapter *);
133static void igb_msg_task(struct igb_adapter *);
134static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
4ae196df 135static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 136static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
137static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 138
c8159b2d
ED		 139static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
140{
141 u32 reg_data;
142
143 reg_data = rd32(E1000_VMOLR(vfn));
144 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
c8159b2d
ED		 145 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
146 E1000_VMOLR_AUPE | /* Accept untagged packets */
147 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
148 wr32(E1000_VMOLR(vfn), reg_data);
149}
150
151static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
152 int vfn)
153{
154 struct e1000_hw *hw = &adapter->hw;
155 u32 vmolr;
156
ae641bdc
AD		 157 /* if it isn't the PF check to see if VFs are enabled and
158 * increase the size to support vlan tags */
159 if (vfn < adapter->vfs_allocated_count &&
160 adapter->vf_data[vfn].vlans_enabled)
161 size += VLAN_TAG_SIZE;
162
c8159b2d
ED		 163 vmolr = rd32(E1000_VMOLR(vfn));
164 vmolr &= ~E1000_VMOLR_RLPML_MASK;
165 vmolr |= size | E1000_VMOLR_LPE;
166 wr32(E1000_VMOLR(vfn), vmolr);
167
168 return 0;
169}
170
9d5c8243 171#ifdef CONFIG_PM
3fe7c4c9 172static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 173static int igb_resume(struct pci_dev *);
174#endif
175static void igb_shutdown(struct pci_dev *);
421e02f0 176#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 177static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
178static struct notifier_block dca_notifier = {
179 .notifier_call = igb_notify_dca,
180 .next = NULL,
181 .priority = 0
182};
183#endif
9d5c8243
AK		 184#ifdef CONFIG_NET_POLL_CONTROLLER
185/* for netdump / net console */
186static void igb_netpoll(struct net_device *);
187#endif
37680117 188#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 189static unsigned int max_vfs = 0;
190module_param(max_vfs, uint, 0);
191MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
192 "per physical function");
193#endif /* CONFIG_PCI_IOV */
194
9d5c8243
AK		 195static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
196 pci_channel_state_t);
197static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
198static void igb_io_resume(struct pci_dev *);
199
200static struct pci_error_handlers igb_err_handler = {
201 .error_detected = igb_io_error_detected,
202 .slot_reset = igb_io_slot_reset,
203 .resume = igb_io_resume,
204};
205
206
207static struct pci_driver igb_driver = {
208 .name = igb_driver_name,
209 .id_table = igb_pci_tbl,
210 .probe = igb_probe,
211 .remove = __devexit_p(igb_remove),
212#ifdef CONFIG_PM
213 /* Power Managment Hooks */
214 .suspend = igb_suspend,
215 .resume = igb_resume,
216#endif
217 .shutdown = igb_shutdown,
218 .err_handler = &igb_err_handler
219};
220
7dfc16fa
AD		 221static int global_quad_port_a; /* global quad port a indication */
222
9d5c8243
AK		 223MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
224MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
225MODULE_LICENSE("GPL");
226MODULE_VERSION(DRV_VERSION);
227
38c845c7
PO		 228/**
229 * Scale the NIC clock cycle by a large factor so that
230 * relatively small clock corrections can be added or
231 * substracted at each clock tick. The drawbacks of a
232 * large factor are a) that the clock register overflows
233 * more quickly (not such a big deal) and b) that the
234 * increment per tick has to fit into 24 bits.
235 *
236 * Note that
237 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
238 * IGB_TSYNC_SCALE
239 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
240 *
241 * The base scale factor is intentionally a power of two
242 * so that the division in %struct timecounter can be done with
243 * a shift.
244 */
245#define IGB_TSYNC_SHIFT (19)
246#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
247
248/**
249 * The duration of one clock cycle of the NIC.
250 *
251 * @todo This hard-coded value is part of the specification and might change
252 * in future hardware revisions. Add revision check.
253 */
254#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
255
256#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
257# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
258#endif
259
260/**
261 * igb_read_clock - read raw cycle counter (to be used by time counter)
262 */
263static cycle_t igb_read_clock(const struct cyclecounter *tc)
264{
265 struct igb_adapter *adapter =
266 container_of(tc, struct igb_adapter, cycles);
267 struct e1000_hw *hw = &adapter->hw;
268 u64 stamp;
269
270 stamp = rd32(E1000_SYSTIML);
271 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
272
273 return stamp;
274}
275
9d5c8243
AK		 276#ifdef DEBUG
277/**
278 * igb_get_hw_dev_name - return device name string
279 * used by hardware layer to print debugging information
280 **/
281char *igb_get_hw_dev_name(struct e1000_hw *hw)
282{
283 struct igb_adapter *adapter = hw->back;
284 return adapter->netdev->name;
285}
38c845c7
PO		 286
287/**
288 * igb_get_time_str - format current NIC and system time as string
289 */
290static char *igb_get_time_str(struct igb_adapter *adapter,
291 char buffer[160])
292{
293 cycle_t hw = adapter->cycles.read(&adapter->cycles);
294 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
295 struct timespec sys;
296 struct timespec delta;
297 getnstimeofday(&sys);
298
299 delta = timespec_sub(nic, sys);
300
301 sprintf(buffer,
33af6bcc
PO		 302 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
303 hw,
38c845c7
PO		 304 (long)nic.tv_sec, nic.tv_nsec,
305 (long)sys.tv_sec, sys.tv_nsec,
306 (long)delta.tv_sec, delta.tv_nsec);
307
308 return buffer;
309}
9d5c8243
AK		 310#endif
311
c493ea45
AD		 312/**
313 * igb_desc_unused - calculate if we have unused descriptors
314 **/
315static int igb_desc_unused(struct igb_ring *ring)
316{
317 if (ring->next_to_clean > ring->next_to_use)
318 return ring->next_to_clean - ring->next_to_use - 1;
319
320 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
321}
322
9d5c8243
AK		 323/**
324 * igb_init_module - Driver Registration Routine
325 *
326 * igb_init_module is the first routine called when the driver is
327 * loaded. All it does is register with the PCI subsystem.
328 **/
329static int __init igb_init_module(void)
330{
331 int ret;
332 printk(KERN_INFO "%s - version %s\n",
333 igb_driver_string, igb_driver_version);
334
335 printk(KERN_INFO "%s\n", igb_copyright);
336
7dfc16fa
AD		 337 global_quad_port_a = 0;
338
421e02f0 339#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 340 dca_register_notify(&dca_notifier);
341#endif
bbd98fe4
AD		 342
343 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 344 return ret;
345}
346
347module_init(igb_init_module);
348
349/**
350 * igb_exit_module - Driver Exit Cleanup Routine
351 *
352 * igb_exit_module is called just before the driver is removed
353 * from memory.
354 **/
355static void __exit igb_exit_module(void)
356{
421e02f0 357#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 358 dca_unregister_notify(&dca_notifier);
359#endif
9d5c8243
AK		 360 pci_unregister_driver(&igb_driver);
361}
362
363module_exit(igb_exit_module);
364
26bc19ec
AD		 365#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
366/**
367 * igb_cache_ring_register - Descriptor ring to register mapping
368 * @adapter: board private structure to initialize
369 *
370 * Once we know the feature-set enabled for the device, we'll cache
371 * the register offset the descriptor ring is assigned to.
372 **/
373static void igb_cache_ring_register(struct igb_adapter *adapter)
374{
375 int i;
047e0030 376 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 377
378 switch (adapter->hw.mac.type) {
379 case e1000_82576:
380 /* The queues are allocated for virtualization such that VF 0
381 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
382 * In order to avoid collision we start at the first free queue
383 * and continue consuming queues in the same sequence
384 */
385 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 386 adapter->rx_ring[i].reg_idx = rbase_offset +
387 Q_IDX_82576(i);
26bc19ec 388 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 389 adapter->tx_ring[i].reg_idx = rbase_offset +
390 Q_IDX_82576(i);
26bc19ec
AD		 391 break;
392 case e1000_82575:
393 default:
394 for (i = 0; i < adapter->num_rx_queues; i++)
395 adapter->rx_ring[i].reg_idx = i;
396 for (i = 0; i < adapter->num_tx_queues; i++)
397 adapter->tx_ring[i].reg_idx = i;
398 break;
399 }
400}
401
047e0030
AD		 402static void igb_free_queues(struct igb_adapter *adapter)
403{
404 kfree(adapter->tx_ring);
405 kfree(adapter->rx_ring);
406
407 adapter->tx_ring = NULL;
408 adapter->rx_ring = NULL;
409
410 adapter->num_rx_queues = 0;
411 adapter->num_tx_queues = 0;
412}
413
9d5c8243
AK		 414/**
415 * igb_alloc_queues - Allocate memory for all rings
416 * @adapter: board private structure to initialize
417 *
418 * We allocate one ring per queue at run-time since we don't know the
419 * number of queues at compile-time.
420 **/
421static int igb_alloc_queues(struct igb_adapter *adapter)
422{
423 int i;
424
425 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
426 sizeof(struct igb_ring), GFP_KERNEL);
427 if (!adapter->tx_ring)
047e0030 428 goto err;
9d5c8243
AK		 429
430 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
431 sizeof(struct igb_ring), GFP_KERNEL);
047e0030
AD		 432 if (!adapter->rx_ring)
433 goto err;
6eb5a7f1 434
661086df
PWJ		 435 for (i = 0; i < adapter->num_tx_queues; i++) {
436 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 437 ring->count = adapter->tx_ring_count;
661086df 438 ring->queue_index = i;
80785298 439 ring->pdev = adapter->pdev;
661086df 440 }
9d5c8243
AK		 441 for (i = 0; i < adapter->num_rx_queues; i++) {
442 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 443 ring->count = adapter->rx_ring_count;
844290e5 444 ring->queue_index = i;
80785298 445 ring->pdev = adapter->pdev;
9d5c8243 446 }
26bc19ec
AD		 447
448 igb_cache_ring_register(adapter);
9d5c8243 449
047e0030 450 return 0;
a88f10ec 451
047e0030
AD		 452err:
453 igb_free_queues(adapter);
d1a8c9e1 454
047e0030 455 return -ENOMEM;
a88f10ec
AD		 456}
457
9d5c8243 458#define IGB_N0_QUEUE -1
047e0030 459static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 460{
461 u32 msixbm = 0;
047e0030 462 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 463 struct e1000_hw *hw = &adapter->hw;
2d064c06 464 u32 ivar, index;
047e0030
AD		 465 int rx_queue = IGB_N0_QUEUE;
466 int tx_queue = IGB_N0_QUEUE;
467
468 if (q_vector->rx_ring)
469 rx_queue = q_vector->rx_ring->reg_idx;
470 if (q_vector->tx_ring)
471 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 472
473 switch (hw->mac.type) {
474 case e1000_82575:
9d5c8243
AK		 475 /* The 82575 assigns vectors using a bitmask, which matches the
476 bitmask for the EICR/EIMS/EIMC registers. To assign one
477 or more queues to a vector, we write the appropriate bits
478 into the MSIXBM register for that vector. */
047e0030 479 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 480 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 481 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 482 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
9d5c8243 483 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 484 q_vector->eims_value = msixbm;
2d064c06
AD		 485 break;
486 case e1000_82576:
26bc19ec 487 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 488 Each queue has a single entry in the table to which we write
489 a vector number along with a "valid" bit. Sadly, the layout
490 of the table is somewhat counterintuitive. */
491 if (rx_queue > IGB_N0_QUEUE) {
047e0030 492 index = (rx_queue & 0x7);
2d064c06 493 ivar = array_rd32(E1000_IVAR0, index);
047e0030 494 if (rx_queue < 8) {
26bc19ec
AD		 495 /* vector goes into low byte of register */
496 ivar = ivar & 0xFFFFFF00;
497 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 498 } else {
499 /* vector goes into third byte of register */
500 ivar = ivar & 0xFF00FFFF;
501 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 502 }
2d064c06
AD		 503 array_wr32(E1000_IVAR0, index, ivar);
504 }
505 if (tx_queue > IGB_N0_QUEUE) {
047e0030 506 index = (tx_queue & 0x7);
2d064c06 507 ivar = array_rd32(E1000_IVAR0, index);
047e0030 508 if (tx_queue < 8) {
26bc19ec
AD		 509 /* vector goes into second byte of register */
510 ivar = ivar & 0xFFFF00FF;
511 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 512 } else {
513 /* vector goes into high byte of register */
514 ivar = ivar & 0x00FFFFFF;
515 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 516 }
2d064c06
AD		 517 array_wr32(E1000_IVAR0, index, ivar);
518 }
047e0030 519 q_vector->eims_value = 1 << msix_vector;
2d064c06
AD		 520 break;
521 default:
522 BUG();
523 break;
524 }
9d5c8243
AK		 525}
526
527/**
528 * igb_configure_msix - Configure MSI-X hardware
529 *
530 * igb_configure_msix sets up the hardware to properly
531 * generate MSI-X interrupts.
532 **/
533static void igb_configure_msix(struct igb_adapter *adapter)
534{
535 u32 tmp;
536 int i, vector = 0;
537 struct e1000_hw *hw = &adapter->hw;
538
539 adapter->eims_enable_mask = 0;
9d5c8243
AK		 540
541 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 542 switch (hw->mac.type) {
543 case e1000_82575:
9d5c8243
AK		 544 tmp = rd32(E1000_CTRL_EXT);
545 /* enable MSI-X PBA support*/
546 tmp |= E1000_CTRL_EXT_PBA_CLR;
547
548 /* Auto-Mask interrupts upon ICR read. */
549 tmp |= E1000_CTRL_EXT_EIAME;
550 tmp |= E1000_CTRL_EXT_IRCA;
551
552 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 553
554 /* enable msix_other interrupt */
555 array_wr32(E1000_MSIXBM(0), vector++,
556 E1000_EIMS_OTHER);
844290e5 557 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 558
2d064c06
AD		 559 break;
560
561 case e1000_82576:
047e0030
AD		 562 /* Turn on MSI-X capability first, or our settings
563 * won't stick. And it will take days to debug. */
564 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
565 E1000_GPIE_PBA | E1000_GPIE_EIAME |
566 E1000_GPIE_NSICR);
567
568 /* enable msix_other interrupt */
569 adapter->eims_other = 1 << vector;
2d064c06 570 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 571
047e0030 572 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 573 break;
574 default:
575 /* do nothing, since nothing else supports MSI-X */
576 break;
577 } /* switch (hw->mac.type) */
047e0030
AD		 578
579 adapter->eims_enable_mask |= adapter->eims_other;
580
581 for (i = 0; i < adapter->num_q_vectors; i++) {
582 struct igb_q_vector *q_vector = adapter->q_vector[i];
583 igb_assign_vector(q_vector, vector++);
584 adapter->eims_enable_mask |= q_vector->eims_value;
585 }
586
9d5c8243
AK		 587 wrfl();
588}
589
590/**
591 * igb_request_msix - Initialize MSI-X interrupts
592 *
593 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
594 * kernel.
595 **/
596static int igb_request_msix(struct igb_adapter *adapter)
597{
598 struct net_device *netdev = adapter->netdev;
047e0030 599 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 600 int i, err = 0, vector = 0;
601
047e0030
AD		 602 err = request_irq(adapter->msix_entries[vector].vector,
603 &igb_msix_other, 0, netdev->name, adapter);
604 if (err)
605 goto out;
606 vector++;
607
608 for (i = 0; i < adapter->num_q_vectors; i++) {
609 struct igb_q_vector *q_vector = adapter->q_vector[i];
610
611 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
612
613 if (q_vector->rx_ring && q_vector->tx_ring)
614 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
615 q_vector->rx_ring->queue_index);
616 else if (q_vector->tx_ring)
617 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
618 q_vector->tx_ring->queue_index);
619 else if (q_vector->rx_ring)
620 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
621 q_vector->rx_ring->queue_index);
9d5c8243 622 else
047e0030
AD		 623 sprintf(q_vector->name, "%s-unused", netdev->name);
624
9d5c8243 625 err = request_irq(adapter->msix_entries[vector].vector,
047e0030
AD		 626 &igb_msix_ring, 0, q_vector->name,
627 q_vector);
9d5c8243
AK		 628 if (err)
629 goto out;
9d5c8243
AK		 630 vector++;
631 }
632
9d5c8243
AK		 633 igb_configure_msix(adapter);
634 return 0;
635out:
636 return err;
637}
638
639static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
640{
641 if (adapter->msix_entries) {
642 pci_disable_msix(adapter->pdev);
643 kfree(adapter->msix_entries);
644 adapter->msix_entries = NULL;
047e0030 645 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 646 pci_disable_msi(adapter->pdev);
047e0030 647 }
9d5c8243
AK		 648}
649
047e0030
AD		 650/**
651 * igb_free_q_vectors - Free memory allocated for interrupt vectors
652 * @adapter: board private structure to initialize
653 *
654 * This function frees the memory allocated to the q_vectors. In addition if
655 * NAPI is enabled it will delete any references to the NAPI struct prior
656 * to freeing the q_vector.
657 **/
658static void igb_free_q_vectors(struct igb_adapter *adapter)
659{
660 int v_idx;
661
662 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
663 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
664 adapter->q_vector[v_idx] = NULL;
665 netif_napi_del(&q_vector->napi);
666 kfree(q_vector);
667 }
668 adapter->num_q_vectors = 0;
669}
670
671/**
672 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
673 *
674 * This function resets the device so that it has 0 rx queues, tx queues, and
675 * MSI-X interrupts allocated.
676 */
677static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
678{
679 igb_free_queues(adapter);
680 igb_free_q_vectors(adapter);
681 igb_reset_interrupt_capability(adapter);
682}
9d5c8243
AK		 683
684/**
685 * igb_set_interrupt_capability - set MSI or MSI-X if supported
686 *
687 * Attempt to configure interrupts using the best available
688 * capabilities of the hardware and kernel.
689 **/
690static void igb_set_interrupt_capability(struct igb_adapter *adapter)
691{
692 int err;
693 int numvecs, i;
694
83b7180d 695 /* Number of supported queues. */
83b7180d
AD		 696 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
697 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
698
047e0030
AD		 699 /* start with one vector for every rx queue */
700 numvecs = adapter->num_rx_queues;
701
702 /* if tx handler is seperate add 1 for every tx queue */
703 numvecs += adapter->num_tx_queues;
704
705 /* store the number of vectors reserved for queues */
706 adapter->num_q_vectors = numvecs;
707
708 /* add 1 vector for link status interrupts */
709 numvecs++;
9d5c8243
AK		 710 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
711 GFP_KERNEL);
712 if (!adapter->msix_entries)
713 goto msi_only;
714
715 for (i = 0; i < numvecs; i++)
716 adapter->msix_entries[i].entry = i;
717
718 err = pci_enable_msix(adapter->pdev,
719 adapter->msix_entries,
720 numvecs);
721 if (err == 0)
34a20e89 722 goto out;
9d5c8243
AK		 723
724 igb_reset_interrupt_capability(adapter);
725
726 /* If we can't do MSI-X, try MSI */
727msi_only:
2a3abf6d
AD		 728#ifdef CONFIG_PCI_IOV
729 /* disable SR-IOV for non MSI-X configurations */
730 if (adapter->vf_data) {
731 struct e1000_hw *hw = &adapter->hw;
732 /* disable iov and allow time for transactions to clear */
733 pci_disable_sriov(adapter->pdev);
734 msleep(500);
735
736 kfree(adapter->vf_data);
737 adapter->vf_data = NULL;
738 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
739 msleep(100);
740 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
741 }
742#endif
9d5c8243 743 adapter->num_rx_queues = 1;
661086df 744 adapter->num_tx_queues = 1;
047e0030 745 adapter->num_q_vectors = 1;
9d5c8243 746 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 747 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 748out:
661086df 749 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 750 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 751 return;
752}
753
047e0030
AD		 754/**
755 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
756 * @adapter: board private structure to initialize
757 *
758 * We allocate one q_vector per queue interrupt. If allocation fails we
759 * return -ENOMEM.
760 **/
761static int igb_alloc_q_vectors(struct igb_adapter *adapter)
762{
763 struct igb_q_vector *q_vector;
764 struct e1000_hw *hw = &adapter->hw;
765 int v_idx;
766
767 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
768 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
769 if (!q_vector)
770 goto err_out;
771 q_vector->adapter = adapter;
772 q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0;
773 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
774 q_vector->itr_val = IGB_START_ITR;
775 q_vector->set_itr = 1;
776 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
777 adapter->q_vector[v_idx] = q_vector;
778 }
779 return 0;
780
781err_out:
782 while (v_idx) {
783 v_idx--;
784 q_vector = adapter->q_vector[v_idx];
785 netif_napi_del(&q_vector->napi);
786 kfree(q_vector);
787 adapter->q_vector[v_idx] = NULL;
788 }
789 return -ENOMEM;
790}
791
792static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
793 int ring_idx, int v_idx)
794{
795 struct igb_q_vector *q_vector;
796
797 q_vector = adapter->q_vector[v_idx];
798 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
799 q_vector->rx_ring->q_vector = q_vector;
800 q_vector->itr_val = adapter->itr;
801}
802
803static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
804 int ring_idx, int v_idx)
805{
806 struct igb_q_vector *q_vector;
807
808 q_vector = adapter->q_vector[v_idx];
809 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
810 q_vector->tx_ring->q_vector = q_vector;
811 q_vector->itr_val = adapter->itr;
812}
813
814/**
815 * igb_map_ring_to_vector - maps allocated queues to vectors
816 *
817 * This function maps the recently allocated queues to vectors.
818 **/
819static int igb_map_ring_to_vector(struct igb_adapter *adapter)
820{
821 int i;
822 int v_idx = 0;
823
824 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
825 (adapter->num_q_vectors < adapter->num_tx_queues))
826 return -ENOMEM;
827
828 if (adapter->num_q_vectors >=
829 (adapter->num_rx_queues + adapter->num_tx_queues)) {
830 for (i = 0; i < adapter->num_rx_queues; i++)
831 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
832 for (i = 0; i < adapter->num_tx_queues; i++)
833 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
834 } else {
835 for (i = 0; i < adapter->num_rx_queues; i++) {
836 if (i < adapter->num_tx_queues)
837 igb_map_tx_ring_to_vector(adapter, i, v_idx);
838 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
839 }
840 for (; i < adapter->num_tx_queues; i++)
841 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
842 }
843 return 0;
844}
845
846/**
847 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
848 *
849 * This function initializes the interrupts and allocates all of the queues.
850 **/
851static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
852{
853 struct pci_dev *pdev = adapter->pdev;
854 int err;
855
856 igb_set_interrupt_capability(adapter);
857
858 err = igb_alloc_q_vectors(adapter);
859 if (err) {
860 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
861 goto err_alloc_q_vectors;
862 }
863
864 err = igb_alloc_queues(adapter);
865 if (err) {
866 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
867 goto err_alloc_queues;
868 }
869
870 err = igb_map_ring_to_vector(adapter);
871 if (err) {
872 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
873 goto err_map_queues;
874 }
875
876
877 return 0;
878err_map_queues:
879 igb_free_queues(adapter);
880err_alloc_queues:
881 igb_free_q_vectors(adapter);
882err_alloc_q_vectors:
883 igb_reset_interrupt_capability(adapter);
884 return err;
885}
886
9d5c8243
AK		 887/**
888 * igb_request_irq - initialize interrupts
889 *
890 * Attempts to configure interrupts using the best available
891 * capabilities of the hardware and kernel.
892 **/
893static int igb_request_irq(struct igb_adapter *adapter)
894{
895 struct net_device *netdev = adapter->netdev;
047e0030 896 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 897 struct e1000_hw *hw = &adapter->hw;
898 int err = 0;
899
900 if (adapter->msix_entries) {
901 err = igb_request_msix(adapter);
844290e5 902 if (!err)
9d5c8243 903 goto request_done;
9d5c8243 904 /* fall back to MSI */
047e0030 905 igb_clear_interrupt_scheme(adapter);
9d5c8243 906 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 907 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 908 igb_free_all_tx_resources(adapter);
909 igb_free_all_rx_resources(adapter);
047e0030 910 adapter->num_tx_queues = 1;
9d5c8243 911 adapter->num_rx_queues = 1;
047e0030
AD		 912 adapter->num_q_vectors = 1;
913 err = igb_alloc_q_vectors(adapter);
914 if (err) {
915 dev_err(&pdev->dev,
916 "Unable to allocate memory for vectors\n");
917 goto request_done;
918 }
919 err = igb_alloc_queues(adapter);
920 if (err) {
921 dev_err(&pdev->dev,
922 "Unable to allocate memory for queues\n");
923 igb_free_q_vectors(adapter);
924 goto request_done;
925 }
926 igb_setup_all_tx_resources(adapter);
927 igb_setup_all_rx_resources(adapter);
844290e5 928 } else {
2d064c06
AD		 929 switch (hw->mac.type) {
930 case e1000_82575:
931 wr32(E1000_MSIXBM(0),
047e0030
AD		 932 (E1000_EICR_RX_QUEUE0 |
933 E1000_EICR_TX_QUEUE0 |
934 E1000_EIMS_OTHER));
2d064c06
AD		 935 break;
936 case e1000_82576:
937 wr32(E1000_IVAR0, E1000_IVAR_VALID);
938 break;
939 default:
940 break;
941 }
9d5c8243 942 }
844290e5 943
7dfc16fa 944 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 945 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
047e0030 946 netdev->name, adapter);
9d5c8243
AK		 947 if (!err)
948 goto request_done;
047e0030 949
9d5c8243
AK		 950 /* fall back to legacy interrupts */
951 igb_reset_interrupt_capability(adapter);
7dfc16fa 952 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 953 }
954
955 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
047e0030 956 netdev->name, adapter);
9d5c8243 957
6cb5e577 958 if (err)
9d5c8243
AK		 959 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
960 err);
9d5c8243
AK		 961
962request_done:
963 return err;
964}
965
966static void igb_free_irq(struct igb_adapter *adapter)
967{
9d5c8243
AK		 968 if (adapter->msix_entries) {
969 int vector = 0, i;
970
047e0030 971 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 972
047e0030
AD		 973 for (i = 0; i < adapter->num_q_vectors; i++) {
974 struct igb_q_vector *q_vector = adapter->q_vector[i];
975 free_irq(adapter->msix_entries[vector++].vector,
976 q_vector);
977 }
978 } else {
979 free_irq(adapter->pdev->irq, adapter);
9d5c8243 980 }
9d5c8243
AK		 981}
982
983/**
984 * igb_irq_disable - Mask off interrupt generation on the NIC
985 * @adapter: board private structure
986 **/
987static void igb_irq_disable(struct igb_adapter *adapter)
988{
989 struct e1000_hw *hw = &adapter->hw;
990
991 if (adapter->msix_entries) {
2dfd1212
AD		 992 u32 regval = rd32(E1000_EIAM);
993 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
994 wr32(E1000_EIMC, adapter->eims_enable_mask);
995 regval = rd32(E1000_EIAC);
996 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 997 }
844290e5
PW		 998
999 wr32(E1000_IAM, 0);
9d5c8243
AK		 1000 wr32(E1000_IMC, ~0);
1001 wrfl();
1002 synchronize_irq(adapter->pdev->irq);
1003}
1004
1005/**
1006 * igb_irq_enable - Enable default interrupt generation settings
1007 * @adapter: board private structure
1008 **/
1009static void igb_irq_enable(struct igb_adapter *adapter)
1010{
1011 struct e1000_hw *hw = &adapter->hw;
1012
1013 if (adapter->msix_entries) {
2dfd1212
AD		 1014 u32 regval = rd32(E1000_EIAC);
1015 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1016 regval = rd32(E1000_EIAM);
1017 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1018 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 1019 if (adapter->vfs_allocated_count)
1020 wr32(E1000_MBVFIMR, 0xFF);
1021 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
1022 E1000_IMS_DOUTSYNC));
844290e5
PW		 1023 } else {
1024 wr32(E1000_IMS, IMS_ENABLE_MASK);
1025 wr32(E1000_IAM, IMS_ENABLE_MASK);
1026 }
9d5c8243
AK		 1027}
1028
1029static void igb_update_mng_vlan(struct igb_adapter *adapter)
1030{
1031 struct net_device *netdev = adapter->netdev;
1032 u16 vid = adapter->hw.mng_cookie.vlan_id;
1033 u16 old_vid = adapter->mng_vlan_id;
1034 if (adapter->vlgrp) {
1035 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
1036 if (adapter->hw.mng_cookie.status &
1037 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1038 igb_vlan_rx_add_vid(netdev, vid);
1039 adapter->mng_vlan_id = vid;
1040 } else
1041 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1042
1043 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1044 (vid != old_vid) &&
1045 !vlan_group_get_device(adapter->vlgrp, old_vid))
1046 igb_vlan_rx_kill_vid(netdev, old_vid);
1047 } else
1048 adapter->mng_vlan_id = vid;
1049 }
1050}
1051
1052/**
1053 * igb_release_hw_control - release control of the h/w to f/w
1054 * @adapter: address of board private structure
1055 *
1056 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1057 * For ASF and Pass Through versions of f/w this means that the
1058 * driver is no longer loaded.
1059 *
1060 **/
1061static void igb_release_hw_control(struct igb_adapter *adapter)
1062{
1063 struct e1000_hw *hw = &adapter->hw;
1064 u32 ctrl_ext;
1065
1066 /* Let firmware take over control of h/w */
1067 ctrl_ext = rd32(E1000_CTRL_EXT);
1068 wr32(E1000_CTRL_EXT,
1069 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1070}
1071
1072
1073/**
1074 * igb_get_hw_control - get control of the h/w from f/w
1075 * @adapter: address of board private structure
1076 *
1077 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1078 * For ASF and Pass Through versions of f/w this means that
1079 * the driver is loaded.
1080 *
1081 **/
1082static void igb_get_hw_control(struct igb_adapter *adapter)
1083{
1084 struct e1000_hw *hw = &adapter->hw;
1085 u32 ctrl_ext;
1086
1087 /* Let firmware know the driver has taken over */
1088 ctrl_ext = rd32(E1000_CTRL_EXT);
1089 wr32(E1000_CTRL_EXT,
1090 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1091}
1092
9d5c8243
AK		 1093/**
1094 * igb_configure - configure the hardware for RX and TX
1095 * @adapter: private board structure
1096 **/
1097static void igb_configure(struct igb_adapter *adapter)
1098{
1099 struct net_device *netdev = adapter->netdev;
1100 int i;
1101
1102 igb_get_hw_control(adapter);
ff41f8dc 1103 igb_set_rx_mode(netdev);
9d5c8243
AK		 1104
1105 igb_restore_vlan(adapter);
9d5c8243 1106
85b430b4 1107 igb_setup_tctl(adapter);
9d5c8243 1108 igb_setup_rctl(adapter);
85b430b4
AD		 1109
1110 igb_configure_tx(adapter);
9d5c8243 1111 igb_configure_rx(adapter);
662d7205
AD		 1112
1113 igb_rx_fifo_flush_82575(&adapter->hw);
1114
c493ea45 1115 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1116 * at least 1 descriptor unused to make sure
1117 * next_to_use != next_to_clean */
1118 for (i = 0; i < adapter->num_rx_queues; i++) {
1119 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 1120 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1121 }
1122
1123
1124 adapter->tx_queue_len = netdev->tx_queue_len;
1125}
1126
1127
1128/**
1129 * igb_up - Open the interface and prepare it to handle traffic
1130 * @adapter: board private structure
1131 **/
1132
1133int igb_up(struct igb_adapter *adapter)
1134{
1135 struct e1000_hw *hw = &adapter->hw;
1136 int i;
1137
1138 /* hardware has been reset, we need to reload some things */
1139 igb_configure(adapter);
1140
1141 clear_bit(__IGB_DOWN, &adapter->state);
1142
047e0030
AD		 1143 for (i = 0; i < adapter->num_q_vectors; i++) {
1144 struct igb_q_vector *q_vector = adapter->q_vector[i];
1145 napi_enable(&q_vector->napi);
1146 }
844290e5 1147 if (adapter->msix_entries)
9d5c8243 1148 igb_configure_msix(adapter);
9d5c8243 1149
4ae196df 1150 igb_vmm_control(adapter);
e1739522
AD		 1151 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1152
9d5c8243
AK		 1153 /* Clear any pending interrupts. */
1154 rd32(E1000_ICR);
1155 igb_irq_enable(adapter);
1156
4cb9be7a
JB		 1157 netif_tx_start_all_queues(adapter->netdev);
1158
9d5c8243
AK		 1159 /* Fire a link change interrupt to start the watchdog. */
1160 wr32(E1000_ICS, E1000_ICS_LSC);
1161 return 0;
1162}
1163
1164void igb_down(struct igb_adapter *adapter)
1165{
1166 struct e1000_hw *hw = &adapter->hw;
1167 struct net_device *netdev = adapter->netdev;
1168 u32 tctl, rctl;
1169 int i;
1170
1171 /* signal that we're down so the interrupt handler does not
1172 * reschedule our watchdog timer */
1173 set_bit(__IGB_DOWN, &adapter->state);
1174
1175 /* disable receives in the hardware */
1176 rctl = rd32(E1000_RCTL);
1177 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1178 /* flush and sleep below */
1179
fd2ea0a7 1180 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1181
1182 /* disable transmits in the hardware */
1183 tctl = rd32(E1000_TCTL);
1184 tctl &= ~E1000_TCTL_EN;
1185 wr32(E1000_TCTL, tctl);
1186 /* flush both disables and wait for them to finish */
1187 wrfl();
1188 msleep(10);
1189
047e0030
AD		 1190 for (i = 0; i < adapter->num_q_vectors; i++) {
1191 struct igb_q_vector *q_vector = adapter->q_vector[i];
1192 napi_disable(&q_vector->napi);
1193 }
9d5c8243 1194
9d5c8243
AK		 1195 igb_irq_disable(adapter);
1196
1197 del_timer_sync(&adapter->watchdog_timer);
1198 del_timer_sync(&adapter->phy_info_timer);
1199
1200 netdev->tx_queue_len = adapter->tx_queue_len;
1201 netif_carrier_off(netdev);
04fe6358
AD		 1202
1203 /* record the stats before reset*/
1204 igb_update_stats(adapter);
1205
9d5c8243
AK		 1206 adapter->link_speed = 0;
1207 adapter->link_duplex = 0;
1208
3023682e
JK		 1209 if (!pci_channel_offline(adapter->pdev))
1210 igb_reset(adapter);
9d5c8243
AK		 1211 igb_clean_all_tx_rings(adapter);
1212 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1213#ifdef CONFIG_IGB_DCA
1214
1215 /* since we reset the hardware DCA settings were cleared */
1216 igb_setup_dca(adapter);
1217#endif
9d5c8243
AK		 1218}
1219
1220void igb_reinit_locked(struct igb_adapter *adapter)
1221{
1222 WARN_ON(in_interrupt());
1223 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1224 msleep(1);
1225 igb_down(adapter);
1226 igb_up(adapter);
1227 clear_bit(__IGB_RESETTING, &adapter->state);
1228}
1229
1230void igb_reset(struct igb_adapter *adapter)
1231{
1232 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1233 struct e1000_mac_info *mac = &hw->mac;
1234 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1235 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1236 u16 hwm;
1237
1238 /* Repartition Pba for greater than 9k mtu
1239 * To take effect CTRL.RST is required.
1240 */
fa4dfae0
AD		 1241 switch (mac->type) {
1242 case e1000_82576:
2d064c06 1243 pba = E1000_PBA_64K;
fa4dfae0
AD		 1244 break;
1245 case e1000_82575:
1246 default:
1247 pba = E1000_PBA_34K;
1248 break;
2d064c06 1249 }
9d5c8243 1250
2d064c06
AD		 1251 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1252 (mac->type < e1000_82576)) {
9d5c8243
AK		 1253 /* adjust PBA for jumbo frames */
1254 wr32(E1000_PBA, pba);
1255
1256 /* To maintain wire speed transmits, the Tx FIFO should be
1257 * large enough to accommodate two full transmit packets,
1258 * rounded up to the next 1KB and expressed in KB. Likewise,
1259 * the Rx FIFO should be large enough to accommodate at least
1260 * one full receive packet and is similarly rounded up and
1261 * expressed in KB. */
1262 pba = rd32(E1000_PBA);
1263 /* upper 16 bits has Tx packet buffer allocation size in KB */
1264 tx_space = pba >> 16;
1265 /* lower 16 bits has Rx packet buffer allocation size in KB */
1266 pba &= 0xffff;
1267 /* the tx fifo also stores 16 bytes of information about the tx
1268 * but don't include ethernet FCS because hardware appends it */
1269 min_tx_space = (adapter->max_frame_size +
85e8d004 1270 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1271 ETH_FCS_LEN) * 2;
1272 min_tx_space = ALIGN(min_tx_space, 1024);
1273 min_tx_space >>= 10;
1274 /* software strips receive CRC, so leave room for it */
1275 min_rx_space = adapter->max_frame_size;
1276 min_rx_space = ALIGN(min_rx_space, 1024);
1277 min_rx_space >>= 10;
1278
1279 /* If current Tx allocation is less than the min Tx FIFO size,
1280 * and the min Tx FIFO size is less than the current Rx FIFO
1281 * allocation, take space away from current Rx allocation */
1282 if (tx_space < min_tx_space &&
1283 ((min_tx_space - tx_space) < pba)) {
1284 pba = pba - (min_tx_space - tx_space);
1285
1286 /* if short on rx space, rx wins and must trump tx
1287 * adjustment */
1288 if (pba < min_rx_space)
1289 pba = min_rx_space;
1290 }
2d064c06 1291 wr32(E1000_PBA, pba);
9d5c8243 1292 }
9d5c8243
AK		 1293
1294 /* flow control settings */
1295 /* The high water mark must be low enough to fit one full frame
1296 * (or the size used for early receive) above it in the Rx FIFO.
1297 * Set it to the lower of:
1298 * - 90% of the Rx FIFO size, or
1299 * - the full Rx FIFO size minus one full frame */
1300 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1301 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1302
2d064c06
AD		 1303 if (mac->type < e1000_82576) {
1304 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1305 fc->low_water = fc->high_water - 8;
1306 } else {
1307 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1308 fc->low_water = fc->high_water - 16;
1309 }
9d5c8243
AK		 1310 fc->pause_time = 0xFFFF;
1311 fc->send_xon = 1;
0cce119a 1312 fc->current_mode = fc->requested_mode;
9d5c8243 1313
4ae196df
AD		 1314 /* disable receive for all VFs and wait one second */
1315 if (adapter->vfs_allocated_count) {
1316 int i;
1317 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1318 adapter->vf_data[i].clear_to_send = false;
1319
1320 /* ping all the active vfs to let them know we are going down */
1321 igb_ping_all_vfs(adapter);
1322
1323 /* disable transmits and receives */
1324 wr32(E1000_VFRE, 0);
1325 wr32(E1000_VFTE, 0);
1326 }
1327
9d5c8243
AK		 1328 /* Allow time for pending master requests to run */
1329 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1330 wr32(E1000_WUC, 0);
1331
1332 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1333 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1334
1335 igb_update_mng_vlan(adapter);
1336
1337 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1338 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1339
1340 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1341 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1342}
1343
2e5c6922
SH		 1344static const struct net_device_ops igb_netdev_ops = {
1345 .ndo_open = igb_open,
1346 .ndo_stop = igb_close,
00829823 1347 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1348 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1349 .ndo_set_rx_mode = igb_set_rx_mode,
1350 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1351 .ndo_set_mac_address = igb_set_mac,
1352 .ndo_change_mtu = igb_change_mtu,
1353 .ndo_do_ioctl = igb_ioctl,
1354 .ndo_tx_timeout = igb_tx_timeout,
1355 .ndo_validate_addr = eth_validate_addr,
1356 .ndo_vlan_rx_register = igb_vlan_rx_register,
1357 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1358 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1359#ifdef CONFIG_NET_POLL_CONTROLLER
1360 .ndo_poll_controller = igb_netpoll,
1361#endif
1362};
1363
9d5c8243
AK		 1364/**
1365 * igb_probe - Device Initialization Routine
1366 * @pdev: PCI device information struct
1367 * @ent: entry in igb_pci_tbl
1368 *
1369 * Returns 0 on success, negative on failure
1370 *
1371 * igb_probe initializes an adapter identified by a pci_dev structure.
1372 * The OS initialization, configuring of the adapter private structure,
1373 * and a hardware reset occur.
1374 **/
1375static int __devinit igb_probe(struct pci_dev *pdev,
1376 const struct pci_device_id *ent)
1377{
1378 struct net_device *netdev;
1379 struct igb_adapter *adapter;
1380 struct e1000_hw *hw;
1381 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1382 unsigned long mmio_start, mmio_len;
2d6a5e95 1383 int err, pci_using_dac;
682337fe 1384 u16 eeprom_data = 0;
9d5c8243
AK		 1385 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1386 u32 part_num;
1387
aed5dec3 1388 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1389 if (err)
1390 return err;
1391
1392 pci_using_dac = 0;
6a35528a 1393 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1394 if (!err) {
6a35528a 1395 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1396 if (!err)
1397 pci_using_dac = 1;
1398 } else {
284901a9 1399 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1400 if (err) {
284901a9 1401 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1402 if (err) {
1403 dev_err(&pdev->dev, "No usable DMA "
1404 "configuration, aborting\n");
1405 goto err_dma;
1406 }
1407 }
1408 }
1409
aed5dec3
AD		 1410 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1411 IORESOURCE_MEM),
1412 igb_driver_name);
9d5c8243
AK		 1413 if (err)
1414 goto err_pci_reg;
1415
19d5afd4 1416 pci_enable_pcie_error_reporting(pdev);
40a914fa 1417
9d5c8243 1418 pci_set_master(pdev);
c682fc23 1419 pci_save_state(pdev);
9d5c8243
AK		 1420
1421 err = -ENOMEM;
1bfaf07b
AD		 1422 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1423 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1424 if (!netdev)
1425 goto err_alloc_etherdev;
1426
1427 SET_NETDEV_DEV(netdev, &pdev->dev);
1428
1429 pci_set_drvdata(pdev, netdev);
1430 adapter = netdev_priv(netdev);
1431 adapter->netdev = netdev;
1432 adapter->pdev = pdev;
1433 hw = &adapter->hw;
1434 hw->back = adapter;
1435 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1436
1437 mmio_start = pci_resource_start(pdev, 0);
1438 mmio_len = pci_resource_len(pdev, 0);
1439
1440 err = -EIO;
28b0759c
AD		 1441 hw->hw_addr = ioremap(mmio_start, mmio_len);
1442 if (!hw->hw_addr)
9d5c8243
AK		 1443 goto err_ioremap;
1444
2e5c6922 1445 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1446 igb_set_ethtool_ops(netdev);
9d5c8243 1447 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1448
1449 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1450
1451 netdev->mem_start = mmio_start;
1452 netdev->mem_end = mmio_start + mmio_len;
1453
9d5c8243
AK		 1454 /* PCI config space info */
1455 hw->vendor_id = pdev->vendor;
1456 hw->device_id = pdev->device;
1457 hw->revision_id = pdev->revision;
1458 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1459 hw->subsystem_device_id = pdev->subsystem_device;
1460
1461 /* setup the private structure */
1462 hw->back = adapter;
1463 /* Copy the default MAC, PHY and NVM function pointers */
1464 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1465 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1466 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1467 /* Initialize skew-specific constants */
1468 err = ei->get_invariants(hw);
1469 if (err)
450c87c8 1470 goto err_sw_init;
9d5c8243 1471
2a3abf6d
AD		 1472#ifdef CONFIG_PCI_IOV
1473 /* since iov functionality isn't critical to base device function we
1474 * can accept failure. If it fails we don't allow iov to be enabled */
1475 if (hw->mac.type == e1000_82576) {
1476 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1477 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1478 int i;
1479 unsigned char mac_addr[ETH_ALEN];
1480
9ca046d5 1481 if (num_vfs) {
2a3abf6d
AD		 1482 adapter->vf_data = kcalloc(num_vfs,
1483 sizeof(struct vf_data_storage),
1484 GFP_KERNEL);
9ca046d5
AD		 1485 if (!adapter->vf_data) {
1486 dev_err(&pdev->dev,
1487 "Could not allocate VF private data - "
1488 "IOV enable failed\n");
2a3abf6d 1489 } else {
9ca046d5
AD		 1490 err = pci_enable_sriov(pdev, num_vfs);
1491 if (!err) {
1492 adapter->vfs_allocated_count = num_vfs;
1493 dev_info(&pdev->dev,
1494 "%d vfs allocated\n",
1495 num_vfs);
1496 for (i = 0;
1497 i < adapter->vfs_allocated_count;
1498 i++) {
1499 random_ether_addr(mac_addr);
1500 igb_set_vf_mac(adapter, i,
1501 mac_addr);
1502 }
1503 } else {
1504 kfree(adapter->vf_data);
1505 adapter->vf_data = NULL;
1506 }
2a3abf6d
AD		 1507 }
1508 }
1509 }
1510
1511#endif
450c87c8 1512 /* setup the private structure */
9d5c8243
AK		 1513 err = igb_sw_init(adapter);
1514 if (err)
1515 goto err_sw_init;
1516
1517 igb_get_bus_info_pcie(hw);
1518
7dfc16fa
AD		 1519 /* set flags */
1520 switch (hw->mac.type) {
7dfc16fa 1521 case e1000_82575:
7dfc16fa
AD		 1522 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1523 break;
bbd98fe4 1524 case e1000_82576:
7dfc16fa
AD		 1525 default:
1526 break;
1527 }
1528
9d5c8243
AK		 1529 hw->phy.autoneg_wait_to_complete = false;
1530 hw->mac.adaptive_ifs = true;
1531
1532 /* Copper options */
1533 if (hw->phy.media_type == e1000_media_type_copper) {
1534 hw->phy.mdix = AUTO_ALL_MODES;
1535 hw->phy.disable_polarity_correction = false;
1536 hw->phy.ms_type = e1000_ms_hw_default;
1537 }
1538
1539 if (igb_check_reset_block(hw))
1540 dev_info(&pdev->dev,
1541 "PHY reset is blocked due to SOL/IDER session.\n");
1542
1543 netdev->features = NETIF_F_SG |
7d8eb29e 1544 NETIF_F_IP_CSUM |
9d5c8243
AK		 1545 NETIF_F_HW_VLAN_TX |
1546 NETIF_F_HW_VLAN_RX |
1547 NETIF_F_HW_VLAN_FILTER;
1548
7d8eb29e 1549 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1550 netdev->features |= NETIF_F_TSO;
9d5c8243 1551 netdev->features |= NETIF_F_TSO6;
48f29ffc 1552
5c0999b7 1553 netdev->features |= NETIF_F_GRO;
d3352520 1554
48f29ffc
JK		 1555 netdev->vlan_features |= NETIF_F_TSO;
1556 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1557 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1558 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1559 netdev->vlan_features |= NETIF_F_SG;
1560
9d5c8243
AK		 1561 if (pci_using_dac)
1562 netdev->features |= NETIF_F_HIGHDMA;
1563
b9473560
JB		 1564 if (adapter->hw.mac.type == e1000_82576)
1565 netdev->features |= NETIF_F_SCTP_CSUM;
1566
9d5c8243
AK		 1567 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1568
1569 /* before reading the NVM, reset the controller to put the device in a
1570 * known good starting state */
1571 hw->mac.ops.reset_hw(hw);
1572
1573 /* make sure the NVM is good */
1574 if (igb_validate_nvm_checksum(hw) < 0) {
1575 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1576 err = -EIO;
1577 goto err_eeprom;
1578 }
1579
1580 /* copy the MAC address out of the NVM */
1581 if (hw->mac.ops.read_mac_addr(hw))
1582 dev_err(&pdev->dev, "NVM Read Error\n");
1583
1584 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1585 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1586
1587 if (!is_valid_ether_addr(netdev->perm_addr)) {
1588 dev_err(&pdev->dev, "Invalid MAC Address\n");
1589 err = -EIO;
1590 goto err_eeprom;
1591 }
1592
0e340485
AD		 1593 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1594 (unsigned long) adapter);
1595 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1596 (unsigned long) adapter);
9d5c8243
AK		 1597
1598 INIT_WORK(&adapter->reset_task, igb_reset_task);
1599 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1600
450c87c8 1601 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1602 adapter->fc_autoneg = true;
1603 hw->mac.autoneg = true;
1604 hw->phy.autoneg_advertised = 0x2f;
1605
0cce119a
AD		 1606 hw->fc.requested_mode = e1000_fc_default;
1607 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1608
cbd347ad 1609 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1610 adapter->itr = IGB_START_ITR;
1611
1612 igb_validate_mdi_setting(hw);
1613
9d5c8243
AK		 1614 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1615 * enable the ACPI Magic Packet filter
1616 */
1617
a2cf8b6c 1618 if (hw->bus.func == 0)
312c75ae 1619 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1620 else if (hw->bus.func == 1)
1621 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1622
1623 if (eeprom_data & eeprom_apme_mask)
1624 adapter->eeprom_wol |= E1000_WUFC_MAG;
1625
1626 /* now that we have the eeprom settings, apply the special cases where
1627 * the eeprom may be wrong or the board simply won't support wake on
1628 * lan on a particular port */
1629 switch (pdev->device) {
1630 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1631 adapter->eeprom_wol = 0;
1632 break;
1633 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1634 case E1000_DEV_ID_82576_FIBER:
1635 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1636 /* Wake events only supported on port A for dual fiber
1637 * regardless of eeprom setting */
1638 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1639 adapter->eeprom_wol = 0;
1640 break;
c8ea5ea9
AD		 1641 case E1000_DEV_ID_82576_QUAD_COPPER:
1642 /* if quad port adapter, disable WoL on all but port A */
1643 if (global_quad_port_a != 0)
1644 adapter->eeprom_wol = 0;
1645 else
1646 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1647 /* Reset for multiple quad port adapters */
1648 if (++global_quad_port_a == 4)
1649 global_quad_port_a = 0;
1650 break;
9d5c8243
AK		 1651 }
1652
1653 /* initialize the wol settings based on the eeprom settings */
1654 adapter->wol = adapter->eeprom_wol;
e1b86d84 1655 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1656
1657 /* reset the hardware with the new settings */
1658 igb_reset(adapter);
1659
1660 /* let the f/w know that the h/w is now under the control of the
1661 * driver. */
1662 igb_get_hw_control(adapter);
1663
9d5c8243
AK		 1664 strcpy(netdev->name, "eth%d");
1665 err = register_netdev(netdev);
1666 if (err)
1667 goto err_register;
1668
b168dfc5
JB		 1669 /* carrier off reporting is important to ethtool even BEFORE open */
1670 netif_carrier_off(netdev);
1671
421e02f0 1672#ifdef CONFIG_IGB_DCA
bbd98fe4 1673 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1674 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1675 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1676 igb_setup_dca(adapter);
1677 }
1678#endif
1679
38c845c7
PO		 1680 /*
1681 * Initialize hardware timer: we keep it running just in case
1682 * that some program needs it later on.
1683 */
1684 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1685 adapter->cycles.read = igb_read_clock;
1686 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1687 adapter->cycles.mult = 1;
1688 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1689 wr32(E1000_TIMINCA,
1690 (1<<24) |
1691 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1692#if 0
1693 /*
1694 * Avoid rollover while we initialize by resetting the time counter.
1695 */
1696 wr32(E1000_SYSTIML, 0x00000000);
1697 wr32(E1000_SYSTIMH, 0x00000000);
1698#else
1699 /*
1700 * Set registers so that rollover occurs soon to test this.
1701 */
1702 wr32(E1000_SYSTIML, 0x00000000);
1703 wr32(E1000_SYSTIMH, 0xFF800000);
1704#endif
1705 wrfl();
1706 timecounter_init(&adapter->clock,
1707 &adapter->cycles,
1708 ktime_to_ns(ktime_get_real()));
1709
33af6bcc
PO		 1710 /*
1711 * Synchronize our NIC clock against system wall clock. NIC
1712 * time stamp reading requires ~3us per sample, each sample
1713 * was pretty stable even under load => only require 10
1714 * samples for each offset comparison.
1715 */
1716 memset(&adapter->compare, 0, sizeof(adapter->compare));
1717 adapter->compare.source = &adapter->clock;
1718 adapter->compare.target = ktime_get_real;
1719 adapter->compare.num_samples = 10;
1720 timecompare_update(&adapter->compare, 0);
1721
38c845c7
PO		 1722#ifdef DEBUG
1723 {
1724 char buffer[160];
1725 printk(KERN_DEBUG
1726 "igb: %s: hw %p initialized timer\n",
1727 igb_get_time_str(adapter, buffer),
1728 &adapter->hw);
1729 }
1730#endif
1731
9d5c8243
AK		 1732 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1733 /* print bus type/speed/width info */
7c510e4b 1734 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1735 netdev->name,
1736 ((hw->bus.speed == e1000_bus_speed_2500)
1737 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1738 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1739 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1740 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1741 "unknown"),
7c510e4b 1742 netdev->dev_addr);
9d5c8243
AK		 1743
1744 igb_read_part_num(hw, &part_num);
1745 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1746 (part_num >> 8), (part_num & 0xff));
1747
1748 dev_info(&pdev->dev,
1749 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1750 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1751 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1752 adapter->num_rx_queues, adapter->num_tx_queues);
1753
9d5c8243
AK		 1754 return 0;
1755
1756err_register:
1757 igb_release_hw_control(adapter);
1758err_eeprom:
1759 if (!igb_check_reset_block(hw))
f5f4cf08 1760 igb_reset_phy(hw);
9d5c8243
AK		 1761
1762 if (hw->flash_address)
1763 iounmap(hw->flash_address);
9d5c8243 1764err_sw_init:
047e0030 1765 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1766 iounmap(hw->hw_addr);
1767err_ioremap:
1768 free_netdev(netdev);
1769err_alloc_etherdev:
aed5dec3
AD		 1770 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1771 IORESOURCE_MEM));
9d5c8243
AK		 1772err_pci_reg:
1773err_dma:
1774 pci_disable_device(pdev);
1775 return err;
1776}
1777
1778/**
1779 * igb_remove - Device Removal Routine
1780 * @pdev: PCI device information struct
1781 *
1782 * igb_remove is called by the PCI subsystem to alert the driver
1783 * that it should release a PCI device. The could be caused by a
1784 * Hot-Plug event, or because the driver is going to be removed from
1785 * memory.
1786 **/
1787static void __devexit igb_remove(struct pci_dev *pdev)
1788{
1789 struct net_device *netdev = pci_get_drvdata(pdev);
1790 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1791 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1792
1793 /* flush_scheduled work may reschedule our watchdog task, so
1794 * explicitly disable watchdog tasks from being rescheduled */
1795 set_bit(__IGB_DOWN, &adapter->state);
1796 del_timer_sync(&adapter->watchdog_timer);
1797 del_timer_sync(&adapter->phy_info_timer);
1798
1799 flush_scheduled_work();
1800
421e02f0 1801#ifdef CONFIG_IGB_DCA
7dfc16fa 1802 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1803 dev_info(&pdev->dev, "DCA disabled\n");
1804 dca_remove_requester(&pdev->dev);
7dfc16fa 1805 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1806 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1807 }
1808#endif
1809
9d5c8243
AK		 1810 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1811 * would have already happened in close and is redundant. */
1812 igb_release_hw_control(adapter);
1813
1814 unregister_netdev(netdev);
1815
f5f4cf08
AD		 1816 if (!igb_check_reset_block(&adapter->hw))
1817 igb_reset_phy(&adapter->hw);
9d5c8243 1818
047e0030 1819 igb_clear_interrupt_scheme(adapter);
9d5c8243 1820
37680117
AD		 1821#ifdef CONFIG_PCI_IOV
1822 /* reclaim resources allocated to VFs */
1823 if (adapter->vf_data) {
1824 /* disable iov and allow time for transactions to clear */
1825 pci_disable_sriov(pdev);
1826 msleep(500);
1827
1828 kfree(adapter->vf_data);
1829 adapter->vf_data = NULL;
1830 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1831 msleep(100);
1832 dev_info(&pdev->dev, "IOV Disabled\n");
1833 }
1834#endif
28b0759c
AD		 1835 iounmap(hw->hw_addr);
1836 if (hw->flash_address)
1837 iounmap(hw->flash_address);
aed5dec3
AD		 1838 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1839 IORESOURCE_MEM));
9d5c8243
AK		 1840
1841 free_netdev(netdev);
1842
19d5afd4 1843 pci_disable_pcie_error_reporting(pdev);
40a914fa 1844
9d5c8243
AK		 1845 pci_disable_device(pdev);
1846}
1847
1848/**
1849 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1850 * @adapter: board private structure to initialize
1851 *
1852 * igb_sw_init initializes the Adapter private data structure.
1853 * Fields are initialized based on PCI device information and
1854 * OS network device settings (MTU size).
1855 **/
1856static int __devinit igb_sw_init(struct igb_adapter *adapter)
1857{
1858 struct e1000_hw *hw = &adapter->hw;
1859 struct net_device *netdev = adapter->netdev;
1860 struct pci_dev *pdev = adapter->pdev;
1861
1862 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1863
68fd9910
AD		 1864 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1865 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243 1866 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9d5c8243
AK		 1867 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1868 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1869
661086df
PWJ		 1870 /* This call may decrease the number of queues depending on
1871 * interrupt mode. */
047e0030 1872 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1873 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1874 return -ENOMEM;
1875 }
1876
1877 /* Explicitly disable IRQ since the NIC can be in any state. */
1878 igb_irq_disable(adapter);
1879
1880 set_bit(__IGB_DOWN, &adapter->state);
1881 return 0;
1882}
1883
1884/**
1885 * igb_open - Called when a network interface is made active
1886 * @netdev: network interface device structure
1887 *
1888 * Returns 0 on success, negative value on failure
1889 *
1890 * The open entry point is called when a network interface is made
1891 * active by the system (IFF_UP). At this point all resources needed
1892 * for transmit and receive operations are allocated, the interrupt
1893 * handler is registered with the OS, the watchdog timer is started,
1894 * and the stack is notified that the interface is ready.
1895 **/
1896static int igb_open(struct net_device *netdev)
1897{
1898 struct igb_adapter *adapter = netdev_priv(netdev);
1899 struct e1000_hw *hw = &adapter->hw;
1900 int err;
1901 int i;
1902
1903 /* disallow open during test */
1904 if (test_bit(__IGB_TESTING, &adapter->state))
1905 return -EBUSY;
1906
b168dfc5
JB		 1907 netif_carrier_off(netdev);
1908
9d5c8243
AK		 1909 /* allocate transmit descriptors */
1910 err = igb_setup_all_tx_resources(adapter);
1911 if (err)
1912 goto err_setup_tx;
1913
1914 /* allocate receive descriptors */
1915 err = igb_setup_all_rx_resources(adapter);
1916 if (err)
1917 goto err_setup_rx;
1918
1919 /* e1000_power_up_phy(adapter); */
1920
1921 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1922 if ((adapter->hw.mng_cookie.status &
1923 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1924 igb_update_mng_vlan(adapter);
1925
1926 /* before we allocate an interrupt, we must be ready to handle it.
1927 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1928 * as soon as we call pci_request_irq, so we have to setup our
1929 * clean_rx handler before we do so. */
1930 igb_configure(adapter);
1931
4ae196df 1932 igb_vmm_control(adapter);
e1739522
AD		 1933 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1934
9d5c8243
AK		 1935 err = igb_request_irq(adapter);
1936 if (err)
1937 goto err_req_irq;
1938
1939 /* From here on the code is the same as igb_up() */
1940 clear_bit(__IGB_DOWN, &adapter->state);
1941
047e0030
AD		 1942 for (i = 0; i < adapter->num_q_vectors; i++) {
1943 struct igb_q_vector *q_vector = adapter->q_vector[i];
1944 napi_enable(&q_vector->napi);
1945 }
9d5c8243
AK		 1946
1947 /* Clear any pending interrupts. */
1948 rd32(E1000_ICR);
844290e5
PW		 1949
1950 igb_irq_enable(adapter);
1951
d55b53ff
JK		 1952 netif_tx_start_all_queues(netdev);
1953
9d5c8243
AK		 1954 /* Fire a link status change interrupt to start the watchdog. */
1955 wr32(E1000_ICS, E1000_ICS_LSC);
1956
1957 return 0;
1958
1959err_req_irq:
1960 igb_release_hw_control(adapter);
1961 /* e1000_power_down_phy(adapter); */
1962 igb_free_all_rx_resources(adapter);
1963err_setup_rx:
1964 igb_free_all_tx_resources(adapter);
1965err_setup_tx:
1966 igb_reset(adapter);
1967
1968 return err;
1969}
1970
1971/**
1972 * igb_close - Disables a network interface
1973 * @netdev: network interface device structure
1974 *
1975 * Returns 0, this is not allowed to fail
1976 *
1977 * The close entry point is called when an interface is de-activated
1978 * by the OS. The hardware is still under the driver's control, but
1979 * needs to be disabled. A global MAC reset is issued to stop the
1980 * hardware, and all transmit and receive resources are freed.
1981 **/
1982static int igb_close(struct net_device *netdev)
1983{
1984 struct igb_adapter *adapter = netdev_priv(netdev);
1985
1986 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1987 igb_down(adapter);
1988
1989 igb_free_irq(adapter);
1990
1991 igb_free_all_tx_resources(adapter);
1992 igb_free_all_rx_resources(adapter);
1993
1994 /* kill manageability vlan ID if supported, but not if a vlan with
1995 * the same ID is registered on the host OS (let 8021q kill it) */
1996 if ((adapter->hw.mng_cookie.status &
1997 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1998 !(adapter->vlgrp &&
1999 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
2000 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2001
2002 return 0;
2003}
2004
2005/**
2006 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2007 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2008 *
2009 * Return 0 on success, negative on failure
2010 **/
80785298 2011int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2012{
80785298 2013 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 2014 int size;
2015
2016 size = sizeof(struct igb_buffer) * tx_ring->count;
2017 tx_ring->buffer_info = vmalloc(size);
2018 if (!tx_ring->buffer_info)
2019 goto err;
2020 memset(tx_ring->buffer_info, 0, size);
2021
2022 /* round up to nearest 4K */
85e8d004 2023 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2024 tx_ring->size = ALIGN(tx_ring->size, 4096);
2025
2026 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2027 &tx_ring->dma);
2028
2029 if (!tx_ring->desc)
2030 goto err;
2031
9d5c8243
AK		 2032 tx_ring->next_to_use = 0;
2033 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2034 return 0;
2035
2036err:
2037 vfree(tx_ring->buffer_info);
047e0030 2038 dev_err(&pdev->dev,
9d5c8243
AK		 2039 "Unable to allocate memory for the transmit descriptor ring\n");
2040 return -ENOMEM;
2041}
2042
2043/**
2044 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2045 * (Descriptors) for all queues
2046 * @adapter: board private structure
2047 *
2048 * Return 0 on success, negative on failure
2049 **/
2050static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2051{
2052 int i, err = 0;
661086df 2053 int r_idx;
9d5c8243
AK		 2054
2055 for (i = 0; i < adapter->num_tx_queues; i++) {
80785298 2056 err = igb_setup_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2057 if (err) {
2058 dev_err(&adapter->pdev->dev,
2059 "Allocation for Tx Queue %u failed\n", i);
2060 for (i--; i >= 0; i--)
3b644cf6 2061 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2062 break;
2063 }
2064 }
2065
661086df
PWJ		 2066 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
2067 r_idx = i % adapter->num_tx_queues;
2068 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 2069 }
9d5c8243
AK		 2070 return err;
2071}
2072
2073/**
85b430b4
AD		 2074 * igb_setup_tctl - configure the transmit control registers
2075 * @adapter: Board private structure
9d5c8243 2076 **/
85b430b4 2077static void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2078{
9d5c8243
AK		 2079 struct e1000_hw *hw = &adapter->hw;
2080 u32 tctl;
9d5c8243 2081
85b430b4
AD		 2082 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2083 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2084
2085 /* Program the Transmit Control Register */
9d5c8243
AK		 2086 tctl = rd32(E1000_TCTL);
2087 tctl &= ~E1000_TCTL_CT;
2088 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2089 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2090
2091 igb_config_collision_dist(hw);
2092
9d5c8243
AK		 2093 /* Enable transmits */
2094 tctl |= E1000_TCTL_EN;
2095
2096 wr32(E1000_TCTL, tctl);
2097}
2098
85b430b4
AD		 2099/**
2100 * igb_configure_tx_ring - Configure transmit ring after Reset
2101 * @adapter: board private structure
2102 * @ring: tx ring to configure
2103 *
2104 * Configure a transmit ring after a reset.
2105 **/
2106static void igb_configure_tx_ring(struct igb_adapter *adapter,
2107 struct igb_ring *ring)
2108{
2109 struct e1000_hw *hw = &adapter->hw;
2110 u32 txdctl;
2111 u64 tdba = ring->dma;
2112 int reg_idx = ring->reg_idx;
2113
2114 /* disable the queue */
2115 txdctl = rd32(E1000_TXDCTL(reg_idx));
2116 wr32(E1000_TXDCTL(reg_idx),
2117 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2118 wrfl();
2119 mdelay(10);
2120
2121 wr32(E1000_TDLEN(reg_idx),
2122 ring->count * sizeof(union e1000_adv_tx_desc));
2123 wr32(E1000_TDBAL(reg_idx),
2124 tdba & 0x00000000ffffffffULL);
2125 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2126
fce99e34
AD		 2127 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2128 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2129 writel(0, ring->head);
2130 writel(0, ring->tail);
85b430b4
AD		 2131
2132 txdctl |= IGB_TX_PTHRESH;
2133 txdctl |= IGB_TX_HTHRESH << 8;
2134 txdctl |= IGB_TX_WTHRESH << 16;
2135
2136 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2137 wr32(E1000_TXDCTL(reg_idx), txdctl);
2138}
2139
2140/**
2141 * igb_configure_tx - Configure transmit Unit after Reset
2142 * @adapter: board private structure
2143 *
2144 * Configure the Tx unit of the MAC after a reset.
2145 **/
2146static void igb_configure_tx(struct igb_adapter *adapter)
2147{
2148 int i;
2149
2150 for (i = 0; i < adapter->num_tx_queues; i++)
2151 igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
2152
2153 /* Setup Transmit Descriptor Settings for eop descriptor */
2154 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
2155}
2156
9d5c8243
AK		 2157/**
2158 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2159 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2160 *
2161 * Returns 0 on success, negative on failure
2162 **/
80785298 2163int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2164{
80785298 2165 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 2166 int size, desc_len;
2167
2168 size = sizeof(struct igb_buffer) * rx_ring->count;
2169 rx_ring->buffer_info = vmalloc(size);
2170 if (!rx_ring->buffer_info)
2171 goto err;
2172 memset(rx_ring->buffer_info, 0, size);
2173
2174 desc_len = sizeof(union e1000_adv_rx_desc);
2175
2176 /* Round up to nearest 4K */
2177 rx_ring->size = rx_ring->count * desc_len;
2178 rx_ring->size = ALIGN(rx_ring->size, 4096);
2179
2180 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2181 &rx_ring->dma);
2182
2183 if (!rx_ring->desc)
2184 goto err;
2185
2186 rx_ring->next_to_clean = 0;
2187 rx_ring->next_to_use = 0;
9d5c8243 2188
9d5c8243
AK		 2189 return 0;
2190
2191err:
2192 vfree(rx_ring->buffer_info);
80785298 2193 dev_err(&pdev->dev, "Unable to allocate memory for "
9d5c8243
AK		 2194 "the receive descriptor ring\n");
2195 return -ENOMEM;
2196}
2197
2198/**
2199 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2200 * (Descriptors) for all queues
2201 * @adapter: board private structure
2202 *
2203 * Return 0 on success, negative on failure
2204 **/
2205static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2206{
2207 int i, err = 0;
2208
2209 for (i = 0; i < adapter->num_rx_queues; i++) {
80785298 2210 err = igb_setup_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2211 if (err) {
2212 dev_err(&adapter->pdev->dev,
2213 "Allocation for Rx Queue %u failed\n", i);
2214 for (i--; i >= 0; i--)
3b644cf6 2215 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2216 break;
2217 }
2218 }
2219
2220 return err;
2221}
2222
2223/**
2224 * igb_setup_rctl - configure the receive control registers
2225 * @adapter: Board private structure
2226 **/
2227static void igb_setup_rctl(struct igb_adapter *adapter)
2228{
2229 struct e1000_hw *hw = &adapter->hw;
2230 u32 rctl;
9d5c8243
AK		 2231
2232 rctl = rd32(E1000_RCTL);
2233
2234 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2235 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2236
69d728ba 2237 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2238 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2239
87cb7e8c
AK		 2240 /*
2241 * enable stripping of CRC. It's unlikely this will break BMC
2242 * redirection as it did with e1000. Newer features require
2243 * that the HW strips the CRC.
73cd78f1 2244 */
87cb7e8c 2245 rctl |= E1000_RCTL_SECRC;
9d5c8243 2246
9b07f3d3 2247 /*
ec54d7d6 2248 * disable store bad packets and clear size bits.
9b07f3d3 2249 */
ec54d7d6 2250 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2251
6ec43fe6
AD		 2252 /* enable LPE to prevent packets larger than max_frame_size */
2253 rctl |= E1000_RCTL_LPE;
9d5c8243 2254
952f72a8
AD		 2255 /* disable queue 0 to prevent tail write w/o re-config */
2256 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2257
e1739522
AD		 2258 /* Attention!!! For SR-IOV PF driver operations you must enable
2259 * queue drop for all VF and PF queues to prevent head of line blocking
2260 * if an un-trusted VF does not provide descriptors to hardware.
2261 */
2262 if (adapter->vfs_allocated_count) {
2263 u32 vmolr;
2264
e1739522
AD		 2265 /* set all queue drop enable bits */
2266 wr32(E1000_QDE, ALL_QUEUES);
e1739522 2267
77a22941 2268 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2269 if (rctl & E1000_RCTL_LPE)
2270 vmolr |= E1000_VMOLR_LPE;
77a22941 2271 if (adapter->num_rx_queues > 1)
e1739522 2272 vmolr |= E1000_VMOLR_RSSE;
77a22941 2273 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2274 }
2275
9d5c8243
AK		 2276 wr32(E1000_RCTL, rctl);
2277}
2278
e1739522
AD		 2279/**
2280 * igb_rlpml_set - set maximum receive packet size
2281 * @adapter: board private structure
2282 *
2283 * Configure maximum receivable packet size.
2284 **/
2285static void igb_rlpml_set(struct igb_adapter *adapter)
2286{
2287 u32 max_frame_size = adapter->max_frame_size;
2288 struct e1000_hw *hw = &adapter->hw;
2289 u16 pf_id = adapter->vfs_allocated_count;
2290
2291 if (adapter->vlgrp)
2292 max_frame_size += VLAN_TAG_SIZE;
2293
2294 /* if vfs are enabled we set RLPML to the largest possible request
2295 * size and set the VMOLR RLPML to the size we need */
2296 if (pf_id) {
2297 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2298 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2299 }
2300
2301 wr32(E1000_RLPML, max_frame_size);
2302}
2303
2304/**
2305 * igb_configure_vt_default_pool - Configure VT default pool
2306 * @adapter: board private structure
2307 *
2308 * Configure the default pool
2309 **/
2310static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2311{
2312 struct e1000_hw *hw = &adapter->hw;
2313 u16 pf_id = adapter->vfs_allocated_count;
2314 u32 vtctl;
2315
2316 /* not in sr-iov mode - do nothing */
2317 if (!pf_id)
2318 return;
2319
2320 vtctl = rd32(E1000_VT_CTL);
2321 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2322 E1000_VT_CTL_DISABLE_DEF_POOL);
2323 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2324 wr32(E1000_VT_CTL, vtctl);
2325}
2326
85b430b4
AD		 2327/**
2328 * igb_configure_rx_ring - Configure a receive ring after Reset
2329 * @adapter: board private structure
2330 * @ring: receive ring to be configured
2331 *
2332 * Configure the Rx unit of the MAC after a reset.
2333 **/
2334static void igb_configure_rx_ring(struct igb_adapter *adapter,
2335 struct igb_ring *ring)
2336{
2337 struct e1000_hw *hw = &adapter->hw;
2338 u64 rdba = ring->dma;
2339 int reg_idx = ring->reg_idx;
952f72a8 2340 u32 srrctl, rxdctl;
85b430b4
AD		 2341
2342 /* disable the queue */
2343 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2344 wr32(E1000_RXDCTL(reg_idx),
2345 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2346
2347 /* Set DMA base address registers */
2348 wr32(E1000_RDBAL(reg_idx),
2349 rdba & 0x00000000ffffffffULL);
2350 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2351 wr32(E1000_RDLEN(reg_idx),
2352 ring->count * sizeof(union e1000_adv_rx_desc));
2353
2354 /* initialize head and tail */
fce99e34
AD		 2355 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2356 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2357 writel(0, ring->head);
2358 writel(0, ring->tail);
85b430b4 2359
952f72a8
AD		 2360 /* set descriptor configuration */
2361 if (adapter->rx_buffer_len < IGB_RXBUFFER_1024) {
2362 srrctl = ALIGN(adapter->rx_buffer_len, 64) <<
2363 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2364#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2365 srrctl |= IGB_RXBUFFER_16384 >>
2366 E1000_SRRCTL_BSIZEPKT_SHIFT;
2367#else
2368 srrctl |= (PAGE_SIZE / 2) >>
2369 E1000_SRRCTL_BSIZEPKT_SHIFT;
2370#endif
2371 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2372 } else {
2373 srrctl = ALIGN(adapter->rx_buffer_len, 1024) >>
2374 E1000_SRRCTL_BSIZEPKT_SHIFT;
2375 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2376 }
2377
2378 wr32(E1000_SRRCTL(reg_idx), srrctl);
2379
85b430b4
AD		 2380 /* enable receive descriptor fetching */
2381 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2382 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2383 rxdctl &= 0xFFF00000;
2384 rxdctl |= IGB_RX_PTHRESH;
2385 rxdctl |= IGB_RX_HTHRESH << 8;
2386 rxdctl |= IGB_RX_WTHRESH << 16;
2387 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2388}
2389
9d5c8243
AK		 2390/**
2391 * igb_configure_rx - Configure receive Unit after Reset
2392 * @adapter: board private structure
2393 *
2394 * Configure the Rx unit of the MAC after a reset.
2395 **/
2396static void igb_configure_rx(struct igb_adapter *adapter)
2397{
9d5c8243
AK		 2398 struct e1000_hw *hw = &adapter->hw;
2399 u32 rctl, rxcsum;
9107584e 2400 int i;
9d5c8243
AK		 2401
2402 /* disable receives while setting up the descriptors */
2403 rctl = rd32(E1000_RCTL);
2404 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2405 wrfl();
2406 mdelay(10);
2407
2408 if (adapter->itr_setting > 3)
6eb5a7f1 2409 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2410
2411 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2412 * the Base and Length of the Rx Descriptor Ring */
85b430b4
AD		 2413 for (i = 0; i < adapter->num_rx_queues; i++)
2414 igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
9d5c8243
AK		 2415
2416 if (adapter->num_rx_queues > 1) {
2417 u32 random[10];
2418 u32 mrqc;
2419 u32 j, shift;
2420 union e1000_reta {
2421 u32 dword;
2422 u8 bytes[4];
2423 } reta;
2424
2425 get_random_bytes(&random[0], 40);
2426
2d064c06
AD		 2427 if (hw->mac.type >= e1000_82576)
2428 shift = 0;
2429 else
2430 shift = 6;
9d5c8243
AK		 2431 for (j = 0; j < (32 * 4); j++) {
2432 reta.bytes[j & 3] =
26bc19ec 2433 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2434 if ((j & 3) == 3)
2435 writel(reta.dword,
2436 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2437 }
e1739522
AD		 2438 if (adapter->vfs_allocated_count)
2439 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2440 else
2441 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2442
2443 /* Fill out hash function seeds */
2444 for (j = 0; j < 10; j++)
2445 array_wr32(E1000_RSSRK(0), j, random[j]);
2446
2447 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2448 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2449 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2450 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2451 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2452 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2453 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2454 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2455
9d5c8243 2456 wr32(E1000_MRQC, mrqc);
2844f797 2457 } else if (adapter->vfs_allocated_count) {
e1739522 2458 /* Enable multi-queue for sr-iov */
2844f797 2459 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2460 }
2461
2844f797
AD		 2462 /* Enable Receive Checksum Offload for TCP and UDP */
2463 rxcsum = rd32(E1000_RXCSUM);
2464 /* Disable raw packet checksumming */
2465 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2466
2467 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2468 /* Enable Receive Checksum Offload for SCTP */
2469 rxcsum |= E1000_RXCSUM_CRCOFL;
2470
7beb0146 2471 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2472 wr32(E1000_RXCSUM, rxcsum);
2473
e1739522
AD		 2474 /* Set the default pool for the PF's first queue */
2475 igb_configure_vt_default_pool(adapter);
2476
68d480c4
AD		 2477 /* set UTA to appropriate mode */
2478 igb_set_uta(adapter);
2479
26ad9178
AD		 2480 /* set the correct pool for the PF default MAC address in entry 0 */
2481 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2482 adapter->vfs_allocated_count);
2483
e1739522 2484 igb_rlpml_set(adapter);
9d5c8243
AK		 2485
2486 /* Enable Receives */
2487 wr32(E1000_RCTL, rctl);
2488}
2489
2490/**
2491 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2492 * @tx_ring: Tx descriptor ring for a specific queue
2493 *
2494 * Free all transmit software resources
2495 **/
68fd9910 2496void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2497{
3b644cf6 2498 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2499
2500 vfree(tx_ring->buffer_info);
2501 tx_ring->buffer_info = NULL;
2502
80785298
AD		 2503 pci_free_consistent(tx_ring->pdev, tx_ring->size,
2504 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2505
2506 tx_ring->desc = NULL;
2507}
2508
2509/**
2510 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2511 * @adapter: board private structure
2512 *
2513 * Free all transmit software resources
2514 **/
2515static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2516{
2517 int i;
2518
2519 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2520 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2521}
2522
80785298 2523static void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
9d5c8243
AK		 2524 struct igb_buffer *buffer_info)
2525{
65689fef 2526 buffer_info->dma = 0;
9d5c8243 2527 if (buffer_info->skb) {
80785298
AD		 2528 skb_dma_unmap(&tx_ring->pdev->dev,
2529 buffer_info->skb,
65689fef 2530 DMA_TO_DEVICE);
9d5c8243
AK		 2531 dev_kfree_skb_any(buffer_info->skb);
2532 buffer_info->skb = NULL;
2533 }
2534 buffer_info->time_stamp = 0;
2535 /* buffer_info must be completely set up in the transmit path */
2536}
2537
2538/**
2539 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2540 * @tx_ring: ring to be cleaned
2541 **/
3b644cf6 2542static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 2543{
2544 struct igb_buffer *buffer_info;
2545 unsigned long size;
2546 unsigned int i;
2547
2548 if (!tx_ring->buffer_info)
2549 return;
2550 /* Free all the Tx ring sk_buffs */
2551
2552 for (i = 0; i < tx_ring->count; i++) {
2553 buffer_info = &tx_ring->buffer_info[i];
80785298 2554 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 2555 }
2556
2557 size = sizeof(struct igb_buffer) * tx_ring->count;
2558 memset(tx_ring->buffer_info, 0, size);
2559
2560 /* Zero out the descriptor ring */
2561
2562 memset(tx_ring->desc, 0, tx_ring->size);
2563
2564 tx_ring->next_to_use = 0;
2565 tx_ring->next_to_clean = 0;
2566
fce99e34
AD		 2567 writel(0, tx_ring->head);
2568 writel(0, tx_ring->tail);
9d5c8243
AK		 2569}
2570
2571/**
2572 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2573 * @adapter: board private structure
2574 **/
2575static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2576{
2577 int i;
2578
2579 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2580 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2581}
2582
2583/**
2584 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2585 * @rx_ring: ring to clean the resources from
2586 *
2587 * Free all receive software resources
2588 **/
68fd9910 2589void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2590{
3b644cf6 2591 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2592
2593 vfree(rx_ring->buffer_info);
2594 rx_ring->buffer_info = NULL;
2595
80785298
AD		 2596 pci_free_consistent(rx_ring->pdev, rx_ring->size,
2597 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 2598
2599 rx_ring->desc = NULL;
2600}
2601
2602/**
2603 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2604 * @adapter: board private structure
2605 *
2606 * Free all receive software resources
2607 **/
2608static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2609{
2610 int i;
2611
2612 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2613 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2614}
2615
2616/**
2617 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2618 * @rx_ring: ring to free buffers from
2619 **/
3b644cf6 2620static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2621{
047e0030 2622 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243 2623 struct igb_buffer *buffer_info;
9d5c8243
AK		 2624 unsigned long size;
2625 unsigned int i;
2626
2627 if (!rx_ring->buffer_info)
2628 return;
2629 /* Free all the Rx ring sk_buffs */
2630 for (i = 0; i < rx_ring->count; i++) {
2631 buffer_info = &rx_ring->buffer_info[i];
2632 if (buffer_info->dma) {
80785298
AD		 2633 pci_unmap_single(rx_ring->pdev,
2634 buffer_info->dma,
6ec43fe6
AD		 2635 adapter->rx_buffer_len,
2636 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2637 buffer_info->dma = 0;
2638 }
2639
2640 if (buffer_info->skb) {
2641 dev_kfree_skb(buffer_info->skb);
2642 buffer_info->skb = NULL;
2643 }
6ec43fe6 2644 if (buffer_info->page_dma) {
80785298
AD		 2645 pci_unmap_page(rx_ring->pdev,
2646 buffer_info->page_dma,
6ec43fe6
AD		 2647 PAGE_SIZE / 2,
2648 PCI_DMA_FROMDEVICE);
2649 buffer_info->page_dma = 0;
2650 }
9d5c8243 2651 if (buffer_info->page) {
9d5c8243
AK		 2652 put_page(buffer_info->page);
2653 buffer_info->page = NULL;
bf36c1a0 2654 buffer_info->page_offset = 0;
9d5c8243
AK		 2655 }
2656 }
2657
9d5c8243
AK		 2658 size = sizeof(struct igb_buffer) * rx_ring->count;
2659 memset(rx_ring->buffer_info, 0, size);
2660
2661 /* Zero out the descriptor ring */
2662 memset(rx_ring->desc, 0, rx_ring->size);
2663
2664 rx_ring->next_to_clean = 0;
2665 rx_ring->next_to_use = 0;
2666
fce99e34
AD		 2667 writel(0, rx_ring->head);
2668 writel(0, rx_ring->tail);
9d5c8243
AK		 2669}
2670
2671/**
2672 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2673 * @adapter: board private structure
2674 **/
2675static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2676{
2677 int i;
2678
2679 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2680 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2681}
2682
2683/**
2684 * igb_set_mac - Change the Ethernet Address of the NIC
2685 * @netdev: network interface device structure
2686 * @p: pointer to an address structure
2687 *
2688 * Returns 0 on success, negative on failure
2689 **/
2690static int igb_set_mac(struct net_device *netdev, void *p)
2691{
2692 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2693 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2694 struct sockaddr *addr = p;
2695
2696 if (!is_valid_ether_addr(addr->sa_data))
2697 return -EADDRNOTAVAIL;
2698
2699 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2700 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2701
26ad9178
AD		 2702 /* set the correct pool for the new PF MAC address in entry 0 */
2703 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2704 adapter->vfs_allocated_count);
e1739522 2705
9d5c8243
AK		 2706 return 0;
2707}
2708
2709/**
68d480c4 2710 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2711 * @netdev: network interface device structure
2712 *
68d480c4
AD		 2713 * Writes multicast address list to the MTA hash table.
2714 * Returns: -ENOMEM on failure
2715 * 0 on no addresses written
2716 * X on writing X addresses to MTA
9d5c8243 2717 **/
68d480c4 2718static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2719{
2720 struct igb_adapter *adapter = netdev_priv(netdev);
2721 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2722 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2723 u8 *mta_list;
2724 u32 vmolr = 0;
9d5c8243
AK		 2725 int i;
2726
68d480c4
AD		 2727 if (!netdev->mc_count) {
2728 /* nothing to program, so clear mc list */
2729 igb_update_mc_addr_list(hw, NULL, 0);
2730 igb_restore_vf_multicasts(adapter);
2731 return 0;
2732 }
9d5c8243 2733
68d480c4
AD		 2734 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2735 if (!mta_list)
2736 return -ENOMEM;
ff41f8dc 2737
68d480c4
AD		 2738 /* set vmolr receive overflow multicast bit */
2739 vmolr |= E1000_VMOLR_ROMPE;
2740
2741 /* The shared function expects a packed array of only addresses. */
2742 mc_ptr = netdev->mc_list;
2743
2744 for (i = 0; i < netdev->mc_count; i++) {
2745 if (!mc_ptr)
2746 break;
2747 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2748 mc_ptr = mc_ptr->next;
746b9f02 2749 }
68d480c4
AD		 2750 igb_update_mc_addr_list(hw, mta_list, i);
2751 kfree(mta_list);
2752
2753 return netdev->mc_count;
2754}
2755
2756/**
2757 * igb_write_uc_addr_list - write unicast addresses to RAR table
2758 * @netdev: network interface device structure
2759 *
2760 * Writes unicast address list to the RAR table.
2761 * Returns: -ENOMEM on failure/insufficient address space
2762 * 0 on no addresses written
2763 * X on writing X addresses to the RAR table
2764 **/
2765static int igb_write_uc_addr_list(struct net_device *netdev)
2766{
2767 struct igb_adapter *adapter = netdev_priv(netdev);
2768 struct e1000_hw *hw = &adapter->hw;
2769 unsigned int vfn = adapter->vfs_allocated_count;
2770 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2771 int count = 0;
2772
2773 /* return ENOMEM indicating insufficient memory for addresses */
2774 if (netdev->uc.count > rar_entries)
2775 return -ENOMEM;
9d5c8243 2776
ff41f8dc
AD		 2777 if (netdev->uc.count && rar_entries) {
2778 struct netdev_hw_addr *ha;
2779 list_for_each_entry(ha, &netdev->uc.list, list) {
2780 if (!rar_entries)
2781 break;
26ad9178
AD		 2782 igb_rar_set_qsel(adapter, ha->addr,
2783 rar_entries--,
68d480c4
AD		 2784 vfn);
2785 count++;
ff41f8dc
AD		 2786 }
2787 }
2788 /* write the addresses in reverse order to avoid write combining */
2789 for (; rar_entries > 0 ; rar_entries--) {
2790 wr32(E1000_RAH(rar_entries), 0);
2791 wr32(E1000_RAL(rar_entries), 0);
2792 }
2793 wrfl();
2794
68d480c4
AD		 2795 return count;
2796}
2797
2798/**
2799 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2800 * @netdev: network interface device structure
2801 *
2802 * The set_rx_mode entry point is called whenever the unicast or multicast
2803 * address lists or the network interface flags are updated. This routine is
2804 * responsible for configuring the hardware for proper unicast, multicast,
2805 * promiscuous mode, and all-multi behavior.
2806 **/
2807static void igb_set_rx_mode(struct net_device *netdev)
2808{
2809 struct igb_adapter *adapter = netdev_priv(netdev);
2810 struct e1000_hw *hw = &adapter->hw;
2811 unsigned int vfn = adapter->vfs_allocated_count;
2812 u32 rctl, vmolr = 0;
2813 int count;
2814
2815 /* Check for Promiscuous and All Multicast modes */
2816 rctl = rd32(E1000_RCTL);
2817
2818 /* clear the effected bits */
2819 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2820
2821 if (netdev->flags & IFF_PROMISC) {
2822 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2823 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2824 } else {
2825 if (netdev->flags & IFF_ALLMULTI) {
2826 rctl |= E1000_RCTL_MPE;
2827 vmolr |= E1000_VMOLR_MPME;
2828 } else {
2829 /*
2830 * Write addresses to the MTA, if the attempt fails
2831 * then we should just turn on promiscous mode so
2832 * that we can at least receive multicast traffic
2833 */
2834 count = igb_write_mc_addr_list(netdev);
2835 if (count < 0) {
2836 rctl |= E1000_RCTL_MPE;
2837 vmolr |= E1000_VMOLR_MPME;
2838 } else if (count) {
2839 vmolr |= E1000_VMOLR_ROMPE;
2840 }
2841 }
2842 /*
2843 * Write addresses to available RAR registers, if there is not
2844 * sufficient space to store all the addresses then enable
2845 * unicast promiscous mode
2846 */
2847 count = igb_write_uc_addr_list(netdev);
2848 if (count < 0) {
2849 rctl |= E1000_RCTL_UPE;
2850 vmolr |= E1000_VMOLR_ROPE;
2851 }
2852 rctl |= E1000_RCTL_VFE;
28fc06f5 2853 }
68d480c4 2854 wr32(E1000_RCTL, rctl);
28fc06f5 2855
68d480c4
AD		 2856 /*
2857 * In order to support SR-IOV and eventually VMDq it is necessary to set
2858 * the VMOLR to enable the appropriate modes. Without this workaround
2859 * we will have issues with VLAN tag stripping not being done for frames
2860 * that are only arriving because we are the default pool
2861 */
2862 if (hw->mac.type < e1000_82576)
28fc06f5 2863 return;
9d5c8243 2864
68d480c4
AD		 2865 vmolr |= rd32(E1000_VMOLR(vfn)) &
2866 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
2867 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 2868 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2869}
2870
2871/* Need to wait a few seconds after link up to get diagnostic information from
2872 * the phy */
2873static void igb_update_phy_info(unsigned long data)
2874{
2875 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2876 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2877}
2878
4d6b725e
AD		 2879/**
2880 * igb_has_link - check shared code for link and determine up/down
2881 * @adapter: pointer to driver private info
2882 **/
2883static bool igb_has_link(struct igb_adapter *adapter)
2884{
2885 struct e1000_hw *hw = &adapter->hw;
2886 bool link_active = false;
2887 s32 ret_val = 0;
2888
2889 /* get_link_status is set on LSC (link status) interrupt or
2890 * rx sequence error interrupt. get_link_status will stay
2891 * false until the e1000_check_for_link establishes link
2892 * for copper adapters ONLY
2893 */
2894 switch (hw->phy.media_type) {
2895 case e1000_media_type_copper:
2896 if (hw->mac.get_link_status) {
2897 ret_val = hw->mac.ops.check_for_link(hw);
2898 link_active = !hw->mac.get_link_status;
2899 } else {
2900 link_active = true;
2901 }
2902 break;
4d6b725e
AD		 2903 case e1000_media_type_internal_serdes:
2904 ret_val = hw->mac.ops.check_for_link(hw);
2905 link_active = hw->mac.serdes_has_link;
2906 break;
2907 default:
2908 case e1000_media_type_unknown:
2909 break;
2910 }
2911
2912 return link_active;
2913}
2914
9d5c8243
AK		 2915/**
2916 * igb_watchdog - Timer Call-back
2917 * @data: pointer to adapter cast into an unsigned long
2918 **/
2919static void igb_watchdog(unsigned long data)
2920{
2921 struct igb_adapter *adapter = (struct igb_adapter *)data;
2922 /* Do the rest outside of interrupt context */
2923 schedule_work(&adapter->watchdog_task);
2924}
2925
2926static void igb_watchdog_task(struct work_struct *work)
2927{
2928 struct igb_adapter *adapter = container_of(work,
2929 struct igb_adapter, watchdog_task);
2930 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2931 struct net_device *netdev = adapter->netdev;
2932 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2933 u32 link;
7a6ea550 2934 int i;
9d5c8243 2935
4d6b725e
AD		 2936 link = igb_has_link(adapter);
2937 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2938 goto link_up;
2939
9d5c8243
AK		 2940 if (link) {
2941 if (!netif_carrier_ok(netdev)) {
2942 u32 ctrl;
2943 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2944 &adapter->link_speed,
2945 &adapter->link_duplex);
2946
2947 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2948 /* Links status message must follow this format */
2949 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2950 "Flow Control: %s\n",
527d47c1 2951 netdev->name,
9d5c8243
AK		 2952 adapter->link_speed,
2953 adapter->link_duplex == FULL_DUPLEX ?
2954 "Full Duplex" : "Half Duplex",
2955 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2956 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2957 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2958 E1000_CTRL_TFCE) ? "TX" : "None")));
2959
2960 /* tweak tx_queue_len according to speed/duplex and
2961 * adjust the timeout factor */
2962 netdev->tx_queue_len = adapter->tx_queue_len;
2963 adapter->tx_timeout_factor = 1;
2964 switch (adapter->link_speed) {
2965 case SPEED_10:
2966 netdev->tx_queue_len = 10;
2967 adapter->tx_timeout_factor = 14;
2968 break;
2969 case SPEED_100:
2970 netdev->tx_queue_len = 100;
2971 /* maybe add some timeout factor ? */
2972 break;
2973 }
2974
2975 netif_carrier_on(netdev);
9d5c8243 2976
4ae196df
AD		 2977 igb_ping_all_vfs(adapter);
2978
4b1a9877 2979 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2980 if (!test_bit(__IGB_DOWN, &adapter->state))
2981 mod_timer(&adapter->phy_info_timer,
2982 round_jiffies(jiffies + 2 * HZ));
2983 }
2984 } else {
2985 if (netif_carrier_ok(netdev)) {
2986 adapter->link_speed = 0;
2987 adapter->link_duplex = 0;
527d47c1
AD		 2988 /* Links status message must follow this format */
2989 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2990 netdev->name);
9d5c8243 2991 netif_carrier_off(netdev);
4b1a9877 2992
4ae196df
AD		 2993 igb_ping_all_vfs(adapter);
2994
4b1a9877 2995 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2996 if (!test_bit(__IGB_DOWN, &adapter->state))
2997 mod_timer(&adapter->phy_info_timer,
2998 round_jiffies(jiffies + 2 * HZ));
2999 }
3000 }
3001
3002link_up:
3003 igb_update_stats(adapter);
3004
4b1a9877 3005 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 3006 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 3007 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 3008 adapter->colc_old = adapter->stats.colc;
3009
3010 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
3011 adapter->gorc_old = adapter->stats.gorc;
3012 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
3013 adapter->gotc_old = adapter->stats.gotc;
3014
3015 igb_update_adaptive(&adapter->hw);
3016
3017 if (!netif_carrier_ok(netdev)) {
c493ea45 3018 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 3019 /* We've lost link, so the controller stops DMA,
3020 * but we've got queued Tx work that's never going
3021 * to get done, so reset controller to flush Tx.
3022 * (Do the reset outside of interrupt context). */
3023 adapter->tx_timeout_count++;
3024 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 3025 /* return immediately since reset is imminent */
3026 return;
9d5c8243
AK		 3027 }
3028 }
3029
3030 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3031 if (adapter->msix_entries) {
047e0030
AD		 3032 u32 eics = 0;
3033 for (i = 0; i < adapter->num_q_vectors; i++) {
3034 struct igb_q_vector *q_vector = adapter->q_vector[i];
3035 eics |= q_vector->eims_value;
3036 }
7a6ea550
AD		 3037 wr32(E1000_EICS, eics);
3038 } else {
3039 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3040 }
9d5c8243
AK		 3041
3042 /* Force detection of hung controller every watchdog period */
3043 tx_ring->detect_tx_hung = true;
3044
3045 /* Reset the timer */
3046 if (!test_bit(__IGB_DOWN, &adapter->state))
3047 mod_timer(&adapter->watchdog_timer,
3048 round_jiffies(jiffies + 2 * HZ));
3049}
3050
3051enum latency_range {
3052 lowest_latency = 0,
3053 low_latency = 1,
3054 bulk_latency = 2,
3055 latency_invalid = 255
3056};
3057
3058
6eb5a7f1
AD		 3059/**
3060 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3061 *
3062 * Stores a new ITR value based on strictly on packet size. This
3063 * algorithm is less sophisticated than that used in igb_update_itr,
3064 * due to the difficulty of synchronizing statistics across multiple
3065 * receive rings. The divisors and thresholds used by this fuction
3066 * were determined based on theoretical maximum wire speed and testing
3067 * data, in order to minimize response time while increasing bulk
3068 * throughput.
3069 * This functionality is controlled by the InterruptThrottleRate module
3070 * parameter (see igb_param.c)
3071 * NOTE: This function is called only when operating in a multiqueue
3072 * receive environment.
047e0030 3073 * @q_vector: pointer to q_vector
6eb5a7f1 3074 **/
047e0030 3075static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3076{
047e0030 3077 int new_val = q_vector->itr_val;
6eb5a7f1 3078 int avg_wire_size = 0;
047e0030 3079 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3080
6eb5a7f1
AD		 3081 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3082 * ints/sec - ITR timer value of 120 ticks.
3083 */
3084 if (adapter->link_speed != SPEED_1000) {
047e0030 3085 new_val = 976;
6eb5a7f1 3086 goto set_itr_val;
9d5c8243 3087 }
047e0030
AD		 3088
3089 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3090 struct igb_ring *ring = q_vector->rx_ring;
3091 avg_wire_size = ring->total_bytes / ring->total_packets;
3092 }
3093
3094 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3095 struct igb_ring *ring = q_vector->tx_ring;
3096 avg_wire_size = max_t(u32, avg_wire_size,
3097 (ring->total_bytes /
3098 ring->total_packets));
3099 }
3100
3101 /* if avg_wire_size isn't set no work was done */
3102 if (!avg_wire_size)
3103 goto clear_counts;
9d5c8243 3104
6eb5a7f1
AD		 3105 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3106 avg_wire_size += 24;
3107
3108 /* Don't starve jumbo frames */
3109 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3110
6eb5a7f1
AD		 3111 /* Give a little boost to mid-size frames */
3112 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3113 new_val = avg_wire_size / 3;
3114 else
3115 new_val = avg_wire_size / 2;
9d5c8243 3116
6eb5a7f1 3117set_itr_val:
047e0030
AD		 3118 if (new_val != q_vector->itr_val) {
3119 q_vector->itr_val = new_val;
3120 q_vector->set_itr = 1;
9d5c8243 3121 }
6eb5a7f1 3122clear_counts:
047e0030
AD		 3123 if (q_vector->rx_ring) {
3124 q_vector->rx_ring->total_bytes = 0;
3125 q_vector->rx_ring->total_packets = 0;
3126 }
3127 if (q_vector->tx_ring) {
3128 q_vector->tx_ring->total_bytes = 0;
3129 q_vector->tx_ring->total_packets = 0;
3130 }
9d5c8243
AK		 3131}
3132
3133/**
3134 * igb_update_itr - update the dynamic ITR value based on statistics
3135 * Stores a new ITR value based on packets and byte
3136 * counts during the last interrupt. The advantage of per interrupt
3137 * computation is faster updates and more accurate ITR for the current
3138 * traffic pattern. Constants in this function were computed
3139 * based on theoretical maximum wire speed and thresholds were set based
3140 * on testing data as well as attempting to minimize response time
3141 * while increasing bulk throughput.
3142 * this functionality is controlled by the InterruptThrottleRate module
3143 * parameter (see igb_param.c)
3144 * NOTE: These calculations are only valid when operating in a single-
3145 * queue environment.
3146 * @adapter: pointer to adapter
047e0030 3147 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3148 * @packets: the number of packets during this measurement interval
3149 * @bytes: the number of bytes during this measurement interval
3150 **/
3151static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3152 int packets, int bytes)
3153{
3154 unsigned int retval = itr_setting;
3155
3156 if (packets == 0)
3157 goto update_itr_done;
3158
3159 switch (itr_setting) {
3160 case lowest_latency:
3161 /* handle TSO and jumbo frames */
3162 if (bytes/packets > 8000)
3163 retval = bulk_latency;
3164 else if ((packets < 5) && (bytes > 512))
3165 retval = low_latency;
3166 break;
3167 case low_latency: /* 50 usec aka 20000 ints/s */
3168 if (bytes > 10000) {
3169 /* this if handles the TSO accounting */
3170 if (bytes/packets > 8000) {
3171 retval = bulk_latency;
3172 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3173 retval = bulk_latency;
3174 } else if ((packets > 35)) {
3175 retval = lowest_latency;
3176 }
3177 } else if (bytes/packets > 2000) {
3178 retval = bulk_latency;
3179 } else if (packets <= 2 && bytes < 512) {
3180 retval = lowest_latency;
3181 }
3182 break;
3183 case bulk_latency: /* 250 usec aka 4000 ints/s */
3184 if (bytes > 25000) {
3185 if (packets > 35)
3186 retval = low_latency;
1e5c3d21 3187 } else if (bytes < 1500) {
9d5c8243
AK		 3188 retval = low_latency;
3189 }
3190 break;
3191 }
3192
3193update_itr_done:
3194 return retval;
3195}
3196
6eb5a7f1 3197static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3198{
047e0030 3199 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3200 u16 current_itr;
047e0030 3201 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3202
3203 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3204 if (adapter->link_speed != SPEED_1000) {
3205 current_itr = 0;
3206 new_itr = 4000;
3207 goto set_itr_now;
3208 }
3209
3210 adapter->rx_itr = igb_update_itr(adapter,
3211 adapter->rx_itr,
3212 adapter->rx_ring->total_packets,
3213 adapter->rx_ring->total_bytes);
9d5c8243 3214
047e0030
AD		 3215 adapter->tx_itr = igb_update_itr(adapter,
3216 adapter->tx_itr,
3217 adapter->tx_ring->total_packets,
3218 adapter->tx_ring->total_bytes);
3219 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3220
6eb5a7f1 3221 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 3222 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3223 current_itr = low_latency;
3224
9d5c8243
AK		 3225 switch (current_itr) {
3226 /* counts and packets in update_itr are dependent on these numbers */
3227 case lowest_latency:
78b1f607 3228 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3229 break;
3230 case low_latency:
78b1f607 3231 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3232 break;
3233 case bulk_latency:
78b1f607 3234 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3235 break;
3236 default:
3237 break;
3238 }
3239
3240set_itr_now:
6eb5a7f1
AD		 3241 adapter->rx_ring->total_bytes = 0;
3242 adapter->rx_ring->total_packets = 0;
047e0030
AD		 3243 adapter->tx_ring->total_bytes = 0;
3244 adapter->tx_ring->total_packets = 0;
6eb5a7f1 3245
047e0030 3246 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3247 /* this attempts to bias the interrupt rate towards Bulk
3248 * by adding intermediate steps when interrupt rate is
3249 * increasing */
047e0030
AD		 3250 new_itr = new_itr > q_vector->itr_val ?
3251 max((new_itr * q_vector->itr_val) /
3252 (new_itr + (q_vector->itr_val >> 2)),
3253 new_itr) :
9d5c8243
AK		 3254 new_itr;
3255 /* Don't write the value here; it resets the adapter's
3256 * internal timer, and causes us to delay far longer than
3257 * we should between interrupts. Instead, we write the ITR
3258 * value at the beginning of the next interrupt so the timing
3259 * ends up being correct.
3260 */
047e0030
AD		 3261 q_vector->itr_val = new_itr;
3262 q_vector->set_itr = 1;
9d5c8243
AK		 3263 }
3264
3265 return;
3266}
3267
9d5c8243
AK		 3268#define IGB_TX_FLAGS_CSUM 0x00000001
3269#define IGB_TX_FLAGS_VLAN 0x00000002
3270#define IGB_TX_FLAGS_TSO 0x00000004
3271#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3272#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3273#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3274#define IGB_TX_FLAGS_VLAN_SHIFT 16
3275
3276static inline int igb_tso_adv(struct igb_adapter *adapter,
3277 struct igb_ring *tx_ring,
3278 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3279{
3280 struct e1000_adv_tx_context_desc *context_desc;
3281 unsigned int i;
3282 int err;
3283 struct igb_buffer *buffer_info;
3284 u32 info = 0, tu_cmd = 0;
3285 u32 mss_l4len_idx, l4len;
3286 *hdr_len = 0;
3287
3288 if (skb_header_cloned(skb)) {
3289 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3290 if (err)
3291 return err;
3292 }
3293
3294 l4len = tcp_hdrlen(skb);
3295 *hdr_len += l4len;
3296
3297 if (skb->protocol == htons(ETH_P_IP)) {
3298 struct iphdr *iph = ip_hdr(skb);
3299 iph->tot_len = 0;
3300 iph->check = 0;
3301 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3302 iph->daddr, 0,
3303 IPPROTO_TCP,
3304 0);
3305 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3306 ipv6_hdr(skb)->payload_len = 0;
3307 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3308 &ipv6_hdr(skb)->daddr,
3309 0, IPPROTO_TCP, 0);
3310 }
3311
3312 i = tx_ring->next_to_use;
3313
3314 buffer_info = &tx_ring->buffer_info[i];
3315 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3316 /* VLAN MACLEN IPLEN */
3317 if (tx_flags & IGB_TX_FLAGS_VLAN)
3318 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3319 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3320 *hdr_len += skb_network_offset(skb);
3321 info |= skb_network_header_len(skb);
3322 *hdr_len += skb_network_header_len(skb);
3323 context_desc->vlan_macip_lens = cpu_to_le32(info);
3324
3325 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3326 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3327
3328 if (skb->protocol == htons(ETH_P_IP))
3329 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3330 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3331
3332 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3333
3334 /* MSS L4LEN IDX */
3335 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3336 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3337
73cd78f1 3338 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3339 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3340 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3341
3342 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3343 context_desc->seqnum_seed = 0;
3344
3345 buffer_info->time_stamp = jiffies;
0e014cb1 3346 buffer_info->next_to_watch = i;
9d5c8243
AK		 3347 buffer_info->dma = 0;
3348 i++;
3349 if (i == tx_ring->count)
3350 i = 0;
3351
3352 tx_ring->next_to_use = i;
3353
3354 return true;
3355}
3356
3357static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3358 struct igb_ring *tx_ring,
3359 struct sk_buff *skb, u32 tx_flags)
3360{
3361 struct e1000_adv_tx_context_desc *context_desc;
80785298 3362 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3363 struct igb_buffer *buffer_info;
3364 u32 info = 0, tu_cmd = 0;
80785298 3365 unsigned int i;
9d5c8243
AK		 3366
3367 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3368 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3369 i = tx_ring->next_to_use;
3370 buffer_info = &tx_ring->buffer_info[i];
3371 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3372
3373 if (tx_flags & IGB_TX_FLAGS_VLAN)
3374 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3375 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3376 if (skb->ip_summed == CHECKSUM_PARTIAL)
3377 info |= skb_network_header_len(skb);
3378
3379 context_desc->vlan_macip_lens = cpu_to_le32(info);
3380
3381 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3382
3383 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3384 __be16 protocol;
3385
3386 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3387 const struct vlan_ethhdr *vhdr =
3388 (const struct vlan_ethhdr*)skb->data;
3389
3390 protocol = vhdr->h_vlan_encapsulated_proto;
3391 } else {
3392 protocol = skb->protocol;
3393 }
3394
3395 switch (protocol) {
09640e63 3396 case cpu_to_be16(ETH_P_IP):
9d5c8243 3397 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3398 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3399 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3400 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3401 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3402 break;
09640e63 3403 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3404 /* XXX what about other V6 headers?? */
3405 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3406 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3407 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3408 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3409 break;
3410 default:
3411 if (unlikely(net_ratelimit()))
80785298 3412 dev_warn(&pdev->dev,
44b0cda3
MW		 3413 "partial checksum but proto=%x!\n",
3414 skb->protocol);
3415 break;
3416 }
9d5c8243
AK		 3417 }
3418
3419 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3420 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3421 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3422 context_desc->mss_l4len_idx =
3423 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3424 else
3425 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3426
3427 buffer_info->time_stamp = jiffies;
0e014cb1 3428 buffer_info->next_to_watch = i;
9d5c8243
AK		 3429 buffer_info->dma = 0;
3430
3431 i++;
3432 if (i == tx_ring->count)
3433 i = 0;
3434 tx_ring->next_to_use = i;
3435
3436 return true;
3437 }
9d5c8243
AK		 3438 return false;
3439}
3440
3441#define IGB_MAX_TXD_PWR 16
3442#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3443
80785298 3444static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3445 unsigned int first)
9d5c8243
AK		 3446{
3447 struct igb_buffer *buffer_info;
80785298 3448 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3449 unsigned int len = skb_headlen(skb);
3450 unsigned int count = 0, i;
3451 unsigned int f;
65689fef 3452 dma_addr_t *map;
9d5c8243
AK		 3453
3454 i = tx_ring->next_to_use;
3455
80785298
AD		 3456 if (skb_dma_map(&pdev->dev, skb, DMA_TO_DEVICE)) {
3457 dev_err(&pdev->dev, "TX DMA map failed\n");
65689fef
AD		 3458 return 0;
3459 }
3460
3461 map = skb_shinfo(skb)->dma_maps;
3462
9d5c8243
AK		 3463 buffer_info = &tx_ring->buffer_info[i];
3464 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3465 buffer_info->length = len;
3466 /* set time_stamp *before* dma to help avoid a possible race */
3467 buffer_info->time_stamp = jiffies;
0e014cb1 3468 buffer_info->next_to_watch = i;
042a53a9 3469 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3470
3471 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3472 struct skb_frag_struct *frag;
3473
65689fef
AD		 3474 i++;
3475 if (i == tx_ring->count)
3476 i = 0;
3477
9d5c8243
AK		 3478 frag = &skb_shinfo(skb)->frags[f];
3479 len = frag->size;
3480
3481 buffer_info = &tx_ring->buffer_info[i];
3482 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3483 buffer_info->length = len;
3484 buffer_info->time_stamp = jiffies;
0e014cb1 3485 buffer_info->next_to_watch = i;
65689fef 3486 buffer_info->dma = map[count];
9d5c8243 3487 count++;
9d5c8243
AK		 3488 }
3489
9d5c8243 3490 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3491 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3492
042a53a9 3493 return count + 1;
9d5c8243
AK		 3494}
3495
3496static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3497 struct igb_ring *tx_ring,
3498 int tx_flags, int count, u32 paylen,
3499 u8 hdr_len)
3500{
3501 union e1000_adv_tx_desc *tx_desc = NULL;
3502 struct igb_buffer *buffer_info;
3503 u32 olinfo_status = 0, cmd_type_len;
3504 unsigned int i;
3505
3506 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3507 E1000_ADVTXD_DCMD_DEXT);
3508
3509 if (tx_flags & IGB_TX_FLAGS_VLAN)
3510 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3511
33af6bcc
PO		 3512 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3513 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3514
9d5c8243
AK		 3515 if (tx_flags & IGB_TX_FLAGS_TSO) {
3516 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3517
3518 /* insert tcp checksum */
3519 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3520
3521 /* insert ip checksum */
3522 if (tx_flags & IGB_TX_FLAGS_IPV4)
3523 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3524
3525 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3526 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3527 }
3528
7dfc16fa
AD		 3529 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3530 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3531 IGB_TX_FLAGS_VLAN)))
661086df 3532 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3533
3534 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3535
3536 i = tx_ring->next_to_use;
3537 while (count--) {
3538 buffer_info = &tx_ring->buffer_info[i];
3539 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3540 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3541 tx_desc->read.cmd_type_len =
3542 cpu_to_le32(cmd_type_len | buffer_info->length);
3543 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3544 i++;
3545 if (i == tx_ring->count)
3546 i = 0;
3547 }
3548
3549 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3550 /* Force memory writes to complete before letting h/w
3551 * know there are new descriptors to fetch. (Only
3552 * applicable for weak-ordered memory model archs,
3553 * such as IA-64). */
3554 wmb();
3555
3556 tx_ring->next_to_use = i;
fce99e34 3557 writel(i, tx_ring->tail);
9d5c8243
AK		 3558 /* we need this if more than one processor can write to our tail
3559 * at a time, it syncronizes IO on IA64/Altix systems */
3560 mmiowb();
3561}
3562
3563static int __igb_maybe_stop_tx(struct net_device *netdev,
3564 struct igb_ring *tx_ring, int size)
3565{
3566 struct igb_adapter *adapter = netdev_priv(netdev);
3567
661086df 3568 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3569
9d5c8243
AK		 3570 /* Herbert's original patch had:
3571 * smp_mb__after_netif_stop_queue();
3572 * but since that doesn't exist yet, just open code it. */
3573 smp_mb();
3574
3575 /* We need to check again in a case another CPU has just
3576 * made room available. */
c493ea45 3577 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3578 return -EBUSY;
3579
3580 /* A reprieve! */
661086df 3581 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3582 ++adapter->restart_queue;
3583 return 0;
3584}
3585
3586static int igb_maybe_stop_tx(struct net_device *netdev,
3587 struct igb_ring *tx_ring, int size)
3588{
c493ea45 3589 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3590 return 0;
3591 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3592}
3593
3b29a56d
SH		 3594static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3595 struct net_device *netdev,
3596 struct igb_ring *tx_ring)
9d5c8243
AK		 3597{
3598 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3599 unsigned int first;
9d5c8243 3600 unsigned int tx_flags = 0;
9d5c8243 3601 u8 hdr_len = 0;
65689fef 3602 int count = 0;
9d5c8243 3603 int tso = 0;
33af6bcc 3604 union skb_shared_tx *shtx;
9d5c8243 3605
9d5c8243
AK		 3606 if (test_bit(__IGB_DOWN, &adapter->state)) {
3607 dev_kfree_skb_any(skb);
3608 return NETDEV_TX_OK;
3609 }
3610
3611 if (skb->len <= 0) {
3612 dev_kfree_skb_any(skb);
3613 return NETDEV_TX_OK;
3614 }
3615
9d5c8243
AK		 3616 /* need: 1 descriptor per page,
3617 * + 2 desc gap to keep tail from touching head,
3618 * + 1 desc for skb->data,
3619 * + 1 desc for context descriptor,
3620 * otherwise try next time */
3621 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3622 /* this is a hard error */
9d5c8243
AK		 3623 return NETDEV_TX_BUSY;
3624 }
33af6bcc
PO		 3625
3626 /*
3627 * TODO: check that there currently is no other packet with
3628 * time stamping in the queue
3629 *
3630 * When doing time stamping, keep the connection to the socket
3631 * a while longer: it is still needed by skb_hwtstamp_tx(),
3632 * called either in igb_tx_hwtstamp() or by our caller when
3633 * doing software time stamping.
3634 */
3635 shtx = skb_tx(skb);
3636 if (unlikely(shtx->hardware)) {
3637 shtx->in_progress = 1;
3638 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3639 }
9d5c8243
AK		 3640
3641 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3642 tx_flags |= IGB_TX_FLAGS_VLAN;
3643 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3644 }
3645
661086df
PWJ		 3646 if (skb->protocol == htons(ETH_P_IP))
3647 tx_flags |= IGB_TX_FLAGS_IPV4;
3648
0e014cb1 3649 first = tx_ring->next_to_use;
9d5c8243
AK		 3650 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3651 &hdr_len) : 0;
3652
3653 if (tso < 0) {
3654 dev_kfree_skb_any(skb);
9d5c8243
AK		 3655 return NETDEV_TX_OK;
3656 }
3657
3658 if (tso)
3659 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3660 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3661 (skb->ip_summed == CHECKSUM_PARTIAL))
3662 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3663
65689fef
AD		 3664 /*
3665 * count reflects descriptors mapped, if 0 then mapping error
3666 * has occured and we need to rewind the descriptor queue
3667 */
80785298 3668 count = igb_tx_map_adv(tx_ring, skb, first);
65689fef
AD		 3669
3670 if (count) {
3671 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3672 skb->len, hdr_len);
65689fef
AD		 3673 /* Make sure there is space in the ring for the next send. */
3674 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3675 } else {
3676 dev_kfree_skb_any(skb);
3677 tx_ring->buffer_info[first].time_stamp = 0;
3678 tx_ring->next_to_use = first;
3679 }
9d5c8243 3680
9d5c8243
AK		 3681 return NETDEV_TX_OK;
3682}
3683
3b29a56d
SH		 3684static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3685 struct net_device *netdev)
9d5c8243
AK		 3686{
3687 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3688 struct igb_ring *tx_ring;
3689
661086df 3690 int r_idx = 0;
1bfaf07b 3691 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3692 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3693
3694 /* This goes back to the question of how to logically map a tx queue
3695 * to a flow. Right now, performance is impacted slightly negatively
3696 * if using multiple tx queues. If the stack breaks away from a
3697 * single qdisc implementation, we can look at this again. */
3b29a56d 3698 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3699}
3700
3701/**
3702 * igb_tx_timeout - Respond to a Tx Hang
3703 * @netdev: network interface device structure
3704 **/
3705static void igb_tx_timeout(struct net_device *netdev)
3706{
3707 struct igb_adapter *adapter = netdev_priv(netdev);
3708 struct e1000_hw *hw = &adapter->hw;
3709
3710 /* Do the reset outside of interrupt context */
3711 adapter->tx_timeout_count++;
3712 schedule_work(&adapter->reset_task);
265de409
AD		 3713 wr32(E1000_EICS,
3714 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3715}
3716
3717static void igb_reset_task(struct work_struct *work)
3718{
3719 struct igb_adapter *adapter;
3720 adapter = container_of(work, struct igb_adapter, reset_task);
3721
3722 igb_reinit_locked(adapter);
3723}
3724
3725/**
3726 * igb_get_stats - Get System Network Statistics
3727 * @netdev: network interface device structure
3728 *
3729 * Returns the address of the device statistics structure.
3730 * The statistics are actually updated from the timer callback.
3731 **/
73cd78f1 3732static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3733{
9d5c8243 3734 /* only return the current stats */
8d24e933 3735 return &netdev->stats;
9d5c8243
AK		 3736}
3737
3738/**
3739 * igb_change_mtu - Change the Maximum Transfer Unit
3740 * @netdev: network interface device structure
3741 * @new_mtu: new value for maximum frame size
3742 *
3743 * Returns 0 on success, negative on failure
3744 **/
3745static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3746{
3747 struct igb_adapter *adapter = netdev_priv(netdev);
3748 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3749
3750 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3751 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3752 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3753 return -EINVAL;
3754 }
3755
9d5c8243
AK		 3756 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3757 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3758 return -EINVAL;
3759 }
3760
3761 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3762 msleep(1);
73cd78f1 3763
9d5c8243
AK		 3764 /* igb_down has a dependency on max_frame_size */
3765 adapter->max_frame_size = max_frame;
3766 if (netif_running(netdev))
3767 igb_down(adapter);
3768
3769 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3770 * means we reserve 2 more, this pushes us to allocate from the next
3771 * larger slab size.
3772 * i.e. RXBUFFER_2048 --> size-4096 slab
3773 */
3774
7d95b717 3775 if (max_frame <= IGB_RXBUFFER_1024)
9d5c8243 3776 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3777 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
9d5c8243 3778 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6
AD		 3779 else
3780 adapter->rx_buffer_len = IGB_RXBUFFER_128;
9d5c8243
AK		 3781
3782 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3783 netdev->mtu, new_mtu);
3784 netdev->mtu = new_mtu;
3785
3786 if (netif_running(netdev))
3787 igb_up(adapter);
3788 else
3789 igb_reset(adapter);
3790
3791 clear_bit(__IGB_RESETTING, &adapter->state);
3792
3793 return 0;
3794}
3795
3796/**
3797 * igb_update_stats - Update the board statistics counters
3798 * @adapter: board private structure
3799 **/
3800
3801void igb_update_stats(struct igb_adapter *adapter)
3802{
8d24e933 3803 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3804 struct e1000_hw *hw = &adapter->hw;
3805 struct pci_dev *pdev = adapter->pdev;
3806 u16 phy_tmp;
3807
3808#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3809
3810 /*
3811 * Prevent stats update while adapter is being reset, or if the pci
3812 * connection is down.
3813 */
3814 if (adapter->link_speed == 0)
3815 return;
3816 if (pci_channel_offline(pdev))
3817 return;
3818
3819 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3820 adapter->stats.gprc += rd32(E1000_GPRC);
3821 adapter->stats.gorc += rd32(E1000_GORCL);
3822 rd32(E1000_GORCH); /* clear GORCL */
3823 adapter->stats.bprc += rd32(E1000_BPRC);
3824 adapter->stats.mprc += rd32(E1000_MPRC);
3825 adapter->stats.roc += rd32(E1000_ROC);
3826
3827 adapter->stats.prc64 += rd32(E1000_PRC64);
3828 adapter->stats.prc127 += rd32(E1000_PRC127);
3829 adapter->stats.prc255 += rd32(E1000_PRC255);
3830 adapter->stats.prc511 += rd32(E1000_PRC511);
3831 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3832 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3833 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3834 adapter->stats.sec += rd32(E1000_SEC);
3835
3836 adapter->stats.mpc += rd32(E1000_MPC);
3837 adapter->stats.scc += rd32(E1000_SCC);
3838 adapter->stats.ecol += rd32(E1000_ECOL);
3839 adapter->stats.mcc += rd32(E1000_MCC);
3840 adapter->stats.latecol += rd32(E1000_LATECOL);
3841 adapter->stats.dc += rd32(E1000_DC);
3842 adapter->stats.rlec += rd32(E1000_RLEC);
3843 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3844 adapter->stats.xontxc += rd32(E1000_XONTXC);
3845 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3846 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3847 adapter->stats.fcruc += rd32(E1000_FCRUC);
3848 adapter->stats.gptc += rd32(E1000_GPTC);
3849 adapter->stats.gotc += rd32(E1000_GOTCL);
3850 rd32(E1000_GOTCH); /* clear GOTCL */
3851 adapter->stats.rnbc += rd32(E1000_RNBC);
3852 adapter->stats.ruc += rd32(E1000_RUC);
3853 adapter->stats.rfc += rd32(E1000_RFC);
3854 adapter->stats.rjc += rd32(E1000_RJC);
3855 adapter->stats.tor += rd32(E1000_TORH);
3856 adapter->stats.tot += rd32(E1000_TOTH);
3857 adapter->stats.tpr += rd32(E1000_TPR);
3858
3859 adapter->stats.ptc64 += rd32(E1000_PTC64);
3860 adapter->stats.ptc127 += rd32(E1000_PTC127);
3861 adapter->stats.ptc255 += rd32(E1000_PTC255);
3862 adapter->stats.ptc511 += rd32(E1000_PTC511);
3863 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3864 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3865
3866 adapter->stats.mptc += rd32(E1000_MPTC);
3867 adapter->stats.bptc += rd32(E1000_BPTC);
3868
3869 /* used for adaptive IFS */
3870
3871 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3872 adapter->stats.tpt += hw->mac.tx_packet_delta;
3873 hw->mac.collision_delta = rd32(E1000_COLC);
3874 adapter->stats.colc += hw->mac.collision_delta;
3875
3876 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3877 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3878 adapter->stats.tncrs += rd32(E1000_TNCRS);
3879 adapter->stats.tsctc += rd32(E1000_TSCTC);
3880 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3881
3882 adapter->stats.iac += rd32(E1000_IAC);
3883 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3884 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3885 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3886 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3887 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3888 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3889 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3890 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3891
3892 /* Fill out the OS statistics structure */
8d24e933
AK		 3893 netdev->stats.multicast = adapter->stats.mprc;
3894 netdev->stats.collisions = adapter->stats.colc;
9d5c8243
AK		 3895
3896 /* Rx Errors */
3897
8c0ab70a
JDB		 3898 if (hw->mac.type != e1000_82575) {
3899 u32 rqdpc_tmp;
3ea73afa 3900 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3901 int i;
3902 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3903 * Queue Drop Packet Count) stats only gets incremented, if
3904 * the DROP_EN but it set (in the SRRCTL register for that
3905 * queue). If DROP_EN bit is NOT set, then the some what
3906 * equivalent count is stored in RNBC (not per queue basis).
3907 * Also note the drop count is due to lack of available
3908 * descriptors.
3909 */
3910 for (i = 0; i < adapter->num_rx_queues; i++) {
3911 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3912 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3913 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3914 }
8d24e933 3915 netdev->stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3916 }
3917
3ea73afa
JDB		 3918 /* Note RNBC (Receive No Buffers Count) is an not an exact
3919 * drop count as the hardware FIFO might save the day. Thats
3920 * one of the reason for saving it in rx_fifo_errors, as its
3921 * potentially not a true drop.
3922 */
8d24e933 3923 netdev->stats.rx_fifo_errors += adapter->stats.rnbc;
3ea73afa 3924
9d5c8243 3925 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3926 * our own version based on RUC and ROC */
8d24e933 3927 netdev->stats.rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 3928 adapter->stats.crcerrs + adapter->stats.algnerrc +
3929 adapter->stats.ruc + adapter->stats.roc +
3930 adapter->stats.cexterr;
8d24e933 3931 netdev->stats.rx_length_errors = adapter->stats.ruc +
9d5c8243 3932 adapter->stats.roc;
8d24e933
AK		 3933 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3934 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3935 netdev->stats.rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 3936
3937 /* Tx Errors */
8d24e933 3938 netdev->stats.tx_errors = adapter->stats.ecol +
9d5c8243 3939 adapter->stats.latecol;
8d24e933
AK		 3940 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3941 netdev->stats.tx_window_errors = adapter->stats.latecol;
3942 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 3943
3944 /* Tx Dropped needs to be maintained elsewhere */
3945
3946 /* Phy Stats */
3947 if (hw->phy.media_type == e1000_media_type_copper) {
3948 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3949 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3950 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3951 adapter->phy_stats.idle_errors += phy_tmp;
3952 }
3953 }
3954
3955 /* Management Stats */
3956 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3957 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3958 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3959}
3960
9d5c8243
AK		 3961static irqreturn_t igb_msix_other(int irq, void *data)
3962{
047e0030 3963 struct igb_adapter *adapter = data;
9d5c8243 3964 struct e1000_hw *hw = &adapter->hw;
844290e5 3965 u32 icr = rd32(E1000_ICR);
844290e5 3966 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 3967
047e0030 3968 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 3969 /* HW is reporting DMA is out of sync */
3970 adapter->stats.doosync++;
3971 }
eebbbdba 3972
4ae196df
AD		 3973 /* Check for a mailbox event */
3974 if (icr & E1000_ICR_VMMB)
3975 igb_msg_task(adapter);
3976
3977 if (icr & E1000_ICR_LSC) {
3978 hw->mac.get_link_status = 1;
3979 /* guard against interrupt when we're going down */
3980 if (!test_bit(__IGB_DOWN, &adapter->state))
3981 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3982 }
3983
3984 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3985 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3986
3987 return IRQ_HANDLED;
3988}
3989
047e0030 3990static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 3991{
047e0030 3992 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 3993
047e0030
AD		 3994 if (!q_vector->set_itr)
3995 return;
73cd78f1 3996
047e0030
AD		 3997 if (!itr_val)
3998 itr_val = 0x4;
661086df 3999
047e0030
AD		 4000 if (q_vector->itr_shift)
4001 itr_val |= itr_val << q_vector->itr_shift;
661086df 4002 else
047e0030 4003 itr_val |= 0x8000000;
661086df 4004
047e0030
AD		 4005 writel(itr_val, q_vector->itr_register);
4006 q_vector->set_itr = 0;
6eb5a7f1
AD		 4007}
4008
047e0030 4009static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4010{
047e0030 4011 struct igb_q_vector *q_vector = data;
9d5c8243 4012
047e0030
AD		 4013 /* Write the ITR value calculated from the previous interrupt. */
4014 igb_write_itr(q_vector);
9d5c8243 4015
047e0030 4016 napi_schedule(&q_vector->napi);
844290e5 4017
047e0030 4018 return IRQ_HANDLED;
fe4506b6
JC		 4019}
4020
421e02f0 4021#ifdef CONFIG_IGB_DCA
047e0030 4022static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4023{
047e0030 4024 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4025 struct e1000_hw *hw = &adapter->hw;
4026 int cpu = get_cpu();
fe4506b6 4027
047e0030
AD		 4028 if (q_vector->cpu == cpu)
4029 goto out_no_update;
4030
4031 if (q_vector->tx_ring) {
4032 int q = q_vector->tx_ring->reg_idx;
4033 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4034 if (hw->mac.type == e1000_82575) {
4035 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4036 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4037 } else {
047e0030
AD		 4038 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4039 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4040 E1000_DCA_TXCTRL_CPUID_SHIFT;
4041 }
4042 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4043 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4044 }
4045 if (q_vector->rx_ring) {
4046 int q = q_vector->rx_ring->reg_idx;
4047 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4048 if (hw->mac.type == e1000_82575) {
2d064c06 4049 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4050 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4051 } else {
4052 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4053 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4054 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4055 }
fe4506b6
JC		 4056 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4057 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4058 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4059 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4060 }
047e0030
AD		 4061 q_vector->cpu = cpu;
4062out_no_update:
fe4506b6
JC		 4063 put_cpu();
4064}
4065
4066static void igb_setup_dca(struct igb_adapter *adapter)
4067{
7e0e99ef 4068 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4069 int i;
4070
7dfc16fa 4071 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4072 return;
4073
7e0e99ef
AD		 4074 /* Always use CB2 mode, difference is masked in the CB driver. */
4075 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4076
047e0030
AD		 4077 for (i = 0; i < adapter->num_q_vectors; i++) {
4078 struct igb_q_vector *q_vector = adapter->q_vector[i];
4079 q_vector->cpu = -1;
4080 igb_update_dca(q_vector);
fe4506b6
JC		 4081 }
4082}
4083
4084static int __igb_notify_dca(struct device *dev, void *data)
4085{
4086 struct net_device *netdev = dev_get_drvdata(dev);
4087 struct igb_adapter *adapter = netdev_priv(netdev);
4088 struct e1000_hw *hw = &adapter->hw;
4089 unsigned long event = *(unsigned long *)data;
4090
4091 switch (event) {
4092 case DCA_PROVIDER_ADD:
4093 /* if already enabled, don't do it again */
7dfc16fa 4094 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4095 break;
fe4506b6
JC		 4096 /* Always use CB2 mode, difference is masked
4097 * in the CB driver. */
cbd347ad 4098 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 4099 if (dca_add_requester(dev) == 0) {
bbd98fe4 4100 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 4101 dev_info(&adapter->pdev->dev, "DCA enabled\n");
4102 igb_setup_dca(adapter);
4103 break;
4104 }
4105 /* Fall Through since DCA is disabled. */
4106 case DCA_PROVIDER_REMOVE:
7dfc16fa 4107 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4108 /* without this a class_device is left
047e0030 4109 * hanging around in the sysfs model */
fe4506b6
JC		 4110 dca_remove_requester(dev);
4111 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 4112 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4113 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4114 }
4115 break;
4116 }
bbd98fe4 4117
fe4506b6 4118 return 0;
9d5c8243
AK		 4119}
4120
fe4506b6
JC		 4121static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4122 void *p)
4123{
4124 int ret_val;
4125
4126 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4127 __igb_notify_dca);
4128
4129 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4130}
421e02f0 4131#endif /* CONFIG_IGB_DCA */
9d5c8243 4132
4ae196df
AD		 4133static void igb_ping_all_vfs(struct igb_adapter *adapter)
4134{
4135 struct e1000_hw *hw = &adapter->hw;
4136 u32 ping;
4137 int i;
4138
4139 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4140 ping = E1000_PF_CONTROL_MSG;
4141 if (adapter->vf_data[i].clear_to_send)
4142 ping |= E1000_VT_MSGTYPE_CTS;
4143 igb_write_mbx(hw, &ping, 1, i);
4144 }
4145}
4146
4147static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4148 u32 *msgbuf, u32 vf)
4149{
4150 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4151 u16 *hash_list = (u16 *)&msgbuf[1];
4152 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4153 int i;
4154
4155 /* only up to 30 hash values supported */
4156 if (n > 30)
4157 n = 30;
4158
4159 /* salt away the number of multi cast addresses assigned
4160 * to this VF for later use to restore when the PF multi cast
4161 * list changes
4162 */
4163 vf_data->num_vf_mc_hashes = n;
4164
4165 /* VFs are limited to using the MTA hash table for their multicast
4166 * addresses */
4167 for (i = 0; i < n; i++)
a419aef8 4168 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4169
4170 /* Flush and reset the mta with the new values */
ff41f8dc 4171 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4172
4173 return 0;
4174}
4175
4176static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4177{
4178 struct e1000_hw *hw = &adapter->hw;
4179 struct vf_data_storage *vf_data;
4180 int i, j;
4181
4182 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4183 vf_data = &adapter->vf_data[i];
75f4f382 4184 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 4185 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4186 }
4187}
4188
4189static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4190{
4191 struct e1000_hw *hw = &adapter->hw;
4192 u32 pool_mask, reg, vid;
4193 int i;
4194
4195 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4196
4197 /* Find the vlan filter for this id */
4198 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4199 reg = rd32(E1000_VLVF(i));
4200
4201 /* remove the vf from the pool */
4202 reg &= ~pool_mask;
4203
4204 /* if pool is empty then remove entry from vfta */
4205 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4206 (reg & E1000_VLVF_VLANID_ENABLE)) {
4207 reg = 0;
4208 vid = reg & E1000_VLVF_VLANID_MASK;
4209 igb_vfta_set(hw, vid, false);
4210 }
4211
4212 wr32(E1000_VLVF(i), reg);
4213 }
ae641bdc
AD		 4214
4215 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4216}
4217
4218static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4219{
4220 struct e1000_hw *hw = &adapter->hw;
4221 u32 reg, i;
4222
4223 /* It is an error to call this function when VFs are not enabled */
4224 if (!adapter->vfs_allocated_count)
4225 return -1;
4226
4227 /* Find the vlan filter for this id */
4228 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4229 reg = rd32(E1000_VLVF(i));
4230 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4231 vid == (reg & E1000_VLVF_VLANID_MASK))
4232 break;
4233 }
4234
4235 if (add) {
4236 if (i == E1000_VLVF_ARRAY_SIZE) {
4237 /* Did not find a matching VLAN ID entry that was
4238 * enabled. Search for a free filter entry, i.e.
4239 * one without the enable bit set
4240 */
4241 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4242 reg = rd32(E1000_VLVF(i));
4243 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4244 break;
4245 }
4246 }
4247 if (i < E1000_VLVF_ARRAY_SIZE) {
4248 /* Found an enabled/available entry */
4249 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4250
4251 /* if !enabled we need to set this up in vfta */
4252 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4253 /* add VID to filter table, if bit already set
4254 * PF must have added it outside of table */
4255 if (igb_vfta_set(hw, vid, true))
4256 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4257 adapter->vfs_allocated_count);
4ae196df
AD		 4258 reg |= E1000_VLVF_VLANID_ENABLE;
4259 }
cad6d05f
AD		 4260 reg &= ~E1000_VLVF_VLANID_MASK;
4261 reg |= vid;
4ae196df
AD		 4262
4263 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4264
4265 /* do not modify RLPML for PF devices */
4266 if (vf >= adapter->vfs_allocated_count)
4267 return 0;
4268
4269 if (!adapter->vf_data[vf].vlans_enabled) {
4270 u32 size;
4271 reg = rd32(E1000_VMOLR(vf));
4272 size = reg & E1000_VMOLR_RLPML_MASK;
4273 size += 4;
4274 reg &= ~E1000_VMOLR_RLPML_MASK;
4275 reg |= size;
4276 wr32(E1000_VMOLR(vf), reg);
4277 }
4278 adapter->vf_data[vf].vlans_enabled++;
4279
4ae196df
AD		 4280 return 0;
4281 }
4282 } else {
4283 if (i < E1000_VLVF_ARRAY_SIZE) {
4284 /* remove vf from the pool */
4285 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4286 /* if pool is empty then remove entry from vfta */
4287 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4288 reg = 0;
4289 igb_vfta_set(hw, vid, false);
4290 }
4291 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4292
4293 /* do not modify RLPML for PF devices */
4294 if (vf >= adapter->vfs_allocated_count)
4295 return 0;
4296
4297 adapter->vf_data[vf].vlans_enabled--;
4298 if (!adapter->vf_data[vf].vlans_enabled) {
4299 u32 size;
4300 reg = rd32(E1000_VMOLR(vf));
4301 size = reg & E1000_VMOLR_RLPML_MASK;
4302 size -= 4;
4303 reg &= ~E1000_VMOLR_RLPML_MASK;
4304 reg |= size;
4305 wr32(E1000_VMOLR(vf), reg);
4306 }
4ae196df
AD		 4307 return 0;
4308 }
4309 }
4310 return -1;
4311}
4312
4313static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4314{
4315 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4316 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4317
4318 return igb_vlvf_set(adapter, vid, add, vf);
4319}
4320
4321static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4322{
4323 struct e1000_hw *hw = &adapter->hw;
4324
4325 /* disable mailbox functionality for vf */
4326 adapter->vf_data[vf].clear_to_send = false;
4327
4328 /* reset offloads to defaults */
4329 igb_set_vmolr(hw, vf);
4330
4331 /* reset vlans for device */
4332 igb_clear_vf_vfta(adapter, vf);
4333
4334 /* reset multicast table array for vf */
4335 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4336
4337 /* Flush and reset the mta with the new values */
ff41f8dc 4338 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4339}
4340
4341static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4342{
4343 struct e1000_hw *hw = &adapter->hw;
4344 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4345 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4346 u32 reg, msgbuf[3];
4347 u8 *addr = (u8 *)(&msgbuf[1]);
4348
4349 /* process all the same items cleared in a function level reset */
4350 igb_vf_reset_event(adapter, vf);
4351
4352 /* set vf mac address */
26ad9178 4353 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4354
4355 /* enable transmit and receive for vf */
4356 reg = rd32(E1000_VFTE);
4357 wr32(E1000_VFTE, reg | (1 << vf));
4358 reg = rd32(E1000_VFRE);
4359 wr32(E1000_VFRE, reg | (1 << vf));
4360
4361 /* enable mailbox functionality for vf */
4362 adapter->vf_data[vf].clear_to_send = true;
4363
4364 /* reply to reset with ack and vf mac address */
4365 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4366 memcpy(addr, vf_mac, 6);
4367 igb_write_mbx(hw, msgbuf, 3, vf);
4368}
4369
4370static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4371{
4372 unsigned char *addr = (char *)&msg[1];
4373 int err = -1;
4374
4375 if (is_valid_ether_addr(addr))
4376 err = igb_set_vf_mac(adapter, vf, addr);
4377
4378 return err;
4379
4380}
4381
4382static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4383{
4384 struct e1000_hw *hw = &adapter->hw;
4385 u32 msg = E1000_VT_MSGTYPE_NACK;
4386
4387 /* if device isn't clear to send it shouldn't be reading either */
4388 if (!adapter->vf_data[vf].clear_to_send)
4389 igb_write_mbx(hw, &msg, 1, vf);
4390}
4391
4392
4393static void igb_msg_task(struct igb_adapter *adapter)
4394{
4395 struct e1000_hw *hw = &adapter->hw;
4396 u32 vf;
4397
4398 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4399 /* process any reset requests */
4400 if (!igb_check_for_rst(hw, vf)) {
4401 adapter->vf_data[vf].clear_to_send = false;
4402 igb_vf_reset_event(adapter, vf);
4403 }
4404
4405 /* process any messages pending */
4406 if (!igb_check_for_msg(hw, vf))
4407 igb_rcv_msg_from_vf(adapter, vf);
4408
4409 /* process any acks */
4410 if (!igb_check_for_ack(hw, vf))
4411 igb_rcv_ack_from_vf(adapter, vf);
4412
4413 }
4414}
4415
4416static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4417{
4418 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4419 u32 msgbuf[mbx_size];
4420 struct e1000_hw *hw = &adapter->hw;
4421 s32 retval;
4422
4423 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4424
4425 if (retval)
4426 dev_err(&adapter->pdev->dev,
4427 "Error receiving message from VF\n");
4428
4429 /* this is a message we already processed, do nothing */
4430 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4431 return retval;
4432
4433 /*
4434 * until the vf completes a reset it should not be
4435 * allowed to start any configuration.
4436 */
4437
4438 if (msgbuf[0] == E1000_VF_RESET) {
4439 igb_vf_reset_msg(adapter, vf);
4440
4441 return retval;
4442 }
4443
4444 if (!adapter->vf_data[vf].clear_to_send) {
4445 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4446 igb_write_mbx(hw, msgbuf, 1, vf);
4447 return retval;
4448 }
4449
4450 switch ((msgbuf[0] & 0xFFFF)) {
4451 case E1000_VF_SET_MAC_ADDR:
4452 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4453 break;
4454 case E1000_VF_SET_MULTICAST:
4455 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4456 break;
4457 case E1000_VF_SET_LPE:
4458 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4459 break;
4460 case E1000_VF_SET_VLAN:
4461 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4462 break;
4463 default:
4464 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4465 retval = -1;
4466 break;
4467 }
4468
4469 /* notify the VF of the results of what it sent us */
4470 if (retval)
4471 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4472 else
4473 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4474
4475 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4476
4477 igb_write_mbx(hw, msgbuf, 1, vf);
4478
4479 return retval;
4480}
4481
68d480c4
AD		 4482/**
4483 * igb_set_uta - Set unicast filter table address
4484 * @adapter: board private structure
4485 *
4486 * The unicast table address is a register array of 32-bit registers.
4487 * The table is meant to be used in a way similar to how the MTA is used
4488 * however due to certain limitations in the hardware it is necessary to
4489 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4490 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4491 **/
4492static void igb_set_uta(struct igb_adapter *adapter)
4493{
4494 struct e1000_hw *hw = &adapter->hw;
4495 int i;
4496
4497 /* The UTA table only exists on 82576 hardware and newer */
4498 if (hw->mac.type < e1000_82576)
4499 return;
4500
4501 /* we only need to do this if VMDq is enabled */
4502 if (!adapter->vfs_allocated_count)
4503 return;
4504
4505 for (i = 0; i < hw->mac.uta_reg_count; i++)
4506 array_wr32(E1000_UTA, i, ~0);
4507}
4508
9d5c8243
AK		 4509/**
4510 * igb_intr_msi - Interrupt Handler
4511 * @irq: interrupt number
4512 * @data: pointer to a network interface device structure
4513 **/
4514static irqreturn_t igb_intr_msi(int irq, void *data)
4515{
047e0030
AD		 4516 struct igb_adapter *adapter = data;
4517 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4518 struct e1000_hw *hw = &adapter->hw;
4519 /* read ICR disables interrupts using IAM */
4520 u32 icr = rd32(E1000_ICR);
4521
047e0030 4522 igb_write_itr(q_vector);
9d5c8243 4523
047e0030 4524 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4525 /* HW is reporting DMA is out of sync */
4526 adapter->stats.doosync++;
4527 }
4528
9d5c8243
AK		 4529 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4530 hw->mac.get_link_status = 1;
4531 if (!test_bit(__IGB_DOWN, &adapter->state))
4532 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4533 }
4534
047e0030 4535 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4536
4537 return IRQ_HANDLED;
4538}
4539
4540/**
4a3c6433 4541 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4542 * @irq: interrupt number
4543 * @data: pointer to a network interface device structure
4544 **/
4545static irqreturn_t igb_intr(int irq, void *data)
4546{
047e0030
AD		 4547 struct igb_adapter *adapter = data;
4548 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4549 struct e1000_hw *hw = &adapter->hw;
4550 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4551 * need for the IMC write */
4552 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4553 if (!icr)
4554 return IRQ_NONE; /* Not our interrupt */
4555
047e0030 4556 igb_write_itr(q_vector);
9d5c8243
AK		 4557
4558 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4559 * not set, then the adapter didn't send an interrupt */
4560 if (!(icr & E1000_ICR_INT_ASSERTED))
4561 return IRQ_NONE;
4562
047e0030 4563 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4564 /* HW is reporting DMA is out of sync */
4565 adapter->stats.doosync++;
4566 }
4567
9d5c8243
AK		 4568 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4569 hw->mac.get_link_status = 1;
4570 /* guard against interrupt when we're going down */
4571 if (!test_bit(__IGB_DOWN, &adapter->state))
4572 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4573 }
4574
047e0030 4575 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4576
4577 return IRQ_HANDLED;
4578}
4579
047e0030 4580static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4581{
047e0030 4582 struct igb_adapter *adapter = q_vector->adapter;
46544258 4583 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4584
46544258 4585 if (adapter->itr_setting & 3) {
047e0030 4586 if (!adapter->msix_entries)
6eb5a7f1 4587 igb_set_itr(adapter);
46544258 4588 else
047e0030 4589 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4590 }
4591
46544258
AD		 4592 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4593 if (adapter->msix_entries)
047e0030 4594 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4595 else
4596 igb_irq_enable(adapter);
4597 }
9d5c8243
AK		 4598}
4599
46544258
AD		 4600/**
4601 * igb_poll - NAPI Rx polling callback
4602 * @napi: napi polling structure
4603 * @budget: count of how many packets we should handle
4604 **/
4605static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4606{
047e0030
AD		 4607 struct igb_q_vector *q_vector = container_of(napi,
4608 struct igb_q_vector,
4609 napi);
4610 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4611
421e02f0 4612#ifdef CONFIG_IGB_DCA
047e0030
AD		 4613 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4614 igb_update_dca(q_vector);
fe4506b6 4615#endif
047e0030
AD		 4616 if (q_vector->tx_ring)
4617 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4618
047e0030
AD		 4619 if (q_vector->rx_ring)
4620 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4621
4622 if (!tx_clean_complete)
4623 work_done = budget;
46544258 4624
9d5c8243 4625 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4626 if (work_done < budget) {
288379f0 4627 napi_complete(napi);
047e0030 4628 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4629 }
4630
46544258 4631 return work_done;
9d5c8243 4632}
6d8126f9 4633
33af6bcc
PO		 4634/**
4635 * igb_hwtstamp - utility function which checks for TX time stamp
4636 * @adapter: board private structure
4637 * @skb: packet that was just sent
4638 *
4639 * If we were asked to do hardware stamping and such a time stamp is
4640 * available, then it must have been for this skb here because we only
4641 * allow only one such packet into the queue.
4642 */
4643static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4644{
4645 union skb_shared_tx *shtx = skb_tx(skb);
4646 struct e1000_hw *hw = &adapter->hw;
4647
4648 if (unlikely(shtx->hardware)) {
4649 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4650 if (valid) {
4651 u64 regval = rd32(E1000_TXSTMPL);
4652 u64 ns;
4653 struct skb_shared_hwtstamps shhwtstamps;
4654
4655 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4656 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4657 ns = timecounter_cyc2time(&adapter->clock,
4658 regval);
4659 timecompare_update(&adapter->compare, ns);
4660 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4661 shhwtstamps.syststamp =
4662 timecompare_transform(&adapter->compare, ns);
4663 skb_tstamp_tx(skb, &shhwtstamps);
4664 }
33af6bcc
PO		 4665 }
4666}
4667
9d5c8243
AK		 4668/**
4669 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4670 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4671 * returns true if ring is completely cleaned
4672 **/
047e0030 4673static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4674{
047e0030
AD		 4675 struct igb_adapter *adapter = q_vector->adapter;
4676 struct igb_ring *tx_ring = q_vector->tx_ring;
3b644cf6 4677 struct net_device *netdev = adapter->netdev;
0e014cb1 4678 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4679 struct igb_buffer *buffer_info;
4680 struct sk_buff *skb;
0e014cb1 4681 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4682 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4683 unsigned int i, eop, count = 0;
4684 bool cleaned = false;
9d5c8243 4685
9d5c8243 4686 i = tx_ring->next_to_clean;
0e014cb1
AD		 4687 eop = tx_ring->buffer_info[i].next_to_watch;
4688 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4689
4690 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4691 (count < tx_ring->count)) {
4692 for (cleaned = false; !cleaned; count++) {
4693 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4694 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4695 cleaned = (i == eop);
9d5c8243
AK		 4696 skb = buffer_info->skb;
4697
4698 if (skb) {
4699 unsigned int segs, bytecount;
4700 /* gso_segs is currently only valid for tcp */
4701 segs = skb_shinfo(skb)->gso_segs ?: 1;
4702 /* multiply data chunks by size of headers */
4703 bytecount = ((segs - 1) * skb_headlen(skb)) +
4704 skb->len;
4705 total_packets += segs;
4706 total_bytes += bytecount;
33af6bcc
PO		 4707
4708 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4709 }
4710
80785298 4711 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 4712 tx_desc->wb.status = 0;
9d5c8243
AK		 4713
4714 i++;
4715 if (i == tx_ring->count)
4716 i = 0;
9d5c8243 4717 }
0e014cb1
AD		 4718 eop = tx_ring->buffer_info[i].next_to_watch;
4719 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4720 }
4721
9d5c8243
AK		 4722 tx_ring->next_to_clean = i;
4723
fc7d345d 4724 if (unlikely(count &&
9d5c8243 4725 netif_carrier_ok(netdev) &&
c493ea45 4726 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4727 /* Make sure that anybody stopping the queue after this
4728 * sees the new next_to_clean.
4729 */
4730 smp_mb();
661086df
PWJ		 4731 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4732 !(test_bit(__IGB_DOWN, &adapter->state))) {
4733 netif_wake_subqueue(netdev, tx_ring->queue_index);
4734 ++adapter->restart_queue;
4735 }
9d5c8243
AK		 4736 }
4737
4738 if (tx_ring->detect_tx_hung) {
4739 /* Detect a transmit hang in hardware, this serializes the
4740 * check with the clearing of time_stamp and movement of i */
4741 tx_ring->detect_tx_hung = false;
4742 if (tx_ring->buffer_info[i].time_stamp &&
4743 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4744 (adapter->tx_timeout_factor * HZ))
4745 && !(rd32(E1000_STATUS) &
4746 E1000_STATUS_TXOFF)) {
4747
9d5c8243 4748 /* detected Tx unit hang */
80785298 4749 dev_err(&tx_ring->pdev->dev,
9d5c8243 4750 "Detected Tx Unit Hang\n"
2d064c06 4751 " Tx Queue <%d>\n"
9d5c8243
AK		 4752 " TDH <%x>\n"
4753 " TDT <%x>\n"
4754 " next_to_use <%x>\n"
4755 " next_to_clean <%x>\n"
9d5c8243
AK		 4756 "buffer_info[next_to_clean]\n"
4757 " time_stamp <%lx>\n"
0e014cb1 4758 " next_to_watch <%x>\n"
9d5c8243
AK		 4759 " jiffies <%lx>\n"
4760 " desc.status <%x>\n",
2d064c06 4761 tx_ring->queue_index,
fce99e34
AD		 4762 readl(tx_ring->head),
4763 readl(tx_ring->tail),
9d5c8243
AK		 4764 tx_ring->next_to_use,
4765 tx_ring->next_to_clean,
9d5c8243 4766 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4767 eop,
9d5c8243 4768 jiffies,
0e014cb1 4769 eop_desc->wb.status);
661086df 4770 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4771 }
4772 }
4773 tx_ring->total_bytes += total_bytes;
4774 tx_ring->total_packets += total_packets;
e21ed353
AD		 4775 tx_ring->tx_stats.bytes += total_bytes;
4776 tx_ring->tx_stats.packets += total_packets;
8d24e933
AK		 4777 netdev->stats.tx_bytes += total_bytes;
4778 netdev->stats.tx_packets += total_packets;
0e014cb1 4779 return (count < tx_ring->count);
9d5c8243
AK		 4780}
4781
9d5c8243
AK		 4782/**
4783 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 4784 * @q_vector: structure containing interrupt and ring information
4785 * @skb: packet to send up
4786 * @vlan_tag: vlan tag for packet
9d5c8243 4787 **/
047e0030
AD		 4788static void igb_receive_skb(struct igb_q_vector *q_vector,
4789 struct sk_buff *skb,
4790 u16 vlan_tag)
4791{
4792 struct igb_adapter *adapter = q_vector->adapter;
4793
4794 if (vlan_tag)
4795 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
4796 vlan_tag, skb);
182ff8df 4797 else
047e0030 4798 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 4799}
4800
9d5c8243
AK		 4801static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4802 u32 status_err, struct sk_buff *skb)
4803{
4804 skb->ip_summed = CHECKSUM_NONE;
4805
4806 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4807 if ((status_err & E1000_RXD_STAT_IXSM) ||
4808 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4809 return;
4810 /* TCP/UDP checksum error bit is set */
4811 if (status_err &
4812 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4813 /*
4814 * work around errata with sctp packets where the TCPE aka
4815 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4816 * packets, (aka let the stack check the crc32c)
4817 */
4818 if (!((adapter->hw.mac.type == e1000_82576) &&
4819 (skb->len == 60)))
4820 adapter->hw_csum_err++;
9d5c8243 4821 /* let the stack verify checksum errors */
9d5c8243
AK		 4822 return;
4823 }
4824 /* It must be a TCP or UDP packet with a valid checksum */
4825 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4826 skb->ip_summed = CHECKSUM_UNNECESSARY;
4827
b9473560 4828 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4829}
4830
2d94d8ab
AD		 4831static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4832 union e1000_adv_rx_desc *rx_desc)
4833{
4834 /* HW will not DMA in data larger than the given buffer, even if it
4835 * parses the (NFS, of course) header to be larger. In that case, it
4836 * fills the header buffer and spills the rest into the page.
4837 */
4838 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4839 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
6ec43fe6
AD		 4840 if (hlen > adapter->rx_buffer_len)
4841 hlen = adapter->rx_buffer_len;
2d94d8ab
AD		 4842 return hlen;
4843}
4844
047e0030
AD		 4845static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
4846 int *work_done, int budget)
9d5c8243 4847{
047e0030 4848 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 4849 struct net_device *netdev = adapter->netdev;
047e0030 4850 struct igb_ring *rx_ring = q_vector->rx_ring;
33af6bcc 4851 struct e1000_hw *hw = &adapter->hw;
80785298 4852 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 4853 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4854 struct igb_buffer *buffer_info , *next_buffer;
4855 struct sk_buff *skb;
9d5c8243
AK		 4856 bool cleaned = false;
4857 int cleaned_count = 0;
4858 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4859 unsigned int i;
2d94d8ab
AD		 4860 u32 staterr;
4861 u16 length;
047e0030 4862 u16 vlan_tag;
9d5c8243
AK		 4863
4864 i = rx_ring->next_to_clean;
69d3ca53 4865 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4866 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4867 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4868
4869 while (staterr & E1000_RXD_STAT_DD) {
4870 if (*work_done >= budget)
4871 break;
4872 (*work_done)++;
9d5c8243 4873
69d3ca53
AD		 4874 skb = buffer_info->skb;
4875 prefetch(skb->data - NET_IP_ALIGN);
4876 buffer_info->skb = NULL;
4877
4878 i++;
4879 if (i == rx_ring->count)
4880 i = 0;
4881 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4882 prefetch(next_rxd);
4883 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4884
4885 length = le16_to_cpu(rx_desc->wb.upper.length);
4886 cleaned = true;
4887 cleaned_count++;
4888
2d94d8ab 4889 if (buffer_info->dma) {
bf36c1a0 4890 pci_unmap_single(pdev, buffer_info->dma,
6ec43fe6 4891 adapter->rx_buffer_len,
bf36c1a0 4892 PCI_DMA_FROMDEVICE);
91615f76 4893 buffer_info->dma = 0;
6ec43fe6
AD		 4894 if (adapter->rx_buffer_len >= IGB_RXBUFFER_1024) {
4895 skb_put(skb, length);
4896 goto send_up;
4897 }
4898 skb_put(skb, igb_get_hlen(adapter, rx_desc));
bf36c1a0
AD		 4899 }
4900
4901 if (length) {
9d5c8243 4902 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4903 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4904 buffer_info->page_dma = 0;
bf36c1a0
AD		 4905
4906 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4907 buffer_info->page,
4908 buffer_info->page_offset,
4909 length);
4910
6ec43fe6 4911 if (page_count(buffer_info->page) != 1)
bf36c1a0
AD		 4912 buffer_info->page = NULL;
4913 else
4914 get_page(buffer_info->page);
9d5c8243
AK		 4915
4916 skb->len += length;
4917 skb->data_len += length;
9d5c8243 4918
bf36c1a0 4919 skb->truesize += length;
9d5c8243 4920 }
9d5c8243 4921
bf36c1a0 4922 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4923 buffer_info->skb = next_buffer->skb;
4924 buffer_info->dma = next_buffer->dma;
4925 next_buffer->skb = skb;
4926 next_buffer->dma = 0;
bf36c1a0
AD		 4927 goto next_desc;
4928 }
69d3ca53 4929send_up:
33af6bcc
PO		 4930 /*
4931 * If this bit is set, then the RX registers contain
4932 * the time stamp. No other packet will be time
4933 * stamped until we read these registers, so read the
4934 * registers to make them available again. Because
4935 * only one packet can be time stamped at a time, we
4936 * know that the register values must belong to this
4937 * one here and therefore we don't need to compare
4938 * any of the additional attributes stored for it.
4939 *
4940 * If nothing went wrong, then it should have a
4941 * skb_shared_tx that we can turn into a
4942 * skb_shared_hwtstamps.
4943 *
4944 * TODO: can time stamping be triggered (thus locking
4945 * the registers) without the packet reaching this point
4946 * here? In that case RX time stamping would get stuck.
4947 *
4948 * TODO: in "time stamp all packets" mode this bit is
4949 * not set. Need a global flag for this mode and then
4950 * always read the registers. Cannot be done without
4951 * a race condition.
4952 */
4953 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4954 u64 regval;
4955 u64 ns;
4956 struct skb_shared_hwtstamps *shhwtstamps =
4957 skb_hwtstamps(skb);
4958
4959 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4960 "igb: no RX time stamp available for time stamped packet");
4961 regval = rd32(E1000_RXSTMPL);
4962 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4963 ns = timecounter_cyc2time(&adapter->clock, regval);
4964 timecompare_update(&adapter->compare, ns);
4965 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4966 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4967 shhwtstamps->syststamp =
4968 timecompare_transform(&adapter->compare, ns);
4969 }
4970
9d5c8243
AK		 4971 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4972 dev_kfree_skb_irq(skb);
4973 goto next_desc;
4974 }
9d5c8243
AK		 4975
4976 total_bytes += skb->len;
4977 total_packets++;
4978
4979 igb_rx_checksum_adv(adapter, staterr, skb);
4980
4981 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 4982 skb_record_rx_queue(skb, rx_ring->queue_index);
4983
4984 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
4985 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 4986
047e0030 4987 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 4988
9d5c8243
AK		 4989next_desc:
4990 rx_desc->wb.upper.status_error = 0;
4991
4992 /* return some buffers to hardware, one at a time is too slow */
4993 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4994 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4995 cleaned_count = 0;
4996 }
4997
4998 /* use prefetched values */
4999 rx_desc = next_rxd;
5000 buffer_info = next_buffer;
9d5c8243
AK		 5001 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5002 }
bf36c1a0 5003
9d5c8243 5004 rx_ring->next_to_clean = i;
c493ea45 5005 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5006
5007 if (cleaned_count)
3b644cf6 5008 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5009
5010 rx_ring->total_packets += total_packets;
5011 rx_ring->total_bytes += total_bytes;
5012 rx_ring->rx_stats.packets += total_packets;
5013 rx_ring->rx_stats.bytes += total_bytes;
8d24e933
AK		 5014 netdev->stats.rx_bytes += total_bytes;
5015 netdev->stats.rx_packets += total_packets;
9d5c8243
AK		 5016 return cleaned;
5017}
5018
9d5c8243
AK		 5019/**
5020 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5021 * @adapter: address of board private structure
5022 **/
3b644cf6 5023static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 5024 int cleaned_count)
5025{
047e0030 5026 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243 5027 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 5028 union e1000_adv_rx_desc *rx_desc;
5029 struct igb_buffer *buffer_info;
5030 struct sk_buff *skb;
5031 unsigned int i;
db761762 5032 int bufsz;
9d5c8243
AK		 5033
5034 i = rx_ring->next_to_use;
5035 buffer_info = &rx_ring->buffer_info[i];
5036
6ec43fe6 5037 bufsz = adapter->rx_buffer_len;
db761762 5038
9d5c8243
AK		 5039 while (cleaned_count--) {
5040 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5041
6ec43fe6 5042 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5043 if (!buffer_info->page) {
bf36c1a0
AD		 5044 buffer_info->page = alloc_page(GFP_ATOMIC);
5045 if (!buffer_info->page) {
5046 adapter->alloc_rx_buff_failed++;
5047 goto no_buffers;
5048 }
5049 buffer_info->page_offset = 0;
5050 } else {
5051 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5052 }
5053 buffer_info->page_dma =
80785298 5054 pci_map_page(rx_ring->pdev, buffer_info->page,
bf36c1a0
AD		 5055 buffer_info->page_offset,
5056 PAGE_SIZE / 2,
9d5c8243
AK		 5057 PCI_DMA_FROMDEVICE);
5058 }
5059
5060 if (!buffer_info->skb) {
89d71a66 5061 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243
AK		 5062 if (!skb) {
5063 adapter->alloc_rx_buff_failed++;
5064 goto no_buffers;
5065 }
5066
9d5c8243 5067 buffer_info->skb = skb;
80785298
AD		 5068 buffer_info->dma = pci_map_single(rx_ring->pdev,
5069 skb->data,
9d5c8243
AK		 5070 bufsz,
5071 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 5072 }
5073 /* Refresh the desc even if buffer_addrs didn't change because
5074 * each write-back erases this info. */
6ec43fe6 5075 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5076 rx_desc->read.pkt_addr =
5077 cpu_to_le64(buffer_info->page_dma);
5078 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5079 } else {
5080 rx_desc->read.pkt_addr =
5081 cpu_to_le64(buffer_info->dma);
5082 rx_desc->read.hdr_addr = 0;
5083 }
5084
5085 i++;
5086 if (i == rx_ring->count)
5087 i = 0;
5088 buffer_info = &rx_ring->buffer_info[i];
5089 }
5090
5091no_buffers:
5092 if (rx_ring->next_to_use != i) {
5093 rx_ring->next_to_use = i;
5094 if (i == 0)
5095 i = (rx_ring->count - 1);
5096 else
5097 i--;
5098
5099 /* Force memory writes to complete before letting h/w
5100 * know there are new descriptors to fetch. (Only
5101 * applicable for weak-ordered memory model archs,
5102 * such as IA-64). */
5103 wmb();
fce99e34 5104 writel(i, rx_ring->tail);
9d5c8243
AK		 5105 }
5106}
5107
5108/**
5109 * igb_mii_ioctl -
5110 * @netdev:
5111 * @ifreq:
5112 * @cmd:
5113 **/
5114static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5115{
5116 struct igb_adapter *adapter = netdev_priv(netdev);
5117 struct mii_ioctl_data *data = if_mii(ifr);
5118
5119 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5120 return -EOPNOTSUPP;
5121
5122 switch (cmd) {
5123 case SIOCGMIIPHY:
5124 data->phy_id = adapter->hw.phy.addr;
5125 break;
5126 case SIOCGMIIREG:
f5f4cf08
AD		 5127 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5128 &data->val_out))
9d5c8243
AK		 5129 return -EIO;
5130 break;
5131 case SIOCSMIIREG:
5132 default:
5133 return -EOPNOTSUPP;
5134 }
5135 return 0;
5136}
5137
c6cb090b
PO		 5138/**
5139 * igb_hwtstamp_ioctl - control hardware time stamping
5140 * @netdev:
5141 * @ifreq:
5142 * @cmd:
5143 *
33af6bcc
PO		 5144 * Outgoing time stamping can be enabled and disabled. Play nice and
5145 * disable it when requested, although it shouldn't case any overhead
5146 * when no packet needs it. At most one packet in the queue may be
5147 * marked for time stamping, otherwise it would be impossible to tell
5148 * for sure to which packet the hardware time stamp belongs.
5149 *
5150 * Incoming time stamping has to be configured via the hardware
5151 * filters. Not all combinations are supported, in particular event
5152 * type has to be specified. Matching the kind of event packet is
5153 * not supported, with the exception of "all V2 events regardless of
5154 * level 2 or 4".
5155 *
c6cb090b
PO		 5156 **/
5157static int igb_hwtstamp_ioctl(struct net_device *netdev,
5158 struct ifreq *ifr, int cmd)
5159{
33af6bcc
PO		 5160 struct igb_adapter *adapter = netdev_priv(netdev);
5161 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5162 struct hwtstamp_config config;
33af6bcc
PO		 5163 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5164 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
5165 u32 tsync_rx_ctl_type = 0;
5166 u32 tsync_rx_cfg = 0;
5167 int is_l4 = 0;
5168 int is_l2 = 0;
5169 short port = 319; /* PTP */
5170 u32 regval;
c6cb090b
PO		 5171
5172 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5173 return -EFAULT;
5174
5175 /* reserved for future extensions */
5176 if (config.flags)
5177 return -EINVAL;
5178
33af6bcc
PO		 5179 switch (config.tx_type) {
5180 case HWTSTAMP_TX_OFF:
5181 tsync_tx_ctl_bit = 0;
5182 break;
5183 case HWTSTAMP_TX_ON:
5184 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5185 break;
5186 default:
5187 return -ERANGE;
5188 }
5189
5190 switch (config.rx_filter) {
5191 case HWTSTAMP_FILTER_NONE:
5192 tsync_rx_ctl_bit = 0;
5193 break;
5194 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5195 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5196 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5197 case HWTSTAMP_FILTER_ALL:
5198 /*
5199 * register TSYNCRXCFG must be set, therefore it is not
5200 * possible to time stamp both Sync and Delay_Req messages
5201 * => fall back to time stamping all packets
5202 */
5203 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
5204 config.rx_filter = HWTSTAMP_FILTER_ALL;
5205 break;
5206 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5207 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5208 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5209 is_l4 = 1;
5210 break;
5211 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5212 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5213 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5214 is_l4 = 1;
5215 break;
5216 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5217 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5218 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5219 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5220 is_l2 = 1;
5221 is_l4 = 1;
5222 config.rx_filter = HWTSTAMP_FILTER_SOME;
5223 break;
5224 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5225 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5226 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5227 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5228 is_l2 = 1;
5229 is_l4 = 1;
5230 config.rx_filter = HWTSTAMP_FILTER_SOME;
5231 break;
5232 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5233 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5234 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5235 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5236 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5237 is_l2 = 1;
5238 break;
5239 default:
5240 return -ERANGE;
5241 }
5242
5243 /* enable/disable TX */
5244 regval = rd32(E1000_TSYNCTXCTL);
5245 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5246 wr32(E1000_TSYNCTXCTL, regval);
5247
5248 /* enable/disable RX, define which PTP packets are time stamped */
5249 regval = rd32(E1000_TSYNCRXCTL);
5250 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5251 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5252 wr32(E1000_TSYNCRXCTL, regval);
5253 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5254
5255 /*
5256 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5257 * (Ethertype to filter on)
5258 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5259 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5260 */
5261 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5262
5263 /* L4 Queue Filter[0]: only filter by source and destination port */
5264 wr32(E1000_SPQF0, htons(port));
5265 wr32(E1000_IMIREXT(0), is_l4 ?
5266 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5267 wr32(E1000_IMIR(0), is_l4 ?
5268 (htons(port)
5269 | (0<<16) /* immediate interrupt disabled */
5270 | 0 /* (1<<17) bit cleared: do not bypass
5271 destination port check */)
5272 : 0);
5273 wr32(E1000_FTQF0, is_l4 ?
5274 (0x11 /* UDP */
5275 | (1<<15) /* VF not compared */
5276 | (1<<27) /* Enable Timestamping */
5277 | (7<<28) /* only source port filter enabled,
5278 source/target address and protocol
5279 masked */)
5280 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5281 enabled */));
5282
5283 wrfl();
5284
5285 adapter->hwtstamp_config = config;
5286
5287 /* clear TX/RX time stamp registers, just to be sure */
5288 regval = rd32(E1000_TXSTMPH);
5289 regval = rd32(E1000_RXSTMPH);
c6cb090b 5290
33af6bcc
PO		 5291 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5292 -EFAULT : 0;
c6cb090b
PO		 5293}
5294
9d5c8243
AK		 5295/**
5296 * igb_ioctl -
5297 * @netdev:
5298 * @ifreq:
5299 * @cmd:
5300 **/
5301static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5302{
5303 switch (cmd) {
5304 case SIOCGMIIPHY:
5305 case SIOCGMIIREG:
5306 case SIOCSMIIREG:
5307 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5308 case SIOCSHWTSTAMP:
5309 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5310 default:
5311 return -EOPNOTSUPP;
5312 }
5313}
5314
009bc06e
AD		 5315s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5316{
5317 struct igb_adapter *adapter = hw->back;
5318 u16 cap_offset;
5319
5320 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5321 if (!cap_offset)
5322 return -E1000_ERR_CONFIG;
5323
5324 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5325
5326 return 0;
5327}
5328
5329s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5330{
5331 struct igb_adapter *adapter = hw->back;
5332 u16 cap_offset;
5333
5334 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5335 if (!cap_offset)
5336 return -E1000_ERR_CONFIG;
5337
5338 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5339
5340 return 0;
5341}
5342
9d5c8243
AK		 5343static void igb_vlan_rx_register(struct net_device *netdev,
5344 struct vlan_group *grp)
5345{
5346 struct igb_adapter *adapter = netdev_priv(netdev);
5347 struct e1000_hw *hw = &adapter->hw;
5348 u32 ctrl, rctl;
5349
5350 igb_irq_disable(adapter);
5351 adapter->vlgrp = grp;
5352
5353 if (grp) {
5354 /* enable VLAN tag insert/strip */
5355 ctrl = rd32(E1000_CTRL);
5356 ctrl |= E1000_CTRL_VME;
5357 wr32(E1000_CTRL, ctrl);
5358
5359 /* enable VLAN receive filtering */
5360 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5361 rctl &= ~E1000_RCTL_CFIEN;
5362 wr32(E1000_RCTL, rctl);
5363 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5364 } else {
5365 /* disable VLAN tag insert/strip */
5366 ctrl = rd32(E1000_CTRL);
5367 ctrl &= ~E1000_CTRL_VME;
5368 wr32(E1000_CTRL, ctrl);
5369
9d5c8243
AK		 5370 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5371 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5372 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5373 }
9d5c8243
AK		 5374 }
5375
e1739522
AD		 5376 igb_rlpml_set(adapter);
5377
9d5c8243
AK		 5378 if (!test_bit(__IGB_DOWN, &adapter->state))
5379 igb_irq_enable(adapter);
5380}
5381
5382static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5383{
5384 struct igb_adapter *adapter = netdev_priv(netdev);
5385 struct e1000_hw *hw = &adapter->hw;
4ae196df 5386 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5387
28b0759c 5388 if ((hw->mng_cookie.status &
9d5c8243
AK		 5389 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5390 (vid == adapter->mng_vlan_id))
5391 return;
4ae196df
AD		 5392
5393 /* add vid to vlvf if sr-iov is enabled,
5394 * if that fails add directly to filter table */
5395 if (igb_vlvf_set(adapter, vid, true, pf_id))
5396 igb_vfta_set(hw, vid, true);
5397
9d5c8243
AK		 5398}
5399
5400static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5401{
5402 struct igb_adapter *adapter = netdev_priv(netdev);
5403 struct e1000_hw *hw = &adapter->hw;
4ae196df 5404 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5405
5406 igb_irq_disable(adapter);
5407 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5408
5409 if (!test_bit(__IGB_DOWN, &adapter->state))
5410 igb_irq_enable(adapter);
5411
5412 if ((adapter->hw.mng_cookie.status &
5413 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5414 (vid == adapter->mng_vlan_id)) {
5415 /* release control to f/w */
5416 igb_release_hw_control(adapter);
5417 return;
5418 }
5419
4ae196df
AD		 5420 /* remove vid from vlvf if sr-iov is enabled,
5421 * if not in vlvf remove from vfta */
5422 if (igb_vlvf_set(adapter, vid, false, pf_id))
5423 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5424}
5425
5426static void igb_restore_vlan(struct igb_adapter *adapter)
5427{
5428 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5429
5430 if (adapter->vlgrp) {
5431 u16 vid;
5432 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5433 if (!vlan_group_get_device(adapter->vlgrp, vid))
5434 continue;
5435 igb_vlan_rx_add_vid(adapter->netdev, vid);
5436 }
5437 }
5438}
5439
5440int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5441{
5442 struct e1000_mac_info *mac = &adapter->hw.mac;
5443
5444 mac->autoneg = 0;
5445
9d5c8243
AK		 5446 switch (spddplx) {
5447 case SPEED_10 + DUPLEX_HALF:
5448 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5449 break;
5450 case SPEED_10 + DUPLEX_FULL:
5451 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5452 break;
5453 case SPEED_100 + DUPLEX_HALF:
5454 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5455 break;
5456 case SPEED_100 + DUPLEX_FULL:
5457 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5458 break;
5459 case SPEED_1000 + DUPLEX_FULL:
5460 mac->autoneg = 1;
5461 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5462 break;
5463 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5464 default:
5465 dev_err(&adapter->pdev->dev,
5466 "Unsupported Speed/Duplex configuration\n");
5467 return -EINVAL;
5468 }
5469 return 0;
5470}
5471
3fe7c4c9 5472static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5473{
5474 struct net_device *netdev = pci_get_drvdata(pdev);
5475 struct igb_adapter *adapter = netdev_priv(netdev);
5476 struct e1000_hw *hw = &adapter->hw;
2d064c06 5477 u32 ctrl, rctl, status;
9d5c8243
AK		 5478 u32 wufc = adapter->wol;
5479#ifdef CONFIG_PM
5480 int retval = 0;
5481#endif
5482
5483 netif_device_detach(netdev);
5484
a88f10ec
AD		 5485 if (netif_running(netdev))
5486 igb_close(netdev);
5487
047e0030 5488 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5489
5490#ifdef CONFIG_PM
5491 retval = pci_save_state(pdev);
5492 if (retval)
5493 return retval;
5494#endif
5495
5496 status = rd32(E1000_STATUS);
5497 if (status & E1000_STATUS_LU)
5498 wufc &= ~E1000_WUFC_LNKC;
5499
5500 if (wufc) {
5501 igb_setup_rctl(adapter);
ff41f8dc 5502 igb_set_rx_mode(netdev);
9d5c8243
AK		 5503
5504 /* turn on all-multi mode if wake on multicast is enabled */
5505 if (wufc & E1000_WUFC_MC) {
5506 rctl = rd32(E1000_RCTL);
5507 rctl |= E1000_RCTL_MPE;
5508 wr32(E1000_RCTL, rctl);
5509 }
5510
5511 ctrl = rd32(E1000_CTRL);
5512 /* advertise wake from D3Cold */
5513 #define E1000_CTRL_ADVD3WUC 0x00100000
5514 /* phy power management enable */
5515 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5516 ctrl |= E1000_CTRL_ADVD3WUC;
5517 wr32(E1000_CTRL, ctrl);
5518
9d5c8243
AK		 5519 /* Allow time for pending master requests to run */
5520 igb_disable_pcie_master(&adapter->hw);
5521
5522 wr32(E1000_WUC, E1000_WUC_PME_EN);
5523 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5524 } else {
5525 wr32(E1000_WUC, 0);
5526 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5527 }
5528
3fe7c4c9
RW		 5529 *enable_wake = wufc || adapter->en_mng_pt;
5530 if (!*enable_wake)
2fb02a26 5531 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5532
5533 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5534 * would have already happened in close and is redundant. */
5535 igb_release_hw_control(adapter);
5536
5537 pci_disable_device(pdev);
5538
9d5c8243
AK		 5539 return 0;
5540}
5541
5542#ifdef CONFIG_PM
3fe7c4c9
RW		 5543static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5544{
5545 int retval;
5546 bool wake;
5547
5548 retval = __igb_shutdown(pdev, &wake);
5549 if (retval)
5550 return retval;
5551
5552 if (wake) {
5553 pci_prepare_to_sleep(pdev);
5554 } else {
5555 pci_wake_from_d3(pdev, false);
5556 pci_set_power_state(pdev, PCI_D3hot);
5557 }
5558
5559 return 0;
5560}
5561
9d5c8243
AK		 5562static int igb_resume(struct pci_dev *pdev)
5563{
5564 struct net_device *netdev = pci_get_drvdata(pdev);
5565 struct igb_adapter *adapter = netdev_priv(netdev);
5566 struct e1000_hw *hw = &adapter->hw;
5567 u32 err;
5568
5569 pci_set_power_state(pdev, PCI_D0);
5570 pci_restore_state(pdev);
42bfd33a 5571
aed5dec3 5572 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5573 if (err) {
5574 dev_err(&pdev->dev,
5575 "igb: Cannot enable PCI device from suspend\n");
5576 return err;
5577 }
5578 pci_set_master(pdev);
5579
5580 pci_enable_wake(pdev, PCI_D3hot, 0);
5581 pci_enable_wake(pdev, PCI_D3cold, 0);
5582
047e0030 5583 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5584 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5585 return -ENOMEM;
9d5c8243
AK		 5586 }
5587
5588 /* e1000_power_up_phy(adapter); */
5589
5590 igb_reset(adapter);
a8564f03
AD		 5591
5592 /* let the f/w know that the h/w is now under the control of the
5593 * driver. */
5594 igb_get_hw_control(adapter);
5595
9d5c8243
AK		 5596 wr32(E1000_WUS, ~0);
5597
a88f10ec
AD		 5598 if (netif_running(netdev)) {
5599 err = igb_open(netdev);
5600 if (err)
5601 return err;
5602 }
9d5c8243
AK		 5603
5604 netif_device_attach(netdev);
5605
9d5c8243
AK		 5606 return 0;
5607}
5608#endif
5609
5610static void igb_shutdown(struct pci_dev *pdev)
5611{
3fe7c4c9
RW		 5612 bool wake;
5613
5614 __igb_shutdown(pdev, &wake);
5615
5616 if (system_state == SYSTEM_POWER_OFF) {
5617 pci_wake_from_d3(pdev, wake);
5618 pci_set_power_state(pdev, PCI_D3hot);
5619 }
9d5c8243
AK		 5620}
5621
5622#ifdef CONFIG_NET_POLL_CONTROLLER
5623/*
5624 * Polling 'interrupt' - used by things like netconsole to send skbs
5625 * without having to re-enable interrupts. It's not called while
5626 * the interrupt routine is executing.
5627 */
5628static void igb_netpoll(struct net_device *netdev)
5629{
5630 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5631 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5632 int i;
9d5c8243 5633
eebbbdba 5634 if (!adapter->msix_entries) {
047e0030 5635 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5636 igb_irq_disable(adapter);
047e0030 5637 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5638 return;
5639 }
9d5c8243 5640
047e0030
AD		 5641 for (i = 0; i < adapter->num_q_vectors; i++) {
5642 struct igb_q_vector *q_vector = adapter->q_vector[i];
5643 wr32(E1000_EIMC, q_vector->eims_value);
5644 napi_schedule(&q_vector->napi);
eebbbdba 5645 }
9d5c8243
AK		 5646}
5647#endif /* CONFIG_NET_POLL_CONTROLLER */
5648
5649/**
5650 * igb_io_error_detected - called when PCI error is detected
5651 * @pdev: Pointer to PCI device
5652 * @state: The current pci connection state
5653 *
5654 * This function is called after a PCI bus error affecting
5655 * this device has been detected.
5656 */
5657static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5658 pci_channel_state_t state)
5659{
5660 struct net_device *netdev = pci_get_drvdata(pdev);
5661 struct igb_adapter *adapter = netdev_priv(netdev);
5662
5663 netif_device_detach(netdev);
5664
59ed6eec
AD		 5665 if (state == pci_channel_io_perm_failure)
5666 return PCI_ERS_RESULT_DISCONNECT;
5667
9d5c8243
AK		 5668 if (netif_running(netdev))
5669 igb_down(adapter);
5670 pci_disable_device(pdev);
5671
5672 /* Request a slot slot reset. */
5673 return PCI_ERS_RESULT_NEED_RESET;
5674}
5675
5676/**
5677 * igb_io_slot_reset - called after the pci bus has been reset.
5678 * @pdev: Pointer to PCI device
5679 *
5680 * Restart the card from scratch, as if from a cold-boot. Implementation
5681 * resembles the first-half of the igb_resume routine.
5682 */
5683static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5684{
5685 struct net_device *netdev = pci_get_drvdata(pdev);
5686 struct igb_adapter *adapter = netdev_priv(netdev);
5687 struct e1000_hw *hw = &adapter->hw;
40a914fa 5688 pci_ers_result_t result;
42bfd33a 5689 int err;
9d5c8243 5690
aed5dec3 5691 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5692 dev_err(&pdev->dev,
5693 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5694 result = PCI_ERS_RESULT_DISCONNECT;
5695 } else {
5696 pci_set_master(pdev);
5697 pci_restore_state(pdev);
9d5c8243 5698
40a914fa
AD		 5699 pci_enable_wake(pdev, PCI_D3hot, 0);
5700 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5701
40a914fa
AD		 5702 igb_reset(adapter);
5703 wr32(E1000_WUS, ~0);
5704 result = PCI_ERS_RESULT_RECOVERED;
5705 }
9d5c8243 5706
ea943d41
JK		 5707 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5708 if (err) {
5709 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5710 "failed 0x%0x\n", err);
5711 /* non-fatal, continue */
5712 }
40a914fa
AD		 5713
5714 return result;
9d5c8243
AK		 5715}
5716
5717/**
5718 * igb_io_resume - called when traffic can start flowing again.
5719 * @pdev: Pointer to PCI device
5720 *
5721 * This callback is called when the error recovery driver tells us that
5722 * its OK to resume normal operation. Implementation resembles the
5723 * second-half of the igb_resume routine.
5724 */
5725static void igb_io_resume(struct pci_dev *pdev)
5726{
5727 struct net_device *netdev = pci_get_drvdata(pdev);
5728 struct igb_adapter *adapter = netdev_priv(netdev);
5729
9d5c8243
AK		 5730 if (netif_running(netdev)) {
5731 if (igb_up(adapter)) {
5732 dev_err(&pdev->dev, "igb_up failed after reset\n");
5733 return;
5734 }
5735 }
5736
5737 netif_device_attach(netdev);
5738
5739 /* let the f/w know that the h/w is now under the control of the
5740 * driver. */
5741 igb_get_hw_control(adapter);
9d5c8243
AK		 5742}
5743
26ad9178
AD		 5744static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5745 u8 qsel)
5746{
5747 u32 rar_low, rar_high;
5748 struct e1000_hw *hw = &adapter->hw;
5749
5750 /* HW expects these in little endian so we reverse the byte order
5751 * from network order (big endian) to little endian
5752 */
5753 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5754 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5755 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5756
5757 /* Indicate to hardware the Address is Valid. */
5758 rar_high |= E1000_RAH_AV;
5759
5760 if (hw->mac.type == e1000_82575)
5761 rar_high |= E1000_RAH_POOL_1 * qsel;
5762 else
5763 rar_high |= E1000_RAH_POOL_1 << qsel;
5764
5765 wr32(E1000_RAL(index), rar_low);
5766 wrfl();
5767 wr32(E1000_RAH(index), rar_high);
5768 wrfl();
5769}
5770
4ae196df
AD		 5771static int igb_set_vf_mac(struct igb_adapter *adapter,
5772 int vf, unsigned char *mac_addr)
5773{
5774 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5775 /* VF MAC addresses start at end of receive addresses and moves
5776 * torwards the first, as a result a collision should not be possible */
5777 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5778
37680117 5779 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5780
26ad9178 5781 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5782
5783 return 0;
5784}
5785
5786static void igb_vmm_control(struct igb_adapter *adapter)
5787{
5788 struct e1000_hw *hw = &adapter->hw;
5789 u32 reg_data;
5790
5791 if (!adapter->vfs_allocated_count)
5792 return;
5793
5794 /* VF's need PF reset indication before they
5795 * can send/receive mail */
5796 reg_data = rd32(E1000_CTRL_EXT);
5797 reg_data |= E1000_CTRL_EXT_PFRSTD;
5798 wr32(E1000_CTRL_EXT, reg_data);
5799
5800 igb_vmdq_set_loopback_pf(hw, true);
5801 igb_vmdq_set_replication_pf(hw, true);
5802}
5803
9d5c8243 5804/* igb_main.c */
Clone of davem's net-next-2.6 tree