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CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
55cac248 52#define DRV_VERSION "2.1.0-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
a3aa1884 63static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
d2ba2ed8
AD		 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
2d064c06 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
84 /* required last entry */
85 {0, }
86};
87
88MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
89
90void igb_reset(struct igb_adapter *);
91static int igb_setup_all_tx_resources(struct igb_adapter *);
92static int igb_setup_all_rx_resources(struct igb_adapter *);
93static void igb_free_all_tx_resources(struct igb_adapter *);
94static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 95static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 96void igb_update_stats(struct igb_adapter *);
97static int igb_probe(struct pci_dev *, const struct pci_device_id *);
98static void __devexit igb_remove(struct pci_dev *pdev);
99static int igb_sw_init(struct igb_adapter *);
100static int igb_open(struct net_device *);
101static int igb_close(struct net_device *);
102static void igb_configure_tx(struct igb_adapter *);
103static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 104static void igb_clean_all_tx_rings(struct igb_adapter *);
105static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 106static void igb_clean_tx_ring(struct igb_ring *);
107static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 108static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 109static void igb_update_phy_info(unsigned long);
110static void igb_watchdog(unsigned long);
111static void igb_watchdog_task(struct work_struct *);
b1a436c3 112static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
9d5c8243
AK		 113static struct net_device_stats *igb_get_stats(struct net_device *);
114static int igb_change_mtu(struct net_device *, int);
115static int igb_set_mac(struct net_device *, void *);
68d480c4 116static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 117static irqreturn_t igb_intr(int irq, void *);
118static irqreturn_t igb_intr_msi(int irq, void *);
119static irqreturn_t igb_msix_other(int irq, void *);
047e0030 120static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 121#ifdef CONFIG_IGB_DCA
047e0030 122static void igb_update_dca(struct igb_q_vector *);
fe4506b6 123static void igb_setup_dca(struct igb_adapter *);
421e02f0 124#endif /* CONFIG_IGB_DCA */
047e0030 125static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 126static int igb_poll(struct napi_struct *, int);
047e0030 127static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 128static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
129static void igb_tx_timeout(struct net_device *);
130static void igb_reset_task(struct work_struct *);
131static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
132static void igb_vlan_rx_add_vid(struct net_device *, u16);
133static void igb_vlan_rx_kill_vid(struct net_device *, u16);
134static void igb_restore_vlan(struct igb_adapter *);
26ad9178 135static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 136static void igb_ping_all_vfs(struct igb_adapter *);
137static void igb_msg_task(struct igb_adapter *);
4ae196df 138static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 139static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 140static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 141static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
142static int igb_ndo_set_vf_vlan(struct net_device *netdev,
143 int vf, u16 vlan, u8 qos);
144static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
145static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
146 struct ifla_vf_info *ivi);
9d5c8243 147
9d5c8243 148#ifdef CONFIG_PM
3fe7c4c9 149static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 150static int igb_resume(struct pci_dev *);
151#endif
152static void igb_shutdown(struct pci_dev *);
421e02f0 153#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 154static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
155static struct notifier_block dca_notifier = {
156 .notifier_call = igb_notify_dca,
157 .next = NULL,
158 .priority = 0
159};
160#endif
9d5c8243
AK		 161#ifdef CONFIG_NET_POLL_CONTROLLER
162/* for netdump / net console */
163static void igb_netpoll(struct net_device *);
164#endif
37680117 165#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 166static unsigned int max_vfs = 0;
167module_param(max_vfs, uint, 0);
168MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
169 "per physical function");
170#endif /* CONFIG_PCI_IOV */
171
9d5c8243
AK		 172static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
173 pci_channel_state_t);
174static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
175static void igb_io_resume(struct pci_dev *);
176
177static struct pci_error_handlers igb_err_handler = {
178 .error_detected = igb_io_error_detected,
179 .slot_reset = igb_io_slot_reset,
180 .resume = igb_io_resume,
181};
182
183
184static struct pci_driver igb_driver = {
185 .name = igb_driver_name,
186 .id_table = igb_pci_tbl,
187 .probe = igb_probe,
188 .remove = __devexit_p(igb_remove),
189#ifdef CONFIG_PM
190 /* Power Managment Hooks */
191 .suspend = igb_suspend,
192 .resume = igb_resume,
193#endif
194 .shutdown = igb_shutdown,
195 .err_handler = &igb_err_handler
196};
197
198MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
199MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
200MODULE_LICENSE("GPL");
201MODULE_VERSION(DRV_VERSION);
202
38c845c7
PO		 203/**
204 * igb_read_clock - read raw cycle counter (to be used by time counter)
205 */
206static cycle_t igb_read_clock(const struct cyclecounter *tc)
207{
208 struct igb_adapter *adapter =
209 container_of(tc, struct igb_adapter, cycles);
210 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 211 u64 stamp = 0;
212 int shift = 0;
38c845c7 213
55cac248
AD		 214 /*
215 * The timestamp latches on lowest register read. For the 82580
216 * the lowest register is SYSTIMR instead of SYSTIML. However we never
217 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
218 */
219 if (hw->mac.type == e1000_82580) {
220 stamp = rd32(E1000_SYSTIMR) >> 8;
221 shift = IGB_82580_TSYNC_SHIFT;
222 }
223
c5b9bd5e
AD		 224 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
225 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 226 return stamp;
227}
228
9d5c8243 229/**
c041076a 230 * igb_get_hw_dev - return device
9d5c8243
AK		 231 * used by hardware layer to print debugging information
232 **/
c041076a 233struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 234{
235 struct igb_adapter *adapter = hw->back;
c041076a 236 return adapter->netdev;
9d5c8243 237}
38c845c7 238
9d5c8243
AK		 239/**
240 * igb_init_module - Driver Registration Routine
241 *
242 * igb_init_module is the first routine called when the driver is
243 * loaded. All it does is register with the PCI subsystem.
244 **/
245static int __init igb_init_module(void)
246{
247 int ret;
248 printk(KERN_INFO "%s - version %s\n",
249 igb_driver_string, igb_driver_version);
250
251 printk(KERN_INFO "%s\n", igb_copyright);
252
421e02f0 253#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 254 dca_register_notify(&dca_notifier);
255#endif
bbd98fe4 256 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 257 return ret;
258}
259
260module_init(igb_init_module);
261
262/**
263 * igb_exit_module - Driver Exit Cleanup Routine
264 *
265 * igb_exit_module is called just before the driver is removed
266 * from memory.
267 **/
268static void __exit igb_exit_module(void)
269{
421e02f0 270#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 271 dca_unregister_notify(&dca_notifier);
272#endif
9d5c8243
AK		 273 pci_unregister_driver(&igb_driver);
274}
275
276module_exit(igb_exit_module);
277
26bc19ec
AD		 278#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
279/**
280 * igb_cache_ring_register - Descriptor ring to register mapping
281 * @adapter: board private structure to initialize
282 *
283 * Once we know the feature-set enabled for the device, we'll cache
284 * the register offset the descriptor ring is assigned to.
285 **/
286static void igb_cache_ring_register(struct igb_adapter *adapter)
287{
ee1b9f06 288 int i = 0, j = 0;
047e0030 289 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 290
291 switch (adapter->hw.mac.type) {
292 case e1000_82576:
293 /* The queues are allocated for virtualization such that VF 0
294 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
295 * In order to avoid collision we start at the first free queue
296 * and continue consuming queues in the same sequence
297 */
ee1b9f06 298 if (adapter->vfs_allocated_count) {
a99955fc 299 for (; i < adapter->rss_queues; i++)
3025a446
AD		 300 adapter->rx_ring[i]->reg_idx = rbase_offset +
301 Q_IDX_82576(i);
a99955fc 302 for (; j < adapter->rss_queues; j++)
3025a446
AD		 303 adapter->tx_ring[j]->reg_idx = rbase_offset +
304 Q_IDX_82576(j);
ee1b9f06 305 }
26bc19ec 306 case e1000_82575:
55cac248 307 case e1000_82580:
d2ba2ed8 308 case e1000_i350:
26bc19ec 309 default:
ee1b9f06 310 for (; i < adapter->num_rx_queues; i++)
3025a446 311 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 312 for (; j < adapter->num_tx_queues; j++)
3025a446 313 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 314 break;
315 }
316}
317
047e0030
AD		 318static void igb_free_queues(struct igb_adapter *adapter)
319{
3025a446 320 int i;
047e0030 321
3025a446
AD		 322 for (i = 0; i < adapter->num_tx_queues; i++) {
323 kfree(adapter->tx_ring[i]);
324 adapter->tx_ring[i] = NULL;
325 }
326 for (i = 0; i < adapter->num_rx_queues; i++) {
327 kfree(adapter->rx_ring[i]);
328 adapter->rx_ring[i] = NULL;
329 }
047e0030
AD		 330 adapter->num_rx_queues = 0;
331 adapter->num_tx_queues = 0;
332}
333
9d5c8243
AK		 334/**
335 * igb_alloc_queues - Allocate memory for all rings
336 * @adapter: board private structure to initialize
337 *
338 * We allocate one ring per queue at run-time since we don't know the
339 * number of queues at compile-time.
340 **/
341static int igb_alloc_queues(struct igb_adapter *adapter)
342{
3025a446 343 struct igb_ring *ring;
9d5c8243
AK		 344 int i;
345
661086df 346 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 347 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
348 if (!ring)
349 goto err;
68fd9910 350 ring->count = adapter->tx_ring_count;
661086df 351 ring->queue_index = i;
80785298 352 ring->pdev = adapter->pdev;
e694e964 353 ring->netdev = adapter->netdev;
85ad76b2
AD		 354 /* For 82575, context index must be unique per ring. */
355 if (adapter->hw.mac.type == e1000_82575)
356 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
3025a446 357 adapter->tx_ring[i] = ring;
661086df 358 }
85ad76b2 359
9d5c8243 360 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 361 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
362 if (!ring)
363 goto err;
68fd9910 364 ring->count = adapter->rx_ring_count;
844290e5 365 ring->queue_index = i;
80785298 366 ring->pdev = adapter->pdev;
e694e964 367 ring->netdev = adapter->netdev;
4c844851 368 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 369 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
370 /* set flag indicating ring supports SCTP checksum offload */
371 if (adapter->hw.mac.type >= e1000_82576)
372 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
3025a446 373 adapter->rx_ring[i] = ring;
9d5c8243 374 }
26bc19ec
AD		 375
376 igb_cache_ring_register(adapter);
9d5c8243 377
047e0030 378 return 0;
a88f10ec 379
047e0030
AD		 380err:
381 igb_free_queues(adapter);
d1a8c9e1 382
047e0030 383 return -ENOMEM;
a88f10ec
AD		 384}
385
9d5c8243 386#define IGB_N0_QUEUE -1
047e0030 387static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 388{
389 u32 msixbm = 0;
047e0030 390 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 391 struct e1000_hw *hw = &adapter->hw;
2d064c06 392 u32 ivar, index;
047e0030
AD		 393 int rx_queue = IGB_N0_QUEUE;
394 int tx_queue = IGB_N0_QUEUE;
395
396 if (q_vector->rx_ring)
397 rx_queue = q_vector->rx_ring->reg_idx;
398 if (q_vector->tx_ring)
399 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 400
401 switch (hw->mac.type) {
402 case e1000_82575:
9d5c8243
AK		 403 /* The 82575 assigns vectors using a bitmask, which matches the
404 bitmask for the EICR/EIMS/EIMC registers. To assign one
405 or more queues to a vector, we write the appropriate bits
406 into the MSIXBM register for that vector. */
047e0030 407 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 408 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 409 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 410 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 411 if (!adapter->msix_entries && msix_vector == 0)
412 msixbm |= E1000_EIMS_OTHER;
9d5c8243 413 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 414 q_vector->eims_value = msixbm;
2d064c06
AD		 415 break;
416 case e1000_82576:
26bc19ec 417 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 418 Each queue has a single entry in the table to which we write
419 a vector number along with a "valid" bit. Sadly, the layout
420 of the table is somewhat counterintuitive. */
421 if (rx_queue > IGB_N0_QUEUE) {
047e0030 422 index = (rx_queue & 0x7);
2d064c06 423 ivar = array_rd32(E1000_IVAR0, index);
047e0030 424 if (rx_queue < 8) {
26bc19ec
AD		 425 /* vector goes into low byte of register */
426 ivar = ivar & 0xFFFFFF00;
427 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 428 } else {
429 /* vector goes into third byte of register */
430 ivar = ivar & 0xFF00FFFF;
431 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 432 }
2d064c06
AD		 433 array_wr32(E1000_IVAR0, index, ivar);
434 }
435 if (tx_queue > IGB_N0_QUEUE) {
047e0030 436 index = (tx_queue & 0x7);
2d064c06 437 ivar = array_rd32(E1000_IVAR0, index);
047e0030 438 if (tx_queue < 8) {
26bc19ec
AD		 439 /* vector goes into second byte of register */
440 ivar = ivar & 0xFFFF00FF;
441 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 442 } else {
443 /* vector goes into high byte of register */
444 ivar = ivar & 0x00FFFFFF;
445 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 446 }
2d064c06
AD		 447 array_wr32(E1000_IVAR0, index, ivar);
448 }
047e0030 449 q_vector->eims_value = 1 << msix_vector;
2d064c06 450 break;
55cac248 451 case e1000_82580:
d2ba2ed8 452 case e1000_i350:
55cac248
AD		 453 /* 82580 uses the same table-based approach as 82576 but has fewer
454 entries as a result we carry over for queues greater than 4. */
455 if (rx_queue > IGB_N0_QUEUE) {
456 index = (rx_queue >> 1);
457 ivar = array_rd32(E1000_IVAR0, index);
458 if (rx_queue & 0x1) {
459 /* vector goes into third byte of register */
460 ivar = ivar & 0xFF00FFFF;
461 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
462 } else {
463 /* vector goes into low byte of register */
464 ivar = ivar & 0xFFFFFF00;
465 ivar |= msix_vector | E1000_IVAR_VALID;
466 }
467 array_wr32(E1000_IVAR0, index, ivar);
468 }
469 if (tx_queue > IGB_N0_QUEUE) {
470 index = (tx_queue >> 1);
471 ivar = array_rd32(E1000_IVAR0, index);
472 if (tx_queue & 0x1) {
473 /* vector goes into high byte of register */
474 ivar = ivar & 0x00FFFFFF;
475 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
476 } else {
477 /* vector goes into second byte of register */
478 ivar = ivar & 0xFFFF00FF;
479 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
480 }
481 array_wr32(E1000_IVAR0, index, ivar);
482 }
483 q_vector->eims_value = 1 << msix_vector;
484 break;
2d064c06
AD		 485 default:
486 BUG();
487 break;
488 }
26b39276
AD		 489
490 /* add q_vector eims value to global eims_enable_mask */
491 adapter->eims_enable_mask |= q_vector->eims_value;
492
493 /* configure q_vector to set itr on first interrupt */
494 q_vector->set_itr = 1;
9d5c8243
AK		 495}
496
497/**
498 * igb_configure_msix - Configure MSI-X hardware
499 *
500 * igb_configure_msix sets up the hardware to properly
501 * generate MSI-X interrupts.
502 **/
503static void igb_configure_msix(struct igb_adapter *adapter)
504{
505 u32 tmp;
506 int i, vector = 0;
507 struct e1000_hw *hw = &adapter->hw;
508
509 adapter->eims_enable_mask = 0;
9d5c8243
AK		 510
511 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 512 switch (hw->mac.type) {
513 case e1000_82575:
9d5c8243
AK		 514 tmp = rd32(E1000_CTRL_EXT);
515 /* enable MSI-X PBA support*/
516 tmp |= E1000_CTRL_EXT_PBA_CLR;
517
518 /* Auto-Mask interrupts upon ICR read. */
519 tmp |= E1000_CTRL_EXT_EIAME;
520 tmp |= E1000_CTRL_EXT_IRCA;
521
522 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 523
524 /* enable msix_other interrupt */
525 array_wr32(E1000_MSIXBM(0), vector++,
526 E1000_EIMS_OTHER);
844290e5 527 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 528
2d064c06
AD		 529 break;
530
531 case e1000_82576:
55cac248 532 case e1000_82580:
d2ba2ed8 533 case e1000_i350:
047e0030
AD		 534 /* Turn on MSI-X capability first, or our settings
535 * won't stick. And it will take days to debug. */
536 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
537 E1000_GPIE_PBA | E1000_GPIE_EIAME |
538 E1000_GPIE_NSICR);
539
540 /* enable msix_other interrupt */
541 adapter->eims_other = 1 << vector;
2d064c06 542 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 543
047e0030 544 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 545 break;
546 default:
547 /* do nothing, since nothing else supports MSI-X */
548 break;
549 } /* switch (hw->mac.type) */
047e0030
AD		 550
551 adapter->eims_enable_mask |= adapter->eims_other;
552
26b39276
AD		 553 for (i = 0; i < adapter->num_q_vectors; i++)
554 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 555
9d5c8243
AK		 556 wrfl();
557}
558
559/**
560 * igb_request_msix - Initialize MSI-X interrupts
561 *
562 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
563 * kernel.
564 **/
565static int igb_request_msix(struct igb_adapter *adapter)
566{
567 struct net_device *netdev = adapter->netdev;
047e0030 568 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 569 int i, err = 0, vector = 0;
570
047e0030 571 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 572 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 573 if (err)
574 goto out;
575 vector++;
576
577 for (i = 0; i < adapter->num_q_vectors; i++) {
578 struct igb_q_vector *q_vector = adapter->q_vector[i];
579
580 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
581
582 if (q_vector->rx_ring && q_vector->tx_ring)
583 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
584 q_vector->rx_ring->queue_index);
585 else if (q_vector->tx_ring)
586 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
587 q_vector->tx_ring->queue_index);
588 else if (q_vector->rx_ring)
589 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
590 q_vector->rx_ring->queue_index);
9d5c8243 591 else
047e0030
AD		 592 sprintf(q_vector->name, "%s-unused", netdev->name);
593
9d5c8243 594 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 595 igb_msix_ring, 0, q_vector->name,
047e0030 596 q_vector);
9d5c8243
AK		 597 if (err)
598 goto out;
9d5c8243
AK		 599 vector++;
600 }
601
9d5c8243
AK		 602 igb_configure_msix(adapter);
603 return 0;
604out:
605 return err;
606}
607
608static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
609{
610 if (adapter->msix_entries) {
611 pci_disable_msix(adapter->pdev);
612 kfree(adapter->msix_entries);
613 adapter->msix_entries = NULL;
047e0030 614 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 615 pci_disable_msi(adapter->pdev);
047e0030 616 }
9d5c8243
AK		 617}
618
047e0030
AD		 619/**
620 * igb_free_q_vectors - Free memory allocated for interrupt vectors
621 * @adapter: board private structure to initialize
622 *
623 * This function frees the memory allocated to the q_vectors. In addition if
624 * NAPI is enabled it will delete any references to the NAPI struct prior
625 * to freeing the q_vector.
626 **/
627static void igb_free_q_vectors(struct igb_adapter *adapter)
628{
629 int v_idx;
630
631 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
632 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
633 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 634 if (!q_vector)
635 continue;
047e0030
AD		 636 netif_napi_del(&q_vector->napi);
637 kfree(q_vector);
638 }
639 adapter->num_q_vectors = 0;
640}
641
642/**
643 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
644 *
645 * This function resets the device so that it has 0 rx queues, tx queues, and
646 * MSI-X interrupts allocated.
647 */
648static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
649{
650 igb_free_queues(adapter);
651 igb_free_q_vectors(adapter);
652 igb_reset_interrupt_capability(adapter);
653}
9d5c8243
AK		 654
655/**
656 * igb_set_interrupt_capability - set MSI or MSI-X if supported
657 *
658 * Attempt to configure interrupts using the best available
659 * capabilities of the hardware and kernel.
660 **/
661static void igb_set_interrupt_capability(struct igb_adapter *adapter)
662{
663 int err;
664 int numvecs, i;
665
83b7180d 666 /* Number of supported queues. */
a99955fc
AD		 667 adapter->num_rx_queues = adapter->rss_queues;
668 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 669
047e0030
AD		 670 /* start with one vector for every rx queue */
671 numvecs = adapter->num_rx_queues;
672
3ad2f3fb 673 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 674 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
675 numvecs += adapter->num_tx_queues;
047e0030
AD		 676
677 /* store the number of vectors reserved for queues */
678 adapter->num_q_vectors = numvecs;
679
680 /* add 1 vector for link status interrupts */
681 numvecs++;
9d5c8243
AK		 682 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
683 GFP_KERNEL);
684 if (!adapter->msix_entries)
685 goto msi_only;
686
687 for (i = 0; i < numvecs; i++)
688 adapter->msix_entries[i].entry = i;
689
690 err = pci_enable_msix(adapter->pdev,
691 adapter->msix_entries,
692 numvecs);
693 if (err == 0)
34a20e89 694 goto out;
9d5c8243
AK		 695
696 igb_reset_interrupt_capability(adapter);
697
698 /* If we can't do MSI-X, try MSI */
699msi_only:
2a3abf6d
AD		 700#ifdef CONFIG_PCI_IOV
701 /* disable SR-IOV for non MSI-X configurations */
702 if (adapter->vf_data) {
703 struct e1000_hw *hw = &adapter->hw;
704 /* disable iov and allow time for transactions to clear */
705 pci_disable_sriov(adapter->pdev);
706 msleep(500);
707
708 kfree(adapter->vf_data);
709 adapter->vf_data = NULL;
710 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
711 msleep(100);
712 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
713 }
714#endif
4fc82adf 715 adapter->vfs_allocated_count = 0;
a99955fc 716 adapter->rss_queues = 1;
4fc82adf 717 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 718 adapter->num_rx_queues = 1;
661086df 719 adapter->num_tx_queues = 1;
047e0030 720 adapter->num_q_vectors = 1;
9d5c8243 721 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 722 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 723out:
661086df 724 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 725 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 726 return;
727}
728
047e0030
AD		 729/**
730 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
731 * @adapter: board private structure to initialize
732 *
733 * We allocate one q_vector per queue interrupt. If allocation fails we
734 * return -ENOMEM.
735 **/
736static int igb_alloc_q_vectors(struct igb_adapter *adapter)
737{
738 struct igb_q_vector *q_vector;
739 struct e1000_hw *hw = &adapter->hw;
740 int v_idx;
741
742 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
743 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
744 if (!q_vector)
745 goto err_out;
746 q_vector->adapter = adapter;
047e0030
AD		 747 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
748 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 749 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
750 adapter->q_vector[v_idx] = q_vector;
751 }
752 return 0;
753
754err_out:
fe0592b4 755 igb_free_q_vectors(adapter);
047e0030
AD		 756 return -ENOMEM;
757}
758
759static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
760 int ring_idx, int v_idx)
761{
3025a446 762 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 763
3025a446 764 q_vector->rx_ring = adapter->rx_ring[ring_idx];
047e0030 765 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 766 q_vector->itr_val = adapter->rx_itr_setting;
767 if (q_vector->itr_val && q_vector->itr_val <= 3)
768 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 769}
770
771static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
772 int ring_idx, int v_idx)
773{
3025a446 774 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 775
3025a446 776 q_vector->tx_ring = adapter->tx_ring[ring_idx];
047e0030 777 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 778 q_vector->itr_val = adapter->tx_itr_setting;
779 if (q_vector->itr_val && q_vector->itr_val <= 3)
780 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 781}
782
783/**
784 * igb_map_ring_to_vector - maps allocated queues to vectors
785 *
786 * This function maps the recently allocated queues to vectors.
787 **/
788static int igb_map_ring_to_vector(struct igb_adapter *adapter)
789{
790 int i;
791 int v_idx = 0;
792
793 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
794 (adapter->num_q_vectors < adapter->num_tx_queues))
795 return -ENOMEM;
796
797 if (adapter->num_q_vectors >=
798 (adapter->num_rx_queues + adapter->num_tx_queues)) {
799 for (i = 0; i < adapter->num_rx_queues; i++)
800 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
801 for (i = 0; i < adapter->num_tx_queues; i++)
802 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
803 } else {
804 for (i = 0; i < adapter->num_rx_queues; i++) {
805 if (i < adapter->num_tx_queues)
806 igb_map_tx_ring_to_vector(adapter, i, v_idx);
807 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
808 }
809 for (; i < adapter->num_tx_queues; i++)
810 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
811 }
812 return 0;
813}
814
815/**
816 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
817 *
818 * This function initializes the interrupts and allocates all of the queues.
819 **/
820static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
821{
822 struct pci_dev *pdev = adapter->pdev;
823 int err;
824
825 igb_set_interrupt_capability(adapter);
826
827 err = igb_alloc_q_vectors(adapter);
828 if (err) {
829 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
830 goto err_alloc_q_vectors;
831 }
832
833 err = igb_alloc_queues(adapter);
834 if (err) {
835 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
836 goto err_alloc_queues;
837 }
838
839 err = igb_map_ring_to_vector(adapter);
840 if (err) {
841 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
842 goto err_map_queues;
843 }
844
845
846 return 0;
847err_map_queues:
848 igb_free_queues(adapter);
849err_alloc_queues:
850 igb_free_q_vectors(adapter);
851err_alloc_q_vectors:
852 igb_reset_interrupt_capability(adapter);
853 return err;
854}
855
9d5c8243
AK		 856/**
857 * igb_request_irq - initialize interrupts
858 *
859 * Attempts to configure interrupts using the best available
860 * capabilities of the hardware and kernel.
861 **/
862static int igb_request_irq(struct igb_adapter *adapter)
863{
864 struct net_device *netdev = adapter->netdev;
047e0030 865 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 866 int err = 0;
867
868 if (adapter->msix_entries) {
869 err = igb_request_msix(adapter);
844290e5 870 if (!err)
9d5c8243 871 goto request_done;
9d5c8243 872 /* fall back to MSI */
047e0030 873 igb_clear_interrupt_scheme(adapter);
9d5c8243 874 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 875 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 876 igb_free_all_tx_resources(adapter);
877 igb_free_all_rx_resources(adapter);
047e0030 878 adapter->num_tx_queues = 1;
9d5c8243 879 adapter->num_rx_queues = 1;
047e0030
AD		 880 adapter->num_q_vectors = 1;
881 err = igb_alloc_q_vectors(adapter);
882 if (err) {
883 dev_err(&pdev->dev,
884 "Unable to allocate memory for vectors\n");
885 goto request_done;
886 }
887 err = igb_alloc_queues(adapter);
888 if (err) {
889 dev_err(&pdev->dev,
890 "Unable to allocate memory for queues\n");
891 igb_free_q_vectors(adapter);
892 goto request_done;
893 }
894 igb_setup_all_tx_resources(adapter);
895 igb_setup_all_rx_resources(adapter);
844290e5 896 } else {
feeb2721 897 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 898 }
844290e5 899
7dfc16fa 900 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 901 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 902 netdev->name, adapter);
9d5c8243
AK		 903 if (!err)
904 goto request_done;
047e0030 905
9d5c8243
AK		 906 /* fall back to legacy interrupts */
907 igb_reset_interrupt_capability(adapter);
7dfc16fa 908 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 909 }
910
a0607fd3 911 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 912 netdev->name, adapter);
9d5c8243 913
6cb5e577 914 if (err)
9d5c8243
AK		 915 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
916 err);
9d5c8243
AK		 917
918request_done:
919 return err;
920}
921
922static void igb_free_irq(struct igb_adapter *adapter)
923{
9d5c8243
AK		 924 if (adapter->msix_entries) {
925 int vector = 0, i;
926
047e0030 927 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 928
047e0030
AD		 929 for (i = 0; i < adapter->num_q_vectors; i++) {
930 struct igb_q_vector *q_vector = adapter->q_vector[i];
931 free_irq(adapter->msix_entries[vector++].vector,
932 q_vector);
933 }
934 } else {
935 free_irq(adapter->pdev->irq, adapter);
9d5c8243 936 }
9d5c8243
AK		 937}
938
939/**
940 * igb_irq_disable - Mask off interrupt generation on the NIC
941 * @adapter: board private structure
942 **/
943static void igb_irq_disable(struct igb_adapter *adapter)
944{
945 struct e1000_hw *hw = &adapter->hw;
946
25568a53
AD		 947 /*
948 * we need to be careful when disabling interrupts. The VFs are also
949 * mapped into these registers and so clearing the bits can cause
950 * issues on the VF drivers so we only need to clear what we set
951 */
9d5c8243 952 if (adapter->msix_entries) {
2dfd1212
AD		 953 u32 regval = rd32(E1000_EIAM);
954 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
955 wr32(E1000_EIMC, adapter->eims_enable_mask);
956 regval = rd32(E1000_EIAC);
957 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 958 }
844290e5
PW		 959
960 wr32(E1000_IAM, 0);
9d5c8243
AK		 961 wr32(E1000_IMC, ~0);
962 wrfl();
963 synchronize_irq(adapter->pdev->irq);
964}
965
966/**
967 * igb_irq_enable - Enable default interrupt generation settings
968 * @adapter: board private structure
969 **/
970static void igb_irq_enable(struct igb_adapter *adapter)
971{
972 struct e1000_hw *hw = &adapter->hw;
973
974 if (adapter->msix_entries) {
25568a53 975 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 976 u32 regval = rd32(E1000_EIAC);
977 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
978 regval = rd32(E1000_EIAM);
979 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 980 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 981 if (adapter->vfs_allocated_count) {
4ae196df 982 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 983 ims |= E1000_IMS_VMMB;
984 }
55cac248
AD		 985 if (adapter->hw.mac.type == e1000_82580)
986 ims |= E1000_IMS_DRSTA;
987
25568a53 988 wr32(E1000_IMS, ims);
844290e5 989 } else {
55cac248
AD		 990 wr32(E1000_IMS, IMS_ENABLE_MASK |
991 E1000_IMS_DRSTA);
992 wr32(E1000_IAM, IMS_ENABLE_MASK |
993 E1000_IMS_DRSTA);
844290e5 994 }
9d5c8243
AK		 995}
996
997static void igb_update_mng_vlan(struct igb_adapter *adapter)
998{
51466239 999 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1000 u16 vid = adapter->hw.mng_cookie.vlan_id;
1001 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1002
1003 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1004 /* add VID to filter table */
1005 igb_vfta_set(hw, vid, true);
1006 adapter->mng_vlan_id = vid;
1007 } else {
1008 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1009 }
1010
1011 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1012 (vid != old_vid) &&
1013 !vlan_group_get_device(adapter->vlgrp, old_vid)) {
1014 /* remove VID from filter table */
1015 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1016 }
1017}
1018
1019/**
1020 * igb_release_hw_control - release control of the h/w to f/w
1021 * @adapter: address of board private structure
1022 *
1023 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1024 * For ASF and Pass Through versions of f/w this means that the
1025 * driver is no longer loaded.
1026 *
1027 **/
1028static void igb_release_hw_control(struct igb_adapter *adapter)
1029{
1030 struct e1000_hw *hw = &adapter->hw;
1031 u32 ctrl_ext;
1032
1033 /* Let firmware take over control of h/w */
1034 ctrl_ext = rd32(E1000_CTRL_EXT);
1035 wr32(E1000_CTRL_EXT,
1036 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1037}
1038
9d5c8243
AK		 1039/**
1040 * igb_get_hw_control - get control of the h/w from f/w
1041 * @adapter: address of board private structure
1042 *
1043 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1044 * For ASF and Pass Through versions of f/w this means that
1045 * the driver is loaded.
1046 *
1047 **/
1048static void igb_get_hw_control(struct igb_adapter *adapter)
1049{
1050 struct e1000_hw *hw = &adapter->hw;
1051 u32 ctrl_ext;
1052
1053 /* Let firmware know the driver has taken over */
1054 ctrl_ext = rd32(E1000_CTRL_EXT);
1055 wr32(E1000_CTRL_EXT,
1056 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1057}
1058
9d5c8243
AK		 1059/**
1060 * igb_configure - configure the hardware for RX and TX
1061 * @adapter: private board structure
1062 **/
1063static void igb_configure(struct igb_adapter *adapter)
1064{
1065 struct net_device *netdev = adapter->netdev;
1066 int i;
1067
1068 igb_get_hw_control(adapter);
ff41f8dc 1069 igb_set_rx_mode(netdev);
9d5c8243
AK		 1070
1071 igb_restore_vlan(adapter);
9d5c8243 1072
85b430b4 1073 igb_setup_tctl(adapter);
06cf2666 1074 igb_setup_mrqc(adapter);
9d5c8243 1075 igb_setup_rctl(adapter);
85b430b4
AD		 1076
1077 igb_configure_tx(adapter);
9d5c8243 1078 igb_configure_rx(adapter);
662d7205
AD		 1079
1080 igb_rx_fifo_flush_82575(&adapter->hw);
1081
c493ea45 1082 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1083 * at least 1 descriptor unused to make sure
1084 * next_to_use != next_to_clean */
1085 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1086 struct igb_ring *ring = adapter->rx_ring[i];
c493ea45 1087 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1088 }
1089
1090
1091 adapter->tx_queue_len = netdev->tx_queue_len;
1092}
1093
88a268c1
NN		 1094/**
1095 * igb_power_up_link - Power up the phy/serdes link
1096 * @adapter: address of board private structure
1097 **/
1098void igb_power_up_link(struct igb_adapter *adapter)
1099{
1100 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1101 igb_power_up_phy_copper(&adapter->hw);
1102 else
1103 igb_power_up_serdes_link_82575(&adapter->hw);
1104}
1105
1106/**
1107 * igb_power_down_link - Power down the phy/serdes link
1108 * @adapter: address of board private structure
1109 */
1110static void igb_power_down_link(struct igb_adapter *adapter)
1111{
1112 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1113 igb_power_down_phy_copper_82575(&adapter->hw);
1114 else
1115 igb_shutdown_serdes_link_82575(&adapter->hw);
1116}
9d5c8243
AK		 1117
1118/**
1119 * igb_up - Open the interface and prepare it to handle traffic
1120 * @adapter: board private structure
1121 **/
9d5c8243
AK		 1122int igb_up(struct igb_adapter *adapter)
1123{
1124 struct e1000_hw *hw = &adapter->hw;
1125 int i;
1126
1127 /* hardware has been reset, we need to reload some things */
1128 igb_configure(adapter);
1129
1130 clear_bit(__IGB_DOWN, &adapter->state);
1131
047e0030
AD		 1132 for (i = 0; i < adapter->num_q_vectors; i++) {
1133 struct igb_q_vector *q_vector = adapter->q_vector[i];
1134 napi_enable(&q_vector->napi);
1135 }
844290e5 1136 if (adapter->msix_entries)
9d5c8243 1137 igb_configure_msix(adapter);
feeb2721
AD		 1138 else
1139 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1140
1141 /* Clear any pending interrupts. */
1142 rd32(E1000_ICR);
1143 igb_irq_enable(adapter);
1144
d4960307
AD		 1145 /* notify VFs that reset has been completed */
1146 if (adapter->vfs_allocated_count) {
1147 u32 reg_data = rd32(E1000_CTRL_EXT);
1148 reg_data |= E1000_CTRL_EXT_PFRSTD;
1149 wr32(E1000_CTRL_EXT, reg_data);
1150 }
1151
4cb9be7a
JB		 1152 netif_tx_start_all_queues(adapter->netdev);
1153
25568a53
AD		 1154 /* start the watchdog. */
1155 hw->mac.get_link_status = 1;
1156 schedule_work(&adapter->watchdog_task);
1157
9d5c8243
AK		 1158 return 0;
1159}
1160
1161void igb_down(struct igb_adapter *adapter)
1162{
9d5c8243 1163 struct net_device *netdev = adapter->netdev;
330a6d6a 1164 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1165 u32 tctl, rctl;
1166 int i;
1167
1168 /* signal that we're down so the interrupt handler does not
1169 * reschedule our watchdog timer */
1170 set_bit(__IGB_DOWN, &adapter->state);
1171
1172 /* disable receives in the hardware */
1173 rctl = rd32(E1000_RCTL);
1174 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1175 /* flush and sleep below */
1176
fd2ea0a7 1177 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1178
1179 /* disable transmits in the hardware */
1180 tctl = rd32(E1000_TCTL);
1181 tctl &= ~E1000_TCTL_EN;
1182 wr32(E1000_TCTL, tctl);
1183 /* flush both disables and wait for them to finish */
1184 wrfl();
1185 msleep(10);
1186
047e0030
AD		 1187 for (i = 0; i < adapter->num_q_vectors; i++) {
1188 struct igb_q_vector *q_vector = adapter->q_vector[i];
1189 napi_disable(&q_vector->napi);
1190 }
9d5c8243 1191
9d5c8243
AK		 1192 igb_irq_disable(adapter);
1193
1194 del_timer_sync(&adapter->watchdog_timer);
1195 del_timer_sync(&adapter->phy_info_timer);
1196
1197 netdev->tx_queue_len = adapter->tx_queue_len;
1198 netif_carrier_off(netdev);
04fe6358
AD		 1199
1200 /* record the stats before reset*/
1201 igb_update_stats(adapter);
1202
9d5c8243
AK		 1203 adapter->link_speed = 0;
1204 adapter->link_duplex = 0;
1205
3023682e
JK		 1206 if (!pci_channel_offline(adapter->pdev))
1207 igb_reset(adapter);
9d5c8243
AK		 1208 igb_clean_all_tx_rings(adapter);
1209 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1210#ifdef CONFIG_IGB_DCA
1211
1212 /* since we reset the hardware DCA settings were cleared */
1213 igb_setup_dca(adapter);
1214#endif
9d5c8243
AK		 1215}
1216
1217void igb_reinit_locked(struct igb_adapter *adapter)
1218{
1219 WARN_ON(in_interrupt());
1220 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1221 msleep(1);
1222 igb_down(adapter);
1223 igb_up(adapter);
1224 clear_bit(__IGB_RESETTING, &adapter->state);
1225}
1226
1227void igb_reset(struct igb_adapter *adapter)
1228{
090b1795 1229 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1230 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1231 struct e1000_mac_info *mac = &hw->mac;
1232 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1233 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1234 u16 hwm;
1235
1236 /* Repartition Pba for greater than 9k mtu
1237 * To take effect CTRL.RST is required.
1238 */
fa4dfae0 1239 switch (mac->type) {
d2ba2ed8 1240 case e1000_i350:
55cac248
AD		 1241 case e1000_82580:
1242 pba = rd32(E1000_RXPBS);
1243 pba = igb_rxpbs_adjust_82580(pba);
1244 break;
fa4dfae0 1245 case e1000_82576:
d249be54
AD		 1246 pba = rd32(E1000_RXPBS);
1247 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1248 break;
1249 case e1000_82575:
1250 default:
1251 pba = E1000_PBA_34K;
1252 break;
2d064c06 1253 }
9d5c8243 1254
2d064c06
AD		 1255 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1256 (mac->type < e1000_82576)) {
9d5c8243
AK		 1257 /* adjust PBA for jumbo frames */
1258 wr32(E1000_PBA, pba);
1259
1260 /* To maintain wire speed transmits, the Tx FIFO should be
1261 * large enough to accommodate two full transmit packets,
1262 * rounded up to the next 1KB and expressed in KB. Likewise,
1263 * the Rx FIFO should be large enough to accommodate at least
1264 * one full receive packet and is similarly rounded up and
1265 * expressed in KB. */
1266 pba = rd32(E1000_PBA);
1267 /* upper 16 bits has Tx packet buffer allocation size in KB */
1268 tx_space = pba >> 16;
1269 /* lower 16 bits has Rx packet buffer allocation size in KB */
1270 pba &= 0xffff;
1271 /* the tx fifo also stores 16 bytes of information about the tx
1272 * but don't include ethernet FCS because hardware appends it */
1273 min_tx_space = (adapter->max_frame_size +
85e8d004 1274 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1275 ETH_FCS_LEN) * 2;
1276 min_tx_space = ALIGN(min_tx_space, 1024);
1277 min_tx_space >>= 10;
1278 /* software strips receive CRC, so leave room for it */
1279 min_rx_space = adapter->max_frame_size;
1280 min_rx_space = ALIGN(min_rx_space, 1024);
1281 min_rx_space >>= 10;
1282
1283 /* If current Tx allocation is less than the min Tx FIFO size,
1284 * and the min Tx FIFO size is less than the current Rx FIFO
1285 * allocation, take space away from current Rx allocation */
1286 if (tx_space < min_tx_space &&
1287 ((min_tx_space - tx_space) < pba)) {
1288 pba = pba - (min_tx_space - tx_space);
1289
1290 /* if short on rx space, rx wins and must trump tx
1291 * adjustment */
1292 if (pba < min_rx_space)
1293 pba = min_rx_space;
1294 }
2d064c06 1295 wr32(E1000_PBA, pba);
9d5c8243 1296 }
9d5c8243
AK		 1297
1298 /* flow control settings */
1299 /* The high water mark must be low enough to fit one full frame
1300 * (or the size used for early receive) above it in the Rx FIFO.
1301 * Set it to the lower of:
1302 * - 90% of the Rx FIFO size, or
1303 * - the full Rx FIFO size minus one full frame */
1304 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1305 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1306
d405ea3e
AD		 1307 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1308 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1309 fc->pause_time = 0xFFFF;
1310 fc->send_xon = 1;
0cce119a 1311 fc->current_mode = fc->requested_mode;
9d5c8243 1312
4ae196df
AD		 1313 /* disable receive for all VFs and wait one second */
1314 if (adapter->vfs_allocated_count) {
1315 int i;
1316 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
f2ca0dbe 1317 adapter->vf_data[i].flags = 0;
4ae196df
AD		 1318
1319 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1320 igb_ping_all_vfs(adapter);
4ae196df
AD		 1321
1322 /* disable transmits and receives */
1323 wr32(E1000_VFRE, 0);
1324 wr32(E1000_VFTE, 0);
1325 }
1326
9d5c8243 1327 /* Allow time for pending master requests to run */
330a6d6a 1328 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1329 wr32(E1000_WUC, 0);
1330
330a6d6a 1331 if (hw->mac.ops.init_hw(hw))
090b1795 1332 dev_err(&pdev->dev, "Hardware Error\n");
9d5c8243 1333
55cac248
AD		 1334 if (hw->mac.type == e1000_82580) {
1335 u32 reg = rd32(E1000_PCIEMISC);
1336 wr32(E1000_PCIEMISC,
1337 reg & ~E1000_PCIEMISC_LX_DECISION);
1338 }
88a268c1
NN		 1339 if (!netif_running(adapter->netdev))
1340 igb_power_down_link(adapter);
1341
9d5c8243
AK		 1342 igb_update_mng_vlan(adapter);
1343
1344 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1345 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1346
330a6d6a 1347 igb_get_phy_info(hw);
9d5c8243
AK		 1348}
1349
2e5c6922 1350static const struct net_device_ops igb_netdev_ops = {
559e9c49 1351 .ndo_open = igb_open,
2e5c6922 1352 .ndo_stop = igb_close,
00829823 1353 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1354 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1355 .ndo_set_rx_mode = igb_set_rx_mode,
1356 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1357 .ndo_set_mac_address = igb_set_mac,
1358 .ndo_change_mtu = igb_change_mtu,
1359 .ndo_do_ioctl = igb_ioctl,
1360 .ndo_tx_timeout = igb_tx_timeout,
1361 .ndo_validate_addr = eth_validate_addr,
1362 .ndo_vlan_rx_register = igb_vlan_rx_register,
1363 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1364 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1365 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1366 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1367 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1368 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1369#ifdef CONFIG_NET_POLL_CONTROLLER
1370 .ndo_poll_controller = igb_netpoll,
1371#endif
1372};
1373
9d5c8243
AK		 1374/**
1375 * igb_probe - Device Initialization Routine
1376 * @pdev: PCI device information struct
1377 * @ent: entry in igb_pci_tbl
1378 *
1379 * Returns 0 on success, negative on failure
1380 *
1381 * igb_probe initializes an adapter identified by a pci_dev structure.
1382 * The OS initialization, configuring of the adapter private structure,
1383 * and a hardware reset occur.
1384 **/
1385static int __devinit igb_probe(struct pci_dev *pdev,
1386 const struct pci_device_id *ent)
1387{
1388 struct net_device *netdev;
1389 struct igb_adapter *adapter;
1390 struct e1000_hw *hw;
4337e993
AD		 1391 u16 eeprom_data = 0;
1392 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1393 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1394 unsigned long mmio_start, mmio_len;
2d6a5e95 1395 int err, pci_using_dac;
9d5c8243
AK		 1396 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1397 u32 part_num;
1398
aed5dec3 1399 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1400 if (err)
1401 return err;
1402
1403 pci_using_dac = 0;
6a35528a 1404 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1405 if (!err) {
6a35528a 1406 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1407 if (!err)
1408 pci_using_dac = 1;
1409 } else {
284901a9 1410 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1411 if (err) {
284901a9 1412 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1413 if (err) {
1414 dev_err(&pdev->dev, "No usable DMA "
1415 "configuration, aborting\n");
1416 goto err_dma;
1417 }
1418 }
1419 }
1420
aed5dec3
AD		 1421 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1422 IORESOURCE_MEM),
1423 igb_driver_name);
9d5c8243
AK		 1424 if (err)
1425 goto err_pci_reg;
1426
19d5afd4 1427 pci_enable_pcie_error_reporting(pdev);
40a914fa 1428
9d5c8243 1429 pci_set_master(pdev);
c682fc23 1430 pci_save_state(pdev);
9d5c8243
AK		 1431
1432 err = -ENOMEM;
1bfaf07b
AD		 1433 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1434 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1435 if (!netdev)
1436 goto err_alloc_etherdev;
1437
1438 SET_NETDEV_DEV(netdev, &pdev->dev);
1439
1440 pci_set_drvdata(pdev, netdev);
1441 adapter = netdev_priv(netdev);
1442 adapter->netdev = netdev;
1443 adapter->pdev = pdev;
1444 hw = &adapter->hw;
1445 hw->back = adapter;
1446 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1447
1448 mmio_start = pci_resource_start(pdev, 0);
1449 mmio_len = pci_resource_len(pdev, 0);
1450
1451 err = -EIO;
28b0759c
AD		 1452 hw->hw_addr = ioremap(mmio_start, mmio_len);
1453 if (!hw->hw_addr)
9d5c8243
AK		 1454 goto err_ioremap;
1455
2e5c6922 1456 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1457 igb_set_ethtool_ops(netdev);
9d5c8243 1458 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1459
1460 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1461
1462 netdev->mem_start = mmio_start;
1463 netdev->mem_end = mmio_start + mmio_len;
1464
9d5c8243
AK		 1465 /* PCI config space info */
1466 hw->vendor_id = pdev->vendor;
1467 hw->device_id = pdev->device;
1468 hw->revision_id = pdev->revision;
1469 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1470 hw->subsystem_device_id = pdev->subsystem_device;
1471
9d5c8243
AK		 1472 /* Copy the default MAC, PHY and NVM function pointers */
1473 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1474 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1475 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1476 /* Initialize skew-specific constants */
1477 err = ei->get_invariants(hw);
1478 if (err)
450c87c8 1479 goto err_sw_init;
9d5c8243 1480
450c87c8 1481 /* setup the private structure */
9d5c8243
AK		 1482 err = igb_sw_init(adapter);
1483 if (err)
1484 goto err_sw_init;
1485
1486 igb_get_bus_info_pcie(hw);
1487
1488 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1489
1490 /* Copper options */
1491 if (hw->phy.media_type == e1000_media_type_copper) {
1492 hw->phy.mdix = AUTO_ALL_MODES;
1493 hw->phy.disable_polarity_correction = false;
1494 hw->phy.ms_type = e1000_ms_hw_default;
1495 }
1496
1497 if (igb_check_reset_block(hw))
1498 dev_info(&pdev->dev,
1499 "PHY reset is blocked due to SOL/IDER session.\n");
1500
1501 netdev->features = NETIF_F_SG |
7d8eb29e 1502 NETIF_F_IP_CSUM |
9d5c8243
AK		 1503 NETIF_F_HW_VLAN_TX |
1504 NETIF_F_HW_VLAN_RX |
1505 NETIF_F_HW_VLAN_FILTER;
1506
7d8eb29e 1507 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1508 netdev->features |= NETIF_F_TSO;
9d5c8243 1509 netdev->features |= NETIF_F_TSO6;
5c0999b7 1510 netdev->features |= NETIF_F_GRO;
d3352520 1511
48f29ffc
JK		 1512 netdev->vlan_features |= NETIF_F_TSO;
1513 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1514 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1515 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1516 netdev->vlan_features |= NETIF_F_SG;
1517
9d5c8243
AK		 1518 if (pci_using_dac)
1519 netdev->features |= NETIF_F_HIGHDMA;
1520
5b043fb0 1521 if (hw->mac.type >= e1000_82576)
b9473560
JB		 1522 netdev->features |= NETIF_F_SCTP_CSUM;
1523
330a6d6a 1524 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1525
1526 /* before reading the NVM, reset the controller to put the device in a
1527 * known good starting state */
1528 hw->mac.ops.reset_hw(hw);
1529
1530 /* make sure the NVM is good */
1531 if (igb_validate_nvm_checksum(hw) < 0) {
1532 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1533 err = -EIO;
1534 goto err_eeprom;
1535 }
1536
1537 /* copy the MAC address out of the NVM */
1538 if (hw->mac.ops.read_mac_addr(hw))
1539 dev_err(&pdev->dev, "NVM Read Error\n");
1540
1541 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1542 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1543
1544 if (!is_valid_ether_addr(netdev->perm_addr)) {
1545 dev_err(&pdev->dev, "Invalid MAC Address\n");
1546 err = -EIO;
1547 goto err_eeprom;
1548 }
1549
0e340485
AD		 1550 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1551 (unsigned long) adapter);
1552 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1553 (unsigned long) adapter);
9d5c8243
AK		 1554
1555 INIT_WORK(&adapter->reset_task, igb_reset_task);
1556 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1557
450c87c8 1558 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1559 adapter->fc_autoneg = true;
1560 hw->mac.autoneg = true;
1561 hw->phy.autoneg_advertised = 0x2f;
1562
0cce119a
AD		 1563 hw->fc.requested_mode = e1000_fc_default;
1564 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1565
9d5c8243
AK		 1566 igb_validate_mdi_setting(hw);
1567
9d5c8243
AK		 1568 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1569 * enable the ACPI Magic Packet filter
1570 */
1571
a2cf8b6c 1572 if (hw->bus.func == 0)
312c75ae 1573 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
55cac248
AD		 1574 else if (hw->mac.type == e1000_82580)
1575 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1576 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1577 &eeprom_data);
a2cf8b6c
AD		 1578 else if (hw->bus.func == 1)
1579 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1580
1581 if (eeprom_data & eeprom_apme_mask)
1582 adapter->eeprom_wol |= E1000_WUFC_MAG;
1583
1584 /* now that we have the eeprom settings, apply the special cases where
1585 * the eeprom may be wrong or the board simply won't support wake on
1586 * lan on a particular port */
1587 switch (pdev->device) {
1588 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1589 adapter->eeprom_wol = 0;
1590 break;
1591 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1592 case E1000_DEV_ID_82576_FIBER:
1593 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1594 /* Wake events only supported on port A for dual fiber
1595 * regardless of eeprom setting */
1596 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1597 adapter->eeprom_wol = 0;
1598 break;
c8ea5ea9
AD		 1599 case E1000_DEV_ID_82576_QUAD_COPPER:
1600 /* if quad port adapter, disable WoL on all but port A */
1601 if (global_quad_port_a != 0)
1602 adapter->eeprom_wol = 0;
1603 else
1604 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1605 /* Reset for multiple quad port adapters */
1606 if (++global_quad_port_a == 4)
1607 global_quad_port_a = 0;
1608 break;
9d5c8243
AK		 1609 }
1610
1611 /* initialize the wol settings based on the eeprom settings */
1612 adapter->wol = adapter->eeprom_wol;
e1b86d84 1613 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1614
1615 /* reset the hardware with the new settings */
1616 igb_reset(adapter);
1617
1618 /* let the f/w know that the h/w is now under the control of the
1619 * driver. */
1620 igb_get_hw_control(adapter);
1621
9d5c8243
AK		 1622 strcpy(netdev->name, "eth%d");
1623 err = register_netdev(netdev);
1624 if (err)
1625 goto err_register;
1626
b168dfc5
JB		 1627 /* carrier off reporting is important to ethtool even BEFORE open */
1628 netif_carrier_off(netdev);
1629
421e02f0 1630#ifdef CONFIG_IGB_DCA
bbd98fe4 1631 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1632 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1633 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1634 igb_setup_dca(adapter);
1635 }
fe4506b6 1636
38c845c7 1637#endif
9d5c8243
AK		 1638 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1639 /* print bus type/speed/width info */
7c510e4b 1640 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 1641 netdev->name,
559e9c49
AD		 1642 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1643 "unknown"),
59c3de89
AD		 1644 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1645 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1646 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1647 "unknown"),
7c510e4b 1648 netdev->dev_addr);
9d5c8243
AK		 1649
1650 igb_read_part_num(hw, &part_num);
1651 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1652 (part_num >> 8), (part_num & 0xff));
1653
1654 dev_info(&pdev->dev,
1655 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1656 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1657 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1658 adapter->num_rx_queues, adapter->num_tx_queues);
1659
9d5c8243
AK		 1660 return 0;
1661
1662err_register:
1663 igb_release_hw_control(adapter);
1664err_eeprom:
1665 if (!igb_check_reset_block(hw))
f5f4cf08 1666 igb_reset_phy(hw);
9d5c8243
AK		 1667
1668 if (hw->flash_address)
1669 iounmap(hw->flash_address);
9d5c8243 1670err_sw_init:
047e0030 1671 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1672 iounmap(hw->hw_addr);
1673err_ioremap:
1674 free_netdev(netdev);
1675err_alloc_etherdev:
559e9c49
AD		 1676 pci_release_selected_regions(pdev,
1677 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 1678err_pci_reg:
1679err_dma:
1680 pci_disable_device(pdev);
1681 return err;
1682}
1683
1684/**
1685 * igb_remove - Device Removal Routine
1686 * @pdev: PCI device information struct
1687 *
1688 * igb_remove is called by the PCI subsystem to alert the driver
1689 * that it should release a PCI device. The could be caused by a
1690 * Hot-Plug event, or because the driver is going to be removed from
1691 * memory.
1692 **/
1693static void __devexit igb_remove(struct pci_dev *pdev)
1694{
1695 struct net_device *netdev = pci_get_drvdata(pdev);
1696 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1697 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1698
1699 /* flush_scheduled work may reschedule our watchdog task, so
1700 * explicitly disable watchdog tasks from being rescheduled */
1701 set_bit(__IGB_DOWN, &adapter->state);
1702 del_timer_sync(&adapter->watchdog_timer);
1703 del_timer_sync(&adapter->phy_info_timer);
1704
1705 flush_scheduled_work();
1706
421e02f0 1707#ifdef CONFIG_IGB_DCA
7dfc16fa 1708 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1709 dev_info(&pdev->dev, "DCA disabled\n");
1710 dca_remove_requester(&pdev->dev);
7dfc16fa 1711 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1712 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1713 }
1714#endif
1715
9d5c8243
AK		 1716 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1717 * would have already happened in close and is redundant. */
1718 igb_release_hw_control(adapter);
1719
1720 unregister_netdev(netdev);
1721
047e0030 1722 igb_clear_interrupt_scheme(adapter);
9d5c8243 1723
37680117
AD		 1724#ifdef CONFIG_PCI_IOV
1725 /* reclaim resources allocated to VFs */
1726 if (adapter->vf_data) {
1727 /* disable iov and allow time for transactions to clear */
1728 pci_disable_sriov(pdev);
1729 msleep(500);
1730
1731 kfree(adapter->vf_data);
1732 adapter->vf_data = NULL;
1733 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1734 msleep(100);
1735 dev_info(&pdev->dev, "IOV Disabled\n");
1736 }
1737#endif
559e9c49 1738
28b0759c
AD		 1739 iounmap(hw->hw_addr);
1740 if (hw->flash_address)
1741 iounmap(hw->flash_address);
559e9c49
AD		 1742 pci_release_selected_regions(pdev,
1743 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 1744
1745 free_netdev(netdev);
1746
19d5afd4 1747 pci_disable_pcie_error_reporting(pdev);
40a914fa 1748
9d5c8243
AK		 1749 pci_disable_device(pdev);
1750}
1751
a6b623e0
AD		 1752/**
1753 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
1754 * @adapter: board private structure to initialize
1755 *
1756 * This function initializes the vf specific data storage and then attempts to
1757 * allocate the VFs. The reason for ordering it this way is because it is much
1758 * mor expensive time wise to disable SR-IOV than it is to allocate and free
1759 * the memory for the VFs.
1760 **/
1761static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
1762{
1763#ifdef CONFIG_PCI_IOV
1764 struct pci_dev *pdev = adapter->pdev;
1765
1766 if (adapter->vfs_allocated_count > 7)
1767 adapter->vfs_allocated_count = 7;
1768
1769 if (adapter->vfs_allocated_count) {
1770 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
1771 sizeof(struct vf_data_storage),
1772 GFP_KERNEL);
1773 /* if allocation failed then we do not support SR-IOV */
1774 if (!adapter->vf_data) {
1775 adapter->vfs_allocated_count = 0;
1776 dev_err(&pdev->dev, "Unable to allocate memory for VF "
1777 "Data Storage\n");
1778 }
1779 }
1780
1781 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
1782 kfree(adapter->vf_data);
1783 adapter->vf_data = NULL;
1784#endif /* CONFIG_PCI_IOV */
1785 adapter->vfs_allocated_count = 0;
1786#ifdef CONFIG_PCI_IOV
1787 } else {
1788 unsigned char mac_addr[ETH_ALEN];
1789 int i;
1790 dev_info(&pdev->dev, "%d vfs allocated\n",
1791 adapter->vfs_allocated_count);
1792 for (i = 0; i < adapter->vfs_allocated_count; i++) {
1793 random_ether_addr(mac_addr);
1794 igb_set_vf_mac(adapter, i, mac_addr);
1795 }
1796 }
1797#endif /* CONFIG_PCI_IOV */
1798}
1799
115f459a
AD		 1800
1801/**
1802 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
1803 * @adapter: board private structure to initialize
1804 *
1805 * igb_init_hw_timer initializes the function pointer and values for the hw
1806 * timer found in hardware.
1807 **/
1808static void igb_init_hw_timer(struct igb_adapter *adapter)
1809{
1810 struct e1000_hw *hw = &adapter->hw;
1811
1812 switch (hw->mac.type) {
d2ba2ed8 1813 case e1000_i350:
55cac248
AD		 1814 case e1000_82580:
1815 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1816 adapter->cycles.read = igb_read_clock;
1817 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1818 adapter->cycles.mult = 1;
1819 /*
1820 * The 82580 timesync updates the system timer every 8ns by 8ns
1821 * and the value cannot be shifted. Instead we need to shift
1822 * the registers to generate a 64bit timer value. As a result
1823 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
1824 * 24 in order to generate a larger value for synchronization.
1825 */
1826 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
1827 /* disable system timer temporarily by setting bit 31 */
1828 wr32(E1000_TSAUXC, 0x80000000);
1829 wrfl();
1830
1831 /* Set registers so that rollover occurs soon to test this. */
1832 wr32(E1000_SYSTIMR, 0x00000000);
1833 wr32(E1000_SYSTIML, 0x80000000);
1834 wr32(E1000_SYSTIMH, 0x000000FF);
1835 wrfl();
1836
1837 /* enable system timer by clearing bit 31 */
1838 wr32(E1000_TSAUXC, 0x0);
1839 wrfl();
1840
1841 timecounter_init(&adapter->clock,
1842 &adapter->cycles,
1843 ktime_to_ns(ktime_get_real()));
1844 /*
1845 * Synchronize our NIC clock against system wall clock. NIC
1846 * time stamp reading requires ~3us per sample, each sample
1847 * was pretty stable even under load => only require 10
1848 * samples for each offset comparison.
1849 */
1850 memset(&adapter->compare, 0, sizeof(adapter->compare));
1851 adapter->compare.source = &adapter->clock;
1852 adapter->compare.target = ktime_get_real;
1853 adapter->compare.num_samples = 10;
1854 timecompare_update(&adapter->compare, 0);
1855 break;
115f459a
AD		 1856 case e1000_82576:
1857 /*
1858 * Initialize hardware timer: we keep it running just in case
1859 * that some program needs it later on.
1860 */
1861 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1862 adapter->cycles.read = igb_read_clock;
1863 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1864 adapter->cycles.mult = 1;
1865 /**
1866 * Scale the NIC clock cycle by a large factor so that
1867 * relatively small clock corrections can be added or
1868 * substracted at each clock tick. The drawbacks of a large
1869 * factor are a) that the clock register overflows more quickly
1870 * (not such a big deal) and b) that the increment per tick has
1871 * to fit into 24 bits. As a result we need to use a shift of
1872 * 19 so we can fit a value of 16 into the TIMINCA register.
1873 */
1874 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
1875 wr32(E1000_TIMINCA,
1876 (1 << E1000_TIMINCA_16NS_SHIFT) |
1877 (16 << IGB_82576_TSYNC_SHIFT));
1878
1879 /* Set registers so that rollover occurs soon to test this. */
1880 wr32(E1000_SYSTIML, 0x00000000);
1881 wr32(E1000_SYSTIMH, 0xFF800000);
1882 wrfl();
1883
1884 timecounter_init(&adapter->clock,
1885 &adapter->cycles,
1886 ktime_to_ns(ktime_get_real()));
1887 /*
1888 * Synchronize our NIC clock against system wall clock. NIC
1889 * time stamp reading requires ~3us per sample, each sample
1890 * was pretty stable even under load => only require 10
1891 * samples for each offset comparison.
1892 */
1893 memset(&adapter->compare, 0, sizeof(adapter->compare));
1894 adapter->compare.source = &adapter->clock;
1895 adapter->compare.target = ktime_get_real;
1896 adapter->compare.num_samples = 10;
1897 timecompare_update(&adapter->compare, 0);
1898 break;
1899 case e1000_82575:
1900 /* 82575 does not support timesync */
1901 default:
1902 break;
1903 }
1904
1905}
1906
9d5c8243
AK		 1907/**
1908 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1909 * @adapter: board private structure to initialize
1910 *
1911 * igb_sw_init initializes the Adapter private data structure.
1912 * Fields are initialized based on PCI device information and
1913 * OS network device settings (MTU size).
1914 **/
1915static int __devinit igb_sw_init(struct igb_adapter *adapter)
1916{
1917 struct e1000_hw *hw = &adapter->hw;
1918 struct net_device *netdev = adapter->netdev;
1919 struct pci_dev *pdev = adapter->pdev;
1920
1921 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1922
68fd9910
AD		 1923 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1924 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 1925 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
1926 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
1927
9d5c8243
AK		 1928 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1929 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1930
a6b623e0
AD		 1931#ifdef CONFIG_PCI_IOV
1932 if (hw->mac.type == e1000_82576)
1933 adapter->vfs_allocated_count = max_vfs;
1934
1935#endif /* CONFIG_PCI_IOV */
a99955fc
AD		 1936 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
1937
1938 /*
1939 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
1940 * then we should combine the queues into a queue pair in order to
1941 * conserve interrupts due to limited supply
1942 */
1943 if ((adapter->rss_queues > 4) ||
1944 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
1945 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1946
a6b623e0 1947 /* This call may decrease the number of queues */
047e0030 1948 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1949 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1950 return -ENOMEM;
1951 }
1952
115f459a 1953 igb_init_hw_timer(adapter);
a6b623e0
AD		 1954 igb_probe_vfs(adapter);
1955
9d5c8243
AK		 1956 /* Explicitly disable IRQ since the NIC can be in any state. */
1957 igb_irq_disable(adapter);
1958
1959 set_bit(__IGB_DOWN, &adapter->state);
1960 return 0;
1961}
1962
1963/**
1964 * igb_open - Called when a network interface is made active
1965 * @netdev: network interface device structure
1966 *
1967 * Returns 0 on success, negative value on failure
1968 *
1969 * The open entry point is called when a network interface is made
1970 * active by the system (IFF_UP). At this point all resources needed
1971 * for transmit and receive operations are allocated, the interrupt
1972 * handler is registered with the OS, the watchdog timer is started,
1973 * and the stack is notified that the interface is ready.
1974 **/
1975static int igb_open(struct net_device *netdev)
1976{
1977 struct igb_adapter *adapter = netdev_priv(netdev);
1978 struct e1000_hw *hw = &adapter->hw;
1979 int err;
1980 int i;
1981
1982 /* disallow open during test */
1983 if (test_bit(__IGB_TESTING, &adapter->state))
1984 return -EBUSY;
1985
b168dfc5
JB		 1986 netif_carrier_off(netdev);
1987
9d5c8243
AK		 1988 /* allocate transmit descriptors */
1989 err = igb_setup_all_tx_resources(adapter);
1990 if (err)
1991 goto err_setup_tx;
1992
1993 /* allocate receive descriptors */
1994 err = igb_setup_all_rx_resources(adapter);
1995 if (err)
1996 goto err_setup_rx;
1997
88a268c1 1998 igb_power_up_link(adapter);
9d5c8243 1999
9d5c8243
AK		 2000 /* before we allocate an interrupt, we must be ready to handle it.
2001 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2002 * as soon as we call pci_request_irq, so we have to setup our
2003 * clean_rx handler before we do so. */
2004 igb_configure(adapter);
2005
2006 err = igb_request_irq(adapter);
2007 if (err)
2008 goto err_req_irq;
2009
2010 /* From here on the code is the same as igb_up() */
2011 clear_bit(__IGB_DOWN, &adapter->state);
2012
047e0030
AD		 2013 for (i = 0; i < adapter->num_q_vectors; i++) {
2014 struct igb_q_vector *q_vector = adapter->q_vector[i];
2015 napi_enable(&q_vector->napi);
2016 }
9d5c8243
AK		 2017
2018 /* Clear any pending interrupts. */
2019 rd32(E1000_ICR);
844290e5
PW		 2020
2021 igb_irq_enable(adapter);
2022
d4960307
AD		 2023 /* notify VFs that reset has been completed */
2024 if (adapter->vfs_allocated_count) {
2025 u32 reg_data = rd32(E1000_CTRL_EXT);
2026 reg_data |= E1000_CTRL_EXT_PFRSTD;
2027 wr32(E1000_CTRL_EXT, reg_data);
2028 }
2029
d55b53ff
JK		 2030 netif_tx_start_all_queues(netdev);
2031
25568a53
AD		 2032 /* start the watchdog. */
2033 hw->mac.get_link_status = 1;
2034 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2035
2036 return 0;
2037
2038err_req_irq:
2039 igb_release_hw_control(adapter);
88a268c1 2040 igb_power_down_link(adapter);
9d5c8243
AK		 2041 igb_free_all_rx_resources(adapter);
2042err_setup_rx:
2043 igb_free_all_tx_resources(adapter);
2044err_setup_tx:
2045 igb_reset(adapter);
2046
2047 return err;
2048}
2049
2050/**
2051 * igb_close - Disables a network interface
2052 * @netdev: network interface device structure
2053 *
2054 * Returns 0, this is not allowed to fail
2055 *
2056 * The close entry point is called when an interface is de-activated
2057 * by the OS. The hardware is still under the driver's control, but
2058 * needs to be disabled. A global MAC reset is issued to stop the
2059 * hardware, and all transmit and receive resources are freed.
2060 **/
2061static int igb_close(struct net_device *netdev)
2062{
2063 struct igb_adapter *adapter = netdev_priv(netdev);
2064
2065 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2066 igb_down(adapter);
2067
2068 igb_free_irq(adapter);
2069
2070 igb_free_all_tx_resources(adapter);
2071 igb_free_all_rx_resources(adapter);
2072
9d5c8243
AK		 2073 return 0;
2074}
2075
2076/**
2077 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2078 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2079 *
2080 * Return 0 on success, negative on failure
2081 **/
80785298 2082int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2083{
80785298 2084 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 2085 int size;
2086
2087 size = sizeof(struct igb_buffer) * tx_ring->count;
2088 tx_ring->buffer_info = vmalloc(size);
2089 if (!tx_ring->buffer_info)
2090 goto err;
2091 memset(tx_ring->buffer_info, 0, size);
2092
2093 /* round up to nearest 4K */
85e8d004 2094 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2095 tx_ring->size = ALIGN(tx_ring->size, 4096);
2096
439705e1
AD		 2097 tx_ring->desc = pci_alloc_consistent(pdev,
2098 tx_ring->size,
9d5c8243
AK		 2099 &tx_ring->dma);
2100
2101 if (!tx_ring->desc)
2102 goto err;
2103
9d5c8243
AK		 2104 tx_ring->next_to_use = 0;
2105 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2106 return 0;
2107
2108err:
2109 vfree(tx_ring->buffer_info);
047e0030 2110 dev_err(&pdev->dev,
9d5c8243
AK		 2111 "Unable to allocate memory for the transmit descriptor ring\n");
2112 return -ENOMEM;
2113}
2114
2115/**
2116 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2117 * (Descriptors) for all queues
2118 * @adapter: board private structure
2119 *
2120 * Return 0 on success, negative on failure
2121 **/
2122static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2123{
439705e1 2124 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2125 int i, err = 0;
2126
2127 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2128 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2129 if (err) {
439705e1 2130 dev_err(&pdev->dev,
9d5c8243
AK		 2131 "Allocation for Tx Queue %u failed\n", i);
2132 for (i--; i >= 0; i--)
3025a446 2133 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2134 break;
2135 }
2136 }
2137
a99955fc 2138 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2139 int r_idx = i % adapter->num_tx_queues;
3025a446 2140 adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
eebbbdba 2141 }
9d5c8243
AK		 2142 return err;
2143}
2144
2145/**
85b430b4
AD		 2146 * igb_setup_tctl - configure the transmit control registers
2147 * @adapter: Board private structure
9d5c8243 2148 **/
d7ee5b3a 2149void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2150{
9d5c8243
AK		 2151 struct e1000_hw *hw = &adapter->hw;
2152 u32 tctl;
9d5c8243 2153
85b430b4
AD		 2154 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2155 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2156
2157 /* Program the Transmit Control Register */
9d5c8243
AK		 2158 tctl = rd32(E1000_TCTL);
2159 tctl &= ~E1000_TCTL_CT;
2160 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2161 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2162
2163 igb_config_collision_dist(hw);
2164
9d5c8243
AK		 2165 /* Enable transmits */
2166 tctl |= E1000_TCTL_EN;
2167
2168 wr32(E1000_TCTL, tctl);
2169}
2170
85b430b4
AD		 2171/**
2172 * igb_configure_tx_ring - Configure transmit ring after Reset
2173 * @adapter: board private structure
2174 * @ring: tx ring to configure
2175 *
2176 * Configure a transmit ring after a reset.
2177 **/
d7ee5b3a
AD		 2178void igb_configure_tx_ring(struct igb_adapter *adapter,
2179 struct igb_ring *ring)
85b430b4
AD		 2180{
2181 struct e1000_hw *hw = &adapter->hw;
2182 u32 txdctl;
2183 u64 tdba = ring->dma;
2184 int reg_idx = ring->reg_idx;
2185
2186 /* disable the queue */
2187 txdctl = rd32(E1000_TXDCTL(reg_idx));
2188 wr32(E1000_TXDCTL(reg_idx),
2189 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2190 wrfl();
2191 mdelay(10);
2192
2193 wr32(E1000_TDLEN(reg_idx),
2194 ring->count * sizeof(union e1000_adv_tx_desc));
2195 wr32(E1000_TDBAL(reg_idx),
2196 tdba & 0x00000000ffffffffULL);
2197 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2198
fce99e34
AD		 2199 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2200 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2201 writel(0, ring->head);
2202 writel(0, ring->tail);
85b430b4
AD		 2203
2204 txdctl |= IGB_TX_PTHRESH;
2205 txdctl |= IGB_TX_HTHRESH << 8;
2206 txdctl |= IGB_TX_WTHRESH << 16;
2207
2208 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2209 wr32(E1000_TXDCTL(reg_idx), txdctl);
2210}
2211
2212/**
2213 * igb_configure_tx - Configure transmit Unit after Reset
2214 * @adapter: board private structure
2215 *
2216 * Configure the Tx unit of the MAC after a reset.
2217 **/
2218static void igb_configure_tx(struct igb_adapter *adapter)
2219{
2220 int i;
2221
2222 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2223 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2224}
2225
9d5c8243
AK		 2226/**
2227 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2228 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2229 *
2230 * Returns 0 on success, negative on failure
2231 **/
80785298 2232int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2233{
80785298 2234 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 2235 int size, desc_len;
2236
2237 size = sizeof(struct igb_buffer) * rx_ring->count;
2238 rx_ring->buffer_info = vmalloc(size);
2239 if (!rx_ring->buffer_info)
2240 goto err;
2241 memset(rx_ring->buffer_info, 0, size);
2242
2243 desc_len = sizeof(union e1000_adv_rx_desc);
2244
2245 /* Round up to nearest 4K */
2246 rx_ring->size = rx_ring->count * desc_len;
2247 rx_ring->size = ALIGN(rx_ring->size, 4096);
2248
2249 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2250 &rx_ring->dma);
2251
2252 if (!rx_ring->desc)
2253 goto err;
2254
2255 rx_ring->next_to_clean = 0;
2256 rx_ring->next_to_use = 0;
9d5c8243 2257
9d5c8243
AK		 2258 return 0;
2259
2260err:
2261 vfree(rx_ring->buffer_info);
439705e1 2262 rx_ring->buffer_info = NULL;
80785298 2263 dev_err(&pdev->dev, "Unable to allocate memory for "
9d5c8243
AK		 2264 "the receive descriptor ring\n");
2265 return -ENOMEM;
2266}
2267
2268/**
2269 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2270 * (Descriptors) for all queues
2271 * @adapter: board private structure
2272 *
2273 * Return 0 on success, negative on failure
2274 **/
2275static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2276{
439705e1 2277 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2278 int i, err = 0;
2279
2280 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2281 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2282 if (err) {
439705e1 2283 dev_err(&pdev->dev,
9d5c8243
AK		 2284 "Allocation for Rx Queue %u failed\n", i);
2285 for (i--; i >= 0; i--)
3025a446 2286 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2287 break;
2288 }
2289 }
2290
2291 return err;
2292}
2293
06cf2666
AD		 2294/**
2295 * igb_setup_mrqc - configure the multiple receive queue control registers
2296 * @adapter: Board private structure
2297 **/
2298static void igb_setup_mrqc(struct igb_adapter *adapter)
2299{
2300 struct e1000_hw *hw = &adapter->hw;
2301 u32 mrqc, rxcsum;
2302 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2303 union e1000_reta {
2304 u32 dword;
2305 u8 bytes[4];
2306 } reta;
2307 static const u8 rsshash[40] = {
2308 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2309 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2310 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2311 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2312
2313 /* Fill out hash function seeds */
2314 for (j = 0; j < 10; j++) {
2315 u32 rsskey = rsshash[(j * 4)];
2316 rsskey |= rsshash[(j * 4) + 1] << 8;
2317 rsskey |= rsshash[(j * 4) + 2] << 16;
2318 rsskey |= rsshash[(j * 4) + 3] << 24;
2319 array_wr32(E1000_RSSRK(0), j, rsskey);
2320 }
2321
a99955fc 2322 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2323
2324 if (adapter->vfs_allocated_count) {
2325 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2326 switch (hw->mac.type) {
d2ba2ed8 2327 case e1000_i350:
55cac248
AD		 2328 case e1000_82580:
2329 num_rx_queues = 1;
2330 shift = 0;
2331 break;
06cf2666
AD		 2332 case e1000_82576:
2333 shift = 3;
2334 num_rx_queues = 2;
2335 break;
2336 case e1000_82575:
2337 shift = 2;
2338 shift2 = 6;
2339 default:
2340 break;
2341 }
2342 } else {
2343 if (hw->mac.type == e1000_82575)
2344 shift = 6;
2345 }
2346
2347 for (j = 0; j < (32 * 4); j++) {
2348 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2349 if (shift2)
2350 reta.bytes[j & 3] |= num_rx_queues << shift2;
2351 if ((j & 3) == 3)
2352 wr32(E1000_RETA(j >> 2), reta.dword);
2353 }
2354
2355 /*
2356 * Disable raw packet checksumming so that RSS hash is placed in
2357 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2358 * offloads as they are enabled by default
2359 */
2360 rxcsum = rd32(E1000_RXCSUM);
2361 rxcsum |= E1000_RXCSUM_PCSD;
2362
2363 if (adapter->hw.mac.type >= e1000_82576)
2364 /* Enable Receive Checksum Offload for SCTP */
2365 rxcsum |= E1000_RXCSUM_CRCOFL;
2366
2367 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2368 wr32(E1000_RXCSUM, rxcsum);
2369
2370 /* If VMDq is enabled then we set the appropriate mode for that, else
2371 * we default to RSS so that an RSS hash is calculated per packet even
2372 * if we are only using one queue */
2373 if (adapter->vfs_allocated_count) {
2374 if (hw->mac.type > e1000_82575) {
2375 /* Set the default pool for the PF's first queue */
2376 u32 vtctl = rd32(E1000_VT_CTL);
2377 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2378 E1000_VT_CTL_DISABLE_DEF_POOL);
2379 vtctl |= adapter->vfs_allocated_count <<
2380 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2381 wr32(E1000_VT_CTL, vtctl);
2382 }
a99955fc 2383 if (adapter->rss_queues > 1)
06cf2666
AD		 2384 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2385 else
2386 mrqc = E1000_MRQC_ENABLE_VMDQ;
2387 } else {
2388 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2389 }
2390 igb_vmm_control(adapter);
2391
2392 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2393 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2394 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2395 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2396 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2397 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2398 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2399 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2400
2401 wr32(E1000_MRQC, mrqc);
2402}
2403
9d5c8243
AK		 2404/**
2405 * igb_setup_rctl - configure the receive control registers
2406 * @adapter: Board private structure
2407 **/
d7ee5b3a 2408void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2409{
2410 struct e1000_hw *hw = &adapter->hw;
2411 u32 rctl;
9d5c8243
AK		 2412
2413 rctl = rd32(E1000_RCTL);
2414
2415 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2416 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2417
69d728ba 2418 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2419 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2420
87cb7e8c
AK		 2421 /*
2422 * enable stripping of CRC. It's unlikely this will break BMC
2423 * redirection as it did with e1000. Newer features require
2424 * that the HW strips the CRC.
73cd78f1 2425 */
87cb7e8c 2426 rctl |= E1000_RCTL_SECRC;
9d5c8243 2427
559e9c49 2428 /* disable store bad packets and clear size bits. */
ec54d7d6 2429 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2430
6ec43fe6
AD		 2431 /* enable LPE to prevent packets larger than max_frame_size */
2432 rctl |= E1000_RCTL_LPE;
9d5c8243 2433
952f72a8
AD		 2434 /* disable queue 0 to prevent tail write w/o re-config */
2435 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2436
e1739522
AD		 2437 /* Attention!!! For SR-IOV PF driver operations you must enable
2438 * queue drop for all VF and PF queues to prevent head of line blocking
2439 * if an un-trusted VF does not provide descriptors to hardware.
2440 */
2441 if (adapter->vfs_allocated_count) {
e1739522
AD		 2442 /* set all queue drop enable bits */
2443 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2444 }
2445
9d5c8243
AK		 2446 wr32(E1000_RCTL, rctl);
2447}
2448
7d5753f0
AD		 2449static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2450 int vfn)
2451{
2452 struct e1000_hw *hw = &adapter->hw;
2453 u32 vmolr;
2454
2455 /* if it isn't the PF check to see if VFs are enabled and
2456 * increase the size to support vlan tags */
2457 if (vfn < adapter->vfs_allocated_count &&
2458 adapter->vf_data[vfn].vlans_enabled)
2459 size += VLAN_TAG_SIZE;
2460
2461 vmolr = rd32(E1000_VMOLR(vfn));
2462 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2463 vmolr |= size | E1000_VMOLR_LPE;
2464 wr32(E1000_VMOLR(vfn), vmolr);
2465
2466 return 0;
2467}
2468
e1739522
AD		 2469/**
2470 * igb_rlpml_set - set maximum receive packet size
2471 * @adapter: board private structure
2472 *
2473 * Configure maximum receivable packet size.
2474 **/
2475static void igb_rlpml_set(struct igb_adapter *adapter)
2476{
2477 u32 max_frame_size = adapter->max_frame_size;
2478 struct e1000_hw *hw = &adapter->hw;
2479 u16 pf_id = adapter->vfs_allocated_count;
2480
2481 if (adapter->vlgrp)
2482 max_frame_size += VLAN_TAG_SIZE;
2483
2484 /* if vfs are enabled we set RLPML to the largest possible request
2485 * size and set the VMOLR RLPML to the size we need */
2486 if (pf_id) {
2487 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
7d5753f0 2488 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2489 }
2490
2491 wr32(E1000_RLPML, max_frame_size);
2492}
2493
8151d294
WM		 2494static inline void igb_set_vmolr(struct igb_adapter *adapter,
2495 int vfn, bool aupe)
7d5753f0
AD		 2496{
2497 struct e1000_hw *hw = &adapter->hw;
2498 u32 vmolr;
2499
2500 /*
2501 * This register exists only on 82576 and newer so if we are older then
2502 * we should exit and do nothing
2503 */
2504 if (hw->mac.type < e1000_82576)
2505 return;
2506
2507 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2508 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2509 if (aupe)
2510 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2511 else
2512 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 2513
2514 /* clear all bits that might not be set */
2515 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2516
a99955fc 2517 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 2518 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2519 /*
2520 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2521 * multicast packets
2522 */
2523 if (vfn <= adapter->vfs_allocated_count)
2524 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2525
2526 wr32(E1000_VMOLR(vfn), vmolr);
2527}
2528
85b430b4
AD		 2529/**
2530 * igb_configure_rx_ring - Configure a receive ring after Reset
2531 * @adapter: board private structure
2532 * @ring: receive ring to be configured
2533 *
2534 * Configure the Rx unit of the MAC after a reset.
2535 **/
d7ee5b3a
AD		 2536void igb_configure_rx_ring(struct igb_adapter *adapter,
2537 struct igb_ring *ring)
85b430b4
AD		 2538{
2539 struct e1000_hw *hw = &adapter->hw;
2540 u64 rdba = ring->dma;
2541 int reg_idx = ring->reg_idx;
952f72a8 2542 u32 srrctl, rxdctl;
85b430b4
AD		 2543
2544 /* disable the queue */
2545 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2546 wr32(E1000_RXDCTL(reg_idx),
2547 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2548
2549 /* Set DMA base address registers */
2550 wr32(E1000_RDBAL(reg_idx),
2551 rdba & 0x00000000ffffffffULL);
2552 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2553 wr32(E1000_RDLEN(reg_idx),
2554 ring->count * sizeof(union e1000_adv_rx_desc));
2555
2556 /* initialize head and tail */
fce99e34
AD		 2557 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2558 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2559 writel(0, ring->head);
2560 writel(0, ring->tail);
85b430b4 2561
952f72a8 2562 /* set descriptor configuration */
4c844851
AD		 2563 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2564 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2565 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2566#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2567 srrctl |= IGB_RXBUFFER_16384 >>
2568 E1000_SRRCTL_BSIZEPKT_SHIFT;
2569#else
2570 srrctl |= (PAGE_SIZE / 2) >>
2571 E1000_SRRCTL_BSIZEPKT_SHIFT;
2572#endif
2573 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2574 } else {
4c844851 2575 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2576 E1000_SRRCTL_BSIZEPKT_SHIFT;
2577 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2578 }
e6bdb6fe
NN		 2579 /* Only set Drop Enable if we are supporting multiple queues */
2580 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
2581 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 2582
2583 wr32(E1000_SRRCTL(reg_idx), srrctl);
2584
7d5753f0 2585 /* set filtering for VMDQ pools */
8151d294 2586 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 2587
85b430b4
AD		 2588 /* enable receive descriptor fetching */
2589 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2590 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2591 rxdctl &= 0xFFF00000;
2592 rxdctl |= IGB_RX_PTHRESH;
2593 rxdctl |= IGB_RX_HTHRESH << 8;
2594 rxdctl |= IGB_RX_WTHRESH << 16;
2595 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2596}
2597
9d5c8243
AK		 2598/**
2599 * igb_configure_rx - Configure receive Unit after Reset
2600 * @adapter: board private structure
2601 *
2602 * Configure the Rx unit of the MAC after a reset.
2603 **/
2604static void igb_configure_rx(struct igb_adapter *adapter)
2605{
9107584e 2606 int i;
9d5c8243 2607
68d480c4
AD		 2608 /* set UTA to appropriate mode */
2609 igb_set_uta(adapter);
2610
26ad9178
AD		 2611 /* set the correct pool for the PF default MAC address in entry 0 */
2612 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2613 adapter->vfs_allocated_count);
2614
06cf2666
AD		 2615 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2616 * the Base and Length of the Rx Descriptor Ring */
2617 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2618 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 2619}
2620
2621/**
2622 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2623 * @tx_ring: Tx descriptor ring for a specific queue
2624 *
2625 * Free all transmit software resources
2626 **/
68fd9910 2627void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2628{
3b644cf6 2629 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2630
2631 vfree(tx_ring->buffer_info);
2632 tx_ring->buffer_info = NULL;
2633
439705e1
AD		 2634 /* if not set, then don't free */
2635 if (!tx_ring->desc)
2636 return;
2637
80785298
AD		 2638 pci_free_consistent(tx_ring->pdev, tx_ring->size,
2639 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2640
2641 tx_ring->desc = NULL;
2642}
2643
2644/**
2645 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2646 * @adapter: board private structure
2647 *
2648 * Free all transmit software resources
2649 **/
2650static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2651{
2652 int i;
2653
2654 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2655 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2656}
2657
b1a436c3
AD		 2658void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
2659 struct igb_buffer *buffer_info)
9d5c8243 2660{
6366ad33
AD		 2661 if (buffer_info->dma) {
2662 if (buffer_info->mapped_as_page)
2663 pci_unmap_page(tx_ring->pdev,
2664 buffer_info->dma,
2665 buffer_info->length,
2666 PCI_DMA_TODEVICE);
2667 else
2668 pci_unmap_single(tx_ring->pdev,
2669 buffer_info->dma,
2670 buffer_info->length,
2671 PCI_DMA_TODEVICE);
2672 buffer_info->dma = 0;
2673 }
9d5c8243
AK		 2674 if (buffer_info->skb) {
2675 dev_kfree_skb_any(buffer_info->skb);
2676 buffer_info->skb = NULL;
2677 }
2678 buffer_info->time_stamp = 0;
6366ad33
AD		 2679 buffer_info->length = 0;
2680 buffer_info->next_to_watch = 0;
2681 buffer_info->mapped_as_page = false;
9d5c8243
AK		 2682}
2683
2684/**
2685 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2686 * @tx_ring: ring to be cleaned
2687 **/
3b644cf6 2688static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 2689{
2690 struct igb_buffer *buffer_info;
2691 unsigned long size;
2692 unsigned int i;
2693
2694 if (!tx_ring->buffer_info)
2695 return;
2696 /* Free all the Tx ring sk_buffs */
2697
2698 for (i = 0; i < tx_ring->count; i++) {
2699 buffer_info = &tx_ring->buffer_info[i];
80785298 2700 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 2701 }
2702
2703 size = sizeof(struct igb_buffer) * tx_ring->count;
2704 memset(tx_ring->buffer_info, 0, size);
2705
2706 /* Zero out the descriptor ring */
9d5c8243
AK		 2707 memset(tx_ring->desc, 0, tx_ring->size);
2708
2709 tx_ring->next_to_use = 0;
2710 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2711}
2712
2713/**
2714 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2715 * @adapter: board private structure
2716 **/
2717static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2718{
2719 int i;
2720
2721 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2722 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 2723}
2724
2725/**
2726 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2727 * @rx_ring: ring to clean the resources from
2728 *
2729 * Free all receive software resources
2730 **/
68fd9910 2731void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2732{
3b644cf6 2733 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2734
2735 vfree(rx_ring->buffer_info);
2736 rx_ring->buffer_info = NULL;
2737
439705e1
AD		 2738 /* if not set, then don't free */
2739 if (!rx_ring->desc)
2740 return;
2741
80785298
AD		 2742 pci_free_consistent(rx_ring->pdev, rx_ring->size,
2743 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 2744
2745 rx_ring->desc = NULL;
2746}
2747
2748/**
2749 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2750 * @adapter: board private structure
2751 *
2752 * Free all receive software resources
2753 **/
2754static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2755{
2756 int i;
2757
2758 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2759 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2760}
2761
2762/**
2763 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2764 * @rx_ring: ring to free buffers from
2765 **/
3b644cf6 2766static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 2767{
2768 struct igb_buffer *buffer_info;
9d5c8243
AK		 2769 unsigned long size;
2770 unsigned int i;
2771
2772 if (!rx_ring->buffer_info)
2773 return;
439705e1 2774
9d5c8243
AK		 2775 /* Free all the Rx ring sk_buffs */
2776 for (i = 0; i < rx_ring->count; i++) {
2777 buffer_info = &rx_ring->buffer_info[i];
2778 if (buffer_info->dma) {
80785298
AD		 2779 pci_unmap_single(rx_ring->pdev,
2780 buffer_info->dma,
4c844851 2781 rx_ring->rx_buffer_len,
6ec43fe6 2782 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2783 buffer_info->dma = 0;
2784 }
2785
2786 if (buffer_info->skb) {
2787 dev_kfree_skb(buffer_info->skb);
2788 buffer_info->skb = NULL;
2789 }
6ec43fe6 2790 if (buffer_info->page_dma) {
80785298
AD		 2791 pci_unmap_page(rx_ring->pdev,
2792 buffer_info->page_dma,
6ec43fe6
AD		 2793 PAGE_SIZE / 2,
2794 PCI_DMA_FROMDEVICE);
2795 buffer_info->page_dma = 0;
2796 }
9d5c8243 2797 if (buffer_info->page) {
9d5c8243
AK		 2798 put_page(buffer_info->page);
2799 buffer_info->page = NULL;
bf36c1a0 2800 buffer_info->page_offset = 0;
9d5c8243
AK		 2801 }
2802 }
2803
9d5c8243
AK		 2804 size = sizeof(struct igb_buffer) * rx_ring->count;
2805 memset(rx_ring->buffer_info, 0, size);
2806
2807 /* Zero out the descriptor ring */
2808 memset(rx_ring->desc, 0, rx_ring->size);
2809
2810 rx_ring->next_to_clean = 0;
2811 rx_ring->next_to_use = 0;
9d5c8243
AK		 2812}
2813
2814/**
2815 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2816 * @adapter: board private structure
2817 **/
2818static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2819{
2820 int i;
2821
2822 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2823 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 2824}
2825
2826/**
2827 * igb_set_mac - Change the Ethernet Address of the NIC
2828 * @netdev: network interface device structure
2829 * @p: pointer to an address structure
2830 *
2831 * Returns 0 on success, negative on failure
2832 **/
2833static int igb_set_mac(struct net_device *netdev, void *p)
2834{
2835 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2836 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2837 struct sockaddr *addr = p;
2838
2839 if (!is_valid_ether_addr(addr->sa_data))
2840 return -EADDRNOTAVAIL;
2841
2842 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2843 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2844
26ad9178
AD		 2845 /* set the correct pool for the new PF MAC address in entry 0 */
2846 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2847 adapter->vfs_allocated_count);
e1739522 2848
9d5c8243
AK		 2849 return 0;
2850}
2851
2852/**
68d480c4 2853 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2854 * @netdev: network interface device structure
2855 *
68d480c4
AD		 2856 * Writes multicast address list to the MTA hash table.
2857 * Returns: -ENOMEM on failure
2858 * 0 on no addresses written
2859 * X on writing X addresses to MTA
9d5c8243 2860 **/
68d480c4 2861static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2862{
2863 struct igb_adapter *adapter = netdev_priv(netdev);
2864 struct e1000_hw *hw = &adapter->hw;
48e2f183 2865 struct dev_mc_list *mc_ptr;
68d480c4 2866 u8 *mta_list;
9d5c8243
AK		 2867 int i;
2868
4cd24eaf 2869 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 2870 /* nothing to program, so clear mc list */
2871 igb_update_mc_addr_list(hw, NULL, 0);
2872 igb_restore_vf_multicasts(adapter);
2873 return 0;
2874 }
9d5c8243 2875
4cd24eaf 2876 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 2877 if (!mta_list)
2878 return -ENOMEM;
ff41f8dc 2879
68d480c4 2880 /* The shared function expects a packed array of only addresses. */
48e2f183
JP		 2881 i = 0;
2882 netdev_for_each_mc_addr(mc_ptr, netdev)
2883 memcpy(mta_list + (i++ * ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
68d480c4 2884
68d480c4
AD		 2885 igb_update_mc_addr_list(hw, mta_list, i);
2886 kfree(mta_list);
2887
4cd24eaf 2888 return netdev_mc_count(netdev);
68d480c4
AD		 2889}
2890
2891/**
2892 * igb_write_uc_addr_list - write unicast addresses to RAR table
2893 * @netdev: network interface device structure
2894 *
2895 * Writes unicast address list to the RAR table.
2896 * Returns: -ENOMEM on failure/insufficient address space
2897 * 0 on no addresses written
2898 * X on writing X addresses to the RAR table
2899 **/
2900static int igb_write_uc_addr_list(struct net_device *netdev)
2901{
2902 struct igb_adapter *adapter = netdev_priv(netdev);
2903 struct e1000_hw *hw = &adapter->hw;
2904 unsigned int vfn = adapter->vfs_allocated_count;
2905 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2906 int count = 0;
2907
2908 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 2909 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 2910 return -ENOMEM;
9d5c8243 2911
32e7bfc4 2912 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 2913 struct netdev_hw_addr *ha;
32e7bfc4
JP		 2914
2915 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 2916 if (!rar_entries)
2917 break;
26ad9178
AD		 2918 igb_rar_set_qsel(adapter, ha->addr,
2919 rar_entries--,
68d480c4
AD		 2920 vfn);
2921 count++;
ff41f8dc
AD		 2922 }
2923 }
2924 /* write the addresses in reverse order to avoid write combining */
2925 for (; rar_entries > 0 ; rar_entries--) {
2926 wr32(E1000_RAH(rar_entries), 0);
2927 wr32(E1000_RAL(rar_entries), 0);
2928 }
2929 wrfl();
2930
68d480c4
AD		 2931 return count;
2932}
2933
2934/**
2935 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2936 * @netdev: network interface device structure
2937 *
2938 * The set_rx_mode entry point is called whenever the unicast or multicast
2939 * address lists or the network interface flags are updated. This routine is
2940 * responsible for configuring the hardware for proper unicast, multicast,
2941 * promiscuous mode, and all-multi behavior.
2942 **/
2943static void igb_set_rx_mode(struct net_device *netdev)
2944{
2945 struct igb_adapter *adapter = netdev_priv(netdev);
2946 struct e1000_hw *hw = &adapter->hw;
2947 unsigned int vfn = adapter->vfs_allocated_count;
2948 u32 rctl, vmolr = 0;
2949 int count;
2950
2951 /* Check for Promiscuous and All Multicast modes */
2952 rctl = rd32(E1000_RCTL);
2953
2954 /* clear the effected bits */
2955 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2956
2957 if (netdev->flags & IFF_PROMISC) {
2958 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2959 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2960 } else {
2961 if (netdev->flags & IFF_ALLMULTI) {
2962 rctl |= E1000_RCTL_MPE;
2963 vmolr |= E1000_VMOLR_MPME;
2964 } else {
2965 /*
2966 * Write addresses to the MTA, if the attempt fails
2967 * then we should just turn on promiscous mode so
2968 * that we can at least receive multicast traffic
2969 */
2970 count = igb_write_mc_addr_list(netdev);
2971 if (count < 0) {
2972 rctl |= E1000_RCTL_MPE;
2973 vmolr |= E1000_VMOLR_MPME;
2974 } else if (count) {
2975 vmolr |= E1000_VMOLR_ROMPE;
2976 }
2977 }
2978 /*
2979 * Write addresses to available RAR registers, if there is not
2980 * sufficient space to store all the addresses then enable
2981 * unicast promiscous mode
2982 */
2983 count = igb_write_uc_addr_list(netdev);
2984 if (count < 0) {
2985 rctl |= E1000_RCTL_UPE;
2986 vmolr |= E1000_VMOLR_ROPE;
2987 }
2988 rctl |= E1000_RCTL_VFE;
28fc06f5 2989 }
68d480c4 2990 wr32(E1000_RCTL, rctl);
28fc06f5 2991
68d480c4
AD		 2992 /*
2993 * In order to support SR-IOV and eventually VMDq it is necessary to set
2994 * the VMOLR to enable the appropriate modes. Without this workaround
2995 * we will have issues with VLAN tag stripping not being done for frames
2996 * that are only arriving because we are the default pool
2997 */
2998 if (hw->mac.type < e1000_82576)
28fc06f5 2999 return;
9d5c8243 3000
68d480c4
AD		 3001 vmolr |= rd32(E1000_VMOLR(vfn)) &
3002 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3003 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3004 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3005}
3006
3007/* Need to wait a few seconds after link up to get diagnostic information from
3008 * the phy */
3009static void igb_update_phy_info(unsigned long data)
3010{
3011 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3012 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3013}
3014
4d6b725e
AD		 3015/**
3016 * igb_has_link - check shared code for link and determine up/down
3017 * @adapter: pointer to driver private info
3018 **/
3145535a 3019bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3020{
3021 struct e1000_hw *hw = &adapter->hw;
3022 bool link_active = false;
3023 s32 ret_val = 0;
3024
3025 /* get_link_status is set on LSC (link status) interrupt or
3026 * rx sequence error interrupt. get_link_status will stay
3027 * false until the e1000_check_for_link establishes link
3028 * for copper adapters ONLY
3029 */
3030 switch (hw->phy.media_type) {
3031 case e1000_media_type_copper:
3032 if (hw->mac.get_link_status) {
3033 ret_val = hw->mac.ops.check_for_link(hw);
3034 link_active = !hw->mac.get_link_status;
3035 } else {
3036 link_active = true;
3037 }
3038 break;
4d6b725e
AD		 3039 case e1000_media_type_internal_serdes:
3040 ret_val = hw->mac.ops.check_for_link(hw);
3041 link_active = hw->mac.serdes_has_link;
3042 break;
3043 default:
3044 case e1000_media_type_unknown:
3045 break;
3046 }
3047
3048 return link_active;
3049}
3050
9d5c8243
AK		 3051/**
3052 * igb_watchdog - Timer Call-back
3053 * @data: pointer to adapter cast into an unsigned long
3054 **/
3055static void igb_watchdog(unsigned long data)
3056{
3057 struct igb_adapter *adapter = (struct igb_adapter *)data;
3058 /* Do the rest outside of interrupt context */
3059 schedule_work(&adapter->watchdog_task);
3060}
3061
3062static void igb_watchdog_task(struct work_struct *work)
3063{
3064 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3065 struct igb_adapter,
3066 watchdog_task);
9d5c8243 3067 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3068 struct net_device *netdev = adapter->netdev;
9d5c8243 3069 u32 link;
7a6ea550 3070 int i;
9d5c8243 3071
4d6b725e 3072 link = igb_has_link(adapter);
9d5c8243
AK		 3073 if (link) {
3074 if (!netif_carrier_ok(netdev)) {
3075 u32 ctrl;
330a6d6a
AD		 3076 hw->mac.ops.get_speed_and_duplex(hw,
3077 &adapter->link_speed,
3078 &adapter->link_duplex);
9d5c8243
AK		 3079
3080 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3081 /* Links status message must follow this format */
3082 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3083 "Flow Control: %s\n",
559e9c49
AD		 3084 netdev->name,
3085 adapter->link_speed,
3086 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3087 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3088 ((ctrl & E1000_CTRL_TFCE) &&
3089 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3090 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3091 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243
AK		 3092
3093 /* tweak tx_queue_len according to speed/duplex and
3094 * adjust the timeout factor */
3095 netdev->tx_queue_len = adapter->tx_queue_len;
3096 adapter->tx_timeout_factor = 1;
3097 switch (adapter->link_speed) {
3098 case SPEED_10:
3099 netdev->tx_queue_len = 10;
3100 adapter->tx_timeout_factor = 14;
3101 break;
3102 case SPEED_100:
3103 netdev->tx_queue_len = 100;
3104 /* maybe add some timeout factor ? */
3105 break;
3106 }
3107
3108 netif_carrier_on(netdev);
9d5c8243 3109
4ae196df
AD		 3110 igb_ping_all_vfs(adapter);
3111
4b1a9877 3112 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3113 if (!test_bit(__IGB_DOWN, &adapter->state))
3114 mod_timer(&adapter->phy_info_timer,
3115 round_jiffies(jiffies + 2 * HZ));
3116 }
3117 } else {
3118 if (netif_carrier_ok(netdev)) {
3119 adapter->link_speed = 0;
3120 adapter->link_duplex = 0;
527d47c1
AD		 3121 /* Links status message must follow this format */
3122 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3123 netdev->name);
9d5c8243 3124 netif_carrier_off(netdev);
4b1a9877 3125
4ae196df
AD		 3126 igb_ping_all_vfs(adapter);
3127
4b1a9877 3128 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3129 if (!test_bit(__IGB_DOWN, &adapter->state))
3130 mod_timer(&adapter->phy_info_timer,
3131 round_jiffies(jiffies + 2 * HZ));
3132 }
3133 }
3134
9d5c8243 3135 igb_update_stats(adapter);
9d5c8243 3136
dbabb065 3137 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3138 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3139 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3140 /* We've lost link, so the controller stops DMA,
3141 * but we've got queued Tx work that's never going
3142 * to get done, so reset controller to flush Tx.
3143 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3144 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3145 adapter->tx_timeout_count++;
3146 schedule_work(&adapter->reset_task);
3147 /* return immediately since reset is imminent */
3148 return;
3149 }
9d5c8243 3150 }
9d5c8243 3151
dbabb065
AD		 3152 /* Force detection of hung controller every watchdog period */
3153 tx_ring->detect_tx_hung = true;
3154 }
f7ba205e 3155
9d5c8243 3156 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3157 if (adapter->msix_entries) {
047e0030
AD		 3158 u32 eics = 0;
3159 for (i = 0; i < adapter->num_q_vectors; i++) {
3160 struct igb_q_vector *q_vector = adapter->q_vector[i];
3161 eics |= q_vector->eims_value;
3162 }
7a6ea550
AD		 3163 wr32(E1000_EICS, eics);
3164 } else {
3165 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3166 }
9d5c8243 3167
9d5c8243
AK		 3168 /* Reset the timer */
3169 if (!test_bit(__IGB_DOWN, &adapter->state))
3170 mod_timer(&adapter->watchdog_timer,
3171 round_jiffies(jiffies + 2 * HZ));
3172}
3173
3174enum latency_range {
3175 lowest_latency = 0,
3176 low_latency = 1,
3177 bulk_latency = 2,
3178 latency_invalid = 255
3179};
3180
6eb5a7f1
AD		 3181/**
3182 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3183 *
3184 * Stores a new ITR value based on strictly on packet size. This
3185 * algorithm is less sophisticated than that used in igb_update_itr,
3186 * due to the difficulty of synchronizing statistics across multiple
3187 * receive rings. The divisors and thresholds used by this fuction
3188 * were determined based on theoretical maximum wire speed and testing
3189 * data, in order to minimize response time while increasing bulk
3190 * throughput.
3191 * This functionality is controlled by the InterruptThrottleRate module
3192 * parameter (see igb_param.c)
3193 * NOTE: This function is called only when operating in a multiqueue
3194 * receive environment.
047e0030 3195 * @q_vector: pointer to q_vector
6eb5a7f1 3196 **/
047e0030 3197static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3198{
047e0030 3199 int new_val = q_vector->itr_val;
6eb5a7f1 3200 int avg_wire_size = 0;
047e0030 3201 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3202
6eb5a7f1
AD		 3203 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3204 * ints/sec - ITR timer value of 120 ticks.
3205 */
3206 if (adapter->link_speed != SPEED_1000) {
047e0030 3207 new_val = 976;
6eb5a7f1 3208 goto set_itr_val;
9d5c8243 3209 }
047e0030
AD		 3210
3211 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3212 struct igb_ring *ring = q_vector->rx_ring;
3213 avg_wire_size = ring->total_bytes / ring->total_packets;
3214 }
3215
3216 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3217 struct igb_ring *ring = q_vector->tx_ring;
3218 avg_wire_size = max_t(u32, avg_wire_size,
3219 (ring->total_bytes /
3220 ring->total_packets));
3221 }
3222
3223 /* if avg_wire_size isn't set no work was done */
3224 if (!avg_wire_size)
3225 goto clear_counts;
9d5c8243 3226
6eb5a7f1
AD		 3227 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3228 avg_wire_size += 24;
3229
3230 /* Don't starve jumbo frames */
3231 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3232
6eb5a7f1
AD		 3233 /* Give a little boost to mid-size frames */
3234 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3235 new_val = avg_wire_size / 3;
3236 else
3237 new_val = avg_wire_size / 2;
9d5c8243 3238
abe1c363
NN		 3239 /* when in itr mode 3 do not exceed 20K ints/sec */
3240 if (adapter->rx_itr_setting == 3 && new_val < 196)
3241 new_val = 196;
3242
6eb5a7f1 3243set_itr_val:
047e0030
AD		 3244 if (new_val != q_vector->itr_val) {
3245 q_vector->itr_val = new_val;
3246 q_vector->set_itr = 1;
9d5c8243 3247 }
6eb5a7f1 3248clear_counts:
047e0030
AD		 3249 if (q_vector->rx_ring) {
3250 q_vector->rx_ring->total_bytes = 0;
3251 q_vector->rx_ring->total_packets = 0;
3252 }
3253 if (q_vector->tx_ring) {
3254 q_vector->tx_ring->total_bytes = 0;
3255 q_vector->tx_ring->total_packets = 0;
3256 }
9d5c8243
AK		 3257}
3258
3259/**
3260 * igb_update_itr - update the dynamic ITR value based on statistics
3261 * Stores a new ITR value based on packets and byte
3262 * counts during the last interrupt. The advantage of per interrupt
3263 * computation is faster updates and more accurate ITR for the current
3264 * traffic pattern. Constants in this function were computed
3265 * based on theoretical maximum wire speed and thresholds were set based
3266 * on testing data as well as attempting to minimize response time
3267 * while increasing bulk throughput.
3268 * this functionality is controlled by the InterruptThrottleRate module
3269 * parameter (see igb_param.c)
3270 * NOTE: These calculations are only valid when operating in a single-
3271 * queue environment.
3272 * @adapter: pointer to adapter
047e0030 3273 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3274 * @packets: the number of packets during this measurement interval
3275 * @bytes: the number of bytes during this measurement interval
3276 **/
3277static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3278 int packets, int bytes)
3279{
3280 unsigned int retval = itr_setting;
3281
3282 if (packets == 0)
3283 goto update_itr_done;
3284
3285 switch (itr_setting) {
3286 case lowest_latency:
3287 /* handle TSO and jumbo frames */
3288 if (bytes/packets > 8000)
3289 retval = bulk_latency;
3290 else if ((packets < 5) && (bytes > 512))
3291 retval = low_latency;
3292 break;
3293 case low_latency: /* 50 usec aka 20000 ints/s */
3294 if (bytes > 10000) {
3295 /* this if handles the TSO accounting */
3296 if (bytes/packets > 8000) {
3297 retval = bulk_latency;
3298 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3299 retval = bulk_latency;
3300 } else if ((packets > 35)) {
3301 retval = lowest_latency;
3302 }
3303 } else if (bytes/packets > 2000) {
3304 retval = bulk_latency;
3305 } else if (packets <= 2 && bytes < 512) {
3306 retval = lowest_latency;
3307 }
3308 break;
3309 case bulk_latency: /* 250 usec aka 4000 ints/s */
3310 if (bytes > 25000) {
3311 if (packets > 35)
3312 retval = low_latency;
1e5c3d21 3313 } else if (bytes < 1500) {
9d5c8243
AK		 3314 retval = low_latency;
3315 }
3316 break;
3317 }
3318
3319update_itr_done:
3320 return retval;
3321}
3322
6eb5a7f1 3323static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3324{
047e0030 3325 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3326 u16 current_itr;
047e0030 3327 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3328
3329 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3330 if (adapter->link_speed != SPEED_1000) {
3331 current_itr = 0;
3332 new_itr = 4000;
3333 goto set_itr_now;
3334 }
3335
3336 adapter->rx_itr = igb_update_itr(adapter,
3337 adapter->rx_itr,
3025a446
AD		 3338 q_vector->rx_ring->total_packets,
3339 q_vector->rx_ring->total_bytes);
9d5c8243 3340
047e0030
AD		 3341 adapter->tx_itr = igb_update_itr(adapter,
3342 adapter->tx_itr,
3025a446
AD		 3343 q_vector->tx_ring->total_packets,
3344 q_vector->tx_ring->total_bytes);
047e0030 3345 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3346
6eb5a7f1 3347 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3348 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3349 current_itr = low_latency;
3350
9d5c8243
AK		 3351 switch (current_itr) {
3352 /* counts and packets in update_itr are dependent on these numbers */
3353 case lowest_latency:
78b1f607 3354 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3355 break;
3356 case low_latency:
78b1f607 3357 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3358 break;
3359 case bulk_latency:
78b1f607 3360 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3361 break;
3362 default:
3363 break;
3364 }
3365
3366set_itr_now:
3025a446
AD		 3367 q_vector->rx_ring->total_bytes = 0;
3368 q_vector->rx_ring->total_packets = 0;
3369 q_vector->tx_ring->total_bytes = 0;
3370 q_vector->tx_ring->total_packets = 0;
6eb5a7f1 3371
047e0030 3372 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3373 /* this attempts to bias the interrupt rate towards Bulk
3374 * by adding intermediate steps when interrupt rate is
3375 * increasing */
047e0030
AD		 3376 new_itr = new_itr > q_vector->itr_val ?
3377 max((new_itr * q_vector->itr_val) /
3378 (new_itr + (q_vector->itr_val >> 2)),
3379 new_itr) :
9d5c8243
AK		 3380 new_itr;
3381 /* Don't write the value here; it resets the adapter's
3382 * internal timer, and causes us to delay far longer than
3383 * we should between interrupts. Instead, we write the ITR
3384 * value at the beginning of the next interrupt so the timing
3385 * ends up being correct.
3386 */
047e0030
AD		 3387 q_vector->itr_val = new_itr;
3388 q_vector->set_itr = 1;
9d5c8243
AK		 3389 }
3390
3391 return;
3392}
3393
9d5c8243
AK		 3394#define IGB_TX_FLAGS_CSUM 0x00000001
3395#define IGB_TX_FLAGS_VLAN 0x00000002
3396#define IGB_TX_FLAGS_TSO 0x00000004
3397#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3398#define IGB_TX_FLAGS_TSTAMP 0x00000010
3399#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3400#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3401
85ad76b2 3402static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3403 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3404{
3405 struct e1000_adv_tx_context_desc *context_desc;
3406 unsigned int i;
3407 int err;
3408 struct igb_buffer *buffer_info;
3409 u32 info = 0, tu_cmd = 0;
91d4ee33
NN		 3410 u32 mss_l4len_idx;
3411 u8 l4len;
9d5c8243
AK		 3412
3413 if (skb_header_cloned(skb)) {
3414 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3415 if (err)
3416 return err;
3417 }
3418
3419 l4len = tcp_hdrlen(skb);
3420 *hdr_len += l4len;
3421
3422 if (skb->protocol == htons(ETH_P_IP)) {
3423 struct iphdr *iph = ip_hdr(skb);
3424 iph->tot_len = 0;
3425 iph->check = 0;
3426 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3427 iph->daddr, 0,
3428 IPPROTO_TCP,
3429 0);
8e1e8a47 3430 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3431 ipv6_hdr(skb)->payload_len = 0;
3432 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3433 &ipv6_hdr(skb)->daddr,
3434 0, IPPROTO_TCP, 0);
3435 }
3436
3437 i = tx_ring->next_to_use;
3438
3439 buffer_info = &tx_ring->buffer_info[i];
3440 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3441 /* VLAN MACLEN IPLEN */
3442 if (tx_flags & IGB_TX_FLAGS_VLAN)
3443 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3444 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3445 *hdr_len += skb_network_offset(skb);
3446 info |= skb_network_header_len(skb);
3447 *hdr_len += skb_network_header_len(skb);
3448 context_desc->vlan_macip_lens = cpu_to_le32(info);
3449
3450 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3451 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3452
3453 if (skb->protocol == htons(ETH_P_IP))
3454 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3455 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3456
3457 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3458
3459 /* MSS L4LEN IDX */
3460 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3461 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3462
73cd78f1 3463 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3464 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3465 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3466
3467 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3468 context_desc->seqnum_seed = 0;
3469
3470 buffer_info->time_stamp = jiffies;
0e014cb1 3471 buffer_info->next_to_watch = i;
9d5c8243
AK		 3472 buffer_info->dma = 0;
3473 i++;
3474 if (i == tx_ring->count)
3475 i = 0;
3476
3477 tx_ring->next_to_use = i;
3478
3479 return true;
3480}
3481
85ad76b2
AD		 3482static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3483 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3484{
3485 struct e1000_adv_tx_context_desc *context_desc;
80785298 3486 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3487 struct igb_buffer *buffer_info;
3488 u32 info = 0, tu_cmd = 0;
80785298 3489 unsigned int i;
9d5c8243
AK		 3490
3491 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3492 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3493 i = tx_ring->next_to_use;
3494 buffer_info = &tx_ring->buffer_info[i];
3495 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3496
3497 if (tx_flags & IGB_TX_FLAGS_VLAN)
3498 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 3499
9d5c8243
AK		 3500 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3501 if (skb->ip_summed == CHECKSUM_PARTIAL)
3502 info |= skb_network_header_len(skb);
3503
3504 context_desc->vlan_macip_lens = cpu_to_le32(info);
3505
3506 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3507
3508 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3509 __be16 protocol;
3510
3511 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3512 const struct vlan_ethhdr *vhdr =
3513 (const struct vlan_ethhdr*)skb->data;
3514
3515 protocol = vhdr->h_vlan_encapsulated_proto;
3516 } else {
3517 protocol = skb->protocol;
3518 }
3519
3520 switch (protocol) {
09640e63 3521 case cpu_to_be16(ETH_P_IP):
9d5c8243 3522 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3523 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3524 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3525 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3526 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3527 break;
09640e63 3528 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3529 /* XXX what about other V6 headers?? */
3530 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3531 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3532 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3533 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3534 break;
3535 default:
3536 if (unlikely(net_ratelimit()))
80785298 3537 dev_warn(&pdev->dev,
44b0cda3
MW		 3538 "partial checksum but proto=%x!\n",
3539 skb->protocol);
3540 break;
3541 }
9d5c8243
AK		 3542 }
3543
3544 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3545 context_desc->seqnum_seed = 0;
85ad76b2 3546 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3547 context_desc->mss_l4len_idx =
85ad76b2 3548 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3549
3550 buffer_info->time_stamp = jiffies;
0e014cb1 3551 buffer_info->next_to_watch = i;
9d5c8243
AK		 3552 buffer_info->dma = 0;
3553
3554 i++;
3555 if (i == tx_ring->count)
3556 i = 0;
3557 tx_ring->next_to_use = i;
3558
3559 return true;
3560 }
9d5c8243
AK		 3561 return false;
3562}
3563
3564#define IGB_MAX_TXD_PWR 16
3565#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3566
80785298 3567static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3568 unsigned int first)
9d5c8243
AK		 3569{
3570 struct igb_buffer *buffer_info;
80785298 3571 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3572 unsigned int len = skb_headlen(skb);
3573 unsigned int count = 0, i;
3574 unsigned int f;
3575
3576 i = tx_ring->next_to_use;
3577
3578 buffer_info = &tx_ring->buffer_info[i];
3579 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3580 buffer_info->length = len;
3581 /* set time_stamp *before* dma to help avoid a possible race */
3582 buffer_info->time_stamp = jiffies;
0e014cb1 3583 buffer_info->next_to_watch = i;
6366ad33
AD		 3584 buffer_info->dma = pci_map_single(pdev, skb->data, len,
3585 PCI_DMA_TODEVICE);
3586 if (pci_dma_mapping_error(pdev, buffer_info->dma))
3587 goto dma_error;
9d5c8243
AK		 3588
3589 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3590 struct skb_frag_struct *frag;
3591
8581145f 3592 count++;
65689fef
AD		 3593 i++;
3594 if (i == tx_ring->count)
3595 i = 0;
3596
9d5c8243
AK		 3597 frag = &skb_shinfo(skb)->frags[f];
3598 len = frag->size;
3599
3600 buffer_info = &tx_ring->buffer_info[i];
3601 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3602 buffer_info->length = len;
3603 buffer_info->time_stamp = jiffies;
0e014cb1 3604 buffer_info->next_to_watch = i;
6366ad33
AD		 3605 buffer_info->mapped_as_page = true;
3606 buffer_info->dma = pci_map_page(pdev,
3607 frag->page,
3608 frag->page_offset,
3609 len,
3610 PCI_DMA_TODEVICE);
3611 if (pci_dma_mapping_error(pdev, buffer_info->dma))
3612 goto dma_error;
3613
9d5c8243
AK		 3614 }
3615
9d5c8243 3616 tx_ring->buffer_info[i].skb = skb;
40e90c26 3617 tx_ring->buffer_info[i].gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
0e014cb1 3618 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3619
cdfd01fc 3620 return ++count;
6366ad33
AD		 3621
3622dma_error:
3623 dev_err(&pdev->dev, "TX DMA map failed\n");
3624
3625 /* clear timestamp and dma mappings for failed buffer_info mapping */
3626 buffer_info->dma = 0;
3627 buffer_info->time_stamp = 0;
3628 buffer_info->length = 0;
3629 buffer_info->next_to_watch = 0;
3630 buffer_info->mapped_as_page = false;
6366ad33
AD		 3631
3632 /* clear timestamp and dma mappings for remaining portion of packet */
a77ff709
NN		 3633 while (count--) {
3634 if (i == 0)
3635 i = tx_ring->count;
6366ad33 3636 i--;
6366ad33
AD		 3637 buffer_info = &tx_ring->buffer_info[i];
3638 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3639 }
3640
3641 return 0;
9d5c8243
AK		 3642}
3643
85ad76b2 3644static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
91d4ee33 3645 u32 tx_flags, int count, u32 paylen,
9d5c8243
AK		 3646 u8 hdr_len)
3647{
cdfd01fc 3648 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 3649 struct igb_buffer *buffer_info;
3650 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 3651 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 3652
3653 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3654 E1000_ADVTXD_DCMD_DEXT);
3655
3656 if (tx_flags & IGB_TX_FLAGS_VLAN)
3657 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3658
33af6bcc
PO		 3659 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3660 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3661
9d5c8243
AK		 3662 if (tx_flags & IGB_TX_FLAGS_TSO) {
3663 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3664
3665 /* insert tcp checksum */
3666 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3667
3668 /* insert ip checksum */
3669 if (tx_flags & IGB_TX_FLAGS_IPV4)
3670 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3671
3672 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3673 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3674 }
3675
85ad76b2
AD		 3676 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
3677 (tx_flags & (IGB_TX_FLAGS_CSUM |
3678 IGB_TX_FLAGS_TSO |
7dfc16fa 3679 IGB_TX_FLAGS_VLAN)))
85ad76b2 3680 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3681
3682 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3683
cdfd01fc 3684 do {
9d5c8243
AK		 3685 buffer_info = &tx_ring->buffer_info[i];
3686 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3687 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3688 tx_desc->read.cmd_type_len =
3689 cpu_to_le32(cmd_type_len | buffer_info->length);
3690 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 3691 count--;
9d5c8243
AK		 3692 i++;
3693 if (i == tx_ring->count)
3694 i = 0;
cdfd01fc 3695 } while (count > 0);
9d5c8243 3696
85ad76b2 3697 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 3698 /* Force memory writes to complete before letting h/w
3699 * know there are new descriptors to fetch. (Only
3700 * applicable for weak-ordered memory model archs,
3701 * such as IA-64). */
3702 wmb();
3703
3704 tx_ring->next_to_use = i;
fce99e34 3705 writel(i, tx_ring->tail);
9d5c8243
AK		 3706 /* we need this if more than one processor can write to our tail
3707 * at a time, it syncronizes IO on IA64/Altix systems */
3708 mmiowb();
3709}
3710
e694e964 3711static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3712{
e694e964
AD		 3713 struct net_device *netdev = tx_ring->netdev;
3714
661086df 3715 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3716
9d5c8243
AK		 3717 /* Herbert's original patch had:
3718 * smp_mb__after_netif_stop_queue();
3719 * but since that doesn't exist yet, just open code it. */
3720 smp_mb();
3721
3722 /* We need to check again in a case another CPU has just
3723 * made room available. */
c493ea45 3724 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3725 return -EBUSY;
3726
3727 /* A reprieve! */
661086df 3728 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 3729 tx_ring->tx_stats.restart_queue++;
9d5c8243
AK		 3730 return 0;
3731}
3732
717ba089 3733static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3734{
c493ea45 3735 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 3736 return 0;
e694e964 3737 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 3738}
3739
b1a436c3
AD		 3740netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3741 struct igb_ring *tx_ring)
9d5c8243 3742{
e694e964 3743 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
cdfd01fc 3744 int tso = 0, count;
91d4ee33
NN		 3745 u32 tx_flags = 0;
3746 u16 first;
3747 u8 hdr_len = 0;
c5b9bd5e 3748 union skb_shared_tx *shtx = skb_tx(skb);
9d5c8243 3749
9d5c8243
AK		 3750 /* need: 1 descriptor per page,
3751 * + 2 desc gap to keep tail from touching head,
3752 * + 1 desc for skb->data,
3753 * + 1 desc for context descriptor,
3754 * otherwise try next time */
e694e964 3755 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 3756 /* this is a hard error */
9d5c8243
AK		 3757 return NETDEV_TX_BUSY;
3758 }
33af6bcc 3759
33af6bcc
PO		 3760 if (unlikely(shtx->hardware)) {
3761 shtx->in_progress = 1;
3762 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3763 }
9d5c8243 3764
cdfd01fc 3765 if (vlan_tx_tag_present(skb) && adapter->vlgrp) {
9d5c8243
AK		 3766 tx_flags |= IGB_TX_FLAGS_VLAN;
3767 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3768 }
3769
661086df
PWJ		 3770 if (skb->protocol == htons(ETH_P_IP))
3771 tx_flags |= IGB_TX_FLAGS_IPV4;
3772
0e014cb1 3773 first = tx_ring->next_to_use;
85ad76b2
AD		 3774 if (skb_is_gso(skb)) {
3775 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 3776
85ad76b2
AD		 3777 if (tso < 0) {
3778 dev_kfree_skb_any(skb);
3779 return NETDEV_TX_OK;
3780 }
9d5c8243
AK		 3781 }
3782
3783 if (tso)
3784 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 3785 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 3786 (skb->ip_summed == CHECKSUM_PARTIAL))
3787 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3788
65689fef 3789 /*
cdfd01fc 3790 * count reflects descriptors mapped, if 0 or less then mapping error
65689fef
AD		 3791 * has occured and we need to rewind the descriptor queue
3792 */
80785298 3793 count = igb_tx_map_adv(tx_ring, skb, first);
6366ad33 3794 if (!count) {
65689fef
AD		 3795 dev_kfree_skb_any(skb);
3796 tx_ring->buffer_info[first].time_stamp = 0;
3797 tx_ring->next_to_use = first;
85ad76b2 3798 return NETDEV_TX_OK;
65689fef 3799 }
9d5c8243 3800
85ad76b2
AD		 3801 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
3802
3803 /* Make sure there is space in the ring for the next send. */
e694e964 3804 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 3805
9d5c8243
AK		 3806 return NETDEV_TX_OK;
3807}
3808
3b29a56d
SH		 3809static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3810 struct net_device *netdev)
9d5c8243
AK		 3811{
3812 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 3813 struct igb_ring *tx_ring;
661086df 3814 int r_idx = 0;
b1a436c3
AD		 3815
3816 if (test_bit(__IGB_DOWN, &adapter->state)) {
3817 dev_kfree_skb_any(skb);
3818 return NETDEV_TX_OK;
3819 }
3820
3821 if (skb->len <= 0) {
3822 dev_kfree_skb_any(skb);
3823 return NETDEV_TX_OK;
3824 }
3825
1bfaf07b 3826 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3827 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3828
3829 /* This goes back to the question of how to logically map a tx queue
3830 * to a flow. Right now, performance is impacted slightly negatively
3831 * if using multiple tx queues. If the stack breaks away from a
3832 * single qdisc implementation, we can look at this again. */
e694e964 3833 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 3834}
3835
3836/**
3837 * igb_tx_timeout - Respond to a Tx Hang
3838 * @netdev: network interface device structure
3839 **/
3840static void igb_tx_timeout(struct net_device *netdev)
3841{
3842 struct igb_adapter *adapter = netdev_priv(netdev);
3843 struct e1000_hw *hw = &adapter->hw;
3844
3845 /* Do the reset outside of interrupt context */
3846 adapter->tx_timeout_count++;
f7ba205e 3847
55cac248
AD		 3848 if (hw->mac.type == e1000_82580)
3849 hw->dev_spec._82575.global_device_reset = true;
3850
9d5c8243 3851 schedule_work(&adapter->reset_task);
265de409
AD		 3852 wr32(E1000_EICS,
3853 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3854}
3855
3856static void igb_reset_task(struct work_struct *work)
3857{
3858 struct igb_adapter *adapter;
3859 adapter = container_of(work, struct igb_adapter, reset_task);
3860
3861 igb_reinit_locked(adapter);
3862}
3863
3864/**
3865 * igb_get_stats - Get System Network Statistics
3866 * @netdev: network interface device structure
3867 *
3868 * Returns the address of the device statistics structure.
3869 * The statistics are actually updated from the timer callback.
3870 **/
73cd78f1 3871static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3872{
9d5c8243 3873 /* only return the current stats */
8d24e933 3874 return &netdev->stats;
9d5c8243
AK		 3875}
3876
3877/**
3878 * igb_change_mtu - Change the Maximum Transfer Unit
3879 * @netdev: network interface device structure
3880 * @new_mtu: new value for maximum frame size
3881 *
3882 * Returns 0 on success, negative on failure
3883 **/
3884static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3885{
3886 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 3887 struct pci_dev *pdev = adapter->pdev;
9d5c8243 3888 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 3889 u32 rx_buffer_len, i;
9d5c8243 3890
c809d227 3891 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 3892 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 3893 return -EINVAL;
3894 }
3895
9d5c8243 3896 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 3897 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 3898 return -EINVAL;
3899 }
3900
3901 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3902 msleep(1);
73cd78f1 3903
9d5c8243
AK		 3904 /* igb_down has a dependency on max_frame_size */
3905 adapter->max_frame_size = max_frame;
559e9c49 3906
9d5c8243
AK		 3907 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3908 * means we reserve 2 more, this pushes us to allocate from the next
3909 * larger slab size.
3910 * i.e. RXBUFFER_2048 --> size-4096 slab
3911 */
3912
7d95b717 3913 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 3914 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3915 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 3916 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 3917 else
4c844851
AD		 3918 rx_buffer_len = IGB_RXBUFFER_128;
3919
3920 if (netif_running(netdev))
3921 igb_down(adapter);
9d5c8243 3922
090b1795 3923 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 3924 netdev->mtu, new_mtu);
3925 netdev->mtu = new_mtu;
3926
4c844851 3927 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3928 adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len;
4c844851 3929
9d5c8243
AK		 3930 if (netif_running(netdev))
3931 igb_up(adapter);
3932 else
3933 igb_reset(adapter);
3934
3935 clear_bit(__IGB_RESETTING, &adapter->state);
3936
3937 return 0;
3938}
3939
3940/**
3941 * igb_update_stats - Update the board statistics counters
3942 * @adapter: board private structure
3943 **/
3944
3945void igb_update_stats(struct igb_adapter *adapter)
3946{
128e45eb 3947 struct net_device_stats *net_stats = igb_get_stats(adapter->netdev);
9d5c8243
AK		 3948 struct e1000_hw *hw = &adapter->hw;
3949 struct pci_dev *pdev = adapter->pdev;
43915c7c 3950 u32 rnbc, reg;
9d5c8243 3951 u16 phy_tmp;
3f9c0164
AD		 3952 int i;
3953 u64 bytes, packets;
9d5c8243
AK		 3954
3955#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3956
3957 /*
3958 * Prevent stats update while adapter is being reset, or if the pci
3959 * connection is down.
3960 */
3961 if (adapter->link_speed == 0)
3962 return;
3963 if (pci_channel_offline(pdev))
3964 return;
3965
3f9c0164
AD		 3966 bytes = 0;
3967 packets = 0;
3968 for (i = 0; i < adapter->num_rx_queues; i++) {
3969 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446
AD		 3970 struct igb_ring *ring = adapter->rx_ring[i];
3971 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 3972 net_stats->rx_fifo_errors += rqdpc_tmp;
3025a446
AD		 3973 bytes += ring->rx_stats.bytes;
3974 packets += ring->rx_stats.packets;
3f9c0164
AD		 3975 }
3976
128e45eb
AD		 3977 net_stats->rx_bytes = bytes;
3978 net_stats->rx_packets = packets;
3f9c0164
AD		 3979
3980 bytes = 0;
3981 packets = 0;
3982 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 3983 struct igb_ring *ring = adapter->tx_ring[i];
3984 bytes += ring->tx_stats.bytes;
3985 packets += ring->tx_stats.packets;
3f9c0164 3986 }
128e45eb
AD		 3987 net_stats->tx_bytes = bytes;
3988 net_stats->tx_packets = packets;
3f9c0164
AD		 3989
3990 /* read stats registers */
9d5c8243
AK		 3991 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3992 adapter->stats.gprc += rd32(E1000_GPRC);
3993 adapter->stats.gorc += rd32(E1000_GORCL);
3994 rd32(E1000_GORCH); /* clear GORCL */
3995 adapter->stats.bprc += rd32(E1000_BPRC);
3996 adapter->stats.mprc += rd32(E1000_MPRC);
3997 adapter->stats.roc += rd32(E1000_ROC);
3998
3999 adapter->stats.prc64 += rd32(E1000_PRC64);
4000 adapter->stats.prc127 += rd32(E1000_PRC127);
4001 adapter->stats.prc255 += rd32(E1000_PRC255);
4002 adapter->stats.prc511 += rd32(E1000_PRC511);
4003 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4004 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4005 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4006 adapter->stats.sec += rd32(E1000_SEC);
4007
4008 adapter->stats.mpc += rd32(E1000_MPC);
4009 adapter->stats.scc += rd32(E1000_SCC);
4010 adapter->stats.ecol += rd32(E1000_ECOL);
4011 adapter->stats.mcc += rd32(E1000_MCC);
4012 adapter->stats.latecol += rd32(E1000_LATECOL);
4013 adapter->stats.dc += rd32(E1000_DC);
4014 adapter->stats.rlec += rd32(E1000_RLEC);
4015 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4016 adapter->stats.xontxc += rd32(E1000_XONTXC);
4017 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4018 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4019 adapter->stats.fcruc += rd32(E1000_FCRUC);
4020 adapter->stats.gptc += rd32(E1000_GPTC);
4021 adapter->stats.gotc += rd32(E1000_GOTCL);
4022 rd32(E1000_GOTCH); /* clear GOTCL */
3f9c0164
AD		 4023 rnbc = rd32(E1000_RNBC);
4024 adapter->stats.rnbc += rnbc;
128e45eb 4025 net_stats->rx_fifo_errors += rnbc;
9d5c8243
AK		 4026 adapter->stats.ruc += rd32(E1000_RUC);
4027 adapter->stats.rfc += rd32(E1000_RFC);
4028 adapter->stats.rjc += rd32(E1000_RJC);
4029 adapter->stats.tor += rd32(E1000_TORH);
4030 adapter->stats.tot += rd32(E1000_TOTH);
4031 adapter->stats.tpr += rd32(E1000_TPR);
4032
4033 adapter->stats.ptc64 += rd32(E1000_PTC64);
4034 adapter->stats.ptc127 += rd32(E1000_PTC127);
4035 adapter->stats.ptc255 += rd32(E1000_PTC255);
4036 adapter->stats.ptc511 += rd32(E1000_PTC511);
4037 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4038 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4039
4040 adapter->stats.mptc += rd32(E1000_MPTC);
4041 adapter->stats.bptc += rd32(E1000_BPTC);
4042
2d0b0f69
NN		 4043 adapter->stats.tpt += rd32(E1000_TPT);
4044 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4045
4046 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4047 /* read internal phy specific stats */
4048 reg = rd32(E1000_CTRL_EXT);
4049 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4050 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4051 adapter->stats.tncrs += rd32(E1000_TNCRS);
4052 }
4053
9d5c8243
AK		 4054 adapter->stats.tsctc += rd32(E1000_TSCTC);
4055 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4056
4057 adapter->stats.iac += rd32(E1000_IAC);
4058 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4059 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4060 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4061 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4062 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4063 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4064 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4065 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4066
4067 /* Fill out the OS statistics structure */
128e45eb
AD		 4068 net_stats->multicast = adapter->stats.mprc;
4069 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4070
4071 /* Rx Errors */
4072
4073 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4074 * our own version based on RUC and ROC */
128e45eb 4075 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4076 adapter->stats.crcerrs + adapter->stats.algnerrc +
4077 adapter->stats.ruc + adapter->stats.roc +
4078 adapter->stats.cexterr;
128e45eb
AD		 4079 net_stats->rx_length_errors = adapter->stats.ruc +
4080 adapter->stats.roc;
4081 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4082 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4083 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4084
4085 /* Tx Errors */
128e45eb
AD		 4086 net_stats->tx_errors = adapter->stats.ecol +
4087 adapter->stats.latecol;
4088 net_stats->tx_aborted_errors = adapter->stats.ecol;
4089 net_stats->tx_window_errors = adapter->stats.latecol;
4090 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4091
4092 /* Tx Dropped needs to be maintained elsewhere */
4093
4094 /* Phy Stats */
4095 if (hw->phy.media_type == e1000_media_type_copper) {
4096 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4097 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4098 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4099 adapter->phy_stats.idle_errors += phy_tmp;
4100 }
4101 }
4102
4103 /* Management Stats */
4104 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4105 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4106 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4107}
4108
9d5c8243
AK		 4109static irqreturn_t igb_msix_other(int irq, void *data)
4110{
047e0030 4111 struct igb_adapter *adapter = data;
9d5c8243 4112 struct e1000_hw *hw = &adapter->hw;
844290e5 4113 u32 icr = rd32(E1000_ICR);
844290e5 4114 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4115
7f081d40
AD		 4116 if (icr & E1000_ICR_DRSTA)
4117 schedule_work(&adapter->reset_task);
4118
047e0030 4119 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4120 /* HW is reporting DMA is out of sync */
4121 adapter->stats.doosync++;
4122 }
eebbbdba 4123
4ae196df
AD		 4124 /* Check for a mailbox event */
4125 if (icr & E1000_ICR_VMMB)
4126 igb_msg_task(adapter);
4127
4128 if (icr & E1000_ICR_LSC) {
4129 hw->mac.get_link_status = 1;
4130 /* guard against interrupt when we're going down */
4131 if (!test_bit(__IGB_DOWN, &adapter->state))
4132 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4133 }
4134
25568a53
AD		 4135 if (adapter->vfs_allocated_count)
4136 wr32(E1000_IMS, E1000_IMS_LSC |
4137 E1000_IMS_VMMB |
4138 E1000_IMS_DOUTSYNC);
4139 else
4140 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4141 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4142
4143 return IRQ_HANDLED;
4144}
4145
047e0030 4146static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4147{
26b39276 4148 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4149 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4150
047e0030
AD		 4151 if (!q_vector->set_itr)
4152 return;
73cd78f1 4153
047e0030
AD		 4154 if (!itr_val)
4155 itr_val = 0x4;
661086df 4156
26b39276
AD		 4157 if (adapter->hw.mac.type == e1000_82575)
4158 itr_val |= itr_val << 16;
661086df 4159 else
047e0030 4160 itr_val |= 0x8000000;
661086df 4161
047e0030
AD		 4162 writel(itr_val, q_vector->itr_register);
4163 q_vector->set_itr = 0;
6eb5a7f1
AD		 4164}
4165
047e0030 4166static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4167{
047e0030 4168 struct igb_q_vector *q_vector = data;
9d5c8243 4169
047e0030
AD		 4170 /* Write the ITR value calculated from the previous interrupt. */
4171 igb_write_itr(q_vector);
9d5c8243 4172
047e0030 4173 napi_schedule(&q_vector->napi);
844290e5 4174
047e0030 4175 return IRQ_HANDLED;
fe4506b6
JC		 4176}
4177
421e02f0 4178#ifdef CONFIG_IGB_DCA
047e0030 4179static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4180{
047e0030 4181 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4182 struct e1000_hw *hw = &adapter->hw;
4183 int cpu = get_cpu();
fe4506b6 4184
047e0030
AD		 4185 if (q_vector->cpu == cpu)
4186 goto out_no_update;
4187
4188 if (q_vector->tx_ring) {
4189 int q = q_vector->tx_ring->reg_idx;
4190 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4191 if (hw->mac.type == e1000_82575) {
4192 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4193 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4194 } else {
047e0030
AD		 4195 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4196 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4197 E1000_DCA_TXCTRL_CPUID_SHIFT;
4198 }
4199 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4200 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4201 }
4202 if (q_vector->rx_ring) {
4203 int q = q_vector->rx_ring->reg_idx;
4204 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4205 if (hw->mac.type == e1000_82575) {
2d064c06 4206 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4207 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4208 } else {
4209 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4210 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4211 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4212 }
fe4506b6
JC		 4213 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4214 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4215 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4216 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4217 }
047e0030
AD		 4218 q_vector->cpu = cpu;
4219out_no_update:
fe4506b6
JC		 4220 put_cpu();
4221}
4222
4223static void igb_setup_dca(struct igb_adapter *adapter)
4224{
7e0e99ef 4225 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4226 int i;
4227
7dfc16fa 4228 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4229 return;
4230
7e0e99ef
AD		 4231 /* Always use CB2 mode, difference is masked in the CB driver. */
4232 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4233
047e0030 4234 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4235 adapter->q_vector[i]->cpu = -1;
4236 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4237 }
4238}
4239
4240static int __igb_notify_dca(struct device *dev, void *data)
4241{
4242 struct net_device *netdev = dev_get_drvdata(dev);
4243 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4244 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4245 struct e1000_hw *hw = &adapter->hw;
4246 unsigned long event = *(unsigned long *)data;
4247
4248 switch (event) {
4249 case DCA_PROVIDER_ADD:
4250 /* if already enabled, don't do it again */
7dfc16fa 4251 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4252 break;
fe4506b6 4253 if (dca_add_requester(dev) == 0) {
bbd98fe4 4254 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4255 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4256 igb_setup_dca(adapter);
4257 break;
4258 }
4259 /* Fall Through since DCA is disabled. */
4260 case DCA_PROVIDER_REMOVE:
7dfc16fa 4261 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4262 /* without this a class_device is left
047e0030 4263 * hanging around in the sysfs model */
fe4506b6 4264 dca_remove_requester(dev);
090b1795 4265 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4266 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4267 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4268 }
4269 break;
4270 }
bbd98fe4 4271
fe4506b6 4272 return 0;
9d5c8243
AK		 4273}
4274
fe4506b6
JC		 4275static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4276 void *p)
4277{
4278 int ret_val;
4279
4280 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4281 __igb_notify_dca);
4282
4283 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4284}
421e02f0 4285#endif /* CONFIG_IGB_DCA */
9d5c8243 4286
4ae196df
AD		 4287static void igb_ping_all_vfs(struct igb_adapter *adapter)
4288{
4289 struct e1000_hw *hw = &adapter->hw;
4290 u32 ping;
4291 int i;
4292
4293 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4294 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4295 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4296 ping |= E1000_VT_MSGTYPE_CTS;
4297 igb_write_mbx(hw, &ping, 1, i);
4298 }
4299}
4300
7d5753f0
AD		 4301static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4302{
4303 struct e1000_hw *hw = &adapter->hw;
4304 u32 vmolr = rd32(E1000_VMOLR(vf));
4305 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4306
4307 vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC |
4308 IGB_VF_FLAG_MULTI_PROMISC);
4309 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4310
4311 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4312 vmolr |= E1000_VMOLR_MPME;
4313 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4314 } else {
4315 /*
4316 * if we have hashes and we are clearing a multicast promisc
4317 * flag we need to write the hashes to the MTA as this step
4318 * was previously skipped
4319 */
4320 if (vf_data->num_vf_mc_hashes > 30) {
4321 vmolr |= E1000_VMOLR_MPME;
4322 } else if (vf_data->num_vf_mc_hashes) {
4323 int j;
4324 vmolr |= E1000_VMOLR_ROMPE;
4325 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4326 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4327 }
4328 }
4329
4330 wr32(E1000_VMOLR(vf), vmolr);
4331
4332 /* there are flags left unprocessed, likely not supported */
4333 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4334 return -EINVAL;
4335
4336 return 0;
4337
4338}
4339
4ae196df
AD		 4340static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4341 u32 *msgbuf, u32 vf)
4342{
4343 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4344 u16 *hash_list = (u16 *)&msgbuf[1];
4345 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4346 int i;
4347
7d5753f0 4348 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4349 * to this VF for later use to restore when the PF multi cast
4350 * list changes
4351 */
4352 vf_data->num_vf_mc_hashes = n;
4353
7d5753f0
AD		 4354 /* only up to 30 hash values supported */
4355 if (n > 30)
4356 n = 30;
4357
4358 /* store the hashes for later use */
4ae196df 4359 for (i = 0; i < n; i++)
a419aef8 4360 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4361
4362 /* Flush and reset the mta with the new values */
ff41f8dc 4363 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4364
4365 return 0;
4366}
4367
4368static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4369{
4370 struct e1000_hw *hw = &adapter->hw;
4371 struct vf_data_storage *vf_data;
4372 int i, j;
4373
4374 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4375 u32 vmolr = rd32(E1000_VMOLR(i));
4376 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4377
4ae196df 4378 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4379
4380 if ((vf_data->num_vf_mc_hashes > 30) ||
4381 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4382 vmolr |= E1000_VMOLR_MPME;
4383 } else if (vf_data->num_vf_mc_hashes) {
4384 vmolr |= E1000_VMOLR_ROMPE;
4385 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4386 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4387 }
4388 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4389 }
4390}
4391
4392static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4393{
4394 struct e1000_hw *hw = &adapter->hw;
4395 u32 pool_mask, reg, vid;
4396 int i;
4397
4398 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4399
4400 /* Find the vlan filter for this id */
4401 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4402 reg = rd32(E1000_VLVF(i));
4403
4404 /* remove the vf from the pool */
4405 reg &= ~pool_mask;
4406
4407 /* if pool is empty then remove entry from vfta */
4408 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4409 (reg & E1000_VLVF_VLANID_ENABLE)) {
4410 reg = 0;
4411 vid = reg & E1000_VLVF_VLANID_MASK;
4412 igb_vfta_set(hw, vid, false);
4413 }
4414
4415 wr32(E1000_VLVF(i), reg);
4416 }
ae641bdc
AD		 4417
4418 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4419}
4420
4421static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4422{
4423 struct e1000_hw *hw = &adapter->hw;
4424 u32 reg, i;
4425
51466239
AD		 4426 /* The vlvf table only exists on 82576 hardware and newer */
4427 if (hw->mac.type < e1000_82576)
4428 return -1;
4429
4430 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 4431 if (!adapter->vfs_allocated_count)
4432 return -1;
4433
4434 /* Find the vlan filter for this id */
4435 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4436 reg = rd32(E1000_VLVF(i));
4437 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4438 vid == (reg & E1000_VLVF_VLANID_MASK))
4439 break;
4440 }
4441
4442 if (add) {
4443 if (i == E1000_VLVF_ARRAY_SIZE) {
4444 /* Did not find a matching VLAN ID entry that was
4445 * enabled. Search for a free filter entry, i.e.
4446 * one without the enable bit set
4447 */
4448 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4449 reg = rd32(E1000_VLVF(i));
4450 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4451 break;
4452 }
4453 }
4454 if (i < E1000_VLVF_ARRAY_SIZE) {
4455 /* Found an enabled/available entry */
4456 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4457
4458 /* if !enabled we need to set this up in vfta */
4459 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 4460 /* add VID to filter table */
4461 igb_vfta_set(hw, vid, true);
4ae196df
AD		 4462 reg |= E1000_VLVF_VLANID_ENABLE;
4463 }
cad6d05f
AD		 4464 reg &= ~E1000_VLVF_VLANID_MASK;
4465 reg |= vid;
4ae196df 4466 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4467
4468 /* do not modify RLPML for PF devices */
4469 if (vf >= adapter->vfs_allocated_count)
4470 return 0;
4471
4472 if (!adapter->vf_data[vf].vlans_enabled) {
4473 u32 size;
4474 reg = rd32(E1000_VMOLR(vf));
4475 size = reg & E1000_VMOLR_RLPML_MASK;
4476 size += 4;
4477 reg &= ~E1000_VMOLR_RLPML_MASK;
4478 reg |= size;
4479 wr32(E1000_VMOLR(vf), reg);
4480 }
ae641bdc 4481
51466239 4482 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 4483 return 0;
4484 }
4485 } else {
4486 if (i < E1000_VLVF_ARRAY_SIZE) {
4487 /* remove vf from the pool */
4488 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4489 /* if pool is empty then remove entry from vfta */
4490 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4491 reg = 0;
4492 igb_vfta_set(hw, vid, false);
4493 }
4494 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4495
4496 /* do not modify RLPML for PF devices */
4497 if (vf >= adapter->vfs_allocated_count)
4498 return 0;
4499
4500 adapter->vf_data[vf].vlans_enabled--;
4501 if (!adapter->vf_data[vf].vlans_enabled) {
4502 u32 size;
4503 reg = rd32(E1000_VMOLR(vf));
4504 size = reg & E1000_VMOLR_RLPML_MASK;
4505 size -= 4;
4506 reg &= ~E1000_VMOLR_RLPML_MASK;
4507 reg |= size;
4508 wr32(E1000_VMOLR(vf), reg);
4509 }
4ae196df
AD		 4510 }
4511 }
8151d294
WM		 4512 return 0;
4513}
4514
4515static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4516{
4517 struct e1000_hw *hw = &adapter->hw;
4518
4519 if (vid)
4520 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
4521 else
4522 wr32(E1000_VMVIR(vf), 0);
4523}
4524
4525static int igb_ndo_set_vf_vlan(struct net_device *netdev,
4526 int vf, u16 vlan, u8 qos)
4527{
4528 int err = 0;
4529 struct igb_adapter *adapter = netdev_priv(netdev);
4530
4531 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
4532 return -EINVAL;
4533 if (vlan || qos) {
4534 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
4535 if (err)
4536 goto out;
4537 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
4538 igb_set_vmolr(adapter, vf, !vlan);
4539 adapter->vf_data[vf].pf_vlan = vlan;
4540 adapter->vf_data[vf].pf_qos = qos;
4541 dev_info(&adapter->pdev->dev,
4542 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
4543 if (test_bit(__IGB_DOWN, &adapter->state)) {
4544 dev_warn(&adapter->pdev->dev,
4545 "The VF VLAN has been set,"
4546 " but the PF device is not up.\n");
4547 dev_warn(&adapter->pdev->dev,
4548 "Bring the PF device up before"
4549 " attempting to use the VF device.\n");
4550 }
4551 } else {
4552 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
4553 false, vf);
4554 igb_set_vmvir(adapter, vlan, vf);
4555 igb_set_vmolr(adapter, vf, true);
4556 adapter->vf_data[vf].pf_vlan = 0;
4557 adapter->vf_data[vf].pf_qos = 0;
4558 }
4559out:
4560 return err;
4ae196df
AD		 4561}
4562
4563static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4564{
4565 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4566 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4567
4568 return igb_vlvf_set(adapter, vid, add, vf);
4569}
4570
f2ca0dbe 4571static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 4572{
8151d294
WM		 4573 /* clear flags */
4574 adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC);
f2ca0dbe 4575 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 4576
4577 /* reset offloads to defaults */
8151d294 4578 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 4579
4580 /* reset vlans for device */
4581 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 4582 if (adapter->vf_data[vf].pf_vlan)
4583 igb_ndo_set_vf_vlan(adapter->netdev, vf,
4584 adapter->vf_data[vf].pf_vlan,
4585 adapter->vf_data[vf].pf_qos);
4586 else
4587 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 4588
4589 /* reset multicast table array for vf */
4590 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4591
4592 /* Flush and reset the mta with the new values */
ff41f8dc 4593 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4594}
4595
f2ca0dbe
AD		 4596static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4597{
4598 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4599
4600 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 4601 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
4602 random_ether_addr(vf_mac);
f2ca0dbe
AD		 4603
4604 /* process remaining reset events */
4605 igb_vf_reset(adapter, vf);
4606}
4607
4608static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 4609{
4610 struct e1000_hw *hw = &adapter->hw;
4611 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4612 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4613 u32 reg, msgbuf[3];
4614 u8 *addr = (u8 *)(&msgbuf[1]);
4615
4616 /* process all the same items cleared in a function level reset */
f2ca0dbe 4617 igb_vf_reset(adapter, vf);
4ae196df
AD		 4618
4619 /* set vf mac address */
26ad9178 4620 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4621
4622 /* enable transmit and receive for vf */
4623 reg = rd32(E1000_VFTE);
4624 wr32(E1000_VFTE, reg | (1 << vf));
4625 reg = rd32(E1000_VFRE);
4626 wr32(E1000_VFRE, reg | (1 << vf));
4627
f2ca0dbe 4628 adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
4ae196df
AD		 4629
4630 /* reply to reset with ack and vf mac address */
4631 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4632 memcpy(addr, vf_mac, 6);
4633 igb_write_mbx(hw, msgbuf, 3, vf);
4634}
4635
4636static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4637{
f2ca0dbe
AD		 4638 unsigned char *addr = (char *)&msg[1];
4639 int err = -1;
4ae196df 4640
f2ca0dbe
AD		 4641 if (is_valid_ether_addr(addr))
4642 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 4643
f2ca0dbe 4644 return err;
4ae196df
AD		 4645}
4646
4647static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4648{
4649 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4650 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4651 u32 msg = E1000_VT_MSGTYPE_NACK;
4652
4653 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 4654 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
4655 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 4656 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 4657 vf_data->last_nack = jiffies;
4ae196df
AD		 4658 }
4659}
4660
f2ca0dbe 4661static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 4662{
f2ca0dbe
AD		 4663 struct pci_dev *pdev = adapter->pdev;
4664 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 4665 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4666 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4667 s32 retval;
4668
f2ca0dbe 4669 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 4670
fef45f4c
AD		 4671 if (retval) {
4672 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 4673 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 4674 vf_data->flags &= ~IGB_VF_FLAG_CTS;
4675 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
4676 return;
4677 goto out;
4678 }
4ae196df
AD		 4679
4680 /* this is a message we already processed, do nothing */
4681 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 4682 return;
4ae196df
AD		 4683
4684 /*
4685 * until the vf completes a reset it should not be
4686 * allowed to start any configuration.
4687 */
4688
4689 if (msgbuf[0] == E1000_VF_RESET) {
4690 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 4691 return;
4ae196df
AD		 4692 }
4693
f2ca0dbe 4694 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 4695 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
4696 return;
4697 retval = -1;
4698 goto out;
4ae196df
AD		 4699 }
4700
4701 switch ((msgbuf[0] & 0xFFFF)) {
4702 case E1000_VF_SET_MAC_ADDR:
4703 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4704 break;
7d5753f0
AD		 4705 case E1000_VF_SET_PROMISC:
4706 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
4707 break;
4ae196df
AD		 4708 case E1000_VF_SET_MULTICAST:
4709 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4710 break;
4711 case E1000_VF_SET_LPE:
4712 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4713 break;
4714 case E1000_VF_SET_VLAN:
8151d294
WM		 4715 if (adapter->vf_data[vf].pf_vlan)
4716 retval = -1;
4717 else
4718 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 4719 break;
4720 default:
090b1795 4721 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 4722 retval = -1;
4723 break;
4724 }
4725
fef45f4c
AD		 4726 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4727out:
4ae196df
AD		 4728 /* notify the VF of the results of what it sent us */
4729 if (retval)
4730 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4731 else
4732 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4733
4ae196df 4734 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 4735}
4ae196df 4736
f2ca0dbe
AD		 4737static void igb_msg_task(struct igb_adapter *adapter)
4738{
4739 struct e1000_hw *hw = &adapter->hw;
4740 u32 vf;
4741
4742 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4743 /* process any reset requests */
4744 if (!igb_check_for_rst(hw, vf))
4745 igb_vf_reset_event(adapter, vf);
4746
4747 /* process any messages pending */
4748 if (!igb_check_for_msg(hw, vf))
4749 igb_rcv_msg_from_vf(adapter, vf);
4750
4751 /* process any acks */
4752 if (!igb_check_for_ack(hw, vf))
4753 igb_rcv_ack_from_vf(adapter, vf);
4754 }
4ae196df
AD		 4755}
4756
68d480c4
AD		 4757/**
4758 * igb_set_uta - Set unicast filter table address
4759 * @adapter: board private structure
4760 *
4761 * The unicast table address is a register array of 32-bit registers.
4762 * The table is meant to be used in a way similar to how the MTA is used
4763 * however due to certain limitations in the hardware it is necessary to
4764 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4765 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4766 **/
4767static void igb_set_uta(struct igb_adapter *adapter)
4768{
4769 struct e1000_hw *hw = &adapter->hw;
4770 int i;
4771
4772 /* The UTA table only exists on 82576 hardware and newer */
4773 if (hw->mac.type < e1000_82576)
4774 return;
4775
4776 /* we only need to do this if VMDq is enabled */
4777 if (!adapter->vfs_allocated_count)
4778 return;
4779
4780 for (i = 0; i < hw->mac.uta_reg_count; i++)
4781 array_wr32(E1000_UTA, i, ~0);
4782}
4783
9d5c8243
AK		 4784/**
4785 * igb_intr_msi - Interrupt Handler
4786 * @irq: interrupt number
4787 * @data: pointer to a network interface device structure
4788 **/
4789static irqreturn_t igb_intr_msi(int irq, void *data)
4790{
047e0030
AD		 4791 struct igb_adapter *adapter = data;
4792 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4793 struct e1000_hw *hw = &adapter->hw;
4794 /* read ICR disables interrupts using IAM */
4795 u32 icr = rd32(E1000_ICR);
4796
047e0030 4797 igb_write_itr(q_vector);
9d5c8243 4798
7f081d40
AD		 4799 if (icr & E1000_ICR_DRSTA)
4800 schedule_work(&adapter->reset_task);
4801
047e0030 4802 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4803 /* HW is reporting DMA is out of sync */
4804 adapter->stats.doosync++;
4805 }
4806
9d5c8243
AK		 4807 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4808 hw->mac.get_link_status = 1;
4809 if (!test_bit(__IGB_DOWN, &adapter->state))
4810 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4811 }
4812
047e0030 4813 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4814
4815 return IRQ_HANDLED;
4816}
4817
4818/**
4a3c6433 4819 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4820 * @irq: interrupt number
4821 * @data: pointer to a network interface device structure
4822 **/
4823static irqreturn_t igb_intr(int irq, void *data)
4824{
047e0030
AD		 4825 struct igb_adapter *adapter = data;
4826 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4827 struct e1000_hw *hw = &adapter->hw;
4828 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4829 * need for the IMC write */
4830 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4831 if (!icr)
4832 return IRQ_NONE; /* Not our interrupt */
4833
047e0030 4834 igb_write_itr(q_vector);
9d5c8243
AK		 4835
4836 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4837 * not set, then the adapter didn't send an interrupt */
4838 if (!(icr & E1000_ICR_INT_ASSERTED))
4839 return IRQ_NONE;
4840
7f081d40
AD		 4841 if (icr & E1000_ICR_DRSTA)
4842 schedule_work(&adapter->reset_task);
4843
047e0030 4844 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4845 /* HW is reporting DMA is out of sync */
4846 adapter->stats.doosync++;
4847 }
4848
9d5c8243
AK		 4849 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4850 hw->mac.get_link_status = 1;
4851 /* guard against interrupt when we're going down */
4852 if (!test_bit(__IGB_DOWN, &adapter->state))
4853 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4854 }
4855
047e0030 4856 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4857
4858 return IRQ_HANDLED;
4859}
4860
047e0030 4861static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4862{
047e0030 4863 struct igb_adapter *adapter = q_vector->adapter;
46544258 4864 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4865
4fc82adf
AD		 4866 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
4867 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 4868 if (!adapter->msix_entries)
6eb5a7f1 4869 igb_set_itr(adapter);
46544258 4870 else
047e0030 4871 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4872 }
4873
46544258
AD		 4874 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4875 if (adapter->msix_entries)
047e0030 4876 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4877 else
4878 igb_irq_enable(adapter);
4879 }
9d5c8243
AK		 4880}
4881
46544258
AD		 4882/**
4883 * igb_poll - NAPI Rx polling callback
4884 * @napi: napi polling structure
4885 * @budget: count of how many packets we should handle
4886 **/
4887static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4888{
047e0030
AD		 4889 struct igb_q_vector *q_vector = container_of(napi,
4890 struct igb_q_vector,
4891 napi);
4892 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4893
421e02f0 4894#ifdef CONFIG_IGB_DCA
047e0030
AD		 4895 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4896 igb_update_dca(q_vector);
fe4506b6 4897#endif
047e0030
AD		 4898 if (q_vector->tx_ring)
4899 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4900
047e0030
AD		 4901 if (q_vector->rx_ring)
4902 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4903
4904 if (!tx_clean_complete)
4905 work_done = budget;
46544258 4906
9d5c8243 4907 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4908 if (work_done < budget) {
288379f0 4909 napi_complete(napi);
047e0030 4910 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4911 }
4912
46544258 4913 return work_done;
9d5c8243 4914}
6d8126f9 4915
33af6bcc 4916/**
c5b9bd5e 4917 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 4918 * @adapter: board private structure
c5b9bd5e
AD		 4919 * @shhwtstamps: timestamp structure to update
4920 * @regval: unsigned 64bit system time value.
4921 *
4922 * We need to convert the system time value stored in the RX/TXSTMP registers
4923 * into a hwtstamp which can be used by the upper level timestamping functions
4924 */
4925static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
4926 struct skb_shared_hwtstamps *shhwtstamps,
4927 u64 regval)
4928{
4929 u64 ns;
4930
55cac248
AD		 4931 /*
4932 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
4933 * 24 to match clock shift we setup earlier.
4934 */
4935 if (adapter->hw.mac.type == e1000_82580)
4936 regval <<= IGB_82580_TSYNC_SHIFT;
4937
c5b9bd5e
AD		 4938 ns = timecounter_cyc2time(&adapter->clock, regval);
4939 timecompare_update(&adapter->compare, ns);
4940 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
4941 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4942 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
4943}
4944
4945/**
4946 * igb_tx_hwtstamp - utility function which checks for TX time stamp
4947 * @q_vector: pointer to q_vector containing needed info
33af6bcc
PO		 4948 * @skb: packet that was just sent
4949 *
4950 * If we were asked to do hardware stamping and such a time stamp is
4951 * available, then it must have been for this skb here because we only
4952 * allow only one such packet into the queue.
4953 */
c5b9bd5e 4954static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
33af6bcc 4955{
c5b9bd5e 4956 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc
PO		 4957 union skb_shared_tx *shtx = skb_tx(skb);
4958 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 4959 struct skb_shared_hwtstamps shhwtstamps;
4960 u64 regval;
33af6bcc 4961
c5b9bd5e
AD		 4962 /* if skb does not support hw timestamp or TX stamp not valid exit */
4963 if (likely(!shtx->hardware) ||
4964 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
4965 return;
4966
4967 regval = rd32(E1000_TXSTMPL);
4968 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4969
4970 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
4971 skb_tstamp_tx(skb, &shhwtstamps);
33af6bcc
PO		 4972}
4973
9d5c8243
AK		 4974/**
4975 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4976 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4977 * returns true if ring is completely cleaned
4978 **/
047e0030 4979static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4980{
047e0030
AD		 4981 struct igb_adapter *adapter = q_vector->adapter;
4982 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 4983 struct net_device *netdev = tx_ring->netdev;
0e014cb1 4984 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4985 struct igb_buffer *buffer_info;
4986 struct sk_buff *skb;
0e014cb1 4987 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4988 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4989 unsigned int i, eop, count = 0;
4990 bool cleaned = false;
9d5c8243 4991
9d5c8243 4992 i = tx_ring->next_to_clean;
0e014cb1
AD		 4993 eop = tx_ring->buffer_info[i].next_to_watch;
4994 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4995
4996 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4997 (count < tx_ring->count)) {
4998 for (cleaned = false; !cleaned; count++) {
4999 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 5000 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 5001 cleaned = (i == eop);
9d5c8243
AK		 5002 skb = buffer_info->skb;
5003
5004 if (skb) {
5005 unsigned int segs, bytecount;
5006 /* gso_segs is currently only valid for tcp */
40e90c26 5007 segs = buffer_info->gso_segs;
9d5c8243
AK		 5008 /* multiply data chunks by size of headers */
5009 bytecount = ((segs - 1) * skb_headlen(skb)) +
5010 skb->len;
5011 total_packets += segs;
5012 total_bytes += bytecount;
33af6bcc 5013
c5b9bd5e 5014 igb_tx_hwtstamp(q_vector, skb);
9d5c8243
AK		 5015 }
5016
80785298 5017 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5018 tx_desc->wb.status = 0;
9d5c8243
AK		 5019
5020 i++;
5021 if (i == tx_ring->count)
5022 i = 0;
9d5c8243 5023 }
0e014cb1
AD		 5024 eop = tx_ring->buffer_info[i].next_to_watch;
5025 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5026 }
5027
9d5c8243
AK		 5028 tx_ring->next_to_clean = i;
5029
fc7d345d 5030 if (unlikely(count &&
9d5c8243 5031 netif_carrier_ok(netdev) &&
c493ea45 5032 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5033 /* Make sure that anybody stopping the queue after this
5034 * sees the new next_to_clean.
5035 */
5036 smp_mb();
661086df
PWJ		 5037 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5038 !(test_bit(__IGB_DOWN, &adapter->state))) {
5039 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 5040 tx_ring->tx_stats.restart_queue++;
661086df 5041 }
9d5c8243
AK		 5042 }
5043
5044 if (tx_ring->detect_tx_hung) {
5045 /* Detect a transmit hang in hardware, this serializes the
5046 * check with the clearing of time_stamp and movement of i */
5047 tx_ring->detect_tx_hung = false;
5048 if (tx_ring->buffer_info[i].time_stamp &&
5049 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5050 (adapter->tx_timeout_factor * HZ)) &&
5051 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5052
9d5c8243 5053 /* detected Tx unit hang */
80785298 5054 dev_err(&tx_ring->pdev->dev,
9d5c8243 5055 "Detected Tx Unit Hang\n"
2d064c06 5056 " Tx Queue <%d>\n"
9d5c8243
AK		 5057 " TDH <%x>\n"
5058 " TDT <%x>\n"
5059 " next_to_use <%x>\n"
5060 " next_to_clean <%x>\n"
9d5c8243
AK		 5061 "buffer_info[next_to_clean]\n"
5062 " time_stamp <%lx>\n"
0e014cb1 5063 " next_to_watch <%x>\n"
9d5c8243
AK		 5064 " jiffies <%lx>\n"
5065 " desc.status <%x>\n",
2d064c06 5066 tx_ring->queue_index,
fce99e34
AD		 5067 readl(tx_ring->head),
5068 readl(tx_ring->tail),
9d5c8243
AK		 5069 tx_ring->next_to_use,
5070 tx_ring->next_to_clean,
f7ba205e 5071 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5072 eop,
9d5c8243 5073 jiffies,
0e014cb1 5074 eop_desc->wb.status);
661086df 5075 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5076 }
5077 }
5078 tx_ring->total_bytes += total_bytes;
5079 tx_ring->total_packets += total_packets;
e21ed353
AD		 5080 tx_ring->tx_stats.bytes += total_bytes;
5081 tx_ring->tx_stats.packets += total_packets;
0e014cb1 5082 return (count < tx_ring->count);
9d5c8243
AK		 5083}
5084
9d5c8243
AK		 5085/**
5086 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 5087 * @q_vector: structure containing interrupt and ring information
5088 * @skb: packet to send up
5089 * @vlan_tag: vlan tag for packet
9d5c8243 5090 **/
047e0030
AD		 5091static void igb_receive_skb(struct igb_q_vector *q_vector,
5092 struct sk_buff *skb,
5093 u16 vlan_tag)
5094{
5095 struct igb_adapter *adapter = q_vector->adapter;
5096
5097 if (vlan_tag)
5098 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
5099 vlan_tag, skb);
182ff8df 5100 else
047e0030 5101 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 5102}
5103
04a5fcaa 5104static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 5105 u32 status_err, struct sk_buff *skb)
5106{
5107 skb->ip_summed = CHECKSUM_NONE;
5108
5109 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5110 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5111 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5112 return;
85ad76b2 5113
9d5c8243
AK		 5114 /* TCP/UDP checksum error bit is set */
5115 if (status_err &
5116 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5117 /*
5118 * work around errata with sctp packets where the TCPE aka
5119 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5120 * packets, (aka let the stack check the crc32c)
5121 */
85ad76b2
AD		 5122 if ((skb->len == 60) &&
5123 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
04a5fcaa 5124 ring->rx_stats.csum_err++;
85ad76b2 5125
9d5c8243 5126 /* let the stack verify checksum errors */
9d5c8243
AK		 5127 return;
5128 }
5129 /* It must be a TCP or UDP packet with a valid checksum */
5130 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5131 skb->ip_summed = CHECKSUM_UNNECESSARY;
5132
85ad76b2 5133 dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5134}
5135
c5b9bd5e
AD		 5136static inline void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
5137 struct sk_buff *skb)
5138{
5139 struct igb_adapter *adapter = q_vector->adapter;
5140 struct e1000_hw *hw = &adapter->hw;
5141 u64 regval;
5142
5143 /*
5144 * If this bit is set, then the RX registers contain the time stamp. No
5145 * other packet will be time stamped until we read these registers, so
5146 * read the registers to make them available again. Because only one
5147 * packet can be time stamped at a time, we know that the register
5148 * values must belong to this one here and therefore we don't need to
5149 * compare any of the additional attributes stored for it.
5150 *
5151 * If nothing went wrong, then it should have a skb_shared_tx that we
5152 * can turn into a skb_shared_hwtstamps.
5153 */
5154 if (likely(!(staterr & E1000_RXDADV_STAT_TS)))
5155 return;
5156 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5157 return;
5158
5159 regval = rd32(E1000_RXSTMPL);
5160 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5161
5162 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5163}
4c844851 5164static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 5165 union e1000_adv_rx_desc *rx_desc)
5166{
5167 /* HW will not DMA in data larger than the given buffer, even if it
5168 * parses the (NFS, of course) header to be larger. In that case, it
5169 * fills the header buffer and spills the rest into the page.
5170 */
5171 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5172 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 5173 if (hlen > rx_ring->rx_buffer_len)
5174 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 5175 return hlen;
5176}
5177
047e0030
AD		 5178static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5179 int *work_done, int budget)
9d5c8243 5180{
047e0030 5181 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 5182 struct net_device *netdev = rx_ring->netdev;
80785298 5183 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 5184 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5185 struct igb_buffer *buffer_info , *next_buffer;
5186 struct sk_buff *skb;
9d5c8243
AK		 5187 bool cleaned = false;
5188 int cleaned_count = 0;
d1eff350 5189 int current_node = numa_node_id();
9d5c8243 5190 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 5191 unsigned int i;
2d94d8ab
AD		 5192 u32 staterr;
5193 u16 length;
047e0030 5194 u16 vlan_tag;
9d5c8243
AK		 5195
5196 i = rx_ring->next_to_clean;
69d3ca53 5197 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 5198 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5199 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5200
5201 while (staterr & E1000_RXD_STAT_DD) {
5202 if (*work_done >= budget)
5203 break;
5204 (*work_done)++;
9d5c8243 5205
69d3ca53
AD		 5206 skb = buffer_info->skb;
5207 prefetch(skb->data - NET_IP_ALIGN);
5208 buffer_info->skb = NULL;
5209
5210 i++;
5211 if (i == rx_ring->count)
5212 i = 0;
42d0781a 5213
69d3ca53
AD		 5214 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5215 prefetch(next_rxd);
5216 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 5217
5218 length = le16_to_cpu(rx_desc->wb.upper.length);
5219 cleaned = true;
5220 cleaned_count++;
5221
2d94d8ab 5222 if (buffer_info->dma) {
bf36c1a0 5223 pci_unmap_single(pdev, buffer_info->dma,
4c844851 5224 rx_ring->rx_buffer_len,
bf36c1a0 5225 PCI_DMA_FROMDEVICE);
91615f76 5226 buffer_info->dma = 0;
4c844851 5227 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 5228 skb_put(skb, length);
5229 goto send_up;
5230 }
4c844851 5231 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 5232 }
5233
5234 if (length) {
9d5c8243 5235 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 5236 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 5237 buffer_info->page_dma = 0;
bf36c1a0
AD		 5238
5239 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
5240 buffer_info->page,
5241 buffer_info->page_offset,
5242 length);
5243
d1eff350
AD		 5244 if ((page_count(buffer_info->page) != 1) ||
5245 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5246 buffer_info->page = NULL;
5247 else
5248 get_page(buffer_info->page);
9d5c8243
AK		 5249
5250 skb->len += length;
5251 skb->data_len += length;
bf36c1a0 5252 skb->truesize += length;
9d5c8243 5253 }
9d5c8243 5254
bf36c1a0 5255 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 5256 buffer_info->skb = next_buffer->skb;
5257 buffer_info->dma = next_buffer->dma;
5258 next_buffer->skb = skb;
5259 next_buffer->dma = 0;
bf36c1a0
AD		 5260 goto next_desc;
5261 }
69d3ca53 5262send_up:
9d5c8243
AK		 5263 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5264 dev_kfree_skb_irq(skb);
5265 goto next_desc;
5266 }
9d5c8243 5267
c5b9bd5e 5268 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5269 total_bytes += skb->len;
5270 total_packets++;
5271
85ad76b2 5272 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5273
5274 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5275 skb_record_rx_queue(skb, rx_ring->queue_index);
5276
5277 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5278 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5279
047e0030 5280 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5281
9d5c8243
AK		 5282next_desc:
5283 rx_desc->wb.upper.status_error = 0;
5284
5285 /* return some buffers to hardware, one at a time is too slow */
5286 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5287 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5288 cleaned_count = 0;
5289 }
5290
5291 /* use prefetched values */
5292 rx_desc = next_rxd;
5293 buffer_info = next_buffer;
9d5c8243
AK		 5294 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5295 }
bf36c1a0 5296
9d5c8243 5297 rx_ring->next_to_clean = i;
c493ea45 5298 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5299
5300 if (cleaned_count)
3b644cf6 5301 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5302
5303 rx_ring->total_packets += total_packets;
5304 rx_ring->total_bytes += total_bytes;
5305 rx_ring->rx_stats.packets += total_packets;
5306 rx_ring->rx_stats.bytes += total_bytes;
9d5c8243
AK		 5307 return cleaned;
5308}
5309
9d5c8243
AK		 5310/**
5311 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5312 * @adapter: address of board private structure
5313 **/
d7ee5b3a 5314void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5315{
e694e964 5316 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5317 union e1000_adv_rx_desc *rx_desc;
5318 struct igb_buffer *buffer_info;
5319 struct sk_buff *skb;
5320 unsigned int i;
db761762 5321 int bufsz;
9d5c8243
AK		 5322
5323 i = rx_ring->next_to_use;
5324 buffer_info = &rx_ring->buffer_info[i];
5325
4c844851 5326 bufsz = rx_ring->rx_buffer_len;
db761762 5327
9d5c8243
AK		 5328 while (cleaned_count--) {
5329 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5330
6ec43fe6 5331 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5332 if (!buffer_info->page) {
42d0781a 5333 buffer_info->page = netdev_alloc_page(netdev);
bf36c1a0 5334 if (!buffer_info->page) {
04a5fcaa 5335 rx_ring->rx_stats.alloc_failed++;
bf36c1a0
AD		 5336 goto no_buffers;
5337 }
5338 buffer_info->page_offset = 0;
5339 } else {
5340 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5341 }
5342 buffer_info->page_dma =
80785298 5343 pci_map_page(rx_ring->pdev, buffer_info->page,
bf36c1a0
AD		 5344 buffer_info->page_offset,
5345 PAGE_SIZE / 2,
9d5c8243 5346 PCI_DMA_FROMDEVICE);
42d0781a
AD		 5347 if (pci_dma_mapping_error(rx_ring->pdev,
5348 buffer_info->page_dma)) {
5349 buffer_info->page_dma = 0;
5350 rx_ring->rx_stats.alloc_failed++;
5351 goto no_buffers;
5352 }
9d5c8243
AK		 5353 }
5354
42d0781a
AD		 5355 skb = buffer_info->skb;
5356 if (!skb) {
89d71a66 5357 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243 5358 if (!skb) {
04a5fcaa 5359 rx_ring->rx_stats.alloc_failed++;
9d5c8243
AK		 5360 goto no_buffers;
5361 }
5362
9d5c8243 5363 buffer_info->skb = skb;
42d0781a
AD		 5364 }
5365 if (!buffer_info->dma) {
80785298
AD		 5366 buffer_info->dma = pci_map_single(rx_ring->pdev,
5367 skb->data,
9d5c8243
AK		 5368 bufsz,
5369 PCI_DMA_FROMDEVICE);
42d0781a
AD		 5370 if (pci_dma_mapping_error(rx_ring->pdev,
5371 buffer_info->dma)) {
5372 buffer_info->dma = 0;
5373 rx_ring->rx_stats.alloc_failed++;
5374 goto no_buffers;
5375 }
9d5c8243
AK		 5376 }
5377 /* Refresh the desc even if buffer_addrs didn't change because
5378 * each write-back erases this info. */
6ec43fe6 5379 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5380 rx_desc->read.pkt_addr =
5381 cpu_to_le64(buffer_info->page_dma);
5382 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5383 } else {
42d0781a 5384 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 5385 rx_desc->read.hdr_addr = 0;
5386 }
5387
5388 i++;
5389 if (i == rx_ring->count)
5390 i = 0;
5391 buffer_info = &rx_ring->buffer_info[i];
5392 }
5393
5394no_buffers:
5395 if (rx_ring->next_to_use != i) {
5396 rx_ring->next_to_use = i;
5397 if (i == 0)
5398 i = (rx_ring->count - 1);
5399 else
5400 i--;
5401
5402 /* Force memory writes to complete before letting h/w
5403 * know there are new descriptors to fetch. (Only
5404 * applicable for weak-ordered memory model archs,
5405 * such as IA-64). */
5406 wmb();
fce99e34 5407 writel(i, rx_ring->tail);
9d5c8243
AK		 5408 }
5409}
5410
5411/**
5412 * igb_mii_ioctl -
5413 * @netdev:
5414 * @ifreq:
5415 * @cmd:
5416 **/
5417static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5418{
5419 struct igb_adapter *adapter = netdev_priv(netdev);
5420 struct mii_ioctl_data *data = if_mii(ifr);
5421
5422 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5423 return -EOPNOTSUPP;
5424
5425 switch (cmd) {
5426 case SIOCGMIIPHY:
5427 data->phy_id = adapter->hw.phy.addr;
5428 break;
5429 case SIOCGMIIREG:
f5f4cf08
AD		 5430 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5431 &data->val_out))
9d5c8243
AK		 5432 return -EIO;
5433 break;
5434 case SIOCSMIIREG:
5435 default:
5436 return -EOPNOTSUPP;
5437 }
5438 return 0;
5439}
5440
c6cb090b
PO		 5441/**
5442 * igb_hwtstamp_ioctl - control hardware time stamping
5443 * @netdev:
5444 * @ifreq:
5445 * @cmd:
5446 *
33af6bcc
PO		 5447 * Outgoing time stamping can be enabled and disabled. Play nice and
5448 * disable it when requested, although it shouldn't case any overhead
5449 * when no packet needs it. At most one packet in the queue may be
5450 * marked for time stamping, otherwise it would be impossible to tell
5451 * for sure to which packet the hardware time stamp belongs.
5452 *
5453 * Incoming time stamping has to be configured via the hardware
5454 * filters. Not all combinations are supported, in particular event
5455 * type has to be specified. Matching the kind of event packet is
5456 * not supported, with the exception of "all V2 events regardless of
5457 * level 2 or 4".
5458 *
c6cb090b
PO		 5459 **/
5460static int igb_hwtstamp_ioctl(struct net_device *netdev,
5461 struct ifreq *ifr, int cmd)
5462{
33af6bcc
PO		 5463 struct igb_adapter *adapter = netdev_priv(netdev);
5464 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5465 struct hwtstamp_config config;
c5b9bd5e
AD		 5466 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
5467 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 5468 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 5469 bool is_l4 = false;
5470 bool is_l2 = false;
33af6bcc 5471 u32 regval;
c6cb090b
PO		 5472
5473 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5474 return -EFAULT;
5475
5476 /* reserved for future extensions */
5477 if (config.flags)
5478 return -EINVAL;
5479
33af6bcc
PO		 5480 switch (config.tx_type) {
5481 case HWTSTAMP_TX_OFF:
c5b9bd5e 5482 tsync_tx_ctl = 0;
33af6bcc 5483 case HWTSTAMP_TX_ON:
33af6bcc
PO		 5484 break;
5485 default:
5486 return -ERANGE;
5487 }
5488
5489 switch (config.rx_filter) {
5490 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 5491 tsync_rx_ctl = 0;
33af6bcc
PO		 5492 break;
5493 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5494 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5495 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5496 case HWTSTAMP_FILTER_ALL:
5497 /*
5498 * register TSYNCRXCFG must be set, therefore it is not
5499 * possible to time stamp both Sync and Delay_Req messages
5500 * => fall back to time stamping all packets
5501 */
c5b9bd5e 5502 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 5503 config.rx_filter = HWTSTAMP_FILTER_ALL;
5504 break;
5505 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 5506 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5507 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 5508 is_l4 = true;
33af6bcc
PO		 5509 break;
5510 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 5511 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5512 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 5513 is_l4 = true;
33af6bcc
PO		 5514 break;
5515 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5516 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 5517 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5518 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 5519 is_l2 = true;
5520 is_l4 = true;
33af6bcc
PO		 5521 config.rx_filter = HWTSTAMP_FILTER_SOME;
5522 break;
5523 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5524 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 5525 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5526 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 5527 is_l2 = true;
5528 is_l4 = true;
33af6bcc
PO		 5529 config.rx_filter = HWTSTAMP_FILTER_SOME;
5530 break;
5531 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5532 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5533 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 5534 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 5535 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 5536 is_l2 = true;
33af6bcc
PO		 5537 break;
5538 default:
5539 return -ERANGE;
5540 }
5541
c5b9bd5e
AD		 5542 if (hw->mac.type == e1000_82575) {
5543 if (tsync_rx_ctl | tsync_tx_ctl)
5544 return -EINVAL;
5545 return 0;
5546 }
5547
33af6bcc
PO		 5548 /* enable/disable TX */
5549 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 5550 regval &= ~E1000_TSYNCTXCTL_ENABLED;
5551 regval |= tsync_tx_ctl;
33af6bcc
PO		 5552 wr32(E1000_TSYNCTXCTL, regval);
5553
c5b9bd5e 5554 /* enable/disable RX */
33af6bcc 5555 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 5556 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
5557 regval |= tsync_rx_ctl;
33af6bcc 5558 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 5559
c5b9bd5e
AD		 5560 /* define which PTP packets are time stamped */
5561 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 5562
c5b9bd5e
AD		 5563 /* define ethertype filter for timestamped packets */
5564 if (is_l2)
5565 wr32(E1000_ETQF(3),
5566 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
5567 E1000_ETQF_1588 | /* enable timestamping */
5568 ETH_P_1588)); /* 1588 eth protocol type */
5569 else
5570 wr32(E1000_ETQF(3), 0);
5571
5572#define PTP_PORT 319
5573 /* L4 Queue Filter[3]: filter by destination port and protocol */
5574 if (is_l4) {
5575 u32 ftqf = (IPPROTO_UDP /* UDP */
5576 | E1000_FTQF_VF_BP /* VF not compared */
5577 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
5578 | E1000_FTQF_MASK); /* mask all inputs */
5579 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
5580
5581 wr32(E1000_IMIR(3), htons(PTP_PORT));
5582 wr32(E1000_IMIREXT(3),
5583 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
5584 if (hw->mac.type == e1000_82576) {
5585 /* enable source port check */
5586 wr32(E1000_SPQF(3), htons(PTP_PORT));
5587 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
5588 }
5589 wr32(E1000_FTQF(3), ftqf);
5590 } else {
5591 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
5592 }
33af6bcc
PO		 5593 wrfl();
5594
5595 adapter->hwtstamp_config = config;
5596
5597 /* clear TX/RX time stamp registers, just to be sure */
5598 regval = rd32(E1000_TXSTMPH);
5599 regval = rd32(E1000_RXSTMPH);
c6cb090b 5600
33af6bcc
PO		 5601 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5602 -EFAULT : 0;
c6cb090b
PO		 5603}
5604
9d5c8243
AK		 5605/**
5606 * igb_ioctl -
5607 * @netdev:
5608 * @ifreq:
5609 * @cmd:
5610 **/
5611static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5612{
5613 switch (cmd) {
5614 case SIOCGMIIPHY:
5615 case SIOCGMIIREG:
5616 case SIOCSMIIREG:
5617 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5618 case SIOCSHWTSTAMP:
5619 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5620 default:
5621 return -EOPNOTSUPP;
5622 }
5623}
5624
009bc06e
AD		 5625s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5626{
5627 struct igb_adapter *adapter = hw->back;
5628 u16 cap_offset;
5629
5630 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5631 if (!cap_offset)
5632 return -E1000_ERR_CONFIG;
5633
5634 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5635
5636 return 0;
5637}
5638
5639s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5640{
5641 struct igb_adapter *adapter = hw->back;
5642 u16 cap_offset;
5643
5644 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5645 if (!cap_offset)
5646 return -E1000_ERR_CONFIG;
5647
5648 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5649
5650 return 0;
5651}
5652
9d5c8243
AK		 5653static void igb_vlan_rx_register(struct net_device *netdev,
5654 struct vlan_group *grp)
5655{
5656 struct igb_adapter *adapter = netdev_priv(netdev);
5657 struct e1000_hw *hw = &adapter->hw;
5658 u32 ctrl, rctl;
5659
5660 igb_irq_disable(adapter);
5661 adapter->vlgrp = grp;
5662
5663 if (grp) {
5664 /* enable VLAN tag insert/strip */
5665 ctrl = rd32(E1000_CTRL);
5666 ctrl |= E1000_CTRL_VME;
5667 wr32(E1000_CTRL, ctrl);
5668
51466239 5669 /* Disable CFI check */
9d5c8243 5670 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5671 rctl &= ~E1000_RCTL_CFIEN;
5672 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 5673 } else {
5674 /* disable VLAN tag insert/strip */
5675 ctrl = rd32(E1000_CTRL);
5676 ctrl &= ~E1000_CTRL_VME;
5677 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 5678 }
5679
e1739522
AD		 5680 igb_rlpml_set(adapter);
5681
9d5c8243
AK		 5682 if (!test_bit(__IGB_DOWN, &adapter->state))
5683 igb_irq_enable(adapter);
5684}
5685
5686static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5687{
5688 struct igb_adapter *adapter = netdev_priv(netdev);
5689 struct e1000_hw *hw = &adapter->hw;
4ae196df 5690 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5691
51466239
AD		 5692 /* attempt to add filter to vlvf array */
5693 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 5694
51466239
AD		 5695 /* add the filter since PF can receive vlans w/o entry in vlvf */
5696 igb_vfta_set(hw, vid, true);
9d5c8243
AK		 5697}
5698
5699static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5700{
5701 struct igb_adapter *adapter = netdev_priv(netdev);
5702 struct e1000_hw *hw = &adapter->hw;
4ae196df 5703 int pf_id = adapter->vfs_allocated_count;
51466239 5704 s32 err;
9d5c8243
AK		 5705
5706 igb_irq_disable(adapter);
5707 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5708
5709 if (!test_bit(__IGB_DOWN, &adapter->state))
5710 igb_irq_enable(adapter);
5711
51466239
AD		 5712 /* remove vlan from VLVF table array */
5713 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 5714
51466239
AD		 5715 /* if vid was not present in VLVF just remove it from table */
5716 if (err)
4ae196df 5717 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5718}
5719
5720static void igb_restore_vlan(struct igb_adapter *adapter)
5721{
5722 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5723
5724 if (adapter->vlgrp) {
5725 u16 vid;
5726 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5727 if (!vlan_group_get_device(adapter->vlgrp, vid))
5728 continue;
5729 igb_vlan_rx_add_vid(adapter->netdev, vid);
5730 }
5731 }
5732}
5733
5734int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5735{
090b1795 5736 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 5737 struct e1000_mac_info *mac = &adapter->hw.mac;
5738
5739 mac->autoneg = 0;
5740
9d5c8243
AK		 5741 switch (spddplx) {
5742 case SPEED_10 + DUPLEX_HALF:
5743 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5744 break;
5745 case SPEED_10 + DUPLEX_FULL:
5746 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5747 break;
5748 case SPEED_100 + DUPLEX_HALF:
5749 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5750 break;
5751 case SPEED_100 + DUPLEX_FULL:
5752 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5753 break;
5754 case SPEED_1000 + DUPLEX_FULL:
5755 mac->autoneg = 1;
5756 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5757 break;
5758 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5759 default:
090b1795 5760 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9d5c8243
AK		 5761 return -EINVAL;
5762 }
5763 return 0;
5764}
5765
3fe7c4c9 5766static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5767{
5768 struct net_device *netdev = pci_get_drvdata(pdev);
5769 struct igb_adapter *adapter = netdev_priv(netdev);
5770 struct e1000_hw *hw = &adapter->hw;
2d064c06 5771 u32 ctrl, rctl, status;
9d5c8243
AK		 5772 u32 wufc = adapter->wol;
5773#ifdef CONFIG_PM
5774 int retval = 0;
5775#endif
5776
5777 netif_device_detach(netdev);
5778
a88f10ec
AD		 5779 if (netif_running(netdev))
5780 igb_close(netdev);
5781
047e0030 5782 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5783
5784#ifdef CONFIG_PM
5785 retval = pci_save_state(pdev);
5786 if (retval)
5787 return retval;
5788#endif
5789
5790 status = rd32(E1000_STATUS);
5791 if (status & E1000_STATUS_LU)
5792 wufc &= ~E1000_WUFC_LNKC;
5793
5794 if (wufc) {
5795 igb_setup_rctl(adapter);
ff41f8dc 5796 igb_set_rx_mode(netdev);
9d5c8243
AK		 5797
5798 /* turn on all-multi mode if wake on multicast is enabled */
5799 if (wufc & E1000_WUFC_MC) {
5800 rctl = rd32(E1000_RCTL);
5801 rctl |= E1000_RCTL_MPE;
5802 wr32(E1000_RCTL, rctl);
5803 }
5804
5805 ctrl = rd32(E1000_CTRL);
5806 /* advertise wake from D3Cold */
5807 #define E1000_CTRL_ADVD3WUC 0x00100000
5808 /* phy power management enable */
5809 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5810 ctrl |= E1000_CTRL_ADVD3WUC;
5811 wr32(E1000_CTRL, ctrl);
5812
9d5c8243 5813 /* Allow time for pending master requests to run */
330a6d6a 5814 igb_disable_pcie_master(hw);
9d5c8243
AK		 5815
5816 wr32(E1000_WUC, E1000_WUC_PME_EN);
5817 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5818 } else {
5819 wr32(E1000_WUC, 0);
5820 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5821 }
5822
3fe7c4c9
RW		 5823 *enable_wake = wufc || adapter->en_mng_pt;
5824 if (!*enable_wake)
88a268c1
NN		 5825 igb_power_down_link(adapter);
5826 else
5827 igb_power_up_link(adapter);
9d5c8243
AK		 5828
5829 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5830 * would have already happened in close and is redundant. */
5831 igb_release_hw_control(adapter);
5832
5833 pci_disable_device(pdev);
5834
9d5c8243
AK		 5835 return 0;
5836}
5837
5838#ifdef CONFIG_PM
3fe7c4c9
RW		 5839static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5840{
5841 int retval;
5842 bool wake;
5843
5844 retval = __igb_shutdown(pdev, &wake);
5845 if (retval)
5846 return retval;
5847
5848 if (wake) {
5849 pci_prepare_to_sleep(pdev);
5850 } else {
5851 pci_wake_from_d3(pdev, false);
5852 pci_set_power_state(pdev, PCI_D3hot);
5853 }
5854
5855 return 0;
5856}
5857
9d5c8243
AK		 5858static int igb_resume(struct pci_dev *pdev)
5859{
5860 struct net_device *netdev = pci_get_drvdata(pdev);
5861 struct igb_adapter *adapter = netdev_priv(netdev);
5862 struct e1000_hw *hw = &adapter->hw;
5863 u32 err;
5864
5865 pci_set_power_state(pdev, PCI_D0);
5866 pci_restore_state(pdev);
b94f2d77 5867 pci_save_state(pdev);
42bfd33a 5868
aed5dec3 5869 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5870 if (err) {
5871 dev_err(&pdev->dev,
5872 "igb: Cannot enable PCI device from suspend\n");
5873 return err;
5874 }
5875 pci_set_master(pdev);
5876
5877 pci_enable_wake(pdev, PCI_D3hot, 0);
5878 pci_enable_wake(pdev, PCI_D3cold, 0);
5879
047e0030 5880 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5881 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5882 return -ENOMEM;
9d5c8243
AK		 5883 }
5884
9d5c8243 5885 igb_reset(adapter);
a8564f03
AD		 5886
5887 /* let the f/w know that the h/w is now under the control of the
5888 * driver. */
5889 igb_get_hw_control(adapter);
5890
9d5c8243
AK		 5891 wr32(E1000_WUS, ~0);
5892
a88f10ec
AD		 5893 if (netif_running(netdev)) {
5894 err = igb_open(netdev);
5895 if (err)
5896 return err;
5897 }
9d5c8243
AK		 5898
5899 netif_device_attach(netdev);
5900
9d5c8243
AK		 5901 return 0;
5902}
5903#endif
5904
5905static void igb_shutdown(struct pci_dev *pdev)
5906{
3fe7c4c9
RW		 5907 bool wake;
5908
5909 __igb_shutdown(pdev, &wake);
5910
5911 if (system_state == SYSTEM_POWER_OFF) {
5912 pci_wake_from_d3(pdev, wake);
5913 pci_set_power_state(pdev, PCI_D3hot);
5914 }
9d5c8243
AK		 5915}
5916
5917#ifdef CONFIG_NET_POLL_CONTROLLER
5918/*
5919 * Polling 'interrupt' - used by things like netconsole to send skbs
5920 * without having to re-enable interrupts. It's not called while
5921 * the interrupt routine is executing.
5922 */
5923static void igb_netpoll(struct net_device *netdev)
5924{
5925 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5926 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5927 int i;
9d5c8243 5928
eebbbdba 5929 if (!adapter->msix_entries) {
047e0030 5930 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5931 igb_irq_disable(adapter);
047e0030 5932 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5933 return;
5934 }
9d5c8243 5935
047e0030
AD		 5936 for (i = 0; i < adapter->num_q_vectors; i++) {
5937 struct igb_q_vector *q_vector = adapter->q_vector[i];
5938 wr32(E1000_EIMC, q_vector->eims_value);
5939 napi_schedule(&q_vector->napi);
eebbbdba 5940 }
9d5c8243
AK		 5941}
5942#endif /* CONFIG_NET_POLL_CONTROLLER */
5943
5944/**
5945 * igb_io_error_detected - called when PCI error is detected
5946 * @pdev: Pointer to PCI device
5947 * @state: The current pci connection state
5948 *
5949 * This function is called after a PCI bus error affecting
5950 * this device has been detected.
5951 */
5952static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5953 pci_channel_state_t state)
5954{
5955 struct net_device *netdev = pci_get_drvdata(pdev);
5956 struct igb_adapter *adapter = netdev_priv(netdev);
5957
5958 netif_device_detach(netdev);
5959
59ed6eec
AD		 5960 if (state == pci_channel_io_perm_failure)
5961 return PCI_ERS_RESULT_DISCONNECT;
5962
9d5c8243
AK		 5963 if (netif_running(netdev))
5964 igb_down(adapter);
5965 pci_disable_device(pdev);
5966
5967 /* Request a slot slot reset. */
5968 return PCI_ERS_RESULT_NEED_RESET;
5969}
5970
5971/**
5972 * igb_io_slot_reset - called after the pci bus has been reset.
5973 * @pdev: Pointer to PCI device
5974 *
5975 * Restart the card from scratch, as if from a cold-boot. Implementation
5976 * resembles the first-half of the igb_resume routine.
5977 */
5978static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5979{
5980 struct net_device *netdev = pci_get_drvdata(pdev);
5981 struct igb_adapter *adapter = netdev_priv(netdev);
5982 struct e1000_hw *hw = &adapter->hw;
40a914fa 5983 pci_ers_result_t result;
42bfd33a 5984 int err;
9d5c8243 5985
aed5dec3 5986 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5987 dev_err(&pdev->dev,
5988 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5989 result = PCI_ERS_RESULT_DISCONNECT;
5990 } else {
5991 pci_set_master(pdev);
5992 pci_restore_state(pdev);
b94f2d77 5993 pci_save_state(pdev);
9d5c8243 5994
40a914fa
AD		 5995 pci_enable_wake(pdev, PCI_D3hot, 0);
5996 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5997
40a914fa
AD		 5998 igb_reset(adapter);
5999 wr32(E1000_WUS, ~0);
6000 result = PCI_ERS_RESULT_RECOVERED;
6001 }
9d5c8243 6002
ea943d41
JK		 6003 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6004 if (err) {
6005 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6006 "failed 0x%0x\n", err);
6007 /* non-fatal, continue */
6008 }
40a914fa
AD		 6009
6010 return result;
9d5c8243
AK		 6011}
6012
6013/**
6014 * igb_io_resume - called when traffic can start flowing again.
6015 * @pdev: Pointer to PCI device
6016 *
6017 * This callback is called when the error recovery driver tells us that
6018 * its OK to resume normal operation. Implementation resembles the
6019 * second-half of the igb_resume routine.
6020 */
6021static void igb_io_resume(struct pci_dev *pdev)
6022{
6023 struct net_device *netdev = pci_get_drvdata(pdev);
6024 struct igb_adapter *adapter = netdev_priv(netdev);
6025
9d5c8243
AK		 6026 if (netif_running(netdev)) {
6027 if (igb_up(adapter)) {
6028 dev_err(&pdev->dev, "igb_up failed after reset\n");
6029 return;
6030 }
6031 }
6032
6033 netif_device_attach(netdev);
6034
6035 /* let the f/w know that the h/w is now under the control of the
6036 * driver. */
6037 igb_get_hw_control(adapter);
9d5c8243
AK		 6038}
6039
26ad9178
AD		 6040static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6041 u8 qsel)
6042{
6043 u32 rar_low, rar_high;
6044 struct e1000_hw *hw = &adapter->hw;
6045
6046 /* HW expects these in little endian so we reverse the byte order
6047 * from network order (big endian) to little endian
6048 */
6049 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6050 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6051 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6052
6053 /* Indicate to hardware the Address is Valid. */
6054 rar_high |= E1000_RAH_AV;
6055
6056 if (hw->mac.type == e1000_82575)
6057 rar_high |= E1000_RAH_POOL_1 * qsel;
6058 else
6059 rar_high |= E1000_RAH_POOL_1 << qsel;
6060
6061 wr32(E1000_RAL(index), rar_low);
6062 wrfl();
6063 wr32(E1000_RAH(index), rar_high);
6064 wrfl();
6065}
6066
4ae196df
AD		 6067static int igb_set_vf_mac(struct igb_adapter *adapter,
6068 int vf, unsigned char *mac_addr)
6069{
6070 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6071 /* VF MAC addresses start at end of receive addresses and moves
6072 * torwards the first, as a result a collision should not be possible */
6073 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6074
37680117 6075 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6076
26ad9178 6077 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6078
6079 return 0;
6080}
6081
8151d294
WM		 6082static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6083{
6084 struct igb_adapter *adapter = netdev_priv(netdev);
6085 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6086 return -EINVAL;
6087 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6088 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6089 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6090 " change effective.");
6091 if (test_bit(__IGB_DOWN, &adapter->state)) {
6092 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6093 " but the PF device is not up.\n");
6094 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6095 " attempting to use the VF device.\n");
6096 }
6097 return igb_set_vf_mac(adapter, vf, mac);
6098}
6099
6100static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6101{
6102 return -EOPNOTSUPP;
6103}
6104
6105static int igb_ndo_get_vf_config(struct net_device *netdev,
6106 int vf, struct ifla_vf_info *ivi)
6107{
6108 struct igb_adapter *adapter = netdev_priv(netdev);
6109 if (vf >= adapter->vfs_allocated_count)
6110 return -EINVAL;
6111 ivi->vf = vf;
6112 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
6113 ivi->tx_rate = 0;
6114 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6115 ivi->qos = adapter->vf_data[vf].pf_qos;
6116 return 0;
6117}
6118
4ae196df
AD		 6119static void igb_vmm_control(struct igb_adapter *adapter)
6120{
6121 struct e1000_hw *hw = &adapter->hw;
10d8e907 6122 u32 reg;
4ae196df 6123
52a1dd4d
AD		 6124 switch (hw->mac.type) {
6125 case e1000_82575:
6126 default:
6127 /* replication is not supported for 82575 */
4ae196df 6128 return;
52a1dd4d
AD		 6129 case e1000_82576:
6130 /* notify HW that the MAC is adding vlan tags */
6131 reg = rd32(E1000_DTXCTL);
6132 reg |= E1000_DTXCTL_VLAN_ADDED;
6133 wr32(E1000_DTXCTL, reg);
6134 case e1000_82580:
6135 /* enable replication vlan tag stripping */
6136 reg = rd32(E1000_RPLOLR);
6137 reg |= E1000_RPLOLR_STRVLAN;
6138 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 6139 case e1000_i350:
6140 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 6141 break;
6142 }
10d8e907 6143
d4960307
AD		 6144 if (adapter->vfs_allocated_count) {
6145 igb_vmdq_set_loopback_pf(hw, true);
6146 igb_vmdq_set_replication_pf(hw, true);
6147 } else {
6148 igb_vmdq_set_loopback_pf(hw, false);
6149 igb_vmdq_set_replication_pf(hw, false);
6150 }
4ae196df
AD		 6151}
6152
9d5c8243 6153/* igb_main.c */
Clone of davem's net-next-2.6 tree