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igb: add combined function for setting rar and pool bits
[net-next-2.6.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
2d064c06
AD		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
73 /* required last entry */
74 {0, }
75};
76
77MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
78
79void igb_reset(struct igb_adapter *);
80static int igb_setup_all_tx_resources(struct igb_adapter *);
81static int igb_setup_all_rx_resources(struct igb_adapter *);
82static void igb_free_all_tx_resources(struct igb_adapter *);
83static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 84void igb_update_stats(struct igb_adapter *);
85static int igb_probe(struct pci_dev *, const struct pci_device_id *);
86static void __devexit igb_remove(struct pci_dev *pdev);
87static int igb_sw_init(struct igb_adapter *);
88static int igb_open(struct net_device *);
89static int igb_close(struct net_device *);
90static void igb_configure_tx(struct igb_adapter *);
91static void igb_configure_rx(struct igb_adapter *);
92static void igb_setup_rctl(struct igb_adapter *);
93static void igb_clean_all_tx_rings(struct igb_adapter *);
94static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 95static void igb_clean_tx_ring(struct igb_ring *);
96static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 97static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 98static void igb_update_phy_info(unsigned long);
99static void igb_watchdog(unsigned long);
100static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 101static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
102 struct net_device *,
103 struct igb_ring *);
104static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
105 struct net_device *);
9d5c8243
AK		 106static struct net_device_stats *igb_get_stats(struct net_device *);
107static int igb_change_mtu(struct net_device *, int);
108static int igb_set_mac(struct net_device *, void *);
109static irqreturn_t igb_intr(int irq, void *);
110static irqreturn_t igb_intr_msi(int irq, void *);
111static irqreturn_t igb_msix_other(int irq, void *);
112static irqreturn_t igb_msix_rx(int irq, void *);
113static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 114#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 115static void igb_update_rx_dca(struct igb_ring *);
116static void igb_update_tx_dca(struct igb_ring *);
117static void igb_setup_dca(struct igb_adapter *);
421e02f0 118#endif /* CONFIG_IGB_DCA */
3b644cf6 119static bool igb_clean_tx_irq(struct igb_ring *);
661086df 120static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 121static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
122static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 123static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
124static void igb_tx_timeout(struct net_device *);
125static void igb_reset_task(struct work_struct *);
126static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
127static void igb_vlan_rx_add_vid(struct net_device *, u16);
128static void igb_vlan_rx_kill_vid(struct net_device *, u16);
129static void igb_restore_vlan(struct igb_adapter *);
26ad9178 130static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 131static void igb_ping_all_vfs(struct igb_adapter *);
132static void igb_msg_task(struct igb_adapter *);
133static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
4ae196df 134static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 135static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 137
c8159b2d
ED		 138static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
139{
140 u32 reg_data;
141
142 reg_data = rd32(E1000_VMOLR(vfn));
143 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
144 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
145 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
146 E1000_VMOLR_AUPE | /* Accept untagged packets */
147 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
148 wr32(E1000_VMOLR(vfn), reg_data);
149}
150
151static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
152 int vfn)
153{
154 struct e1000_hw *hw = &adapter->hw;
155 u32 vmolr;
156
ae641bdc
AD		 157 /* if it isn't the PF check to see if VFs are enabled and
158 * increase the size to support vlan tags */
159 if (vfn < adapter->vfs_allocated_count &&
160 adapter->vf_data[vfn].vlans_enabled)
161 size += VLAN_TAG_SIZE;
162
c8159b2d
ED		 163 vmolr = rd32(E1000_VMOLR(vfn));
164 vmolr &= ~E1000_VMOLR_RLPML_MASK;
165 vmolr |= size | E1000_VMOLR_LPE;
166 wr32(E1000_VMOLR(vfn), vmolr);
167
168 return 0;
169}
170
9d5c8243 171#ifdef CONFIG_PM
3fe7c4c9 172static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 173static int igb_resume(struct pci_dev *);
174#endif
175static void igb_shutdown(struct pci_dev *);
421e02f0 176#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 177static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
178static struct notifier_block dca_notifier = {
179 .notifier_call = igb_notify_dca,
180 .next = NULL,
181 .priority = 0
182};
183#endif
9d5c8243
AK		 184#ifdef CONFIG_NET_POLL_CONTROLLER
185/* for netdump / net console */
186static void igb_netpoll(struct net_device *);
187#endif
37680117 188#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 189static unsigned int max_vfs = 0;
190module_param(max_vfs, uint, 0);
191MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
192 "per physical function");
193#endif /* CONFIG_PCI_IOV */
194
9d5c8243
AK		 195static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
196 pci_channel_state_t);
197static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
198static void igb_io_resume(struct pci_dev *);
199
200static struct pci_error_handlers igb_err_handler = {
201 .error_detected = igb_io_error_detected,
202 .slot_reset = igb_io_slot_reset,
203 .resume = igb_io_resume,
204};
205
206
207static struct pci_driver igb_driver = {
208 .name = igb_driver_name,
209 .id_table = igb_pci_tbl,
210 .probe = igb_probe,
211 .remove = __devexit_p(igb_remove),
212#ifdef CONFIG_PM
213 /* Power Managment Hooks */
214 .suspend = igb_suspend,
215 .resume = igb_resume,
216#endif
217 .shutdown = igb_shutdown,
218 .err_handler = &igb_err_handler
219};
220
7dfc16fa
AD		 221static int global_quad_port_a; /* global quad port a indication */
222
9d5c8243
AK		 223MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
224MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
225MODULE_LICENSE("GPL");
226MODULE_VERSION(DRV_VERSION);
227
38c845c7
PO		 228/**
229 * Scale the NIC clock cycle by a large factor so that
230 * relatively small clock corrections can be added or
231 * substracted at each clock tick. The drawbacks of a
232 * large factor are a) that the clock register overflows
233 * more quickly (not such a big deal) and b) that the
234 * increment per tick has to fit into 24 bits.
235 *
236 * Note that
237 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
238 * IGB_TSYNC_SCALE
239 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
240 *
241 * The base scale factor is intentionally a power of two
242 * so that the division in %struct timecounter can be done with
243 * a shift.
244 */
245#define IGB_TSYNC_SHIFT (19)
246#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
247
248/**
249 * The duration of one clock cycle of the NIC.
250 *
251 * @todo This hard-coded value is part of the specification and might change
252 * in future hardware revisions. Add revision check.
253 */
254#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
255
256#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
257# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
258#endif
259
260/**
261 * igb_read_clock - read raw cycle counter (to be used by time counter)
262 */
263static cycle_t igb_read_clock(const struct cyclecounter *tc)
264{
265 struct igb_adapter *adapter =
266 container_of(tc, struct igb_adapter, cycles);
267 struct e1000_hw *hw = &adapter->hw;
268 u64 stamp;
269
270 stamp = rd32(E1000_SYSTIML);
271 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
272
273 return stamp;
274}
275
9d5c8243
AK		 276#ifdef DEBUG
277/**
278 * igb_get_hw_dev_name - return device name string
279 * used by hardware layer to print debugging information
280 **/
281char *igb_get_hw_dev_name(struct e1000_hw *hw)
282{
283 struct igb_adapter *adapter = hw->back;
284 return adapter->netdev->name;
285}
38c845c7
PO		 286
287/**
288 * igb_get_time_str - format current NIC and system time as string
289 */
290static char *igb_get_time_str(struct igb_adapter *adapter,
291 char buffer[160])
292{
293 cycle_t hw = adapter->cycles.read(&adapter->cycles);
294 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
295 struct timespec sys;
296 struct timespec delta;
297 getnstimeofday(&sys);
298
299 delta = timespec_sub(nic, sys);
300
301 sprintf(buffer,
33af6bcc
PO		 302 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
303 hw,
38c845c7
PO		 304 (long)nic.tv_sec, nic.tv_nsec,
305 (long)sys.tv_sec, sys.tv_nsec,
306 (long)delta.tv_sec, delta.tv_nsec);
307
308 return buffer;
309}
9d5c8243
AK		 310#endif
311
c493ea45
AD		 312/**
313 * igb_desc_unused - calculate if we have unused descriptors
314 **/
315static int igb_desc_unused(struct igb_ring *ring)
316{
317 if (ring->next_to_clean > ring->next_to_use)
318 return ring->next_to_clean - ring->next_to_use - 1;
319
320 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
321}
322
9d5c8243
AK		 323/**
324 * igb_init_module - Driver Registration Routine
325 *
326 * igb_init_module is the first routine called when the driver is
327 * loaded. All it does is register with the PCI subsystem.
328 **/
329static int __init igb_init_module(void)
330{
331 int ret;
332 printk(KERN_INFO "%s - version %s\n",
333 igb_driver_string, igb_driver_version);
334
335 printk(KERN_INFO "%s\n", igb_copyright);
336
7dfc16fa
AD		 337 global_quad_port_a = 0;
338
421e02f0 339#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 340 dca_register_notify(&dca_notifier);
341#endif
bbd98fe4
AD		 342
343 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 344 return ret;
345}
346
347module_init(igb_init_module);
348
349/**
350 * igb_exit_module - Driver Exit Cleanup Routine
351 *
352 * igb_exit_module is called just before the driver is removed
353 * from memory.
354 **/
355static void __exit igb_exit_module(void)
356{
421e02f0 357#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 358 dca_unregister_notify(&dca_notifier);
359#endif
9d5c8243
AK		 360 pci_unregister_driver(&igb_driver);
361}
362
363module_exit(igb_exit_module);
364
26bc19ec
AD		 365#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
366/**
367 * igb_cache_ring_register - Descriptor ring to register mapping
368 * @adapter: board private structure to initialize
369 *
370 * Once we know the feature-set enabled for the device, we'll cache
371 * the register offset the descriptor ring is assigned to.
372 **/
373static void igb_cache_ring_register(struct igb_adapter *adapter)
374{
375 int i;
1bfaf07b 376 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 377
378 switch (adapter->hw.mac.type) {
379 case e1000_82576:
380 /* The queues are allocated for virtualization such that VF 0
381 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
382 * In order to avoid collision we start at the first free queue
383 * and continue consuming queues in the same sequence
384 */
385 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 386 adapter->rx_ring[i].reg_idx = rbase_offset +
387 Q_IDX_82576(i);
26bc19ec 388 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 389 adapter->tx_ring[i].reg_idx = rbase_offset +
390 Q_IDX_82576(i);
26bc19ec
AD		 391 break;
392 case e1000_82575:
393 default:
394 for (i = 0; i < adapter->num_rx_queues; i++)
395 adapter->rx_ring[i].reg_idx = i;
396 for (i = 0; i < adapter->num_tx_queues; i++)
397 adapter->tx_ring[i].reg_idx = i;
398 break;
399 }
400}
401
9d5c8243
AK		 402/**
403 * igb_alloc_queues - Allocate memory for all rings
404 * @adapter: board private structure to initialize
405 *
406 * We allocate one ring per queue at run-time since we don't know the
407 * number of queues at compile-time.
408 **/
409static int igb_alloc_queues(struct igb_adapter *adapter)
410{
411 int i;
412
413 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
414 sizeof(struct igb_ring), GFP_KERNEL);
415 if (!adapter->tx_ring)
416 return -ENOMEM;
417
418 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
419 sizeof(struct igb_ring), GFP_KERNEL);
420 if (!adapter->rx_ring) {
421 kfree(adapter->tx_ring);
422 return -ENOMEM;
423 }
424
6eb5a7f1
AD		 425 adapter->rx_ring->buddy = adapter->tx_ring;
426
661086df
PWJ		 427 for (i = 0; i < adapter->num_tx_queues; i++) {
428 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 429 ring->count = adapter->tx_ring_count;
661086df
PWJ		 430 ring->adapter = adapter;
431 ring->queue_index = i;
432 }
9d5c8243
AK		 433 for (i = 0; i < adapter->num_rx_queues; i++) {
434 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 435 ring->count = adapter->rx_ring_count;
9d5c8243 436 ring->adapter = adapter;
844290e5 437 ring->queue_index = i;
9d5c8243
AK		 438 ring->itr_register = E1000_ITR;
439
844290e5 440 /* set a default napi handler for each rx_ring */
661086df 441 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 442 }
26bc19ec
AD		 443
444 igb_cache_ring_register(adapter);
9d5c8243
AK		 445 return 0;
446}
447
a88f10ec
AD		 448static void igb_free_queues(struct igb_adapter *adapter)
449{
450 int i;
451
452 for (i = 0; i < adapter->num_rx_queues; i++)
453 netif_napi_del(&adapter->rx_ring[i].napi);
454
d1a8c9e1
AD		 455 adapter->num_rx_queues = 0;
456 adapter->num_tx_queues = 0;
457
a88f10ec
AD		 458 kfree(adapter->tx_ring);
459 kfree(adapter->rx_ring);
460}
461
9d5c8243
AK		 462#define IGB_N0_QUEUE -1
463static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
464 int tx_queue, int msix_vector)
465{
466 u32 msixbm = 0;
467 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 468 u32 ivar, index;
469
470 switch (hw->mac.type) {
471 case e1000_82575:
9d5c8243
AK		 472 /* The 82575 assigns vectors using a bitmask, which matches the
473 bitmask for the EICR/EIMS/EIMC registers. To assign one
474 or more queues to a vector, we write the appropriate bits
475 into the MSIXBM register for that vector. */
476 if (rx_queue > IGB_N0_QUEUE) {
477 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
478 adapter->rx_ring[rx_queue].eims_value = msixbm;
479 }
480 if (tx_queue > IGB_N0_QUEUE) {
481 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
482 adapter->tx_ring[tx_queue].eims_value =
483 E1000_EICR_TX_QUEUE0 << tx_queue;
484 }
485 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 486 break;
487 case e1000_82576:
26bc19ec 488 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 489 Each queue has a single entry in the table to which we write
490 a vector number along with a "valid" bit. Sadly, the layout
491 of the table is somewhat counterintuitive. */
492 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 493 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 494 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 495 if (rx_queue & 0x1) {
2d064c06
AD		 496 /* vector goes into third byte of register */
497 ivar = ivar & 0xFF00FFFF;
498 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 499 } else {
500 /* vector goes into low byte of register */
501 ivar = ivar & 0xFFFFFF00;
502 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 503 }
504 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
505 array_wr32(E1000_IVAR0, index, ivar);
506 }
507 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 508 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 509 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 510 if (tx_queue & 0x1) {
2d064c06
AD		 511 /* vector goes into high byte of register */
512 ivar = ivar & 0x00FFFFFF;
513 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 514 } else {
515 /* vector goes into second byte of register */
516 ivar = ivar & 0xFFFF00FF;
517 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 518 }
519 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
520 array_wr32(E1000_IVAR0, index, ivar);
521 }
522 break;
523 default:
524 BUG();
525 break;
526 }
9d5c8243
AK		 527}
528
529/**
530 * igb_configure_msix - Configure MSI-X hardware
531 *
532 * igb_configure_msix sets up the hardware to properly
533 * generate MSI-X interrupts.
534 **/
535static void igb_configure_msix(struct igb_adapter *adapter)
536{
537 u32 tmp;
538 int i, vector = 0;
539 struct e1000_hw *hw = &adapter->hw;
540
541 adapter->eims_enable_mask = 0;
2d064c06
AD		 542 if (hw->mac.type == e1000_82576)
543 /* Turn on MSI-X capability first, or our settings
544 * won't stick. And it will take days to debug. */
545 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 546 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 547 E1000_GPIE_NSICR);
9d5c8243
AK		 548
549 for (i = 0; i < adapter->num_tx_queues; i++) {
550 struct igb_ring *tx_ring = &adapter->tx_ring[i];
551 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
552 adapter->eims_enable_mask |= tx_ring->eims_value;
553 if (tx_ring->itr_val)
6eb5a7f1 554 writel(tx_ring->itr_val,
9d5c8243
AK		 555 hw->hw_addr + tx_ring->itr_register);
556 else
557 writel(1, hw->hw_addr + tx_ring->itr_register);
558 }
559
560 for (i = 0; i < adapter->num_rx_queues; i++) {
561 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 562 rx_ring->buddy = NULL;
9d5c8243
AK		 563 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
564 adapter->eims_enable_mask |= rx_ring->eims_value;
565 if (rx_ring->itr_val)
6eb5a7f1 566 writel(rx_ring->itr_val,
9d5c8243
AK		 567 hw->hw_addr + rx_ring->itr_register);
568 else
569 writel(1, hw->hw_addr + rx_ring->itr_register);
570 }
571
572
573 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 574 switch (hw->mac.type) {
575 case e1000_82575:
9d5c8243
AK		 576 array_wr32(E1000_MSIXBM(0), vector++,
577 E1000_EIMS_OTHER);
578
9d5c8243
AK		 579 tmp = rd32(E1000_CTRL_EXT);
580 /* enable MSI-X PBA support*/
581 tmp |= E1000_CTRL_EXT_PBA_CLR;
582
583 /* Auto-Mask interrupts upon ICR read. */
584 tmp |= E1000_CTRL_EXT_EIAME;
585 tmp |= E1000_CTRL_EXT_IRCA;
586
587 wr32(E1000_CTRL_EXT, tmp);
588 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 589 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 590
2d064c06
AD		 591 break;
592
593 case e1000_82576:
594 tmp = (vector++ | E1000_IVAR_VALID) << 8;
595 wr32(E1000_IVAR_MISC, tmp);
596
597 adapter->eims_enable_mask = (1 << (vector)) - 1;
598 adapter->eims_other = 1 << (vector - 1);
599 break;
600 default:
601 /* do nothing, since nothing else supports MSI-X */
602 break;
603 } /* switch (hw->mac.type) */
9d5c8243
AK		 604 wrfl();
605}
606
607/**
608 * igb_request_msix - Initialize MSI-X interrupts
609 *
610 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
611 * kernel.
612 **/
613static int igb_request_msix(struct igb_adapter *adapter)
614{
615 struct net_device *netdev = adapter->netdev;
616 int i, err = 0, vector = 0;
617
618 vector = 0;
619
620 for (i = 0; i < adapter->num_tx_queues; i++) {
621 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 622 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 623 err = request_irq(adapter->msix_entries[vector].vector,
624 &igb_msix_tx, 0, ring->name,
625 &(adapter->tx_ring[i]));
626 if (err)
627 goto out;
628 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 629 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 630 vector++;
631 }
632 for (i = 0; i < adapter->num_rx_queues; i++) {
633 struct igb_ring *ring = &(adapter->rx_ring[i]);
634 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 635 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 636 else
637 memcpy(ring->name, netdev->name, IFNAMSIZ);
638 err = request_irq(adapter->msix_entries[vector].vector,
639 &igb_msix_rx, 0, ring->name,
640 &(adapter->rx_ring[i]));
641 if (err)
642 goto out;
643 ring->itr_register = E1000_EITR(0) + (vector << 2);
644 ring->itr_val = adapter->itr;
645 vector++;
646 }
647
648 err = request_irq(adapter->msix_entries[vector].vector,
649 &igb_msix_other, 0, netdev->name, netdev);
650 if (err)
651 goto out;
652
9d5c8243
AK		 653 igb_configure_msix(adapter);
654 return 0;
655out:
656 return err;
657}
658
659static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
660{
661 if (adapter->msix_entries) {
662 pci_disable_msix(adapter->pdev);
663 kfree(adapter->msix_entries);
664 adapter->msix_entries = NULL;
7dfc16fa 665 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 666 pci_disable_msi(adapter->pdev);
667 return;
668}
669
670
671/**
672 * igb_set_interrupt_capability - set MSI or MSI-X if supported
673 *
674 * Attempt to configure interrupts using the best available
675 * capabilities of the hardware and kernel.
676 **/
677static void igb_set_interrupt_capability(struct igb_adapter *adapter)
678{
679 int err;
680 int numvecs, i;
681
83b7180d
AD		 682 /* Number of supported queues. */
683 /* Having more queues than CPUs doesn't make sense. */
684 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
685 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
686
9d5c8243
AK		 687 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
688 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
689 GFP_KERNEL);
690 if (!adapter->msix_entries)
691 goto msi_only;
692
693 for (i = 0; i < numvecs; i++)
694 adapter->msix_entries[i].entry = i;
695
696 err = pci_enable_msix(adapter->pdev,
697 adapter->msix_entries,
698 numvecs);
699 if (err == 0)
34a20e89 700 goto out;
9d5c8243
AK		 701
702 igb_reset_interrupt_capability(adapter);
703
704 /* If we can't do MSI-X, try MSI */
705msi_only:
2a3abf6d
AD		 706#ifdef CONFIG_PCI_IOV
707 /* disable SR-IOV for non MSI-X configurations */
708 if (adapter->vf_data) {
709 struct e1000_hw *hw = &adapter->hw;
710 /* disable iov and allow time for transactions to clear */
711 pci_disable_sriov(adapter->pdev);
712 msleep(500);
713
714 kfree(adapter->vf_data);
715 adapter->vf_data = NULL;
716 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
717 msleep(100);
718 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
719 }
720#endif
9d5c8243 721 adapter->num_rx_queues = 1;
661086df 722 adapter->num_tx_queues = 1;
9d5c8243 723 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 724 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 725out:
661086df 726 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 727 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 728 return;
729}
730
731/**
732 * igb_request_irq - initialize interrupts
733 *
734 * Attempts to configure interrupts using the best available
735 * capabilities of the hardware and kernel.
736 **/
737static int igb_request_irq(struct igb_adapter *adapter)
738{
739 struct net_device *netdev = adapter->netdev;
740 struct e1000_hw *hw = &adapter->hw;
741 int err = 0;
742
743 if (adapter->msix_entries) {
744 err = igb_request_msix(adapter);
844290e5 745 if (!err)
9d5c8243 746 goto request_done;
9d5c8243
AK		 747 /* fall back to MSI */
748 igb_reset_interrupt_capability(adapter);
749 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 750 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 751 igb_free_all_tx_resources(adapter);
752 igb_free_all_rx_resources(adapter);
753 adapter->num_rx_queues = 1;
754 igb_alloc_queues(adapter);
844290e5 755 } else {
2d064c06
AD		 756 switch (hw->mac.type) {
757 case e1000_82575:
758 wr32(E1000_MSIXBM(0),
759 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
760 break;
761 case e1000_82576:
762 wr32(E1000_IVAR0, E1000_IVAR_VALID);
763 break;
764 default:
765 break;
766 }
9d5c8243 767 }
844290e5 768
7dfc16fa 769 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 770 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
771 netdev->name, netdev);
772 if (!err)
773 goto request_done;
774 /* fall back to legacy interrupts */
775 igb_reset_interrupt_capability(adapter);
7dfc16fa 776 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 777 }
778
779 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
780 netdev->name, netdev);
781
6cb5e577 782 if (err)
9d5c8243
AK		 783 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
784 err);
9d5c8243
AK		 785
786request_done:
787 return err;
788}
789
790static void igb_free_irq(struct igb_adapter *adapter)
791{
792 struct net_device *netdev = adapter->netdev;
793
794 if (adapter->msix_entries) {
795 int vector = 0, i;
796
797 for (i = 0; i < adapter->num_tx_queues; i++)
798 free_irq(adapter->msix_entries[vector++].vector,
799 &(adapter->tx_ring[i]));
800 for (i = 0; i < adapter->num_rx_queues; i++)
801 free_irq(adapter->msix_entries[vector++].vector,
802 &(adapter->rx_ring[i]));
803
804 free_irq(adapter->msix_entries[vector++].vector, netdev);
805 return;
806 }
807
808 free_irq(adapter->pdev->irq, netdev);
809}
810
811/**
812 * igb_irq_disable - Mask off interrupt generation on the NIC
813 * @adapter: board private structure
814 **/
815static void igb_irq_disable(struct igb_adapter *adapter)
816{
817 struct e1000_hw *hw = &adapter->hw;
818
819 if (adapter->msix_entries) {
2dfd1212
AD		 820 u32 regval = rd32(E1000_EIAM);
821 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
822 wr32(E1000_EIMC, adapter->eims_enable_mask);
823 regval = rd32(E1000_EIAC);
824 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 825 }
844290e5
PW		 826
827 wr32(E1000_IAM, 0);
9d5c8243
AK		 828 wr32(E1000_IMC, ~0);
829 wrfl();
830 synchronize_irq(adapter->pdev->irq);
831}
832
833/**
834 * igb_irq_enable - Enable default interrupt generation settings
835 * @adapter: board private structure
836 **/
837static void igb_irq_enable(struct igb_adapter *adapter)
838{
839 struct e1000_hw *hw = &adapter->hw;
840
841 if (adapter->msix_entries) {
2dfd1212
AD		 842 u32 regval = rd32(E1000_EIAC);
843 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
844 regval = rd32(E1000_EIAM);
845 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 846 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 847 if (adapter->vfs_allocated_count)
848 wr32(E1000_MBVFIMR, 0xFF);
849 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
850 E1000_IMS_DOUTSYNC));
844290e5
PW		 851 } else {
852 wr32(E1000_IMS, IMS_ENABLE_MASK);
853 wr32(E1000_IAM, IMS_ENABLE_MASK);
854 }
9d5c8243
AK		 855}
856
857static void igb_update_mng_vlan(struct igb_adapter *adapter)
858{
859 struct net_device *netdev = adapter->netdev;
860 u16 vid = adapter->hw.mng_cookie.vlan_id;
861 u16 old_vid = adapter->mng_vlan_id;
862 if (adapter->vlgrp) {
863 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
864 if (adapter->hw.mng_cookie.status &
865 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
866 igb_vlan_rx_add_vid(netdev, vid);
867 adapter->mng_vlan_id = vid;
868 } else
869 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
870
871 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
872 (vid != old_vid) &&
873 !vlan_group_get_device(adapter->vlgrp, old_vid))
874 igb_vlan_rx_kill_vid(netdev, old_vid);
875 } else
876 adapter->mng_vlan_id = vid;
877 }
878}
879
880/**
881 * igb_release_hw_control - release control of the h/w to f/w
882 * @adapter: address of board private structure
883 *
884 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
885 * For ASF and Pass Through versions of f/w this means that the
886 * driver is no longer loaded.
887 *
888 **/
889static void igb_release_hw_control(struct igb_adapter *adapter)
890{
891 struct e1000_hw *hw = &adapter->hw;
892 u32 ctrl_ext;
893
894 /* Let firmware take over control of h/w */
895 ctrl_ext = rd32(E1000_CTRL_EXT);
896 wr32(E1000_CTRL_EXT,
897 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
898}
899
900
901/**
902 * igb_get_hw_control - get control of the h/w from f/w
903 * @adapter: address of board private structure
904 *
905 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
906 * For ASF and Pass Through versions of f/w this means that
907 * the driver is loaded.
908 *
909 **/
910static void igb_get_hw_control(struct igb_adapter *adapter)
911{
912 struct e1000_hw *hw = &adapter->hw;
913 u32 ctrl_ext;
914
915 /* Let firmware know the driver has taken over */
916 ctrl_ext = rd32(E1000_CTRL_EXT);
917 wr32(E1000_CTRL_EXT,
918 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
919}
920
9d5c8243
AK		 921/**
922 * igb_configure - configure the hardware for RX and TX
923 * @adapter: private board structure
924 **/
925static void igb_configure(struct igb_adapter *adapter)
926{
927 struct net_device *netdev = adapter->netdev;
928 int i;
929
930 igb_get_hw_control(adapter);
ff41f8dc 931 igb_set_rx_mode(netdev);
9d5c8243
AK		 932
933 igb_restore_vlan(adapter);
9d5c8243
AK		 934
935 igb_configure_tx(adapter);
936 igb_setup_rctl(adapter);
937 igb_configure_rx(adapter);
662d7205
AD		 938
939 igb_rx_fifo_flush_82575(&adapter->hw);
940
c493ea45 941 /* call igb_desc_unused which always leaves
9d5c8243
AK		 942 * at least 1 descriptor unused to make sure
943 * next_to_use != next_to_clean */
944 for (i = 0; i < adapter->num_rx_queues; i++) {
945 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 946 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 947 }
948
949
950 adapter->tx_queue_len = netdev->tx_queue_len;
951}
952
953
954/**
955 * igb_up - Open the interface and prepare it to handle traffic
956 * @adapter: board private structure
957 **/
958
959int igb_up(struct igb_adapter *adapter)
960{
961 struct e1000_hw *hw = &adapter->hw;
962 int i;
963
964 /* hardware has been reset, we need to reload some things */
965 igb_configure(adapter);
966
967 clear_bit(__IGB_DOWN, &adapter->state);
968
844290e5
PW		 969 for (i = 0; i < adapter->num_rx_queues; i++)
970 napi_enable(&adapter->rx_ring[i].napi);
971 if (adapter->msix_entries)
9d5c8243 972 igb_configure_msix(adapter);
9d5c8243 973
4ae196df 974 igb_vmm_control(adapter);
e1739522
AD		 975 igb_set_vmolr(hw, adapter->vfs_allocated_count);
976
9d5c8243
AK		 977 /* Clear any pending interrupts. */
978 rd32(E1000_ICR);
979 igb_irq_enable(adapter);
980
4cb9be7a
JB		 981 netif_tx_start_all_queues(adapter->netdev);
982
9d5c8243
AK		 983 /* Fire a link change interrupt to start the watchdog. */
984 wr32(E1000_ICS, E1000_ICS_LSC);
985 return 0;
986}
987
988void igb_down(struct igb_adapter *adapter)
989{
990 struct e1000_hw *hw = &adapter->hw;
991 struct net_device *netdev = adapter->netdev;
992 u32 tctl, rctl;
993 int i;
994
995 /* signal that we're down so the interrupt handler does not
996 * reschedule our watchdog timer */
997 set_bit(__IGB_DOWN, &adapter->state);
998
999 /* disable receives in the hardware */
1000 rctl = rd32(E1000_RCTL);
1001 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1002 /* flush and sleep below */
1003
fd2ea0a7 1004 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1005
1006 /* disable transmits in the hardware */
1007 tctl = rd32(E1000_TCTL);
1008 tctl &= ~E1000_TCTL_EN;
1009 wr32(E1000_TCTL, tctl);
1010 /* flush both disables and wait for them to finish */
1011 wrfl();
1012 msleep(10);
1013
844290e5
PW		 1014 for (i = 0; i < adapter->num_rx_queues; i++)
1015 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 1016
9d5c8243
AK		 1017 igb_irq_disable(adapter);
1018
1019 del_timer_sync(&adapter->watchdog_timer);
1020 del_timer_sync(&adapter->phy_info_timer);
1021
1022 netdev->tx_queue_len = adapter->tx_queue_len;
1023 netif_carrier_off(netdev);
04fe6358
AD		 1024
1025 /* record the stats before reset*/
1026 igb_update_stats(adapter);
1027
9d5c8243
AK		 1028 adapter->link_speed = 0;
1029 adapter->link_duplex = 0;
1030
3023682e
JK		 1031 if (!pci_channel_offline(adapter->pdev))
1032 igb_reset(adapter);
9d5c8243
AK		 1033 igb_clean_all_tx_rings(adapter);
1034 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1035#ifdef CONFIG_IGB_DCA
1036
1037 /* since we reset the hardware DCA settings were cleared */
1038 igb_setup_dca(adapter);
1039#endif
9d5c8243
AK		 1040}
1041
1042void igb_reinit_locked(struct igb_adapter *adapter)
1043{
1044 WARN_ON(in_interrupt());
1045 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1046 msleep(1);
1047 igb_down(adapter);
1048 igb_up(adapter);
1049 clear_bit(__IGB_RESETTING, &adapter->state);
1050}
1051
1052void igb_reset(struct igb_adapter *adapter)
1053{
1054 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1055 struct e1000_mac_info *mac = &hw->mac;
1056 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1057 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1058 u16 hwm;
1059
1060 /* Repartition Pba for greater than 9k mtu
1061 * To take effect CTRL.RST is required.
1062 */
fa4dfae0
AD		 1063 switch (mac->type) {
1064 case e1000_82576:
2d064c06 1065 pba = E1000_PBA_64K;
fa4dfae0
AD		 1066 break;
1067 case e1000_82575:
1068 default:
1069 pba = E1000_PBA_34K;
1070 break;
2d064c06 1071 }
9d5c8243 1072
2d064c06
AD		 1073 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1074 (mac->type < e1000_82576)) {
9d5c8243
AK		 1075 /* adjust PBA for jumbo frames */
1076 wr32(E1000_PBA, pba);
1077
1078 /* To maintain wire speed transmits, the Tx FIFO should be
1079 * large enough to accommodate two full transmit packets,
1080 * rounded up to the next 1KB and expressed in KB. Likewise,
1081 * the Rx FIFO should be large enough to accommodate at least
1082 * one full receive packet and is similarly rounded up and
1083 * expressed in KB. */
1084 pba = rd32(E1000_PBA);
1085 /* upper 16 bits has Tx packet buffer allocation size in KB */
1086 tx_space = pba >> 16;
1087 /* lower 16 bits has Rx packet buffer allocation size in KB */
1088 pba &= 0xffff;
1089 /* the tx fifo also stores 16 bytes of information about the tx
1090 * but don't include ethernet FCS because hardware appends it */
1091 min_tx_space = (adapter->max_frame_size +
85e8d004 1092 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1093 ETH_FCS_LEN) * 2;
1094 min_tx_space = ALIGN(min_tx_space, 1024);
1095 min_tx_space >>= 10;
1096 /* software strips receive CRC, so leave room for it */
1097 min_rx_space = adapter->max_frame_size;
1098 min_rx_space = ALIGN(min_rx_space, 1024);
1099 min_rx_space >>= 10;
1100
1101 /* If current Tx allocation is less than the min Tx FIFO size,
1102 * and the min Tx FIFO size is less than the current Rx FIFO
1103 * allocation, take space away from current Rx allocation */
1104 if (tx_space < min_tx_space &&
1105 ((min_tx_space - tx_space) < pba)) {
1106 pba = pba - (min_tx_space - tx_space);
1107
1108 /* if short on rx space, rx wins and must trump tx
1109 * adjustment */
1110 if (pba < min_rx_space)
1111 pba = min_rx_space;
1112 }
2d064c06 1113 wr32(E1000_PBA, pba);
9d5c8243 1114 }
9d5c8243
AK		 1115
1116 /* flow control settings */
1117 /* The high water mark must be low enough to fit one full frame
1118 * (or the size used for early receive) above it in the Rx FIFO.
1119 * Set it to the lower of:
1120 * - 90% of the Rx FIFO size, or
1121 * - the full Rx FIFO size minus one full frame */
1122 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1123 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1124
2d064c06
AD		 1125 if (mac->type < e1000_82576) {
1126 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1127 fc->low_water = fc->high_water - 8;
1128 } else {
1129 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1130 fc->low_water = fc->high_water - 16;
1131 }
9d5c8243
AK		 1132 fc->pause_time = 0xFFFF;
1133 fc->send_xon = 1;
0cce119a 1134 fc->current_mode = fc->requested_mode;
9d5c8243 1135
4ae196df
AD		 1136 /* disable receive for all VFs and wait one second */
1137 if (adapter->vfs_allocated_count) {
1138 int i;
1139 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1140 adapter->vf_data[i].clear_to_send = false;
1141
1142 /* ping all the active vfs to let them know we are going down */
1143 igb_ping_all_vfs(adapter);
1144
1145 /* disable transmits and receives */
1146 wr32(E1000_VFRE, 0);
1147 wr32(E1000_VFTE, 0);
1148 }
1149
9d5c8243
AK		 1150 /* Allow time for pending master requests to run */
1151 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1152 wr32(E1000_WUC, 0);
1153
1154 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1155 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1156
1157 igb_update_mng_vlan(adapter);
1158
1159 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1160 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1161
1162 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1163 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1164}
1165
2e5c6922
SH		 1166static const struct net_device_ops igb_netdev_ops = {
1167 .ndo_open = igb_open,
1168 .ndo_stop = igb_close,
00829823 1169 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1170 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1171 .ndo_set_rx_mode = igb_set_rx_mode,
1172 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1173 .ndo_set_mac_address = igb_set_mac,
1174 .ndo_change_mtu = igb_change_mtu,
1175 .ndo_do_ioctl = igb_ioctl,
1176 .ndo_tx_timeout = igb_tx_timeout,
1177 .ndo_validate_addr = eth_validate_addr,
1178 .ndo_vlan_rx_register = igb_vlan_rx_register,
1179 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1180 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1181#ifdef CONFIG_NET_POLL_CONTROLLER
1182 .ndo_poll_controller = igb_netpoll,
1183#endif
1184};
1185
9d5c8243
AK		 1186/**
1187 * igb_probe - Device Initialization Routine
1188 * @pdev: PCI device information struct
1189 * @ent: entry in igb_pci_tbl
1190 *
1191 * Returns 0 on success, negative on failure
1192 *
1193 * igb_probe initializes an adapter identified by a pci_dev structure.
1194 * The OS initialization, configuring of the adapter private structure,
1195 * and a hardware reset occur.
1196 **/
1197static int __devinit igb_probe(struct pci_dev *pdev,
1198 const struct pci_device_id *ent)
1199{
1200 struct net_device *netdev;
1201 struct igb_adapter *adapter;
1202 struct e1000_hw *hw;
1203 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1204 unsigned long mmio_start, mmio_len;
2d6a5e95 1205 int err, pci_using_dac;
682337fe 1206 u16 eeprom_data = 0;
9d5c8243
AK		 1207 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1208 u32 part_num;
1209
aed5dec3 1210 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1211 if (err)
1212 return err;
1213
1214 pci_using_dac = 0;
6a35528a 1215 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1216 if (!err) {
6a35528a 1217 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1218 if (!err)
1219 pci_using_dac = 1;
1220 } else {
284901a9 1221 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1222 if (err) {
284901a9 1223 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1224 if (err) {
1225 dev_err(&pdev->dev, "No usable DMA "
1226 "configuration, aborting\n");
1227 goto err_dma;
1228 }
1229 }
1230 }
1231
aed5dec3
AD		 1232 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1233 IORESOURCE_MEM),
1234 igb_driver_name);
9d5c8243
AK		 1235 if (err)
1236 goto err_pci_reg;
1237
19d5afd4 1238 pci_enable_pcie_error_reporting(pdev);
40a914fa 1239
9d5c8243 1240 pci_set_master(pdev);
c682fc23 1241 pci_save_state(pdev);
9d5c8243
AK		 1242
1243 err = -ENOMEM;
1bfaf07b
AD		 1244 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1245 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1246 if (!netdev)
1247 goto err_alloc_etherdev;
1248
1249 SET_NETDEV_DEV(netdev, &pdev->dev);
1250
1251 pci_set_drvdata(pdev, netdev);
1252 adapter = netdev_priv(netdev);
1253 adapter->netdev = netdev;
1254 adapter->pdev = pdev;
1255 hw = &adapter->hw;
1256 hw->back = adapter;
1257 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1258
1259 mmio_start = pci_resource_start(pdev, 0);
1260 mmio_len = pci_resource_len(pdev, 0);
1261
1262 err = -EIO;
28b0759c
AD		 1263 hw->hw_addr = ioremap(mmio_start, mmio_len);
1264 if (!hw->hw_addr)
9d5c8243
AK		 1265 goto err_ioremap;
1266
2e5c6922 1267 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1268 igb_set_ethtool_ops(netdev);
9d5c8243 1269 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1270
1271 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1272
1273 netdev->mem_start = mmio_start;
1274 netdev->mem_end = mmio_start + mmio_len;
1275
9d5c8243
AK		 1276 /* PCI config space info */
1277 hw->vendor_id = pdev->vendor;
1278 hw->device_id = pdev->device;
1279 hw->revision_id = pdev->revision;
1280 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1281 hw->subsystem_device_id = pdev->subsystem_device;
1282
1283 /* setup the private structure */
1284 hw->back = adapter;
1285 /* Copy the default MAC, PHY and NVM function pointers */
1286 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1287 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1288 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1289 /* Initialize skew-specific constants */
1290 err = ei->get_invariants(hw);
1291 if (err)
450c87c8 1292 goto err_sw_init;
9d5c8243 1293
2a3abf6d
AD		 1294#ifdef CONFIG_PCI_IOV
1295 /* since iov functionality isn't critical to base device function we
1296 * can accept failure. If it fails we don't allow iov to be enabled */
1297 if (hw->mac.type == e1000_82576) {
1298 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1299 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1300 int i;
1301 unsigned char mac_addr[ETH_ALEN];
1302
9ca046d5 1303 if (num_vfs) {
2a3abf6d
AD		 1304 adapter->vf_data = kcalloc(num_vfs,
1305 sizeof(struct vf_data_storage),
1306 GFP_KERNEL);
9ca046d5
AD		 1307 if (!adapter->vf_data) {
1308 dev_err(&pdev->dev,
1309 "Could not allocate VF private data - "
1310 "IOV enable failed\n");
2a3abf6d 1311 } else {
9ca046d5
AD		 1312 err = pci_enable_sriov(pdev, num_vfs);
1313 if (!err) {
1314 adapter->vfs_allocated_count = num_vfs;
1315 dev_info(&pdev->dev,
1316 "%d vfs allocated\n",
1317 num_vfs);
1318 for (i = 0;
1319 i < adapter->vfs_allocated_count;
1320 i++) {
1321 random_ether_addr(mac_addr);
1322 igb_set_vf_mac(adapter, i,
1323 mac_addr);
1324 }
1325 } else {
1326 kfree(adapter->vf_data);
1327 adapter->vf_data = NULL;
1328 }
2a3abf6d
AD		 1329 }
1330 }
1331 }
1332
1333#endif
450c87c8 1334 /* setup the private structure */
9d5c8243
AK		 1335 err = igb_sw_init(adapter);
1336 if (err)
1337 goto err_sw_init;
1338
1339 igb_get_bus_info_pcie(hw);
1340
7dfc16fa
AD		 1341 /* set flags */
1342 switch (hw->mac.type) {
7dfc16fa 1343 case e1000_82575:
7dfc16fa
AD		 1344 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1345 break;
bbd98fe4 1346 case e1000_82576:
7dfc16fa
AD		 1347 default:
1348 break;
1349 }
1350
9d5c8243
AK		 1351 hw->phy.autoneg_wait_to_complete = false;
1352 hw->mac.adaptive_ifs = true;
1353
1354 /* Copper options */
1355 if (hw->phy.media_type == e1000_media_type_copper) {
1356 hw->phy.mdix = AUTO_ALL_MODES;
1357 hw->phy.disable_polarity_correction = false;
1358 hw->phy.ms_type = e1000_ms_hw_default;
1359 }
1360
1361 if (igb_check_reset_block(hw))
1362 dev_info(&pdev->dev,
1363 "PHY reset is blocked due to SOL/IDER session.\n");
1364
1365 netdev->features = NETIF_F_SG |
7d8eb29e 1366 NETIF_F_IP_CSUM |
9d5c8243
AK		 1367 NETIF_F_HW_VLAN_TX |
1368 NETIF_F_HW_VLAN_RX |
1369 NETIF_F_HW_VLAN_FILTER;
1370
7d8eb29e 1371 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1372 netdev->features |= NETIF_F_TSO;
9d5c8243 1373 netdev->features |= NETIF_F_TSO6;
48f29ffc 1374
5c0999b7 1375 netdev->features |= NETIF_F_GRO;
d3352520 1376
48f29ffc
JK		 1377 netdev->vlan_features |= NETIF_F_TSO;
1378 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1379 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1380 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1381 netdev->vlan_features |= NETIF_F_SG;
1382
9d5c8243
AK		 1383 if (pci_using_dac)
1384 netdev->features |= NETIF_F_HIGHDMA;
1385
b9473560
JB		 1386 if (adapter->hw.mac.type == e1000_82576)
1387 netdev->features |= NETIF_F_SCTP_CSUM;
1388
9d5c8243
AK		 1389 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1390
1391 /* before reading the NVM, reset the controller to put the device in a
1392 * known good starting state */
1393 hw->mac.ops.reset_hw(hw);
1394
1395 /* make sure the NVM is good */
1396 if (igb_validate_nvm_checksum(hw) < 0) {
1397 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1398 err = -EIO;
1399 goto err_eeprom;
1400 }
1401
1402 /* copy the MAC address out of the NVM */
1403 if (hw->mac.ops.read_mac_addr(hw))
1404 dev_err(&pdev->dev, "NVM Read Error\n");
1405
1406 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1407 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1408
1409 if (!is_valid_ether_addr(netdev->perm_addr)) {
1410 dev_err(&pdev->dev, "Invalid MAC Address\n");
1411 err = -EIO;
1412 goto err_eeprom;
1413 }
1414
0e340485
AD		 1415 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1416 (unsigned long) adapter);
1417 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1418 (unsigned long) adapter);
9d5c8243
AK		 1419
1420 INIT_WORK(&adapter->reset_task, igb_reset_task);
1421 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1422
450c87c8 1423 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1424 adapter->fc_autoneg = true;
1425 hw->mac.autoneg = true;
1426 hw->phy.autoneg_advertised = 0x2f;
1427
0cce119a
AD		 1428 hw->fc.requested_mode = e1000_fc_default;
1429 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1430
cbd347ad 1431 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1432 adapter->itr = IGB_START_ITR;
1433
1434 igb_validate_mdi_setting(hw);
1435
9d5c8243
AK		 1436 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1437 * enable the ACPI Magic Packet filter
1438 */
1439
a2cf8b6c 1440 if (hw->bus.func == 0)
312c75ae 1441 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1442 else if (hw->bus.func == 1)
1443 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1444
1445 if (eeprom_data & eeprom_apme_mask)
1446 adapter->eeprom_wol |= E1000_WUFC_MAG;
1447
1448 /* now that we have the eeprom settings, apply the special cases where
1449 * the eeprom may be wrong or the board simply won't support wake on
1450 * lan on a particular port */
1451 switch (pdev->device) {
1452 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1453 adapter->eeprom_wol = 0;
1454 break;
1455 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1456 case E1000_DEV_ID_82576_FIBER:
1457 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1458 /* Wake events only supported on port A for dual fiber
1459 * regardless of eeprom setting */
1460 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1461 adapter->eeprom_wol = 0;
1462 break;
c8ea5ea9
AD		 1463 case E1000_DEV_ID_82576_QUAD_COPPER:
1464 /* if quad port adapter, disable WoL on all but port A */
1465 if (global_quad_port_a != 0)
1466 adapter->eeprom_wol = 0;
1467 else
1468 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1469 /* Reset for multiple quad port adapters */
1470 if (++global_quad_port_a == 4)
1471 global_quad_port_a = 0;
1472 break;
9d5c8243
AK		 1473 }
1474
1475 /* initialize the wol settings based on the eeprom settings */
1476 adapter->wol = adapter->eeprom_wol;
e1b86d84 1477 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1478
1479 /* reset the hardware with the new settings */
1480 igb_reset(adapter);
1481
1482 /* let the f/w know that the h/w is now under the control of the
1483 * driver. */
1484 igb_get_hw_control(adapter);
1485
9d5c8243
AK		 1486 strcpy(netdev->name, "eth%d");
1487 err = register_netdev(netdev);
1488 if (err)
1489 goto err_register;
1490
b168dfc5
JB		 1491 /* carrier off reporting is important to ethtool even BEFORE open */
1492 netif_carrier_off(netdev);
1493
421e02f0 1494#ifdef CONFIG_IGB_DCA
bbd98fe4 1495 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1496 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1497 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1498 igb_setup_dca(adapter);
1499 }
1500#endif
1501
38c845c7
PO		 1502 /*
1503 * Initialize hardware timer: we keep it running just in case
1504 * that some program needs it later on.
1505 */
1506 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1507 adapter->cycles.read = igb_read_clock;
1508 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1509 adapter->cycles.mult = 1;
1510 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1511 wr32(E1000_TIMINCA,
1512 (1<<24) |
1513 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1514#if 0
1515 /*
1516 * Avoid rollover while we initialize by resetting the time counter.
1517 */
1518 wr32(E1000_SYSTIML, 0x00000000);
1519 wr32(E1000_SYSTIMH, 0x00000000);
1520#else
1521 /*
1522 * Set registers so that rollover occurs soon to test this.
1523 */
1524 wr32(E1000_SYSTIML, 0x00000000);
1525 wr32(E1000_SYSTIMH, 0xFF800000);
1526#endif
1527 wrfl();
1528 timecounter_init(&adapter->clock,
1529 &adapter->cycles,
1530 ktime_to_ns(ktime_get_real()));
1531
33af6bcc
PO		 1532 /*
1533 * Synchronize our NIC clock against system wall clock. NIC
1534 * time stamp reading requires ~3us per sample, each sample
1535 * was pretty stable even under load => only require 10
1536 * samples for each offset comparison.
1537 */
1538 memset(&adapter->compare, 0, sizeof(adapter->compare));
1539 adapter->compare.source = &adapter->clock;
1540 adapter->compare.target = ktime_get_real;
1541 adapter->compare.num_samples = 10;
1542 timecompare_update(&adapter->compare, 0);
1543
38c845c7
PO		 1544#ifdef DEBUG
1545 {
1546 char buffer[160];
1547 printk(KERN_DEBUG
1548 "igb: %s: hw %p initialized timer\n",
1549 igb_get_time_str(adapter, buffer),
1550 &adapter->hw);
1551 }
1552#endif
1553
9d5c8243
AK		 1554 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1555 /* print bus type/speed/width info */
7c510e4b 1556 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1557 netdev->name,
1558 ((hw->bus.speed == e1000_bus_speed_2500)
1559 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1560 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1561 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1562 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1563 "unknown"),
7c510e4b 1564 netdev->dev_addr);
9d5c8243
AK		 1565
1566 igb_read_part_num(hw, &part_num);
1567 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1568 (part_num >> 8), (part_num & 0xff));
1569
1570 dev_info(&pdev->dev,
1571 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1572 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1573 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1574 adapter->num_rx_queues, adapter->num_tx_queues);
1575
9d5c8243
AK		 1576 return 0;
1577
1578err_register:
1579 igb_release_hw_control(adapter);
1580err_eeprom:
1581 if (!igb_check_reset_block(hw))
f5f4cf08 1582 igb_reset_phy(hw);
9d5c8243
AK		 1583
1584 if (hw->flash_address)
1585 iounmap(hw->flash_address);
1586
a88f10ec 1587 igb_free_queues(adapter);
9d5c8243 1588err_sw_init:
9d5c8243
AK		 1589 iounmap(hw->hw_addr);
1590err_ioremap:
1591 free_netdev(netdev);
1592err_alloc_etherdev:
aed5dec3
AD		 1593 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1594 IORESOURCE_MEM));
9d5c8243
AK		 1595err_pci_reg:
1596err_dma:
1597 pci_disable_device(pdev);
1598 return err;
1599}
1600
1601/**
1602 * igb_remove - Device Removal Routine
1603 * @pdev: PCI device information struct
1604 *
1605 * igb_remove is called by the PCI subsystem to alert the driver
1606 * that it should release a PCI device. The could be caused by a
1607 * Hot-Plug event, or because the driver is going to be removed from
1608 * memory.
1609 **/
1610static void __devexit igb_remove(struct pci_dev *pdev)
1611{
1612 struct net_device *netdev = pci_get_drvdata(pdev);
1613 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1614 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1615
1616 /* flush_scheduled work may reschedule our watchdog task, so
1617 * explicitly disable watchdog tasks from being rescheduled */
1618 set_bit(__IGB_DOWN, &adapter->state);
1619 del_timer_sync(&adapter->watchdog_timer);
1620 del_timer_sync(&adapter->phy_info_timer);
1621
1622 flush_scheduled_work();
1623
421e02f0 1624#ifdef CONFIG_IGB_DCA
7dfc16fa 1625 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1626 dev_info(&pdev->dev, "DCA disabled\n");
1627 dca_remove_requester(&pdev->dev);
7dfc16fa 1628 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1629 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1630 }
1631#endif
1632
9d5c8243
AK		 1633 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1634 * would have already happened in close and is redundant. */
1635 igb_release_hw_control(adapter);
1636
1637 unregister_netdev(netdev);
1638
f5f4cf08
AD		 1639 if (!igb_check_reset_block(&adapter->hw))
1640 igb_reset_phy(&adapter->hw);
9d5c8243 1641
9d5c8243
AK		 1642 igb_reset_interrupt_capability(adapter);
1643
a88f10ec 1644 igb_free_queues(adapter);
9d5c8243 1645
37680117
AD		 1646#ifdef CONFIG_PCI_IOV
1647 /* reclaim resources allocated to VFs */
1648 if (adapter->vf_data) {
1649 /* disable iov and allow time for transactions to clear */
1650 pci_disable_sriov(pdev);
1651 msleep(500);
1652
1653 kfree(adapter->vf_data);
1654 adapter->vf_data = NULL;
1655 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1656 msleep(100);
1657 dev_info(&pdev->dev, "IOV Disabled\n");
1658 }
1659#endif
28b0759c
AD		 1660 iounmap(hw->hw_addr);
1661 if (hw->flash_address)
1662 iounmap(hw->flash_address);
aed5dec3
AD		 1663 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1664 IORESOURCE_MEM));
9d5c8243
AK		 1665
1666 free_netdev(netdev);
1667
19d5afd4 1668 pci_disable_pcie_error_reporting(pdev);
40a914fa 1669
9d5c8243
AK		 1670 pci_disable_device(pdev);
1671}
1672
1673/**
1674 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1675 * @adapter: board private structure to initialize
1676 *
1677 * igb_sw_init initializes the Adapter private data structure.
1678 * Fields are initialized based on PCI device information and
1679 * OS network device settings (MTU size).
1680 **/
1681static int __devinit igb_sw_init(struct igb_adapter *adapter)
1682{
1683 struct e1000_hw *hw = &adapter->hw;
1684 struct net_device *netdev = adapter->netdev;
1685 struct pci_dev *pdev = adapter->pdev;
1686
1687 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1688
68fd9910
AD		 1689 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1690 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1691 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1692 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1693 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1694 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1695
661086df
PWJ		 1696 /* This call may decrease the number of queues depending on
1697 * interrupt mode. */
9d5c8243
AK		 1698 igb_set_interrupt_capability(adapter);
1699
1700 if (igb_alloc_queues(adapter)) {
1701 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1702 return -ENOMEM;
1703 }
1704
1705 /* Explicitly disable IRQ since the NIC can be in any state. */
1706 igb_irq_disable(adapter);
1707
1708 set_bit(__IGB_DOWN, &adapter->state);
1709 return 0;
1710}
1711
1712/**
1713 * igb_open - Called when a network interface is made active
1714 * @netdev: network interface device structure
1715 *
1716 * Returns 0 on success, negative value on failure
1717 *
1718 * The open entry point is called when a network interface is made
1719 * active by the system (IFF_UP). At this point all resources needed
1720 * for transmit and receive operations are allocated, the interrupt
1721 * handler is registered with the OS, the watchdog timer is started,
1722 * and the stack is notified that the interface is ready.
1723 **/
1724static int igb_open(struct net_device *netdev)
1725{
1726 struct igb_adapter *adapter = netdev_priv(netdev);
1727 struct e1000_hw *hw = &adapter->hw;
1728 int err;
1729 int i;
1730
1731 /* disallow open during test */
1732 if (test_bit(__IGB_TESTING, &adapter->state))
1733 return -EBUSY;
1734
b168dfc5
JB		 1735 netif_carrier_off(netdev);
1736
9d5c8243
AK		 1737 /* allocate transmit descriptors */
1738 err = igb_setup_all_tx_resources(adapter);
1739 if (err)
1740 goto err_setup_tx;
1741
1742 /* allocate receive descriptors */
1743 err = igb_setup_all_rx_resources(adapter);
1744 if (err)
1745 goto err_setup_rx;
1746
1747 /* e1000_power_up_phy(adapter); */
1748
1749 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1750 if ((adapter->hw.mng_cookie.status &
1751 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1752 igb_update_mng_vlan(adapter);
1753
1754 /* before we allocate an interrupt, we must be ready to handle it.
1755 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1756 * as soon as we call pci_request_irq, so we have to setup our
1757 * clean_rx handler before we do so. */
1758 igb_configure(adapter);
1759
4ae196df 1760 igb_vmm_control(adapter);
e1739522
AD		 1761 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1762
9d5c8243
AK		 1763 err = igb_request_irq(adapter);
1764 if (err)
1765 goto err_req_irq;
1766
1767 /* From here on the code is the same as igb_up() */
1768 clear_bit(__IGB_DOWN, &adapter->state);
1769
844290e5
PW		 1770 for (i = 0; i < adapter->num_rx_queues; i++)
1771 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1772
1773 /* Clear any pending interrupts. */
1774 rd32(E1000_ICR);
844290e5
PW		 1775
1776 igb_irq_enable(adapter);
1777
d55b53ff
JK		 1778 netif_tx_start_all_queues(netdev);
1779
9d5c8243
AK		 1780 /* Fire a link status change interrupt to start the watchdog. */
1781 wr32(E1000_ICS, E1000_ICS_LSC);
1782
1783 return 0;
1784
1785err_req_irq:
1786 igb_release_hw_control(adapter);
1787 /* e1000_power_down_phy(adapter); */
1788 igb_free_all_rx_resources(adapter);
1789err_setup_rx:
1790 igb_free_all_tx_resources(adapter);
1791err_setup_tx:
1792 igb_reset(adapter);
1793
1794 return err;
1795}
1796
1797/**
1798 * igb_close - Disables a network interface
1799 * @netdev: network interface device structure
1800 *
1801 * Returns 0, this is not allowed to fail
1802 *
1803 * The close entry point is called when an interface is de-activated
1804 * by the OS. The hardware is still under the driver's control, but
1805 * needs to be disabled. A global MAC reset is issued to stop the
1806 * hardware, and all transmit and receive resources are freed.
1807 **/
1808static int igb_close(struct net_device *netdev)
1809{
1810 struct igb_adapter *adapter = netdev_priv(netdev);
1811
1812 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1813 igb_down(adapter);
1814
1815 igb_free_irq(adapter);
1816
1817 igb_free_all_tx_resources(adapter);
1818 igb_free_all_rx_resources(adapter);
1819
1820 /* kill manageability vlan ID if supported, but not if a vlan with
1821 * the same ID is registered on the host OS (let 8021q kill it) */
1822 if ((adapter->hw.mng_cookie.status &
1823 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1824 !(adapter->vlgrp &&
1825 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1826 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1827
1828 return 0;
1829}
1830
1831/**
1832 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1833 * @adapter: board private structure
1834 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1835 *
1836 * Return 0 on success, negative on failure
1837 **/
9d5c8243
AK		 1838int igb_setup_tx_resources(struct igb_adapter *adapter,
1839 struct igb_ring *tx_ring)
1840{
1841 struct pci_dev *pdev = adapter->pdev;
1842 int size;
1843
1844 size = sizeof(struct igb_buffer) * tx_ring->count;
1845 tx_ring->buffer_info = vmalloc(size);
1846 if (!tx_ring->buffer_info)
1847 goto err;
1848 memset(tx_ring->buffer_info, 0, size);
1849
1850 /* round up to nearest 4K */
85e8d004 1851 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1852 tx_ring->size = ALIGN(tx_ring->size, 4096);
1853
1854 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1855 &tx_ring->dma);
1856
1857 if (!tx_ring->desc)
1858 goto err;
1859
1860 tx_ring->adapter = adapter;
1861 tx_ring->next_to_use = 0;
1862 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1863 return 0;
1864
1865err:
1866 vfree(tx_ring->buffer_info);
1867 dev_err(&adapter->pdev->dev,
1868 "Unable to allocate memory for the transmit descriptor ring\n");
1869 return -ENOMEM;
1870}
1871
1872/**
1873 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1874 * (Descriptors) for all queues
1875 * @adapter: board private structure
1876 *
1877 * Return 0 on success, negative on failure
1878 **/
1879static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1880{
1881 int i, err = 0;
661086df 1882 int r_idx;
9d5c8243
AK		 1883
1884 for (i = 0; i < adapter->num_tx_queues; i++) {
1885 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1886 if (err) {
1887 dev_err(&adapter->pdev->dev,
1888 "Allocation for Tx Queue %u failed\n", i);
1889 for (i--; i >= 0; i--)
3b644cf6 1890 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1891 break;
1892 }
1893 }
1894
661086df
PWJ		 1895 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1896 r_idx = i % adapter->num_tx_queues;
1897 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1898 }
9d5c8243
AK		 1899 return err;
1900}
1901
1902/**
1903 * igb_configure_tx - Configure transmit Unit after Reset
1904 * @adapter: board private structure
1905 *
1906 * Configure the Tx unit of the MAC after a reset.
1907 **/
1908static void igb_configure_tx(struct igb_adapter *adapter)
1909{
0e014cb1 1910 u64 tdba;
9d5c8243
AK		 1911 struct e1000_hw *hw = &adapter->hw;
1912 u32 tctl;
1913 u32 txdctl, txctrl;
26bc19ec 1914 int i, j;
9d5c8243
AK		 1915
1916 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1917 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1918 j = ring->reg_idx;
1919 wr32(E1000_TDLEN(j),
85e8d004 1920 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1921 tdba = ring->dma;
26bc19ec 1922 wr32(E1000_TDBAL(j),
73cd78f1 1923 tdba & 0x00000000ffffffffULL);
26bc19ec 1924 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1925
26bc19ec
AD		 1926 ring->head = E1000_TDH(j);
1927 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1928 writel(0, hw->hw_addr + ring->tail);
1929 writel(0, hw->hw_addr + ring->head);
26bc19ec 1930 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1931 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1932 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1933
1934 /* Turn off Relaxed Ordering on head write-backs. The
1935 * writebacks MUST be delivered in order or it will
1936 * completely screw up our bookeeping.
1937 */
26bc19ec 1938 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1939 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1940 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1941 }
1942
e1739522
AD		 1943 /* disable queue 0 to prevent tail bump w/o re-configuration */
1944 if (adapter->vfs_allocated_count)
1945 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1946
1947 /* Program the Transmit Control Register */
9d5c8243
AK		 1948 tctl = rd32(E1000_TCTL);
1949 tctl &= ~E1000_TCTL_CT;
1950 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1951 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1952
1953 igb_config_collision_dist(hw);
1954
1955 /* Setup Transmit Descriptor Settings for eop descriptor */
1956 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1957
1958 /* Enable transmits */
1959 tctl |= E1000_TCTL_EN;
1960
1961 wr32(E1000_TCTL, tctl);
1962}
1963
1964/**
1965 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1966 * @adapter: board private structure
1967 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1968 *
1969 * Returns 0 on success, negative on failure
1970 **/
9d5c8243
AK		 1971int igb_setup_rx_resources(struct igb_adapter *adapter,
1972 struct igb_ring *rx_ring)
1973{
1974 struct pci_dev *pdev = adapter->pdev;
1975 int size, desc_len;
1976
1977 size = sizeof(struct igb_buffer) * rx_ring->count;
1978 rx_ring->buffer_info = vmalloc(size);
1979 if (!rx_ring->buffer_info)
1980 goto err;
1981 memset(rx_ring->buffer_info, 0, size);
1982
1983 desc_len = sizeof(union e1000_adv_rx_desc);
1984
1985 /* Round up to nearest 4K */
1986 rx_ring->size = rx_ring->count * desc_len;
1987 rx_ring->size = ALIGN(rx_ring->size, 4096);
1988
1989 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1990 &rx_ring->dma);
1991
1992 if (!rx_ring->desc)
1993 goto err;
1994
1995 rx_ring->next_to_clean = 0;
1996 rx_ring->next_to_use = 0;
9d5c8243
AK		 1997
1998 rx_ring->adapter = adapter;
9d5c8243
AK		 1999
2000 return 0;
2001
2002err:
2003 vfree(rx_ring->buffer_info);
2004 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2005 "the receive descriptor ring\n");
2006 return -ENOMEM;
2007}
2008
2009/**
2010 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2011 * (Descriptors) for all queues
2012 * @adapter: board private structure
2013 *
2014 * Return 0 on success, negative on failure
2015 **/
2016static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2017{
2018 int i, err = 0;
2019
2020 for (i = 0; i < adapter->num_rx_queues; i++) {
2021 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2022 if (err) {
2023 dev_err(&adapter->pdev->dev,
2024 "Allocation for Rx Queue %u failed\n", i);
2025 for (i--; i >= 0; i--)
3b644cf6 2026 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2027 break;
2028 }
2029 }
2030
2031 return err;
2032}
2033
2034/**
2035 * igb_setup_rctl - configure the receive control registers
2036 * @adapter: Board private structure
2037 **/
2038static void igb_setup_rctl(struct igb_adapter *adapter)
2039{
2040 struct e1000_hw *hw = &adapter->hw;
2041 u32 rctl;
2042 u32 srrctl = 0;
77a22941 2043 int i;
9d5c8243
AK		 2044
2045 rctl = rd32(E1000_RCTL);
2046
2047 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2048 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2049
69d728ba 2050 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2051 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2052
87cb7e8c
AK		 2053 /*
2054 * enable stripping of CRC. It's unlikely this will break BMC
2055 * redirection as it did with e1000. Newer features require
2056 * that the HW strips the CRC.
73cd78f1 2057 */
87cb7e8c 2058 rctl |= E1000_RCTL_SECRC;
9d5c8243 2059
9b07f3d3 2060 /*
ec54d7d6 2061 * disable store bad packets and clear size bits.
9b07f3d3 2062 */
ec54d7d6 2063 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2064
ec54d7d6 2065 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 2066 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 2067
2068 /* Setup buffer sizes */
2069 switch (adapter->rx_buffer_len) {
2070 case IGB_RXBUFFER_256:
2071 rctl |= E1000_RCTL_SZ_256;
2072 break;
2073 case IGB_RXBUFFER_512:
2074 rctl |= E1000_RCTL_SZ_512;
2075 break;
2076 default:
2077 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2078 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2079 break;
9d5c8243
AK		 2080 }
2081
2082 /* 82575 and greater support packet-split where the protocol
2083 * header is placed in skb->data and the packet data is
2084 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2085 * In the case of a non-split, skb->data is linearly filled,
2086 * followed by the page buffers. Therefore, skb->data is
2087 * sized to hold the largest protocol header.
2088 */
2089 /* allocations using alloc_page take too long for regular MTU
2090 * so only enable packet split for jumbo frames */
ec54d7d6 2091 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2092 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2093 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2094 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2095 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2096 } else {
2097 adapter->rx_ps_hdr_size = 0;
2098 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2099 }
2100
e1739522
AD		 2101 /* Attention!!! For SR-IOV PF driver operations you must enable
2102 * queue drop for all VF and PF queues to prevent head of line blocking
2103 * if an un-trusted VF does not provide descriptors to hardware.
2104 */
2105 if (adapter->vfs_allocated_count) {
2106 u32 vmolr;
2107
e1739522
AD		 2108 /* set all queue drop enable bits */
2109 wr32(E1000_QDE, ALL_QUEUES);
2110 srrctl |= E1000_SRRCTL_DROP_EN;
2111
2112 /* disable queue 0 to prevent tail write w/o re-config */
2113 wr32(E1000_RXDCTL(0), 0);
2114
77a22941 2115 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2116 if (rctl & E1000_RCTL_LPE)
2117 vmolr |= E1000_VMOLR_LPE;
77a22941 2118 if (adapter->num_rx_queues > 1)
e1739522 2119 vmolr |= E1000_VMOLR_RSSE;
77a22941 2120 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2121 }
2122
26bc19ec 2123 for (i = 0; i < adapter->num_rx_queues; i++) {
77a22941 2124 int j = adapter->rx_ring[i].reg_idx;
26bc19ec
AD		 2125 wr32(E1000_SRRCTL(j), srrctl);
2126 }
9d5c8243
AK		 2127
2128 wr32(E1000_RCTL, rctl);
2129}
2130
e1739522
AD		 2131/**
2132 * igb_rlpml_set - set maximum receive packet size
2133 * @adapter: board private structure
2134 *
2135 * Configure maximum receivable packet size.
2136 **/
2137static void igb_rlpml_set(struct igb_adapter *adapter)
2138{
2139 u32 max_frame_size = adapter->max_frame_size;
2140 struct e1000_hw *hw = &adapter->hw;
2141 u16 pf_id = adapter->vfs_allocated_count;
2142
2143 if (adapter->vlgrp)
2144 max_frame_size += VLAN_TAG_SIZE;
2145
2146 /* if vfs are enabled we set RLPML to the largest possible request
2147 * size and set the VMOLR RLPML to the size we need */
2148 if (pf_id) {
2149 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2150 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2151 }
2152
2153 wr32(E1000_RLPML, max_frame_size);
2154}
2155
2156/**
2157 * igb_configure_vt_default_pool - Configure VT default pool
2158 * @adapter: board private structure
2159 *
2160 * Configure the default pool
2161 **/
2162static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2163{
2164 struct e1000_hw *hw = &adapter->hw;
2165 u16 pf_id = adapter->vfs_allocated_count;
2166 u32 vtctl;
2167
2168 /* not in sr-iov mode - do nothing */
2169 if (!pf_id)
2170 return;
2171
2172 vtctl = rd32(E1000_VT_CTL);
2173 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2174 E1000_VT_CTL_DISABLE_DEF_POOL);
2175 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2176 wr32(E1000_VT_CTL, vtctl);
2177}
2178
9d5c8243
AK		 2179/**
2180 * igb_configure_rx - Configure receive Unit after Reset
2181 * @adapter: board private structure
2182 *
2183 * Configure the Rx unit of the MAC after a reset.
2184 **/
2185static void igb_configure_rx(struct igb_adapter *adapter)
2186{
2187 u64 rdba;
2188 struct e1000_hw *hw = &adapter->hw;
2189 u32 rctl, rxcsum;
2190 u32 rxdctl;
9107584e 2191 int i;
9d5c8243
AK		 2192
2193 /* disable receives while setting up the descriptors */
2194 rctl = rd32(E1000_RCTL);
2195 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2196 wrfl();
2197 mdelay(10);
2198
2199 if (adapter->itr_setting > 3)
6eb5a7f1 2200 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2201
2202 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2203 * the Base and Length of the Rx Descriptor Ring */
2204 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2205 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2206 int j = ring->reg_idx;
9d5c8243 2207 rdba = ring->dma;
26bc19ec 2208 wr32(E1000_RDBAL(j),
73cd78f1 2209 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2210 wr32(E1000_RDBAH(j), rdba >> 32);
2211 wr32(E1000_RDLEN(j),
73cd78f1 2212 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2213
26bc19ec
AD		 2214 ring->head = E1000_RDH(j);
2215 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2216 writel(0, hw->hw_addr + ring->tail);
2217 writel(0, hw->hw_addr + ring->head);
2218
26bc19ec 2219 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2220 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2221 rxdctl &= 0xFFF00000;
2222 rxdctl |= IGB_RX_PTHRESH;
2223 rxdctl |= IGB_RX_HTHRESH << 8;
2224 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2225 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2226 }
2227
2228 if (adapter->num_rx_queues > 1) {
2229 u32 random[10];
2230 u32 mrqc;
2231 u32 j, shift;
2232 union e1000_reta {
2233 u32 dword;
2234 u8 bytes[4];
2235 } reta;
2236
2237 get_random_bytes(&random[0], 40);
2238
2d064c06
AD		 2239 if (hw->mac.type >= e1000_82576)
2240 shift = 0;
2241 else
2242 shift = 6;
9d5c8243
AK		 2243 for (j = 0; j < (32 * 4); j++) {
2244 reta.bytes[j & 3] =
26bc19ec 2245 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2246 if ((j & 3) == 3)
2247 writel(reta.dword,
2248 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2249 }
e1739522
AD		 2250 if (adapter->vfs_allocated_count)
2251 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2252 else
2253 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2254
2255 /* Fill out hash function seeds */
2256 for (j = 0; j < 10; j++)
2257 array_wr32(E1000_RSSRK(0), j, random[j]);
2258
2259 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2260 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2261 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2262 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2263 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2264 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2265 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2266 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2267
9d5c8243 2268 wr32(E1000_MRQC, mrqc);
2844f797 2269 } else if (adapter->vfs_allocated_count) {
e1739522 2270 /* Enable multi-queue for sr-iov */
2844f797 2271 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2272 }
2273
2844f797
AD		 2274 /* Enable Receive Checksum Offload for TCP and UDP */
2275 rxcsum = rd32(E1000_RXCSUM);
2276 /* Disable raw packet checksumming */
2277 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2278
2279 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2280 /* Enable Receive Checksum Offload for SCTP */
2281 rxcsum |= E1000_RXCSUM_CRCOFL;
2282
7beb0146 2283 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2284 wr32(E1000_RXCSUM, rxcsum);
2285
e1739522
AD		 2286 /* Set the default pool for the PF's first queue */
2287 igb_configure_vt_default_pool(adapter);
2288
26ad9178
AD		 2289 /* set the correct pool for the PF default MAC address in entry 0 */
2290 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2291 adapter->vfs_allocated_count);
2292
e1739522 2293 igb_rlpml_set(adapter);
9d5c8243
AK		 2294
2295 /* Enable Receives */
2296 wr32(E1000_RCTL, rctl);
2297}
2298
2299/**
2300 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2301 * @tx_ring: Tx descriptor ring for a specific queue
2302 *
2303 * Free all transmit software resources
2304 **/
68fd9910 2305void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2306{
3b644cf6 2307 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2308
3b644cf6 2309 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2310
2311 vfree(tx_ring->buffer_info);
2312 tx_ring->buffer_info = NULL;
2313
2314 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2315
2316 tx_ring->desc = NULL;
2317}
2318
2319/**
2320 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2321 * @adapter: board private structure
2322 *
2323 * Free all transmit software resources
2324 **/
2325static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2326{
2327 int i;
2328
2329 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2330 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2331}
2332
2333static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2334 struct igb_buffer *buffer_info)
2335{
65689fef 2336 buffer_info->dma = 0;
9d5c8243 2337 if (buffer_info->skb) {
65689fef
AD		 2338 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2339 DMA_TO_DEVICE);
9d5c8243
AK		 2340 dev_kfree_skb_any(buffer_info->skb);
2341 buffer_info->skb = NULL;
2342 }
2343 buffer_info->time_stamp = 0;
2344 /* buffer_info must be completely set up in the transmit path */
2345}
2346
2347/**
2348 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2349 * @tx_ring: ring to be cleaned
2350 **/
3b644cf6 2351static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2352{
3b644cf6 2353 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2354 struct igb_buffer *buffer_info;
2355 unsigned long size;
2356 unsigned int i;
2357
2358 if (!tx_ring->buffer_info)
2359 return;
2360 /* Free all the Tx ring sk_buffs */
2361
2362 for (i = 0; i < tx_ring->count; i++) {
2363 buffer_info = &tx_ring->buffer_info[i];
2364 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2365 }
2366
2367 size = sizeof(struct igb_buffer) * tx_ring->count;
2368 memset(tx_ring->buffer_info, 0, size);
2369
2370 /* Zero out the descriptor ring */
2371
2372 memset(tx_ring->desc, 0, tx_ring->size);
2373
2374 tx_ring->next_to_use = 0;
2375 tx_ring->next_to_clean = 0;
2376
2377 writel(0, adapter->hw.hw_addr + tx_ring->head);
2378 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2379}
2380
2381/**
2382 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2383 * @adapter: board private structure
2384 **/
2385static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2386{
2387 int i;
2388
2389 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2390 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2391}
2392
2393/**
2394 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2395 * @rx_ring: ring to clean the resources from
2396 *
2397 * Free all receive software resources
2398 **/
68fd9910 2399void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2400{
3b644cf6 2401 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2402
3b644cf6 2403 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2404
2405 vfree(rx_ring->buffer_info);
2406 rx_ring->buffer_info = NULL;
2407
2408 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2409
2410 rx_ring->desc = NULL;
2411}
2412
2413/**
2414 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2415 * @adapter: board private structure
2416 *
2417 * Free all receive software resources
2418 **/
2419static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2420{
2421 int i;
2422
2423 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2424 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2425}
2426
2427/**
2428 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2429 * @rx_ring: ring to free buffers from
2430 **/
3b644cf6 2431static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2432{
3b644cf6 2433 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2434 struct igb_buffer *buffer_info;
2435 struct pci_dev *pdev = adapter->pdev;
2436 unsigned long size;
2437 unsigned int i;
2438
2439 if (!rx_ring->buffer_info)
2440 return;
2441 /* Free all the Rx ring sk_buffs */
2442 for (i = 0; i < rx_ring->count; i++) {
2443 buffer_info = &rx_ring->buffer_info[i];
2444 if (buffer_info->dma) {
2445 if (adapter->rx_ps_hdr_size)
2446 pci_unmap_single(pdev, buffer_info->dma,
2447 adapter->rx_ps_hdr_size,
2448 PCI_DMA_FROMDEVICE);
2449 else
2450 pci_unmap_single(pdev, buffer_info->dma,
2451 adapter->rx_buffer_len,
2452 PCI_DMA_FROMDEVICE);
2453 buffer_info->dma = 0;
2454 }
2455
2456 if (buffer_info->skb) {
2457 dev_kfree_skb(buffer_info->skb);
2458 buffer_info->skb = NULL;
2459 }
2460 if (buffer_info->page) {
bf36c1a0
AD		 2461 if (buffer_info->page_dma)
2462 pci_unmap_page(pdev, buffer_info->page_dma,
2463 PAGE_SIZE / 2,
2464 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2465 put_page(buffer_info->page);
2466 buffer_info->page = NULL;
2467 buffer_info->page_dma = 0;
bf36c1a0 2468 buffer_info->page_offset = 0;
9d5c8243
AK		 2469 }
2470 }
2471
9d5c8243
AK		 2472 size = sizeof(struct igb_buffer) * rx_ring->count;
2473 memset(rx_ring->buffer_info, 0, size);
2474
2475 /* Zero out the descriptor ring */
2476 memset(rx_ring->desc, 0, rx_ring->size);
2477
2478 rx_ring->next_to_clean = 0;
2479 rx_ring->next_to_use = 0;
2480
2481 writel(0, adapter->hw.hw_addr + rx_ring->head);
2482 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2483}
2484
2485/**
2486 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2487 * @adapter: board private structure
2488 **/
2489static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2490{
2491 int i;
2492
2493 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2494 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2495}
2496
2497/**
2498 * igb_set_mac - Change the Ethernet Address of the NIC
2499 * @netdev: network interface device structure
2500 * @p: pointer to an address structure
2501 *
2502 * Returns 0 on success, negative on failure
2503 **/
2504static int igb_set_mac(struct net_device *netdev, void *p)
2505{
2506 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2507 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2508 struct sockaddr *addr = p;
2509
2510 if (!is_valid_ether_addr(addr->sa_data))
2511 return -EADDRNOTAVAIL;
2512
2513 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2514 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2515
26ad9178
AD		 2516 /* set the correct pool for the new PF MAC address in entry 0 */
2517 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2518 adapter->vfs_allocated_count);
e1739522 2519
9d5c8243
AK		 2520 return 0;
2521}
2522
2523/**
ff41f8dc 2524 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
9d5c8243
AK		 2525 * @netdev: network interface device structure
2526 *
ff41f8dc
AD		 2527 * The set_rx_mode entry point is called whenever the unicast or multicast
2528 * address lists or the network interface flags are updated. This routine is
2529 * responsible for configuring the hardware for proper unicast, multicast,
9d5c8243
AK		 2530 * promiscuous mode, and all-multi behavior.
2531 **/
ff41f8dc 2532static void igb_set_rx_mode(struct net_device *netdev)
9d5c8243
AK		 2533{
2534 struct igb_adapter *adapter = netdev_priv(netdev);
2535 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 2536 unsigned int rar_entries = hw->mac.rar_entry_count -
2537 (adapter->vfs_allocated_count + 1);
2538 struct dev_mc_list *mc_ptr = netdev->mc_list;
c5cd11e3 2539 u8 *mta_list = NULL;
9d5c8243
AK		 2540 u32 rctl;
2541 int i;
2542
2543 /* Check for Promiscuous and All Multicast modes */
9d5c8243
AK		 2544 rctl = rd32(E1000_RCTL);
2545
746b9f02 2546 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2547 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2548 rctl &= ~E1000_RCTL_VFE;
2549 } else {
ff41f8dc 2550 if (netdev->flags & IFF_ALLMULTI)
746b9f02 2551 rctl |= E1000_RCTL_MPE;
ff41f8dc
AD		 2552 else
2553 rctl &= ~E1000_RCTL_MPE;
2554
2555 if (netdev->uc.count > rar_entries)
2556 rctl |= E1000_RCTL_UPE;
2557 else
746b9f02 2558 rctl &= ~E1000_RCTL_UPE;
78ed11a5 2559 rctl |= E1000_RCTL_VFE;
746b9f02 2560 }
9d5c8243
AK		 2561 wr32(E1000_RCTL, rctl);
2562
ff41f8dc
AD		 2563 if (netdev->uc.count && rar_entries) {
2564 struct netdev_hw_addr *ha;
2565 list_for_each_entry(ha, &netdev->uc.list, list) {
2566 if (!rar_entries)
2567 break;
26ad9178
AD		 2568 igb_rar_set_qsel(adapter, ha->addr,
2569 rar_entries--,
2570 adapter->vfs_allocated_count);
ff41f8dc
AD		 2571 }
2572 }
2573 /* write the addresses in reverse order to avoid write combining */
2574 for (; rar_entries > 0 ; rar_entries--) {
2575 wr32(E1000_RAH(rar_entries), 0);
2576 wr32(E1000_RAL(rar_entries), 0);
2577 }
2578 wrfl();
2579
28fc06f5
AD		 2580 if (!netdev->mc_count) {
2581 /* nothing to program, so clear mc list */
2582 igb_update_mc_addr_list(hw, NULL, 0);
2583 igb_restore_vf_multicasts(adapter);
2584 return;
2585 }
2586
2587 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2588 if (!mta_list) {
2589 dev_err(&adapter->pdev->dev,
2590 "failed to allocate multicast filter list\n");
2591 return;
9d5c8243
AK		 2592 }
2593
9d5c8243 2594 /* The shared function expects a packed array of only addresses. */
9d5c8243
AK		 2595 for (i = 0; i < netdev->mc_count; i++) {
2596 if (!mc_ptr)
2597 break;
2598 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2599 mc_ptr = mc_ptr->next;
2600 }
28fc06f5 2601 igb_update_mc_addr_list(hw, mta_list, i);
9d5c8243 2602 kfree(mta_list);
28fc06f5 2603 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2604}
2605
2606/* Need to wait a few seconds after link up to get diagnostic information from
2607 * the phy */
2608static void igb_update_phy_info(unsigned long data)
2609{
2610 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2611 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2612}
2613
4d6b725e
AD		 2614/**
2615 * igb_has_link - check shared code for link and determine up/down
2616 * @adapter: pointer to driver private info
2617 **/
2618static bool igb_has_link(struct igb_adapter *adapter)
2619{
2620 struct e1000_hw *hw = &adapter->hw;
2621 bool link_active = false;
2622 s32 ret_val = 0;
2623
2624 /* get_link_status is set on LSC (link status) interrupt or
2625 * rx sequence error interrupt. get_link_status will stay
2626 * false until the e1000_check_for_link establishes link
2627 * for copper adapters ONLY
2628 */
2629 switch (hw->phy.media_type) {
2630 case e1000_media_type_copper:
2631 if (hw->mac.get_link_status) {
2632 ret_val = hw->mac.ops.check_for_link(hw);
2633 link_active = !hw->mac.get_link_status;
2634 } else {
2635 link_active = true;
2636 }
2637 break;
4d6b725e
AD		 2638 case e1000_media_type_internal_serdes:
2639 ret_val = hw->mac.ops.check_for_link(hw);
2640 link_active = hw->mac.serdes_has_link;
2641 break;
2642 default:
2643 case e1000_media_type_unknown:
2644 break;
2645 }
2646
2647 return link_active;
2648}
2649
9d5c8243
AK		 2650/**
2651 * igb_watchdog - Timer Call-back
2652 * @data: pointer to adapter cast into an unsigned long
2653 **/
2654static void igb_watchdog(unsigned long data)
2655{
2656 struct igb_adapter *adapter = (struct igb_adapter *)data;
2657 /* Do the rest outside of interrupt context */
2658 schedule_work(&adapter->watchdog_task);
2659}
2660
2661static void igb_watchdog_task(struct work_struct *work)
2662{
2663 struct igb_adapter *adapter = container_of(work,
2664 struct igb_adapter, watchdog_task);
2665 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2666 struct net_device *netdev = adapter->netdev;
2667 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2668 u32 link;
7a6ea550 2669 u32 eics = 0;
7a6ea550 2670 int i;
9d5c8243 2671
4d6b725e
AD		 2672 link = igb_has_link(adapter);
2673 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2674 goto link_up;
2675
9d5c8243
AK		 2676 if (link) {
2677 if (!netif_carrier_ok(netdev)) {
2678 u32 ctrl;
2679 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2680 &adapter->link_speed,
2681 &adapter->link_duplex);
2682
2683 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2684 /* Links status message must follow this format */
2685 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2686 "Flow Control: %s\n",
527d47c1 2687 netdev->name,
9d5c8243
AK		 2688 adapter->link_speed,
2689 adapter->link_duplex == FULL_DUPLEX ?
2690 "Full Duplex" : "Half Duplex",
2691 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2692 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2693 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2694 E1000_CTRL_TFCE) ? "TX" : "None")));
2695
2696 /* tweak tx_queue_len according to speed/duplex and
2697 * adjust the timeout factor */
2698 netdev->tx_queue_len = adapter->tx_queue_len;
2699 adapter->tx_timeout_factor = 1;
2700 switch (adapter->link_speed) {
2701 case SPEED_10:
2702 netdev->tx_queue_len = 10;
2703 adapter->tx_timeout_factor = 14;
2704 break;
2705 case SPEED_100:
2706 netdev->tx_queue_len = 100;
2707 /* maybe add some timeout factor ? */
2708 break;
2709 }
2710
2711 netif_carrier_on(netdev);
9d5c8243 2712
4ae196df
AD		 2713 igb_ping_all_vfs(adapter);
2714
4b1a9877 2715 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2716 if (!test_bit(__IGB_DOWN, &adapter->state))
2717 mod_timer(&adapter->phy_info_timer,
2718 round_jiffies(jiffies + 2 * HZ));
2719 }
2720 } else {
2721 if (netif_carrier_ok(netdev)) {
2722 adapter->link_speed = 0;
2723 adapter->link_duplex = 0;
527d47c1
AD		 2724 /* Links status message must follow this format */
2725 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2726 netdev->name);
9d5c8243 2727 netif_carrier_off(netdev);
4b1a9877 2728
4ae196df
AD		 2729 igb_ping_all_vfs(adapter);
2730
4b1a9877 2731 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2732 if (!test_bit(__IGB_DOWN, &adapter->state))
2733 mod_timer(&adapter->phy_info_timer,
2734 round_jiffies(jiffies + 2 * HZ));
2735 }
2736 }
2737
2738link_up:
2739 igb_update_stats(adapter);
2740
4b1a9877 2741 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2742 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2743 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2744 adapter->colc_old = adapter->stats.colc;
2745
2746 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2747 adapter->gorc_old = adapter->stats.gorc;
2748 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2749 adapter->gotc_old = adapter->stats.gotc;
2750
2751 igb_update_adaptive(&adapter->hw);
2752
2753 if (!netif_carrier_ok(netdev)) {
c493ea45 2754 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 2755 /* We've lost link, so the controller stops DMA,
2756 * but we've got queued Tx work that's never going
2757 * to get done, so reset controller to flush Tx.
2758 * (Do the reset outside of interrupt context). */
2759 adapter->tx_timeout_count++;
2760 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 2761 /* return immediately since reset is imminent */
2762 return;
9d5c8243
AK		 2763 }
2764 }
2765
2766 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2767 if (adapter->msix_entries) {
2768 for (i = 0; i < adapter->num_rx_queues; i++)
2769 eics |= adapter->rx_ring[i].eims_value;
2770 wr32(E1000_EICS, eics);
2771 } else {
2772 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2773 }
9d5c8243
AK		 2774
2775 /* Force detection of hung controller every watchdog period */
2776 tx_ring->detect_tx_hung = true;
2777
2778 /* Reset the timer */
2779 if (!test_bit(__IGB_DOWN, &adapter->state))
2780 mod_timer(&adapter->watchdog_timer,
2781 round_jiffies(jiffies + 2 * HZ));
2782}
2783
2784enum latency_range {
2785 lowest_latency = 0,
2786 low_latency = 1,
2787 bulk_latency = 2,
2788 latency_invalid = 255
2789};
2790
2791
6eb5a7f1
AD		 2792/**
2793 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2794 *
2795 * Stores a new ITR value based on strictly on packet size. This
2796 * algorithm is less sophisticated than that used in igb_update_itr,
2797 * due to the difficulty of synchronizing statistics across multiple
2798 * receive rings. The divisors and thresholds used by this fuction
2799 * were determined based on theoretical maximum wire speed and testing
2800 * data, in order to minimize response time while increasing bulk
2801 * throughput.
2802 * This functionality is controlled by the InterruptThrottleRate module
2803 * parameter (see igb_param.c)
2804 * NOTE: This function is called only when operating in a multiqueue
2805 * receive environment.
2806 * @rx_ring: pointer to ring
2807 **/
2808static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2809{
6eb5a7f1
AD		 2810 int new_val = rx_ring->itr_val;
2811 int avg_wire_size = 0;
2812 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2813
6eb5a7f1
AD		 2814 if (!rx_ring->total_packets)
2815 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2816
6eb5a7f1
AD		 2817 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2818 * ints/sec - ITR timer value of 120 ticks.
2819 */
2820 if (adapter->link_speed != SPEED_1000) {
2821 new_val = 120;
2822 goto set_itr_val;
9d5c8243 2823 }
6eb5a7f1 2824 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2825
6eb5a7f1
AD		 2826 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2827 avg_wire_size += 24;
2828
2829 /* Don't starve jumbo frames */
2830 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2831
6eb5a7f1
AD		 2832 /* Give a little boost to mid-size frames */
2833 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2834 new_val = avg_wire_size / 3;
2835 else
2836 new_val = avg_wire_size / 2;
9d5c8243 2837
6eb5a7f1 2838set_itr_val:
9d5c8243
AK		 2839 if (new_val != rx_ring->itr_val) {
2840 rx_ring->itr_val = new_val;
6eb5a7f1 2841 rx_ring->set_itr = 1;
9d5c8243 2842 }
6eb5a7f1
AD		 2843clear_counts:
2844 rx_ring->total_bytes = 0;
2845 rx_ring->total_packets = 0;
9d5c8243
AK		 2846}
2847
2848/**
2849 * igb_update_itr - update the dynamic ITR value based on statistics
2850 * Stores a new ITR value based on packets and byte
2851 * counts during the last interrupt. The advantage of per interrupt
2852 * computation is faster updates and more accurate ITR for the current
2853 * traffic pattern. Constants in this function were computed
2854 * based on theoretical maximum wire speed and thresholds were set based
2855 * on testing data as well as attempting to minimize response time
2856 * while increasing bulk throughput.
2857 * this functionality is controlled by the InterruptThrottleRate module
2858 * parameter (see igb_param.c)
2859 * NOTE: These calculations are only valid when operating in a single-
2860 * queue environment.
2861 * @adapter: pointer to adapter
2862 * @itr_setting: current adapter->itr
2863 * @packets: the number of packets during this measurement interval
2864 * @bytes: the number of bytes during this measurement interval
2865 **/
2866static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2867 int packets, int bytes)
2868{
2869 unsigned int retval = itr_setting;
2870
2871 if (packets == 0)
2872 goto update_itr_done;
2873
2874 switch (itr_setting) {
2875 case lowest_latency:
2876 /* handle TSO and jumbo frames */
2877 if (bytes/packets > 8000)
2878 retval = bulk_latency;
2879 else if ((packets < 5) && (bytes > 512))
2880 retval = low_latency;
2881 break;
2882 case low_latency: /* 50 usec aka 20000 ints/s */
2883 if (bytes > 10000) {
2884 /* this if handles the TSO accounting */
2885 if (bytes/packets > 8000) {
2886 retval = bulk_latency;
2887 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2888 retval = bulk_latency;
2889 } else if ((packets > 35)) {
2890 retval = lowest_latency;
2891 }
2892 } else if (bytes/packets > 2000) {
2893 retval = bulk_latency;
2894 } else if (packets <= 2 && bytes < 512) {
2895 retval = lowest_latency;
2896 }
2897 break;
2898 case bulk_latency: /* 250 usec aka 4000 ints/s */
2899 if (bytes > 25000) {
2900 if (packets > 35)
2901 retval = low_latency;
1e5c3d21 2902 } else if (bytes < 1500) {
9d5c8243
AK		 2903 retval = low_latency;
2904 }
2905 break;
2906 }
2907
2908update_itr_done:
2909 return retval;
2910}
2911
6eb5a7f1 2912static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2913{
2914 u16 current_itr;
2915 u32 new_itr = adapter->itr;
2916
2917 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2918 if (adapter->link_speed != SPEED_1000) {
2919 current_itr = 0;
2920 new_itr = 4000;
2921 goto set_itr_now;
2922 }
2923
2924 adapter->rx_itr = igb_update_itr(adapter,
2925 adapter->rx_itr,
2926 adapter->rx_ring->total_packets,
2927 adapter->rx_ring->total_bytes);
9d5c8243 2928
6eb5a7f1 2929 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2930 adapter->tx_itr = igb_update_itr(adapter,
2931 adapter->tx_itr,
2932 adapter->tx_ring->total_packets,
2933 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2934 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2935 } else {
2936 current_itr = adapter->rx_itr;
2937 }
2938
6eb5a7f1 2939 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2940 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2941 current_itr = low_latency;
2942
9d5c8243
AK		 2943 switch (current_itr) {
2944 /* counts and packets in update_itr are dependent on these numbers */
2945 case lowest_latency:
78b1f607 2946 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 2947 break;
2948 case low_latency:
78b1f607 2949 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 2950 break;
2951 case bulk_latency:
78b1f607 2952 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 2953 break;
2954 default:
2955 break;
2956 }
2957
2958set_itr_now:
6eb5a7f1
AD		 2959 adapter->rx_ring->total_bytes = 0;
2960 adapter->rx_ring->total_packets = 0;
2961 if (adapter->rx_ring->buddy) {
2962 adapter->rx_ring->buddy->total_bytes = 0;
2963 adapter->rx_ring->buddy->total_packets = 0;
2964 }
2965
9d5c8243
AK		 2966 if (new_itr != adapter->itr) {
2967 /* this attempts to bias the interrupt rate towards Bulk
2968 * by adding intermediate steps when interrupt rate is
2969 * increasing */
2970 new_itr = new_itr > adapter->itr ?
78b1f607
AD		 2971 max((new_itr * adapter->itr) /
2972 (new_itr + (adapter->itr >> 2)), new_itr) :
9d5c8243
AK		 2973 new_itr;
2974 /* Don't write the value here; it resets the adapter's
2975 * internal timer, and causes us to delay far longer than
2976 * we should between interrupts. Instead, we write the ITR
2977 * value at the beginning of the next interrupt so the timing
2978 * ends up being correct.
2979 */
2980 adapter->itr = new_itr;
78b1f607 2981 adapter->rx_ring->itr_val = new_itr;
6eb5a7f1 2982 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2983 }
2984
2985 return;
2986}
2987
2988
2989#define IGB_TX_FLAGS_CSUM 0x00000001
2990#define IGB_TX_FLAGS_VLAN 0x00000002
2991#define IGB_TX_FLAGS_TSO 0x00000004
2992#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 2993#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 2994#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2995#define IGB_TX_FLAGS_VLAN_SHIFT 16
2996
2997static inline int igb_tso_adv(struct igb_adapter *adapter,
2998 struct igb_ring *tx_ring,
2999 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3000{
3001 struct e1000_adv_tx_context_desc *context_desc;
3002 unsigned int i;
3003 int err;
3004 struct igb_buffer *buffer_info;
3005 u32 info = 0, tu_cmd = 0;
3006 u32 mss_l4len_idx, l4len;
3007 *hdr_len = 0;
3008
3009 if (skb_header_cloned(skb)) {
3010 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3011 if (err)
3012 return err;
3013 }
3014
3015 l4len = tcp_hdrlen(skb);
3016 *hdr_len += l4len;
3017
3018 if (skb->protocol == htons(ETH_P_IP)) {
3019 struct iphdr *iph = ip_hdr(skb);
3020 iph->tot_len = 0;
3021 iph->check = 0;
3022 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3023 iph->daddr, 0,
3024 IPPROTO_TCP,
3025 0);
3026 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3027 ipv6_hdr(skb)->payload_len = 0;
3028 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3029 &ipv6_hdr(skb)->daddr,
3030 0, IPPROTO_TCP, 0);
3031 }
3032
3033 i = tx_ring->next_to_use;
3034
3035 buffer_info = &tx_ring->buffer_info[i];
3036 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3037 /* VLAN MACLEN IPLEN */
3038 if (tx_flags & IGB_TX_FLAGS_VLAN)
3039 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3040 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3041 *hdr_len += skb_network_offset(skb);
3042 info |= skb_network_header_len(skb);
3043 *hdr_len += skb_network_header_len(skb);
3044 context_desc->vlan_macip_lens = cpu_to_le32(info);
3045
3046 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3047 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3048
3049 if (skb->protocol == htons(ETH_P_IP))
3050 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3051 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3052
3053 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3054
3055 /* MSS L4LEN IDX */
3056 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3057 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3058
73cd78f1 3059 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3060 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3061 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3062
3063 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3064 context_desc->seqnum_seed = 0;
3065
3066 buffer_info->time_stamp = jiffies;
0e014cb1 3067 buffer_info->next_to_watch = i;
9d5c8243
AK		 3068 buffer_info->dma = 0;
3069 i++;
3070 if (i == tx_ring->count)
3071 i = 0;
3072
3073 tx_ring->next_to_use = i;
3074
3075 return true;
3076}
3077
3078static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3079 struct igb_ring *tx_ring,
3080 struct sk_buff *skb, u32 tx_flags)
3081{
3082 struct e1000_adv_tx_context_desc *context_desc;
3083 unsigned int i;
3084 struct igb_buffer *buffer_info;
3085 u32 info = 0, tu_cmd = 0;
3086
3087 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3088 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3089 i = tx_ring->next_to_use;
3090 buffer_info = &tx_ring->buffer_info[i];
3091 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3092
3093 if (tx_flags & IGB_TX_FLAGS_VLAN)
3094 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3095 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3096 if (skb->ip_summed == CHECKSUM_PARTIAL)
3097 info |= skb_network_header_len(skb);
3098
3099 context_desc->vlan_macip_lens = cpu_to_le32(info);
3100
3101 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3102
3103 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3104 __be16 protocol;
3105
3106 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3107 const struct vlan_ethhdr *vhdr =
3108 (const struct vlan_ethhdr*)skb->data;
3109
3110 protocol = vhdr->h_vlan_encapsulated_proto;
3111 } else {
3112 protocol = skb->protocol;
3113 }
3114
3115 switch (protocol) {
09640e63 3116 case cpu_to_be16(ETH_P_IP):
9d5c8243 3117 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3118 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3119 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3120 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3121 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3122 break;
09640e63 3123 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3124 /* XXX what about other V6 headers?? */
3125 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3126 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3127 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3128 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3129 break;
3130 default:
3131 if (unlikely(net_ratelimit()))
3132 dev_warn(&adapter->pdev->dev,
3133 "partial checksum but proto=%x!\n",
3134 skb->protocol);
3135 break;
3136 }
9d5c8243
AK		 3137 }
3138
3139 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3140 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3141 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3142 context_desc->mss_l4len_idx =
3143 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3144 else
3145 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3146
3147 buffer_info->time_stamp = jiffies;
0e014cb1 3148 buffer_info->next_to_watch = i;
9d5c8243
AK		 3149 buffer_info->dma = 0;
3150
3151 i++;
3152 if (i == tx_ring->count)
3153 i = 0;
3154 tx_ring->next_to_use = i;
3155
3156 return true;
3157 }
9d5c8243
AK		 3158 return false;
3159}
3160
3161#define IGB_MAX_TXD_PWR 16
3162#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3163
3164static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3165 struct igb_ring *tx_ring, struct sk_buff *skb,
3166 unsigned int first)
9d5c8243
AK		 3167{
3168 struct igb_buffer *buffer_info;
3169 unsigned int len = skb_headlen(skb);
3170 unsigned int count = 0, i;
3171 unsigned int f;
65689fef 3172 dma_addr_t *map;
9d5c8243
AK		 3173
3174 i = tx_ring->next_to_use;
3175
65689fef
AD		 3176 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3177 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3178 return 0;
3179 }
3180
3181 map = skb_shinfo(skb)->dma_maps;
3182
9d5c8243
AK		 3183 buffer_info = &tx_ring->buffer_info[i];
3184 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3185 buffer_info->length = len;
3186 /* set time_stamp *before* dma to help avoid a possible race */
3187 buffer_info->time_stamp = jiffies;
0e014cb1 3188 buffer_info->next_to_watch = i;
042a53a9 3189 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3190
3191 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3192 struct skb_frag_struct *frag;
3193
65689fef
AD		 3194 i++;
3195 if (i == tx_ring->count)
3196 i = 0;
3197
9d5c8243
AK		 3198 frag = &skb_shinfo(skb)->frags[f];
3199 len = frag->size;
3200
3201 buffer_info = &tx_ring->buffer_info[i];
3202 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3203 buffer_info->length = len;
3204 buffer_info->time_stamp = jiffies;
0e014cb1 3205 buffer_info->next_to_watch = i;
65689fef 3206 buffer_info->dma = map[count];
9d5c8243 3207 count++;
9d5c8243
AK		 3208 }
3209
9d5c8243 3210 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3211 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3212
042a53a9 3213 return count + 1;
9d5c8243
AK		 3214}
3215
3216static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3217 struct igb_ring *tx_ring,
3218 int tx_flags, int count, u32 paylen,
3219 u8 hdr_len)
3220{
3221 union e1000_adv_tx_desc *tx_desc = NULL;
3222 struct igb_buffer *buffer_info;
3223 u32 olinfo_status = 0, cmd_type_len;
3224 unsigned int i;
3225
3226 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3227 E1000_ADVTXD_DCMD_DEXT);
3228
3229 if (tx_flags & IGB_TX_FLAGS_VLAN)
3230 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3231
33af6bcc
PO		 3232 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3233 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3234
9d5c8243
AK		 3235 if (tx_flags & IGB_TX_FLAGS_TSO) {
3236 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3237
3238 /* insert tcp checksum */
3239 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3240
3241 /* insert ip checksum */
3242 if (tx_flags & IGB_TX_FLAGS_IPV4)
3243 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3244
3245 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3246 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3247 }
3248
7dfc16fa
AD		 3249 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3250 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3251 IGB_TX_FLAGS_VLAN)))
661086df 3252 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3253
3254 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3255
3256 i = tx_ring->next_to_use;
3257 while (count--) {
3258 buffer_info = &tx_ring->buffer_info[i];
3259 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3260 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3261 tx_desc->read.cmd_type_len =
3262 cpu_to_le32(cmd_type_len | buffer_info->length);
3263 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3264 i++;
3265 if (i == tx_ring->count)
3266 i = 0;
3267 }
3268
3269 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3270 /* Force memory writes to complete before letting h/w
3271 * know there are new descriptors to fetch. (Only
3272 * applicable for weak-ordered memory model archs,
3273 * such as IA-64). */
3274 wmb();
3275
3276 tx_ring->next_to_use = i;
3277 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3278 /* we need this if more than one processor can write to our tail
3279 * at a time, it syncronizes IO on IA64/Altix systems */
3280 mmiowb();
3281}
3282
3283static int __igb_maybe_stop_tx(struct net_device *netdev,
3284 struct igb_ring *tx_ring, int size)
3285{
3286 struct igb_adapter *adapter = netdev_priv(netdev);
3287
661086df 3288 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3289
9d5c8243
AK		 3290 /* Herbert's original patch had:
3291 * smp_mb__after_netif_stop_queue();
3292 * but since that doesn't exist yet, just open code it. */
3293 smp_mb();
3294
3295 /* We need to check again in a case another CPU has just
3296 * made room available. */
c493ea45 3297 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3298 return -EBUSY;
3299
3300 /* A reprieve! */
661086df 3301 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3302 ++adapter->restart_queue;
3303 return 0;
3304}
3305
3306static int igb_maybe_stop_tx(struct net_device *netdev,
3307 struct igb_ring *tx_ring, int size)
3308{
c493ea45 3309 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3310 return 0;
3311 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3312}
3313
3b29a56d
SH		 3314static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3315 struct net_device *netdev,
3316 struct igb_ring *tx_ring)
9d5c8243
AK		 3317{
3318 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3319 unsigned int first;
9d5c8243 3320 unsigned int tx_flags = 0;
9d5c8243 3321 u8 hdr_len = 0;
65689fef 3322 int count = 0;
9d5c8243 3323 int tso = 0;
33af6bcc 3324 union skb_shared_tx *shtx;
9d5c8243 3325
9d5c8243
AK		 3326 if (test_bit(__IGB_DOWN, &adapter->state)) {
3327 dev_kfree_skb_any(skb);
3328 return NETDEV_TX_OK;
3329 }
3330
3331 if (skb->len <= 0) {
3332 dev_kfree_skb_any(skb);
3333 return NETDEV_TX_OK;
3334 }
3335
9d5c8243
AK		 3336 /* need: 1 descriptor per page,
3337 * + 2 desc gap to keep tail from touching head,
3338 * + 1 desc for skb->data,
3339 * + 1 desc for context descriptor,
3340 * otherwise try next time */
3341 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3342 /* this is a hard error */
9d5c8243
AK		 3343 return NETDEV_TX_BUSY;
3344 }
33af6bcc
PO		 3345
3346 /*
3347 * TODO: check that there currently is no other packet with
3348 * time stamping in the queue
3349 *
3350 * When doing time stamping, keep the connection to the socket
3351 * a while longer: it is still needed by skb_hwtstamp_tx(),
3352 * called either in igb_tx_hwtstamp() or by our caller when
3353 * doing software time stamping.
3354 */
3355 shtx = skb_tx(skb);
3356 if (unlikely(shtx->hardware)) {
3357 shtx->in_progress = 1;
3358 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3359 }
9d5c8243
AK		 3360
3361 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3362 tx_flags |= IGB_TX_FLAGS_VLAN;
3363 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3364 }
3365
661086df
PWJ		 3366 if (skb->protocol == htons(ETH_P_IP))
3367 tx_flags |= IGB_TX_FLAGS_IPV4;
3368
0e014cb1 3369 first = tx_ring->next_to_use;
9d5c8243
AK		 3370 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3371 &hdr_len) : 0;
3372
3373 if (tso < 0) {
3374 dev_kfree_skb_any(skb);
9d5c8243
AK		 3375 return NETDEV_TX_OK;
3376 }
3377
3378 if (tso)
3379 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3380 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3381 (skb->ip_summed == CHECKSUM_PARTIAL))
3382 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3383
65689fef
AD		 3384 /*
3385 * count reflects descriptors mapped, if 0 then mapping error
3386 * has occured and we need to rewind the descriptor queue
3387 */
3388 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3389
3390 if (count) {
3391 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3392 skb->len, hdr_len);
65689fef
AD		 3393 /* Make sure there is space in the ring for the next send. */
3394 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3395 } else {
3396 dev_kfree_skb_any(skb);
3397 tx_ring->buffer_info[first].time_stamp = 0;
3398 tx_ring->next_to_use = first;
3399 }
9d5c8243 3400
9d5c8243
AK		 3401 return NETDEV_TX_OK;
3402}
3403
3b29a56d
SH		 3404static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3405 struct net_device *netdev)
9d5c8243
AK		 3406{
3407 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3408 struct igb_ring *tx_ring;
3409
661086df 3410 int r_idx = 0;
1bfaf07b 3411 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3412 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3413
3414 /* This goes back to the question of how to logically map a tx queue
3415 * to a flow. Right now, performance is impacted slightly negatively
3416 * if using multiple tx queues. If the stack breaks away from a
3417 * single qdisc implementation, we can look at this again. */
3b29a56d 3418 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3419}
3420
3421/**
3422 * igb_tx_timeout - Respond to a Tx Hang
3423 * @netdev: network interface device structure
3424 **/
3425static void igb_tx_timeout(struct net_device *netdev)
3426{
3427 struct igb_adapter *adapter = netdev_priv(netdev);
3428 struct e1000_hw *hw = &adapter->hw;
3429
3430 /* Do the reset outside of interrupt context */
3431 adapter->tx_timeout_count++;
3432 schedule_work(&adapter->reset_task);
265de409
AD		 3433 wr32(E1000_EICS,
3434 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3435}
3436
3437static void igb_reset_task(struct work_struct *work)
3438{
3439 struct igb_adapter *adapter;
3440 adapter = container_of(work, struct igb_adapter, reset_task);
3441
3442 igb_reinit_locked(adapter);
3443}
3444
3445/**
3446 * igb_get_stats - Get System Network Statistics
3447 * @netdev: network interface device structure
3448 *
3449 * Returns the address of the device statistics structure.
3450 * The statistics are actually updated from the timer callback.
3451 **/
73cd78f1 3452static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3453{
3454 struct igb_adapter *adapter = netdev_priv(netdev);
3455
3456 /* only return the current stats */
3457 return &adapter->net_stats;
3458}
3459
3460/**
3461 * igb_change_mtu - Change the Maximum Transfer Unit
3462 * @netdev: network interface device structure
3463 * @new_mtu: new value for maximum frame size
3464 *
3465 * Returns 0 on success, negative on failure
3466 **/
3467static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3468{
3469 struct igb_adapter *adapter = netdev_priv(netdev);
3470 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3471
3472 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3473 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3474 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3475 return -EINVAL;
3476 }
3477
9d5c8243
AK		 3478 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3479 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3480 return -EINVAL;
3481 }
3482
3483 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3484 msleep(1);
73cd78f1 3485
9d5c8243
AK		 3486 /* igb_down has a dependency on max_frame_size */
3487 adapter->max_frame_size = max_frame;
3488 if (netif_running(netdev))
3489 igb_down(adapter);
3490
3491 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3492 * means we reserve 2 more, this pushes us to allocate from the next
3493 * larger slab size.
3494 * i.e. RXBUFFER_2048 --> size-4096 slab
3495 */
3496
3497 if (max_frame <= IGB_RXBUFFER_256)
3498 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3499 else if (max_frame <= IGB_RXBUFFER_512)
3500 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3501 else if (max_frame <= IGB_RXBUFFER_1024)
3502 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3503 else if (max_frame <= IGB_RXBUFFER_2048)
3504 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3505 else
bf36c1a0
AD		 3506#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3507 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3508#else
3509 adapter->rx_buffer_len = PAGE_SIZE / 2;
3510#endif
e1739522
AD		 3511
3512 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3513 if (adapter->vfs_allocated_count &&
3514 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3515 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3516
9d5c8243
AK		 3517 /* adjust allocation if LPE protects us, and we aren't using SBP */
3518 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3519 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3520 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3521
3522 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3523 netdev->mtu, new_mtu);
3524 netdev->mtu = new_mtu;
3525
3526 if (netif_running(netdev))
3527 igb_up(adapter);
3528 else
3529 igb_reset(adapter);
3530
3531 clear_bit(__IGB_RESETTING, &adapter->state);
3532
3533 return 0;
3534}
3535
3536/**
3537 * igb_update_stats - Update the board statistics counters
3538 * @adapter: board private structure
3539 **/
3540
3541void igb_update_stats(struct igb_adapter *adapter)
3542{
3543 struct e1000_hw *hw = &adapter->hw;
3544 struct pci_dev *pdev = adapter->pdev;
3545 u16 phy_tmp;
3546
3547#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3548
3549 /*
3550 * Prevent stats update while adapter is being reset, or if the pci
3551 * connection is down.
3552 */
3553 if (adapter->link_speed == 0)
3554 return;
3555 if (pci_channel_offline(pdev))
3556 return;
3557
3558 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3559 adapter->stats.gprc += rd32(E1000_GPRC);
3560 adapter->stats.gorc += rd32(E1000_GORCL);
3561 rd32(E1000_GORCH); /* clear GORCL */
3562 adapter->stats.bprc += rd32(E1000_BPRC);
3563 adapter->stats.mprc += rd32(E1000_MPRC);
3564 adapter->stats.roc += rd32(E1000_ROC);
3565
3566 adapter->stats.prc64 += rd32(E1000_PRC64);
3567 adapter->stats.prc127 += rd32(E1000_PRC127);
3568 adapter->stats.prc255 += rd32(E1000_PRC255);
3569 adapter->stats.prc511 += rd32(E1000_PRC511);
3570 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3571 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3572 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3573 adapter->stats.sec += rd32(E1000_SEC);
3574
3575 adapter->stats.mpc += rd32(E1000_MPC);
3576 adapter->stats.scc += rd32(E1000_SCC);
3577 adapter->stats.ecol += rd32(E1000_ECOL);
3578 adapter->stats.mcc += rd32(E1000_MCC);
3579 adapter->stats.latecol += rd32(E1000_LATECOL);
3580 adapter->stats.dc += rd32(E1000_DC);
3581 adapter->stats.rlec += rd32(E1000_RLEC);
3582 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3583 adapter->stats.xontxc += rd32(E1000_XONTXC);
3584 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3585 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3586 adapter->stats.fcruc += rd32(E1000_FCRUC);
3587 adapter->stats.gptc += rd32(E1000_GPTC);
3588 adapter->stats.gotc += rd32(E1000_GOTCL);
3589 rd32(E1000_GOTCH); /* clear GOTCL */
3590 adapter->stats.rnbc += rd32(E1000_RNBC);
3591 adapter->stats.ruc += rd32(E1000_RUC);
3592 adapter->stats.rfc += rd32(E1000_RFC);
3593 adapter->stats.rjc += rd32(E1000_RJC);
3594 adapter->stats.tor += rd32(E1000_TORH);
3595 adapter->stats.tot += rd32(E1000_TOTH);
3596 adapter->stats.tpr += rd32(E1000_TPR);
3597
3598 adapter->stats.ptc64 += rd32(E1000_PTC64);
3599 adapter->stats.ptc127 += rd32(E1000_PTC127);
3600 adapter->stats.ptc255 += rd32(E1000_PTC255);
3601 adapter->stats.ptc511 += rd32(E1000_PTC511);
3602 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3603 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3604
3605 adapter->stats.mptc += rd32(E1000_MPTC);
3606 adapter->stats.bptc += rd32(E1000_BPTC);
3607
3608 /* used for adaptive IFS */
3609
3610 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3611 adapter->stats.tpt += hw->mac.tx_packet_delta;
3612 hw->mac.collision_delta = rd32(E1000_COLC);
3613 adapter->stats.colc += hw->mac.collision_delta;
3614
3615 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3616 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3617 adapter->stats.tncrs += rd32(E1000_TNCRS);
3618 adapter->stats.tsctc += rd32(E1000_TSCTC);
3619 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3620
3621 adapter->stats.iac += rd32(E1000_IAC);
3622 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3623 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3624 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3625 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3626 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3627 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3628 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3629 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3630
3631 /* Fill out the OS statistics structure */
3632 adapter->net_stats.multicast = adapter->stats.mprc;
3633 adapter->net_stats.collisions = adapter->stats.colc;
3634
3635 /* Rx Errors */
3636
8c0ab70a
JDB		 3637 if (hw->mac.type != e1000_82575) {
3638 u32 rqdpc_tmp;
3ea73afa 3639 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3640 int i;
3641 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3642 * Queue Drop Packet Count) stats only gets incremented, if
3643 * the DROP_EN but it set (in the SRRCTL register for that
3644 * queue). If DROP_EN bit is NOT set, then the some what
3645 * equivalent count is stored in RNBC (not per queue basis).
3646 * Also note the drop count is due to lack of available
3647 * descriptors.
3648 */
3649 for (i = 0; i < adapter->num_rx_queues; i++) {
3650 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3651 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3652 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3653 }
3ea73afa 3654 adapter->net_stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3655 }
3656
3ea73afa
JDB		 3657 /* Note RNBC (Receive No Buffers Count) is an not an exact
3658 * drop count as the hardware FIFO might save the day. Thats
3659 * one of the reason for saving it in rx_fifo_errors, as its
3660 * potentially not a true drop.
3661 */
3662 adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3663
9d5c8243 3664 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3665 * our own version based on RUC and ROC */
9d5c8243
AK		 3666 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3667 adapter->stats.crcerrs + adapter->stats.algnerrc +
3668 adapter->stats.ruc + adapter->stats.roc +
3669 adapter->stats.cexterr;
3670 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3671 adapter->stats.roc;
3672 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3673 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3674 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3675
3676 /* Tx Errors */
3677 adapter->net_stats.tx_errors = adapter->stats.ecol +
3678 adapter->stats.latecol;
3679 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3680 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3681 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3682
3683 /* Tx Dropped needs to be maintained elsewhere */
3684
3685 /* Phy Stats */
3686 if (hw->phy.media_type == e1000_media_type_copper) {
3687 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3688 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3689 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3690 adapter->phy_stats.idle_errors += phy_tmp;
3691 }
3692 }
3693
3694 /* Management Stats */
3695 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3696 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3697 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3698}
3699
9d5c8243
AK		 3700static irqreturn_t igb_msix_other(int irq, void *data)
3701{
3702 struct net_device *netdev = data;
3703 struct igb_adapter *adapter = netdev_priv(netdev);
3704 struct e1000_hw *hw = &adapter->hw;
844290e5 3705 u32 icr = rd32(E1000_ICR);
9d5c8243 3706
844290e5 3707 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3708
3709 if(icr & E1000_ICR_DOUTSYNC) {
3710 /* HW is reporting DMA is out of sync */
3711 adapter->stats.doosync++;
3712 }
eebbbdba 3713
4ae196df
AD		 3714 /* Check for a mailbox event */
3715 if (icr & E1000_ICR_VMMB)
3716 igb_msg_task(adapter);
3717
3718 if (icr & E1000_ICR_LSC) {
3719 hw->mac.get_link_status = 1;
3720 /* guard against interrupt when we're going down */
3721 if (!test_bit(__IGB_DOWN, &adapter->state))
3722 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3723 }
3724
3725 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3726 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3727
3728 return IRQ_HANDLED;
3729}
3730
3731static irqreturn_t igb_msix_tx(int irq, void *data)
3732{
3733 struct igb_ring *tx_ring = data;
3734 struct igb_adapter *adapter = tx_ring->adapter;
3735 struct e1000_hw *hw = &adapter->hw;
3736
421e02f0 3737#ifdef CONFIG_IGB_DCA
7dfc16fa 3738 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3739 igb_update_tx_dca(tx_ring);
3740#endif
73cd78f1 3741
9d5c8243
AK		 3742 tx_ring->total_bytes = 0;
3743 tx_ring->total_packets = 0;
661086df
PWJ		 3744
3745 /* auto mask will automatically reenable the interrupt when we write
3746 * EICS */
3b644cf6 3747 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3748 /* Ring was not completely cleaned, so fire another interrupt */
3749 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3750 else
9d5c8243 3751 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3752
9d5c8243
AK		 3753 return IRQ_HANDLED;
3754}
3755
6eb5a7f1
AD		 3756static void igb_write_itr(struct igb_ring *ring)
3757{
3758 struct e1000_hw *hw = &ring->adapter->hw;
3759 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3760 switch (hw->mac.type) {
3761 case e1000_82576:
73cd78f1 3762 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3763 0x80000000);
3764 break;
3765 default:
73cd78f1 3766 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3767 (ring->itr_val << 16));
3768 break;
3769 }
3770 ring->set_itr = 0;
3771 }
3772}
3773
9d5c8243
AK		 3774static irqreturn_t igb_msix_rx(int irq, void *data)
3775{
3776 struct igb_ring *rx_ring = data;
9d5c8243 3777
844290e5
PW		 3778 /* Write the ITR value calculated at the end of the
3779 * previous interrupt.
3780 */
9d5c8243 3781
6eb5a7f1 3782 igb_write_itr(rx_ring);
9d5c8243 3783
288379f0
BH		 3784 if (napi_schedule_prep(&rx_ring->napi))
3785 __napi_schedule(&rx_ring->napi);
844290e5 3786
421e02f0 3787#ifdef CONFIG_IGB_DCA
8d253320 3788 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3789 igb_update_rx_dca(rx_ring);
3790#endif
3791 return IRQ_HANDLED;
3792}
3793
421e02f0 3794#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3795static void igb_update_rx_dca(struct igb_ring *rx_ring)
3796{
3797 u32 dca_rxctrl;
3798 struct igb_adapter *adapter = rx_ring->adapter;
3799 struct e1000_hw *hw = &adapter->hw;
3800 int cpu = get_cpu();
26bc19ec 3801 int q = rx_ring->reg_idx;
fe4506b6
JC		 3802
3803 if (rx_ring->cpu != cpu) {
3804 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3805 if (hw->mac.type == e1000_82576) {
3806 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
92be7917 3807 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3808 E1000_DCA_RXCTRL_CPUID_SHIFT;
3809 } else {
3810 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 3811 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3812 }
fe4506b6
JC		 3813 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3814 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3815 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3816 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3817 rx_ring->cpu = cpu;
3818 }
3819 put_cpu();
3820}
3821
3822static void igb_update_tx_dca(struct igb_ring *tx_ring)
3823{
3824 u32 dca_txctrl;
3825 struct igb_adapter *adapter = tx_ring->adapter;
3826 struct e1000_hw *hw = &adapter->hw;
3827 int cpu = get_cpu();
26bc19ec 3828 int q = tx_ring->reg_idx;
fe4506b6
JC		 3829
3830 if (tx_ring->cpu != cpu) {
3831 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3832 if (hw->mac.type == e1000_82576) {
3833 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
92be7917 3834 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3835 E1000_DCA_TXCTRL_CPUID_SHIFT;
3836 } else {
3837 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
92be7917 3838 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3839 }
fe4506b6
JC		 3840 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3841 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3842 tx_ring->cpu = cpu;
3843 }
3844 put_cpu();
3845}
3846
3847static void igb_setup_dca(struct igb_adapter *adapter)
3848{
7e0e99ef 3849 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 3850 int i;
3851
7dfc16fa 3852 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3853 return;
3854
7e0e99ef
AD		 3855 /* Always use CB2 mode, difference is masked in the CB driver. */
3856 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3857
fe4506b6
JC		 3858 for (i = 0; i < adapter->num_tx_queues; i++) {
3859 adapter->tx_ring[i].cpu = -1;
3860 igb_update_tx_dca(&adapter->tx_ring[i]);
3861 }
3862 for (i = 0; i < adapter->num_rx_queues; i++) {
3863 adapter->rx_ring[i].cpu = -1;
3864 igb_update_rx_dca(&adapter->rx_ring[i]);
3865 }
3866}
3867
3868static int __igb_notify_dca(struct device *dev, void *data)
3869{
3870 struct net_device *netdev = dev_get_drvdata(dev);
3871 struct igb_adapter *adapter = netdev_priv(netdev);
3872 struct e1000_hw *hw = &adapter->hw;
3873 unsigned long event = *(unsigned long *)data;
3874
3875 switch (event) {
3876 case DCA_PROVIDER_ADD:
3877 /* if already enabled, don't do it again */
7dfc16fa 3878 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3879 break;
fe4506b6
JC		 3880 /* Always use CB2 mode, difference is masked
3881 * in the CB driver. */
cbd347ad 3882 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3883 if (dca_add_requester(dev) == 0) {
bbd98fe4 3884 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3885 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3886 igb_setup_dca(adapter);
3887 break;
3888 }
3889 /* Fall Through since DCA is disabled. */
3890 case DCA_PROVIDER_REMOVE:
7dfc16fa 3891 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3892 /* without this a class_device is left
3893 * hanging around in the sysfs model */
3894 dca_remove_requester(dev);
3895 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3896 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3897 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3898 }
3899 break;
3900 }
bbd98fe4 3901
fe4506b6 3902 return 0;
9d5c8243
AK		 3903}
3904
fe4506b6
JC		 3905static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3906 void *p)
3907{
3908 int ret_val;
3909
3910 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3911 __igb_notify_dca);
3912
3913 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3914}
421e02f0 3915#endif /* CONFIG_IGB_DCA */
9d5c8243 3916
4ae196df
AD		 3917static void igb_ping_all_vfs(struct igb_adapter *adapter)
3918{
3919 struct e1000_hw *hw = &adapter->hw;
3920 u32 ping;
3921 int i;
3922
3923 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3924 ping = E1000_PF_CONTROL_MSG;
3925 if (adapter->vf_data[i].clear_to_send)
3926 ping |= E1000_VT_MSGTYPE_CTS;
3927 igb_write_mbx(hw, &ping, 1, i);
3928 }
3929}
3930
3931static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3932 u32 *msgbuf, u32 vf)
3933{
3934 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3935 u16 *hash_list = (u16 *)&msgbuf[1];
3936 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3937 int i;
3938
3939 /* only up to 30 hash values supported */
3940 if (n > 30)
3941 n = 30;
3942
3943 /* salt away the number of multi cast addresses assigned
3944 * to this VF for later use to restore when the PF multi cast
3945 * list changes
3946 */
3947 vf_data->num_vf_mc_hashes = n;
3948
3949 /* VFs are limited to using the MTA hash table for their multicast
3950 * addresses */
3951 for (i = 0; i < n; i++)
a419aef8 3952 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 3953
3954 /* Flush and reset the mta with the new values */
ff41f8dc 3955 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 3956
3957 return 0;
3958}
3959
3960static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3961{
3962 struct e1000_hw *hw = &adapter->hw;
3963 struct vf_data_storage *vf_data;
3964 int i, j;
3965
3966 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3967 vf_data = &adapter->vf_data[i];
75f4f382 3968 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 3969 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3970 }
3971}
3972
3973static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3974{
3975 struct e1000_hw *hw = &adapter->hw;
3976 u32 pool_mask, reg, vid;
3977 int i;
3978
3979 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3980
3981 /* Find the vlan filter for this id */
3982 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3983 reg = rd32(E1000_VLVF(i));
3984
3985 /* remove the vf from the pool */
3986 reg &= ~pool_mask;
3987
3988 /* if pool is empty then remove entry from vfta */
3989 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3990 (reg & E1000_VLVF_VLANID_ENABLE)) {
3991 reg = 0;
3992 vid = reg & E1000_VLVF_VLANID_MASK;
3993 igb_vfta_set(hw, vid, false);
3994 }
3995
3996 wr32(E1000_VLVF(i), reg);
3997 }
ae641bdc
AD		 3998
3999 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4000}
4001
4002static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4003{
4004 struct e1000_hw *hw = &adapter->hw;
4005 u32 reg, i;
4006
4007 /* It is an error to call this function when VFs are not enabled */
4008 if (!adapter->vfs_allocated_count)
4009 return -1;
4010
4011 /* Find the vlan filter for this id */
4012 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4013 reg = rd32(E1000_VLVF(i));
4014 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4015 vid == (reg & E1000_VLVF_VLANID_MASK))
4016 break;
4017 }
4018
4019 if (add) {
4020 if (i == E1000_VLVF_ARRAY_SIZE) {
4021 /* Did not find a matching VLAN ID entry that was
4022 * enabled. Search for a free filter entry, i.e.
4023 * one without the enable bit set
4024 */
4025 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4026 reg = rd32(E1000_VLVF(i));
4027 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4028 break;
4029 }
4030 }
4031 if (i < E1000_VLVF_ARRAY_SIZE) {
4032 /* Found an enabled/available entry */
4033 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4034
4035 /* if !enabled we need to set this up in vfta */
4036 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4037 /* add VID to filter table, if bit already set
4038 * PF must have added it outside of table */
4039 if (igb_vfta_set(hw, vid, true))
4040 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4041 adapter->vfs_allocated_count);
4ae196df
AD		 4042 reg |= E1000_VLVF_VLANID_ENABLE;
4043 }
cad6d05f
AD		 4044 reg &= ~E1000_VLVF_VLANID_MASK;
4045 reg |= vid;
4ae196df
AD		 4046
4047 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4048
4049 /* do not modify RLPML for PF devices */
4050 if (vf >= adapter->vfs_allocated_count)
4051 return 0;
4052
4053 if (!adapter->vf_data[vf].vlans_enabled) {
4054 u32 size;
4055 reg = rd32(E1000_VMOLR(vf));
4056 size = reg & E1000_VMOLR_RLPML_MASK;
4057 size += 4;
4058 reg &= ~E1000_VMOLR_RLPML_MASK;
4059 reg |= size;
4060 wr32(E1000_VMOLR(vf), reg);
4061 }
4062 adapter->vf_data[vf].vlans_enabled++;
4063
4ae196df
AD		 4064 return 0;
4065 }
4066 } else {
4067 if (i < E1000_VLVF_ARRAY_SIZE) {
4068 /* remove vf from the pool */
4069 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4070 /* if pool is empty then remove entry from vfta */
4071 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4072 reg = 0;
4073 igb_vfta_set(hw, vid, false);
4074 }
4075 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4076
4077 /* do not modify RLPML for PF devices */
4078 if (vf >= adapter->vfs_allocated_count)
4079 return 0;
4080
4081 adapter->vf_data[vf].vlans_enabled--;
4082 if (!adapter->vf_data[vf].vlans_enabled) {
4083 u32 size;
4084 reg = rd32(E1000_VMOLR(vf));
4085 size = reg & E1000_VMOLR_RLPML_MASK;
4086 size -= 4;
4087 reg &= ~E1000_VMOLR_RLPML_MASK;
4088 reg |= size;
4089 wr32(E1000_VMOLR(vf), reg);
4090 }
4ae196df
AD		 4091 return 0;
4092 }
4093 }
4094 return -1;
4095}
4096
4097static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4098{
4099 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4100 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4101
4102 return igb_vlvf_set(adapter, vid, add, vf);
4103}
4104
4105static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4106{
4107 struct e1000_hw *hw = &adapter->hw;
4108
4109 /* disable mailbox functionality for vf */
4110 adapter->vf_data[vf].clear_to_send = false;
4111
4112 /* reset offloads to defaults */
4113 igb_set_vmolr(hw, vf);
4114
4115 /* reset vlans for device */
4116 igb_clear_vf_vfta(adapter, vf);
4117
4118 /* reset multicast table array for vf */
4119 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4120
4121 /* Flush and reset the mta with the new values */
ff41f8dc 4122 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4123}
4124
4125static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4126{
4127 struct e1000_hw *hw = &adapter->hw;
4128 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4129 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4130 u32 reg, msgbuf[3];
4131 u8 *addr = (u8 *)(&msgbuf[1]);
4132
4133 /* process all the same items cleared in a function level reset */
4134 igb_vf_reset_event(adapter, vf);
4135
4136 /* set vf mac address */
26ad9178 4137 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4138
4139 /* enable transmit and receive for vf */
4140 reg = rd32(E1000_VFTE);
4141 wr32(E1000_VFTE, reg | (1 << vf));
4142 reg = rd32(E1000_VFRE);
4143 wr32(E1000_VFRE, reg | (1 << vf));
4144
4145 /* enable mailbox functionality for vf */
4146 adapter->vf_data[vf].clear_to_send = true;
4147
4148 /* reply to reset with ack and vf mac address */
4149 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4150 memcpy(addr, vf_mac, 6);
4151 igb_write_mbx(hw, msgbuf, 3, vf);
4152}
4153
4154static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4155{
4156 unsigned char *addr = (char *)&msg[1];
4157 int err = -1;
4158
4159 if (is_valid_ether_addr(addr))
4160 err = igb_set_vf_mac(adapter, vf, addr);
4161
4162 return err;
4163
4164}
4165
4166static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4167{
4168 struct e1000_hw *hw = &adapter->hw;
4169 u32 msg = E1000_VT_MSGTYPE_NACK;
4170
4171 /* if device isn't clear to send it shouldn't be reading either */
4172 if (!adapter->vf_data[vf].clear_to_send)
4173 igb_write_mbx(hw, &msg, 1, vf);
4174}
4175
4176
4177static void igb_msg_task(struct igb_adapter *adapter)
4178{
4179 struct e1000_hw *hw = &adapter->hw;
4180 u32 vf;
4181
4182 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4183 /* process any reset requests */
4184 if (!igb_check_for_rst(hw, vf)) {
4185 adapter->vf_data[vf].clear_to_send = false;
4186 igb_vf_reset_event(adapter, vf);
4187 }
4188
4189 /* process any messages pending */
4190 if (!igb_check_for_msg(hw, vf))
4191 igb_rcv_msg_from_vf(adapter, vf);
4192
4193 /* process any acks */
4194 if (!igb_check_for_ack(hw, vf))
4195 igb_rcv_ack_from_vf(adapter, vf);
4196
4197 }
4198}
4199
4200static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4201{
4202 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4203 u32 msgbuf[mbx_size];
4204 struct e1000_hw *hw = &adapter->hw;
4205 s32 retval;
4206
4207 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4208
4209 if (retval)
4210 dev_err(&adapter->pdev->dev,
4211 "Error receiving message from VF\n");
4212
4213 /* this is a message we already processed, do nothing */
4214 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4215 return retval;
4216
4217 /*
4218 * until the vf completes a reset it should not be
4219 * allowed to start any configuration.
4220 */
4221
4222 if (msgbuf[0] == E1000_VF_RESET) {
4223 igb_vf_reset_msg(adapter, vf);
4224
4225 return retval;
4226 }
4227
4228 if (!adapter->vf_data[vf].clear_to_send) {
4229 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4230 igb_write_mbx(hw, msgbuf, 1, vf);
4231 return retval;
4232 }
4233
4234 switch ((msgbuf[0] & 0xFFFF)) {
4235 case E1000_VF_SET_MAC_ADDR:
4236 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4237 break;
4238 case E1000_VF_SET_MULTICAST:
4239 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4240 break;
4241 case E1000_VF_SET_LPE:
4242 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4243 break;
4244 case E1000_VF_SET_VLAN:
4245 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4246 break;
4247 default:
4248 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4249 retval = -1;
4250 break;
4251 }
4252
4253 /* notify the VF of the results of what it sent us */
4254 if (retval)
4255 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4256 else
4257 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4258
4259 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4260
4261 igb_write_mbx(hw, msgbuf, 1, vf);
4262
4263 return retval;
4264}
4265
9d5c8243
AK		 4266/**
4267 * igb_intr_msi - Interrupt Handler
4268 * @irq: interrupt number
4269 * @data: pointer to a network interface device structure
4270 **/
4271static irqreturn_t igb_intr_msi(int irq, void *data)
4272{
4273 struct net_device *netdev = data;
4274 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4275 struct e1000_hw *hw = &adapter->hw;
4276 /* read ICR disables interrupts using IAM */
4277 u32 icr = rd32(E1000_ICR);
4278
6eb5a7f1 4279 igb_write_itr(adapter->rx_ring);
9d5c8243 4280
dda0e083
AD		 4281 if(icr & E1000_ICR_DOUTSYNC) {
4282 /* HW is reporting DMA is out of sync */
4283 adapter->stats.doosync++;
4284 }
4285
9d5c8243
AK		 4286 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4287 hw->mac.get_link_status = 1;
4288 if (!test_bit(__IGB_DOWN, &adapter->state))
4289 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4290 }
4291
288379f0 4292 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4293
4294 return IRQ_HANDLED;
4295}
4296
4297/**
4a3c6433 4298 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4299 * @irq: interrupt number
4300 * @data: pointer to a network interface device structure
4301 **/
4302static irqreturn_t igb_intr(int irq, void *data)
4303{
4304 struct net_device *netdev = data;
4305 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4306 struct e1000_hw *hw = &adapter->hw;
4307 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4308 * need for the IMC write */
4309 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4310 if (!icr)
4311 return IRQ_NONE; /* Not our interrupt */
4312
6eb5a7f1 4313 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 4314
4315 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4316 * not set, then the adapter didn't send an interrupt */
4317 if (!(icr & E1000_ICR_INT_ASSERTED))
4318 return IRQ_NONE;
4319
dda0e083
AD		 4320 if(icr & E1000_ICR_DOUTSYNC) {
4321 /* HW is reporting DMA is out of sync */
4322 adapter->stats.doosync++;
4323 }
4324
9d5c8243
AK		 4325 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4326 hw->mac.get_link_status = 1;
4327 /* guard against interrupt when we're going down */
4328 if (!test_bit(__IGB_DOWN, &adapter->state))
4329 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4330 }
4331
288379f0 4332 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4333
4334 return IRQ_HANDLED;
4335}
4336
46544258 4337static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 4338{
661086df 4339 struct igb_adapter *adapter = rx_ring->adapter;
46544258 4340 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4341
46544258
AD		 4342 if (adapter->itr_setting & 3) {
4343 if (adapter->num_rx_queues == 1)
6eb5a7f1 4344 igb_set_itr(adapter);
46544258
AD		 4345 else
4346 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 4347 }
4348
46544258
AD		 4349 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4350 if (adapter->msix_entries)
4351 wr32(E1000_EIMS, rx_ring->eims_value);
4352 else
4353 igb_irq_enable(adapter);
4354 }
9d5c8243
AK		 4355}
4356
46544258
AD		 4357/**
4358 * igb_poll - NAPI Rx polling callback
4359 * @napi: napi polling structure
4360 * @budget: count of how many packets we should handle
4361 **/
4362static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 4363{
4364 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
9d5c8243
AK		 4365 int work_done = 0;
4366
421e02f0 4367#ifdef CONFIG_IGB_DCA
bd38e5d1 4368 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 4369 igb_update_rx_dca(rx_ring);
4370#endif
3b644cf6 4371 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 4372
46544258
AD		 4373 if (rx_ring->buddy) {
4374#ifdef CONFIG_IGB_DCA
bd38e5d1 4375 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
46544258
AD		 4376 igb_update_tx_dca(rx_ring->buddy);
4377#endif
4378 if (!igb_clean_tx_irq(rx_ring->buddy))
4379 work_done = budget;
4380 }
4381
9d5c8243 4382 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4383 if (work_done < budget) {
288379f0 4384 napi_complete(napi);
46544258 4385 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 4386 }
4387
46544258 4388 return work_done;
9d5c8243 4389}
6d8126f9 4390
33af6bcc
PO		 4391/**
4392 * igb_hwtstamp - utility function which checks for TX time stamp
4393 * @adapter: board private structure
4394 * @skb: packet that was just sent
4395 *
4396 * If we were asked to do hardware stamping and such a time stamp is
4397 * available, then it must have been for this skb here because we only
4398 * allow only one such packet into the queue.
4399 */
4400static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4401{
4402 union skb_shared_tx *shtx = skb_tx(skb);
4403 struct e1000_hw *hw = &adapter->hw;
4404
4405 if (unlikely(shtx->hardware)) {
4406 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4407 if (valid) {
4408 u64 regval = rd32(E1000_TXSTMPL);
4409 u64 ns;
4410 struct skb_shared_hwtstamps shhwtstamps;
4411
4412 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4413 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4414 ns = timecounter_cyc2time(&adapter->clock,
4415 regval);
4416 timecompare_update(&adapter->compare, ns);
4417 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4418 shhwtstamps.syststamp =
4419 timecompare_transform(&adapter->compare, ns);
4420 skb_tstamp_tx(skb, &shhwtstamps);
4421 }
33af6bcc
PO		 4422 }
4423}
4424
9d5c8243
AK		 4425/**
4426 * igb_clean_tx_irq - Reclaim resources after transmit completes
4427 * @adapter: board private structure
4428 * returns true if ring is completely cleaned
4429 **/
3b644cf6 4430static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 4431{
3b644cf6 4432 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 4433 struct net_device *netdev = adapter->netdev;
0e014cb1 4434 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4435 struct igb_buffer *buffer_info;
4436 struct sk_buff *skb;
0e014cb1 4437 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4438 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4439 unsigned int i, eop, count = 0;
4440 bool cleaned = false;
9d5c8243 4441
9d5c8243 4442 i = tx_ring->next_to_clean;
0e014cb1
AD		 4443 eop = tx_ring->buffer_info[i].next_to_watch;
4444 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4445
4446 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4447 (count < tx_ring->count)) {
4448 for (cleaned = false; !cleaned; count++) {
4449 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4450 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4451 cleaned = (i == eop);
9d5c8243
AK		 4452 skb = buffer_info->skb;
4453
4454 if (skb) {
4455 unsigned int segs, bytecount;
4456 /* gso_segs is currently only valid for tcp */
4457 segs = skb_shinfo(skb)->gso_segs ?: 1;
4458 /* multiply data chunks by size of headers */
4459 bytecount = ((segs - 1) * skb_headlen(skb)) +
4460 skb->len;
4461 total_packets += segs;
4462 total_bytes += bytecount;
33af6bcc
PO		 4463
4464 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4465 }
4466
4467 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4468 tx_desc->wb.status = 0;
9d5c8243
AK		 4469
4470 i++;
4471 if (i == tx_ring->count)
4472 i = 0;
9d5c8243 4473 }
0e014cb1
AD		 4474 eop = tx_ring->buffer_info[i].next_to_watch;
4475 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4476 }
4477
9d5c8243
AK		 4478 tx_ring->next_to_clean = i;
4479
fc7d345d 4480 if (unlikely(count &&
9d5c8243 4481 netif_carrier_ok(netdev) &&
c493ea45 4482 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4483 /* Make sure that anybody stopping the queue after this
4484 * sees the new next_to_clean.
4485 */
4486 smp_mb();
661086df
PWJ		 4487 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4488 !(test_bit(__IGB_DOWN, &adapter->state))) {
4489 netif_wake_subqueue(netdev, tx_ring->queue_index);
4490 ++adapter->restart_queue;
4491 }
9d5c8243
AK		 4492 }
4493
4494 if (tx_ring->detect_tx_hung) {
4495 /* Detect a transmit hang in hardware, this serializes the
4496 * check with the clearing of time_stamp and movement of i */
4497 tx_ring->detect_tx_hung = false;
4498 if (tx_ring->buffer_info[i].time_stamp &&
4499 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4500 (adapter->tx_timeout_factor * HZ))
4501 && !(rd32(E1000_STATUS) &
4502 E1000_STATUS_TXOFF)) {
4503
9d5c8243
AK		 4504 /* detected Tx unit hang */
4505 dev_err(&adapter->pdev->dev,
4506 "Detected Tx Unit Hang\n"
2d064c06 4507 " Tx Queue <%d>\n"
9d5c8243
AK		 4508 " TDH <%x>\n"
4509 " TDT <%x>\n"
4510 " next_to_use <%x>\n"
4511 " next_to_clean <%x>\n"
9d5c8243
AK		 4512 "buffer_info[next_to_clean]\n"
4513 " time_stamp <%lx>\n"
0e014cb1 4514 " next_to_watch <%x>\n"
9d5c8243
AK		 4515 " jiffies <%lx>\n"
4516 " desc.status <%x>\n",
2d064c06 4517 tx_ring->queue_index,
9d5c8243
AK		 4518 readl(adapter->hw.hw_addr + tx_ring->head),
4519 readl(adapter->hw.hw_addr + tx_ring->tail),
4520 tx_ring->next_to_use,
4521 tx_ring->next_to_clean,
9d5c8243 4522 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4523 eop,
9d5c8243 4524 jiffies,
0e014cb1 4525 eop_desc->wb.status);
661086df 4526 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4527 }
4528 }
4529 tx_ring->total_bytes += total_bytes;
4530 tx_ring->total_packets += total_packets;
e21ed353
AD		 4531 tx_ring->tx_stats.bytes += total_bytes;
4532 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 4533 adapter->net_stats.tx_bytes += total_bytes;
4534 adapter->net_stats.tx_packets += total_packets;
0e014cb1 4535 return (count < tx_ring->count);
9d5c8243
AK		 4536}
4537
9d5c8243
AK		 4538/**
4539 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4540 * @ring: pointer to receive ring receving this packet
9d5c8243 4541 * @status: descriptor status field as written by hardware
73cd78f1 4542 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4543 * @skb: pointer to sk_buff to be indicated to stack
4544 **/
d3352520
AD		 4545static void igb_receive_skb(struct igb_ring *ring, u8 status,
4546 union e1000_adv_rx_desc * rx_desc,
4547 struct sk_buff *skb)
4548{
4549 struct igb_adapter * adapter = ring->adapter;
4550 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4551
0c8dfc83 4552 skb_record_rx_queue(skb, ring->queue_index);
182ff8df
AD		 4553 if (vlan_extracted)
4554 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4555 le16_to_cpu(rx_desc->wb.upper.vlan),
4556 skb);
4557 else
4558 napi_gro_receive(&ring->napi, skb);
9d5c8243
AK		 4559}
4560
9d5c8243
AK		 4561static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4562 u32 status_err, struct sk_buff *skb)
4563{
4564 skb->ip_summed = CHECKSUM_NONE;
4565
4566 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4567 if ((status_err & E1000_RXD_STAT_IXSM) ||
4568 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4569 return;
4570 /* TCP/UDP checksum error bit is set */
4571 if (status_err &
4572 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4573 /*
4574 * work around errata with sctp packets where the TCPE aka
4575 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4576 * packets, (aka let the stack check the crc32c)
4577 */
4578 if (!((adapter->hw.mac.type == e1000_82576) &&
4579 (skb->len == 60)))
4580 adapter->hw_csum_err++;
9d5c8243 4581 /* let the stack verify checksum errors */
9d5c8243
AK		 4582 return;
4583 }
4584 /* It must be a TCP or UDP packet with a valid checksum */
4585 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4586 skb->ip_summed = CHECKSUM_UNNECESSARY;
4587
b9473560 4588 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4589 adapter->hw_csum_good++;
4590}
4591
2d94d8ab
AD		 4592static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4593 union e1000_adv_rx_desc *rx_desc)
4594{
4595 /* HW will not DMA in data larger than the given buffer, even if it
4596 * parses the (NFS, of course) header to be larger. In that case, it
4597 * fills the header buffer and spills the rest into the page.
4598 */
4599 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4600 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4601 if (hlen > adapter->rx_ps_hdr_size)
4602 hlen = adapter->rx_ps_hdr_size;
4603 return hlen;
4604}
4605
3b644cf6
MW		 4606static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4607 int *work_done, int budget)
9d5c8243 4608{
3b644cf6 4609 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4610 struct net_device *netdev = adapter->netdev;
33af6bcc 4611 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4612 struct pci_dev *pdev = adapter->pdev;
4613 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4614 struct igb_buffer *buffer_info , *next_buffer;
4615 struct sk_buff *skb;
9d5c8243
AK		 4616 bool cleaned = false;
4617 int cleaned_count = 0;
4618 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4619 unsigned int i;
2d94d8ab
AD		 4620 u32 staterr;
4621 u16 length;
9d5c8243
AK		 4622
4623 i = rx_ring->next_to_clean;
69d3ca53 4624 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4625 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4626 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4627
4628 while (staterr & E1000_RXD_STAT_DD) {
4629 if (*work_done >= budget)
4630 break;
4631 (*work_done)++;
9d5c8243 4632
69d3ca53
AD		 4633 skb = buffer_info->skb;
4634 prefetch(skb->data - NET_IP_ALIGN);
4635 buffer_info->skb = NULL;
4636
4637 i++;
4638 if (i == rx_ring->count)
4639 i = 0;
4640 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4641 prefetch(next_rxd);
4642 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4643
4644 length = le16_to_cpu(rx_desc->wb.upper.length);
4645 cleaned = true;
4646 cleaned_count++;
4647
91615f76 4648 /* this is the fast path for the non-packet split case */
bf36c1a0
AD		 4649 if (!adapter->rx_ps_hdr_size) {
4650 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4651 adapter->rx_buffer_len,
bf36c1a0 4652 PCI_DMA_FROMDEVICE);
91615f76 4653 buffer_info->dma = 0;
bf36c1a0
AD		 4654 skb_put(skb, length);
4655 goto send_up;
9d5c8243
AK		 4656 }
4657
2d94d8ab
AD		 4658 if (buffer_info->dma) {
4659 u16 hlen = igb_get_hlen(adapter, rx_desc);
bf36c1a0 4660 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4661 adapter->rx_ps_hdr_size,
bf36c1a0 4662 PCI_DMA_FROMDEVICE);
91615f76 4663 buffer_info->dma = 0;
bf36c1a0
AD		 4664 skb_put(skb, hlen);
4665 }
4666
4667 if (length) {
9d5c8243 4668 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4669 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4670 buffer_info->page_dma = 0;
bf36c1a0
AD		 4671
4672 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4673 buffer_info->page,
4674 buffer_info->page_offset,
4675 length);
4676
4677 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4678 (page_count(buffer_info->page) != 1))
4679 buffer_info->page = NULL;
4680 else
4681 get_page(buffer_info->page);
9d5c8243
AK		 4682
4683 skb->len += length;
4684 skb->data_len += length;
9d5c8243 4685
bf36c1a0 4686 skb->truesize += length;
9d5c8243 4687 }
9d5c8243 4688
bf36c1a0 4689 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4690 buffer_info->skb = next_buffer->skb;
4691 buffer_info->dma = next_buffer->dma;
4692 next_buffer->skb = skb;
4693 next_buffer->dma = 0;
bf36c1a0
AD		 4694 goto next_desc;
4695 }
69d3ca53 4696send_up:
33af6bcc
PO		 4697 /*
4698 * If this bit is set, then the RX registers contain
4699 * the time stamp. No other packet will be time
4700 * stamped until we read these registers, so read the
4701 * registers to make them available again. Because
4702 * only one packet can be time stamped at a time, we
4703 * know that the register values must belong to this
4704 * one here and therefore we don't need to compare
4705 * any of the additional attributes stored for it.
4706 *
4707 * If nothing went wrong, then it should have a
4708 * skb_shared_tx that we can turn into a
4709 * skb_shared_hwtstamps.
4710 *
4711 * TODO: can time stamping be triggered (thus locking
4712 * the registers) without the packet reaching this point
4713 * here? In that case RX time stamping would get stuck.
4714 *
4715 * TODO: in "time stamp all packets" mode this bit is
4716 * not set. Need a global flag for this mode and then
4717 * always read the registers. Cannot be done without
4718 * a race condition.
4719 */
4720 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4721 u64 regval;
4722 u64 ns;
4723 struct skb_shared_hwtstamps *shhwtstamps =
4724 skb_hwtstamps(skb);
4725
4726 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4727 "igb: no RX time stamp available for time stamped packet");
4728 regval = rd32(E1000_RXSTMPL);
4729 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4730 ns = timecounter_cyc2time(&adapter->clock, regval);
4731 timecompare_update(&adapter->compare, ns);
4732 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4733 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4734 shhwtstamps->syststamp =
4735 timecompare_transform(&adapter->compare, ns);
4736 }
4737
9d5c8243
AK		 4738 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4739 dev_kfree_skb_irq(skb);
4740 goto next_desc;
4741 }
9d5c8243
AK		 4742
4743 total_bytes += skb->len;
4744 total_packets++;
4745
4746 igb_rx_checksum_adv(adapter, staterr, skb);
4747
4748 skb->protocol = eth_type_trans(skb, netdev);
4749
d3352520 4750 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4751
9d5c8243
AK		 4752next_desc:
4753 rx_desc->wb.upper.status_error = 0;
4754
4755 /* return some buffers to hardware, one at a time is too slow */
4756 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4757 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4758 cleaned_count = 0;
4759 }
4760
4761 /* use prefetched values */
4762 rx_desc = next_rxd;
4763 buffer_info = next_buffer;
9d5c8243
AK		 4764 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4765 }
bf36c1a0 4766
9d5c8243 4767 rx_ring->next_to_clean = i;
c493ea45 4768 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 4769
4770 if (cleaned_count)
3b644cf6 4771 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4772
4773 rx_ring->total_packets += total_packets;
4774 rx_ring->total_bytes += total_bytes;
4775 rx_ring->rx_stats.packets += total_packets;
4776 rx_ring->rx_stats.bytes += total_bytes;
4777 adapter->net_stats.rx_bytes += total_bytes;
4778 adapter->net_stats.rx_packets += total_packets;
4779 return cleaned;
4780}
4781
9d5c8243
AK		 4782/**
4783 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4784 * @adapter: address of board private structure
4785 **/
3b644cf6 4786static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4787 int cleaned_count)
4788{
3b644cf6 4789 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4790 struct net_device *netdev = adapter->netdev;
4791 struct pci_dev *pdev = adapter->pdev;
4792 union e1000_adv_rx_desc *rx_desc;
4793 struct igb_buffer *buffer_info;
4794 struct sk_buff *skb;
4795 unsigned int i;
db761762 4796 int bufsz;
9d5c8243
AK		 4797
4798 i = rx_ring->next_to_use;
4799 buffer_info = &rx_ring->buffer_info[i];
4800
db761762
AD		 4801 if (adapter->rx_ps_hdr_size)
4802 bufsz = adapter->rx_ps_hdr_size;
4803 else
4804 bufsz = adapter->rx_buffer_len;
db761762 4805
9d5c8243
AK		 4806 while (cleaned_count--) {
4807 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4808
bf36c1a0 4809 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4810 if (!buffer_info->page) {
bf36c1a0
AD		 4811 buffer_info->page = alloc_page(GFP_ATOMIC);
4812 if (!buffer_info->page) {
4813 adapter->alloc_rx_buff_failed++;
4814 goto no_buffers;
4815 }
4816 buffer_info->page_offset = 0;
4817 } else {
4818 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4819 }
4820 buffer_info->page_dma =
db761762 4821 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4822 buffer_info->page_offset,
4823 PAGE_SIZE / 2,
9d5c8243
AK		 4824 PCI_DMA_FROMDEVICE);
4825 }
4826
4827 if (!buffer_info->skb) {
91615f76 4828 skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
9d5c8243
AK		 4829 if (!skb) {
4830 adapter->alloc_rx_buff_failed++;
4831 goto no_buffers;
4832 }
4833
4834 /* Make buffer alignment 2 beyond a 16 byte boundary
4835 * this will result in a 16 byte aligned IP header after
4836 * the 14 byte MAC header is removed
4837 */
4838 skb_reserve(skb, NET_IP_ALIGN);
4839
4840 buffer_info->skb = skb;
4841 buffer_info->dma = pci_map_single(pdev, skb->data,
4842 bufsz,
4843 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4844 }
4845 /* Refresh the desc even if buffer_addrs didn't change because
4846 * each write-back erases this info. */
4847 if (adapter->rx_ps_hdr_size) {
4848 rx_desc->read.pkt_addr =
4849 cpu_to_le64(buffer_info->page_dma);
4850 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4851 } else {
4852 rx_desc->read.pkt_addr =
4853 cpu_to_le64(buffer_info->dma);
4854 rx_desc->read.hdr_addr = 0;
4855 }
4856
4857 i++;
4858 if (i == rx_ring->count)
4859 i = 0;
4860 buffer_info = &rx_ring->buffer_info[i];
4861 }
4862
4863no_buffers:
4864 if (rx_ring->next_to_use != i) {
4865 rx_ring->next_to_use = i;
4866 if (i == 0)
4867 i = (rx_ring->count - 1);
4868 else
4869 i--;
4870
4871 /* Force memory writes to complete before letting h/w
4872 * know there are new descriptors to fetch. (Only
4873 * applicable for weak-ordered memory model archs,
4874 * such as IA-64). */
4875 wmb();
4876 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4877 }
4878}
4879
4880/**
4881 * igb_mii_ioctl -
4882 * @netdev:
4883 * @ifreq:
4884 * @cmd:
4885 **/
4886static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4887{
4888 struct igb_adapter *adapter = netdev_priv(netdev);
4889 struct mii_ioctl_data *data = if_mii(ifr);
4890
4891 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4892 return -EOPNOTSUPP;
4893
4894 switch (cmd) {
4895 case SIOCGMIIPHY:
4896 data->phy_id = adapter->hw.phy.addr;
4897 break;
4898 case SIOCGMIIREG:
f5f4cf08
AD		 4899 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4900 &data->val_out))
9d5c8243
AK		 4901 return -EIO;
4902 break;
4903 case SIOCSMIIREG:
4904 default:
4905 return -EOPNOTSUPP;
4906 }
4907 return 0;
4908}
4909
c6cb090b
PO		 4910/**
4911 * igb_hwtstamp_ioctl - control hardware time stamping
4912 * @netdev:
4913 * @ifreq:
4914 * @cmd:
4915 *
33af6bcc
PO		 4916 * Outgoing time stamping can be enabled and disabled. Play nice and
4917 * disable it when requested, although it shouldn't case any overhead
4918 * when no packet needs it. At most one packet in the queue may be
4919 * marked for time stamping, otherwise it would be impossible to tell
4920 * for sure to which packet the hardware time stamp belongs.
4921 *
4922 * Incoming time stamping has to be configured via the hardware
4923 * filters. Not all combinations are supported, in particular event
4924 * type has to be specified. Matching the kind of event packet is
4925 * not supported, with the exception of "all V2 events regardless of
4926 * level 2 or 4".
4927 *
c6cb090b
PO		 4928 **/
4929static int igb_hwtstamp_ioctl(struct net_device *netdev,
4930 struct ifreq *ifr, int cmd)
4931{
33af6bcc
PO		 4932 struct igb_adapter *adapter = netdev_priv(netdev);
4933 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4934 struct hwtstamp_config config;
33af6bcc
PO		 4935 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4936 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4937 u32 tsync_rx_ctl_type = 0;
4938 u32 tsync_rx_cfg = 0;
4939 int is_l4 = 0;
4940 int is_l2 = 0;
4941 short port = 319; /* PTP */
4942 u32 regval;
c6cb090b
PO		 4943
4944 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4945 return -EFAULT;
4946
4947 /* reserved for future extensions */
4948 if (config.flags)
4949 return -EINVAL;
4950
33af6bcc
PO		 4951 switch (config.tx_type) {
4952 case HWTSTAMP_TX_OFF:
4953 tsync_tx_ctl_bit = 0;
4954 break;
4955 case HWTSTAMP_TX_ON:
4956 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4957 break;
4958 default:
4959 return -ERANGE;
4960 }
4961
4962 switch (config.rx_filter) {
4963 case HWTSTAMP_FILTER_NONE:
4964 tsync_rx_ctl_bit = 0;
4965 break;
4966 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4967 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4968 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4969 case HWTSTAMP_FILTER_ALL:
4970 /*
4971 * register TSYNCRXCFG must be set, therefore it is not
4972 * possible to time stamp both Sync and Delay_Req messages
4973 * => fall back to time stamping all packets
4974 */
4975 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4976 config.rx_filter = HWTSTAMP_FILTER_ALL;
4977 break;
4978 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4979 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4980 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4981 is_l4 = 1;
4982 break;
4983 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4984 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4985 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4986 is_l4 = 1;
4987 break;
4988 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4989 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4990 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4991 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4992 is_l2 = 1;
4993 is_l4 = 1;
4994 config.rx_filter = HWTSTAMP_FILTER_SOME;
4995 break;
4996 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4997 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4998 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4999 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5000 is_l2 = 1;
5001 is_l4 = 1;
5002 config.rx_filter = HWTSTAMP_FILTER_SOME;
5003 break;
5004 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5005 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5006 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5007 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5008 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5009 is_l2 = 1;
5010 break;
5011 default:
5012 return -ERANGE;
5013 }
5014
5015 /* enable/disable TX */
5016 regval = rd32(E1000_TSYNCTXCTL);
5017 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5018 wr32(E1000_TSYNCTXCTL, regval);
5019
5020 /* enable/disable RX, define which PTP packets are time stamped */
5021 regval = rd32(E1000_TSYNCRXCTL);
5022 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5023 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5024 wr32(E1000_TSYNCRXCTL, regval);
5025 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5026
5027 /*
5028 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5029 * (Ethertype to filter on)
5030 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5031 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5032 */
5033 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5034
5035 /* L4 Queue Filter[0]: only filter by source and destination port */
5036 wr32(E1000_SPQF0, htons(port));
5037 wr32(E1000_IMIREXT(0), is_l4 ?
5038 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5039 wr32(E1000_IMIR(0), is_l4 ?
5040 (htons(port)
5041 | (0<<16) /* immediate interrupt disabled */
5042 | 0 /* (1<<17) bit cleared: do not bypass
5043 destination port check */)
5044 : 0);
5045 wr32(E1000_FTQF0, is_l4 ?
5046 (0x11 /* UDP */
5047 | (1<<15) /* VF not compared */
5048 | (1<<27) /* Enable Timestamping */
5049 | (7<<28) /* only source port filter enabled,
5050 source/target address and protocol
5051 masked */)
5052 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5053 enabled */));
5054
5055 wrfl();
5056
5057 adapter->hwtstamp_config = config;
5058
5059 /* clear TX/RX time stamp registers, just to be sure */
5060 regval = rd32(E1000_TXSTMPH);
5061 regval = rd32(E1000_RXSTMPH);
c6cb090b 5062
33af6bcc
PO		 5063 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5064 -EFAULT : 0;
c6cb090b
PO		 5065}
5066
9d5c8243
AK		 5067/**
5068 * igb_ioctl -
5069 * @netdev:
5070 * @ifreq:
5071 * @cmd:
5072 **/
5073static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5074{
5075 switch (cmd) {
5076 case SIOCGMIIPHY:
5077 case SIOCGMIIREG:
5078 case SIOCSMIIREG:
5079 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5080 case SIOCSHWTSTAMP:
5081 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5082 default:
5083 return -EOPNOTSUPP;
5084 }
5085}
5086
009bc06e
AD		 5087s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5088{
5089 struct igb_adapter *adapter = hw->back;
5090 u16 cap_offset;
5091
5092 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5093 if (!cap_offset)
5094 return -E1000_ERR_CONFIG;
5095
5096 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5097
5098 return 0;
5099}
5100
5101s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5102{
5103 struct igb_adapter *adapter = hw->back;
5104 u16 cap_offset;
5105
5106 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5107 if (!cap_offset)
5108 return -E1000_ERR_CONFIG;
5109
5110 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5111
5112 return 0;
5113}
5114
9d5c8243
AK		 5115static void igb_vlan_rx_register(struct net_device *netdev,
5116 struct vlan_group *grp)
5117{
5118 struct igb_adapter *adapter = netdev_priv(netdev);
5119 struct e1000_hw *hw = &adapter->hw;
5120 u32 ctrl, rctl;
5121
5122 igb_irq_disable(adapter);
5123 adapter->vlgrp = grp;
5124
5125 if (grp) {
5126 /* enable VLAN tag insert/strip */
5127 ctrl = rd32(E1000_CTRL);
5128 ctrl |= E1000_CTRL_VME;
5129 wr32(E1000_CTRL, ctrl);
5130
5131 /* enable VLAN receive filtering */
5132 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5133 rctl &= ~E1000_RCTL_CFIEN;
5134 wr32(E1000_RCTL, rctl);
5135 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5136 } else {
5137 /* disable VLAN tag insert/strip */
5138 ctrl = rd32(E1000_CTRL);
5139 ctrl &= ~E1000_CTRL_VME;
5140 wr32(E1000_CTRL, ctrl);
5141
9d5c8243
AK		 5142 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5143 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5144 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5145 }
9d5c8243
AK		 5146 }
5147
e1739522
AD		 5148 igb_rlpml_set(adapter);
5149
9d5c8243
AK		 5150 if (!test_bit(__IGB_DOWN, &adapter->state))
5151 igb_irq_enable(adapter);
5152}
5153
5154static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5155{
5156 struct igb_adapter *adapter = netdev_priv(netdev);
5157 struct e1000_hw *hw = &adapter->hw;
4ae196df 5158 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5159
28b0759c 5160 if ((hw->mng_cookie.status &
9d5c8243
AK		 5161 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5162 (vid == adapter->mng_vlan_id))
5163 return;
4ae196df
AD		 5164
5165 /* add vid to vlvf if sr-iov is enabled,
5166 * if that fails add directly to filter table */
5167 if (igb_vlvf_set(adapter, vid, true, pf_id))
5168 igb_vfta_set(hw, vid, true);
5169
9d5c8243
AK		 5170}
5171
5172static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5173{
5174 struct igb_adapter *adapter = netdev_priv(netdev);
5175 struct e1000_hw *hw = &adapter->hw;
4ae196df 5176 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5177
5178 igb_irq_disable(adapter);
5179 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5180
5181 if (!test_bit(__IGB_DOWN, &adapter->state))
5182 igb_irq_enable(adapter);
5183
5184 if ((adapter->hw.mng_cookie.status &
5185 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5186 (vid == adapter->mng_vlan_id)) {
5187 /* release control to f/w */
5188 igb_release_hw_control(adapter);
5189 return;
5190 }
5191
4ae196df
AD		 5192 /* remove vid from vlvf if sr-iov is enabled,
5193 * if not in vlvf remove from vfta */
5194 if (igb_vlvf_set(adapter, vid, false, pf_id))
5195 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5196}
5197
5198static void igb_restore_vlan(struct igb_adapter *adapter)
5199{
5200 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5201
5202 if (adapter->vlgrp) {
5203 u16 vid;
5204 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5205 if (!vlan_group_get_device(adapter->vlgrp, vid))
5206 continue;
5207 igb_vlan_rx_add_vid(adapter->netdev, vid);
5208 }
5209 }
5210}
5211
5212int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5213{
5214 struct e1000_mac_info *mac = &adapter->hw.mac;
5215
5216 mac->autoneg = 0;
5217
9d5c8243
AK		 5218 switch (spddplx) {
5219 case SPEED_10 + DUPLEX_HALF:
5220 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5221 break;
5222 case SPEED_10 + DUPLEX_FULL:
5223 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5224 break;
5225 case SPEED_100 + DUPLEX_HALF:
5226 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5227 break;
5228 case SPEED_100 + DUPLEX_FULL:
5229 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5230 break;
5231 case SPEED_1000 + DUPLEX_FULL:
5232 mac->autoneg = 1;
5233 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5234 break;
5235 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5236 default:
5237 dev_err(&adapter->pdev->dev,
5238 "Unsupported Speed/Duplex configuration\n");
5239 return -EINVAL;
5240 }
5241 return 0;
5242}
5243
3fe7c4c9 5244static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5245{
5246 struct net_device *netdev = pci_get_drvdata(pdev);
5247 struct igb_adapter *adapter = netdev_priv(netdev);
5248 struct e1000_hw *hw = &adapter->hw;
2d064c06 5249 u32 ctrl, rctl, status;
9d5c8243
AK		 5250 u32 wufc = adapter->wol;
5251#ifdef CONFIG_PM
5252 int retval = 0;
5253#endif
5254
5255 netif_device_detach(netdev);
5256
a88f10ec
AD		 5257 if (netif_running(netdev))
5258 igb_close(netdev);
5259
5260 igb_reset_interrupt_capability(adapter);
5261
5262 igb_free_queues(adapter);
9d5c8243
AK		 5263
5264#ifdef CONFIG_PM
5265 retval = pci_save_state(pdev);
5266 if (retval)
5267 return retval;
5268#endif
5269
5270 status = rd32(E1000_STATUS);
5271 if (status & E1000_STATUS_LU)
5272 wufc &= ~E1000_WUFC_LNKC;
5273
5274 if (wufc) {
5275 igb_setup_rctl(adapter);
ff41f8dc 5276 igb_set_rx_mode(netdev);
9d5c8243
AK		 5277
5278 /* turn on all-multi mode if wake on multicast is enabled */
5279 if (wufc & E1000_WUFC_MC) {
5280 rctl = rd32(E1000_RCTL);
5281 rctl |= E1000_RCTL_MPE;
5282 wr32(E1000_RCTL, rctl);
5283 }
5284
5285 ctrl = rd32(E1000_CTRL);
5286 /* advertise wake from D3Cold */
5287 #define E1000_CTRL_ADVD3WUC 0x00100000
5288 /* phy power management enable */
5289 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5290 ctrl |= E1000_CTRL_ADVD3WUC;
5291 wr32(E1000_CTRL, ctrl);
5292
9d5c8243
AK		 5293 /* Allow time for pending master requests to run */
5294 igb_disable_pcie_master(&adapter->hw);
5295
5296 wr32(E1000_WUC, E1000_WUC_PME_EN);
5297 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5298 } else {
5299 wr32(E1000_WUC, 0);
5300 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5301 }
5302
3fe7c4c9
RW		 5303 *enable_wake = wufc || adapter->en_mng_pt;
5304 if (!*enable_wake)
2fb02a26 5305 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5306
5307 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5308 * would have already happened in close and is redundant. */
5309 igb_release_hw_control(adapter);
5310
5311 pci_disable_device(pdev);
5312
9d5c8243
AK		 5313 return 0;
5314}
5315
5316#ifdef CONFIG_PM
3fe7c4c9
RW		 5317static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5318{
5319 int retval;
5320 bool wake;
5321
5322 retval = __igb_shutdown(pdev, &wake);
5323 if (retval)
5324 return retval;
5325
5326 if (wake) {
5327 pci_prepare_to_sleep(pdev);
5328 } else {
5329 pci_wake_from_d3(pdev, false);
5330 pci_set_power_state(pdev, PCI_D3hot);
5331 }
5332
5333 return 0;
5334}
5335
9d5c8243
AK		 5336static int igb_resume(struct pci_dev *pdev)
5337{
5338 struct net_device *netdev = pci_get_drvdata(pdev);
5339 struct igb_adapter *adapter = netdev_priv(netdev);
5340 struct e1000_hw *hw = &adapter->hw;
5341 u32 err;
5342
5343 pci_set_power_state(pdev, PCI_D0);
5344 pci_restore_state(pdev);
42bfd33a 5345
aed5dec3 5346 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5347 if (err) {
5348 dev_err(&pdev->dev,
5349 "igb: Cannot enable PCI device from suspend\n");
5350 return err;
5351 }
5352 pci_set_master(pdev);
5353
5354 pci_enable_wake(pdev, PCI_D3hot, 0);
5355 pci_enable_wake(pdev, PCI_D3cold, 0);
5356
a88f10ec
AD		 5357 igb_set_interrupt_capability(adapter);
5358
5359 if (igb_alloc_queues(adapter)) {
5360 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5361 return -ENOMEM;
9d5c8243
AK		 5362 }
5363
5364 /* e1000_power_up_phy(adapter); */
5365
5366 igb_reset(adapter);
a8564f03
AD		 5367
5368 /* let the f/w know that the h/w is now under the control of the
5369 * driver. */
5370 igb_get_hw_control(adapter);
5371
9d5c8243
AK		 5372 wr32(E1000_WUS, ~0);
5373
a88f10ec
AD		 5374 if (netif_running(netdev)) {
5375 err = igb_open(netdev);
5376 if (err)
5377 return err;
5378 }
9d5c8243
AK		 5379
5380 netif_device_attach(netdev);
5381
9d5c8243
AK		 5382 return 0;
5383}
5384#endif
5385
5386static void igb_shutdown(struct pci_dev *pdev)
5387{
3fe7c4c9
RW		 5388 bool wake;
5389
5390 __igb_shutdown(pdev, &wake);
5391
5392 if (system_state == SYSTEM_POWER_OFF) {
5393 pci_wake_from_d3(pdev, wake);
5394 pci_set_power_state(pdev, PCI_D3hot);
5395 }
9d5c8243
AK		 5396}
5397
5398#ifdef CONFIG_NET_POLL_CONTROLLER
5399/*
5400 * Polling 'interrupt' - used by things like netconsole to send skbs
5401 * without having to re-enable interrupts. It's not called while
5402 * the interrupt routine is executing.
5403 */
5404static void igb_netpoll(struct net_device *netdev)
5405{
5406 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5407 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5408 int i;
9d5c8243 5409
eebbbdba
AD		 5410 if (!adapter->msix_entries) {
5411 igb_irq_disable(adapter);
5412 napi_schedule(&adapter->rx_ring[0].napi);
5413 return;
5414 }
9d5c8243 5415
eebbbdba
AD		 5416 for (i = 0; i < adapter->num_tx_queues; i++) {
5417 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5418 wr32(E1000_EIMC, tx_ring->eims_value);
5419 igb_clean_tx_irq(tx_ring);
5420 wr32(E1000_EIMS, tx_ring->eims_value);
5421 }
9d5c8243 5422
eebbbdba
AD		 5423 for (i = 0; i < adapter->num_rx_queues; i++) {
5424 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5425 wr32(E1000_EIMC, rx_ring->eims_value);
5426 napi_schedule(&rx_ring->napi);
5427 }
9d5c8243
AK		 5428}
5429#endif /* CONFIG_NET_POLL_CONTROLLER */
5430
5431/**
5432 * igb_io_error_detected - called when PCI error is detected
5433 * @pdev: Pointer to PCI device
5434 * @state: The current pci connection state
5435 *
5436 * This function is called after a PCI bus error affecting
5437 * this device has been detected.
5438 */
5439static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5440 pci_channel_state_t state)
5441{
5442 struct net_device *netdev = pci_get_drvdata(pdev);
5443 struct igb_adapter *adapter = netdev_priv(netdev);
5444
5445 netif_device_detach(netdev);
5446
59ed6eec
AD		 5447 if (state == pci_channel_io_perm_failure)
5448 return PCI_ERS_RESULT_DISCONNECT;
5449
9d5c8243
AK		 5450 if (netif_running(netdev))
5451 igb_down(adapter);
5452 pci_disable_device(pdev);
5453
5454 /* Request a slot slot reset. */
5455 return PCI_ERS_RESULT_NEED_RESET;
5456}
5457
5458/**
5459 * igb_io_slot_reset - called after the pci bus has been reset.
5460 * @pdev: Pointer to PCI device
5461 *
5462 * Restart the card from scratch, as if from a cold-boot. Implementation
5463 * resembles the first-half of the igb_resume routine.
5464 */
5465static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5466{
5467 struct net_device *netdev = pci_get_drvdata(pdev);
5468 struct igb_adapter *adapter = netdev_priv(netdev);
5469 struct e1000_hw *hw = &adapter->hw;
40a914fa 5470 pci_ers_result_t result;
42bfd33a 5471 int err;
9d5c8243 5472
aed5dec3 5473 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5474 dev_err(&pdev->dev,
5475 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5476 result = PCI_ERS_RESULT_DISCONNECT;
5477 } else {
5478 pci_set_master(pdev);
5479 pci_restore_state(pdev);
9d5c8243 5480
40a914fa
AD		 5481 pci_enable_wake(pdev, PCI_D3hot, 0);
5482 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5483
40a914fa
AD		 5484 igb_reset(adapter);
5485 wr32(E1000_WUS, ~0);
5486 result = PCI_ERS_RESULT_RECOVERED;
5487 }
9d5c8243 5488
ea943d41
JK		 5489 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5490 if (err) {
5491 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5492 "failed 0x%0x\n", err);
5493 /* non-fatal, continue */
5494 }
40a914fa
AD		 5495
5496 return result;
9d5c8243
AK		 5497}
5498
5499/**
5500 * igb_io_resume - called when traffic can start flowing again.
5501 * @pdev: Pointer to PCI device
5502 *
5503 * This callback is called when the error recovery driver tells us that
5504 * its OK to resume normal operation. Implementation resembles the
5505 * second-half of the igb_resume routine.
5506 */
5507static void igb_io_resume(struct pci_dev *pdev)
5508{
5509 struct net_device *netdev = pci_get_drvdata(pdev);
5510 struct igb_adapter *adapter = netdev_priv(netdev);
5511
9d5c8243
AK		 5512 if (netif_running(netdev)) {
5513 if (igb_up(adapter)) {
5514 dev_err(&pdev->dev, "igb_up failed after reset\n");
5515 return;
5516 }
5517 }
5518
5519 netif_device_attach(netdev);
5520
5521 /* let the f/w know that the h/w is now under the control of the
5522 * driver. */
5523 igb_get_hw_control(adapter);
9d5c8243
AK		 5524}
5525
26ad9178
AD		 5526static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5527 u8 qsel)
5528{
5529 u32 rar_low, rar_high;
5530 struct e1000_hw *hw = &adapter->hw;
5531
5532 /* HW expects these in little endian so we reverse the byte order
5533 * from network order (big endian) to little endian
5534 */
5535 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5536 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5537 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5538
5539 /* Indicate to hardware the Address is Valid. */
5540 rar_high |= E1000_RAH_AV;
5541
5542 if (hw->mac.type == e1000_82575)
5543 rar_high |= E1000_RAH_POOL_1 * qsel;
5544 else
5545 rar_high |= E1000_RAH_POOL_1 << qsel;
5546
5547 wr32(E1000_RAL(index), rar_low);
5548 wrfl();
5549 wr32(E1000_RAH(index), rar_high);
5550 wrfl();
5551}
5552
4ae196df
AD		 5553static int igb_set_vf_mac(struct igb_adapter *adapter,
5554 int vf, unsigned char *mac_addr)
5555{
5556 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5557 /* VF MAC addresses start at end of receive addresses and moves
5558 * torwards the first, as a result a collision should not be possible */
5559 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5560
37680117 5561 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5562
26ad9178 5563 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5564
5565 return 0;
5566}
5567
5568static void igb_vmm_control(struct igb_adapter *adapter)
5569{
5570 struct e1000_hw *hw = &adapter->hw;
5571 u32 reg_data;
5572
5573 if (!adapter->vfs_allocated_count)
5574 return;
5575
5576 /* VF's need PF reset indication before they
5577 * can send/receive mail */
5578 reg_data = rd32(E1000_CTRL_EXT);
5579 reg_data |= E1000_CTRL_EXT_PFRSTD;
5580 wr32(E1000_CTRL_EXT, reg_data);
5581
5582 igb_vmdq_set_loopback_pf(hw, true);
5583 igb_vmdq_set_replication_pf(hw, true);
5584}
5585
9d5c8243 5586/* igb_main.c */
Clone of davem's net-next-2.6 tree