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Merge branch 'ebt_config_compat_v4' of git://git.breakpoint.cc/fw/nf-next-2.6
[net-next-2.6.git] / drivers / net / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
d43c36dc 37#include <linux/sched.h>
9d5c8243
AK		 38
39#include "igb.h"
40
41struct igb_stats {
42 char stat_string[ETH_GSTRING_LEN];
43 int sizeof_stat;
44 int stat_offset;
45};
46
128e45eb
AD		 47#define IGB_STAT(_name, _stat) { \
48 .stat_string = _name, \
49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
50 .stat_offset = offsetof(struct igb_adapter, _stat) \
51}
9d5c8243 52static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 53 IGB_STAT("rx_packets", stats.gprc),
54 IGB_STAT("tx_packets", stats.gptc),
55 IGB_STAT("rx_bytes", stats.gorc),
56 IGB_STAT("tx_bytes", stats.gotc),
57 IGB_STAT("rx_broadcast", stats.bprc),
58 IGB_STAT("tx_broadcast", stats.bptc),
59 IGB_STAT("rx_multicast", stats.mprc),
60 IGB_STAT("tx_multicast", stats.mptc),
61 IGB_STAT("multicast", stats.mprc),
62 IGB_STAT("collisions", stats.colc),
63 IGB_STAT("rx_crc_errors", stats.crcerrs),
64 IGB_STAT("rx_no_buffer_count", stats.rnbc),
65 IGB_STAT("rx_missed_errors", stats.mpc),
66 IGB_STAT("tx_aborted_errors", stats.ecol),
67 IGB_STAT("tx_carrier_errors", stats.tncrs),
68 IGB_STAT("tx_window_errors", stats.latecol),
69 IGB_STAT("tx_abort_late_coll", stats.latecol),
70 IGB_STAT("tx_deferred_ok", stats.dc),
71 IGB_STAT("tx_single_coll_ok", stats.scc),
72 IGB_STAT("tx_multi_coll_ok", stats.mcc),
73 IGB_STAT("tx_timeout_count", tx_timeout_count),
74 IGB_STAT("rx_long_length_errors", stats.roc),
75 IGB_STAT("rx_short_length_errors", stats.ruc),
76 IGB_STAT("rx_align_errors", stats.algnerrc),
77 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
79 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
81 IGB_STAT("tx_flow_control_xon", stats.xontxc),
82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
83 IGB_STAT("rx_long_byte_count", stats.gorc),
84 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
85 IGB_STAT("tx_smbus", stats.mgptc),
86 IGB_STAT("rx_smbus", stats.mgprc),
87 IGB_STAT("dropped_smbus", stats.mgpdc),
88};
89
90#define IGB_NETDEV_STAT(_net_stat) { \
91 .stat_string = __stringify(_net_stat), \
92 .sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \
93 .stat_offset = offsetof(struct net_device_stats, _net_stat) \
94}
95static const struct igb_stats igb_gstrings_net_stats[] = {
96 IGB_NETDEV_STAT(rx_errors),
97 IGB_NETDEV_STAT(tx_errors),
98 IGB_NETDEV_STAT(tx_dropped),
99 IGB_NETDEV_STAT(rx_length_errors),
100 IGB_NETDEV_STAT(rx_over_errors),
101 IGB_NETDEV_STAT(rx_frame_errors),
102 IGB_NETDEV_STAT(rx_fifo_errors),
103 IGB_NETDEV_STAT(tx_fifo_errors),
104 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 105};
106
128e45eb
AD		 107#define IGB_GLOBAL_STATS_LEN \
108 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
109#define IGB_NETDEV_STATS_LEN \
110 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
111#define IGB_RX_QUEUE_STATS_LEN \
112 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
113#define IGB_TX_QUEUE_STATS_LEN \
114 (sizeof(struct igb_tx_queue_stats) / sizeof(u64))
9d5c8243 115#define IGB_QUEUE_STATS_LEN \
317f66bd 116 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 117 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 118 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 119 IGB_TX_QUEUE_STATS_LEN))
120#define IGB_STATS_LEN \
121 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
122
9d5c8243
AK		 123static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
124 "Register test (offline)", "Eeprom test (offline)",
125 "Interrupt test (offline)", "Loopback test (offline)",
126 "Link test (on/offline)"
127};
317f66bd 128#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 129
130static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
131{
132 struct igb_adapter *adapter = netdev_priv(netdev);
133 struct e1000_hw *hw = &adapter->hw;
317f66bd 134 u32 status;
9d5c8243
AK		 135
136 if (hw->phy.media_type == e1000_media_type_copper) {
137
138 ecmd->supported = (SUPPORTED_10baseT_Half |
139 SUPPORTED_10baseT_Full |
140 SUPPORTED_100baseT_Half |
141 SUPPORTED_100baseT_Full |
142 SUPPORTED_1000baseT_Full|
143 SUPPORTED_Autoneg |
144 SUPPORTED_TP);
145 ecmd->advertising = ADVERTISED_TP;
146
147 if (hw->mac.autoneg == 1) {
148 ecmd->advertising |= ADVERTISED_Autoneg;
149 /* the e1000 autoneg seems to match ethtool nicely */
150 ecmd->advertising |= hw->phy.autoneg_advertised;
151 }
152
153 ecmd->port = PORT_TP;
154 ecmd->phy_address = hw->phy.addr;
155 } else {
156 ecmd->supported = (SUPPORTED_1000baseT_Full |
157 SUPPORTED_FIBRE |
158 SUPPORTED_Autoneg);
159
160 ecmd->advertising = (ADVERTISED_1000baseT_Full |
161 ADVERTISED_FIBRE |
162 ADVERTISED_Autoneg);
163
164 ecmd->port = PORT_FIBRE;
165 }
166
167 ecmd->transceiver = XCVR_INTERNAL;
168
317f66bd 169 status = rd32(E1000_STATUS);
9d5c8243 170
317f66bd 171 if (status & E1000_STATUS_LU) {
9d5c8243 172
317f66bd
AD		 173 if ((status & E1000_STATUS_SPEED_1000) ||
174 hw->phy.media_type != e1000_media_type_copper)
175 ecmd->speed = SPEED_1000;
176 else if (status & E1000_STATUS_SPEED_100)
177 ecmd->speed = SPEED_100;
178 else
179 ecmd->speed = SPEED_10;
9d5c8243 180
317f66bd
AD		 181 if ((status & E1000_STATUS_FD) ||
182 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 183 ecmd->duplex = DUPLEX_FULL;
184 else
185 ecmd->duplex = DUPLEX_HALF;
186 } else {
187 ecmd->speed = -1;
188 ecmd->duplex = -1;
189 }
190
dcc3ae9a 191 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
9d5c8243
AK		 192 return 0;
193}
194
195static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
196{
197 struct igb_adapter *adapter = netdev_priv(netdev);
198 struct e1000_hw *hw = &adapter->hw;
199
200 /* When SoL/IDER sessions are active, autoneg/speed/duplex
201 * cannot be changed */
202 if (igb_check_reset_block(hw)) {
203 dev_err(&adapter->pdev->dev, "Cannot change link "
204 "characteristics when SoL/IDER is active.\n");
205 return -EINVAL;
206 }
207
208 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
209 msleep(1);
210
211 if (ecmd->autoneg == AUTONEG_ENABLE) {
212 hw->mac.autoneg = 1;
dcc3ae9a
AD		 213 hw->phy.autoneg_advertised = ecmd->advertising |
214 ADVERTISED_TP |
215 ADVERTISED_Autoneg;
9d5c8243 216 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 217 if (adapter->fc_autoneg)
218 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 219 } else {
9d5c8243
AK		 220 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
221 clear_bit(__IGB_RESETTING, &adapter->state);
222 return -EINVAL;
223 }
dcc3ae9a 224 }
9d5c8243
AK		 225
226 /* reset the link */
9d5c8243
AK		 227 if (netif_running(adapter->netdev)) {
228 igb_down(adapter);
229 igb_up(adapter);
230 } else
231 igb_reset(adapter);
232
233 clear_bit(__IGB_RESETTING, &adapter->state);
234 return 0;
235}
236
3145535a
NN		 237static u32 igb_get_link(struct net_device *netdev)
238{
239 struct igb_adapter *adapter = netdev_priv(netdev);
240 struct e1000_mac_info *mac = &adapter->hw.mac;
241
242 /*
243 * If the link is not reported up to netdev, interrupts are disabled,
244 * and so the physical link state may have changed since we last
245 * looked. Set get_link_status to make sure that the true link
246 * state is interrogated, rather than pulling a cached and possibly
247 * stale link state from the driver.
248 */
249 if (!netif_carrier_ok(netdev))
250 mac->get_link_status = 1;
251
252 return igb_has_link(adapter);
253}
254
9d5c8243
AK		 255static void igb_get_pauseparam(struct net_device *netdev,
256 struct ethtool_pauseparam *pause)
257{
258 struct igb_adapter *adapter = netdev_priv(netdev);
259 struct e1000_hw *hw = &adapter->hw;
260
261 pause->autoneg =
262 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
263
0cce119a 264 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 265 pause->rx_pause = 1;
0cce119a 266 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 267 pause->tx_pause = 1;
0cce119a 268 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 269 pause->rx_pause = 1;
270 pause->tx_pause = 1;
271 }
272}
273
274static int igb_set_pauseparam(struct net_device *netdev,
275 struct ethtool_pauseparam *pause)
276{
277 struct igb_adapter *adapter = netdev_priv(netdev);
278 struct e1000_hw *hw = &adapter->hw;
279 int retval = 0;
280
281 adapter->fc_autoneg = pause->autoneg;
282
283 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
284 msleep(1);
285
9d5c8243 286 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 287 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 288 if (netif_running(adapter->netdev)) {
289 igb_down(adapter);
290 igb_up(adapter);
317f66bd 291 } else {
9d5c8243 292 igb_reset(adapter);
317f66bd 293 }
0cce119a
AD		 294 } else {
295 if (pause->rx_pause && pause->tx_pause)
296 hw->fc.requested_mode = e1000_fc_full;
297 else if (pause->rx_pause && !pause->tx_pause)
298 hw->fc.requested_mode = e1000_fc_rx_pause;
299 else if (!pause->rx_pause && pause->tx_pause)
300 hw->fc.requested_mode = e1000_fc_tx_pause;
301 else if (!pause->rx_pause && !pause->tx_pause)
302 hw->fc.requested_mode = e1000_fc_none;
303
304 hw->fc.current_mode = hw->fc.requested_mode;
305
dcc3ae9a
AD		 306 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
307 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 308 }
9d5c8243
AK		 309
310 clear_bit(__IGB_RESETTING, &adapter->state);
311 return retval;
312}
313
314static u32 igb_get_rx_csum(struct net_device *netdev)
315{
316 struct igb_adapter *adapter = netdev_priv(netdev);
3025a446 317 return !!(adapter->rx_ring[0]->flags & IGB_RING_FLAG_RX_CSUM);
9d5c8243
AK		 318}
319
320static int igb_set_rx_csum(struct net_device *netdev, u32 data)
321{
322 struct igb_adapter *adapter = netdev_priv(netdev);
85ad76b2 323 int i;
7beb0146 324
85ad76b2
AD		 325 for (i = 0; i < adapter->num_rx_queues; i++) {
326 if (data)
3025a446 327 adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM;
85ad76b2 328 else
3025a446 329 adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM;
85ad76b2 330 }
9d5c8243
AK		 331
332 return 0;
333}
334
335static u32 igb_get_tx_csum(struct net_device *netdev)
336{
7d8eb29e 337 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9d5c8243
AK		 338}
339
340static int igb_set_tx_csum(struct net_device *netdev, u32 data)
341{
b9473560
JB		 342 struct igb_adapter *adapter = netdev_priv(netdev);
343
344 if (data) {
7d8eb29e 345 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
317f66bd 346 if (adapter->hw.mac.type >= e1000_82576)
b9473560
JB		 347 netdev->features |= NETIF_F_SCTP_CSUM;
348 } else {
349 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
350 NETIF_F_SCTP_CSUM);
351 }
9d5c8243
AK		 352
353 return 0;
354}
355
356static int igb_set_tso(struct net_device *netdev, u32 data)
357{
358 struct igb_adapter *adapter = netdev_priv(netdev);
359
7d8eb29e 360 if (data) {
9d5c8243 361 netdev->features |= NETIF_F_TSO;
9d5c8243 362 netdev->features |= NETIF_F_TSO6;
7d8eb29e
AD		 363 } else {
364 netdev->features &= ~NETIF_F_TSO;
9d5c8243 365 netdev->features &= ~NETIF_F_TSO6;
7d8eb29e 366 }
9d5c8243
AK		 367
368 dev_info(&adapter->pdev->dev, "TSO is %s\n",
369 data ? "Enabled" : "Disabled");
370 return 0;
371}
372
373static u32 igb_get_msglevel(struct net_device *netdev)
374{
375 struct igb_adapter *adapter = netdev_priv(netdev);
376 return adapter->msg_enable;
377}
378
379static void igb_set_msglevel(struct net_device *netdev, u32 data)
380{
381 struct igb_adapter *adapter = netdev_priv(netdev);
382 adapter->msg_enable = data;
383}
384
385static int igb_get_regs_len(struct net_device *netdev)
386{
387#define IGB_REGS_LEN 551
388 return IGB_REGS_LEN * sizeof(u32);
389}
390
391static void igb_get_regs(struct net_device *netdev,
392 struct ethtool_regs *regs, void *p)
393{
394 struct igb_adapter *adapter = netdev_priv(netdev);
395 struct e1000_hw *hw = &adapter->hw;
396 u32 *regs_buff = p;
397 u8 i;
398
399 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
400
401 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
402
403 /* General Registers */
404 regs_buff[0] = rd32(E1000_CTRL);
405 regs_buff[1] = rd32(E1000_STATUS);
406 regs_buff[2] = rd32(E1000_CTRL_EXT);
407 regs_buff[3] = rd32(E1000_MDIC);
408 regs_buff[4] = rd32(E1000_SCTL);
409 regs_buff[5] = rd32(E1000_CONNSW);
410 regs_buff[6] = rd32(E1000_VET);
411 regs_buff[7] = rd32(E1000_LEDCTL);
412 regs_buff[8] = rd32(E1000_PBA);
413 regs_buff[9] = rd32(E1000_PBS);
414 regs_buff[10] = rd32(E1000_FRTIMER);
415 regs_buff[11] = rd32(E1000_TCPTIMER);
416
417 /* NVM Register */
418 regs_buff[12] = rd32(E1000_EECD);
419
420 /* Interrupt */
fe59de38
AD		 421 /* Reading EICS for EICR because they read the
422 * same but EICS does not clear on read */
423 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 424 regs_buff[14] = rd32(E1000_EICS);
425 regs_buff[15] = rd32(E1000_EIMS);
426 regs_buff[16] = rd32(E1000_EIMC);
427 regs_buff[17] = rd32(E1000_EIAC);
428 regs_buff[18] = rd32(E1000_EIAM);
fe59de38
AD		 429 /* Reading ICS for ICR because they read the
430 * same but ICS does not clear on read */
431 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 432 regs_buff[20] = rd32(E1000_ICS);
433 regs_buff[21] = rd32(E1000_IMS);
434 regs_buff[22] = rd32(E1000_IMC);
435 regs_buff[23] = rd32(E1000_IAC);
436 regs_buff[24] = rd32(E1000_IAM);
437 regs_buff[25] = rd32(E1000_IMIRVP);
438
439 /* Flow Control */
440 regs_buff[26] = rd32(E1000_FCAL);
441 regs_buff[27] = rd32(E1000_FCAH);
442 regs_buff[28] = rd32(E1000_FCTTV);
443 regs_buff[29] = rd32(E1000_FCRTL);
444 regs_buff[30] = rd32(E1000_FCRTH);
445 regs_buff[31] = rd32(E1000_FCRTV);
446
447 /* Receive */
448 regs_buff[32] = rd32(E1000_RCTL);
449 regs_buff[33] = rd32(E1000_RXCSUM);
450 regs_buff[34] = rd32(E1000_RLPML);
451 regs_buff[35] = rd32(E1000_RFCTL);
452 regs_buff[36] = rd32(E1000_MRQC);
e1739522 453 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 454
455 /* Transmit */
456 regs_buff[38] = rd32(E1000_TCTL);
457 regs_buff[39] = rd32(E1000_TCTL_EXT);
458 regs_buff[40] = rd32(E1000_TIPG);
459 regs_buff[41] = rd32(E1000_DTXCTL);
460
461 /* Wake Up */
462 regs_buff[42] = rd32(E1000_WUC);
463 regs_buff[43] = rd32(E1000_WUFC);
464 regs_buff[44] = rd32(E1000_WUS);
465 regs_buff[45] = rd32(E1000_IPAV);
466 regs_buff[46] = rd32(E1000_WUPL);
467
468 /* MAC */
469 regs_buff[47] = rd32(E1000_PCS_CFG0);
470 regs_buff[48] = rd32(E1000_PCS_LCTL);
471 regs_buff[49] = rd32(E1000_PCS_LSTAT);
472 regs_buff[50] = rd32(E1000_PCS_ANADV);
473 regs_buff[51] = rd32(E1000_PCS_LPAB);
474 regs_buff[52] = rd32(E1000_PCS_NPTX);
475 regs_buff[53] = rd32(E1000_PCS_LPABNP);
476
477 /* Statistics */
478 regs_buff[54] = adapter->stats.crcerrs;
479 regs_buff[55] = adapter->stats.algnerrc;
480 regs_buff[56] = adapter->stats.symerrs;
481 regs_buff[57] = adapter->stats.rxerrc;
482 regs_buff[58] = adapter->stats.mpc;
483 regs_buff[59] = adapter->stats.scc;
484 regs_buff[60] = adapter->stats.ecol;
485 regs_buff[61] = adapter->stats.mcc;
486 regs_buff[62] = adapter->stats.latecol;
487 regs_buff[63] = adapter->stats.colc;
488 regs_buff[64] = adapter->stats.dc;
489 regs_buff[65] = adapter->stats.tncrs;
490 regs_buff[66] = adapter->stats.sec;
491 regs_buff[67] = adapter->stats.htdpmc;
492 regs_buff[68] = adapter->stats.rlec;
493 regs_buff[69] = adapter->stats.xonrxc;
494 regs_buff[70] = adapter->stats.xontxc;
495 regs_buff[71] = adapter->stats.xoffrxc;
496 regs_buff[72] = adapter->stats.xofftxc;
497 regs_buff[73] = adapter->stats.fcruc;
498 regs_buff[74] = adapter->stats.prc64;
499 regs_buff[75] = adapter->stats.prc127;
500 regs_buff[76] = adapter->stats.prc255;
501 regs_buff[77] = adapter->stats.prc511;
502 regs_buff[78] = adapter->stats.prc1023;
503 regs_buff[79] = adapter->stats.prc1522;
504 regs_buff[80] = adapter->stats.gprc;
505 regs_buff[81] = adapter->stats.bprc;
506 regs_buff[82] = adapter->stats.mprc;
507 regs_buff[83] = adapter->stats.gptc;
508 regs_buff[84] = adapter->stats.gorc;
509 regs_buff[86] = adapter->stats.gotc;
510 regs_buff[88] = adapter->stats.rnbc;
511 regs_buff[89] = adapter->stats.ruc;
512 regs_buff[90] = adapter->stats.rfc;
513 regs_buff[91] = adapter->stats.roc;
514 regs_buff[92] = adapter->stats.rjc;
515 regs_buff[93] = adapter->stats.mgprc;
516 regs_buff[94] = adapter->stats.mgpdc;
517 regs_buff[95] = adapter->stats.mgptc;
518 regs_buff[96] = adapter->stats.tor;
519 regs_buff[98] = adapter->stats.tot;
520 regs_buff[100] = adapter->stats.tpr;
521 regs_buff[101] = adapter->stats.tpt;
522 regs_buff[102] = adapter->stats.ptc64;
523 regs_buff[103] = adapter->stats.ptc127;
524 regs_buff[104] = adapter->stats.ptc255;
525 regs_buff[105] = adapter->stats.ptc511;
526 regs_buff[106] = adapter->stats.ptc1023;
527 regs_buff[107] = adapter->stats.ptc1522;
528 regs_buff[108] = adapter->stats.mptc;
529 regs_buff[109] = adapter->stats.bptc;
530 regs_buff[110] = adapter->stats.tsctc;
531 regs_buff[111] = adapter->stats.iac;
532 regs_buff[112] = adapter->stats.rpthc;
533 regs_buff[113] = adapter->stats.hgptc;
534 regs_buff[114] = adapter->stats.hgorc;
535 regs_buff[116] = adapter->stats.hgotc;
536 regs_buff[118] = adapter->stats.lenerrs;
537 regs_buff[119] = adapter->stats.scvpc;
538 regs_buff[120] = adapter->stats.hrmpc;
539
9d5c8243
AK		 540 for (i = 0; i < 4; i++)
541 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
542 for (i = 0; i < 4; i++)
83ab50a5 543 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 544 for (i = 0; i < 4; i++)
545 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
546 for (i = 0; i < 4; i++)
547 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
548 for (i = 0; i < 4; i++)
549 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
550 for (i = 0; i < 4; i++)
551 regs_buff[141 + i] = rd32(E1000_RDH(i));
552 for (i = 0; i < 4; i++)
553 regs_buff[145 + i] = rd32(E1000_RDT(i));
554 for (i = 0; i < 4; i++)
555 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
556
557 for (i = 0; i < 10; i++)
558 regs_buff[153 + i] = rd32(E1000_EITR(i));
559 for (i = 0; i < 8; i++)
560 regs_buff[163 + i] = rd32(E1000_IMIR(i));
561 for (i = 0; i < 8; i++)
562 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
563 for (i = 0; i < 16; i++)
564 regs_buff[179 + i] = rd32(E1000_RAL(i));
565 for (i = 0; i < 16; i++)
566 regs_buff[195 + i] = rd32(E1000_RAH(i));
567
568 for (i = 0; i < 4; i++)
569 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
570 for (i = 0; i < 4; i++)
571 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
572 for (i = 0; i < 4; i++)
573 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
574 for (i = 0; i < 4; i++)
575 regs_buff[223 + i] = rd32(E1000_TDH(i));
576 for (i = 0; i < 4; i++)
577 regs_buff[227 + i] = rd32(E1000_TDT(i));
578 for (i = 0; i < 4; i++)
579 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
580 for (i = 0; i < 4; i++)
581 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
582 for (i = 0; i < 4; i++)
583 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
584 for (i = 0; i < 4; i++)
585 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
586
587 for (i = 0; i < 4; i++)
588 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
589 for (i = 0; i < 4; i++)
590 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
591 for (i = 0; i < 32; i++)
592 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
593 for (i = 0; i < 128; i++)
594 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
595 for (i = 0; i < 128; i++)
596 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
597 for (i = 0; i < 4; i++)
598 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
599
600 regs_buff[547] = rd32(E1000_TDFH);
601 regs_buff[548] = rd32(E1000_TDFT);
602 regs_buff[549] = rd32(E1000_TDFHS);
603 regs_buff[550] = rd32(E1000_TDFPC);
604
605}
606
607static int igb_get_eeprom_len(struct net_device *netdev)
608{
609 struct igb_adapter *adapter = netdev_priv(netdev);
610 return adapter->hw.nvm.word_size * 2;
611}
612
613static int igb_get_eeprom(struct net_device *netdev,
614 struct ethtool_eeprom *eeprom, u8 *bytes)
615{
616 struct igb_adapter *adapter = netdev_priv(netdev);
617 struct e1000_hw *hw = &adapter->hw;
618 u16 *eeprom_buff;
619 int first_word, last_word;
620 int ret_val = 0;
621 u16 i;
622
623 if (eeprom->len == 0)
624 return -EINVAL;
625
626 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
627
628 first_word = eeprom->offset >> 1;
629 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
630
631 eeprom_buff = kmalloc(sizeof(u16) *
632 (last_word - first_word + 1), GFP_KERNEL);
633 if (!eeprom_buff)
634 return -ENOMEM;
635
636 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 637 ret_val = hw->nvm.ops.read(hw, first_word,
9d5c8243
AK		 638 last_word - first_word + 1,
639 eeprom_buff);
640 else {
641 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 642 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
9d5c8243
AK		 643 &eeprom_buff[i]);
644 if (ret_val)
645 break;
646 }
647 }
648
649 /* Device's eeprom is always little-endian, word addressable */
650 for (i = 0; i < last_word - first_word + 1; i++)
651 le16_to_cpus(&eeprom_buff[i]);
652
653 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
654 eeprom->len);
655 kfree(eeprom_buff);
656
657 return ret_val;
658}
659
660static int igb_set_eeprom(struct net_device *netdev,
661 struct ethtool_eeprom *eeprom, u8 *bytes)
662{
663 struct igb_adapter *adapter = netdev_priv(netdev);
664 struct e1000_hw *hw = &adapter->hw;
665 u16 *eeprom_buff;
666 void *ptr;
667 int max_len, first_word, last_word, ret_val = 0;
668 u16 i;
669
670 if (eeprom->len == 0)
671 return -EOPNOTSUPP;
672
673 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
674 return -EFAULT;
675
676 max_len = hw->nvm.word_size * 2;
677
678 first_word = eeprom->offset >> 1;
679 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
680 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
681 if (!eeprom_buff)
682 return -ENOMEM;
683
684 ptr = (void *)eeprom_buff;
685
686 if (eeprom->offset & 1) {
687 /* need read/modify/write of first changed EEPROM word */
688 /* only the second byte of the word is being modified */
312c75ae 689 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 690 &eeprom_buff[0]);
691 ptr++;
692 }
693 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
694 /* need read/modify/write of last changed EEPROM word */
695 /* only the first byte of the word is being modified */
312c75ae 696 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 697 &eeprom_buff[last_word - first_word]);
698 }
699
700 /* Device's eeprom is always little-endian, word addressable */
701 for (i = 0; i < last_word - first_word + 1; i++)
702 le16_to_cpus(&eeprom_buff[i]);
703
704 memcpy(ptr, bytes, eeprom->len);
705
706 for (i = 0; i < last_word - first_word + 1; i++)
707 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
708
312c75ae 709 ret_val = hw->nvm.ops.write(hw, first_word,
9d5c8243
AK		 710 last_word - first_word + 1, eeprom_buff);
711
712 /* Update the checksum over the first part of the EEPROM if needed
713 * and flush shadow RAM for 82573 controllers */
714 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
715 igb_update_nvm_checksum(hw);
716
717 kfree(eeprom_buff);
718 return ret_val;
719}
720
721static void igb_get_drvinfo(struct net_device *netdev,
722 struct ethtool_drvinfo *drvinfo)
723{
724 struct igb_adapter *adapter = netdev_priv(netdev);
725 char firmware_version[32];
726 u16 eeprom_data;
727
728 strncpy(drvinfo->driver, igb_driver_name, 32);
729 strncpy(drvinfo->version, igb_driver_version, 32);
730
731 /* EEPROM image version # is reported as firmware version # for
732 * 82575 controllers */
312c75ae 733 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
9d5c8243
AK		 734 sprintf(firmware_version, "%d.%d-%d",
735 (eeprom_data & 0xF000) >> 12,
736 (eeprom_data & 0x0FF0) >> 4,
737 eeprom_data & 0x000F);
738
739 strncpy(drvinfo->fw_version, firmware_version, 32);
740 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
741 drvinfo->n_stats = IGB_STATS_LEN;
742 drvinfo->testinfo_len = IGB_TEST_LEN;
743 drvinfo->regdump_len = igb_get_regs_len(netdev);
744 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
745}
746
747static void igb_get_ringparam(struct net_device *netdev,
748 struct ethtool_ringparam *ring)
749{
750 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 751
752 ring->rx_max_pending = IGB_MAX_RXD;
753 ring->tx_max_pending = IGB_MAX_TXD;
754 ring->rx_mini_max_pending = 0;
755 ring->rx_jumbo_max_pending = 0;
68fd9910
AD		 756 ring->rx_pending = adapter->rx_ring_count;
757 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 758 ring->rx_mini_pending = 0;
759 ring->rx_jumbo_pending = 0;
760}
761
762static int igb_set_ringparam(struct net_device *netdev,
763 struct ethtool_ringparam *ring)
764{
765 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 766 struct igb_ring *temp_ring;
6d9f4fc4 767 int i, err = 0;
0e15439a 768 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 769
770 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
771 return -EINVAL;
772
0e15439a
AD		 773 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
774 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 775 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
776
0e15439a
AD		 777 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
778 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 779 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
780
68fd9910
AD		 781 if ((new_tx_count == adapter->tx_ring_count) &&
782 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 783 /* nothing to do */
784 return 0;
785 }
786
6d9f4fc4
AD		 787 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
788 msleep(1);
789
790 if (!netif_running(adapter->netdev)) {
791 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 792 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 793 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 794 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 795 adapter->tx_ring_count = new_tx_count;
796 adapter->rx_ring_count = new_rx_count;
797 goto clear_reset;
798 }
799
68fd9910
AD		 800 if (adapter->num_tx_queues > adapter->num_rx_queues)
801 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
802 else
803 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
68fd9910 804
6d9f4fc4
AD		 805 if (!temp_ring) {
806 err = -ENOMEM;
807 goto clear_reset;
808 }
9d5c8243 809
6d9f4fc4 810 igb_down(adapter);
9d5c8243
AK		 811
812 /*
813 * We can't just free everything and then setup again,
814 * because the ISRs in MSI-X mode get passed pointers
815 * to the tx and rx ring structs.
816 */
68fd9910 817 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 818 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 819 memcpy(&temp_ring[i], adapter->tx_ring[i],
820 sizeof(struct igb_ring));
821
68fd9910 822 temp_ring[i].count = new_tx_count;
80785298 823 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 824 if (err) {
68fd9910
AD		 825 while (i) {
826 i--;
827 igb_free_tx_resources(&temp_ring[i]);
828 }
9d5c8243
AK		 829 goto err_setup;
830 }
9d5c8243 831 }
68fd9910 832
3025a446
AD		 833 for (i = 0; i < adapter->num_tx_queues; i++) {
834 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 835
3025a446
AD		 836 memcpy(adapter->tx_ring[i], &temp_ring[i],
837 sizeof(struct igb_ring));
838 }
68fd9910
AD		 839
840 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 841 }
842
3025a446 843 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 844 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 845 memcpy(&temp_ring[i], adapter->rx_ring[i],
846 sizeof(struct igb_ring));
847
68fd9910 848 temp_ring[i].count = new_rx_count;
80785298 849 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 850 if (err) {
68fd9910
AD		 851 while (i) {
852 i--;
853 igb_free_rx_resources(&temp_ring[i]);
854 }
9d5c8243
AK		 855 goto err_setup;
856 }
857
9d5c8243 858 }
68fd9910 859
3025a446
AD		 860 for (i = 0; i < adapter->num_rx_queues; i++) {
861 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 862
3025a446
AD		 863 memcpy(adapter->rx_ring[i], &temp_ring[i],
864 sizeof(struct igb_ring));
865 }
68fd9910
AD		 866
867 adapter->rx_ring_count = new_rx_count;
9d5c8243 868 }
9d5c8243 869err_setup:
6d9f4fc4 870 igb_up(adapter);
68fd9910 871 vfree(temp_ring);
6d9f4fc4
AD		 872clear_reset:
873 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 874 return err;
875}
876
877/* ethtool register test data */
878struct igb_reg_test {
879 u16 reg;
2d064c06
AD		 880 u16 reg_offset;
881 u16 array_len;
882 u16 test_type;
9d5c8243
AK		 883 u32 mask;
884 u32 write;
885};
886
887/* In the hardware, registers are laid out either singly, in arrays
888 * spaced 0x100 bytes apart, or in contiguous tables. We assume
889 * most tests take place on arrays or single registers (handled
890 * as a single-element array) and special-case the tables.
891 * Table tests are always pattern tests.
892 *
893 * We also make provision for some required setup steps by specifying
894 * registers to be written without any read-back testing.
895 */
896
897#define PATTERN_TEST 1
898#define SET_READ_TEST 2
899#define WRITE_NO_TEST 3
900#define TABLE32_TEST 4
901#define TABLE64_TEST_LO 5
902#define TABLE64_TEST_HI 6
903
55cac248
AD		 904/* 82580 reg test */
905static struct igb_reg_test reg_test_82580[] = {
906 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
907 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
908 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
909 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
910 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
911 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
912 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
913 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
914 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
915 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
916 /* RDH is read-only for 82580, only test RDT. */
917 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
918 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
919 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
920 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
921 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
922 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
923 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
924 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
925 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
926 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
927 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
928 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
929 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
930 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
931 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
932 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
933 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
934 { E1000_RA, 0, 16, TABLE64_TEST_LO,
935 0xFFFFFFFF, 0xFFFFFFFF },
936 { E1000_RA, 0, 16, TABLE64_TEST_HI,
937 0x83FFFFFF, 0xFFFFFFFF },
938 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
939 0xFFFFFFFF, 0xFFFFFFFF },
940 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
941 0x83FFFFFF, 0xFFFFFFFF },
942 { E1000_MTA, 0, 128, TABLE32_TEST,
943 0xFFFFFFFF, 0xFFFFFFFF },
944 { 0, 0, 0, 0 }
945};
946
2d064c06
AD		 947/* 82576 reg test */
948static struct igb_reg_test reg_test_82576[] = {
949 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
950 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
951 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
952 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
953 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
954 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
955 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 956 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
957 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
958 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
959 /* Enable all RX queues before testing. */
960 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
961 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 962 /* RDH is read-only for 82576, only test RDT. */
963 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 964 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 965 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 966 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 967 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
968 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
969 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
970 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
971 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
972 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 973 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
974 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
975 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 976 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
977 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
978 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
979 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
980 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
981 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
982 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
983 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
984 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
985 { 0, 0, 0, 0 }
986};
987
988/* 82575 register test */
9d5c8243 989static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 990 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
991 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
992 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
993 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
994 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
995 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
996 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 997 /* Enable all four RX queues before testing. */
2d064c06 998 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 999 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 1000 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1001 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1002 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1003 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1004 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1005 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1006 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1007 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1008 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1009 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1010 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1011 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1012 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1013 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1014 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1015 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1016 { 0, 0, 0, 0 }
1017};
1018
1019static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1020 int reg, u32 mask, u32 write)
1021{
2753f4ce 1022 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1023 u32 pat, val;
317f66bd 1024 static const u32 _test[] =
9d5c8243
AK		 1025 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1026 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce
AD		 1027 wr32(reg, (_test[pat] & write));
1028 val = rd32(reg);
9d5c8243
AK		 1029 if (val != (_test[pat] & write & mask)) {
1030 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1031 "failed: got 0x%08X expected 0x%08X\n",
1032 reg, val, (_test[pat] & write & mask));
1033 *data = reg;
1034 return 1;
1035 }
1036 }
317f66bd 1037
9d5c8243
AK		 1038 return 0;
1039}
1040
1041static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1042 int reg, u32 mask, u32 write)
1043{
2753f4ce 1044 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1045 u32 val;
2753f4ce
AD		 1046 wr32(reg, write & mask);
1047 val = rd32(reg);
9d5c8243
AK		 1048 if ((write & mask) != (val & mask)) {
1049 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1050 " got 0x%08X expected 0x%08X\n", reg,
1051 (val & mask), (write & mask));
1052 *data = reg;
1053 return 1;
1054 }
317f66bd 1055
9d5c8243
AK		 1056 return 0;
1057}
1058
1059#define REG_PATTERN_TEST(reg, mask, write) \
1060 do { \
1061 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1062 return 1; \
1063 } while (0)
1064
1065#define REG_SET_AND_CHECK(reg, mask, write) \
1066 do { \
1067 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1068 return 1; \
1069 } while (0)
1070
1071static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1072{
1073 struct e1000_hw *hw = &adapter->hw;
1074 struct igb_reg_test *test;
1075 u32 value, before, after;
1076 u32 i, toggle;
1077
2d064c06 1078 switch (adapter->hw.mac.type) {
55cac248
AD		 1079 case e1000_82580:
1080 test = reg_test_82580;
1081 toggle = 0x7FEFF3FF;
1082 break;
2d064c06
AD		 1083 case e1000_82576:
1084 test = reg_test_82576;
317f66bd 1085 toggle = 0x7FFFF3FF;
2d064c06
AD		 1086 break;
1087 default:
1088 test = reg_test_82575;
317f66bd 1089 toggle = 0x7FFFF3FF;
2d064c06
AD		 1090 break;
1091 }
9d5c8243
AK		 1092
1093 /* Because the status register is such a special case,
1094 * we handle it separately from the rest of the register
1095 * tests. Some bits are read-only, some toggle, and some
1096 * are writable on newer MACs.
1097 */
1098 before = rd32(E1000_STATUS);
1099 value = (rd32(E1000_STATUS) & toggle);
1100 wr32(E1000_STATUS, toggle);
1101 after = rd32(E1000_STATUS) & toggle;
1102 if (value != after) {
1103 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1104 "got: 0x%08X expected: 0x%08X\n", after, value);
1105 *data = 1;
1106 return 1;
1107 }
1108 /* restore previous status */
1109 wr32(E1000_STATUS, before);
1110
1111 /* Perform the remainder of the register test, looping through
1112 * the test table until we either fail or reach the null entry.
1113 */
1114 while (test->reg) {
1115 for (i = 0; i < test->array_len; i++) {
1116 switch (test->test_type) {
1117 case PATTERN_TEST:
2753f4ce
AD		 1118 REG_PATTERN_TEST(test->reg +
1119 (i * test->reg_offset),
9d5c8243
AK		 1120 test->mask,
1121 test->write);
1122 break;
1123 case SET_READ_TEST:
2753f4ce
AD		 1124 REG_SET_AND_CHECK(test->reg +
1125 (i * test->reg_offset),
9d5c8243
AK		 1126 test->mask,
1127 test->write);
1128 break;
1129 case WRITE_NO_TEST:
1130 writel(test->write,
1131 (adapter->hw.hw_addr + test->reg)
2d064c06 1132 + (i * test->reg_offset));
9d5c8243
AK		 1133 break;
1134 case TABLE32_TEST:
1135 REG_PATTERN_TEST(test->reg + (i * 4),
1136 test->mask,
1137 test->write);
1138 break;
1139 case TABLE64_TEST_LO:
1140 REG_PATTERN_TEST(test->reg + (i * 8),
1141 test->mask,
1142 test->write);
1143 break;
1144 case TABLE64_TEST_HI:
1145 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1146 test->mask,
1147 test->write);
1148 break;
1149 }
1150 }
1151 test++;
1152 }
1153
1154 *data = 0;
1155 return 0;
1156}
1157
1158static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1159{
1160 u16 temp;
1161 u16 checksum = 0;
1162 u16 i;
1163
1164 *data = 0;
1165 /* Read and add up the contents of the EEPROM */
1166 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
317f66bd 1167 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
9d5c8243
AK		 1168 *data = 1;
1169 break;
1170 }
1171 checksum += temp;
1172 }
1173
1174 /* If Checksum is not Correct return error else test passed */
1175 if ((checksum != (u16) NVM_SUM) && !(*data))
1176 *data = 2;
1177
1178 return *data;
1179}
1180
1181static irqreturn_t igb_test_intr(int irq, void *data)
1182{
317f66bd 1183 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1184 struct e1000_hw *hw = &adapter->hw;
1185
1186 adapter->test_icr |= rd32(E1000_ICR);
1187
1188 return IRQ_HANDLED;
1189}
1190
1191static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1192{
1193 struct e1000_hw *hw = &adapter->hw;
1194 struct net_device *netdev = adapter->netdev;
2753f4ce 1195 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1196 u32 irq = adapter->pdev->irq;
1197
1198 *data = 0;
1199
1200 /* Hook up test interrupt handler just for this test */
4eefa8f0
AD		 1201 if (adapter->msix_entries) {
1202 if (request_irq(adapter->msix_entries[0].vector,
a0607fd3 1203 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1204 *data = 1;
1205 return -1;
1206 }
4eefa8f0 1207 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1208 shared_int = false;
4eefa8f0 1209 if (request_irq(irq,
a0607fd3 1210 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1211 *data = 1;
1212 return -1;
1213 }
a0607fd3 1214 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1215 netdev->name, adapter)) {
9d5c8243 1216 shared_int = false;
a0607fd3 1217 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1218 netdev->name, adapter)) {
9d5c8243
AK		 1219 *data = 1;
1220 return -1;
1221 }
1222 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1223 (shared_int ? "shared" : "unshared"));
317f66bd 1224
9d5c8243 1225 /* Disable all the interrupts */
4eefa8f0 1226 wr32(E1000_IMC, ~0);
9d5c8243
AK		 1227 msleep(10);
1228
2753f4ce 1229 /* Define all writable bits for ICS */
4eefa8f0 1230 switch (hw->mac.type) {
2753f4ce
AD		 1231 case e1000_82575:
1232 ics_mask = 0x37F47EDD;
1233 break;
1234 case e1000_82576:
1235 ics_mask = 0x77D4FBFD;
1236 break;
55cac248
AD		 1237 case e1000_82580:
1238 ics_mask = 0x77DCFED5;
1239 break;
2753f4ce
AD		 1240 default:
1241 ics_mask = 0x7FFFFFFF;
1242 break;
1243 }
1244
9d5c8243 1245 /* Test each interrupt */
2753f4ce 1246 for (; i < 31; i++) {
9d5c8243
AK		 1247 /* Interrupt to test */
1248 mask = 1 << i;
1249
2753f4ce
AD		 1250 if (!(mask & ics_mask))
1251 continue;
1252
9d5c8243
AK		 1253 if (!shared_int) {
1254 /* Disable the interrupt to be reported in
1255 * the cause register and then force the same
1256 * interrupt and see if one gets posted. If
1257 * an interrupt was posted to the bus, the
1258 * test failed.
1259 */
1260 adapter->test_icr = 0;
2753f4ce
AD		 1261
1262 /* Flush any pending interrupts */
1263 wr32(E1000_ICR, ~0);
1264
1265 wr32(E1000_IMC, mask);
1266 wr32(E1000_ICS, mask);
9d5c8243
AK		 1267 msleep(10);
1268
1269 if (adapter->test_icr & mask) {
1270 *data = 3;
1271 break;
1272 }
1273 }
1274
1275 /* Enable the interrupt to be reported in
1276 * the cause register and then force the same
1277 * interrupt and see if one gets posted. If
1278 * an interrupt was not posted to the bus, the
1279 * test failed.
1280 */
1281 adapter->test_icr = 0;
2753f4ce
AD		 1282
1283 /* Flush any pending interrupts */
1284 wr32(E1000_ICR, ~0);
1285
9d5c8243
AK		 1286 wr32(E1000_IMS, mask);
1287 wr32(E1000_ICS, mask);
1288 msleep(10);
1289
1290 if (!(adapter->test_icr & mask)) {
1291 *data = 4;
1292 break;
1293 }
1294
1295 if (!shared_int) {
1296 /* Disable the other interrupts to be reported in
1297 * the cause register and then force the other
1298 * interrupts and see if any get posted. If
1299 * an interrupt was posted to the bus, the
1300 * test failed.
1301 */
1302 adapter->test_icr = 0;
2753f4ce
AD		 1303
1304 /* Flush any pending interrupts */
1305 wr32(E1000_ICR, ~0);
1306
1307 wr32(E1000_IMC, ~mask);
1308 wr32(E1000_ICS, ~mask);
9d5c8243
AK		 1309 msleep(10);
1310
2753f4ce 1311 if (adapter->test_icr & mask) {
9d5c8243
AK		 1312 *data = 5;
1313 break;
1314 }
1315 }
1316 }
1317
1318 /* Disable all the interrupts */
2753f4ce 1319 wr32(E1000_IMC, ~0);
9d5c8243
AK		 1320 msleep(10);
1321
1322 /* Unhook test interrupt handler */
4eefa8f0
AD		 1323 if (adapter->msix_entries)
1324 free_irq(adapter->msix_entries[0].vector, adapter);
1325 else
1326 free_irq(irq, adapter);
9d5c8243
AK		 1327
1328 return *data;
1329}
1330
1331static void igb_free_desc_rings(struct igb_adapter *adapter)
1332{
d7ee5b3a
AD		 1333 igb_free_tx_resources(&adapter->test_tx_ring);
1334 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1335}
1336
1337static int igb_setup_desc_rings(struct igb_adapter *adapter)
1338{
9d5c8243
AK		 1339 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1340 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1341 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1342 int ret_val;
9d5c8243
AK		 1343
1344 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a
AD		 1345 tx_ring->count = IGB_DEFAULT_TXD;
1346 tx_ring->pdev = adapter->pdev;
1347 tx_ring->netdev = adapter->netdev;
1348 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1349
d7ee5b3a 1350 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1351 ret_val = 1;
1352 goto err_nomem;
1353 }
1354
d7ee5b3a
AD		 1355 igb_setup_tctl(adapter);
1356 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1357
9d5c8243 1358 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a
AD		 1359 rx_ring->count = IGB_DEFAULT_RXD;
1360 rx_ring->pdev = adapter->pdev;
1361 rx_ring->netdev = adapter->netdev;
1362 rx_ring->rx_buffer_len = IGB_RXBUFFER_2048;
1363 rx_ring->reg_idx = adapter->vfs_allocated_count;
1364
1365 if (igb_setup_rx_resources(rx_ring)) {
1366 ret_val = 3;
9d5c8243
AK		 1367 goto err_nomem;
1368 }
9d5c8243 1369
d7ee5b3a
AD		 1370 /* set the default queue to queue 0 of PF */
1371 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1372
d7ee5b3a
AD		 1373 /* enable receive ring */
1374 igb_setup_rctl(adapter);
1375 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1376
d7ee5b3a 1377 igb_alloc_rx_buffers_adv(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1378
1379 return 0;
1380
1381err_nomem:
1382 igb_free_desc_rings(adapter);
1383 return ret_val;
1384}
1385
1386static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1387{
1388 struct e1000_hw *hw = &adapter->hw;
1389
1390 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1391 igb_write_phy_reg(hw, 29, 0x001F);
1392 igb_write_phy_reg(hw, 30, 0x8FFC);
1393 igb_write_phy_reg(hw, 29, 0x001A);
1394 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1395}
1396
1397static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1398{
1399 struct e1000_hw *hw = &adapter->hw;
1400 u32 ctrl_reg = 0;
9d5c8243
AK		 1401
1402 hw->mac.autoneg = false;
1403
1404 if (hw->phy.type == e1000_phy_m88) {
1405 /* Auto-MDI/MDIX Off */
f5f4cf08 1406 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
9d5c8243 1407 /* reset to update Auto-MDI/MDIX */
f5f4cf08 1408 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
9d5c8243 1409 /* autoneg off */
f5f4cf08 1410 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
55cac248
AD		 1411 } else if (hw->phy.type == e1000_phy_82580) {
1412 /* enable MII loopback */
1413 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
9d5c8243
AK		 1414 }
1415
1416 ctrl_reg = rd32(E1000_CTRL);
1417
1418 /* force 1000, set loopback */
f5f4cf08 1419 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1420
1421 /* Now set up the MAC to the same speed/duplex as the PHY. */
1422 ctrl_reg = rd32(E1000_CTRL);
1423 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1424 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1425 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1426 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1427 E1000_CTRL_FD | /* Force Duplex to FULL */
1428 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1429
cdfa9f64 1430 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1431 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1432
1433 wr32(E1000_CTRL, ctrl_reg);
1434
1435 /* Disable the receiver on the PHY so when a cable is plugged in, the
1436 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1437 */
1438 if (hw->phy.type == e1000_phy_m88)
1439 igb_phy_disable_receiver(adapter);
1440
1441 udelay(500);
1442
1443 return 0;
1444}
1445
1446static int igb_set_phy_loopback(struct igb_adapter *adapter)
1447{
1448 return igb_integrated_phy_loopback(adapter);
1449}
1450
1451static int igb_setup_loopback_test(struct igb_adapter *adapter)
1452{
1453 struct e1000_hw *hw = &adapter->hw;
2d064c06 1454 u32 reg;
9d5c8243 1455
317f66bd
AD		 1456 reg = rd32(E1000_CTRL_EXT);
1457
1458 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1459 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
2d064c06
AD		 1460 reg = rd32(E1000_RCTL);
1461 reg |= E1000_RCTL_LBM_TCVR;
1462 wr32(E1000_RCTL, reg);
1463
1464 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1465
1466 reg = rd32(E1000_CTRL);
1467 reg &= ~(E1000_CTRL_RFCE |
1468 E1000_CTRL_TFCE |
1469 E1000_CTRL_LRST);
1470 reg |= E1000_CTRL_SLU |
2753f4ce 1471 E1000_CTRL_FD;
2d064c06
AD		 1472 wr32(E1000_CTRL, reg);
1473
1474 /* Unset switch control to serdes energy detect */
1475 reg = rd32(E1000_CONNSW);
1476 reg &= ~E1000_CONNSW_ENRGSRC;
1477 wr32(E1000_CONNSW, reg);
1478
1479 /* Set PCS register for forced speed */
1480 reg = rd32(E1000_PCS_LCTL);
1481 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1482 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1483 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1484 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1485 E1000_PCS_LCTL_FSD | /* Force Speed */
1486 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1487 wr32(E1000_PCS_LCTL, reg);
1488
9d5c8243 1489 return 0;
9d5c8243
AK		 1490 }
1491
317f66bd 1492 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1493}
1494
1495static void igb_loopback_cleanup(struct igb_adapter *adapter)
1496{
1497 struct e1000_hw *hw = &adapter->hw;
1498 u32 rctl;
1499 u16 phy_reg;
1500
1501 rctl = rd32(E1000_RCTL);
1502 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1503 wr32(E1000_RCTL, rctl);
1504
1505 hw->mac.autoneg = true;
f5f4cf08 1506 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1507 if (phy_reg & MII_CR_LOOPBACK) {
1508 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1509 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1510 igb_phy_sw_reset(hw);
1511 }
1512}
1513
1514static void igb_create_lbtest_frame(struct sk_buff *skb,
1515 unsigned int frame_size)
1516{
1517 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1518 frame_size /= 2;
1519 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1520 memset(&skb->data[frame_size + 10], 0xBE, 1);
1521 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1522}
1523
1524static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1525{
317f66bd
AD		 1526 frame_size /= 2;
1527 if (*(skb->data + 3) == 0xFF) {
1528 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1529 (*(skb->data + frame_size + 12) == 0xAF)) {
9d5c8243 1530 return 0;
317f66bd
AD		 1531 }
1532 }
9d5c8243
AK		 1533 return 13;
1534}
1535
ad93d17e
AD		 1536static int igb_clean_test_rings(struct igb_ring *rx_ring,
1537 struct igb_ring *tx_ring,
1538 unsigned int size)
1539{
1540 union e1000_adv_rx_desc *rx_desc;
1541 struct igb_buffer *buffer_info;
1542 int rx_ntc, tx_ntc, count = 0;
1543 u32 staterr;
1544
1545 /* initialize next to clean and descriptor values */
1546 rx_ntc = rx_ring->next_to_clean;
1547 tx_ntc = tx_ring->next_to_clean;
1548 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1549 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1550
1551 while (staterr & E1000_RXD_STAT_DD) {
1552 /* check rx buffer */
1553 buffer_info = &rx_ring->buffer_info[rx_ntc];
1554
1555 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
1556 pci_unmap_single(rx_ring->pdev,
1557 buffer_info->dma,
1558 rx_ring->rx_buffer_len,
1559 PCI_DMA_FROMDEVICE);
1560 buffer_info->dma = 0;
1561
1562 /* verify contents of skb */
1563 if (!igb_check_lbtest_frame(buffer_info->skb, size))
1564 count++;
1565
1566 /* unmap buffer on tx side */
1567 buffer_info = &tx_ring->buffer_info[tx_ntc];
1568 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
1569
1570 /* increment rx/tx next to clean counters */
1571 rx_ntc++;
1572 if (rx_ntc == rx_ring->count)
1573 rx_ntc = 0;
1574 tx_ntc++;
1575 if (tx_ntc == tx_ring->count)
1576 tx_ntc = 0;
1577
1578 /* fetch next descriptor */
1579 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1580 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1581 }
1582
1583 /* re-map buffers to ring, store next to clean values */
1584 igb_alloc_rx_buffers_adv(rx_ring, count);
1585 rx_ring->next_to_clean = rx_ntc;
1586 tx_ring->next_to_clean = tx_ntc;
1587
1588 return count;
1589}
1590
9d5c8243
AK		 1591static int igb_run_loopback_test(struct igb_adapter *adapter)
1592{
9d5c8243
AK		 1593 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1594 struct igb_ring *rx_ring = &adapter->test_rx_ring;
ad93d17e
AD		 1595 int i, j, lc, good_cnt, ret_val = 0;
1596 unsigned int size = 1024;
1597 netdev_tx_t tx_ret_val;
1598 struct sk_buff *skb;
1599
1600 /* allocate test skb */
1601 skb = alloc_skb(size, GFP_KERNEL);
1602 if (!skb)
1603 return 11;
9d5c8243 1604
ad93d17e
AD		 1605 /* place data into test skb */
1606 igb_create_lbtest_frame(skb, size);
1607 skb_put(skb, size);
9d5c8243 1608
317f66bd
AD		 1609 /*
1610 * Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1611 * The idea is to wrap the largest ring a number of times using 64
1612 * send/receive pairs during each loop
1613 */
1614
1615 if (rx_ring->count <= tx_ring->count)
1616 lc = ((tx_ring->count / 64) * 2) + 1;
1617 else
1618 lc = ((rx_ring->count / 64) * 2) + 1;
1619
9d5c8243 1620 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1621 /* reset count of good packets */
9d5c8243 1622 good_cnt = 0;
ad93d17e
AD		 1623
1624 /* place 64 packets on the transmit queue*/
1625 for (i = 0; i < 64; i++) {
1626 skb_get(skb);
1627 tx_ret_val = igb_xmit_frame_ring_adv(skb, tx_ring);
1628 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1629 good_cnt++;
ad93d17e
AD		 1630 }
1631
9d5c8243 1632 if (good_cnt != 64) {
ad93d17e 1633 ret_val = 12;
9d5c8243
AK		 1634 break;
1635 }
ad93d17e
AD		 1636
1637 /* allow 200 milliseconds for packets to go from tx to rx */
1638 msleep(200);
1639
1640 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1641 if (good_cnt != 64) {
1642 ret_val = 13;
9d5c8243
AK		 1643 break;
1644 }
1645 } /* end loop count loop */
ad93d17e
AD		 1646
1647 /* free the original skb */
1648 kfree_skb(skb);
1649
9d5c8243
AK		 1650 return ret_val;
1651}
1652
1653static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1654{
1655 /* PHY loopback cannot be performed if SoL/IDER
1656 * sessions are active */
1657 if (igb_check_reset_block(&adapter->hw)) {
1658 dev_err(&adapter->pdev->dev,
1659 "Cannot do PHY loopback test "
1660 "when SoL/IDER is active.\n");
1661 *data = 0;
1662 goto out;
1663 }
1664 *data = igb_setup_desc_rings(adapter);
1665 if (*data)
1666 goto out;
1667 *data = igb_setup_loopback_test(adapter);
1668 if (*data)
1669 goto err_loopback;
1670 *data = igb_run_loopback_test(adapter);
1671 igb_loopback_cleanup(adapter);
1672
1673err_loopback:
1674 igb_free_desc_rings(adapter);
1675out:
1676 return *data;
1677}
1678
1679static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1680{
1681 struct e1000_hw *hw = &adapter->hw;
1682 *data = 0;
1683 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1684 int i = 0;
1685 hw->mac.serdes_has_link = false;
1686
1687 /* On some blade server designs, link establishment
1688 * could take as long as 2-3 minutes */
1689 do {
1690 hw->mac.ops.check_for_link(&adapter->hw);
1691 if (hw->mac.serdes_has_link)
1692 return *data;
1693 msleep(20);
1694 } while (i++ < 3750);
1695
1696 *data = 1;
1697 } else {
1698 hw->mac.ops.check_for_link(&adapter->hw);
1699 if (hw->mac.autoneg)
1700 msleep(4000);
1701
317f66bd 1702 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1703 *data = 1;
1704 }
1705 return *data;
1706}
1707
1708static void igb_diag_test(struct net_device *netdev,
1709 struct ethtool_test *eth_test, u64 *data)
1710{
1711 struct igb_adapter *adapter = netdev_priv(netdev);
1712 u16 autoneg_advertised;
1713 u8 forced_speed_duplex, autoneg;
1714 bool if_running = netif_running(netdev);
1715
1716 set_bit(__IGB_TESTING, &adapter->state);
1717 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1718 /* Offline tests */
1719
1720 /* save speed, duplex, autoneg settings */
1721 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1722 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1723 autoneg = adapter->hw.mac.autoneg;
1724
1725 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1726
88a268c1
NN		 1727 /* power up link for link test */
1728 igb_power_up_link(adapter);
1729
9d5c8243
AK		 1730 /* Link test performed before hardware reset so autoneg doesn't
1731 * interfere with test result */
1732 if (igb_link_test(adapter, &data[4]))
1733 eth_test->flags |= ETH_TEST_FL_FAILED;
1734
1735 if (if_running)
1736 /* indicate we're in test mode */
1737 dev_close(netdev);
1738 else
1739 igb_reset(adapter);
1740
1741 if (igb_reg_test(adapter, &data[0]))
1742 eth_test->flags |= ETH_TEST_FL_FAILED;
1743
1744 igb_reset(adapter);
1745 if (igb_eeprom_test(adapter, &data[1]))
1746 eth_test->flags |= ETH_TEST_FL_FAILED;
1747
1748 igb_reset(adapter);
1749 if (igb_intr_test(adapter, &data[2]))
1750 eth_test->flags |= ETH_TEST_FL_FAILED;
1751
1752 igb_reset(adapter);
88a268c1
NN		 1753 /* power up link for loopback test */
1754 igb_power_up_link(adapter);
9d5c8243
AK		 1755 if (igb_loopback_test(adapter, &data[3]))
1756 eth_test->flags |= ETH_TEST_FL_FAILED;
1757
1758 /* restore speed, duplex, autoneg settings */
1759 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1760 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1761 adapter->hw.mac.autoneg = autoneg;
1762
1763 /* force this routine to wait until autoneg complete/timeout */
1764 adapter->hw.phy.autoneg_wait_to_complete = true;
1765 igb_reset(adapter);
1766 adapter->hw.phy.autoneg_wait_to_complete = false;
1767
1768 clear_bit(__IGB_TESTING, &adapter->state);
1769 if (if_running)
1770 dev_open(netdev);
1771 } else {
1772 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 1773
1774 /* PHY is powered down when interface is down */
1775 if (!netif_carrier_ok(netdev)) {
1776 data[4] = 0;
1777 } else {
1778 if (igb_link_test(adapter, &data[4]))
1779 eth_test->flags |= ETH_TEST_FL_FAILED;
1780 }
9d5c8243
AK		 1781
1782 /* Online tests aren't run; pass by default */
1783 data[0] = 0;
1784 data[1] = 0;
1785 data[2] = 0;
1786 data[3] = 0;
1787
1788 clear_bit(__IGB_TESTING, &adapter->state);
1789 }
1790 msleep_interruptible(4 * 1000);
1791}
1792
1793static int igb_wol_exclusion(struct igb_adapter *adapter,
1794 struct ethtool_wolinfo *wol)
1795{
1796 struct e1000_hw *hw = &adapter->hw;
1797 int retval = 1; /* fail by default */
1798
1799 switch (hw->device_id) {
1800 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1801 /* WoL not supported */
1802 wol->supported = 0;
1803 break;
1804 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1805 case E1000_DEV_ID_82576_FIBER:
1806 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1807 /* Wake events not supported on port B */
1808 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1809 wol->supported = 0;
1810 break;
1811 }
7dfc16fa
AD		 1812 /* return success for non excluded adapter ports */
1813 retval = 0;
1814 break;
c8ea5ea9
AD		 1815 case E1000_DEV_ID_82576_QUAD_COPPER:
1816 /* quad port adapters only support WoL on port A */
1817 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1818 wol->supported = 0;
1819 break;
1820 }
1821 /* return success for non excluded adapter ports */
1822 retval = 0;
1823 break;
9d5c8243
AK		 1824 default:
1825 /* dual port cards only support WoL on port A from now on
1826 * unless it was enabled in the eeprom for port B
1827 * so exclude FUNC_1 ports from having WoL enabled */
58b8b042 1828 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
9d5c8243
AK		 1829 !adapter->eeprom_wol) {
1830 wol->supported = 0;
1831 break;
1832 }
1833
1834 retval = 0;
1835 }
1836
1837 return retval;
1838}
1839
1840static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1841{
1842 struct igb_adapter *adapter = netdev_priv(netdev);
1843
1844 wol->supported = WAKE_UCAST | WAKE_MCAST |
22939f06
NN		 1845 WAKE_BCAST | WAKE_MAGIC |
1846 WAKE_PHY;
9d5c8243
AK		 1847 wol->wolopts = 0;
1848
1849 /* this function will set ->supported = 0 and return 1 if wol is not
1850 * supported by this hardware */
e1b86d84
RW		 1851 if (igb_wol_exclusion(adapter, wol) ||
1852 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1853 return;
1854
1855 /* apply any specific unsupported masks here */
1856 switch (adapter->hw.device_id) {
1857 default:
1858 break;
1859 }
1860
1861 if (adapter->wol & E1000_WUFC_EX)
1862 wol->wolopts |= WAKE_UCAST;
1863 if (adapter->wol & E1000_WUFC_MC)
1864 wol->wolopts |= WAKE_MCAST;
1865 if (adapter->wol & E1000_WUFC_BC)
1866 wol->wolopts |= WAKE_BCAST;
1867 if (adapter->wol & E1000_WUFC_MAG)
1868 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 1869 if (adapter->wol & E1000_WUFC_LNKC)
1870 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 1871}
1872
1873static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1874{
1875 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 1876
22939f06 1877 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 1878 return -EOPNOTSUPP;
1879
e1b86d84
RW		 1880 if (igb_wol_exclusion(adapter, wol) ||
1881 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1882 return wol->wolopts ? -EOPNOTSUPP : 0;
1883
9d5c8243
AK		 1884 /* these settings will always override what we currently have */
1885 adapter->wol = 0;
1886
1887 if (wol->wolopts & WAKE_UCAST)
1888 adapter->wol |= E1000_WUFC_EX;
1889 if (wol->wolopts & WAKE_MCAST)
1890 adapter->wol |= E1000_WUFC_MC;
1891 if (wol->wolopts & WAKE_BCAST)
1892 adapter->wol |= E1000_WUFC_BC;
1893 if (wol->wolopts & WAKE_MAGIC)
1894 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 1895 if (wol->wolopts & WAKE_PHY)
1896 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 1897 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1898
9d5c8243
AK		 1899 return 0;
1900}
1901
9d5c8243
AK		 1902/* bit defines for adapter->led_status */
1903#define IGB_LED_ON 0
1904
1905static int igb_phys_id(struct net_device *netdev, u32 data)
1906{
1907 struct igb_adapter *adapter = netdev_priv(netdev);
1908 struct e1000_hw *hw = &adapter->hw;
317f66bd 1909 unsigned long timeout;
9d5c8243 1910
317f66bd
AD		 1911 timeout = data * 1000;
1912
1913 /*
1914 * msleep_interruptable only accepts unsigned int so we are limited
1915 * in how long a duration we can wait
1916 */
1917 if (!timeout || timeout > UINT_MAX)
1918 timeout = UINT_MAX;
9d5c8243
AK		 1919
1920 igb_blink_led(hw);
317f66bd 1921 msleep_interruptible(timeout);
9d5c8243
AK		 1922
1923 igb_led_off(hw);
1924 clear_bit(IGB_LED_ON, &adapter->led_status);
1925 igb_cleanup_led(hw);
1926
1927 return 0;
1928}
1929
1930static int igb_set_coalesce(struct net_device *netdev,
1931 struct ethtool_coalesce *ec)
1932{
1933 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 1934 int i;
9d5c8243
AK		 1935
1936 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1937 ((ec->rx_coalesce_usecs > 3) &&
1938 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1939 (ec->rx_coalesce_usecs == 2))
1940 return -EINVAL;
1941
4fc82adf
AD		 1942 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1943 ((ec->tx_coalesce_usecs > 3) &&
1944 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1945 (ec->tx_coalesce_usecs == 2))
1946 return -EINVAL;
1947
1948 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
1949 return -EINVAL;
1950
9d5c8243 1951 /* convert to rate of irq's per second */
4fc82adf
AD		 1952 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
1953 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
1954 else
1955 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
1956
1957 /* convert to rate of irq's per second */
1958 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
1959 adapter->tx_itr_setting = adapter->rx_itr_setting;
1960 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
1961 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
1962 else
1963 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 1964
047e0030
AD		 1965 for (i = 0; i < adapter->num_q_vectors; i++) {
1966 struct igb_q_vector *q_vector = adapter->q_vector[i];
4fc82adf
AD		 1967 if (q_vector->rx_ring)
1968 q_vector->itr_val = adapter->rx_itr_setting;
1969 else
1970 q_vector->itr_val = adapter->tx_itr_setting;
1971 if (q_vector->itr_val && q_vector->itr_val <= 3)
1972 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1973 q_vector->set_itr = 1;
1974 }
9d5c8243
AK		 1975
1976 return 0;
1977}
1978
1979static int igb_get_coalesce(struct net_device *netdev,
1980 struct ethtool_coalesce *ec)
1981{
1982 struct igb_adapter *adapter = netdev_priv(netdev);
1983
4fc82adf
AD		 1984 if (adapter->rx_itr_setting <= 3)
1985 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 1986 else
4fc82adf
AD		 1987 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
1988
1989 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
1990 if (adapter->tx_itr_setting <= 3)
1991 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
1992 else
1993 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
1994 }
9d5c8243
AK		 1995
1996 return 0;
1997}
1998
9d5c8243
AK		 1999static int igb_nway_reset(struct net_device *netdev)
2000{
2001 struct igb_adapter *adapter = netdev_priv(netdev);
2002 if (netif_running(netdev))
2003 igb_reinit_locked(adapter);
2004 return 0;
2005}
2006
2007static int igb_get_sset_count(struct net_device *netdev, int sset)
2008{
2009 switch (sset) {
2010 case ETH_SS_STATS:
2011 return IGB_STATS_LEN;
2012 case ETH_SS_TEST:
2013 return IGB_TEST_LEN;
2014 default:
2015 return -ENOTSUPP;
2016 }
2017}
2018
2019static void igb_get_ethtool_stats(struct net_device *netdev,
2020 struct ethtool_stats *stats, u64 *data)
2021{
2022 struct igb_adapter *adapter = netdev_priv(netdev);
128e45eb 2023 struct net_device_stats *net_stats = &netdev->stats;
9d5c8243 2024 u64 *queue_stat;
128e45eb
AD		 2025 int i, j, k;
2026 char *p;
9d5c8243
AK		 2027
2028 igb_update_stats(adapter);
317f66bd 2029
9d5c8243 2030 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2031 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2032 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2033 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2034 }
128e45eb
AD		 2035 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2036 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2037 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2038 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2039 }
e21ed353 2040 for (j = 0; j < adapter->num_tx_queues; j++) {
3025a446 2041 queue_stat = (u64 *)&adapter->tx_ring[j]->tx_stats;
128e45eb
AD		 2042 for (k = 0; k < IGB_TX_QUEUE_STATS_LEN; k++, i++)
2043 data[i] = queue_stat[k];
e21ed353 2044 }
9d5c8243 2045 for (j = 0; j < adapter->num_rx_queues; j++) {
3025a446 2046 queue_stat = (u64 *)&adapter->rx_ring[j]->rx_stats;
128e45eb
AD		 2047 for (k = 0; k < IGB_RX_QUEUE_STATS_LEN; k++, i++)
2048 data[i] = queue_stat[k];
9d5c8243
AK		 2049 }
2050}
2051
2052static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2053{
2054 struct igb_adapter *adapter = netdev_priv(netdev);
2055 u8 *p = data;
2056 int i;
2057
2058 switch (stringset) {
2059 case ETH_SS_TEST:
2060 memcpy(data, *igb_gstrings_test,
2061 IGB_TEST_LEN*ETH_GSTRING_LEN);
2062 break;
2063 case ETH_SS_STATS:
2064 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2065 memcpy(p, igb_gstrings_stats[i].stat_string,
2066 ETH_GSTRING_LEN);
2067 p += ETH_GSTRING_LEN;
2068 }
128e45eb
AD		 2069 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2070 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2071 ETH_GSTRING_LEN);
2072 p += ETH_GSTRING_LEN;
2073 }
9d5c8243
AK		 2074 for (i = 0; i < adapter->num_tx_queues; i++) {
2075 sprintf(p, "tx_queue_%u_packets", i);
2076 p += ETH_GSTRING_LEN;
2077 sprintf(p, "tx_queue_%u_bytes", i);
2078 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2079 sprintf(p, "tx_queue_%u_restart", i);
2080 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2081 }
2082 for (i = 0; i < adapter->num_rx_queues; i++) {
2083 sprintf(p, "rx_queue_%u_packets", i);
2084 p += ETH_GSTRING_LEN;
2085 sprintf(p, "rx_queue_%u_bytes", i);
2086 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2087 sprintf(p, "rx_queue_%u_drops", i);
2088 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2089 sprintf(p, "rx_queue_%u_csum_err", i);
2090 p += ETH_GSTRING_LEN;
2091 sprintf(p, "rx_queue_%u_alloc_failed", i);
2092 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2093 }
2094/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2095 break;
2096 }
2097}
2098
0fc0b732 2099static const struct ethtool_ops igb_ethtool_ops = {
9d5c8243
AK		 2100 .get_settings = igb_get_settings,
2101 .set_settings = igb_set_settings,
2102 .get_drvinfo = igb_get_drvinfo,
2103 .get_regs_len = igb_get_regs_len,
2104 .get_regs = igb_get_regs,
2105 .get_wol = igb_get_wol,
2106 .set_wol = igb_set_wol,
2107 .get_msglevel = igb_get_msglevel,
2108 .set_msglevel = igb_set_msglevel,
2109 .nway_reset = igb_nway_reset,
3145535a 2110 .get_link = igb_get_link,
9d5c8243
AK		 2111 .get_eeprom_len = igb_get_eeprom_len,
2112 .get_eeprom = igb_get_eeprom,
2113 .set_eeprom = igb_set_eeprom,
2114 .get_ringparam = igb_get_ringparam,
2115 .set_ringparam = igb_set_ringparam,
2116 .get_pauseparam = igb_get_pauseparam,
2117 .set_pauseparam = igb_set_pauseparam,
2118 .get_rx_csum = igb_get_rx_csum,
2119 .set_rx_csum = igb_set_rx_csum,
2120 .get_tx_csum = igb_get_tx_csum,
2121 .set_tx_csum = igb_set_tx_csum,
2122 .get_sg = ethtool_op_get_sg,
2123 .set_sg = ethtool_op_set_sg,
2124 .get_tso = ethtool_op_get_tso,
2125 .set_tso = igb_set_tso,
2126 .self_test = igb_diag_test,
2127 .get_strings = igb_get_strings,
2128 .phys_id = igb_phys_id,
2129 .get_sset_count = igb_get_sset_count,
2130 .get_ethtool_stats = igb_get_ethtool_stats,
2131 .get_coalesce = igb_get_coalesce,
2132 .set_coalesce = igb_set_coalesce,
2133};
2134
2135void igb_set_ethtool_ops(struct net_device *netdev)
2136{
2137 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2138}
Clone of davem's net-next-2.6 tree