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igb: fix stats handling
[net-next-2.6.git] / drivers / net / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
d43c36dc 37#include <linux/sched.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39
40#include "igb.h"
41
42struct igb_stats {
43 char stat_string[ETH_GSTRING_LEN];
44 int sizeof_stat;
45 int stat_offset;
46};
47
128e45eb
AD		 48#define IGB_STAT(_name, _stat) { \
49 .stat_string = _name, \
50 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
51 .stat_offset = offsetof(struct igb_adapter, _stat) \
52}
9d5c8243 53static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 54 IGB_STAT("rx_packets", stats.gprc),
55 IGB_STAT("tx_packets", stats.gptc),
56 IGB_STAT("rx_bytes", stats.gorc),
57 IGB_STAT("tx_bytes", stats.gotc),
58 IGB_STAT("rx_broadcast", stats.bprc),
59 IGB_STAT("tx_broadcast", stats.bptc),
60 IGB_STAT("rx_multicast", stats.mprc),
61 IGB_STAT("tx_multicast", stats.mptc),
62 IGB_STAT("multicast", stats.mprc),
63 IGB_STAT("collisions", stats.colc),
64 IGB_STAT("rx_crc_errors", stats.crcerrs),
65 IGB_STAT("rx_no_buffer_count", stats.rnbc),
66 IGB_STAT("rx_missed_errors", stats.mpc),
67 IGB_STAT("tx_aborted_errors", stats.ecol),
68 IGB_STAT("tx_carrier_errors", stats.tncrs),
69 IGB_STAT("tx_window_errors", stats.latecol),
70 IGB_STAT("tx_abort_late_coll", stats.latecol),
71 IGB_STAT("tx_deferred_ok", stats.dc),
72 IGB_STAT("tx_single_coll_ok", stats.scc),
73 IGB_STAT("tx_multi_coll_ok", stats.mcc),
74 IGB_STAT("tx_timeout_count", tx_timeout_count),
75 IGB_STAT("rx_long_length_errors", stats.roc),
76 IGB_STAT("rx_short_length_errors", stats.ruc),
77 IGB_STAT("rx_align_errors", stats.algnerrc),
78 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
79 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
80 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
81 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
82 IGB_STAT("tx_flow_control_xon", stats.xontxc),
83 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
84 IGB_STAT("rx_long_byte_count", stats.gorc),
85 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
86 IGB_STAT("tx_smbus", stats.mgptc),
87 IGB_STAT("rx_smbus", stats.mgprc),
88 IGB_STAT("dropped_smbus", stats.mgpdc),
89};
90
91#define IGB_NETDEV_STAT(_net_stat) { \
92 .stat_string = __stringify(_net_stat), \
12dcd86b
ED		 93 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
94 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
128e45eb
AD		 95}
96static const struct igb_stats igb_gstrings_net_stats[] = {
97 IGB_NETDEV_STAT(rx_errors),
98 IGB_NETDEV_STAT(tx_errors),
99 IGB_NETDEV_STAT(tx_dropped),
100 IGB_NETDEV_STAT(rx_length_errors),
101 IGB_NETDEV_STAT(rx_over_errors),
102 IGB_NETDEV_STAT(rx_frame_errors),
103 IGB_NETDEV_STAT(rx_fifo_errors),
104 IGB_NETDEV_STAT(tx_fifo_errors),
105 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 106};
107
128e45eb
AD		 108#define IGB_GLOBAL_STATS_LEN \
109 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
110#define IGB_NETDEV_STATS_LEN \
111 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
112#define IGB_RX_QUEUE_STATS_LEN \
113 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
12dcd86b
ED		 114
115#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
116
9d5c8243 117#define IGB_QUEUE_STATS_LEN \
317f66bd 118 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 119 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 120 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 121 IGB_TX_QUEUE_STATS_LEN))
122#define IGB_STATS_LEN \
123 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
124
9d5c8243
AK		 125static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
126 "Register test (offline)", "Eeprom test (offline)",
127 "Interrupt test (offline)", "Loopback test (offline)",
128 "Link test (on/offline)"
129};
317f66bd 130#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 131
132static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
133{
134 struct igb_adapter *adapter = netdev_priv(netdev);
135 struct e1000_hw *hw = &adapter->hw;
317f66bd 136 u32 status;
9d5c8243
AK		 137
138 if (hw->phy.media_type == e1000_media_type_copper) {
139
140 ecmd->supported = (SUPPORTED_10baseT_Half |
141 SUPPORTED_10baseT_Full |
142 SUPPORTED_100baseT_Half |
143 SUPPORTED_100baseT_Full |
144 SUPPORTED_1000baseT_Full|
145 SUPPORTED_Autoneg |
146 SUPPORTED_TP);
147 ecmd->advertising = ADVERTISED_TP;
148
149 if (hw->mac.autoneg == 1) {
150 ecmd->advertising |= ADVERTISED_Autoneg;
151 /* the e1000 autoneg seems to match ethtool nicely */
152 ecmd->advertising |= hw->phy.autoneg_advertised;
153 }
154
155 ecmd->port = PORT_TP;
156 ecmd->phy_address = hw->phy.addr;
157 } else {
158 ecmd->supported = (SUPPORTED_1000baseT_Full |
159 SUPPORTED_FIBRE |
160 SUPPORTED_Autoneg);
161
162 ecmd->advertising = (ADVERTISED_1000baseT_Full |
163 ADVERTISED_FIBRE |
164 ADVERTISED_Autoneg);
165
166 ecmd->port = PORT_FIBRE;
167 }
168
169 ecmd->transceiver = XCVR_INTERNAL;
170
317f66bd 171 status = rd32(E1000_STATUS);
9d5c8243 172
317f66bd 173 if (status & E1000_STATUS_LU) {
9d5c8243 174
317f66bd
AD		 175 if ((status & E1000_STATUS_SPEED_1000) ||
176 hw->phy.media_type != e1000_media_type_copper)
177 ecmd->speed = SPEED_1000;
178 else if (status & E1000_STATUS_SPEED_100)
179 ecmd->speed = SPEED_100;
180 else
181 ecmd->speed = SPEED_10;
9d5c8243 182
317f66bd
AD		 183 if ((status & E1000_STATUS_FD) ||
184 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 185 ecmd->duplex = DUPLEX_FULL;
186 else
187 ecmd->duplex = DUPLEX_HALF;
188 } else {
189 ecmd->speed = -1;
190 ecmd->duplex = -1;
191 }
192
dcc3ae9a 193 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
9d5c8243
AK		 194 return 0;
195}
196
197static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
198{
199 struct igb_adapter *adapter = netdev_priv(netdev);
200 struct e1000_hw *hw = &adapter->hw;
201
202 /* When SoL/IDER sessions are active, autoneg/speed/duplex
203 * cannot be changed */
204 if (igb_check_reset_block(hw)) {
205 dev_err(&adapter->pdev->dev, "Cannot change link "
206 "characteristics when SoL/IDER is active.\n");
207 return -EINVAL;
208 }
209
210 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
211 msleep(1);
212
213 if (ecmd->autoneg == AUTONEG_ENABLE) {
214 hw->mac.autoneg = 1;
dcc3ae9a
AD		 215 hw->phy.autoneg_advertised = ecmd->advertising |
216 ADVERTISED_TP |
217 ADVERTISED_Autoneg;
9d5c8243 218 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 219 if (adapter->fc_autoneg)
220 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 221 } else {
9d5c8243
AK		 222 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
223 clear_bit(__IGB_RESETTING, &adapter->state);
224 return -EINVAL;
225 }
dcc3ae9a 226 }
9d5c8243
AK		 227
228 /* reset the link */
9d5c8243
AK		 229 if (netif_running(adapter->netdev)) {
230 igb_down(adapter);
231 igb_up(adapter);
232 } else
233 igb_reset(adapter);
234
235 clear_bit(__IGB_RESETTING, &adapter->state);
236 return 0;
237}
238
3145535a
NN		 239static u32 igb_get_link(struct net_device *netdev)
240{
241 struct igb_adapter *adapter = netdev_priv(netdev);
242 struct e1000_mac_info *mac = &adapter->hw.mac;
243
244 /*
245 * If the link is not reported up to netdev, interrupts are disabled,
246 * and so the physical link state may have changed since we last
247 * looked. Set get_link_status to make sure that the true link
248 * state is interrogated, rather than pulling a cached and possibly
249 * stale link state from the driver.
250 */
251 if (!netif_carrier_ok(netdev))
252 mac->get_link_status = 1;
253
254 return igb_has_link(adapter);
255}
256
9d5c8243
AK		 257static void igb_get_pauseparam(struct net_device *netdev,
258 struct ethtool_pauseparam *pause)
259{
260 struct igb_adapter *adapter = netdev_priv(netdev);
261 struct e1000_hw *hw = &adapter->hw;
262
263 pause->autoneg =
264 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
265
0cce119a 266 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 267 pause->rx_pause = 1;
0cce119a 268 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 269 pause->tx_pause = 1;
0cce119a 270 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 271 pause->rx_pause = 1;
272 pause->tx_pause = 1;
273 }
274}
275
276static int igb_set_pauseparam(struct net_device *netdev,
277 struct ethtool_pauseparam *pause)
278{
279 struct igb_adapter *adapter = netdev_priv(netdev);
280 struct e1000_hw *hw = &adapter->hw;
281 int retval = 0;
282
283 adapter->fc_autoneg = pause->autoneg;
284
285 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
286 msleep(1);
287
9d5c8243 288 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 289 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 290 if (netif_running(adapter->netdev)) {
291 igb_down(adapter);
292 igb_up(adapter);
317f66bd 293 } else {
9d5c8243 294 igb_reset(adapter);
317f66bd 295 }
0cce119a
AD		 296 } else {
297 if (pause->rx_pause && pause->tx_pause)
298 hw->fc.requested_mode = e1000_fc_full;
299 else if (pause->rx_pause && !pause->tx_pause)
300 hw->fc.requested_mode = e1000_fc_rx_pause;
301 else if (!pause->rx_pause && pause->tx_pause)
302 hw->fc.requested_mode = e1000_fc_tx_pause;
303 else if (!pause->rx_pause && !pause->tx_pause)
304 hw->fc.requested_mode = e1000_fc_none;
305
306 hw->fc.current_mode = hw->fc.requested_mode;
307
dcc3ae9a
AD		 308 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
309 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 310 }
9d5c8243
AK		 311
312 clear_bit(__IGB_RESETTING, &adapter->state);
313 return retval;
314}
315
316static u32 igb_get_rx_csum(struct net_device *netdev)
317{
318 struct igb_adapter *adapter = netdev_priv(netdev);
3025a446 319 return !!(adapter->rx_ring[0]->flags & IGB_RING_FLAG_RX_CSUM);
9d5c8243
AK		 320}
321
322static int igb_set_rx_csum(struct net_device *netdev, u32 data)
323{
324 struct igb_adapter *adapter = netdev_priv(netdev);
85ad76b2 325 int i;
7beb0146 326
85ad76b2
AD		 327 for (i = 0; i < adapter->num_rx_queues; i++) {
328 if (data)
3025a446 329 adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM;
85ad76b2 330 else
3025a446 331 adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM;
85ad76b2 332 }
9d5c8243
AK		 333
334 return 0;
335}
336
337static u32 igb_get_tx_csum(struct net_device *netdev)
338{
7d8eb29e 339 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9d5c8243
AK		 340}
341
342static int igb_set_tx_csum(struct net_device *netdev, u32 data)
343{
b9473560
JB		 344 struct igb_adapter *adapter = netdev_priv(netdev);
345
346 if (data) {
7d8eb29e 347 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
317f66bd 348 if (adapter->hw.mac.type >= e1000_82576)
b9473560
JB		 349 netdev->features |= NETIF_F_SCTP_CSUM;
350 } else {
351 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
352 NETIF_F_SCTP_CSUM);
353 }
9d5c8243
AK		 354
355 return 0;
356}
357
358static int igb_set_tso(struct net_device *netdev, u32 data)
359{
360 struct igb_adapter *adapter = netdev_priv(netdev);
361
7d8eb29e 362 if (data) {
9d5c8243 363 netdev->features |= NETIF_F_TSO;
9d5c8243 364 netdev->features |= NETIF_F_TSO6;
7d8eb29e
AD		 365 } else {
366 netdev->features &= ~NETIF_F_TSO;
9d5c8243 367 netdev->features &= ~NETIF_F_TSO6;
7d8eb29e 368 }
9d5c8243
AK		 369
370 dev_info(&adapter->pdev->dev, "TSO is %s\n",
371 data ? "Enabled" : "Disabled");
372 return 0;
373}
374
375static u32 igb_get_msglevel(struct net_device *netdev)
376{
377 struct igb_adapter *adapter = netdev_priv(netdev);
378 return adapter->msg_enable;
379}
380
381static void igb_set_msglevel(struct net_device *netdev, u32 data)
382{
383 struct igb_adapter *adapter = netdev_priv(netdev);
384 adapter->msg_enable = data;
385}
386
387static int igb_get_regs_len(struct net_device *netdev)
388{
389#define IGB_REGS_LEN 551
390 return IGB_REGS_LEN * sizeof(u32);
391}
392
393static void igb_get_regs(struct net_device *netdev,
394 struct ethtool_regs *regs, void *p)
395{
396 struct igb_adapter *adapter = netdev_priv(netdev);
397 struct e1000_hw *hw = &adapter->hw;
398 u32 *regs_buff = p;
399 u8 i;
400
401 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
402
403 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
404
405 /* General Registers */
406 regs_buff[0] = rd32(E1000_CTRL);
407 regs_buff[1] = rd32(E1000_STATUS);
408 regs_buff[2] = rd32(E1000_CTRL_EXT);
409 regs_buff[3] = rd32(E1000_MDIC);
410 regs_buff[4] = rd32(E1000_SCTL);
411 regs_buff[5] = rd32(E1000_CONNSW);
412 regs_buff[6] = rd32(E1000_VET);
413 regs_buff[7] = rd32(E1000_LEDCTL);
414 regs_buff[8] = rd32(E1000_PBA);
415 regs_buff[9] = rd32(E1000_PBS);
416 regs_buff[10] = rd32(E1000_FRTIMER);
417 regs_buff[11] = rd32(E1000_TCPTIMER);
418
419 /* NVM Register */
420 regs_buff[12] = rd32(E1000_EECD);
421
422 /* Interrupt */
fe59de38
AD		 423 /* Reading EICS for EICR because they read the
424 * same but EICS does not clear on read */
425 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 426 regs_buff[14] = rd32(E1000_EICS);
427 regs_buff[15] = rd32(E1000_EIMS);
428 regs_buff[16] = rd32(E1000_EIMC);
429 regs_buff[17] = rd32(E1000_EIAC);
430 regs_buff[18] = rd32(E1000_EIAM);
fe59de38
AD		 431 /* Reading ICS for ICR because they read the
432 * same but ICS does not clear on read */
433 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 434 regs_buff[20] = rd32(E1000_ICS);
435 regs_buff[21] = rd32(E1000_IMS);
436 regs_buff[22] = rd32(E1000_IMC);
437 regs_buff[23] = rd32(E1000_IAC);
438 regs_buff[24] = rd32(E1000_IAM);
439 regs_buff[25] = rd32(E1000_IMIRVP);
440
441 /* Flow Control */
442 regs_buff[26] = rd32(E1000_FCAL);
443 regs_buff[27] = rd32(E1000_FCAH);
444 regs_buff[28] = rd32(E1000_FCTTV);
445 regs_buff[29] = rd32(E1000_FCRTL);
446 regs_buff[30] = rd32(E1000_FCRTH);
447 regs_buff[31] = rd32(E1000_FCRTV);
448
449 /* Receive */
450 regs_buff[32] = rd32(E1000_RCTL);
451 regs_buff[33] = rd32(E1000_RXCSUM);
452 regs_buff[34] = rd32(E1000_RLPML);
453 regs_buff[35] = rd32(E1000_RFCTL);
454 regs_buff[36] = rd32(E1000_MRQC);
e1739522 455 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 456
457 /* Transmit */
458 regs_buff[38] = rd32(E1000_TCTL);
459 regs_buff[39] = rd32(E1000_TCTL_EXT);
460 regs_buff[40] = rd32(E1000_TIPG);
461 regs_buff[41] = rd32(E1000_DTXCTL);
462
463 /* Wake Up */
464 regs_buff[42] = rd32(E1000_WUC);
465 regs_buff[43] = rd32(E1000_WUFC);
466 regs_buff[44] = rd32(E1000_WUS);
467 regs_buff[45] = rd32(E1000_IPAV);
468 regs_buff[46] = rd32(E1000_WUPL);
469
470 /* MAC */
471 regs_buff[47] = rd32(E1000_PCS_CFG0);
472 regs_buff[48] = rd32(E1000_PCS_LCTL);
473 regs_buff[49] = rd32(E1000_PCS_LSTAT);
474 regs_buff[50] = rd32(E1000_PCS_ANADV);
475 regs_buff[51] = rd32(E1000_PCS_LPAB);
476 regs_buff[52] = rd32(E1000_PCS_NPTX);
477 regs_buff[53] = rd32(E1000_PCS_LPABNP);
478
479 /* Statistics */
480 regs_buff[54] = adapter->stats.crcerrs;
481 regs_buff[55] = adapter->stats.algnerrc;
482 regs_buff[56] = adapter->stats.symerrs;
483 regs_buff[57] = adapter->stats.rxerrc;
484 regs_buff[58] = adapter->stats.mpc;
485 regs_buff[59] = adapter->stats.scc;
486 regs_buff[60] = adapter->stats.ecol;
487 regs_buff[61] = adapter->stats.mcc;
488 regs_buff[62] = adapter->stats.latecol;
489 regs_buff[63] = adapter->stats.colc;
490 regs_buff[64] = adapter->stats.dc;
491 regs_buff[65] = adapter->stats.tncrs;
492 regs_buff[66] = adapter->stats.sec;
493 regs_buff[67] = adapter->stats.htdpmc;
494 regs_buff[68] = adapter->stats.rlec;
495 regs_buff[69] = adapter->stats.xonrxc;
496 regs_buff[70] = adapter->stats.xontxc;
497 regs_buff[71] = adapter->stats.xoffrxc;
498 regs_buff[72] = adapter->stats.xofftxc;
499 regs_buff[73] = adapter->stats.fcruc;
500 regs_buff[74] = adapter->stats.prc64;
501 regs_buff[75] = adapter->stats.prc127;
502 regs_buff[76] = adapter->stats.prc255;
503 regs_buff[77] = adapter->stats.prc511;
504 regs_buff[78] = adapter->stats.prc1023;
505 regs_buff[79] = adapter->stats.prc1522;
506 regs_buff[80] = adapter->stats.gprc;
507 regs_buff[81] = adapter->stats.bprc;
508 regs_buff[82] = adapter->stats.mprc;
509 regs_buff[83] = adapter->stats.gptc;
510 regs_buff[84] = adapter->stats.gorc;
511 regs_buff[86] = adapter->stats.gotc;
512 regs_buff[88] = adapter->stats.rnbc;
513 regs_buff[89] = adapter->stats.ruc;
514 regs_buff[90] = adapter->stats.rfc;
515 regs_buff[91] = adapter->stats.roc;
516 regs_buff[92] = adapter->stats.rjc;
517 regs_buff[93] = adapter->stats.mgprc;
518 regs_buff[94] = adapter->stats.mgpdc;
519 regs_buff[95] = adapter->stats.mgptc;
520 regs_buff[96] = adapter->stats.tor;
521 regs_buff[98] = adapter->stats.tot;
522 regs_buff[100] = adapter->stats.tpr;
523 regs_buff[101] = adapter->stats.tpt;
524 regs_buff[102] = adapter->stats.ptc64;
525 regs_buff[103] = adapter->stats.ptc127;
526 regs_buff[104] = adapter->stats.ptc255;
527 regs_buff[105] = adapter->stats.ptc511;
528 regs_buff[106] = adapter->stats.ptc1023;
529 regs_buff[107] = adapter->stats.ptc1522;
530 regs_buff[108] = adapter->stats.mptc;
531 regs_buff[109] = adapter->stats.bptc;
532 regs_buff[110] = adapter->stats.tsctc;
533 regs_buff[111] = adapter->stats.iac;
534 regs_buff[112] = adapter->stats.rpthc;
535 regs_buff[113] = adapter->stats.hgptc;
536 regs_buff[114] = adapter->stats.hgorc;
537 regs_buff[116] = adapter->stats.hgotc;
538 regs_buff[118] = adapter->stats.lenerrs;
539 regs_buff[119] = adapter->stats.scvpc;
540 regs_buff[120] = adapter->stats.hrmpc;
541
9d5c8243
AK		 542 for (i = 0; i < 4; i++)
543 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
544 for (i = 0; i < 4; i++)
83ab50a5 545 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 546 for (i = 0; i < 4; i++)
547 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
548 for (i = 0; i < 4; i++)
549 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
550 for (i = 0; i < 4; i++)
551 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
552 for (i = 0; i < 4; i++)
553 regs_buff[141 + i] = rd32(E1000_RDH(i));
554 for (i = 0; i < 4; i++)
555 regs_buff[145 + i] = rd32(E1000_RDT(i));
556 for (i = 0; i < 4; i++)
557 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
558
559 for (i = 0; i < 10; i++)
560 regs_buff[153 + i] = rd32(E1000_EITR(i));
561 for (i = 0; i < 8; i++)
562 regs_buff[163 + i] = rd32(E1000_IMIR(i));
563 for (i = 0; i < 8; i++)
564 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
565 for (i = 0; i < 16; i++)
566 regs_buff[179 + i] = rd32(E1000_RAL(i));
567 for (i = 0; i < 16; i++)
568 regs_buff[195 + i] = rd32(E1000_RAH(i));
569
570 for (i = 0; i < 4; i++)
571 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
572 for (i = 0; i < 4; i++)
573 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
574 for (i = 0; i < 4; i++)
575 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
576 for (i = 0; i < 4; i++)
577 regs_buff[223 + i] = rd32(E1000_TDH(i));
578 for (i = 0; i < 4; i++)
579 regs_buff[227 + i] = rd32(E1000_TDT(i));
580 for (i = 0; i < 4; i++)
581 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
582 for (i = 0; i < 4; i++)
583 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
584 for (i = 0; i < 4; i++)
585 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
586 for (i = 0; i < 4; i++)
587 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
588
589 for (i = 0; i < 4; i++)
590 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
591 for (i = 0; i < 4; i++)
592 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
593 for (i = 0; i < 32; i++)
594 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
595 for (i = 0; i < 128; i++)
596 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
597 for (i = 0; i < 128; i++)
598 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
599 for (i = 0; i < 4; i++)
600 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
601
602 regs_buff[547] = rd32(E1000_TDFH);
603 regs_buff[548] = rd32(E1000_TDFT);
604 regs_buff[549] = rd32(E1000_TDFHS);
605 regs_buff[550] = rd32(E1000_TDFPC);
606
607}
608
609static int igb_get_eeprom_len(struct net_device *netdev)
610{
611 struct igb_adapter *adapter = netdev_priv(netdev);
612 return adapter->hw.nvm.word_size * 2;
613}
614
615static int igb_get_eeprom(struct net_device *netdev,
616 struct ethtool_eeprom *eeprom, u8 *bytes)
617{
618 struct igb_adapter *adapter = netdev_priv(netdev);
619 struct e1000_hw *hw = &adapter->hw;
620 u16 *eeprom_buff;
621 int first_word, last_word;
622 int ret_val = 0;
623 u16 i;
624
625 if (eeprom->len == 0)
626 return -EINVAL;
627
628 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
629
630 first_word = eeprom->offset >> 1;
631 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
632
633 eeprom_buff = kmalloc(sizeof(u16) *
634 (last_word - first_word + 1), GFP_KERNEL);
635 if (!eeprom_buff)
636 return -ENOMEM;
637
638 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 639 ret_val = hw->nvm.ops.read(hw, first_word,
9d5c8243
AK		 640 last_word - first_word + 1,
641 eeprom_buff);
642 else {
643 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 644 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
9d5c8243
AK		 645 &eeprom_buff[i]);
646 if (ret_val)
647 break;
648 }
649 }
650
651 /* Device's eeprom is always little-endian, word addressable */
652 for (i = 0; i < last_word - first_word + 1; i++)
653 le16_to_cpus(&eeprom_buff[i]);
654
655 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
656 eeprom->len);
657 kfree(eeprom_buff);
658
659 return ret_val;
660}
661
662static int igb_set_eeprom(struct net_device *netdev,
663 struct ethtool_eeprom *eeprom, u8 *bytes)
664{
665 struct igb_adapter *adapter = netdev_priv(netdev);
666 struct e1000_hw *hw = &adapter->hw;
667 u16 *eeprom_buff;
668 void *ptr;
669 int max_len, first_word, last_word, ret_val = 0;
670 u16 i;
671
672 if (eeprom->len == 0)
673 return -EOPNOTSUPP;
674
675 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
676 return -EFAULT;
677
678 max_len = hw->nvm.word_size * 2;
679
680 first_word = eeprom->offset >> 1;
681 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
682 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
683 if (!eeprom_buff)
684 return -ENOMEM;
685
686 ptr = (void *)eeprom_buff;
687
688 if (eeprom->offset & 1) {
689 /* need read/modify/write of first changed EEPROM word */
690 /* only the second byte of the word is being modified */
312c75ae 691 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 692 &eeprom_buff[0]);
693 ptr++;
694 }
695 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
696 /* need read/modify/write of last changed EEPROM word */
697 /* only the first byte of the word is being modified */
312c75ae 698 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 699 &eeprom_buff[last_word - first_word]);
700 }
701
702 /* Device's eeprom is always little-endian, word addressable */
703 for (i = 0; i < last_word - first_word + 1; i++)
704 le16_to_cpus(&eeprom_buff[i]);
705
706 memcpy(ptr, bytes, eeprom->len);
707
708 for (i = 0; i < last_word - first_word + 1; i++)
709 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
710
312c75ae 711 ret_val = hw->nvm.ops.write(hw, first_word,
9d5c8243
AK		 712 last_word - first_word + 1, eeprom_buff);
713
714 /* Update the checksum over the first part of the EEPROM if needed
715 * and flush shadow RAM for 82573 controllers */
716 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
717 igb_update_nvm_checksum(hw);
718
719 kfree(eeprom_buff);
720 return ret_val;
721}
722
723static void igb_get_drvinfo(struct net_device *netdev,
724 struct ethtool_drvinfo *drvinfo)
725{
726 struct igb_adapter *adapter = netdev_priv(netdev);
727 char firmware_version[32];
728 u16 eeprom_data;
729
730 strncpy(drvinfo->driver, igb_driver_name, 32);
731 strncpy(drvinfo->version, igb_driver_version, 32);
732
733 /* EEPROM image version # is reported as firmware version # for
734 * 82575 controllers */
312c75ae 735 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
9d5c8243
AK		 736 sprintf(firmware_version, "%d.%d-%d",
737 (eeprom_data & 0xF000) >> 12,
738 (eeprom_data & 0x0FF0) >> 4,
739 eeprom_data & 0x000F);
740
741 strncpy(drvinfo->fw_version, firmware_version, 32);
742 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
743 drvinfo->n_stats = IGB_STATS_LEN;
744 drvinfo->testinfo_len = IGB_TEST_LEN;
745 drvinfo->regdump_len = igb_get_regs_len(netdev);
746 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
747}
748
749static void igb_get_ringparam(struct net_device *netdev,
750 struct ethtool_ringparam *ring)
751{
752 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 753
754 ring->rx_max_pending = IGB_MAX_RXD;
755 ring->tx_max_pending = IGB_MAX_TXD;
756 ring->rx_mini_max_pending = 0;
757 ring->rx_jumbo_max_pending = 0;
68fd9910
AD		 758 ring->rx_pending = adapter->rx_ring_count;
759 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 760 ring->rx_mini_pending = 0;
761 ring->rx_jumbo_pending = 0;
762}
763
764static int igb_set_ringparam(struct net_device *netdev,
765 struct ethtool_ringparam *ring)
766{
767 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 768 struct igb_ring *temp_ring;
6d9f4fc4 769 int i, err = 0;
0e15439a 770 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 771
772 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
773 return -EINVAL;
774
0e15439a
AD		 775 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
776 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 777 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
778
0e15439a
AD		 779 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
780 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 781 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
782
68fd9910
AD		 783 if ((new_tx_count == adapter->tx_ring_count) &&
784 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 785 /* nothing to do */
786 return 0;
787 }
788
6d9f4fc4
AD		 789 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
790 msleep(1);
791
792 if (!netif_running(adapter->netdev)) {
793 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 794 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 795 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 796 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 797 adapter->tx_ring_count = new_tx_count;
798 adapter->rx_ring_count = new_rx_count;
799 goto clear_reset;
800 }
801
68fd9910
AD		 802 if (adapter->num_tx_queues > adapter->num_rx_queues)
803 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
804 else
805 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
68fd9910 806
6d9f4fc4
AD		 807 if (!temp_ring) {
808 err = -ENOMEM;
809 goto clear_reset;
810 }
9d5c8243 811
6d9f4fc4 812 igb_down(adapter);
9d5c8243
AK		 813
814 /*
815 * We can't just free everything and then setup again,
816 * because the ISRs in MSI-X mode get passed pointers
817 * to the tx and rx ring structs.
818 */
68fd9910 819 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 820 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 821 memcpy(&temp_ring[i], adapter->tx_ring[i],
822 sizeof(struct igb_ring));
823
68fd9910 824 temp_ring[i].count = new_tx_count;
80785298 825 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 826 if (err) {
68fd9910
AD		 827 while (i) {
828 i--;
829 igb_free_tx_resources(&temp_ring[i]);
830 }
9d5c8243
AK		 831 goto err_setup;
832 }
9d5c8243 833 }
68fd9910 834
3025a446
AD		 835 for (i = 0; i < adapter->num_tx_queues; i++) {
836 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 837
3025a446
AD		 838 memcpy(adapter->tx_ring[i], &temp_ring[i],
839 sizeof(struct igb_ring));
840 }
68fd9910
AD		 841
842 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 843 }
844
3025a446 845 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 846 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 847 memcpy(&temp_ring[i], adapter->rx_ring[i],
848 sizeof(struct igb_ring));
849
68fd9910 850 temp_ring[i].count = new_rx_count;
80785298 851 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 852 if (err) {
68fd9910
AD		 853 while (i) {
854 i--;
855 igb_free_rx_resources(&temp_ring[i]);
856 }
9d5c8243
AK		 857 goto err_setup;
858 }
859
9d5c8243 860 }
68fd9910 861
3025a446
AD		 862 for (i = 0; i < adapter->num_rx_queues; i++) {
863 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 864
3025a446
AD		 865 memcpy(adapter->rx_ring[i], &temp_ring[i],
866 sizeof(struct igb_ring));
867 }
68fd9910
AD		 868
869 adapter->rx_ring_count = new_rx_count;
9d5c8243 870 }
9d5c8243 871err_setup:
6d9f4fc4 872 igb_up(adapter);
68fd9910 873 vfree(temp_ring);
6d9f4fc4
AD		 874clear_reset:
875 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 876 return err;
877}
878
879/* ethtool register test data */
880struct igb_reg_test {
881 u16 reg;
2d064c06
AD		 882 u16 reg_offset;
883 u16 array_len;
884 u16 test_type;
9d5c8243
AK		 885 u32 mask;
886 u32 write;
887};
888
889/* In the hardware, registers are laid out either singly, in arrays
890 * spaced 0x100 bytes apart, or in contiguous tables. We assume
891 * most tests take place on arrays or single registers (handled
892 * as a single-element array) and special-case the tables.
893 * Table tests are always pattern tests.
894 *
895 * We also make provision for some required setup steps by specifying
896 * registers to be written without any read-back testing.
897 */
898
899#define PATTERN_TEST 1
900#define SET_READ_TEST 2
901#define WRITE_NO_TEST 3
902#define TABLE32_TEST 4
903#define TABLE64_TEST_LO 5
904#define TABLE64_TEST_HI 6
905
d2ba2ed8
AD		 906/* i350 reg test */
907static struct igb_reg_test reg_test_i350[] = {
908 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
909 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
910 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
911 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
912 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
913 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 914 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 915 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
916 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 917 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 918 /* RDH is read-only for i350, only test RDT. */
919 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
920 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
921 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
922 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
923 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
924 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
925 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 926 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 927 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
928 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 929 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 930 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
931 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
932 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
933 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
934 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
935 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
936 { E1000_RA, 0, 16, TABLE64_TEST_LO,
937 0xFFFFFFFF, 0xFFFFFFFF },
938 { E1000_RA, 0, 16, TABLE64_TEST_HI,
939 0xC3FFFFFF, 0xFFFFFFFF },
940 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
941 0xFFFFFFFF, 0xFFFFFFFF },
942 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
943 0xC3FFFFFF, 0xFFFFFFFF },
944 { E1000_MTA, 0, 128, TABLE32_TEST,
945 0xFFFFFFFF, 0xFFFFFFFF },
946 { 0, 0, 0, 0 }
947};
948
55cac248
AD		 949/* 82580 reg test */
950static struct igb_reg_test reg_test_82580[] = {
951 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
952 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
953 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
954 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
955 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
956 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
957 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
958 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
959 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
960 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
961 /* RDH is read-only for 82580, only test RDT. */
962 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
963 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
964 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
965 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
966 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
967 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
968 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
969 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
970 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
971 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
972 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
973 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
974 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
975 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
976 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
977 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
978 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
979 { E1000_RA, 0, 16, TABLE64_TEST_LO,
980 0xFFFFFFFF, 0xFFFFFFFF },
981 { E1000_RA, 0, 16, TABLE64_TEST_HI,
982 0x83FFFFFF, 0xFFFFFFFF },
983 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
984 0xFFFFFFFF, 0xFFFFFFFF },
985 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
986 0x83FFFFFF, 0xFFFFFFFF },
987 { E1000_MTA, 0, 128, TABLE32_TEST,
988 0xFFFFFFFF, 0xFFFFFFFF },
989 { 0, 0, 0, 0 }
990};
991
2d064c06
AD		 992/* 82576 reg test */
993static struct igb_reg_test reg_test_82576[] = {
994 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
995 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
996 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
997 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
998 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
999 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1000 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1001 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1002 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1003 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1004 /* Enable all RX queues before testing. */
1005 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1006 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 1007 /* RDH is read-only for 82576, only test RDT. */
1008 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 1009 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 1010 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 1011 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 1012 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1013 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1014 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1015 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1016 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1017 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1018 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1019 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1020 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 1021 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1022 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1023 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1024 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1025 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1026 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1027 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1028 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1029 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1030 { 0, 0, 0, 0 }
1031};
1032
1033/* 82575 register test */
9d5c8243 1034static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 1035 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1036 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1037 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1038 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1039 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1040 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1041 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 1042 /* Enable all four RX queues before testing. */
2d064c06 1043 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 1044 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 1045 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1046 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1047 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1048 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1049 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1050 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1051 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1052 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1053 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1054 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1055 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1056 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1057 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1058 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1059 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1060 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1061 { 0, 0, 0, 0 }
1062};
1063
1064static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1065 int reg, u32 mask, u32 write)
1066{
2753f4ce 1067 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1068 u32 pat, val;
317f66bd 1069 static const u32 _test[] =
9d5c8243
AK		 1070 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1071 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce
AD		 1072 wr32(reg, (_test[pat] & write));
1073 val = rd32(reg);
9d5c8243
AK		 1074 if (val != (_test[pat] & write & mask)) {
1075 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1076 "failed: got 0x%08X expected 0x%08X\n",
1077 reg, val, (_test[pat] & write & mask));
1078 *data = reg;
1079 return 1;
1080 }
1081 }
317f66bd 1082
9d5c8243
AK		 1083 return 0;
1084}
1085
1086static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1087 int reg, u32 mask, u32 write)
1088{
2753f4ce 1089 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1090 u32 val;
2753f4ce
AD		 1091 wr32(reg, write & mask);
1092 val = rd32(reg);
9d5c8243
AK		 1093 if ((write & mask) != (val & mask)) {
1094 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1095 " got 0x%08X expected 0x%08X\n", reg,
1096 (val & mask), (write & mask));
1097 *data = reg;
1098 return 1;
1099 }
317f66bd 1100
9d5c8243
AK		 1101 return 0;
1102}
1103
1104#define REG_PATTERN_TEST(reg, mask, write) \
1105 do { \
1106 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1107 return 1; \
1108 } while (0)
1109
1110#define REG_SET_AND_CHECK(reg, mask, write) \
1111 do { \
1112 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1113 return 1; \
1114 } while (0)
1115
1116static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1117{
1118 struct e1000_hw *hw = &adapter->hw;
1119 struct igb_reg_test *test;
1120 u32 value, before, after;
1121 u32 i, toggle;
1122
2d064c06 1123 switch (adapter->hw.mac.type) {
d2ba2ed8
AD		 1124 case e1000_i350:
1125 test = reg_test_i350;
1126 toggle = 0x7FEFF3FF;
1127 break;
55cac248
AD		 1128 case e1000_82580:
1129 test = reg_test_82580;
1130 toggle = 0x7FEFF3FF;
1131 break;
2d064c06
AD		 1132 case e1000_82576:
1133 test = reg_test_82576;
317f66bd 1134 toggle = 0x7FFFF3FF;
2d064c06
AD		 1135 break;
1136 default:
1137 test = reg_test_82575;
317f66bd 1138 toggle = 0x7FFFF3FF;
2d064c06
AD		 1139 break;
1140 }
9d5c8243
AK		 1141
1142 /* Because the status register is such a special case,
1143 * we handle it separately from the rest of the register
1144 * tests. Some bits are read-only, some toggle, and some
1145 * are writable on newer MACs.
1146 */
1147 before = rd32(E1000_STATUS);
1148 value = (rd32(E1000_STATUS) & toggle);
1149 wr32(E1000_STATUS, toggle);
1150 after = rd32(E1000_STATUS) & toggle;
1151 if (value != after) {
1152 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1153 "got: 0x%08X expected: 0x%08X\n", after, value);
1154 *data = 1;
1155 return 1;
1156 }
1157 /* restore previous status */
1158 wr32(E1000_STATUS, before);
1159
1160 /* Perform the remainder of the register test, looping through
1161 * the test table until we either fail or reach the null entry.
1162 */
1163 while (test->reg) {
1164 for (i = 0; i < test->array_len; i++) {
1165 switch (test->test_type) {
1166 case PATTERN_TEST:
2753f4ce
AD		 1167 REG_PATTERN_TEST(test->reg +
1168 (i * test->reg_offset),
9d5c8243
AK		 1169 test->mask,
1170 test->write);
1171 break;
1172 case SET_READ_TEST:
2753f4ce
AD		 1173 REG_SET_AND_CHECK(test->reg +
1174 (i * test->reg_offset),
9d5c8243
AK		 1175 test->mask,
1176 test->write);
1177 break;
1178 case WRITE_NO_TEST:
1179 writel(test->write,
1180 (adapter->hw.hw_addr + test->reg)
2d064c06 1181 + (i * test->reg_offset));
9d5c8243
AK		 1182 break;
1183 case TABLE32_TEST:
1184 REG_PATTERN_TEST(test->reg + (i * 4),
1185 test->mask,
1186 test->write);
1187 break;
1188 case TABLE64_TEST_LO:
1189 REG_PATTERN_TEST(test->reg + (i * 8),
1190 test->mask,
1191 test->write);
1192 break;
1193 case TABLE64_TEST_HI:
1194 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1195 test->mask,
1196 test->write);
1197 break;
1198 }
1199 }
1200 test++;
1201 }
1202
1203 *data = 0;
1204 return 0;
1205}
1206
1207static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1208{
1209 u16 temp;
1210 u16 checksum = 0;
1211 u16 i;
1212
1213 *data = 0;
1214 /* Read and add up the contents of the EEPROM */
1215 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
317f66bd 1216 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
9d5c8243
AK		 1217 *data = 1;
1218 break;
1219 }
1220 checksum += temp;
1221 }
1222
1223 /* If Checksum is not Correct return error else test passed */
1224 if ((checksum != (u16) NVM_SUM) && !(*data))
1225 *data = 2;
1226
1227 return *data;
1228}
1229
1230static irqreturn_t igb_test_intr(int irq, void *data)
1231{
317f66bd 1232 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1233 struct e1000_hw *hw = &adapter->hw;
1234
1235 adapter->test_icr |= rd32(E1000_ICR);
1236
1237 return IRQ_HANDLED;
1238}
1239
1240static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1241{
1242 struct e1000_hw *hw = &adapter->hw;
1243 struct net_device *netdev = adapter->netdev;
2753f4ce 1244 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1245 u32 irq = adapter->pdev->irq;
1246
1247 *data = 0;
1248
1249 /* Hook up test interrupt handler just for this test */
4eefa8f0
AD		 1250 if (adapter->msix_entries) {
1251 if (request_irq(adapter->msix_entries[0].vector,
a0607fd3 1252 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1253 *data = 1;
1254 return -1;
1255 }
4eefa8f0 1256 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1257 shared_int = false;
4eefa8f0 1258 if (request_irq(irq,
a0607fd3 1259 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1260 *data = 1;
1261 return -1;
1262 }
a0607fd3 1263 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1264 netdev->name, adapter)) {
9d5c8243 1265 shared_int = false;
a0607fd3 1266 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1267 netdev->name, adapter)) {
9d5c8243
AK		 1268 *data = 1;
1269 return -1;
1270 }
1271 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1272 (shared_int ? "shared" : "unshared"));
317f66bd 1273
9d5c8243 1274 /* Disable all the interrupts */
4eefa8f0 1275 wr32(E1000_IMC, ~0);
9d5c8243
AK		 1276 msleep(10);
1277
2753f4ce 1278 /* Define all writable bits for ICS */
4eefa8f0 1279 switch (hw->mac.type) {
2753f4ce
AD		 1280 case e1000_82575:
1281 ics_mask = 0x37F47EDD;
1282 break;
1283 case e1000_82576:
1284 ics_mask = 0x77D4FBFD;
1285 break;
55cac248
AD		 1286 case e1000_82580:
1287 ics_mask = 0x77DCFED5;
1288 break;
d2ba2ed8
AD		 1289 case e1000_i350:
1290 ics_mask = 0x77DCFED5;
1291 break;
2753f4ce
AD		 1292 default:
1293 ics_mask = 0x7FFFFFFF;
1294 break;
1295 }
1296
9d5c8243 1297 /* Test each interrupt */
2753f4ce 1298 for (; i < 31; i++) {
9d5c8243
AK		 1299 /* Interrupt to test */
1300 mask = 1 << i;
1301
2753f4ce
AD		 1302 if (!(mask & ics_mask))
1303 continue;
1304
9d5c8243
AK		 1305 if (!shared_int) {
1306 /* Disable the interrupt to be reported in
1307 * the cause register and then force the same
1308 * interrupt and see if one gets posted. If
1309 * an interrupt was posted to the bus, the
1310 * test failed.
1311 */
1312 adapter->test_icr = 0;
2753f4ce
AD		 1313
1314 /* Flush any pending interrupts */
1315 wr32(E1000_ICR, ~0);
1316
1317 wr32(E1000_IMC, mask);
1318 wr32(E1000_ICS, mask);
9d5c8243
AK		 1319 msleep(10);
1320
1321 if (adapter->test_icr & mask) {
1322 *data = 3;
1323 break;
1324 }
1325 }
1326
1327 /* Enable the interrupt to be reported in
1328 * the cause register and then force the same
1329 * interrupt and see if one gets posted. If
1330 * an interrupt was not posted to the bus, the
1331 * test failed.
1332 */
1333 adapter->test_icr = 0;
2753f4ce
AD		 1334
1335 /* Flush any pending interrupts */
1336 wr32(E1000_ICR, ~0);
1337
9d5c8243
AK		 1338 wr32(E1000_IMS, mask);
1339 wr32(E1000_ICS, mask);
1340 msleep(10);
1341
1342 if (!(adapter->test_icr & mask)) {
1343 *data = 4;
1344 break;
1345 }
1346
1347 if (!shared_int) {
1348 /* Disable the other interrupts to be reported in
1349 * the cause register and then force the other
1350 * interrupts and see if any get posted. If
1351 * an interrupt was posted to the bus, the
1352 * test failed.
1353 */
1354 adapter->test_icr = 0;
2753f4ce
AD		 1355
1356 /* Flush any pending interrupts */
1357 wr32(E1000_ICR, ~0);
1358
1359 wr32(E1000_IMC, ~mask);
1360 wr32(E1000_ICS, ~mask);
9d5c8243
AK		 1361 msleep(10);
1362
2753f4ce 1363 if (adapter->test_icr & mask) {
9d5c8243
AK		 1364 *data = 5;
1365 break;
1366 }
1367 }
1368 }
1369
1370 /* Disable all the interrupts */
2753f4ce 1371 wr32(E1000_IMC, ~0);
9d5c8243
AK		 1372 msleep(10);
1373
1374 /* Unhook test interrupt handler */
4eefa8f0
AD		 1375 if (adapter->msix_entries)
1376 free_irq(adapter->msix_entries[0].vector, adapter);
1377 else
1378 free_irq(irq, adapter);
9d5c8243
AK		 1379
1380 return *data;
1381}
1382
1383static void igb_free_desc_rings(struct igb_adapter *adapter)
1384{
d7ee5b3a
AD		 1385 igb_free_tx_resources(&adapter->test_tx_ring);
1386 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1387}
1388
1389static int igb_setup_desc_rings(struct igb_adapter *adapter)
1390{
9d5c8243
AK		 1391 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1392 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1393 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1394 int ret_val;
9d5c8243
AK		 1395
1396 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a 1397 tx_ring->count = IGB_DEFAULT_TXD;
59d71989 1398 tx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1399 tx_ring->netdev = adapter->netdev;
1400 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1401
d7ee5b3a 1402 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1403 ret_val = 1;
1404 goto err_nomem;
1405 }
1406
d7ee5b3a
AD		 1407 igb_setup_tctl(adapter);
1408 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1409
9d5c8243 1410 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a 1411 rx_ring->count = IGB_DEFAULT_RXD;
59d71989 1412 rx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1413 rx_ring->netdev = adapter->netdev;
1414 rx_ring->rx_buffer_len = IGB_RXBUFFER_2048;
1415 rx_ring->reg_idx = adapter->vfs_allocated_count;
1416
1417 if (igb_setup_rx_resources(rx_ring)) {
1418 ret_val = 3;
9d5c8243
AK		 1419 goto err_nomem;
1420 }
9d5c8243 1421
d7ee5b3a
AD		 1422 /* set the default queue to queue 0 of PF */
1423 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1424
d7ee5b3a
AD		 1425 /* enable receive ring */
1426 igb_setup_rctl(adapter);
1427 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1428
d7ee5b3a 1429 igb_alloc_rx_buffers_adv(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1430
1431 return 0;
1432
1433err_nomem:
1434 igb_free_desc_rings(adapter);
1435 return ret_val;
1436}
1437
1438static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1439{
1440 struct e1000_hw *hw = &adapter->hw;
1441
1442 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1443 igb_write_phy_reg(hw, 29, 0x001F);
1444 igb_write_phy_reg(hw, 30, 0x8FFC);
1445 igb_write_phy_reg(hw, 29, 0x001A);
1446 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1447}
1448
1449static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1450{
1451 struct e1000_hw *hw = &adapter->hw;
1452 u32 ctrl_reg = 0;
9d5c8243
AK		 1453
1454 hw->mac.autoneg = false;
1455
1456 if (hw->phy.type == e1000_phy_m88) {
1457 /* Auto-MDI/MDIX Off */
f5f4cf08 1458 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
9d5c8243 1459 /* reset to update Auto-MDI/MDIX */
f5f4cf08 1460 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
9d5c8243 1461 /* autoneg off */
f5f4cf08 1462 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
55cac248
AD		 1463 } else if (hw->phy.type == e1000_phy_82580) {
1464 /* enable MII loopback */
1465 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
9d5c8243
AK		 1466 }
1467
1468 ctrl_reg = rd32(E1000_CTRL);
1469
1470 /* force 1000, set loopback */
f5f4cf08 1471 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1472
1473 /* Now set up the MAC to the same speed/duplex as the PHY. */
1474 ctrl_reg = rd32(E1000_CTRL);
1475 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1476 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1477 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1478 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1479 E1000_CTRL_FD | /* Force Duplex to FULL */
1480 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1481
cdfa9f64 1482 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1483 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1484
1485 wr32(E1000_CTRL, ctrl_reg);
1486
1487 /* Disable the receiver on the PHY so when a cable is plugged in, the
1488 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1489 */
1490 if (hw->phy.type == e1000_phy_m88)
1491 igb_phy_disable_receiver(adapter);
1492
1493 udelay(500);
1494
1495 return 0;
1496}
1497
1498static int igb_set_phy_loopback(struct igb_adapter *adapter)
1499{
1500 return igb_integrated_phy_loopback(adapter);
1501}
1502
1503static int igb_setup_loopback_test(struct igb_adapter *adapter)
1504{
1505 struct e1000_hw *hw = &adapter->hw;
2d064c06 1506 u32 reg;
9d5c8243 1507
317f66bd
AD		 1508 reg = rd32(E1000_CTRL_EXT);
1509
1510 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1511 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
2d064c06
AD		 1512 reg = rd32(E1000_RCTL);
1513 reg |= E1000_RCTL_LBM_TCVR;
1514 wr32(E1000_RCTL, reg);
1515
1516 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1517
1518 reg = rd32(E1000_CTRL);
1519 reg &= ~(E1000_CTRL_RFCE |
1520 E1000_CTRL_TFCE |
1521 E1000_CTRL_LRST);
1522 reg |= E1000_CTRL_SLU |
2753f4ce 1523 E1000_CTRL_FD;
2d064c06
AD		 1524 wr32(E1000_CTRL, reg);
1525
1526 /* Unset switch control to serdes energy detect */
1527 reg = rd32(E1000_CONNSW);
1528 reg &= ~E1000_CONNSW_ENRGSRC;
1529 wr32(E1000_CONNSW, reg);
1530
1531 /* Set PCS register for forced speed */
1532 reg = rd32(E1000_PCS_LCTL);
1533 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1534 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1535 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1536 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1537 E1000_PCS_LCTL_FSD | /* Force Speed */
1538 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1539 wr32(E1000_PCS_LCTL, reg);
1540
9d5c8243 1541 return 0;
9d5c8243
AK		 1542 }
1543
317f66bd 1544 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1545}
1546
1547static void igb_loopback_cleanup(struct igb_adapter *adapter)
1548{
1549 struct e1000_hw *hw = &adapter->hw;
1550 u32 rctl;
1551 u16 phy_reg;
1552
1553 rctl = rd32(E1000_RCTL);
1554 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1555 wr32(E1000_RCTL, rctl);
1556
1557 hw->mac.autoneg = true;
f5f4cf08 1558 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1559 if (phy_reg & MII_CR_LOOPBACK) {
1560 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1561 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1562 igb_phy_sw_reset(hw);
1563 }
1564}
1565
1566static void igb_create_lbtest_frame(struct sk_buff *skb,
1567 unsigned int frame_size)
1568{
1569 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1570 frame_size /= 2;
1571 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1572 memset(&skb->data[frame_size + 10], 0xBE, 1);
1573 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1574}
1575
1576static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1577{
317f66bd
AD		 1578 frame_size /= 2;
1579 if (*(skb->data + 3) == 0xFF) {
1580 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1581 (*(skb->data + frame_size + 12) == 0xAF)) {
9d5c8243 1582 return 0;
317f66bd
AD		 1583 }
1584 }
9d5c8243
AK		 1585 return 13;
1586}
1587
ad93d17e
AD		 1588static int igb_clean_test_rings(struct igb_ring *rx_ring,
1589 struct igb_ring *tx_ring,
1590 unsigned int size)
1591{
1592 union e1000_adv_rx_desc *rx_desc;
1593 struct igb_buffer *buffer_info;
1594 int rx_ntc, tx_ntc, count = 0;
1595 u32 staterr;
1596
1597 /* initialize next to clean and descriptor values */
1598 rx_ntc = rx_ring->next_to_clean;
1599 tx_ntc = tx_ring->next_to_clean;
1600 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1601 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1602
1603 while (staterr & E1000_RXD_STAT_DD) {
1604 /* check rx buffer */
1605 buffer_info = &rx_ring->buffer_info[rx_ntc];
1606
1607 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
59d71989 1608 dma_unmap_single(rx_ring->dev,
ad93d17e
AD		 1609 buffer_info->dma,
1610 rx_ring->rx_buffer_len,
59d71989 1611 DMA_FROM_DEVICE);
ad93d17e
AD		 1612 buffer_info->dma = 0;
1613
1614 /* verify contents of skb */
1615 if (!igb_check_lbtest_frame(buffer_info->skb, size))
1616 count++;
1617
1618 /* unmap buffer on tx side */
1619 buffer_info = &tx_ring->buffer_info[tx_ntc];
1620 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
1621
1622 /* increment rx/tx next to clean counters */
1623 rx_ntc++;
1624 if (rx_ntc == rx_ring->count)
1625 rx_ntc = 0;
1626 tx_ntc++;
1627 if (tx_ntc == tx_ring->count)
1628 tx_ntc = 0;
1629
1630 /* fetch next descriptor */
1631 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1632 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1633 }
1634
1635 /* re-map buffers to ring, store next to clean values */
1636 igb_alloc_rx_buffers_adv(rx_ring, count);
1637 rx_ring->next_to_clean = rx_ntc;
1638 tx_ring->next_to_clean = tx_ntc;
1639
1640 return count;
1641}
1642
9d5c8243
AK		 1643static int igb_run_loopback_test(struct igb_adapter *adapter)
1644{
9d5c8243
AK		 1645 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1646 struct igb_ring *rx_ring = &adapter->test_rx_ring;
ad93d17e
AD		 1647 int i, j, lc, good_cnt, ret_val = 0;
1648 unsigned int size = 1024;
1649 netdev_tx_t tx_ret_val;
1650 struct sk_buff *skb;
1651
1652 /* allocate test skb */
1653 skb = alloc_skb(size, GFP_KERNEL);
1654 if (!skb)
1655 return 11;
9d5c8243 1656
ad93d17e
AD		 1657 /* place data into test skb */
1658 igb_create_lbtest_frame(skb, size);
1659 skb_put(skb, size);
9d5c8243 1660
317f66bd
AD		 1661 /*
1662 * Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1663 * The idea is to wrap the largest ring a number of times using 64
1664 * send/receive pairs during each loop
1665 */
1666
1667 if (rx_ring->count <= tx_ring->count)
1668 lc = ((tx_ring->count / 64) * 2) + 1;
1669 else
1670 lc = ((rx_ring->count / 64) * 2) + 1;
1671
9d5c8243 1672 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1673 /* reset count of good packets */
9d5c8243 1674 good_cnt = 0;
ad93d17e
AD		 1675
1676 /* place 64 packets on the transmit queue*/
1677 for (i = 0; i < 64; i++) {
1678 skb_get(skb);
1679 tx_ret_val = igb_xmit_frame_ring_adv(skb, tx_ring);
1680 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1681 good_cnt++;
ad93d17e
AD		 1682 }
1683
9d5c8243 1684 if (good_cnt != 64) {
ad93d17e 1685 ret_val = 12;
9d5c8243
AK		 1686 break;
1687 }
ad93d17e
AD		 1688
1689 /* allow 200 milliseconds for packets to go from tx to rx */
1690 msleep(200);
1691
1692 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1693 if (good_cnt != 64) {
1694 ret_val = 13;
9d5c8243
AK		 1695 break;
1696 }
1697 } /* end loop count loop */
ad93d17e
AD		 1698
1699 /* free the original skb */
1700 kfree_skb(skb);
1701
9d5c8243
AK		 1702 return ret_val;
1703}
1704
1705static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1706{
1707 /* PHY loopback cannot be performed if SoL/IDER
1708 * sessions are active */
1709 if (igb_check_reset_block(&adapter->hw)) {
1710 dev_err(&adapter->pdev->dev,
1711 "Cannot do PHY loopback test "
1712 "when SoL/IDER is active.\n");
1713 *data = 0;
1714 goto out;
1715 }
1716 *data = igb_setup_desc_rings(adapter);
1717 if (*data)
1718 goto out;
1719 *data = igb_setup_loopback_test(adapter);
1720 if (*data)
1721 goto err_loopback;
1722 *data = igb_run_loopback_test(adapter);
1723 igb_loopback_cleanup(adapter);
1724
1725err_loopback:
1726 igb_free_desc_rings(adapter);
1727out:
1728 return *data;
1729}
1730
1731static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1732{
1733 struct e1000_hw *hw = &adapter->hw;
1734 *data = 0;
1735 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1736 int i = 0;
1737 hw->mac.serdes_has_link = false;
1738
1739 /* On some blade server designs, link establishment
1740 * could take as long as 2-3 minutes */
1741 do {
1742 hw->mac.ops.check_for_link(&adapter->hw);
1743 if (hw->mac.serdes_has_link)
1744 return *data;
1745 msleep(20);
1746 } while (i++ < 3750);
1747
1748 *data = 1;
1749 } else {
1750 hw->mac.ops.check_for_link(&adapter->hw);
1751 if (hw->mac.autoneg)
1752 msleep(4000);
1753
317f66bd 1754 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1755 *data = 1;
1756 }
1757 return *data;
1758}
1759
1760static void igb_diag_test(struct net_device *netdev,
1761 struct ethtool_test *eth_test, u64 *data)
1762{
1763 struct igb_adapter *adapter = netdev_priv(netdev);
1764 u16 autoneg_advertised;
1765 u8 forced_speed_duplex, autoneg;
1766 bool if_running = netif_running(netdev);
1767
1768 set_bit(__IGB_TESTING, &adapter->state);
1769 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1770 /* Offline tests */
1771
1772 /* save speed, duplex, autoneg settings */
1773 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1774 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1775 autoneg = adapter->hw.mac.autoneg;
1776
1777 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1778
88a268c1
NN		 1779 /* power up link for link test */
1780 igb_power_up_link(adapter);
1781
9d5c8243
AK		 1782 /* Link test performed before hardware reset so autoneg doesn't
1783 * interfere with test result */
1784 if (igb_link_test(adapter, &data[4]))
1785 eth_test->flags |= ETH_TEST_FL_FAILED;
1786
1787 if (if_running)
1788 /* indicate we're in test mode */
1789 dev_close(netdev);
1790 else
1791 igb_reset(adapter);
1792
1793 if (igb_reg_test(adapter, &data[0]))
1794 eth_test->flags |= ETH_TEST_FL_FAILED;
1795
1796 igb_reset(adapter);
1797 if (igb_eeprom_test(adapter, &data[1]))
1798 eth_test->flags |= ETH_TEST_FL_FAILED;
1799
1800 igb_reset(adapter);
1801 if (igb_intr_test(adapter, &data[2]))
1802 eth_test->flags |= ETH_TEST_FL_FAILED;
1803
1804 igb_reset(adapter);
88a268c1
NN		 1805 /* power up link for loopback test */
1806 igb_power_up_link(adapter);
9d5c8243
AK		 1807 if (igb_loopback_test(adapter, &data[3]))
1808 eth_test->flags |= ETH_TEST_FL_FAILED;
1809
1810 /* restore speed, duplex, autoneg settings */
1811 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1812 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1813 adapter->hw.mac.autoneg = autoneg;
1814
1815 /* force this routine to wait until autoneg complete/timeout */
1816 adapter->hw.phy.autoneg_wait_to_complete = true;
1817 igb_reset(adapter);
1818 adapter->hw.phy.autoneg_wait_to_complete = false;
1819
1820 clear_bit(__IGB_TESTING, &adapter->state);
1821 if (if_running)
1822 dev_open(netdev);
1823 } else {
1824 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 1825
1826 /* PHY is powered down when interface is down */
8d420a1b
AD		 1827 if (if_running && igb_link_test(adapter, &data[4]))
1828 eth_test->flags |= ETH_TEST_FL_FAILED;
1829 else
88a268c1 1830 data[4] = 0;
9d5c8243
AK		 1831
1832 /* Online tests aren't run; pass by default */
1833 data[0] = 0;
1834 data[1] = 0;
1835 data[2] = 0;
1836 data[3] = 0;
1837
1838 clear_bit(__IGB_TESTING, &adapter->state);
1839 }
1840 msleep_interruptible(4 * 1000);
1841}
1842
1843static int igb_wol_exclusion(struct igb_adapter *adapter,
1844 struct ethtool_wolinfo *wol)
1845{
1846 struct e1000_hw *hw = &adapter->hw;
1847 int retval = 1; /* fail by default */
1848
1849 switch (hw->device_id) {
1850 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1851 /* WoL not supported */
1852 wol->supported = 0;
1853 break;
1854 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1855 case E1000_DEV_ID_82576_FIBER:
1856 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1857 /* Wake events not supported on port B */
1858 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1859 wol->supported = 0;
1860 break;
1861 }
7dfc16fa
AD		 1862 /* return success for non excluded adapter ports */
1863 retval = 0;
1864 break;
c8ea5ea9 1865 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 1866 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 1867 /* quad port adapters only support WoL on port A */
1868 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1869 wol->supported = 0;
1870 break;
1871 }
1872 /* return success for non excluded adapter ports */
1873 retval = 0;
1874 break;
9d5c8243
AK		 1875 default:
1876 /* dual port cards only support WoL on port A from now on
1877 * unless it was enabled in the eeprom for port B
1878 * so exclude FUNC_1 ports from having WoL enabled */
58b8b042 1879 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
9d5c8243
AK		 1880 !adapter->eeprom_wol) {
1881 wol->supported = 0;
1882 break;
1883 }
1884
1885 retval = 0;
1886 }
1887
1888 return retval;
1889}
1890
1891static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1892{
1893 struct igb_adapter *adapter = netdev_priv(netdev);
1894
1895 wol->supported = WAKE_UCAST | WAKE_MCAST |
22939f06
NN		 1896 WAKE_BCAST | WAKE_MAGIC |
1897 WAKE_PHY;
9d5c8243
AK		 1898 wol->wolopts = 0;
1899
1900 /* this function will set ->supported = 0 and return 1 if wol is not
1901 * supported by this hardware */
e1b86d84
RW		 1902 if (igb_wol_exclusion(adapter, wol) ||
1903 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1904 return;
1905
1906 /* apply any specific unsupported masks here */
1907 switch (adapter->hw.device_id) {
1908 default:
1909 break;
1910 }
1911
1912 if (adapter->wol & E1000_WUFC_EX)
1913 wol->wolopts |= WAKE_UCAST;
1914 if (adapter->wol & E1000_WUFC_MC)
1915 wol->wolopts |= WAKE_MCAST;
1916 if (adapter->wol & E1000_WUFC_BC)
1917 wol->wolopts |= WAKE_BCAST;
1918 if (adapter->wol & E1000_WUFC_MAG)
1919 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 1920 if (adapter->wol & E1000_WUFC_LNKC)
1921 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 1922}
1923
1924static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1925{
1926 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 1927
22939f06 1928 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 1929 return -EOPNOTSUPP;
1930
e1b86d84
RW		 1931 if (igb_wol_exclusion(adapter, wol) ||
1932 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1933 return wol->wolopts ? -EOPNOTSUPP : 0;
1934
9d5c8243
AK		 1935 /* these settings will always override what we currently have */
1936 adapter->wol = 0;
1937
1938 if (wol->wolopts & WAKE_UCAST)
1939 adapter->wol |= E1000_WUFC_EX;
1940 if (wol->wolopts & WAKE_MCAST)
1941 adapter->wol |= E1000_WUFC_MC;
1942 if (wol->wolopts & WAKE_BCAST)
1943 adapter->wol |= E1000_WUFC_BC;
1944 if (wol->wolopts & WAKE_MAGIC)
1945 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 1946 if (wol->wolopts & WAKE_PHY)
1947 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 1948 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1949
9d5c8243
AK		 1950 return 0;
1951}
1952
9d5c8243
AK		 1953/* bit defines for adapter->led_status */
1954#define IGB_LED_ON 0
1955
1956static int igb_phys_id(struct net_device *netdev, u32 data)
1957{
1958 struct igb_adapter *adapter = netdev_priv(netdev);
1959 struct e1000_hw *hw = &adapter->hw;
317f66bd 1960 unsigned long timeout;
9d5c8243 1961
317f66bd
AD		 1962 timeout = data * 1000;
1963
1964 /*
1965 * msleep_interruptable only accepts unsigned int so we are limited
1966 * in how long a duration we can wait
1967 */
1968 if (!timeout || timeout > UINT_MAX)
1969 timeout = UINT_MAX;
9d5c8243
AK		 1970
1971 igb_blink_led(hw);
317f66bd 1972 msleep_interruptible(timeout);
9d5c8243
AK		 1973
1974 igb_led_off(hw);
1975 clear_bit(IGB_LED_ON, &adapter->led_status);
1976 igb_cleanup_led(hw);
1977
1978 return 0;
1979}
1980
1981static int igb_set_coalesce(struct net_device *netdev,
1982 struct ethtool_coalesce *ec)
1983{
1984 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 1985 int i;
9d5c8243
AK		 1986
1987 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1988 ((ec->rx_coalesce_usecs > 3) &&
1989 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1990 (ec->rx_coalesce_usecs == 2))
1991 return -EINVAL;
1992
4fc82adf
AD		 1993 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1994 ((ec->tx_coalesce_usecs > 3) &&
1995 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1996 (ec->tx_coalesce_usecs == 2))
1997 return -EINVAL;
1998
1999 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2000 return -EINVAL;
2001
9d5c8243 2002 /* convert to rate of irq's per second */
4fc82adf
AD		 2003 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2004 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2005 else
2006 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2007
2008 /* convert to rate of irq's per second */
2009 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2010 adapter->tx_itr_setting = adapter->rx_itr_setting;
2011 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2012 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2013 else
2014 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 2015
047e0030
AD		 2016 for (i = 0; i < adapter->num_q_vectors; i++) {
2017 struct igb_q_vector *q_vector = adapter->q_vector[i];
4fc82adf
AD		 2018 if (q_vector->rx_ring)
2019 q_vector->itr_val = adapter->rx_itr_setting;
2020 else
2021 q_vector->itr_val = adapter->tx_itr_setting;
2022 if (q_vector->itr_val && q_vector->itr_val <= 3)
2023 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 2024 q_vector->set_itr = 1;
2025 }
9d5c8243
AK		 2026
2027 return 0;
2028}
2029
2030static int igb_get_coalesce(struct net_device *netdev,
2031 struct ethtool_coalesce *ec)
2032{
2033 struct igb_adapter *adapter = netdev_priv(netdev);
2034
4fc82adf
AD		 2035 if (adapter->rx_itr_setting <= 3)
2036 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 2037 else
4fc82adf
AD		 2038 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2039
2040 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2041 if (adapter->tx_itr_setting <= 3)
2042 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2043 else
2044 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2045 }
9d5c8243
AK		 2046
2047 return 0;
2048}
2049
9d5c8243
AK		 2050static int igb_nway_reset(struct net_device *netdev)
2051{
2052 struct igb_adapter *adapter = netdev_priv(netdev);
2053 if (netif_running(netdev))
2054 igb_reinit_locked(adapter);
2055 return 0;
2056}
2057
2058static int igb_get_sset_count(struct net_device *netdev, int sset)
2059{
2060 switch (sset) {
2061 case ETH_SS_STATS:
2062 return IGB_STATS_LEN;
2063 case ETH_SS_TEST:
2064 return IGB_TEST_LEN;
2065 default:
2066 return -ENOTSUPP;
2067 }
2068}
2069
2070static void igb_get_ethtool_stats(struct net_device *netdev,
2071 struct ethtool_stats *stats, u64 *data)
2072{
2073 struct igb_adapter *adapter = netdev_priv(netdev);
12dcd86b
ED		 2074 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2075 unsigned int start;
2076 struct igb_ring *ring;
2077 int i, j;
128e45eb 2078 char *p;
9d5c8243 2079
12dcd86b
ED		 2080 spin_lock(&adapter->stats64_lock);
2081 igb_update_stats(adapter, net_stats);
317f66bd 2082
9d5c8243 2083 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2084 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2085 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2086 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2087 }
128e45eb
AD		 2088 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2089 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2090 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2091 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2092 }
e21ed353 2093 for (j = 0; j < adapter->num_tx_queues; j++) {
12dcd86b
ED		 2094 u64 restart2;
2095
2096 ring = adapter->tx_ring[j];
2097 do {
2098 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2099 data[i] = ring->tx_stats.packets;
2100 data[i+1] = ring->tx_stats.bytes;
2101 data[i+2] = ring->tx_stats.restart_queue;
2102 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2103 do {
2104 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2105 restart2 = ring->tx_stats.restart_queue2;
2106 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2107 data[i+2] += restart2;
2108
2109 i += IGB_TX_QUEUE_STATS_LEN;
e21ed353 2110 }
9d5c8243 2111 for (j = 0; j < adapter->num_rx_queues; j++) {
12dcd86b
ED		 2112 ring = adapter->rx_ring[j];
2113 do {
2114 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2115 data[i] = ring->rx_stats.packets;
2116 data[i+1] = ring->rx_stats.bytes;
2117 data[i+2] = ring->rx_stats.drops;
2118 data[i+3] = ring->rx_stats.csum_err;
2119 data[i+4] = ring->rx_stats.alloc_failed;
2120 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2121 i += IGB_RX_QUEUE_STATS_LEN;
9d5c8243 2122 }
12dcd86b 2123 spin_unlock(&adapter->stats64_lock);
9d5c8243
AK		 2124}
2125
2126static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2127{
2128 struct igb_adapter *adapter = netdev_priv(netdev);
2129 u8 *p = data;
2130 int i;
2131
2132 switch (stringset) {
2133 case ETH_SS_TEST:
2134 memcpy(data, *igb_gstrings_test,
2135 IGB_TEST_LEN*ETH_GSTRING_LEN);
2136 break;
2137 case ETH_SS_STATS:
2138 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2139 memcpy(p, igb_gstrings_stats[i].stat_string,
2140 ETH_GSTRING_LEN);
2141 p += ETH_GSTRING_LEN;
2142 }
128e45eb
AD		 2143 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2144 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2145 ETH_GSTRING_LEN);
2146 p += ETH_GSTRING_LEN;
2147 }
9d5c8243
AK		 2148 for (i = 0; i < adapter->num_tx_queues; i++) {
2149 sprintf(p, "tx_queue_%u_packets", i);
2150 p += ETH_GSTRING_LEN;
2151 sprintf(p, "tx_queue_%u_bytes", i);
2152 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2153 sprintf(p, "tx_queue_%u_restart", i);
2154 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2155 }
2156 for (i = 0; i < adapter->num_rx_queues; i++) {
2157 sprintf(p, "rx_queue_%u_packets", i);
2158 p += ETH_GSTRING_LEN;
2159 sprintf(p, "rx_queue_%u_bytes", i);
2160 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2161 sprintf(p, "rx_queue_%u_drops", i);
2162 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2163 sprintf(p, "rx_queue_%u_csum_err", i);
2164 p += ETH_GSTRING_LEN;
2165 sprintf(p, "rx_queue_%u_alloc_failed", i);
2166 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2167 }
2168/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2169 break;
2170 }
2171}
2172
0fc0b732 2173static const struct ethtool_ops igb_ethtool_ops = {
9d5c8243
AK		 2174 .get_settings = igb_get_settings,
2175 .set_settings = igb_set_settings,
2176 .get_drvinfo = igb_get_drvinfo,
2177 .get_regs_len = igb_get_regs_len,
2178 .get_regs = igb_get_regs,
2179 .get_wol = igb_get_wol,
2180 .set_wol = igb_set_wol,
2181 .get_msglevel = igb_get_msglevel,
2182 .set_msglevel = igb_set_msglevel,
2183 .nway_reset = igb_nway_reset,
3145535a 2184 .get_link = igb_get_link,
9d5c8243
AK		 2185 .get_eeprom_len = igb_get_eeprom_len,
2186 .get_eeprom = igb_get_eeprom,
2187 .set_eeprom = igb_set_eeprom,
2188 .get_ringparam = igb_get_ringparam,
2189 .set_ringparam = igb_set_ringparam,
2190 .get_pauseparam = igb_get_pauseparam,
2191 .set_pauseparam = igb_set_pauseparam,
2192 .get_rx_csum = igb_get_rx_csum,
2193 .set_rx_csum = igb_set_rx_csum,
2194 .get_tx_csum = igb_get_tx_csum,
2195 .set_tx_csum = igb_set_tx_csum,
2196 .get_sg = ethtool_op_get_sg,
2197 .set_sg = ethtool_op_set_sg,
2198 .get_tso = ethtool_op_get_tso,
2199 .set_tso = igb_set_tso,
2200 .self_test = igb_diag_test,
2201 .get_strings = igb_get_strings,
2202 .phys_id = igb_phys_id,
2203 .get_sset_count = igb_get_sset_count,
2204 .get_ethtool_stats = igb_get_ethtool_stats,
2205 .get_coalesce = igb_get_coalesce,
2206 .set_coalesce = igb_set_coalesce,
2207};
2208
2209void igb_set_ethtool_ops(struct net_device *netdev)
2210{
2211 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2212}
Clone of davem's net-next-2.6 tree