[net-next-2.6.git] / drivers / net / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
                                           (hw->mac.type > e1000_82575 ? 8 : 4))
#define IGB_ABS_MAX_TX_QUEUES              8
#define IGB_MAX_TX_QUEUES                  IGB_MAX_RX_QUEUES

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	u32 flags;
	unsigned long last_nack;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
};

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                     8
#define IGB_RX_HTHRESH                     8
#define IGB_RX_WTHRESH                     1
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
                                             adapter->msix_entries) ? 1 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_64    64     /* Used for packet split */
#define IGB_RXBUFFER_128   128    /* Used for packet split */
#define IGB_RXBUFFER_1024  1024
#define IGB_RXBUFFER_2048  2048
#define IGB_RXBUFFER_16384 16384

#define MAX_STD_JUMBO_FRAME_SIZE 9234

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u16 length;
			u16 next_to_watch;
			unsigned int bytecount;
			u16 gso_segs;
			u8 tx_flags;
			u8 mapped_as_page;
		};
		/* RX */
		struct {
			struct page *page;
			dma_addr_t page_dma;
			u16 page_offset;
		};
	};
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 restart_queue2;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_q_vector {
	struct igb_adapter *adapter; /* backlink */
	struct igb_ring *rx_ring;
	struct igb_ring *tx_ring;
	struct napi_struct napi;

	u32 eims_value;
	u16 cpu;

	u16 itr_val;
	u8 set_itr;
	void __iomem *itr_register;

	char name[IFNAMSIZ + 9];
};

struct igb_ring {
	struct igb_q_vector *q_vector; /* backlink to q_vector */
	struct net_device *netdev;     /* back pointer to net_device */
	struct device *dev;            /* device pointer for dma mapping */
	dma_addr_t dma;                /* phys address of the ring */
	void *desc;                    /* descriptor ring memory */
	unsigned int size;             /* length of desc. ring in bytes */
	u16 count;                     /* number of desc. in the ring */
	u16 next_to_use;
	u16 next_to_clean;
	u8 queue_index;
	u8 reg_idx;
	void __iomem *head;
	void __iomem *tail;
	struct igb_buffer *buffer_info; /* array of buffer info structs */

	unsigned int total_bytes;
	unsigned int total_packets;

	u32 flags;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			struct u64_stats_sync tx_syncp;
			struct u64_stats_sync tx_syncp2;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			struct u64_stats_sync rx_syncp;
			u32 rx_buffer_len;
		};
	};
};

#define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
#define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */

#define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */

#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)

#define E1000_RX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
#define E1000_TX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
#define E1000_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))

/* igb_desc_unused - calculate if we have unused descriptors */
static inline int igb_desc_unused(struct igb_ring *ring)
{
	if (ring->next_to_clean > ring->next_to_use)
		return ring->next_to_clean - ring->next_to_use - 1;

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
}

/* board specific private data structure */
struct igb_adapter {
	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;
	struct vlan_group *vlgrp;
	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* TX */
	struct igb_ring *tx_ring[16];
	u32 tx_timeout_count;

	/* RX */
	struct igb_ring *rx_ring[16];
	int num_tx_queues;
	int num_rx_queues;

	u32 max_frame_size;
	u32 min_frame_size;

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	spinlock_t stats64_lock;
	struct rtnl_link_stats64 stats64;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	unsigned int num_q_vectors;
	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	struct msix_entry *msix_entries;
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	unsigned long state;
	unsigned int flags;
	u32 eeprom_wol;

	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
	u16 tx_ring_count;
	u16 rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
	u32 rss_queues;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_QUEUE_PAIRS       (1 << 3)

#define IGB_82576_TSYNC_SHIFT 19
#define IGB_82580_TSYNC_SHIFT 24
#define IGB_TS_HDR_LEN        16
enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u16);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_setup_tctl(struct igb_adapter *);
extern void igb_setup_rctl(struct igb_adapter *);
extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
					   struct igb_buffer *);
extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
extern bool igb_has_link(struct igb_adapter *adapter);
extern void igb_set_ethtool_ops(struct net_device *);
extern void igb_power_up_link(struct igb_adapter *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
86d5d38f	4	Copyright(c) 2007-2009 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
38c845c7	40
9d5c8243 AK	41	struct igb_adapter;
9d5c8243 AK	42
6eb5a7f1 AD	43	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	44	#define IGB_START_ITR 648
9d5c8243	45
9d5c8243 AK	46	/* TX/RX descriptor defines */
	47	#define IGB_DEFAULT_TXD 256
	48	#define IGB_MIN_TXD 80
	49	#define IGB_MAX_TXD 4096
	50
	51	#define IGB_DEFAULT_RXD 256
	52	#define IGB_MIN_RXD 80
	53	#define IGB_MAX_RXD 4096
	54
	55	#define IGB_DEFAULT_ITR 3 /* dynamic */
	56	#define IGB_MAX_ITR_USECS 10000
	57	#define IGB_MIN_ITR_USECS 10
047e0030 AD	58	#define NON_Q_VECTORS 1
047e0030 AD	59	#define MAX_Q_VECTORS 8
9d5c8243 AK	60
9d5c8243 AK	61	/* Transmit and receive queues */
a99955fc AD	62	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
	63	(hw->mac.type > e1000_82575 ? 8 : 4))
	64	#define IGB_ABS_MAX_TX_QUEUES 8
	65	#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
9d5c8243	66
4ae196df AD	67	#define IGB_MAX_VF_MC_ENTRIES 30
	68	#define IGB_MAX_VF_FUNCTIONS 8
	69	#define IGB_MAX_VFTA_ENTRIES 128
	70
	71	struct vf_data_storage {
	72	unsigned char vf_mac_addresses[ETH_ALEN];
	73	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	74	u16 num_vf_mc_hashes;
ae641bdc	75	u16 vlans_enabled;
f2ca0dbe AD	76	u32 flags;
f2ca0dbe AD	77	unsigned long last_nack;
8151d294 WM	78	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
8151d294 WM	79	u16 pf_qos;
4ae196df AD	80	};
4ae196df AD	81
f2ca0dbe	82	#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
7d5753f0 AD	83	#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
7d5753f0 AD	84	#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
8151d294	85	#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
f2ca0dbe	86
9d5c8243 AK	87	/* RX descriptor control thresholds.
	88	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	89	* descriptors available in its onboard memory.
	90	* Setting this to 0 disables RX descriptor prefetch.
	91	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	92	* available in host memory.
	93	* If PTHRESH is 0, this should also be 0.
	94	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	95	* descriptors until either it has this many to write back, or the
	96	* ITR timer expires.
	97	*/
58fd62f5	98	#define IGB_RX_PTHRESH 8
9d5c8243 AK	99	#define IGB_RX_HTHRESH 8
9d5c8243 AK	100	#define IGB_RX_WTHRESH 1
85b430b4 AD	101	#define IGB_TX_PTHRESH 8
	102	#define IGB_TX_HTHRESH 1
	103	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
58fd62f5	104	adapter->msix_entries) ? 1 : 16)
9d5c8243 AK	105
	106	/* this is the size past which hardware will drop packets when setting LPE=0 */
	107	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	108
	109	/* Supported Rx Buffer Sizes */
757b77e2	110	#define IGB_RXBUFFER_64 64 /* Used for packet split */
9d5c8243	111	#define IGB_RXBUFFER_128 128 /* Used for packet split */
9d5c8243 AK	112	#define IGB_RXBUFFER_1024 1024
9d5c8243 AK	113	#define IGB_RXBUFFER_2048 2048
9d5c8243 AK	114	#define IGB_RXBUFFER_16384 16384
9d5c8243 AK	115
e1739522	116	#define MAX_STD_JUMBO_FRAME_SIZE 9234
9d5c8243 AK	117
	118	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	119	#define IGB_TX_QUEUE_WAKE 16
	120	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	121	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	122
	123	#define AUTO_ALL_MODES 0
	124	#define IGB_EEPROM_APME 0x0400
	125
	126	#ifndef IGB_MASTER_SLAVE
	127	/* Switch to override PHY master/slave setting */
	128	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	129	#endif
	130
	131	#define IGB_MNG_VLAN_NONE -1
	132
	133	/* wrapper around a pointer to a socket buffer,
	134	* so a DMA handle can be stored along with the buffer */
	135	struct igb_buffer {
	136	struct sk_buff *skb;
	137	dma_addr_t dma;
	138	union {
	139	/* TX */
	140	struct {
	141	unsigned long time_stamp;
0e014cb1 AD	142	u16 length;
0e014cb1 AD	143	u16 next_to_watch;
2873957d	144	unsigned int bytecount;
40e90c26	145	u16 gso_segs;
2244d07b	146	u8 tx_flags;
2873957d	147	u8 mapped_as_page;
9d5c8243 AK	148	};
	149	/* RX */
	150	struct {
	151	struct page *page;
6366ad33 AD	152	dma_addr_t page_dma;
6366ad33 AD	153	u16 page_offset;
9d5c8243 AK	154	};
	155	};
	156	};
	157
8c0ab70a	158	struct igb_tx_queue_stats {
9d5c8243 AK	159	u64 packets;
9d5c8243 AK	160	u64 bytes;
04a5fcaa	161	u64 restart_queue;
12dcd86b	162	u64 restart_queue2;
9d5c8243 AK	163	};
9d5c8243 AK	164
8c0ab70a JDB	165	struct igb_rx_queue_stats {
	166	u64 packets;
	167	u64 bytes;
	168	u64 drops;
04a5fcaa AD	169	u64 csum_err;
04a5fcaa AD	170	u64 alloc_failed;
8c0ab70a JDB	171	};
8c0ab70a JDB	172
047e0030	173	struct igb_q_vector {
9d5c8243	174	struct igb_adapter adapter; / backlink */
047e0030 AD	175	struct igb_ring *rx_ring;
	176	struct igb_ring *tx_ring;
	177	struct napi_struct napi;
	178
	179	u32 eims_value;
	180	u16 cpu;
	181
	182	u16 itr_val;
	183	u8 set_itr;
047e0030 AD	184	void __iomem *itr_register;
	185
	186	char name[IFNAMSIZ + 9];
	187	};
	188
	189	struct igb_ring {
	190	struct igb_q_vector q_vector; / backlink to q_vector */
e694e964	191	struct net_device netdev; / back pointer to net_device */
59d71989	192	struct device dev; / device pointer for dma mapping */
047e0030	193	dma_addr_t dma; /* phys address of the ring */
e694e964	194	void desc; / descriptor ring memory */
047e0030	195	unsigned int size; /* length of desc. ring in bytes */
2e5655e7	196	u16 count; /* number of desc. in the ring */
9d5c8243 AK	197	u16 next_to_use;
9d5c8243 AK	198	u16 next_to_clean;
2e5655e7 AD	199	u8 queue_index;
2e5655e7 AD	200	u8 reg_idx;
fce99e34 AD	201	void __iomem *head;
fce99e34 AD	202	void __iomem *tail;
9d5c8243 AK	203	struct igb_buffer buffer_info; / array of buffer info structs */
9d5c8243 AK	204
9d5c8243 AK	205	unsigned int total_bytes;
	206	unsigned int total_packets;
	207
85ad76b2 AD	208	u32 flags;
85ad76b2 AD	209
9d5c8243 AK	210	union {
	211	/* TX */
	212	struct {
8c0ab70a	213	struct igb_tx_queue_stats tx_stats;
12dcd86b ED	214	struct u64_stats_sync tx_syncp;
12dcd86b ED	215	struct u64_stats_sync tx_syncp2;
9d5c8243 AK	216	bool detect_tx_hung;
	217	};
	218	/* RX */
	219	struct {
8c0ab70a	220	struct igb_rx_queue_stats rx_stats;
12dcd86b	221	struct u64_stats_sync rx_syncp;
4c844851	222	u32 rx_buffer_len;
9d5c8243 AK	223	};
9d5c8243 AK	224	};
9d5c8243 AK	225	};
9d5c8243 AK	226
85ad76b2 AD	227	#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
	228	#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
	229
	230	#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
	231
	232	#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP \| E1000_TXD_CMD_RS)
	233
9d5c8243 AK	234	#define E1000_RX_DESC_ADV(R, i) \
	235	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
	236	#define E1000_TX_DESC_ADV(R, i) \
	237	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
	238	#define E1000_TX_CTXTDESC_ADV(R, i) \
	239	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
9d5c8243	240
d7ee5b3a AD	241	/* igb_desc_unused - calculate if we have unused descriptors */
	242	static inline int igb_desc_unused(struct igb_ring *ring)
	243	{
	244	if (ring->next_to_clean > ring->next_to_use)
	245	return ring->next_to_clean - ring->next_to_use - 1;
	246
	247	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
	248	}
	249
9d5c8243	250	/* board specific private data structure */
9d5c8243 AK	251	struct igb_adapter {
	252	struct timer_list watchdog_timer;
	253	struct timer_list phy_info_timer;
	254	struct vlan_group *vlgrp;
	255	u16 mng_vlan_id;
	256	u32 bd_number;
9d5c8243 AK	257	u32 wol;
	258	u32 en_mng_pt;
	259	u16 link_speed;
	260	u16 link_duplex;
2e5655e7	261
9d5c8243	262	/* Interrupt Throttle Rate */
4fc82adf AD	263	u32 rx_itr_setting;
4fc82adf AD	264	u32 tx_itr_setting;
9d5c8243 AK	265	u16 tx_itr;
9d5c8243 AK	266	u16 rx_itr;
9d5c8243 AK	267
	268	struct work_struct reset_task;
	269	struct work_struct watchdog_task;
	270	bool fc_autoneg;
	271	u8 tx_timeout_factor;
	272	struct timer_list blink_timer;
	273	unsigned long led_status;
	274
	275	/* TX */
3025a446	276	struct igb_ring *tx_ring[16];
9d5c8243 AK	277	u32 tx_timeout_count;
	278
	279	/* RX */
3025a446	280	struct igb_ring *rx_ring[16];
9d5c8243 AK	281	int num_tx_queues;
	282	int num_rx_queues;
	283
9d5c8243 AK	284	u32 max_frame_size;
	285	u32 min_frame_size;
	286
	287	/* OS defined structs */
	288	struct net_device *netdev;
9d5c8243	289	struct pci_dev *pdev;
38c845c7 PO	290	struct cyclecounter cycles;
38c845c7 PO	291	struct timecounter clock;
33af6bcc PO	292	struct timecompare compare;
33af6bcc PO	293	struct hwtstamp_config hwtstamp_config;
9d5c8243	294
12dcd86b ED	295	spinlock_t stats64_lock;
	296	struct rtnl_link_stats64 stats64;
	297
9d5c8243 AK	298	/* structs defined in e1000_hw.h */
	299	struct e1000_hw hw;
	300	struct e1000_hw_stats stats;
	301	struct e1000_phy_info phy_info;
	302	struct e1000_phy_stats phy_stats;
	303
	304	u32 test_icr;
	305	struct igb_ring test_tx_ring;
	306	struct igb_ring test_rx_ring;
	307
	308	int msg_enable;
047e0030 AD	309
	310	unsigned int num_q_vectors;
	311	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243 AK	312	struct msix_entry *msix_entries;
9d5c8243 AK	313	u32 eims_enable_mask;
844290e5	314	u32 eims_other;
9d5c8243 AK	315
	316	/* to not mess up cache alignment, always add to the bottom */
	317	unsigned long state;
7dfc16fa	318	unsigned int flags;
9d5c8243	319	u32 eeprom_wol;
42bfd33a	320
1bfaf07b	321	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
2e5655e7 AD	322	u16 tx_ring_count;
2e5655e7 AD	323	u16 rx_ring_count;
1bfaf07b	324	unsigned int vfs_allocated_count;
4ae196df	325	struct vf_data_storage *vf_data;
a99955fc	326	u32 rss_queues;
9d5c8243 AK	327	};
9d5c8243 AK	328
7dfc16fa	329	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	330	#define IGB_FLAG_DCA_ENABLED (1 << 1)
cbd347ad AD	331	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
4fc82adf	332	#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
7dfc16fa	333
c5b9bd5e	334	#define IGB_82576_TSYNC_SHIFT 19
55cac248	335	#define IGB_82580_TSYNC_SHIFT 24
757b77e2	336	#define IGB_TS_HDR_LEN 16
9d5c8243 AK	337	enum e1000_state_t {
	338	__IGB_TESTING,
	339	__IGB_RESETTING,
	340	__IGB_DOWN
	341	};
	342
	343	enum igb_boards {
	344	board_82575,
	345	};
	346
	347	extern char igb_driver_name[];
	348	extern char igb_driver_version[];
	349
9d5c8243 AK	350	extern int igb_up(struct igb_adapter *);
	351	extern void igb_down(struct igb_adapter *);
	352	extern void igb_reinit_locked(struct igb_adapter *);
	353	extern void igb_reset(struct igb_adapter *);
	354	extern int igb_set_spd_dplx(struct igb_adapter *, u16);
80785298 AD	355	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	356	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	357	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	358	extern void igb_free_rx_resources(struct igb_ring *);
d7ee5b3a AD	359	extern void igb_configure_tx_ring(struct igb_adapter , struct igb_ring );
	360	extern void igb_configure_rx_ring(struct igb_adapter , struct igb_ring );
	361	extern void igb_setup_tctl(struct igb_adapter *);
	362	extern void igb_setup_rctl(struct igb_adapter *);
b1a436c3 AD	363	extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff , struct igb_ring );
	364	extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
	365	struct igb_buffer *);
d7ee5b3a	366	extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
12dcd86b	367	extern void igb_update_stats(struct igb_adapter , struct rtnl_link_stats64 );
3145535a	368	extern bool igb_has_link(struct igb_adapter *adapter);
9d5c8243	369	extern void igb_set_ethtool_ops(struct net_device *);
88a268c1	370	extern void igb_power_up_link(struct igb_adapter *);
9d5c8243	371
f5f4cf08 AD	372	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	373	{
a8d2a0c2 AD	374	if (hw->phy.ops.reset)
a8d2a0c2 AD	375	return hw->phy.ops.reset(hw);
f5f4cf08 AD	376
	377	return 0;
	378	}
	379
	380	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	381	{
a8d2a0c2 AD	382	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	383	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	384
	385	return 0;
	386	}
	387
	388	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	389	{
a8d2a0c2 AD	390	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	391	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	392
	393	return 0;
	394	}
	395
	396	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	397	{
	398	if (hw->phy.ops.get_phy_info)
	399	return hw->phy.ops.get_phy_info(hw);
	400
	401	return 0;
	402	}
	403
9d5c8243	404	#endif /* _IGB_H_ */