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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* e1000_82575 | |
29 | * e1000_82576 | |
30 | */ | |
31 | ||
32 | #include <linux/types.h> | |
2d064c06 | 33 | #include <linux/if_ether.h> |
9d5c8243 AK |
34 | |
35 | #include "e1000_mac.h" | |
36 | #include "e1000_82575.h" | |
37 | ||
38 | static s32 igb_get_invariants_82575(struct e1000_hw *); | |
39 | static s32 igb_acquire_phy_82575(struct e1000_hw *); | |
40 | static void igb_release_phy_82575(struct e1000_hw *); | |
41 | static s32 igb_acquire_nvm_82575(struct e1000_hw *); | |
42 | static void igb_release_nvm_82575(struct e1000_hw *); | |
43 | static s32 igb_check_for_link_82575(struct e1000_hw *); | |
44 | static s32 igb_get_cfg_done_82575(struct e1000_hw *); | |
45 | static s32 igb_init_hw_82575(struct e1000_hw *); | |
46 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); | |
47 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); | |
bb2ac47b AD |
48 | static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); |
49 | static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); | |
9d5c8243 | 50 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
bb2ac47b | 51 | static s32 igb_reset_hw_82580(struct e1000_hw *); |
9d5c8243 AK |
52 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
53 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); | |
2fb02a26 | 54 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *); |
9d5c8243 AK |
55 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); |
56 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); | |
57 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); | |
9d5c8243 AK |
58 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
59 | u16 *); | |
60 | static s32 igb_get_phy_id_82575(struct e1000_hw *); | |
61 | static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); | |
62 | static bool igb_sgmii_active_82575(struct e1000_hw *); | |
63 | static s32 igb_reset_init_script_82575(struct e1000_hw *); | |
64 | static s32 igb_read_mac_addr_82575(struct e1000_hw *); | |
009bc06e | 65 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); |
99870a73 | 66 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); |
9d5c8243 | 67 | |
bb2ac47b AD |
68 | static const u16 e1000_82580_rxpbs_table[] = |
69 | { 36, 72, 144, 1, 2, 4, 8, 16, | |
70 | 35, 70, 140 }; | |
71 | #define E1000_82580_RXPBS_TABLE_SIZE \ | |
72 | (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) | |
73 | ||
4085f746 NN |
74 | /** |
75 | * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO | |
76 | * @hw: pointer to the HW structure | |
77 | * | |
78 | * Called to determine if the I2C pins are being used for I2C or as an | |
79 | * external MDIO interface since the two options are mutually exclusive. | |
80 | **/ | |
81 | static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) | |
82 | { | |
83 | u32 reg = 0; | |
84 | bool ext_mdio = false; | |
85 | ||
86 | switch (hw->mac.type) { | |
87 | case e1000_82575: | |
88 | case e1000_82576: | |
89 | reg = rd32(E1000_MDIC); | |
90 | ext_mdio = !!(reg & E1000_MDIC_DEST); | |
91 | break; | |
92 | case e1000_82580: | |
93 | case e1000_i350: | |
94 | reg = rd32(E1000_MDICNFG); | |
95 | ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); | |
96 | break; | |
97 | default: | |
98 | break; | |
99 | } | |
100 | return ext_mdio; | |
101 | } | |
102 | ||
9d5c8243 AK |
103 | static s32 igb_get_invariants_82575(struct e1000_hw *hw) |
104 | { | |
105 | struct e1000_phy_info *phy = &hw->phy; | |
106 | struct e1000_nvm_info *nvm = &hw->nvm; | |
107 | struct e1000_mac_info *mac = &hw->mac; | |
c1889bfe | 108 | struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; |
9d5c8243 AK |
109 | u32 eecd; |
110 | s32 ret_val; | |
111 | u16 size; | |
112 | u32 ctrl_ext = 0; | |
113 | ||
114 | switch (hw->device_id) { | |
115 | case E1000_DEV_ID_82575EB_COPPER: | |
116 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
117 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
118 | mac->type = e1000_82575; | |
119 | break; | |
2d064c06 | 120 | case E1000_DEV_ID_82576: |
9eb2341d | 121 | case E1000_DEV_ID_82576_NS: |
747d49ba | 122 | case E1000_DEV_ID_82576_NS_SERDES: |
2d064c06 AD |
123 | case E1000_DEV_ID_82576_FIBER: |
124 | case E1000_DEV_ID_82576_SERDES: | |
c8ea5ea9 | 125 | case E1000_DEV_ID_82576_QUAD_COPPER: |
b894fa26 | 126 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
4703bf73 | 127 | case E1000_DEV_ID_82576_SERDES_QUAD: |
2d064c06 AD |
128 | mac->type = e1000_82576; |
129 | break; | |
bb2ac47b AD |
130 | case E1000_DEV_ID_82580_COPPER: |
131 | case E1000_DEV_ID_82580_FIBER: | |
132 | case E1000_DEV_ID_82580_SERDES: | |
133 | case E1000_DEV_ID_82580_SGMII: | |
134 | case E1000_DEV_ID_82580_COPPER_DUAL: | |
308fb39a JG |
135 | case E1000_DEV_ID_DH89XXCC_SGMII: |
136 | case E1000_DEV_ID_DH89XXCC_SERDES: | |
bb2ac47b AD |
137 | mac->type = e1000_82580; |
138 | break; | |
d2ba2ed8 AD |
139 | case E1000_DEV_ID_I350_COPPER: |
140 | case E1000_DEV_ID_I350_FIBER: | |
141 | case E1000_DEV_ID_I350_SERDES: | |
142 | case E1000_DEV_ID_I350_SGMII: | |
143 | mac->type = e1000_i350; | |
144 | break; | |
9d5c8243 AK |
145 | default: |
146 | return -E1000_ERR_MAC_INIT; | |
147 | break; | |
148 | } | |
149 | ||
9d5c8243 AK |
150 | /* Set media type */ |
151 | /* | |
152 | * The 82575 uses bits 22:23 for link mode. The mode can be changed | |
153 | * based on the EEPROM. We cannot rely upon device ID. There | |
154 | * is no distinguishable difference between fiber and internal | |
155 | * SerDes mode on the 82575. There can be an external PHY attached | |
156 | * on the SGMII interface. For this, we'll set sgmii_active to true. | |
157 | */ | |
158 | phy->media_type = e1000_media_type_copper; | |
159 | dev_spec->sgmii_active = false; | |
160 | ||
161 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
2fb02a26 AD |
162 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
163 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
9d5c8243 | 164 | dev_spec->sgmii_active = true; |
2fb02a26 | 165 | break; |
bb2ac47b | 166 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: |
2fb02a26 AD |
167 | case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: |
168 | hw->phy.media_type = e1000_media_type_internal_serdes; | |
2fb02a26 AD |
169 | break; |
170 | default: | |
2fb02a26 | 171 | break; |
9d5c8243 | 172 | } |
2fb02a26 | 173 | |
9d5c8243 AK |
174 | /* Set mta register count */ |
175 | mac->mta_reg_count = 128; | |
176 | /* Set rar entry count */ | |
177 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; | |
2d064c06 AD |
178 | if (mac->type == e1000_82576) |
179 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; | |
bb2ac47b AD |
180 | if (mac->type == e1000_82580) |
181 | mac->rar_entry_count = E1000_RAR_ENTRIES_82580; | |
d2ba2ed8 AD |
182 | if (mac->type == e1000_i350) |
183 | mac->rar_entry_count = E1000_RAR_ENTRIES_I350; | |
bb2ac47b | 184 | /* reset */ |
d2ba2ed8 | 185 | if (mac->type >= e1000_82580) |
bb2ac47b AD |
186 | mac->ops.reset_hw = igb_reset_hw_82580; |
187 | else | |
188 | mac->ops.reset_hw = igb_reset_hw_82575; | |
9d5c8243 AK |
189 | /* Set if part includes ASF firmware */ |
190 | mac->asf_firmware_present = true; | |
191 | /* Set if manageability features are enabled. */ | |
192 | mac->arc_subsystem_valid = | |
193 | (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) | |
194 | ? true : false; | |
195 | ||
196 | /* physical interface link setup */ | |
197 | mac->ops.setup_physical_interface = | |
198 | (hw->phy.media_type == e1000_media_type_copper) | |
199 | ? igb_setup_copper_link_82575 | |
2fb02a26 | 200 | : igb_setup_serdes_link_82575; |
9d5c8243 AK |
201 | |
202 | /* NVM initialization */ | |
203 | eecd = rd32(E1000_EECD); | |
204 | ||
205 | nvm->opcode_bits = 8; | |
206 | nvm->delay_usec = 1; | |
207 | switch (nvm->override) { | |
208 | case e1000_nvm_override_spi_large: | |
209 | nvm->page_size = 32; | |
210 | nvm->address_bits = 16; | |
211 | break; | |
212 | case e1000_nvm_override_spi_small: | |
213 | nvm->page_size = 8; | |
214 | nvm->address_bits = 8; | |
215 | break; | |
216 | default: | |
217 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
218 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
219 | break; | |
220 | } | |
221 | ||
222 | nvm->type = e1000_nvm_eeprom_spi; | |
223 | ||
224 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
225 | E1000_EECD_SIZE_EX_SHIFT); | |
226 | ||
227 | /* | |
228 | * Added to a constant, "size" becomes the left-shift value | |
229 | * for setting word_size. | |
230 | */ | |
231 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
5c3cad75 JK |
232 | |
233 | /* EEPROM access above 16k is unsupported */ | |
234 | if (size > 14) | |
235 | size = 14; | |
9d5c8243 AK |
236 | nvm->word_size = 1 << size; |
237 | ||
a0c98605 AD |
238 | /* if 82576 then initialize mailbox parameters */ |
239 | if (mac->type == e1000_82576) | |
240 | igb_init_mbx_params_pf(hw); | |
241 | ||
9d5c8243 AK |
242 | /* setup PHY parameters */ |
243 | if (phy->media_type != e1000_media_type_copper) { | |
244 | phy->type = e1000_phy_none; | |
245 | return 0; | |
246 | } | |
247 | ||
248 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
249 | phy->reset_delay_us = 100; | |
250 | ||
99870a73 AD |
251 | ctrl_ext = rd32(E1000_CTRL_EXT); |
252 | ||
9d5c8243 | 253 | /* PHY function pointers */ |
99870a73 | 254 | if (igb_sgmii_active_82575(hw)) { |
4085f746 | 255 | phy->ops.reset = igb_phy_hw_reset_sgmii_82575; |
99870a73 AD |
256 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
257 | } else { | |
4085f746 | 258 | phy->ops.reset = igb_phy_hw_reset; |
99870a73 AD |
259 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; |
260 | } | |
261 | ||
262 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
263 | igb_reset_mdicnfg_82580(hw); | |
4085f746 NN |
264 | |
265 | if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { | |
266 | phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; | |
267 | phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; | |
d2ba2ed8 | 268 | } else if (hw->mac.type >= e1000_82580) { |
4085f746 NN |
269 | phy->ops.read_reg = igb_read_phy_reg_82580; |
270 | phy->ops.write_reg = igb_write_phy_reg_82580; | |
9d5c8243 | 271 | } else { |
4085f746 NN |
272 | phy->ops.read_reg = igb_read_phy_reg_igp; |
273 | phy->ops.write_reg = igb_write_phy_reg_igp; | |
9d5c8243 AK |
274 | } |
275 | ||
19e588e7 AD |
276 | /* set lan id */ |
277 | hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> | |
278 | E1000_STATUS_FUNC_SHIFT; | |
279 | ||
9d5c8243 AK |
280 | /* Set phy->phy_addr and phy->id. */ |
281 | ret_val = igb_get_phy_id_82575(hw); | |
282 | if (ret_val) | |
283 | return ret_val; | |
284 | ||
285 | /* Verify phy id and set remaining function pointers */ | |
286 | switch (phy->id) { | |
308fb39a JG |
287 | case I347AT4_E_PHY_ID: |
288 | case M88E1112_E_PHY_ID: | |
9d5c8243 AK |
289 | case M88E1111_I_PHY_ID: |
290 | phy->type = e1000_phy_m88; | |
291 | phy->ops.get_phy_info = igb_get_phy_info_m88; | |
308fb39a JG |
292 | |
293 | if (phy->id == I347AT4_E_PHY_ID || | |
294 | phy->id == M88E1112_E_PHY_ID) | |
295 | phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; | |
296 | else | |
297 | phy->ops.get_cable_length = igb_get_cable_length_m88; | |
298 | ||
9d5c8243 AK |
299 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; |
300 | break; | |
301 | case IGP03E1000_E_PHY_ID: | |
302 | phy->type = e1000_phy_igp_3; | |
303 | phy->ops.get_phy_info = igb_get_phy_info_igp; | |
304 | phy->ops.get_cable_length = igb_get_cable_length_igp_2; | |
305 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; | |
306 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; | |
307 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; | |
308 | break; | |
bb2ac47b | 309 | case I82580_I_PHY_ID: |
d2ba2ed8 | 310 | case I350_I_PHY_ID: |
bb2ac47b AD |
311 | phy->type = e1000_phy_82580; |
312 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580; | |
313 | phy->ops.get_cable_length = igb_get_cable_length_82580; | |
314 | phy->ops.get_phy_info = igb_get_phy_info_82580; | |
315 | break; | |
9d5c8243 AK |
316 | default: |
317 | return -E1000_ERR_PHY; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | /** | |
733596be | 324 | * igb_acquire_phy_82575 - Acquire rights to access PHY |
9d5c8243 AK |
325 | * @hw: pointer to the HW structure |
326 | * | |
327 | * Acquire access rights to the correct PHY. This is a | |
328 | * function pointer entry point called by the api module. | |
329 | **/ | |
330 | static s32 igb_acquire_phy_82575(struct e1000_hw *hw) | |
331 | { | |
008c3422 | 332 | u16 mask = E1000_SWFW_PHY0_SM; |
9d5c8243 | 333 | |
008c3422 AD |
334 | if (hw->bus.func == E1000_FUNC_1) |
335 | mask = E1000_SWFW_PHY1_SM; | |
ede3ef0d NN |
336 | else if (hw->bus.func == E1000_FUNC_2) |
337 | mask = E1000_SWFW_PHY2_SM; | |
338 | else if (hw->bus.func == E1000_FUNC_3) | |
339 | mask = E1000_SWFW_PHY3_SM; | |
9d5c8243 AK |
340 | |
341 | return igb_acquire_swfw_sync_82575(hw, mask); | |
342 | } | |
343 | ||
344 | /** | |
733596be | 345 | * igb_release_phy_82575 - Release rights to access PHY |
9d5c8243 AK |
346 | * @hw: pointer to the HW structure |
347 | * | |
348 | * A wrapper to release access rights to the correct PHY. This is a | |
349 | * function pointer entry point called by the api module. | |
350 | **/ | |
351 | static void igb_release_phy_82575(struct e1000_hw *hw) | |
352 | { | |
008c3422 AD |
353 | u16 mask = E1000_SWFW_PHY0_SM; |
354 | ||
355 | if (hw->bus.func == E1000_FUNC_1) | |
356 | mask = E1000_SWFW_PHY1_SM; | |
ede3ef0d NN |
357 | else if (hw->bus.func == E1000_FUNC_2) |
358 | mask = E1000_SWFW_PHY2_SM; | |
359 | else if (hw->bus.func == E1000_FUNC_3) | |
360 | mask = E1000_SWFW_PHY3_SM; | |
9d5c8243 | 361 | |
9d5c8243 AK |
362 | igb_release_swfw_sync_82575(hw, mask); |
363 | } | |
364 | ||
365 | /** | |
733596be | 366 | * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii |
9d5c8243 AK |
367 | * @hw: pointer to the HW structure |
368 | * @offset: register offset to be read | |
369 | * @data: pointer to the read data | |
370 | * | |
371 | * Reads the PHY register at offset using the serial gigabit media independent | |
372 | * interface and stores the retrieved information in data. | |
373 | **/ | |
374 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
375 | u16 *data) | |
376 | { | |
bf6f7a92 | 377 | s32 ret_val = -E1000_ERR_PARAM; |
9d5c8243 AK |
378 | |
379 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 380 | hw_dbg("PHY Address %u is out of range\n", offset); |
bf6f7a92 | 381 | goto out; |
9d5c8243 AK |
382 | } |
383 | ||
bf6f7a92 AD |
384 | ret_val = hw->phy.ops.acquire(hw); |
385 | if (ret_val) | |
386 | goto out; | |
9d5c8243 | 387 | |
bf6f7a92 | 388 | ret_val = igb_read_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 389 | |
bf6f7a92 AD |
390 | hw->phy.ops.release(hw); |
391 | ||
392 | out: | |
393 | return ret_val; | |
9d5c8243 AK |
394 | } |
395 | ||
396 | /** | |
733596be | 397 | * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii |
9d5c8243 AK |
398 | * @hw: pointer to the HW structure |
399 | * @offset: register offset to write to | |
400 | * @data: data to write at register offset | |
401 | * | |
402 | * Writes the data to PHY register at the offset using the serial gigabit | |
403 | * media independent interface. | |
404 | **/ | |
405 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
406 | u16 data) | |
407 | { | |
bf6f7a92 AD |
408 | s32 ret_val = -E1000_ERR_PARAM; |
409 | ||
9d5c8243 AK |
410 | |
411 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 412 | hw_dbg("PHY Address %d is out of range\n", offset); |
bf6f7a92 | 413 | goto out; |
9d5c8243 AK |
414 | } |
415 | ||
bf6f7a92 AD |
416 | ret_val = hw->phy.ops.acquire(hw); |
417 | if (ret_val) | |
418 | goto out; | |
9d5c8243 | 419 | |
bf6f7a92 | 420 | ret_val = igb_write_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 421 | |
bf6f7a92 AD |
422 | hw->phy.ops.release(hw); |
423 | ||
424 | out: | |
425 | return ret_val; | |
9d5c8243 AK |
426 | } |
427 | ||
428 | /** | |
733596be | 429 | * igb_get_phy_id_82575 - Retrieve PHY addr and id |
9d5c8243 AK |
430 | * @hw: pointer to the HW structure |
431 | * | |
652fff32 | 432 | * Retrieves the PHY address and ID for both PHY's which do and do not use |
9d5c8243 AK |
433 | * sgmi interface. |
434 | **/ | |
435 | static s32 igb_get_phy_id_82575(struct e1000_hw *hw) | |
436 | { | |
437 | struct e1000_phy_info *phy = &hw->phy; | |
438 | s32 ret_val = 0; | |
439 | u16 phy_id; | |
2fb02a26 | 440 | u32 ctrl_ext; |
4085f746 | 441 | u32 mdic; |
9d5c8243 AK |
442 | |
443 | /* | |
444 | * For SGMII PHYs, we try the list of possible addresses until | |
445 | * we find one that works. For non-SGMII PHYs | |
446 | * (e.g. integrated copper PHYs), an address of 1 should | |
447 | * work. The result of this function should mean phy->phy_addr | |
448 | * and phy->id are set correctly. | |
449 | */ | |
450 | if (!(igb_sgmii_active_82575(hw))) { | |
451 | phy->addr = 1; | |
452 | ret_val = igb_get_phy_id(hw); | |
453 | goto out; | |
454 | } | |
455 | ||
4085f746 NN |
456 | if (igb_sgmii_uses_mdio_82575(hw)) { |
457 | switch (hw->mac.type) { | |
458 | case e1000_82575: | |
459 | case e1000_82576: | |
460 | mdic = rd32(E1000_MDIC); | |
461 | mdic &= E1000_MDIC_PHY_MASK; | |
462 | phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; | |
463 | break; | |
464 | case e1000_82580: | |
465 | case e1000_i350: | |
466 | mdic = rd32(E1000_MDICNFG); | |
467 | mdic &= E1000_MDICNFG_PHY_MASK; | |
468 | phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; | |
469 | break; | |
470 | default: | |
471 | ret_val = -E1000_ERR_PHY; | |
472 | goto out; | |
473 | break; | |
474 | } | |
475 | ret_val = igb_get_phy_id(hw); | |
476 | goto out; | |
477 | } | |
478 | ||
2fb02a26 AD |
479 | /* Power on sgmii phy if it is disabled */ |
480 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
481 | wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); | |
482 | wrfl(); | |
483 | msleep(300); | |
484 | ||
9d5c8243 AK |
485 | /* |
486 | * The address field in the I2CCMD register is 3 bits and 0 is invalid. | |
487 | * Therefore, we need to test 1-7 | |
488 | */ | |
489 | for (phy->addr = 1; phy->addr < 8; phy->addr++) { | |
490 | ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); | |
491 | if (ret_val == 0) { | |
652fff32 AK |
492 | hw_dbg("Vendor ID 0x%08X read at address %u\n", |
493 | phy_id, phy->addr); | |
9d5c8243 AK |
494 | /* |
495 | * At the time of this writing, The M88 part is | |
496 | * the only supported SGMII PHY product. | |
497 | */ | |
498 | if (phy_id == M88_VENDOR) | |
499 | break; | |
500 | } else { | |
652fff32 | 501 | hw_dbg("PHY address %u was unreadable\n", phy->addr); |
9d5c8243 AK |
502 | } |
503 | } | |
504 | ||
505 | /* A valid PHY type couldn't be found. */ | |
506 | if (phy->addr == 8) { | |
507 | phy->addr = 0; | |
508 | ret_val = -E1000_ERR_PHY; | |
509 | goto out; | |
2fb02a26 AD |
510 | } else { |
511 | ret_val = igb_get_phy_id(hw); | |
9d5c8243 AK |
512 | } |
513 | ||
2fb02a26 AD |
514 | /* restore previous sfp cage power state */ |
515 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
9d5c8243 AK |
516 | |
517 | out: | |
518 | return ret_val; | |
519 | } | |
520 | ||
521 | /** | |
733596be | 522 | * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset |
9d5c8243 AK |
523 | * @hw: pointer to the HW structure |
524 | * | |
525 | * Resets the PHY using the serial gigabit media independent interface. | |
526 | **/ | |
527 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) | |
528 | { | |
529 | s32 ret_val; | |
530 | ||
531 | /* | |
532 | * This isn't a true "hard" reset, but is the only reset | |
533 | * available to us at this time. | |
534 | */ | |
535 | ||
652fff32 | 536 | hw_dbg("Soft resetting SGMII attached PHY...\n"); |
9d5c8243 AK |
537 | |
538 | /* | |
539 | * SFP documentation requires the following to configure the SPF module | |
540 | * to work on SGMII. No further documentation is given. | |
541 | */ | |
a8d2a0c2 | 542 | ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); |
9d5c8243 AK |
543 | if (ret_val) |
544 | goto out; | |
545 | ||
546 | ret_val = igb_phy_sw_reset(hw); | |
547 | ||
548 | out: | |
549 | return ret_val; | |
550 | } | |
551 | ||
552 | /** | |
733596be | 553 | * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state |
9d5c8243 AK |
554 | * @hw: pointer to the HW structure |
555 | * @active: true to enable LPLU, false to disable | |
556 | * | |
557 | * Sets the LPLU D0 state according to the active flag. When | |
558 | * activating LPLU this function also disables smart speed | |
559 | * and vice versa. LPLU will not be activated unless the | |
560 | * device autonegotiation advertisement meets standards of | |
561 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
562 | * This is a function pointer entry point only called by | |
563 | * PHY setup routines. | |
564 | **/ | |
565 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) | |
566 | { | |
567 | struct e1000_phy_info *phy = &hw->phy; | |
568 | s32 ret_val; | |
569 | u16 data; | |
570 | ||
a8d2a0c2 | 571 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
572 | if (ret_val) |
573 | goto out; | |
574 | ||
575 | if (active) { | |
576 | data |= IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 577 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 578 | data); |
9d5c8243 AK |
579 | if (ret_val) |
580 | goto out; | |
581 | ||
582 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 583 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 584 | &data); |
9d5c8243 | 585 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
a8d2a0c2 | 586 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 587 | data); |
9d5c8243 AK |
588 | if (ret_val) |
589 | goto out; | |
590 | } else { | |
591 | data &= ~IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 592 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 593 | data); |
9d5c8243 AK |
594 | /* |
595 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
596 | * during Dx states where the power conservation is most | |
597 | * important. During driver activity we should enable | |
598 | * SmartSpeed, so performance is maintained. | |
599 | */ | |
600 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 601 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 602 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
603 | if (ret_val) |
604 | goto out; | |
605 | ||
606 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 607 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 608 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
609 | if (ret_val) |
610 | goto out; | |
611 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 612 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 613 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
614 | if (ret_val) |
615 | goto out; | |
616 | ||
617 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 618 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 619 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
620 | if (ret_val) |
621 | goto out; | |
622 | } | |
623 | } | |
624 | ||
625 | out: | |
626 | return ret_val; | |
627 | } | |
628 | ||
629 | /** | |
733596be | 630 | * igb_acquire_nvm_82575 - Request for access to EEPROM |
9d5c8243 AK |
631 | * @hw: pointer to the HW structure |
632 | * | |
652fff32 | 633 | * Acquire the necessary semaphores for exclusive access to the EEPROM. |
9d5c8243 AK |
634 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
635 | * Return successful if access grant bit set, else clear the request for | |
636 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
637 | **/ | |
638 | static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) | |
639 | { | |
640 | s32 ret_val; | |
641 | ||
642 | ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
643 | if (ret_val) | |
644 | goto out; | |
645 | ||
646 | ret_val = igb_acquire_nvm(hw); | |
647 | ||
648 | if (ret_val) | |
649 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
650 | ||
651 | out: | |
652 | return ret_val; | |
653 | } | |
654 | ||
655 | /** | |
733596be | 656 | * igb_release_nvm_82575 - Release exclusive access to EEPROM |
9d5c8243 AK |
657 | * @hw: pointer to the HW structure |
658 | * | |
659 | * Stop any current commands to the EEPROM and clear the EEPROM request bit, | |
660 | * then release the semaphores acquired. | |
661 | **/ | |
662 | static void igb_release_nvm_82575(struct e1000_hw *hw) | |
663 | { | |
664 | igb_release_nvm(hw); | |
665 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); | |
666 | } | |
667 | ||
668 | /** | |
733596be | 669 | * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore |
9d5c8243 AK |
670 | * @hw: pointer to the HW structure |
671 | * @mask: specifies which semaphore to acquire | |
672 | * | |
673 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
674 | * will also specify which port we're acquiring the lock for. | |
675 | **/ | |
676 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
677 | { | |
678 | u32 swfw_sync; | |
679 | u32 swmask = mask; | |
680 | u32 fwmask = mask << 16; | |
681 | s32 ret_val = 0; | |
682 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ | |
683 | ||
684 | while (i < timeout) { | |
685 | if (igb_get_hw_semaphore(hw)) { | |
686 | ret_val = -E1000_ERR_SWFW_SYNC; | |
687 | goto out; | |
688 | } | |
689 | ||
690 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
691 | if (!(swfw_sync & (fwmask | swmask))) | |
692 | break; | |
693 | ||
694 | /* | |
695 | * Firmware currently using resource (fwmask) | |
696 | * or other software thread using resource (swmask) | |
697 | */ | |
698 | igb_put_hw_semaphore(hw); | |
699 | mdelay(5); | |
700 | i++; | |
701 | } | |
702 | ||
703 | if (i == timeout) { | |
652fff32 | 704 | hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
9d5c8243 AK |
705 | ret_val = -E1000_ERR_SWFW_SYNC; |
706 | goto out; | |
707 | } | |
708 | ||
709 | swfw_sync |= swmask; | |
710 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
711 | ||
712 | igb_put_hw_semaphore(hw); | |
713 | ||
714 | out: | |
715 | return ret_val; | |
716 | } | |
717 | ||
718 | /** | |
733596be | 719 | * igb_release_swfw_sync_82575 - Release SW/FW semaphore |
9d5c8243 AK |
720 | * @hw: pointer to the HW structure |
721 | * @mask: specifies which semaphore to acquire | |
722 | * | |
723 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
724 | * will also specify which port we're releasing the lock for. | |
725 | **/ | |
726 | static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
727 | { | |
728 | u32 swfw_sync; | |
729 | ||
730 | while (igb_get_hw_semaphore(hw) != 0); | |
731 | /* Empty */ | |
732 | ||
733 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
734 | swfw_sync &= ~mask; | |
735 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
736 | ||
737 | igb_put_hw_semaphore(hw); | |
738 | } | |
739 | ||
740 | /** | |
733596be | 741 | * igb_get_cfg_done_82575 - Read config done bit |
9d5c8243 AK |
742 | * @hw: pointer to the HW structure |
743 | * | |
744 | * Read the management control register for the config done bit for | |
745 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | |
746 | * to read the config done bit, so an error is *ONLY* logged and returns | |
747 | * 0. If we were to return with error, EEPROM-less silicon | |
748 | * would not be able to be reset or change link. | |
749 | **/ | |
750 | static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) | |
751 | { | |
752 | s32 timeout = PHY_CFG_TIMEOUT; | |
753 | s32 ret_val = 0; | |
754 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
755 | ||
756 | if (hw->bus.func == 1) | |
757 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
bb2ac47b AD |
758 | else if (hw->bus.func == E1000_FUNC_2) |
759 | mask = E1000_NVM_CFG_DONE_PORT_2; | |
760 | else if (hw->bus.func == E1000_FUNC_3) | |
761 | mask = E1000_NVM_CFG_DONE_PORT_3; | |
9d5c8243 AK |
762 | |
763 | while (timeout) { | |
764 | if (rd32(E1000_EEMNGCTL) & mask) | |
765 | break; | |
766 | msleep(1); | |
767 | timeout--; | |
768 | } | |
769 | if (!timeout) | |
652fff32 | 770 | hw_dbg("MNG configuration cycle has not completed.\n"); |
9d5c8243 AK |
771 | |
772 | /* If EEPROM is not marked present, init the PHY manually */ | |
773 | if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && | |
774 | (hw->phy.type == e1000_phy_igp_3)) | |
775 | igb_phy_init_script_igp3(hw); | |
776 | ||
777 | return ret_val; | |
778 | } | |
779 | ||
780 | /** | |
733596be | 781 | * igb_check_for_link_82575 - Check for link |
9d5c8243 AK |
782 | * @hw: pointer to the HW structure |
783 | * | |
784 | * If sgmii is enabled, then use the pcs register to determine link, otherwise | |
785 | * use the generic interface for determining link. | |
786 | **/ | |
787 | static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |
788 | { | |
789 | s32 ret_val; | |
790 | u16 speed, duplex; | |
791 | ||
70d92f86 | 792 | if (hw->phy.media_type != e1000_media_type_copper) { |
9d5c8243 | 793 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
2d064c06 | 794 | &duplex); |
5d0932a5 AD |
795 | /* |
796 | * Use this flag to determine if link needs to be checked or | |
797 | * not. If we have link clear the flag so that we do not | |
798 | * continue to check for link. | |
799 | */ | |
800 | hw->mac.get_link_status = !hw->mac.serdes_has_link; | |
801 | } else { | |
9d5c8243 | 802 | ret_val = igb_check_for_copper_link(hw); |
5d0932a5 | 803 | } |
9d5c8243 AK |
804 | |
805 | return ret_val; | |
806 | } | |
70d92f86 | 807 | |
88a268c1 NN |
808 | /** |
809 | * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown | |
810 | * @hw: pointer to the HW structure | |
811 | **/ | |
812 | void igb_power_up_serdes_link_82575(struct e1000_hw *hw) | |
813 | { | |
814 | u32 reg; | |
815 | ||
816 | ||
817 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
818 | !igb_sgmii_active_82575(hw)) | |
819 | return; | |
820 | ||
821 | /* Enable PCS to turn on link */ | |
822 | reg = rd32(E1000_PCS_CFG0); | |
823 | reg |= E1000_PCS_CFG_PCS_EN; | |
824 | wr32(E1000_PCS_CFG0, reg); | |
825 | ||
826 | /* Power up the laser */ | |
827 | reg = rd32(E1000_CTRL_EXT); | |
828 | reg &= ~E1000_CTRL_EXT_SDP3_DATA; | |
829 | wr32(E1000_CTRL_EXT, reg); | |
830 | ||
831 | /* flush the write to verify completion */ | |
832 | wrfl(); | |
833 | msleep(1); | |
834 | } | |
835 | ||
9d5c8243 | 836 | /** |
733596be | 837 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
9d5c8243 AK |
838 | * @hw: pointer to the HW structure |
839 | * @speed: stores the current speed | |
840 | * @duplex: stores the current duplex | |
841 | * | |
652fff32 | 842 | * Using the physical coding sub-layer (PCS), retrieve the current speed and |
9d5c8243 AK |
843 | * duplex, then store the values in the pointers provided. |
844 | **/ | |
845 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, | |
846 | u16 *duplex) | |
847 | { | |
848 | struct e1000_mac_info *mac = &hw->mac; | |
849 | u32 pcs; | |
850 | ||
851 | /* Set up defaults for the return values of this function */ | |
852 | mac->serdes_has_link = false; | |
853 | *speed = 0; | |
854 | *duplex = 0; | |
855 | ||
856 | /* | |
857 | * Read the PCS Status register for link state. For non-copper mode, | |
858 | * the status register is not accurate. The PCS status register is | |
859 | * used instead. | |
860 | */ | |
861 | pcs = rd32(E1000_PCS_LSTAT); | |
862 | ||
863 | /* | |
864 | * The link up bit determines when link is up on autoneg. The sync ok | |
865 | * gets set once both sides sync up and agree upon link. Stable link | |
866 | * can be determined by checking for both link up and link sync ok | |
867 | */ | |
868 | if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { | |
869 | mac->serdes_has_link = true; | |
870 | ||
871 | /* Detect and store PCS speed */ | |
872 | if (pcs & E1000_PCS_LSTS_SPEED_1000) { | |
873 | *speed = SPEED_1000; | |
874 | } else if (pcs & E1000_PCS_LSTS_SPEED_100) { | |
875 | *speed = SPEED_100; | |
876 | } else { | |
877 | *speed = SPEED_10; | |
878 | } | |
879 | ||
880 | /* Detect and store PCS duplex */ | |
881 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { | |
882 | *duplex = FULL_DUPLEX; | |
883 | } else { | |
884 | *duplex = HALF_DUPLEX; | |
885 | } | |
886 | } | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
2d064c06 | 891 | /** |
2fb02a26 | 892 | * igb_shutdown_serdes_link_82575 - Remove link during power down |
9d5c8243 | 893 | * @hw: pointer to the HW structure |
9d5c8243 | 894 | * |
2d064c06 AD |
895 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
896 | * when management pass thru is not enabled. | |
9d5c8243 | 897 | **/ |
2fb02a26 | 898 | void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 899 | { |
2d064c06 AD |
900 | u32 reg; |
901 | ||
53c992fa | 902 | if (hw->phy.media_type != e1000_media_type_internal_serdes && |
2fb02a26 | 903 | igb_sgmii_active_82575(hw)) |
2d064c06 AD |
904 | return; |
905 | ||
53c992fa | 906 | if (!igb_enable_mng_pass_thru(hw)) { |
2d064c06 AD |
907 | /* Disable PCS to turn off link */ |
908 | reg = rd32(E1000_PCS_CFG0); | |
909 | reg &= ~E1000_PCS_CFG_PCS_EN; | |
910 | wr32(E1000_PCS_CFG0, reg); | |
911 | ||
912 | /* shutdown the laser */ | |
913 | reg = rd32(E1000_CTRL_EXT); | |
2fb02a26 | 914 | reg |= E1000_CTRL_EXT_SDP3_DATA; |
2d064c06 AD |
915 | wr32(E1000_CTRL_EXT, reg); |
916 | ||
917 | /* flush the write to verify completion */ | |
918 | wrfl(); | |
919 | msleep(1); | |
920 | } | |
9d5c8243 AK |
921 | } |
922 | ||
923 | /** | |
733596be | 924 | * igb_reset_hw_82575 - Reset hardware |
9d5c8243 AK |
925 | * @hw: pointer to the HW structure |
926 | * | |
927 | * This resets the hardware into a known state. This is a | |
928 | * function pointer entry point called by the api module. | |
929 | **/ | |
930 | static s32 igb_reset_hw_82575(struct e1000_hw *hw) | |
931 | { | |
932 | u32 ctrl, icr; | |
933 | s32 ret_val; | |
934 | ||
935 | /* | |
936 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
937 | * on the last TLP read/write transaction when MAC is reset. | |
938 | */ | |
939 | ret_val = igb_disable_pcie_master(hw); | |
940 | if (ret_val) | |
652fff32 | 941 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
9d5c8243 | 942 | |
009bc06e AD |
943 | /* set the completion timeout for interface */ |
944 | ret_val = igb_set_pcie_completion_timeout(hw); | |
945 | if (ret_val) { | |
946 | hw_dbg("PCI-E Set completion timeout has failed.\n"); | |
947 | } | |
948 | ||
652fff32 | 949 | hw_dbg("Masking off all interrupts\n"); |
9d5c8243 AK |
950 | wr32(E1000_IMC, 0xffffffff); |
951 | ||
952 | wr32(E1000_RCTL, 0); | |
953 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
954 | wrfl(); | |
955 | ||
956 | msleep(10); | |
957 | ||
958 | ctrl = rd32(E1000_CTRL); | |
959 | ||
652fff32 | 960 | hw_dbg("Issuing a global reset to MAC\n"); |
9d5c8243 AK |
961 | wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); |
962 | ||
963 | ret_val = igb_get_auto_rd_done(hw); | |
964 | if (ret_val) { | |
965 | /* | |
966 | * When auto config read does not complete, do not | |
967 | * return with an error. This can happen in situations | |
968 | * where there is no eeprom and prevents getting link. | |
969 | */ | |
652fff32 | 970 | hw_dbg("Auto Read Done did not complete\n"); |
9d5c8243 AK |
971 | } |
972 | ||
973 | /* If EEPROM is not present, run manual init scripts */ | |
974 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
975 | igb_reset_init_script_82575(hw); | |
976 | ||
977 | /* Clear any pending interrupt events. */ | |
978 | wr32(E1000_IMC, 0xffffffff); | |
979 | icr = rd32(E1000_ICR); | |
980 | ||
5ac16659 AD |
981 | /* Install any alternate MAC address into RAR0 */ |
982 | ret_val = igb_check_alt_mac_addr(hw); | |
9d5c8243 AK |
983 | |
984 | return ret_val; | |
985 | } | |
986 | ||
987 | /** | |
733596be | 988 | * igb_init_hw_82575 - Initialize hardware |
9d5c8243 AK |
989 | * @hw: pointer to the HW structure |
990 | * | |
991 | * This inits the hardware readying it for operation. | |
992 | **/ | |
993 | static s32 igb_init_hw_82575(struct e1000_hw *hw) | |
994 | { | |
995 | struct e1000_mac_info *mac = &hw->mac; | |
996 | s32 ret_val; | |
997 | u16 i, rar_count = mac->rar_entry_count; | |
998 | ||
999 | /* Initialize identification LED */ | |
1000 | ret_val = igb_id_led_init(hw); | |
1001 | if (ret_val) { | |
652fff32 | 1002 | hw_dbg("Error initializing identification LED\n"); |
9d5c8243 AK |
1003 | /* This is not fatal and we should not stop init due to this */ |
1004 | } | |
1005 | ||
1006 | /* Disabling VLAN filtering */ | |
652fff32 | 1007 | hw_dbg("Initializing the IEEE VLAN\n"); |
9d5c8243 AK |
1008 | igb_clear_vfta(hw); |
1009 | ||
1010 | /* Setup the receive address */ | |
5ac16659 AD |
1011 | igb_init_rx_addrs(hw, rar_count); |
1012 | ||
9d5c8243 | 1013 | /* Zero out the Multicast HASH table */ |
652fff32 | 1014 | hw_dbg("Zeroing the MTA\n"); |
9d5c8243 AK |
1015 | for (i = 0; i < mac->mta_reg_count; i++) |
1016 | array_wr32(E1000_MTA, i, 0); | |
1017 | ||
68d480c4 AD |
1018 | /* Zero out the Unicast HASH table */ |
1019 | hw_dbg("Zeroing the UTA\n"); | |
1020 | for (i = 0; i < mac->uta_reg_count; i++) | |
1021 | array_wr32(E1000_UTA, i, 0); | |
1022 | ||
9d5c8243 AK |
1023 | /* Setup link and flow control */ |
1024 | ret_val = igb_setup_link(hw); | |
1025 | ||
1026 | /* | |
1027 | * Clear all of the statistics registers (clear on read). It is | |
1028 | * important that we do this after we have tried to establish link | |
1029 | * because the symbol error count will increment wildly if there | |
1030 | * is no link. | |
1031 | */ | |
1032 | igb_clear_hw_cntrs_82575(hw); | |
1033 | ||
1034 | return ret_val; | |
1035 | } | |
1036 | ||
1037 | /** | |
733596be | 1038 | * igb_setup_copper_link_82575 - Configure copper link settings |
9d5c8243 AK |
1039 | * @hw: pointer to the HW structure |
1040 | * | |
1041 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1042 | * for link, once link is established calls to configure collision distance | |
1043 | * and flow control are called. | |
1044 | **/ | |
1045 | static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) | |
1046 | { | |
12645a19 | 1047 | u32 ctrl; |
9d5c8243 | 1048 | s32 ret_val; |
9d5c8243 AK |
1049 | |
1050 | ctrl = rd32(E1000_CTRL); | |
1051 | ctrl |= E1000_CTRL_SLU; | |
1052 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1053 | wr32(E1000_CTRL, ctrl); | |
1054 | ||
2fb02a26 AD |
1055 | ret_val = igb_setup_serdes_link_82575(hw); |
1056 | if (ret_val) | |
1057 | goto out; | |
1058 | ||
1059 | if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { | |
bb2ac47b AD |
1060 | /* allow time for SFP cage time to power up phy */ |
1061 | msleep(300); | |
1062 | ||
2fb02a26 AD |
1063 | ret_val = hw->phy.ops.reset(hw); |
1064 | if (ret_val) { | |
1065 | hw_dbg("Error resetting the PHY.\n"); | |
1066 | goto out; | |
1067 | } | |
1068 | } | |
9d5c8243 AK |
1069 | switch (hw->phy.type) { |
1070 | case e1000_phy_m88: | |
308fb39a JG |
1071 | if (hw->phy.id == I347AT4_E_PHY_ID || |
1072 | hw->phy.id == M88E1112_E_PHY_ID) | |
1073 | ret_val = igb_copper_link_setup_m88_gen2(hw); | |
1074 | else | |
1075 | ret_val = igb_copper_link_setup_m88(hw); | |
9d5c8243 AK |
1076 | break; |
1077 | case e1000_phy_igp_3: | |
1078 | ret_val = igb_copper_link_setup_igp(hw); | |
9d5c8243 | 1079 | break; |
bb2ac47b AD |
1080 | case e1000_phy_82580: |
1081 | ret_val = igb_copper_link_setup_82580(hw); | |
1082 | break; | |
9d5c8243 AK |
1083 | default: |
1084 | ret_val = -E1000_ERR_PHY; | |
1085 | break; | |
1086 | } | |
1087 | ||
1088 | if (ret_val) | |
1089 | goto out; | |
1090 | ||
81fadd81 | 1091 | ret_val = igb_setup_copper_link(hw); |
9d5c8243 AK |
1092 | out: |
1093 | return ret_val; | |
1094 | } | |
1095 | ||
1096 | /** | |
70d92f86 | 1097 | * igb_setup_serdes_link_82575 - Setup link for serdes |
9d5c8243 AK |
1098 | * @hw: pointer to the HW structure |
1099 | * | |
70d92f86 AD |
1100 | * Configure the physical coding sub-layer (PCS) link. The PCS link is |
1101 | * used on copper connections where the serialized gigabit media independent | |
1102 | * interface (sgmii), or serdes fiber is being used. Configures the link | |
1103 | * for auto-negotiation or forces speed/duplex. | |
9d5c8243 | 1104 | **/ |
2fb02a26 | 1105 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 1106 | { |
bb2ac47b AD |
1107 | u32 ctrl_ext, ctrl_reg, reg; |
1108 | bool pcs_autoneg; | |
2fb02a26 AD |
1109 | |
1110 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
1111 | !igb_sgmii_active_82575(hw)) | |
1112 | return 0; | |
9d5c8243 AK |
1113 | |
1114 | /* | |
1115 | * On the 82575, SerDes loopback mode persists until it is | |
1116 | * explicitly turned off or a power cycle is performed. A read to | |
1117 | * the register does not indicate its status. Therefore, we ensure | |
1118 | * loopback mode is disabled during initialization. | |
1119 | */ | |
1120 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); | |
1121 | ||
2fb02a26 | 1122 | /* power on the sfp cage if present */ |
bb2ac47b AD |
1123 | ctrl_ext = rd32(E1000_CTRL_EXT); |
1124 | ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; | |
1125 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
2fb02a26 AD |
1126 | |
1127 | ctrl_reg = rd32(E1000_CTRL); | |
1128 | ctrl_reg |= E1000_CTRL_SLU; | |
1129 | ||
1130 | if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { | |
1131 | /* set both sw defined pins */ | |
1132 | ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; | |
1133 | ||
1134 | /* Set switch control to serdes energy detect */ | |
1135 | reg = rd32(E1000_CONNSW); | |
1136 | reg |= E1000_CONNSW_ENRGSRC; | |
1137 | wr32(E1000_CONNSW, reg); | |
1138 | } | |
1139 | ||
1140 | reg = rd32(E1000_PCS_LCTL); | |
1141 | ||
bb2ac47b AD |
1142 | /* default pcs_autoneg to the same setting as mac autoneg */ |
1143 | pcs_autoneg = hw->mac.autoneg; | |
2fb02a26 | 1144 | |
bb2ac47b AD |
1145 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
1146 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
1147 | /* sgmii mode lets the phy handle forcing speed/duplex */ | |
1148 | pcs_autoneg = true; | |
1149 | /* autoneg time out should be disabled for SGMII mode */ | |
2fb02a26 | 1150 | reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); |
bb2ac47b AD |
1151 | break; |
1152 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: | |
1153 | /* disable PCS autoneg and support parallel detect only */ | |
1154 | pcs_autoneg = false; | |
1155 | default: | |
1156 | /* | |
1157 | * non-SGMII modes only supports a speed of 1000/Full for the | |
1158 | * link so it is best to just force the MAC and let the pcs | |
1159 | * link either autoneg or be forced to 1000/Full | |
1160 | */ | |
2fb02a26 AD |
1161 | ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | |
1162 | E1000_CTRL_FD | E1000_CTRL_FRCDPX; | |
bb2ac47b AD |
1163 | |
1164 | /* set speed of 1000/Full if speed/duplex is forced */ | |
1165 | reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; | |
1166 | break; | |
921aa749 AD |
1167 | } |
1168 | ||
2fb02a26 | 1169 | wr32(E1000_CTRL, ctrl_reg); |
9d5c8243 AK |
1170 | |
1171 | /* | |
1172 | * New SerDes mode allows for forcing speed or autonegotiating speed | |
1173 | * at 1gb. Autoneg should be default set by most drivers. This is the | |
1174 | * mode that will be compatible with older link partners and switches. | |
1175 | * However, both are supported by the hardware and some drivers/tools. | |
1176 | */ | |
9d5c8243 AK |
1177 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
1178 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | |
1179 | ||
2fb02a26 AD |
1180 | /* |
1181 | * We force flow control to prevent the CTRL register values from being | |
1182 | * overwritten by the autonegotiated flow control values | |
1183 | */ | |
1184 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1185 | ||
bb2ac47b | 1186 | if (pcs_autoneg) { |
9d5c8243 | 1187 | /* Set PCS register for autoneg */ |
bb2ac47b | 1188 | reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ |
70d92f86 | 1189 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ |
bb2ac47b | 1190 | hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); |
9d5c8243 | 1191 | } else { |
bb2ac47b | 1192 | /* Set PCS register for forced link */ |
d68caec6 | 1193 | reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ |
bb2ac47b AD |
1194 | |
1195 | hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); | |
9d5c8243 | 1196 | } |
726c09e7 | 1197 | |
9d5c8243 AK |
1198 | wr32(E1000_PCS_LCTL, reg); |
1199 | ||
2fb02a26 AD |
1200 | if (!igb_sgmii_active_82575(hw)) |
1201 | igb_force_mac_fc(hw); | |
9d5c8243 | 1202 | |
2fb02a26 | 1203 | return 0; |
9d5c8243 AK |
1204 | } |
1205 | ||
1206 | /** | |
733596be | 1207 | * igb_sgmii_active_82575 - Return sgmii state |
9d5c8243 AK |
1208 | * @hw: pointer to the HW structure |
1209 | * | |
1210 | * 82575 silicon has a serialized gigabit media independent interface (sgmii) | |
1211 | * which can be enabled for use in the embedded applications. Simply | |
1212 | * return the current state of the sgmii interface. | |
1213 | **/ | |
1214 | static bool igb_sgmii_active_82575(struct e1000_hw *hw) | |
1215 | { | |
c1889bfe | 1216 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
c1889bfe | 1217 | return dev_spec->sgmii_active; |
9d5c8243 AK |
1218 | } |
1219 | ||
1220 | /** | |
733596be | 1221 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
9d5c8243 AK |
1222 | * @hw: pointer to the HW structure |
1223 | * | |
1224 | * Inits recommended HW defaults after a reset when there is no EEPROM | |
1225 | * detected. This is only for the 82575. | |
1226 | **/ | |
1227 | static s32 igb_reset_init_script_82575(struct e1000_hw *hw) | |
1228 | { | |
1229 | if (hw->mac.type == e1000_82575) { | |
652fff32 | 1230 | hw_dbg("Running reset init script for 82575\n"); |
9d5c8243 AK |
1231 | /* SerDes configuration via SERDESCTRL */ |
1232 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); | |
1233 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); | |
1234 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); | |
1235 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); | |
1236 | ||
1237 | /* CCM configuration via CCMCTL register */ | |
1238 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); | |
1239 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); | |
1240 | ||
1241 | /* PCIe lanes configuration */ | |
1242 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); | |
1243 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); | |
1244 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); | |
1245 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); | |
1246 | ||
1247 | /* PCIe PLL Configuration */ | |
1248 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); | |
1249 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); | |
1250 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); | |
1251 | } | |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | ||
1256 | /** | |
733596be | 1257 | * igb_read_mac_addr_82575 - Read device MAC address |
9d5c8243 AK |
1258 | * @hw: pointer to the HW structure |
1259 | **/ | |
1260 | static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) | |
1261 | { | |
1262 | s32 ret_val = 0; | |
1263 | ||
22896639 AD |
1264 | /* |
1265 | * If there's an alternate MAC address place it in RAR0 | |
1266 | * so that it will override the Si installed default perm | |
1267 | * address. | |
1268 | */ | |
1269 | ret_val = igb_check_alt_mac_addr(hw); | |
1270 | if (ret_val) | |
1271 | goto out; | |
1272 | ||
1273 | ret_val = igb_read_mac_addr(hw); | |
9d5c8243 | 1274 | |
22896639 | 1275 | out: |
9d5c8243 AK |
1276 | return ret_val; |
1277 | } | |
1278 | ||
88a268c1 NN |
1279 | /** |
1280 | * igb_power_down_phy_copper_82575 - Remove link during PHY power down | |
1281 | * @hw: pointer to the HW structure | |
1282 | * | |
1283 | * In the case of a PHY power down to save power, or to turn off link during a | |
1284 | * driver unload, or wake on lan is not enabled, remove the link. | |
1285 | **/ | |
1286 | void igb_power_down_phy_copper_82575(struct e1000_hw *hw) | |
1287 | { | |
1288 | /* If the management interface is not enabled, then power down */ | |
1289 | if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) | |
1290 | igb_power_down_phy_copper(hw); | |
88a268c1 NN |
1291 | } |
1292 | ||
9d5c8243 | 1293 | /** |
733596be | 1294 | * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters |
9d5c8243 AK |
1295 | * @hw: pointer to the HW structure |
1296 | * | |
1297 | * Clears the hardware counters by reading the counter registers. | |
1298 | **/ | |
1299 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) | |
1300 | { | |
9d5c8243 AK |
1301 | igb_clear_hw_cntrs_base(hw); |
1302 | ||
cc9073bb AD |
1303 | rd32(E1000_PRC64); |
1304 | rd32(E1000_PRC127); | |
1305 | rd32(E1000_PRC255); | |
1306 | rd32(E1000_PRC511); | |
1307 | rd32(E1000_PRC1023); | |
1308 | rd32(E1000_PRC1522); | |
1309 | rd32(E1000_PTC64); | |
1310 | rd32(E1000_PTC127); | |
1311 | rd32(E1000_PTC255); | |
1312 | rd32(E1000_PTC511); | |
1313 | rd32(E1000_PTC1023); | |
1314 | rd32(E1000_PTC1522); | |
1315 | ||
1316 | rd32(E1000_ALGNERRC); | |
1317 | rd32(E1000_RXERRC); | |
1318 | rd32(E1000_TNCRS); | |
1319 | rd32(E1000_CEXTERR); | |
1320 | rd32(E1000_TSCTC); | |
1321 | rd32(E1000_TSCTFC); | |
1322 | ||
1323 | rd32(E1000_MGTPRC); | |
1324 | rd32(E1000_MGTPDC); | |
1325 | rd32(E1000_MGTPTC); | |
1326 | ||
1327 | rd32(E1000_IAC); | |
1328 | rd32(E1000_ICRXOC); | |
1329 | ||
1330 | rd32(E1000_ICRXPTC); | |
1331 | rd32(E1000_ICRXATC); | |
1332 | rd32(E1000_ICTXPTC); | |
1333 | rd32(E1000_ICTXATC); | |
1334 | rd32(E1000_ICTXQEC); | |
1335 | rd32(E1000_ICTXQMTC); | |
1336 | rd32(E1000_ICRXDMTC); | |
1337 | ||
1338 | rd32(E1000_CBTMPC); | |
1339 | rd32(E1000_HTDPMC); | |
1340 | rd32(E1000_CBRMPC); | |
1341 | rd32(E1000_RPTHC); | |
1342 | rd32(E1000_HGPTC); | |
1343 | rd32(E1000_HTCBDPC); | |
1344 | rd32(E1000_HGORCL); | |
1345 | rd32(E1000_HGORCH); | |
1346 | rd32(E1000_HGOTCL); | |
1347 | rd32(E1000_HGOTCH); | |
1348 | rd32(E1000_LENERRS); | |
9d5c8243 AK |
1349 | |
1350 | /* This register should not be read in copper configurations */ | |
2fb02a26 AD |
1351 | if (hw->phy.media_type == e1000_media_type_internal_serdes || |
1352 | igb_sgmii_active_82575(hw)) | |
cc9073bb | 1353 | rd32(E1000_SCVPC); |
9d5c8243 AK |
1354 | } |
1355 | ||
662d7205 AD |
1356 | /** |
1357 | * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable | |
1358 | * @hw: pointer to the HW structure | |
1359 | * | |
1360 | * After rx enable if managability is enabled then there is likely some | |
1361 | * bad data at the start of the fifo and possibly in the DMA fifo. This | |
1362 | * function clears the fifos and flushes any packets that came in as rx was | |
1363 | * being enabled. | |
1364 | **/ | |
1365 | void igb_rx_fifo_flush_82575(struct e1000_hw *hw) | |
1366 | { | |
1367 | u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; | |
1368 | int i, ms_wait; | |
1369 | ||
1370 | if (hw->mac.type != e1000_82575 || | |
1371 | !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) | |
1372 | return; | |
1373 | ||
1374 | /* Disable all RX queues */ | |
1375 | for (i = 0; i < 4; i++) { | |
1376 | rxdctl[i] = rd32(E1000_RXDCTL(i)); | |
1377 | wr32(E1000_RXDCTL(i), | |
1378 | rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); | |
1379 | } | |
1380 | /* Poll all queues to verify they have shut down */ | |
1381 | for (ms_wait = 0; ms_wait < 10; ms_wait++) { | |
1382 | msleep(1); | |
1383 | rx_enabled = 0; | |
1384 | for (i = 0; i < 4; i++) | |
1385 | rx_enabled |= rd32(E1000_RXDCTL(i)); | |
1386 | if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) | |
1387 | break; | |
1388 | } | |
1389 | ||
1390 | if (ms_wait == 10) | |
1391 | hw_dbg("Queue disable timed out after 10ms\n"); | |
1392 | ||
1393 | /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all | |
1394 | * incoming packets are rejected. Set enable and wait 2ms so that | |
1395 | * any packet that was coming in as RCTL.EN was set is flushed | |
1396 | */ | |
1397 | rfctl = rd32(E1000_RFCTL); | |
1398 | wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); | |
1399 | ||
1400 | rlpml = rd32(E1000_RLPML); | |
1401 | wr32(E1000_RLPML, 0); | |
1402 | ||
1403 | rctl = rd32(E1000_RCTL); | |
1404 | temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); | |
1405 | temp_rctl |= E1000_RCTL_LPE; | |
1406 | ||
1407 | wr32(E1000_RCTL, temp_rctl); | |
1408 | wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); | |
1409 | wrfl(); | |
1410 | msleep(2); | |
1411 | ||
1412 | /* Enable RX queues that were previously enabled and restore our | |
1413 | * previous state | |
1414 | */ | |
1415 | for (i = 0; i < 4; i++) | |
1416 | wr32(E1000_RXDCTL(i), rxdctl[i]); | |
1417 | wr32(E1000_RCTL, rctl); | |
1418 | wrfl(); | |
1419 | ||
1420 | wr32(E1000_RLPML, rlpml); | |
1421 | wr32(E1000_RFCTL, rfctl); | |
1422 | ||
1423 | /* Flush receive errors generated by workaround */ | |
1424 | rd32(E1000_ROC); | |
1425 | rd32(E1000_RNBC); | |
1426 | rd32(E1000_MPC); | |
1427 | } | |
1428 | ||
009bc06e AD |
1429 | /** |
1430 | * igb_set_pcie_completion_timeout - set pci-e completion timeout | |
1431 | * @hw: pointer to the HW structure | |
1432 | * | |
1433 | * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, | |
1434 | * however the hardware default for these parts is 500us to 1ms which is less | |
1435 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
1436 | * increase the value to either 10ms to 200ms for capability version 1 config, | |
1437 | * or 16ms to 55ms for version 2. | |
1438 | **/ | |
1439 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) | |
1440 | { | |
1441 | u32 gcr = rd32(E1000_GCR); | |
1442 | s32 ret_val = 0; | |
1443 | u16 pcie_devctl2; | |
1444 | ||
1445 | /* only take action if timeout value is defaulted to 0 */ | |
1446 | if (gcr & E1000_GCR_CMPL_TMOUT_MASK) | |
1447 | goto out; | |
1448 | ||
1449 | /* | |
1450 | * if capababilities version is type 1 we can write the | |
1451 | * timeout of 10ms to 200ms through the GCR register | |
1452 | */ | |
1453 | if (!(gcr & E1000_GCR_CAP_VER2)) { | |
1454 | gcr |= E1000_GCR_CMPL_TMOUT_10ms; | |
1455 | goto out; | |
1456 | } | |
1457 | ||
1458 | /* | |
1459 | * for version 2 capabilities we need to write the config space | |
1460 | * directly in order to set the completion timeout value for | |
1461 | * 16ms to 55ms | |
1462 | */ | |
1463 | ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1464 | &pcie_devctl2); | |
1465 | if (ret_val) | |
1466 | goto out; | |
1467 | ||
1468 | pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; | |
1469 | ||
1470 | ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1471 | &pcie_devctl2); | |
1472 | out: | |
1473 | /* disable completion timeout resend */ | |
1474 | gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; | |
1475 | ||
1476 | wr32(E1000_GCR, gcr); | |
1477 | return ret_val; | |
1478 | } | |
1479 | ||
4ae196df AD |
1480 | /** |
1481 | * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback | |
1482 | * @hw: pointer to the hardware struct | |
1483 | * @enable: state to enter, either enabled or disabled | |
1484 | * | |
1485 | * enables/disables L2 switch loopback functionality. | |
1486 | **/ | |
1487 | void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) | |
1488 | { | |
1489 | u32 dtxswc = rd32(E1000_DTXSWC); | |
1490 | ||
1491 | if (enable) | |
1492 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1493 | else | |
1494 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1495 | ||
1496 | wr32(E1000_DTXSWC, dtxswc); | |
1497 | } | |
1498 | ||
1499 | /** | |
1500 | * igb_vmdq_set_replication_pf - enable or disable vmdq replication | |
1501 | * @hw: pointer to the hardware struct | |
1502 | * @enable: state to enter, either enabled or disabled | |
1503 | * | |
1504 | * enables/disables replication of packets across multiple pools. | |
1505 | **/ | |
1506 | void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) | |
1507 | { | |
1508 | u32 vt_ctl = rd32(E1000_VT_CTL); | |
1509 | ||
1510 | if (enable) | |
1511 | vt_ctl |= E1000_VT_CTL_VM_REPL_EN; | |
1512 | else | |
1513 | vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; | |
1514 | ||
1515 | wr32(E1000_VT_CTL, vt_ctl); | |
1516 | } | |
1517 | ||
bb2ac47b AD |
1518 | /** |
1519 | * igb_read_phy_reg_82580 - Read 82580 MDI control register | |
1520 | * @hw: pointer to the HW structure | |
1521 | * @offset: register offset to be read | |
1522 | * @data: pointer to the read data | |
1523 | * | |
1524 | * Reads the MDI control register in the PHY at offset and stores the | |
1525 | * information read to data. | |
1526 | **/ | |
1527 | static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) | |
1528 | { | |
bb2ac47b AD |
1529 | s32 ret_val; |
1530 | ||
1531 | ||
1532 | ret_val = hw->phy.ops.acquire(hw); | |
1533 | if (ret_val) | |
1534 | goto out; | |
1535 | ||
bb2ac47b AD |
1536 | ret_val = igb_read_phy_reg_mdic(hw, offset, data); |
1537 | ||
1538 | hw->phy.ops.release(hw); | |
1539 | ||
1540 | out: | |
1541 | return ret_val; | |
1542 | } | |
1543 | ||
1544 | /** | |
1545 | * igb_write_phy_reg_82580 - Write 82580 MDI control register | |
1546 | * @hw: pointer to the HW structure | |
1547 | * @offset: register offset to write to | |
1548 | * @data: data to write to register at offset | |
1549 | * | |
1550 | * Writes data to MDI control register in the PHY at offset. | |
1551 | **/ | |
1552 | static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) | |
1553 | { | |
bb2ac47b AD |
1554 | s32 ret_val; |
1555 | ||
1556 | ||
1557 | ret_val = hw->phy.ops.acquire(hw); | |
1558 | if (ret_val) | |
1559 | goto out; | |
1560 | ||
bb2ac47b AD |
1561 | ret_val = igb_write_phy_reg_mdic(hw, offset, data); |
1562 | ||
1563 | hw->phy.ops.release(hw); | |
1564 | ||
1565 | out: | |
1566 | return ret_val; | |
1567 | } | |
1568 | ||
08451e25 NN |
1569 | /** |
1570 | * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits | |
1571 | * @hw: pointer to the HW structure | |
1572 | * | |
1573 | * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on | |
1574 | * the values found in the EEPROM. This addresses an issue in which these | |
1575 | * bits are not restored from EEPROM after reset. | |
1576 | **/ | |
1577 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) | |
1578 | { | |
1579 | s32 ret_val = 0; | |
1580 | u32 mdicnfg; | |
1581 | u16 nvm_data; | |
1582 | ||
1583 | if (hw->mac.type != e1000_82580) | |
1584 | goto out; | |
1585 | if (!igb_sgmii_active_82575(hw)) | |
1586 | goto out; | |
1587 | ||
1588 | ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + | |
1589 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
1590 | &nvm_data); | |
1591 | if (ret_val) { | |
1592 | hw_dbg("NVM Read Error\n"); | |
1593 | goto out; | |
1594 | } | |
1595 | ||
1596 | mdicnfg = rd32(E1000_MDICNFG); | |
1597 | if (nvm_data & NVM_WORD24_EXT_MDIO) | |
1598 | mdicnfg |= E1000_MDICNFG_EXT_MDIO; | |
1599 | if (nvm_data & NVM_WORD24_COM_MDIO) | |
1600 | mdicnfg |= E1000_MDICNFG_COM_MDIO; | |
1601 | wr32(E1000_MDICNFG, mdicnfg); | |
1602 | out: | |
1603 | return ret_val; | |
1604 | } | |
1605 | ||
bb2ac47b AD |
1606 | /** |
1607 | * igb_reset_hw_82580 - Reset hardware | |
1608 | * @hw: pointer to the HW structure | |
1609 | * | |
1610 | * This resets function or entire device (all ports, etc.) | |
1611 | * to a known state. | |
1612 | **/ | |
1613 | static s32 igb_reset_hw_82580(struct e1000_hw *hw) | |
1614 | { | |
1615 | s32 ret_val = 0; | |
1616 | /* BH SW mailbox bit in SW_FW_SYNC */ | |
1617 | u16 swmbsw_mask = E1000_SW_SYNCH_MB; | |
1618 | u32 ctrl, icr; | |
1619 | bool global_device_reset = hw->dev_spec._82575.global_device_reset; | |
1620 | ||
1621 | ||
1622 | hw->dev_spec._82575.global_device_reset = false; | |
1623 | ||
1624 | /* Get current control state. */ | |
1625 | ctrl = rd32(E1000_CTRL); | |
1626 | ||
1627 | /* | |
1628 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
1629 | * on the last TLP read/write transaction when MAC is reset. | |
1630 | */ | |
1631 | ret_val = igb_disable_pcie_master(hw); | |
1632 | if (ret_val) | |
1633 | hw_dbg("PCI-E Master disable polling has failed.\n"); | |
1634 | ||
1635 | hw_dbg("Masking off all interrupts\n"); | |
1636 | wr32(E1000_IMC, 0xffffffff); | |
1637 | wr32(E1000_RCTL, 0); | |
1638 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
1639 | wrfl(); | |
1640 | ||
1641 | msleep(10); | |
1642 | ||
1643 | /* Determine whether or not a global dev reset is requested */ | |
1644 | if (global_device_reset && | |
1645 | igb_acquire_swfw_sync_82575(hw, swmbsw_mask)) | |
1646 | global_device_reset = false; | |
1647 | ||
1648 | if (global_device_reset && | |
1649 | !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) | |
1650 | ctrl |= E1000_CTRL_DEV_RST; | |
1651 | else | |
1652 | ctrl |= E1000_CTRL_RST; | |
1653 | ||
1654 | wr32(E1000_CTRL, ctrl); | |
1655 | ||
1656 | /* Add delay to insure DEV_RST has time to complete */ | |
1657 | if (global_device_reset) | |
1658 | msleep(5); | |
1659 | ||
1660 | ret_val = igb_get_auto_rd_done(hw); | |
1661 | if (ret_val) { | |
1662 | /* | |
1663 | * When auto config read does not complete, do not | |
1664 | * return with an error. This can happen in situations | |
1665 | * where there is no eeprom and prevents getting link. | |
1666 | */ | |
1667 | hw_dbg("Auto Read Done did not complete\n"); | |
1668 | } | |
1669 | ||
1670 | /* If EEPROM is not present, run manual init scripts */ | |
1671 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
1672 | igb_reset_init_script_82575(hw); | |
1673 | ||
1674 | /* clear global device reset status bit */ | |
1675 | wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); | |
1676 | ||
1677 | /* Clear any pending interrupt events. */ | |
1678 | wr32(E1000_IMC, 0xffffffff); | |
1679 | icr = rd32(E1000_ICR); | |
1680 | ||
08451e25 NN |
1681 | ret_val = igb_reset_mdicnfg_82580(hw); |
1682 | if (ret_val) | |
1683 | hw_dbg("Could not reset MDICNFG based on EEPROM\n"); | |
1684 | ||
bb2ac47b AD |
1685 | /* Install any alternate MAC address into RAR0 */ |
1686 | ret_val = igb_check_alt_mac_addr(hw); | |
1687 | ||
1688 | /* Release semaphore */ | |
1689 | if (global_device_reset) | |
1690 | igb_release_swfw_sync_82575(hw, swmbsw_mask); | |
1691 | ||
1692 | return ret_val; | |
1693 | } | |
1694 | ||
1695 | /** | |
1696 | * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size | |
1697 | * @data: data received by reading RXPBS register | |
1698 | * | |
1699 | * The 82580 uses a table based approach for packet buffer allocation sizes. | |
1700 | * This function converts the retrieved value into the correct table value | |
1701 | * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 | |
1702 | * 0x0 36 72 144 1 2 4 8 16 | |
1703 | * 0x8 35 70 140 rsv rsv rsv rsv rsv | |
1704 | */ | |
1705 | u16 igb_rxpbs_adjust_82580(u32 data) | |
1706 | { | |
1707 | u16 ret_val = 0; | |
1708 | ||
1709 | if (data < E1000_82580_RXPBS_TABLE_SIZE) | |
1710 | ret_val = e1000_82580_rxpbs_table[data]; | |
1711 | ||
1712 | return ret_val; | |
1713 | } | |
1714 | ||
9d5c8243 | 1715 | static struct e1000_mac_operations e1000_mac_ops_82575 = { |
9d5c8243 AK |
1716 | .init_hw = igb_init_hw_82575, |
1717 | .check_for_link = igb_check_for_link_82575, | |
2d064c06 | 1718 | .rar_set = igb_rar_set, |
9d5c8243 AK |
1719 | .read_mac_addr = igb_read_mac_addr_82575, |
1720 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, | |
1721 | }; | |
1722 | ||
1723 | static struct e1000_phy_operations e1000_phy_ops_82575 = { | |
a8d2a0c2 | 1724 | .acquire = igb_acquire_phy_82575, |
9d5c8243 | 1725 | .get_cfg_done = igb_get_cfg_done_82575, |
a8d2a0c2 | 1726 | .release = igb_release_phy_82575, |
9d5c8243 AK |
1727 | }; |
1728 | ||
1729 | static struct e1000_nvm_operations e1000_nvm_ops_82575 = { | |
312c75ae AD |
1730 | .acquire = igb_acquire_nvm_82575, |
1731 | .read = igb_read_nvm_eerd, | |
1732 | .release = igb_release_nvm_82575, | |
1733 | .write = igb_write_nvm_spi, | |
9d5c8243 AK |
1734 | }; |
1735 | ||
1736 | const struct e1000_info e1000_82575_info = { | |
1737 | .get_invariants = igb_get_invariants_82575, | |
1738 | .mac_ops = &e1000_mac_ops_82575, | |
1739 | .phy_ops = &e1000_phy_ops_82575, | |
1740 | .nvm_ops = &e1000_nvm_ops_82575, | |
1741 | }; | |
1742 |