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[net-next-2.6.git] / drivers / net / ibm_newemac / core.c
CommitLineData
1d3bb996
DG		 1/*
2 * drivers/net/ibm_newemac/core.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
17cf803a
BH		 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
1d3bb996
DG		 11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Matt Porter <mporter@kernel.crashing.org>
16 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
17 * Armin Kuster <akuster@mvista.com>
18 * Johnnie Peters <jpeters@mvista.com>
19 *
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
24 *
25 */
26
e72701ac 27#include <linux/module.h>
1d3bb996
DG		 28#include <linux/sched.h>
29#include <linux/string.h>
30#include <linux/errno.h>
31#include <linux/delay.h>
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/crc32.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
39#include <linux/bitops.h>
40#include <linux/workqueue.h>
283029d1 41#include <linux/of.h>
5a0e3ad6 42#include <linux/slab.h>
1d3bb996
DG		 43
44#include <asm/processor.h>
45#include <asm/io.h>
46#include <asm/dma.h>
47#include <asm/uaccess.h>
0925ab5d
VB		 48#include <asm/dcr.h>
49#include <asm/dcr-regs.h>
1d3bb996
DG		 50
51#include "core.h"
52
53/*
54 * Lack of dma_unmap_???? calls is intentional.
55 *
56 * API-correct usage requires additional support state information to be
57 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
58 * EMAC design (e.g. TX buffer passed from network stack can be split into
59 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
60 * maintaining such information will add additional overhead.
61 * Current DMA API implementation for 4xx processors only ensures cache coherency
62 * and dma_unmap_???? routines are empty and are likely to stay this way.
63 * I decided to omit dma_unmap_??? calls because I don't want to add additional
64 * complexity just for the sake of following some abstract API, when it doesn't
65 * add any real benefit to the driver. I understand that this decision maybe
66 * controversial, but I really tried to make code API-correct and efficient
67 * at the same time and didn't come up with code I liked :(. --ebs
68 */
69
70#define DRV_NAME "emac"
71#define DRV_VERSION "3.54"
72#define DRV_DESC "PPC 4xx OCP EMAC driver"
73
74MODULE_DESCRIPTION(DRV_DESC);
75MODULE_AUTHOR
76 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
77MODULE_LICENSE("GPL");
78
79/*
80 * PPC64 doesn't (yet) have a cacheable_memcpy
81 */
82#ifdef CONFIG_PPC64
83#define cacheable_memcpy(d,s,n) memcpy((d),(s),(n))
84#endif
85
86/* minimum number of free TX descriptors required to wake up TX process */
87#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
88
89/* If packet size is less than this number, we allocate small skb and copy packet
90 * contents into it instead of just sending original big skb up
91 */
92#define EMAC_RX_COPY_THRESH CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD
93
94/* Since multiple EMACs share MDIO lines in various ways, we need
95 * to avoid re-using the same PHY ID in cases where the arch didn't
96 * setup precise phy_map entries
97 *
98 * XXX This is something that needs to be reworked as we can have multiple
99 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
100 * probably require in that case to have explicit PHY IDs in the device-tree
101 */
102static u32 busy_phy_map;
103static DEFINE_MUTEX(emac_phy_map_lock);
104
105/* This is the wait queue used to wait on any event related to probe, that
106 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
107 */
108static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
109
110/* Having stable interface names is a doomed idea. However, it would be nice
111 * if we didn't have completely random interface names at boot too :-) It's
112 * just a matter of making everybody's life easier. Since we are doing
113 * threaded probing, it's a bit harder though. The base idea here is that
114 * we make up a list of all emacs in the device-tree before we register the
115 * driver. Every emac will then wait for the previous one in the list to
116 * initialize before itself. We should also keep that list ordered by
117 * cell_index.
118 * That list is only 4 entries long, meaning that additional EMACs don't
119 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
120 */
121
122#define EMAC_BOOT_LIST_SIZE 4
123static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
124
125/* How long should I wait for dependent devices ? */
126#define EMAC_PROBE_DEP_TIMEOUT (HZ * 5)
127
128/* I don't want to litter system log with timeout errors
129 * when we have brain-damaged PHY.
130 */
131static inline void emac_report_timeout_error(struct emac_instance *dev,
132 const char *error)
133{
11121e30 134 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
9e3cb294 135 EMAC_FTR_460EX_PHY_CLK_FIX |
11121e30
VB		 136 EMAC_FTR_440EP_PHY_CLK_FIX))
137 DBG(dev, "%s" NL, error);
138 else if (net_ratelimit())
62f0c338 139 printk(KERN_ERR "%s: %s\n", dev->ofdev->node->full_name, error);
1d3bb996
DG		 140}
141
11121e30
VB		 142/* EMAC PHY clock workaround:
143 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
144 * which allows controlling each EMAC clock
145 */
146static inline void emac_rx_clk_tx(struct emac_instance *dev)
147{
148#ifdef CONFIG_PPC_DCR_NATIVE
149 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
150 dcri_clrset(SDR0, SDR0_MFR,
151 0, SDR0_MFR_ECS >> dev->cell_index);
152#endif
153}
154
155static inline void emac_rx_clk_default(struct emac_instance *dev)
156{
157#ifdef CONFIG_PPC_DCR_NATIVE
158 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
159 dcri_clrset(SDR0, SDR0_MFR,
160 SDR0_MFR_ECS >> dev->cell_index, 0);
161#endif
162}
163
1d3bb996
DG		 164/* PHY polling intervals */
165#define PHY_POLL_LINK_ON HZ
166#define PHY_POLL_LINK_OFF (HZ / 5)
167
168/* Graceful stop timeouts in us.
169 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
170 */
171#define STOP_TIMEOUT_10 1230
172#define STOP_TIMEOUT_100 124
173#define STOP_TIMEOUT_1000 13
174#define STOP_TIMEOUT_1000_JUMBO 73
175
4373c932
PB		 176static unsigned char default_mcast_addr[] = {
177 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
178};
179
1d3bb996
DG		 180/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
181static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
182 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
183 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
184 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
185 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
186 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
187 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
188 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
189 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
190 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
191 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
192 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
193 "tx_bd_excessive_collisions", "tx_bd_late_collision",
194 "tx_bd_multple_collisions", "tx_bd_single_collision",
195 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
196 "tx_errors"
197};
198
199static irqreturn_t emac_irq(int irq, void *dev_instance);
200static void emac_clean_tx_ring(struct emac_instance *dev);
201static void __emac_set_multicast_list(struct emac_instance *dev);
202
203static inline int emac_phy_supports_gige(int phy_mode)
204{
205 return phy_mode == PHY_MODE_GMII ||
206 phy_mode == PHY_MODE_RGMII ||
9e3cb294 207 phy_mode == PHY_MODE_SGMII ||
1d3bb996
DG		 208 phy_mode == PHY_MODE_TBI ||
209 phy_mode == PHY_MODE_RTBI;
210}
211
212static inline int emac_phy_gpcs(int phy_mode)
213{
9e3cb294
VG		 214 return phy_mode == PHY_MODE_SGMII ||
215 phy_mode == PHY_MODE_TBI ||
1d3bb996
DG		 216 phy_mode == PHY_MODE_RTBI;
217}
218
219static inline void emac_tx_enable(struct emac_instance *dev)
220{
221 struct emac_regs __iomem *p = dev->emacp;
222 u32 r;
223
224 DBG(dev, "tx_enable" NL);
225
226 r = in_be32(&p->mr0);
227 if (!(r & EMAC_MR0_TXE))
228 out_be32(&p->mr0, r | EMAC_MR0_TXE);
229}
230
231static void emac_tx_disable(struct emac_instance *dev)
232{
233 struct emac_regs __iomem *p = dev->emacp;
234 u32 r;
235
236 DBG(dev, "tx_disable" NL);
237
238 r = in_be32(&p->mr0);
239 if (r & EMAC_MR0_TXE) {
240 int n = dev->stop_timeout;
241 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
242 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
243 udelay(1);
244 --n;
245 }
246 if (unlikely(!n))
247 emac_report_timeout_error(dev, "TX disable timeout");
248 }
249}
250
251static void emac_rx_enable(struct emac_instance *dev)
252{
253 struct emac_regs __iomem *p = dev->emacp;
254 u32 r;
255
256 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
257 goto out;
258
259 DBG(dev, "rx_enable" NL);
260
261 r = in_be32(&p->mr0);
262 if (!(r & EMAC_MR0_RXE)) {
263 if (unlikely(!(r & EMAC_MR0_RXI))) {
264 /* Wait if previous async disable is still in progress */
265 int n = dev->stop_timeout;
266 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
267 udelay(1);
268 --n;
269 }
270 if (unlikely(!n))
271 emac_report_timeout_error(dev,
272 "RX disable timeout");
273 }
274 out_be32(&p->mr0, r | EMAC_MR0_RXE);
275 }
276 out:
277 ;
278}
279
280static void emac_rx_disable(struct emac_instance *dev)
281{
282 struct emac_regs __iomem *p = dev->emacp;
283 u32 r;
284
285 DBG(dev, "rx_disable" NL);
286
287 r = in_be32(&p->mr0);
288 if (r & EMAC_MR0_RXE) {
289 int n = dev->stop_timeout;
290 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
291 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
292 udelay(1);
293 --n;
294 }
295 if (unlikely(!n))
296 emac_report_timeout_error(dev, "RX disable timeout");
297 }
298}
299
300static inline void emac_netif_stop(struct emac_instance *dev)
301{
302 netif_tx_lock_bh(dev->ndev);
e308a5d8 303 netif_addr_lock(dev->ndev);
1d3bb996 304 dev->no_mcast = 1;
e308a5d8 305 netif_addr_unlock(dev->ndev);
1d3bb996
DG		 306 netif_tx_unlock_bh(dev->ndev);
307 dev->ndev->trans_start = jiffies; /* prevent tx timeout */
308 mal_poll_disable(dev->mal, &dev->commac);
309 netif_tx_disable(dev->ndev);
310}
311
312static inline void emac_netif_start(struct emac_instance *dev)
313{
314 netif_tx_lock_bh(dev->ndev);
e308a5d8 315 netif_addr_lock(dev->ndev);
1d3bb996
DG		 316 dev->no_mcast = 0;
317 if (dev->mcast_pending && netif_running(dev->ndev))
318 __emac_set_multicast_list(dev);
e308a5d8 319 netif_addr_unlock(dev->ndev);
1d3bb996
DG		 320 netif_tx_unlock_bh(dev->ndev);
321
322 netif_wake_queue(dev->ndev);
323
324 /* NOTE: unconditional netif_wake_queue is only appropriate
325 * so long as all callers are assured to have free tx slots
326 * (taken from tg3... though the case where that is wrong is
327 * not terribly harmful)
328 */
329 mal_poll_enable(dev->mal, &dev->commac);
330}
331
332static inline void emac_rx_disable_async(struct emac_instance *dev)
333{
334 struct emac_regs __iomem *p = dev->emacp;
335 u32 r;
336
337 DBG(dev, "rx_disable_async" NL);
338
339 r = in_be32(&p->mr0);
340 if (r & EMAC_MR0_RXE)
341 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
342}
343
344static int emac_reset(struct emac_instance *dev)
345{
346 struct emac_regs __iomem *p = dev->emacp;
347 int n = 20;
348
349 DBG(dev, "reset" NL);
350
351 if (!dev->reset_failed) {
352 /* 40x erratum suggests stopping RX channel before reset,
353 * we stop TX as well
354 */
355 emac_rx_disable(dev);
356 emac_tx_disable(dev);
357 }
358
9e3cb294
VG		 359#ifdef CONFIG_PPC_DCR_NATIVE
360 /* Enable internal clock source */
361 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
362 dcri_clrset(SDR0, SDR0_ETH_CFG,
363 0, SDR0_ETH_CFG_ECS << dev->cell_index);
364#endif
365
1d3bb996
DG		 366 out_be32(&p->mr0, EMAC_MR0_SRST);
367 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
368 --n;
369
9e3cb294
VG		 370#ifdef CONFIG_PPC_DCR_NATIVE
371 /* Enable external clock source */
372 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
373 dcri_clrset(SDR0, SDR0_ETH_CFG,
374 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
375#endif
376
1d3bb996
DG		 377 if (n) {
378 dev->reset_failed = 0;
379 return 0;
380 } else {
381 emac_report_timeout_error(dev, "reset timeout");
382 dev->reset_failed = 1;
383 return -ETIMEDOUT;
384 }
385}
386
387static void emac_hash_mc(struct emac_instance *dev)
388{
05781ccd
GE		 389 const int regs = EMAC_XAHT_REGS(dev);
390 u32 *gaht_base = emac_gaht_base(dev);
391 u32 gaht_temp[regs];
1d3bb996 392 struct dev_mc_list *dmi;
05781ccd 393 int i;
1d3bb996 394
4cd24eaf 395 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
1d3bb996 396
05781ccd
GE		 397 memset(gaht_temp, 0, sizeof (gaht_temp));
398
48e2f183 399 netdev_for_each_mc_addr(dmi, dev->ndev) {
05781ccd 400 int slot, reg, mask;
7c510e4b 401 DBG2(dev, "mc %pM" NL, dmi->dmi_addr);
1d3bb996 402
05781ccd
GE		 403 slot = EMAC_XAHT_CRC_TO_SLOT(dev, ether_crc(ETH_ALEN, dmi->dmi_addr));
404 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
405 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
406
407 gaht_temp[reg] |= mask;
1d3bb996 408 }
05781ccd
GE		 409
410 for (i = 0; i < regs; i++)
411 out_be32(gaht_base + i, gaht_temp[i]);
1d3bb996
DG		 412}
413
414static inline u32 emac_iff2rmr(struct net_device *ndev)
415{
416 struct emac_instance *dev = netdev_priv(ndev);
417 u32 r;
418
419 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
420
421 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
422 r |= EMAC4_RMR_BASE;
423 else
424 r |= EMAC_RMR_BASE;
425
426 if (ndev->flags & IFF_PROMISC)
427 r |= EMAC_RMR_PME;
05781ccd 428 else if (ndev->flags & IFF_ALLMULTI ||
4cd24eaf 429 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
1d3bb996 430 r |= EMAC_RMR_PMME;
4cd24eaf 431 else if (!netdev_mc_empty(ndev))
1d3bb996
DG		 432 r |= EMAC_RMR_MAE;
433
434 return r;
435}
436
437static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
438{
439 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
440
441 DBG2(dev, "__emac_calc_base_mr1" NL);
442
443 switch(tx_size) {
444 case 2048:
445 ret |= EMAC_MR1_TFS_2K;
446 break;
447 default:
3201fce0 448 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
1d3bb996
DG		 449 dev->ndev->name, tx_size);
450 }
451
452 switch(rx_size) {
453 case 16384:
454 ret |= EMAC_MR1_RFS_16K;
455 break;
456 case 4096:
457 ret |= EMAC_MR1_RFS_4K;
458 break;
459 default:
460 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
461 dev->ndev->name, rx_size);
462 }
463
464 return ret;
465}
466
467static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
468{
469 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
4696c3c4 470 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
1d3bb996
DG		 471
472 DBG2(dev, "__emac4_calc_base_mr1" NL);
473
474 switch(tx_size) {
3201fce0
DM		 475 case 16384:
476 ret |= EMAC4_MR1_TFS_16K;
477 break;
1d3bb996
DG		 478 case 4096:
479 ret |= EMAC4_MR1_TFS_4K;
480 break;
481 case 2048:
482 ret |= EMAC4_MR1_TFS_2K;
483 break;
484 default:
3201fce0 485 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
1d3bb996
DG		 486 dev->ndev->name, tx_size);
487 }
488
489 switch(rx_size) {
490 case 16384:
491 ret |= EMAC4_MR1_RFS_16K;
492 break;
493 case 4096:
494 ret |= EMAC4_MR1_RFS_4K;
495 break;
496 case 2048:
497 ret |= EMAC4_MR1_RFS_2K;
498 break;
499 default:
500 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
501 dev->ndev->name, rx_size);
502 }
503
504 return ret;
505}
506
507static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
508{
509 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
510 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
511 __emac_calc_base_mr1(dev, tx_size, rx_size);
512}
513
514static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
515{
516 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
517 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
518 else
519 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
520}
521
522static inline u32 emac_calc_rwmr(struct emac_instance *dev,
523 unsigned int low, unsigned int high)
524{
525 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
526 return (low << 22) | ( (high & 0x3ff) << 6);
527 else
528 return (low << 23) | ( (high & 0x1ff) << 7);
529}
530
531static int emac_configure(struct emac_instance *dev)
532{
533 struct emac_regs __iomem *p = dev->emacp;
534 struct net_device *ndev = dev->ndev;
911b237d 535 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
1d3bb996
DG		 536 u32 r, mr1 = 0;
537
538 DBG(dev, "configure" NL);
539
911b237d
BH		 540 if (!link) {
541 out_be32(&p->mr1, in_be32(&p->mr1)
542 | EMAC_MR1_FDE | EMAC_MR1_ILE);
543 udelay(100);
544 } else if (emac_reset(dev) < 0)
1d3bb996
DG		 545 return -ETIMEDOUT;
546
547 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
548 tah_reset(dev->tah_dev);
549
911b237d
BH		 550 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
551 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
1d3bb996
DG		 552
553 /* Default fifo sizes */
554 tx_size = dev->tx_fifo_size;
555 rx_size = dev->rx_fifo_size;
556
911b237d
BH		 557 /* No link, force loopback */
558 if (!link)
559 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
560
1d3bb996 561 /* Check for full duplex */
911b237d 562 else if (dev->phy.duplex == DUPLEX_FULL)
1d3bb996
DG		 563 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
564
565 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
566 dev->stop_timeout = STOP_TIMEOUT_10;
567 switch (dev->phy.speed) {
568 case SPEED_1000:
569 if (emac_phy_gpcs(dev->phy.mode)) {
9e3cb294
VG		 570 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
571 (dev->phy.gpcs_address != 0xffffffff) ?
572 dev->phy.gpcs_address : dev->phy.address);
1d3bb996
DG		 573
574 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
575 * identify this GPCS PHY later.
576 */
05781ccd 577 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
1d3bb996
DG		 578 } else
579 mr1 |= EMAC_MR1_MF_1000;
580
581 /* Extended fifo sizes */
582 tx_size = dev->tx_fifo_size_gige;
583 rx_size = dev->rx_fifo_size_gige;
584
585 if (dev->ndev->mtu > ETH_DATA_LEN) {
f34ebab6
SR		 586 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
587 mr1 |= EMAC4_MR1_JPSM;
588 else
589 mr1 |= EMAC_MR1_JPSM;
1d3bb996
DG		 590 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
591 } else
592 dev->stop_timeout = STOP_TIMEOUT_1000;
593 break;
594 case SPEED_100:
595 mr1 |= EMAC_MR1_MF_100;
596 dev->stop_timeout = STOP_TIMEOUT_100;
597 break;
598 default: /* make gcc happy */
599 break;
600 }
601
602 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
603 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
604 dev->phy.speed);
605 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
606 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
607
608 /* on 40x erratum forces us to NOT use integrated flow control,
609 * let's hope it works on 44x ;)
610 */
611 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
612 dev->phy.duplex == DUPLEX_FULL) {
613 if (dev->phy.pause)
614 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
615 else if (dev->phy.asym_pause)
616 mr1 |= EMAC_MR1_APP;
617 }
618
619 /* Add base settings & fifo sizes & program MR1 */
620 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
621 out_be32(&p->mr1, mr1);
622
623 /* Set individual MAC address */
624 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
625 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
626 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
627 ndev->dev_addr[5]);
628
629 /* VLAN Tag Protocol ID */
630 out_be32(&p->vtpid, 0x8100);
631
632 /* Receive mode register */
633 r = emac_iff2rmr(ndev);
634 if (r & EMAC_RMR_MAE)
635 emac_hash_mc(dev);
636 out_be32(&p->rmr, r);
637
638 /* FIFOs thresholds */
639 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
640 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
641 tx_size / 2 / dev->fifo_entry_size);
642 else
643 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
644 tx_size / 2 / dev->fifo_entry_size);
645 out_be32(&p->tmr1, r);
646 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
647
648 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
649 there should be still enough space in FIFO to allow the our link
650 partner time to process this frame and also time to send PAUSE
651 frame itself.
652
653 Here is the worst case scenario for the RX FIFO "headroom"
654 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
655
656 1) One maximum-length frame on TX 1522 bytes
657 2) One PAUSE frame time 64 bytes
658 3) PAUSE frame decode time allowance 64 bytes
659 4) One maximum-length frame on RX 1522 bytes
660 5) Round-trip propagation delay of the link (100Mb) 15 bytes
661 ----------
662 3187 bytes
663
664 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
665 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
666 */
667 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
668 rx_size / 4 / dev->fifo_entry_size);
669 out_be32(&p->rwmr, r);
670
671 /* Set PAUSE timer to the maximum */
672 out_be32(&p->ptr, 0xffff);
673
674 /* IRQ sources */
675 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
676 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
677 EMAC_ISR_IRE | EMAC_ISR_TE;
678 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
679 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
680 EMAC4_ISR_RXOE | */;
681 out_be32(&p->iser, r);
682
683 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
9e3cb294
VG		 684 if (emac_phy_gpcs(dev->phy.mode)) {
685 if (dev->phy.gpcs_address != 0xffffffff)
686 emac_mii_reset_gpcs(&dev->phy);
687 else
688 emac_mii_reset_phy(&dev->phy);
689 }
1d3bb996
DG		 690
691 return 0;
692}
693
694static void emac_reinitialize(struct emac_instance *dev)
695{
696 DBG(dev, "reinitialize" NL);
697
698 emac_netif_stop(dev);
699 if (!emac_configure(dev)) {
700 emac_tx_enable(dev);
701 emac_rx_enable(dev);
702 }
703 emac_netif_start(dev);
704}
705
706static void emac_full_tx_reset(struct emac_instance *dev)
707{
708 DBG(dev, "full_tx_reset" NL);
709
710 emac_tx_disable(dev);
711 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
712 emac_clean_tx_ring(dev);
713 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
714
715 emac_configure(dev);
716
717 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
718 emac_tx_enable(dev);
719 emac_rx_enable(dev);
720}
721
722static void emac_reset_work(struct work_struct *work)
723{
724 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
725
726 DBG(dev, "reset_work" NL);
727
728 mutex_lock(&dev->link_lock);
61dbcece
BH		 729 if (dev->opened) {
730 emac_netif_stop(dev);
731 emac_full_tx_reset(dev);
732 emac_netif_start(dev);
733 }
1d3bb996
DG		 734 mutex_unlock(&dev->link_lock);
735}
736
737static void emac_tx_timeout(struct net_device *ndev)
738{
739 struct emac_instance *dev = netdev_priv(ndev);
740
741 DBG(dev, "tx_timeout" NL);
742
743 schedule_work(&dev->reset_work);
744}
745
746
747static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
748{
749 int done = !!(stacr & EMAC_STACR_OC);
750
751 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
752 done = !done;
753
754 return done;
755};
756
757static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
758{
759 struct emac_regs __iomem *p = dev->emacp;
760 u32 r = 0;
761 int n, err = -ETIMEDOUT;
762
763 mutex_lock(&dev->mdio_lock);
764
765 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
766
767 /* Enable proper MDIO port */
768 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
769 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
770 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
771 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
772
773 /* Wait for management interface to become idle */
cca87c18 774 n = 20;
1d3bb996
DG		 775 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
776 udelay(1);
777 if (!--n) {
778 DBG2(dev, " -> timeout wait idle\n");
779 goto bail;
780 }
781 }
782
783 /* Issue read command */
784 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
785 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
786 else
787 r = EMAC_STACR_BASE(dev->opb_bus_freq);
788 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
789 r |= EMAC_STACR_OC;
bff713b5 790 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
1d3bb996
DG		 791 r |= EMACX_STACR_STAC_READ;
792 else
793 r |= EMAC_STACR_STAC_READ;
794 r |= (reg & EMAC_STACR_PRA_MASK)
795 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
796 out_be32(&p->stacr, r);
797
798 /* Wait for read to complete */
cca87c18 799 n = 200;
1d3bb996
DG		 800 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
801 udelay(1);
802 if (!--n) {
803 DBG2(dev, " -> timeout wait complete\n");
804 goto bail;
805 }
806 }
807
808 if (unlikely(r & EMAC_STACR_PHYE)) {
809 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
810 err = -EREMOTEIO;
811 goto bail;
812 }
813
814 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
815
816 DBG2(dev, "mdio_read -> %04x" NL, r);
817 err = 0;
818 bail:
819 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
820 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
821 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
822 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
823 mutex_unlock(&dev->mdio_lock);
824
825 return err == 0 ? r : err;
826}
827
828static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
829 u16 val)
830{
831 struct emac_regs __iomem *p = dev->emacp;
832 u32 r = 0;
833 int n, err = -ETIMEDOUT;
834
835 mutex_lock(&dev->mdio_lock);
836
837 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
838
839 /* Enable proper MDIO port */
840 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
841 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
842 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
843 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
844
845 /* Wait for management interface to be idle */
cca87c18 846 n = 20;
1d3bb996
DG		 847 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
848 udelay(1);
849 if (!--n) {
850 DBG2(dev, " -> timeout wait idle\n");
851 goto bail;
852 }
853 }
854
855 /* Issue write command */
856 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
857 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
858 else
859 r = EMAC_STACR_BASE(dev->opb_bus_freq);
860 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
861 r |= EMAC_STACR_OC;
bff713b5 862 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
1d3bb996
DG		 863 r |= EMACX_STACR_STAC_WRITE;
864 else
865 r |= EMAC_STACR_STAC_WRITE;
866 r |= (reg & EMAC_STACR_PRA_MASK) |
867 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
868 (val << EMAC_STACR_PHYD_SHIFT);
869 out_be32(&p->stacr, r);
870
871 /* Wait for write to complete */
cca87c18 872 n = 200;
1d3bb996
DG		 873 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
874 udelay(1);
875 if (!--n) {
876 DBG2(dev, " -> timeout wait complete\n");
877 goto bail;
878 }
879 }
880 err = 0;
881 bail:
882 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
883 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
884 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
885 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
886 mutex_unlock(&dev->mdio_lock);
887}
888
889static int emac_mdio_read(struct net_device *ndev, int id, int reg)
890{
891 struct emac_instance *dev = netdev_priv(ndev);
892 int res;
893
9e3cb294
VG		 894 res = __emac_mdio_read((dev->mdio_instance &&
895 dev->phy.gpcs_address != id) ?
896 dev->mdio_instance : dev,
1d3bb996
DG		 897 (u8) id, (u8) reg);
898 return res;
899}
900
901static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
902{
903 struct emac_instance *dev = netdev_priv(ndev);
904
9e3cb294
VG		 905 __emac_mdio_write((dev->mdio_instance &&
906 dev->phy.gpcs_address != id) ?
907 dev->mdio_instance : dev,
1d3bb996
DG		 908 (u8) id, (u8) reg, (u16) val);
909}
910
911/* Tx lock BH */
912static void __emac_set_multicast_list(struct emac_instance *dev)
913{
914 struct emac_regs __iomem *p = dev->emacp;
915 u32 rmr = emac_iff2rmr(dev->ndev);
916
917 DBG(dev, "__multicast %08x" NL, rmr);
918
919 /* I decided to relax register access rules here to avoid
920 * full EMAC reset.
921 *
922 * There is a real problem with EMAC4 core if we use MWSW_001 bit
923 * in MR1 register and do a full EMAC reset.
924 * One TX BD status update is delayed and, after EMAC reset, it
925 * never happens, resulting in TX hung (it'll be recovered by TX
926 * timeout handler eventually, but this is just gross).
927 * So we either have to do full TX reset or try to cheat here :)
928 *
929 * The only required change is to RX mode register, so I *think* all
930 * we need is just to stop RX channel. This seems to work on all
931 * tested SoCs. --ebs
932 *
933 * If we need the full reset, we might just trigger the workqueue
934 * and do it async... a bit nasty but should work --BenH
935 */
936 dev->mcast_pending = 0;
937 emac_rx_disable(dev);
938 if (rmr & EMAC_RMR_MAE)
939 emac_hash_mc(dev);
940 out_be32(&p->rmr, rmr);
941 emac_rx_enable(dev);
942}
943
944/* Tx lock BH */
945static void emac_set_multicast_list(struct net_device *ndev)
946{
947 struct emac_instance *dev = netdev_priv(ndev);
948
949 DBG(dev, "multicast" NL);
950
951 BUG_ON(!netif_running(dev->ndev));
952
953 if (dev->no_mcast) {
954 dev->mcast_pending = 1;
955 return;
956 }
957 __emac_set_multicast_list(dev);
958}
959
960static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
961{
962 int rx_sync_size = emac_rx_sync_size(new_mtu);
963 int rx_skb_size = emac_rx_skb_size(new_mtu);
964 int i, ret = 0;
965
966 mutex_lock(&dev->link_lock);
967 emac_netif_stop(dev);
968 emac_rx_disable(dev);
969 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
970
971 if (dev->rx_sg_skb) {
972 ++dev->estats.rx_dropped_resize;
973 dev_kfree_skb(dev->rx_sg_skb);
974 dev->rx_sg_skb = NULL;
975 }
976
977 /* Make a first pass over RX ring and mark BDs ready, dropping
978 * non-processed packets on the way. We need this as a separate pass
979 * to simplify error recovery in the case of allocation failure later.
980 */
981 for (i = 0; i < NUM_RX_BUFF; ++i) {
982 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
983 ++dev->estats.rx_dropped_resize;
984
985 dev->rx_desc[i].data_len = 0;
986 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
987 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
988 }
989
990 /* Reallocate RX ring only if bigger skb buffers are required */
991 if (rx_skb_size <= dev->rx_skb_size)
992 goto skip;
993
994 /* Second pass, allocate new skbs */
995 for (i = 0; i < NUM_RX_BUFF; ++i) {
996 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
997 if (!skb) {
998 ret = -ENOMEM;
999 goto oom;
1000 }
1001
1002 BUG_ON(!dev->rx_skb[i]);
1003 dev_kfree_skb(dev->rx_skb[i]);
1004
1005 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1006 dev->rx_desc[i].data_ptr =
1007 dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size,
1008 DMA_FROM_DEVICE) + 2;
1009 dev->rx_skb[i] = skb;
1010 }
1011 skip:
1012 /* Check if we need to change "Jumbo" bit in MR1 */
1013 if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
1014 /* This is to prevent starting RX channel in emac_rx_enable() */
1015 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1016
1017 dev->ndev->mtu = new_mtu;
1018 emac_full_tx_reset(dev);
1019 }
1020
1021 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1022 oom:
1023 /* Restart RX */
1024 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1025 dev->rx_slot = 0;
1026 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1027 emac_rx_enable(dev);
1028 emac_netif_start(dev);
1029 mutex_unlock(&dev->link_lock);
1030
1031 return ret;
1032}
1033
1034/* Process ctx, rtnl_lock semaphore */
1035static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1036{
1037 struct emac_instance *dev = netdev_priv(ndev);
1038 int ret = 0;
1039
1040 if (new_mtu < EMAC_MIN_MTU || new_mtu > dev->max_mtu)
1041 return -EINVAL;
1042
1043 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1044
1045 if (netif_running(ndev)) {
1046 /* Check if we really need to reinitalize RX ring */
1047 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1048 ret = emac_resize_rx_ring(dev, new_mtu);
1049 }
1050
1051 if (!ret) {
1052 ndev->mtu = new_mtu;
1053 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1054 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1055 }
1056
1057 return ret;
1058}
1059
1060static void emac_clean_tx_ring(struct emac_instance *dev)
1061{
1062 int i;
1063
1064 for (i = 0; i < NUM_TX_BUFF; ++i) {
1065 if (dev->tx_skb[i]) {
1066 dev_kfree_skb(dev->tx_skb[i]);
1067 dev->tx_skb[i] = NULL;
1068 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1069 ++dev->estats.tx_dropped;
1070 }
1071 dev->tx_desc[i].ctrl = 0;
1072 dev->tx_desc[i].data_ptr = 0;
1073 }
1074}
1075
1076static void emac_clean_rx_ring(struct emac_instance *dev)
1077{
1078 int i;
1079
1080 for (i = 0; i < NUM_RX_BUFF; ++i)
1081 if (dev->rx_skb[i]) {
1082 dev->rx_desc[i].ctrl = 0;
1083 dev_kfree_skb(dev->rx_skb[i]);
1084 dev->rx_skb[i] = NULL;
1085 dev->rx_desc[i].data_ptr = 0;
1086 }
1087
1088 if (dev->rx_sg_skb) {
1089 dev_kfree_skb(dev->rx_sg_skb);
1090 dev->rx_sg_skb = NULL;
1091 }
1092}
1093
1094static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot,
1095 gfp_t flags)
1096{
1097 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
1098 if (unlikely(!skb))
1099 return -ENOMEM;
1100
1101 dev->rx_skb[slot] = skb;
1102 dev->rx_desc[slot].data_len = 0;
1103
1104 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1105 dev->rx_desc[slot].data_ptr =
1106 dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size,
1107 DMA_FROM_DEVICE) + 2;
1108 wmb();
1109 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1110 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1111
1112 return 0;
1113}
1114
1115static void emac_print_link_status(struct emac_instance *dev)
1116{
1117 if (netif_carrier_ok(dev->ndev))
1118 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1119 dev->ndev->name, dev->phy.speed,
1120 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1121 dev->phy.pause ? ", pause enabled" :
1122 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1123 else
1124 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1125}
1126
1127/* Process ctx, rtnl_lock semaphore */
1128static int emac_open(struct net_device *ndev)
1129{
1130 struct emac_instance *dev = netdev_priv(ndev);
1131 int err, i;
1132
1133 DBG(dev, "open" NL);
1134
1135 /* Setup error IRQ handler */
1136 err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1137 if (err) {
1138 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1139 ndev->name, dev->emac_irq);
1140 return err;
1141 }
1142
1143 /* Allocate RX ring */
1144 for (i = 0; i < NUM_RX_BUFF; ++i)
1145 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
1146 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1147 ndev->name);
1148 goto oom;
1149 }
1150
1151 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1152 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1153 dev->rx_sg_skb = NULL;
1154
1155 mutex_lock(&dev->link_lock);
61dbcece 1156 dev->opened = 1;
1d3bb996 1157
61dbcece 1158 /* Start PHY polling now.
1d3bb996
DG		 1159 */
1160 if (dev->phy.address >= 0) {
1161 int link_poll_interval;
1162 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1163 dev->phy.def->ops->read_link(&dev->phy);
11121e30 1164 emac_rx_clk_default(dev);
1d3bb996
DG		 1165 netif_carrier_on(dev->ndev);
1166 link_poll_interval = PHY_POLL_LINK_ON;
1167 } else {
11121e30 1168 emac_rx_clk_tx(dev);
1d3bb996
DG		 1169 netif_carrier_off(dev->ndev);
1170 link_poll_interval = PHY_POLL_LINK_OFF;
1171 }
1172 dev->link_polling = 1;
1173 wmb();
1174 schedule_delayed_work(&dev->link_work, link_poll_interval);
1175 emac_print_link_status(dev);
1176 } else
1177 netif_carrier_on(dev->ndev);
1178
e8296582
BH		 1179 /* Required for Pause packet support in EMAC */
1180 dev_mc_add(ndev, default_mcast_addr, sizeof(default_mcast_addr), 1);
1181
1d3bb996
DG		 1182 emac_configure(dev);
1183 mal_poll_add(dev->mal, &dev->commac);
1184 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1185 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1186 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1187 emac_tx_enable(dev);
1188 emac_rx_enable(dev);
1189 emac_netif_start(dev);
1190
1191 mutex_unlock(&dev->link_lock);
1192
1193 return 0;
1194 oom:
1195 emac_clean_rx_ring(dev);
1196 free_irq(dev->emac_irq, dev);
1197
1198 return -ENOMEM;
1199}
1200
1201/* BHs disabled */
1202#if 0
1203static int emac_link_differs(struct emac_instance *dev)
1204{
1205 u32 r = in_be32(&dev->emacp->mr1);
1206
1207 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1208 int speed, pause, asym_pause;
1209
1210 if (r & EMAC_MR1_MF_1000)
1211 speed = SPEED_1000;
1212 else if (r & EMAC_MR1_MF_100)
1213 speed = SPEED_100;
1214 else
1215 speed = SPEED_10;
1216
1217 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1218 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1219 pause = 1;
1220 asym_pause = 0;
1221 break;
1222 case EMAC_MR1_APP:
1223 pause = 0;
1224 asym_pause = 1;
1225 break;
1226 default:
1227 pause = asym_pause = 0;
1228 }
1229 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1230 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1231}
1232#endif
1233
1234static void emac_link_timer(struct work_struct *work)
1235{
1236 struct emac_instance *dev =
10fd9d7e 1237 container_of(to_delayed_work(work),
1d3bb996
DG		 1238 struct emac_instance, link_work);
1239 int link_poll_interval;
1240
1241 mutex_lock(&dev->link_lock);
1d3bb996
DG		 1242 DBG2(dev, "link timer" NL);
1243
61dbcece
BH		 1244 if (!dev->opened)
1245 goto bail;
1246
1d3bb996
DG		 1247 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1248 if (!netif_carrier_ok(dev->ndev)) {
11121e30 1249 emac_rx_clk_default(dev);
1d3bb996
DG		 1250 /* Get new link parameters */
1251 dev->phy.def->ops->read_link(&dev->phy);
1252
1253 netif_carrier_on(dev->ndev);
1254 emac_netif_stop(dev);
1255 emac_full_tx_reset(dev);
1256 emac_netif_start(dev);
1257 emac_print_link_status(dev);
1258 }
1259 link_poll_interval = PHY_POLL_LINK_ON;
1260 } else {
1261 if (netif_carrier_ok(dev->ndev)) {
11121e30 1262 emac_rx_clk_tx(dev);
1d3bb996
DG		 1263 netif_carrier_off(dev->ndev);
1264 netif_tx_disable(dev->ndev);
911b237d 1265 emac_reinitialize(dev);
1d3bb996
DG		 1266 emac_print_link_status(dev);
1267 }
1268 link_poll_interval = PHY_POLL_LINK_OFF;
1269 }
1270 schedule_delayed_work(&dev->link_work, link_poll_interval);
61dbcece 1271 bail:
1d3bb996
DG		 1272 mutex_unlock(&dev->link_lock);
1273}
1274
1275static void emac_force_link_update(struct emac_instance *dev)
1276{
1277 netif_carrier_off(dev->ndev);
61dbcece 1278 smp_rmb();
1d3bb996
DG		 1279 if (dev->link_polling) {
1280 cancel_rearming_delayed_work(&dev->link_work);
1281 if (dev->link_polling)
1282 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1283 }
1284}
1285
1286/* Process ctx, rtnl_lock semaphore */
1287static int emac_close(struct net_device *ndev)
1288{
1289 struct emac_instance *dev = netdev_priv(ndev);
1290
1291 DBG(dev, "close" NL);
1292
61dbcece
BH		 1293 if (dev->phy.address >= 0) {
1294 dev->link_polling = 0;
1d3bb996 1295 cancel_rearming_delayed_work(&dev->link_work);
61dbcece
BH		 1296 }
1297 mutex_lock(&dev->link_lock);
1d3bb996 1298 emac_netif_stop(dev);
61dbcece
BH		 1299 dev->opened = 0;
1300 mutex_unlock(&dev->link_lock);
1d3bb996
DG		 1301
1302 emac_rx_disable(dev);
1303 emac_tx_disable(dev);
1304 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1305 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1306 mal_poll_del(dev->mal, &dev->commac);
1307
1308 emac_clean_tx_ring(dev);
1309 emac_clean_rx_ring(dev);
1310
1311 free_irq(dev->emac_irq, dev);
1312
d3b325f9
PG		 1313 netif_carrier_off(ndev);
1314
1d3bb996
DG		 1315 return 0;
1316}
1317
1318static inline u16 emac_tx_csum(struct emac_instance *dev,
1319 struct sk_buff *skb)
1320{
e66f4168
VB		 1321 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1322 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1d3bb996
DG		 1323 ++dev->stats.tx_packets_csum;
1324 return EMAC_TX_CTRL_TAH_CSUM;
1325 }
1326 return 0;
1327}
1328
1329static inline int emac_xmit_finish(struct emac_instance *dev, int len)
1330{
1331 struct emac_regs __iomem *p = dev->emacp;
1332 struct net_device *ndev = dev->ndev;
1333
1334 /* Send the packet out. If the if makes a significant perf
1335 * difference, then we can store the TMR0 value in "dev"
1336 * instead
1337 */
1338 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1d3bb996 1339 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
07c2c76e 1340 else
1341 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1d3bb996
DG		 1342
1343 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1344 netif_stop_queue(ndev);
1345 DBG2(dev, "stopped TX queue" NL);
1346 }
1347
1348 ndev->trans_start = jiffies;
1349 ++dev->stats.tx_packets;
1350 dev->stats.tx_bytes += len;
1351
ec634fe3 1352 return NETDEV_TX_OK;
1d3bb996
DG		 1353}
1354
1355/* Tx lock BH */
1356static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1357{
1358 struct emac_instance *dev = netdev_priv(ndev);
1359 unsigned int len = skb->len;
1360 int slot;
1361
1362 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1363 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1364
1365 slot = dev->tx_slot++;
1366 if (dev->tx_slot == NUM_TX_BUFF) {
1367 dev->tx_slot = 0;
1368 ctrl |= MAL_TX_CTRL_WRAP;
1369 }
1370
1371 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1372
1373 dev->tx_skb[slot] = skb;
1374 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1375 skb->data, len,
1376 DMA_TO_DEVICE);
1377 dev->tx_desc[slot].data_len = (u16) len;
1378 wmb();
1379 dev->tx_desc[slot].ctrl = ctrl;
1380
1381 return emac_xmit_finish(dev, len);
1382}
1383
1d3bb996
DG		 1384static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1385 u32 pd, int len, int last, u16 base_ctrl)
1386{
1387 while (1) {
1388 u16 ctrl = base_ctrl;
1389 int chunk = min(len, MAL_MAX_TX_SIZE);
1390 len -= chunk;
1391
1392 slot = (slot + 1) % NUM_TX_BUFF;
1393
1394 if (last && !len)
1395 ctrl |= MAL_TX_CTRL_LAST;
1396 if (slot == NUM_TX_BUFF - 1)
1397 ctrl |= MAL_TX_CTRL_WRAP;
1398
1399 dev->tx_skb[slot] = NULL;
1400 dev->tx_desc[slot].data_ptr = pd;
1401 dev->tx_desc[slot].data_len = (u16) chunk;
1402 dev->tx_desc[slot].ctrl = ctrl;
1403 ++dev->tx_cnt;
1404
1405 if (!len)
1406 break;
1407
1408 pd += chunk;
1409 }
1410 return slot;
1411}
1412
1413/* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1414static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1415{
1416 struct emac_instance *dev = netdev_priv(ndev);
1417 int nr_frags = skb_shinfo(skb)->nr_frags;
1418 int len = skb->len, chunk;
1419 int slot, i;
1420 u16 ctrl;
1421 u32 pd;
1422
1423 /* This is common "fast" path */
1424 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1425 return emac_start_xmit(skb, ndev);
1426
1427 len -= skb->data_len;
1428
1429 /* Note, this is only an *estimation*, we can still run out of empty
1430 * slots because of the additional fragmentation into
1431 * MAL_MAX_TX_SIZE-sized chunks
1432 */
1433 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1434 goto stop_queue;
1435
1436 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1437 emac_tx_csum(dev, skb);
1438 slot = dev->tx_slot;
1439
1440 /* skb data */
1441 dev->tx_skb[slot] = NULL;
1442 chunk = min(len, MAL_MAX_TX_SIZE);
1443 dev->tx_desc[slot].data_ptr = pd =
1444 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1445 dev->tx_desc[slot].data_len = (u16) chunk;
1446 len -= chunk;
1447 if (unlikely(len))
1448 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1449 ctrl);
1450 /* skb fragments */
1451 for (i = 0; i < nr_frags; ++i) {
1452 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1453 len = frag->size;
1454
1455 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1456 goto undo_frame;
1457
1458 pd = dma_map_page(&dev->ofdev->dev, frag->page, frag->page_offset, len,
1459 DMA_TO_DEVICE);
1460
1461 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1462 ctrl);
1463 }
1464
1465 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1466
1467 /* Attach skb to the last slot so we don't release it too early */
1468 dev->tx_skb[slot] = skb;
1469
1470 /* Send the packet out */
1471 if (dev->tx_slot == NUM_TX_BUFF - 1)
1472 ctrl |= MAL_TX_CTRL_WRAP;
1473 wmb();
1474 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1475 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1476
1477 return emac_xmit_finish(dev, skb->len);
1478
1479 undo_frame:
1480 /* Well, too bad. Our previous estimation was overly optimistic.
1481 * Undo everything.
1482 */
1483 while (slot != dev->tx_slot) {
1484 dev->tx_desc[slot].ctrl = 0;
1485 --dev->tx_cnt;
1486 if (--slot < 0)
1487 slot = NUM_TX_BUFF - 1;
1488 }
1489 ++dev->estats.tx_undo;
1490
1491 stop_queue:
1492 netif_stop_queue(ndev);
1493 DBG2(dev, "stopped TX queue" NL);
5b548140 1494 return NETDEV_TX_BUSY;
1d3bb996 1495}
1d3bb996
DG		 1496
1497/* Tx lock BHs */
1498static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1499{
1500 struct emac_error_stats *st = &dev->estats;
1501
1502 DBG(dev, "BD TX error %04x" NL, ctrl);
1503
1504 ++st->tx_bd_errors;
1505 if (ctrl & EMAC_TX_ST_BFCS)
1506 ++st->tx_bd_bad_fcs;
1507 if (ctrl & EMAC_TX_ST_LCS)
1508 ++st->tx_bd_carrier_loss;
1509 if (ctrl & EMAC_TX_ST_ED)
1510 ++st->tx_bd_excessive_deferral;
1511 if (ctrl & EMAC_TX_ST_EC)
1512 ++st->tx_bd_excessive_collisions;
1513 if (ctrl & EMAC_TX_ST_LC)
1514 ++st->tx_bd_late_collision;
1515 if (ctrl & EMAC_TX_ST_MC)
1516 ++st->tx_bd_multple_collisions;
1517 if (ctrl & EMAC_TX_ST_SC)
1518 ++st->tx_bd_single_collision;
1519 if (ctrl & EMAC_TX_ST_UR)
1520 ++st->tx_bd_underrun;
1521 if (ctrl & EMAC_TX_ST_SQE)
1522 ++st->tx_bd_sqe;
1523}
1524
1525static void emac_poll_tx(void *param)
1526{
1527 struct emac_instance *dev = param;
1528 u32 bad_mask;
1529
1530 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1531
1532 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1533 bad_mask = EMAC_IS_BAD_TX_TAH;
1534 else
1535 bad_mask = EMAC_IS_BAD_TX;
1536
1537 netif_tx_lock_bh(dev->ndev);
1538 if (dev->tx_cnt) {
1539 u16 ctrl;
1540 int slot = dev->ack_slot, n = 0;
1541 again:
1542 ctrl = dev->tx_desc[slot].ctrl;
1543 if (!(ctrl & MAL_TX_CTRL_READY)) {
1544 struct sk_buff *skb = dev->tx_skb[slot];
1545 ++n;
1546
1547 if (skb) {
1548 dev_kfree_skb(skb);
1549 dev->tx_skb[slot] = NULL;
1550 }
1551 slot = (slot + 1) % NUM_TX_BUFF;
1552
1553 if (unlikely(ctrl & bad_mask))
1554 emac_parse_tx_error(dev, ctrl);
1555
1556 if (--dev->tx_cnt)
1557 goto again;
1558 }
1559 if (n) {
1560 dev->ack_slot = slot;
1561 if (netif_queue_stopped(dev->ndev) &&
1562 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1563 netif_wake_queue(dev->ndev);
1564
1565 DBG2(dev, "tx %d pkts" NL, n);
1566 }
1567 }
1568 netif_tx_unlock_bh(dev->ndev);
1569}
1570
1571static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1572 int len)
1573{
1574 struct sk_buff *skb = dev->rx_skb[slot];
1575
1576 DBG2(dev, "recycle %d %d" NL, slot, len);
1577
1578 if (len)
1579 dma_map_single(&dev->ofdev->dev, skb->data - 2,
1580 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1581
1582 dev->rx_desc[slot].data_len = 0;
1583 wmb();
1584 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1585 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1586}
1587
1588static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1589{
1590 struct emac_error_stats *st = &dev->estats;
1591
1592 DBG(dev, "BD RX error %04x" NL, ctrl);
1593
1594 ++st->rx_bd_errors;
1595 if (ctrl & EMAC_RX_ST_OE)
1596 ++st->rx_bd_overrun;
1597 if (ctrl & EMAC_RX_ST_BP)
1598 ++st->rx_bd_bad_packet;
1599 if (ctrl & EMAC_RX_ST_RP)
1600 ++st->rx_bd_runt_packet;
1601 if (ctrl & EMAC_RX_ST_SE)
1602 ++st->rx_bd_short_event;
1603 if (ctrl & EMAC_RX_ST_AE)
1604 ++st->rx_bd_alignment_error;
1605 if (ctrl & EMAC_RX_ST_BFCS)
1606 ++st->rx_bd_bad_fcs;
1607 if (ctrl & EMAC_RX_ST_PTL)
1608 ++st->rx_bd_packet_too_long;
1609 if (ctrl & EMAC_RX_ST_ORE)
1610 ++st->rx_bd_out_of_range;
1611 if (ctrl & EMAC_RX_ST_IRE)
1612 ++st->rx_bd_in_range;
1613}
1614
1615static inline void emac_rx_csum(struct emac_instance *dev,
1616 struct sk_buff *skb, u16 ctrl)
1617{
1618#ifdef CONFIG_IBM_NEW_EMAC_TAH
1619 if (!ctrl && dev->tah_dev) {
1620 skb->ip_summed = CHECKSUM_UNNECESSARY;
1621 ++dev->stats.rx_packets_csum;
1622 }
1623#endif
1624}
1625
1626static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1627{
1628 if (likely(dev->rx_sg_skb != NULL)) {
1629 int len = dev->rx_desc[slot].data_len;
1630 int tot_len = dev->rx_sg_skb->len + len;
1631
1632 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1633 ++dev->estats.rx_dropped_mtu;
1634 dev_kfree_skb(dev->rx_sg_skb);
1635 dev->rx_sg_skb = NULL;
1636 } else {
bef1bc95 1637 cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
1d3bb996
DG		 1638 dev->rx_skb[slot]->data, len);
1639 skb_put(dev->rx_sg_skb, len);
1640 emac_recycle_rx_skb(dev, slot, len);
1641 return 0;
1642 }
1643 }
1644 emac_recycle_rx_skb(dev, slot, 0);
1645 return -1;
1646}
1647
1648/* NAPI poll context */
1649static int emac_poll_rx(void *param, int budget)
1650{
1651 struct emac_instance *dev = param;
1652 int slot = dev->rx_slot, received = 0;
1653
1654 DBG2(dev, "poll_rx(%d)" NL, budget);
1655
1656 again:
1657 while (budget > 0) {
1658 int len;
1659 struct sk_buff *skb;
1660 u16 ctrl = dev->rx_desc[slot].ctrl;
1661
1662 if (ctrl & MAL_RX_CTRL_EMPTY)
1663 break;
1664
1665 skb = dev->rx_skb[slot];
1666 mb();
1667 len = dev->rx_desc[slot].data_len;
1668
1669 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1670 goto sg;
1671
1672 ctrl &= EMAC_BAD_RX_MASK;
1673 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1674 emac_parse_rx_error(dev, ctrl);
1675 ++dev->estats.rx_dropped_error;
1676 emac_recycle_rx_skb(dev, slot, 0);
1677 len = 0;
1678 goto next;
1679 }
6c688f42
SN		 1680
1681 if (len < ETH_HLEN) {
1682 ++dev->estats.rx_dropped_stack;
1683 emac_recycle_rx_skb(dev, slot, len);
1684 goto next;
1685 }
1d3bb996
DG		 1686
1687 if (len && len < EMAC_RX_COPY_THRESH) {
1688 struct sk_buff *copy_skb =
1689 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1690 if (unlikely(!copy_skb))
1691 goto oom;
1692
1693 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1694 cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1695 len + 2);
1696 emac_recycle_rx_skb(dev, slot, len);
1697 skb = copy_skb;
1698 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1699 goto oom;
1700
1701 skb_put(skb, len);
1702 push_packet:
1703 skb->dev = dev->ndev;
1704 skb->protocol = eth_type_trans(skb, dev->ndev);
1705 emac_rx_csum(dev, skb, ctrl);
1706
1707 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1708 ++dev->estats.rx_dropped_stack;
1709 next:
1710 ++dev->stats.rx_packets;
1711 skip:
1712 dev->stats.rx_bytes += len;
1713 slot = (slot + 1) % NUM_RX_BUFF;
1714 --budget;
1715 ++received;
1716 continue;
1717 sg:
1718 if (ctrl & MAL_RX_CTRL_FIRST) {
1719 BUG_ON(dev->rx_sg_skb);
1720 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1721 DBG(dev, "rx OOM %d" NL, slot);
1722 ++dev->estats.rx_dropped_oom;
1723 emac_recycle_rx_skb(dev, slot, 0);
1724 } else {
1725 dev->rx_sg_skb = skb;
1726 skb_put(skb, len);
1727 }
1728 } else if (!emac_rx_sg_append(dev, slot) &&
1729 (ctrl & MAL_RX_CTRL_LAST)) {
1730
1731 skb = dev->rx_sg_skb;
1732 dev->rx_sg_skb = NULL;
1733
1734 ctrl &= EMAC_BAD_RX_MASK;
1735 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1736 emac_parse_rx_error(dev, ctrl);
1737 ++dev->estats.rx_dropped_error;
1738 dev_kfree_skb(skb);
1739 len = 0;
1740 } else
1741 goto push_packet;
1742 }
1743 goto skip;
1744 oom:
1745 DBG(dev, "rx OOM %d" NL, slot);
1746 /* Drop the packet and recycle skb */
1747 ++dev->estats.rx_dropped_oom;
1748 emac_recycle_rx_skb(dev, slot, 0);
1749 goto next;
1750 }
1751
1752 if (received) {
1753 DBG2(dev, "rx %d BDs" NL, received);
1754 dev->rx_slot = slot;
1755 }
1756
1757 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1758 mb();
1759 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1760 DBG2(dev, "rx restart" NL);
1761 received = 0;
1762 goto again;
1763 }
1764
1765 if (dev->rx_sg_skb) {
1766 DBG2(dev, "dropping partial rx packet" NL);
1767 ++dev->estats.rx_dropped_error;
1768 dev_kfree_skb(dev->rx_sg_skb);
1769 dev->rx_sg_skb = NULL;
1770 }
1771
1772 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1773 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1774 emac_rx_enable(dev);
1775 dev->rx_slot = 0;
1776 }
1777 return received;
1778}
1779
1780/* NAPI poll context */
1781static int emac_peek_rx(void *param)
1782{
1783 struct emac_instance *dev = param;
1784
1785 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1786}
1787
1788/* NAPI poll context */
1789static int emac_peek_rx_sg(void *param)
1790{
1791 struct emac_instance *dev = param;
1792
1793 int slot = dev->rx_slot;
1794 while (1) {
1795 u16 ctrl = dev->rx_desc[slot].ctrl;
1796 if (ctrl & MAL_RX_CTRL_EMPTY)
1797 return 0;
1798 else if (ctrl & MAL_RX_CTRL_LAST)
1799 return 1;
1800
1801 slot = (slot + 1) % NUM_RX_BUFF;
1802
1803 /* I'm just being paranoid here :) */
1804 if (unlikely(slot == dev->rx_slot))
1805 return 0;
1806 }
1807}
1808
1809/* Hard IRQ */
1810static void emac_rxde(void *param)
1811{
1812 struct emac_instance *dev = param;
1813
1814 ++dev->estats.rx_stopped;
1815 emac_rx_disable_async(dev);
1816}
1817
1818/* Hard IRQ */
1819static irqreturn_t emac_irq(int irq, void *dev_instance)
1820{
1821 struct emac_instance *dev = dev_instance;
1822 struct emac_regs __iomem *p = dev->emacp;
1823 struct emac_error_stats *st = &dev->estats;
1824 u32 isr;
1825
1826 spin_lock(&dev->lock);
1827
1828 isr = in_be32(&p->isr);
1829 out_be32(&p->isr, isr);
1830
1831 DBG(dev, "isr = %08x" NL, isr);
1832
1833 if (isr & EMAC4_ISR_TXPE)
1834 ++st->tx_parity;
1835 if (isr & EMAC4_ISR_RXPE)
1836 ++st->rx_parity;
1837 if (isr & EMAC4_ISR_TXUE)
1838 ++st->tx_underrun;
1839 if (isr & EMAC4_ISR_RXOE)
1840 ++st->rx_fifo_overrun;
1841 if (isr & EMAC_ISR_OVR)
1842 ++st->rx_overrun;
1843 if (isr & EMAC_ISR_BP)
1844 ++st->rx_bad_packet;
1845 if (isr & EMAC_ISR_RP)
1846 ++st->rx_runt_packet;
1847 if (isr & EMAC_ISR_SE)
1848 ++st->rx_short_event;
1849 if (isr & EMAC_ISR_ALE)
1850 ++st->rx_alignment_error;
1851 if (isr & EMAC_ISR_BFCS)
1852 ++st->rx_bad_fcs;
1853 if (isr & EMAC_ISR_PTLE)
1854 ++st->rx_packet_too_long;
1855 if (isr & EMAC_ISR_ORE)
1856 ++st->rx_out_of_range;
1857 if (isr & EMAC_ISR_IRE)
1858 ++st->rx_in_range;
1859 if (isr & EMAC_ISR_SQE)
1860 ++st->tx_sqe;
1861 if (isr & EMAC_ISR_TE)
1862 ++st->tx_errors;
1863
1864 spin_unlock(&dev->lock);
1865
1866 return IRQ_HANDLED;
1867}
1868
1869static struct net_device_stats *emac_stats(struct net_device *ndev)
1870{
1871 struct emac_instance *dev = netdev_priv(ndev);
1872 struct emac_stats *st = &dev->stats;
1873 struct emac_error_stats *est = &dev->estats;
1874 struct net_device_stats *nst = &dev->nstats;
1875 unsigned long flags;
1876
1877 DBG2(dev, "stats" NL);
1878
1879 /* Compute "legacy" statistics */
1880 spin_lock_irqsave(&dev->lock, flags);
1881 nst->rx_packets = (unsigned long)st->rx_packets;
1882 nst->rx_bytes = (unsigned long)st->rx_bytes;
1883 nst->tx_packets = (unsigned long)st->tx_packets;
1884 nst->tx_bytes = (unsigned long)st->tx_bytes;
1885 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1886 est->rx_dropped_error +
1887 est->rx_dropped_resize +
1888 est->rx_dropped_mtu);
1889 nst->tx_dropped = (unsigned long)est->tx_dropped;
1890
1891 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1892 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1893 est->rx_fifo_overrun +
1894 est->rx_overrun);
1895 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1896 est->rx_alignment_error);
1897 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1898 est->rx_bad_fcs);
1899 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1900 est->rx_bd_short_event +
1901 est->rx_bd_packet_too_long +
1902 est->rx_bd_out_of_range +
1903 est->rx_bd_in_range +
1904 est->rx_runt_packet +
1905 est->rx_short_event +
1906 est->rx_packet_too_long +
1907 est->rx_out_of_range +
1908 est->rx_in_range);
1909
1910 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1911 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1912 est->tx_underrun);
1913 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1914 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1915 est->tx_bd_excessive_collisions +
1916 est->tx_bd_late_collision +
1917 est->tx_bd_multple_collisions);
1918 spin_unlock_irqrestore(&dev->lock, flags);
1919 return nst;
1920}
1921
1922static struct mal_commac_ops emac_commac_ops = {
1923 .poll_tx = &emac_poll_tx,
1924 .poll_rx = &emac_poll_rx,
1925 .peek_rx = &emac_peek_rx,
1926 .rxde = &emac_rxde,
1927};
1928
1929static struct mal_commac_ops emac_commac_sg_ops = {
1930 .poll_tx = &emac_poll_tx,
1931 .poll_rx = &emac_poll_rx,
1932 .peek_rx = &emac_peek_rx_sg,
1933 .rxde = &emac_rxde,
1934};
1935
1936/* Ethtool support */
1937static int emac_ethtool_get_settings(struct net_device *ndev,
1938 struct ethtool_cmd *cmd)
1939{
1940 struct emac_instance *dev = netdev_priv(ndev);
1941
1942 cmd->supported = dev->phy.features;
1943 cmd->port = PORT_MII;
1944 cmd->phy_address = dev->phy.address;
1945 cmd->transceiver =
1946 dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1947
1948 mutex_lock(&dev->link_lock);
1949 cmd->advertising = dev->phy.advertising;
1950 cmd->autoneg = dev->phy.autoneg;
1951 cmd->speed = dev->phy.speed;
1952 cmd->duplex = dev->phy.duplex;
1953 mutex_unlock(&dev->link_lock);
1954
1955 return 0;
1956}
1957
1958static int emac_ethtool_set_settings(struct net_device *ndev,
1959 struct ethtool_cmd *cmd)
1960{
1961 struct emac_instance *dev = netdev_priv(ndev);
1962 u32 f = dev->phy.features;
1963
1964 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
1965 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1966
1967 /* Basic sanity checks */
1968 if (dev->phy.address < 0)
1969 return -EOPNOTSUPP;
1970 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1971 return -EINVAL;
1972 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1973 return -EINVAL;
1974 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1975 return -EINVAL;
1976
1977 if (cmd->autoneg == AUTONEG_DISABLE) {
1978 switch (cmd->speed) {
1979 case SPEED_10:
8e95a202
JP		 1980 if (cmd->duplex == DUPLEX_HALF &&
1981 !(f & SUPPORTED_10baseT_Half))
1d3bb996 1982 return -EINVAL;
8e95a202
JP		 1983 if (cmd->duplex == DUPLEX_FULL &&
1984 !(f & SUPPORTED_10baseT_Full))
1d3bb996
DG		 1985 return -EINVAL;
1986 break;
1987 case SPEED_100:
8e95a202
JP		 1988 if (cmd->duplex == DUPLEX_HALF &&
1989 !(f & SUPPORTED_100baseT_Half))
1d3bb996 1990 return -EINVAL;
8e95a202
JP		 1991 if (cmd->duplex == DUPLEX_FULL &&
1992 !(f & SUPPORTED_100baseT_Full))
1d3bb996
DG		 1993 return -EINVAL;
1994 break;
1995 case SPEED_1000:
8e95a202
JP		 1996 if (cmd->duplex == DUPLEX_HALF &&
1997 !(f & SUPPORTED_1000baseT_Half))
1d3bb996 1998 return -EINVAL;
8e95a202
JP		 1999 if (cmd->duplex == DUPLEX_FULL &&
2000 !(f & SUPPORTED_1000baseT_Full))
1d3bb996
DG		 2001 return -EINVAL;
2002 break;
2003 default:
2004 return -EINVAL;
2005 }
2006
2007 mutex_lock(&dev->link_lock);
2008 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
2009 cmd->duplex);
2010 mutex_unlock(&dev->link_lock);
2011
2012 } else {
2013 if (!(f & SUPPORTED_Autoneg))
2014 return -EINVAL;
2015
2016 mutex_lock(&dev->link_lock);
2017 dev->phy.def->ops->setup_aneg(&dev->phy,
2018 (cmd->advertising & f) |
2019 (dev->phy.advertising &
2020 (ADVERTISED_Pause |
2021 ADVERTISED_Asym_Pause)));
2022 mutex_unlock(&dev->link_lock);
2023 }
2024 emac_force_link_update(dev);
2025
2026 return 0;
2027}
2028
2029static void emac_ethtool_get_ringparam(struct net_device *ndev,
2030 struct ethtool_ringparam *rp)
2031{
2032 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2033 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2034}
2035
2036static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2037 struct ethtool_pauseparam *pp)
2038{
2039 struct emac_instance *dev = netdev_priv(ndev);
2040
2041 mutex_lock(&dev->link_lock);
2042 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2043 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2044 pp->autoneg = 1;
2045
2046 if (dev->phy.duplex == DUPLEX_FULL) {
2047 if (dev->phy.pause)
2048 pp->rx_pause = pp->tx_pause = 1;
2049 else if (dev->phy.asym_pause)
2050 pp->tx_pause = 1;
2051 }
2052 mutex_unlock(&dev->link_lock);
2053}
2054
2055static u32 emac_ethtool_get_rx_csum(struct net_device *ndev)
2056{
2057 struct emac_instance *dev = netdev_priv(ndev);
2058
eb4d84f1 2059 return dev->tah_dev != NULL;
1d3bb996
DG		 2060}
2061
2062static int emac_get_regs_len(struct emac_instance *dev)
2063{
2064 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
2065 return sizeof(struct emac_ethtool_regs_subhdr) +
05781ccd 2066 EMAC4_ETHTOOL_REGS_SIZE(dev);
1d3bb996
DG		 2067 else
2068 return sizeof(struct emac_ethtool_regs_subhdr) +
05781ccd 2069 EMAC_ETHTOOL_REGS_SIZE(dev);
1d3bb996
DG		 2070}
2071
2072static int emac_ethtool_get_regs_len(struct net_device *ndev)
2073{
2074 struct emac_instance *dev = netdev_priv(ndev);
2075 int size;
2076
2077 size = sizeof(struct emac_ethtool_regs_hdr) +
2078 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2079 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2080 size += zmii_get_regs_len(dev->zmii_dev);
2081 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2082 size += rgmii_get_regs_len(dev->rgmii_dev);
2083 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2084 size += tah_get_regs_len(dev->tah_dev);
2085
2086 return size;
2087}
2088
2089static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2090{
2091 struct emac_ethtool_regs_subhdr *hdr = buf;
2092
2093 hdr->index = dev->cell_index;
2094 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2095 hdr->version = EMAC4_ETHTOOL_REGS_VER;
05781ccd
GE		 2096 memcpy_fromio(hdr + 1, dev->emacp, EMAC4_ETHTOOL_REGS_SIZE(dev));
2097 return ((void *)(hdr + 1) + EMAC4_ETHTOOL_REGS_SIZE(dev));
1d3bb996
DG		 2098 } else {
2099 hdr->version = EMAC_ETHTOOL_REGS_VER;
05781ccd
GE		 2100 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE(dev));
2101 return ((void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE(dev));
1d3bb996
DG		 2102 }
2103}
2104
2105static void emac_ethtool_get_regs(struct net_device *ndev,
2106 struct ethtool_regs *regs, void *buf)
2107{
2108 struct emac_instance *dev = netdev_priv(ndev);
2109 struct emac_ethtool_regs_hdr *hdr = buf;
2110
2111 hdr->components = 0;
2112 buf = hdr + 1;
2113
2114 buf = mal_dump_regs(dev->mal, buf);
2115 buf = emac_dump_regs(dev, buf);
2116 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2117 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2118 buf = zmii_dump_regs(dev->zmii_dev, buf);
2119 }
2120 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2121 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2122 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2123 }
2124 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2125 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2126 buf = tah_dump_regs(dev->tah_dev, buf);
2127 }
2128}
2129
2130static int emac_ethtool_nway_reset(struct net_device *ndev)
2131{
2132 struct emac_instance *dev = netdev_priv(ndev);
2133 int res = 0;
2134
2135 DBG(dev, "nway_reset" NL);
2136
2137 if (dev->phy.address < 0)
2138 return -EOPNOTSUPP;
2139
2140 mutex_lock(&dev->link_lock);
2141 if (!dev->phy.autoneg) {
2142 res = -EINVAL;
2143 goto out;
2144 }
2145
2146 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2147 out:
2148 mutex_unlock(&dev->link_lock);
2149 emac_force_link_update(dev);
2150 return res;
2151}
2152
15f0a394 2153static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
1d3bb996 2154{
15f0a394
BH		 2155 if (stringset == ETH_SS_STATS)
2156 return EMAC_ETHTOOL_STATS_COUNT;
2157 else
2158 return -EINVAL;
1d3bb996
DG		 2159}
2160
2161static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2162 u8 * buf)
2163{
2164 if (stringset == ETH_SS_STATS)
2165 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2166}
2167
2168static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2169 struct ethtool_stats *estats,
2170 u64 * tmp_stats)
2171{
2172 struct emac_instance *dev = netdev_priv(ndev);
2173
2174 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2175 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2176 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2177}
2178
2179static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2180 struct ethtool_drvinfo *info)
2181{
2182 struct emac_instance *dev = netdev_priv(ndev);
2183
2184 strcpy(info->driver, "ibm_emac");
2185 strcpy(info->version, DRV_VERSION);
2186 info->fw_version[0] = '\0';
2187 sprintf(info->bus_info, "PPC 4xx EMAC-%d %s",
2188 dev->cell_index, dev->ofdev->node->full_name);
1d3bb996
DG		 2189 info->regdump_len = emac_ethtool_get_regs_len(ndev);
2190}
2191
2192static const struct ethtool_ops emac_ethtool_ops = {
2193 .get_settings = emac_ethtool_get_settings,
2194 .set_settings = emac_ethtool_set_settings,
2195 .get_drvinfo = emac_ethtool_get_drvinfo,
2196
2197 .get_regs_len = emac_ethtool_get_regs_len,
2198 .get_regs = emac_ethtool_get_regs,
2199
2200 .nway_reset = emac_ethtool_nway_reset,
2201
2202 .get_ringparam = emac_ethtool_get_ringparam,
2203 .get_pauseparam = emac_ethtool_get_pauseparam,
2204
2205 .get_rx_csum = emac_ethtool_get_rx_csum,
2206
2207 .get_strings = emac_ethtool_get_strings,
15f0a394 2208 .get_sset_count = emac_ethtool_get_sset_count,
1d3bb996
DG		 2209 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2210
2211 .get_link = ethtool_op_get_link,
2212 .get_tx_csum = ethtool_op_get_tx_csum,
2213 .get_sg = ethtool_op_get_sg,
2214};
2215
2216static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2217{
2218 struct emac_instance *dev = netdev_priv(ndev);
0fa0ee05 2219 struct mii_ioctl_data *data = if_mii(rq);
1d3bb996
DG		 2220
2221 DBG(dev, "ioctl %08x" NL, cmd);
2222
2223 if (dev->phy.address < 0)
2224 return -EOPNOTSUPP;
2225
2226 switch (cmd) {
2227 case SIOCGMIIPHY:
0fa0ee05 2228 data->phy_id = dev->phy.address;
1d3bb996
DG		 2229 /* Fall through */
2230 case SIOCGMIIREG:
0fa0ee05
BH		 2231 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2232 data->reg_num);
1d3bb996
DG		 2233 return 0;
2234
2235 case SIOCSMIIREG:
0fa0ee05
BH		 2236 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2237 data->val_in);
1d3bb996
DG		 2238 return 0;
2239 default:
2240 return -EOPNOTSUPP;
2241 }
2242}
2243
2244struct emac_depentry {
2245 u32 phandle;
2246 struct device_node *node;
2247 struct of_device *ofdev;
2248 void *drvdata;
2249};
2250
2251#define EMAC_DEP_MAL_IDX 0
2252#define EMAC_DEP_ZMII_IDX 1
2253#define EMAC_DEP_RGMII_IDX 2
2254#define EMAC_DEP_TAH_IDX 3
2255#define EMAC_DEP_MDIO_IDX 4
2256#define EMAC_DEP_PREV_IDX 5
2257#define EMAC_DEP_COUNT 6
2258
2259static int __devinit emac_check_deps(struct emac_instance *dev,
2260 struct emac_depentry *deps)
2261{
2262 int i, there = 0;
2263 struct device_node *np;
2264
2265 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2266 /* no dependency on that item, allright */
2267 if (deps[i].phandle == 0) {
2268 there++;
2269 continue;
2270 }
2271 /* special case for blist as the dependency might go away */
2272 if (i == EMAC_DEP_PREV_IDX) {
2273 np = *(dev->blist - 1);
2274 if (np == NULL) {
2275 deps[i].phandle = 0;
2276 there++;
2277 continue;
2278 }
2279 if (deps[i].node == NULL)
2280 deps[i].node = of_node_get(np);
2281 }
2282 if (deps[i].node == NULL)
2283 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2284 if (deps[i].node == NULL)
2285 continue;
2286 if (deps[i].ofdev == NULL)
2287 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2288 if (deps[i].ofdev == NULL)
2289 continue;
2290 if (deps[i].drvdata == NULL)
2291 deps[i].drvdata = dev_get_drvdata(&deps[i].ofdev->dev);
2292 if (deps[i].drvdata != NULL)
2293 there++;
2294 }
2295 return (there == EMAC_DEP_COUNT);
2296}
2297
2298static void emac_put_deps(struct emac_instance *dev)
2299{
2300 if (dev->mal_dev)
2301 of_dev_put(dev->mal_dev);
2302 if (dev->zmii_dev)
2303 of_dev_put(dev->zmii_dev);
2304 if (dev->rgmii_dev)
2305 of_dev_put(dev->rgmii_dev);
2306 if (dev->mdio_dev)
2307 of_dev_put(dev->mdio_dev);
2308 if (dev->tah_dev)
2309 of_dev_put(dev->tah_dev);
2310}
2311
2312static int __devinit emac_of_bus_notify(struct notifier_block *nb,
2313 unsigned long action, void *data)
2314{
2315 /* We are only intereted in device addition */
2316 if (action == BUS_NOTIFY_BOUND_DRIVER)
2317 wake_up_all(&emac_probe_wait);
2318 return 0;
2319}
2320
51d4a1cc 2321static struct notifier_block emac_of_bus_notifier __devinitdata = {
1d3bb996
DG		 2322 .notifier_call = emac_of_bus_notify
2323};
2324
2325static int __devinit emac_wait_deps(struct emac_instance *dev)
2326{
2327 struct emac_depentry deps[EMAC_DEP_COUNT];
2328 int i, err;
2329
2330 memset(&deps, 0, sizeof(deps));
2331
2332 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2333 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2334 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2335 if (dev->tah_ph)
2336 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2337 if (dev->mdio_ph)
2338 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2339 if (dev->blist && dev->blist > emac_boot_list)
2340 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2341 bus_register_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2342 wait_event_timeout(emac_probe_wait,
2343 emac_check_deps(dev, deps),
2344 EMAC_PROBE_DEP_TIMEOUT);
2345 bus_unregister_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2346 err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2347 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2348 if (deps[i].node)
2349 of_node_put(deps[i].node);
2350 if (err && deps[i].ofdev)
2351 of_dev_put(deps[i].ofdev);
2352 }
2353 if (err == 0) {
2354 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2355 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2356 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2357 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2358 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2359 }
2360 if (deps[EMAC_DEP_PREV_IDX].ofdev)
2361 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2362 return err;
2363}
2364
2365static int __devinit emac_read_uint_prop(struct device_node *np, const char *name,
2366 u32 *val, int fatal)
2367{
2368 int len;
2369 const u32 *prop = of_get_property(np, name, &len);
2370 if (prop == NULL || len < sizeof(u32)) {
2371 if (fatal)
2372 printk(KERN_ERR "%s: missing %s property\n",
2373 np->full_name, name);
2374 return -ENODEV;
2375 }
2376 *val = *prop;
2377 return 0;
2378}
2379
2380static int __devinit emac_init_phy(struct emac_instance *dev)
2381{
2382 struct device_node *np = dev->ofdev->node;
2383 struct net_device *ndev = dev->ndev;
2384 u32 phy_map, adv;
2385 int i;
2386
2387 dev->phy.dev = ndev;
2388 dev->phy.mode = dev->phy_mode;
2389
2390 /* PHY-less configuration.
2391 * XXX I probably should move these settings to the dev tree
2392 */
2393 if (dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) {
2394 emac_reset(dev);
2395
2396 /* PHY-less configuration.
2397 * XXX I probably should move these settings to the dev tree
2398 */
2399 dev->phy.address = -1;
9e3cb294
VG		 2400 dev->phy.features = SUPPORTED_MII;
2401 if (emac_phy_supports_gige(dev->phy_mode))
2402 dev->phy.features |= SUPPORTED_1000baseT_Full;
2403 else
2404 dev->phy.features |= SUPPORTED_100baseT_Full;
1d3bb996
DG		 2405 dev->phy.pause = 1;
2406
2407 return 0;
2408 }
2409
2410 mutex_lock(&emac_phy_map_lock);
2411 phy_map = dev->phy_map | busy_phy_map;
2412
2413 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2414
2415 dev->phy.mdio_read = emac_mdio_read;
2416 dev->phy.mdio_write = emac_mdio_write;
2417
0925ab5d
VB		 2418 /* Enable internal clock source */
2419#ifdef CONFIG_PPC_DCR_NATIVE
2420 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2421 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
11121e30
VB		 2422#endif
2423 /* PHY clock workaround */
2424 emac_rx_clk_tx(dev);
2425
2426 /* Enable internal clock source on 440GX*/
2427#ifdef CONFIG_PPC_DCR_NATIVE
2428 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2429 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
0925ab5d 2430#endif
1d3bb996
DG		 2431 /* Configure EMAC with defaults so we can at least use MDIO
2432 * This is needed mostly for 440GX
2433 */
2434 if (emac_phy_gpcs(dev->phy.mode)) {
2435 /* XXX
2436 * Make GPCS PHY address equal to EMAC index.
2437 * We probably should take into account busy_phy_map
2438 * and/or phy_map here.
2439 *
2440 * Note that the busy_phy_map is currently global
2441 * while it should probably be per-ASIC...
2442 */
9e3cb294
VG		 2443 dev->phy.gpcs_address = dev->gpcs_address;
2444 if (dev->phy.gpcs_address == 0xffffffff)
2445 dev->phy.address = dev->cell_index;
1d3bb996
DG		 2446 }
2447
2448 emac_configure(dev);
2449
2450 if (dev->phy_address != 0xffffffff)
2451 phy_map = ~(1 << dev->phy_address);
2452
2453 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2454 if (!(phy_map & 1)) {
2455 int r;
2456 busy_phy_map |= 1 << i;
2457
2458 /* Quick check if there is a PHY at the address */
2459 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2460 if (r == 0xffff || r < 0)
2461 continue;
2462 if (!emac_mii_phy_probe(&dev->phy, i))
2463 break;
2464 }
0925ab5d
VB		 2465
2466 /* Enable external clock source */
2467#ifdef CONFIG_PPC_DCR_NATIVE
2468 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2469 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2470#endif
1d3bb996
DG		 2471 mutex_unlock(&emac_phy_map_lock);
2472 if (i == 0x20) {
2473 printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
2474 return -ENXIO;
2475 }
2476
2477 /* Init PHY */
2478 if (dev->phy.def->ops->init)
2479 dev->phy.def->ops->init(&dev->phy);
2480
2481 /* Disable any PHY features not supported by the platform */
2482 dev->phy.def->features &= ~dev->phy_feat_exc;
2483
2484 /* Setup initial link parameters */
2485 if (dev->phy.features & SUPPORTED_Autoneg) {
2486 adv = dev->phy.features;
2487 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2488 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2489 /* Restart autonegotiation */
2490 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2491 } else {
2492 u32 f = dev->phy.def->features;
2493 int speed = SPEED_10, fd = DUPLEX_HALF;
2494
2495 /* Select highest supported speed/duplex */
2496 if (f & SUPPORTED_1000baseT_Full) {
2497 speed = SPEED_1000;
2498 fd = DUPLEX_FULL;
2499 } else if (f & SUPPORTED_1000baseT_Half)
2500 speed = SPEED_1000;
2501 else if (f & SUPPORTED_100baseT_Full) {
2502 speed = SPEED_100;
2503 fd = DUPLEX_FULL;
2504 } else if (f & SUPPORTED_100baseT_Half)
2505 speed = SPEED_100;
2506 else if (f & SUPPORTED_10baseT_Full)
2507 fd = DUPLEX_FULL;
2508
2509 /* Force link parameters */
2510 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2511 }
2512 return 0;
2513}
2514
2515static int __devinit emac_init_config(struct emac_instance *dev)
2516{
2517 struct device_node *np = dev->ofdev->node;
2518 const void *p;
2519 unsigned int plen;
2520 const char *pm, *phy_modes[] = {
2521 [PHY_MODE_NA] = "",
2522 [PHY_MODE_MII] = "mii",
2523 [PHY_MODE_RMII] = "rmii",
2524 [PHY_MODE_SMII] = "smii",
2525 [PHY_MODE_RGMII] = "rgmii",
2526 [PHY_MODE_TBI] = "tbi",
2527 [PHY_MODE_GMII] = "gmii",
2528 [PHY_MODE_RTBI] = "rtbi",
2529 [PHY_MODE_SGMII] = "sgmii",
2530 };
2531
2532 /* Read config from device-tree */
2533 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2534 return -ENXIO;
2535 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2536 return -ENXIO;
2537 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2538 return -ENXIO;
2539 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2540 return -ENXIO;
2541 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2542 dev->max_mtu = 1500;
2543 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2544 dev->rx_fifo_size = 2048;
2545 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2546 dev->tx_fifo_size = 2048;
2547 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2548 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2549 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2550 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2551 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2552 dev->phy_address = 0xffffffff;
2553 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2554 dev->phy_map = 0xffffffff;
9e3cb294
VG		 2555 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2556 dev->gpcs_address = 0xffffffff;
1d3bb996
DG		 2557 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2558 return -ENXIO;
2559 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2560 dev->tah_ph = 0;
2561 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
63b6cad7 2562 dev->tah_port = 0;
1d3bb996
DG		 2563 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2564 dev->mdio_ph = 0;
2565 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
a419aef8 2566 dev->zmii_ph = 0;
1d3bb996 2567 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
a419aef8 2568 dev->zmii_port = 0xffffffff;
1d3bb996 2569 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
a419aef8 2570 dev->rgmii_ph = 0;
1d3bb996 2571 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
a419aef8 2572 dev->rgmii_port = 0xffffffff;
1d3bb996
DG		 2573 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2574 dev->fifo_entry_size = 16;
2575 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2576 dev->mal_burst_size = 256;
2577
2578 /* PHY mode needs some decoding */
2579 dev->phy_mode = PHY_MODE_NA;
2580 pm = of_get_property(np, "phy-mode", &plen);
2581 if (pm != NULL) {
2582 int i;
2583 for (i = 0; i < ARRAY_SIZE(phy_modes); i++)
2584 if (!strcasecmp(pm, phy_modes[i])) {
2585 dev->phy_mode = i;
2586 break;
2587 }
2588 }
2589
2590 /* Backward compat with non-final DT */
2591 if (dev->phy_mode == PHY_MODE_NA && pm != NULL && plen == 4) {
2592 u32 nmode = *(const u32 *)pm;
2593 if (nmode > PHY_MODE_NA && nmode <= PHY_MODE_SGMII)
2594 dev->phy_mode = nmode;
2595 }
2596
2597 /* Check EMAC version */
05781ccd
GE		 2598 if (of_device_is_compatible(np, "ibm,emac4sync")) {
2599 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
9e3cb294
VG		 2600 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2601 of_device_is_compatible(np, "ibm,emac-460gt"))
2602 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
9616a755
BH		 2603 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2604 of_device_is_compatible(np, "ibm,emac-405exr"))
2605 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
05781ccd 2606 } else if (of_device_is_compatible(np, "ibm,emac4")) {
1d3bb996 2607 dev->features |= EMAC_FTR_EMAC4;
0925ab5d
VB		 2608 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2609 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
11121e30
VB		 2610 } else {
2611 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2612 of_device_is_compatible(np, "ibm,emac-440gr"))
2613 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
1ff0fcfc 2614 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
c778e11d 2615#ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL
b68d185a 2616 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
1ff0fcfc
JB		 2617#else
2618 printk(KERN_ERR "%s: Flow control not disabled!\n",
2619 np->full_name);
2620 return -ENXIO;
2621#endif
2622 }
2623
0925ab5d 2624 }
bff713b5
BH		 2625
2626 /* Fixup some feature bits based on the device tree */
2627 if (of_get_property(np, "has-inverted-stacr-oc", NULL))
1d3bb996 2628 dev->features |= EMAC_FTR_STACR_OC_INVERT;
bff713b5
BH		 2629 if (of_get_property(np, "has-new-stacr-staopc", NULL))
2630 dev->features |= EMAC_FTR_HAS_NEW_STACR;
1d3bb996 2631
bff713b5
BH		 2632 /* CAB lacks the appropriate properties */
2633 if (of_device_is_compatible(np, "ibm,emac-axon"))
2634 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2635 EMAC_FTR_STACR_OC_INVERT;
2636
2637 /* Enable TAH/ZMII/RGMII features as found */
1d3bb996
DG		 2638 if (dev->tah_ph != 0) {
2639#ifdef CONFIG_IBM_NEW_EMAC_TAH
2640 dev->features |= EMAC_FTR_HAS_TAH;
2641#else
2642 printk(KERN_ERR "%s: TAH support not enabled !\n",
2643 np->full_name);
2644 return -ENXIO;
2645#endif
2646 }
2647
2648 if (dev->zmii_ph != 0) {
2649#ifdef CONFIG_IBM_NEW_EMAC_ZMII
2650 dev->features |= EMAC_FTR_HAS_ZMII;
2651#else
2652 printk(KERN_ERR "%s: ZMII support not enabled !\n",
2653 np->full_name);
2654 return -ENXIO;
2655#endif
2656 }
2657
2658 if (dev->rgmii_ph != 0) {
2659#ifdef CONFIG_IBM_NEW_EMAC_RGMII
2660 dev->features |= EMAC_FTR_HAS_RGMII;
2661#else
2662 printk(KERN_ERR "%s: RGMII support not enabled !\n",
2663 np->full_name);
2664 return -ENXIO;
2665#endif
2666 }
2667
2668 /* Read MAC-address */
2669 p = of_get_property(np, "local-mac-address", NULL);
2670 if (p == NULL) {
2671 printk(KERN_ERR "%s: Can't find local-mac-address property\n",
2672 np->full_name);
2673 return -ENXIO;
2674 }
2675 memcpy(dev->ndev->dev_addr, p, 6);
2676
05781ccd
GE		 2677 /* IAHT and GAHT filter parameterization */
2678 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2679 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2680 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2681 } else {
2682 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2683 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2684 }
2685
1d3bb996
DG		 2686 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2687 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2688 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2689 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2690 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2691
2692 return 0;
2693}
2694
15efc02b
AB		 2695static const struct net_device_ops emac_netdev_ops = {
2696 .ndo_open = emac_open,
2697 .ndo_stop = emac_close,
2698 .ndo_get_stats = emac_stats,
2699 .ndo_set_multicast_list = emac_set_multicast_list,
2700 .ndo_do_ioctl = emac_ioctl,
2701 .ndo_tx_timeout = emac_tx_timeout,
2702 .ndo_validate_addr = eth_validate_addr,
2703 .ndo_set_mac_address = eth_mac_addr,
2704 .ndo_start_xmit = emac_start_xmit,
2705 .ndo_change_mtu = eth_change_mtu,
2706};
2707
2708static const struct net_device_ops emac_gige_netdev_ops = {
2709 .ndo_open = emac_open,
2710 .ndo_stop = emac_close,
2711 .ndo_get_stats = emac_stats,
2712 .ndo_set_multicast_list = emac_set_multicast_list,
2713 .ndo_do_ioctl = emac_ioctl,
2714 .ndo_tx_timeout = emac_tx_timeout,
2715 .ndo_validate_addr = eth_validate_addr,
2716 .ndo_set_mac_address = eth_mac_addr,
2717 .ndo_start_xmit = emac_start_xmit_sg,
2718 .ndo_change_mtu = emac_change_mtu,
2719};
2720
1d3bb996
DG		 2721static int __devinit emac_probe(struct of_device *ofdev,
2722 const struct of_device_id *match)
2723{
2724 struct net_device *ndev;
2725 struct emac_instance *dev;
2726 struct device_node *np = ofdev->node;
2727 struct device_node **blist = NULL;
2728 int err, i;
2729
be63c09a
JB		 2730 /* Skip unused/unwired EMACS. We leave the check for an unused
2731 * property here for now, but new flat device trees should set a
2732 * status property to "disabled" instead.
2733 */
2734 if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
3d722562
HB		 2735 return -ENODEV;
2736
1d3bb996
DG		 2737 /* Find ourselves in the bootlist if we are there */
2738 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
2739 if (emac_boot_list[i] == np)
2740 blist = &emac_boot_list[i];
2741
2742 /* Allocate our net_device structure */
2743 err = -ENOMEM;
2744 ndev = alloc_etherdev(sizeof(struct emac_instance));
2745 if (!ndev) {
2746 printk(KERN_ERR "%s: could not allocate ethernet device!\n",
2747 np->full_name);
2748 goto err_gone;
2749 }
2750 dev = netdev_priv(ndev);
2751 dev->ndev = ndev;
2752 dev->ofdev = ofdev;
2753 dev->blist = blist;
1d3bb996
DG		 2754 SET_NETDEV_DEV(ndev, &ofdev->dev);
2755
2756 /* Initialize some embedded data structures */
2757 mutex_init(&dev->mdio_lock);
2758 mutex_init(&dev->link_lock);
2759 spin_lock_init(&dev->lock);
2760 INIT_WORK(&dev->reset_work, emac_reset_work);
2761
2762 /* Init various config data based on device-tree */
2763 err = emac_init_config(dev);
2764 if (err != 0)
2765 goto err_free;
2766
2767 /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
2768 dev->emac_irq = irq_of_parse_and_map(np, 0);
2769 dev->wol_irq = irq_of_parse_and_map(np, 1);
2770 if (dev->emac_irq == NO_IRQ) {
2771 printk(KERN_ERR "%s: Can't map main interrupt\n", np->full_name);
2772 goto err_free;
2773 }
2774 ndev->irq = dev->emac_irq;
2775
2776 /* Map EMAC regs */
2777 if (of_address_to_resource(np, 0, &dev->rsrc_regs)) {
2778 printk(KERN_ERR "%s: Can't get registers address\n",
2779 np->full_name);
2780 goto err_irq_unmap;
2781 }
2782 // TODO : request_mem_region
05781ccd
GE		 2783 dev->emacp = ioremap(dev->rsrc_regs.start,
2784 dev->rsrc_regs.end - dev->rsrc_regs.start + 1);
1d3bb996
DG		 2785 if (dev->emacp == NULL) {
2786 printk(KERN_ERR "%s: Can't map device registers!\n",
2787 np->full_name);
2788 err = -ENOMEM;
2789 goto err_irq_unmap;
2790 }
2791
2792 /* Wait for dependent devices */
2793 err = emac_wait_deps(dev);
2794 if (err) {
2795 printk(KERN_ERR
2796 "%s: Timeout waiting for dependent devices\n",
2797 np->full_name);
2798 /* display more info about what's missing ? */
2799 goto err_reg_unmap;
2800 }
2801 dev->mal = dev_get_drvdata(&dev->mal_dev->dev);
2802 if (dev->mdio_dev != NULL)
2803 dev->mdio_instance = dev_get_drvdata(&dev->mdio_dev->dev);
2804
2805 /* Register with MAL */
2806 dev->commac.ops = &emac_commac_ops;
2807 dev->commac.dev = dev;
2808 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
2809 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
2810 err = mal_register_commac(dev->mal, &dev->commac);
2811 if (err) {
2812 printk(KERN_ERR "%s: failed to register with mal %s!\n",
2813 np->full_name, dev->mal_dev->node->full_name);
2814 goto err_rel_deps;
2815 }
2816 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
2817 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
2818
2819 /* Get pointers to BD rings */
2820 dev->tx_desc =
2821 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
2822 dev->rx_desc =
2823 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
2824
2825 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
2826 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
2827
2828 /* Clean rings */
2829 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2830 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
ab9b30cc
SN		 2831 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
2832 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
1d3bb996
DG		 2833
2834 /* Attach to ZMII, if needed */
2835 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
2836 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
2837 goto err_unreg_commac;
2838
2839 /* Attach to RGMII, if needed */
2840 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
2841 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
2842 goto err_detach_zmii;
2843
2844 /* Attach to TAH, if needed */
2845 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
2846 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
2847 goto err_detach_rgmii;
2848
2849 /* Set some link defaults before we can find out real parameters */
2850 dev->phy.speed = SPEED_100;
2851 dev->phy.duplex = DUPLEX_FULL;
2852 dev->phy.autoneg = AUTONEG_DISABLE;
2853 dev->phy.pause = dev->phy.asym_pause = 0;
2854 dev->stop_timeout = STOP_TIMEOUT_100;
2855 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
2856
2857 /* Find PHY if any */
2858 err = emac_init_phy(dev);
2859 if (err != 0)
2860 goto err_detach_tah;
2861
ee63d22b 2862 if (dev->tah_dev)
1d3bb996 2863 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1d3bb996 2864 ndev->watchdog_timeo = 5 * HZ;
1d3bb996 2865 if (emac_phy_supports_gige(dev->phy_mode)) {
15efc02b 2866 ndev->netdev_ops = &emac_gige_netdev_ops;
1d3bb996 2867 dev->commac.ops = &emac_commac_sg_ops;
15efc02b
AB		 2868 } else
2869 ndev->netdev_ops = &emac_netdev_ops;
1d3bb996
DG		 2870 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2871
2872 netif_carrier_off(ndev);
2873 netif_stop_queue(ndev);
2874
2875 err = register_netdev(ndev);
2876 if (err) {
2877 printk(KERN_ERR "%s: failed to register net device (%d)!\n",
2878 np->full_name, err);
2879 goto err_detach_tah;
2880 }
2881
2882 /* Set our drvdata last as we don't want them visible until we are
2883 * fully initialized
2884 */
2885 wmb();
2886 dev_set_drvdata(&ofdev->dev, dev);
2887
2888 /* There's a new kid in town ! Let's tell everybody */
2889 wake_up_all(&emac_probe_wait);
2890
2891
7c510e4b
JB		 2892 printk(KERN_INFO "%s: EMAC-%d %s, MAC %pM\n",
2893 ndev->name, dev->cell_index, np->full_name, ndev->dev_addr);
1d3bb996 2894
9e3cb294
VG		 2895 if (dev->phy_mode == PHY_MODE_SGMII)
2896 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
2897
1d3bb996
DG		 2898 if (dev->phy.address >= 0)
2899 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2900 dev->phy.def->name, dev->phy.address);
2901
2902 emac_dbg_register(dev);
2903
2904 /* Life is good */
2905 return 0;
2906
2907 /* I have a bad feeling about this ... */
2908
2909 err_detach_tah:
2910 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2911 tah_detach(dev->tah_dev, dev->tah_port);
2912 err_detach_rgmii:
2913 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2914 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2915 err_detach_zmii:
2916 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2917 zmii_detach(dev->zmii_dev, dev->zmii_port);
2918 err_unreg_commac:
2919 mal_unregister_commac(dev->mal, &dev->commac);
2920 err_rel_deps:
2921 emac_put_deps(dev);
2922 err_reg_unmap:
2923 iounmap(dev->emacp);
2924 err_irq_unmap:
2925 if (dev->wol_irq != NO_IRQ)
2926 irq_dispose_mapping(dev->wol_irq);
2927 if (dev->emac_irq != NO_IRQ)
2928 irq_dispose_mapping(dev->emac_irq);
2929 err_free:
2930 kfree(ndev);
2931 err_gone:
2932 /* if we were on the bootlist, remove us as we won't show up and
2933 * wake up all waiters to notify them in case they were waiting
2934 * on us
2935 */
2936 if (blist) {
2937 *blist = NULL;
2938 wake_up_all(&emac_probe_wait);
2939 }
2940 return err;
2941}
2942
2943static int __devexit emac_remove(struct of_device *ofdev)
2944{
2945 struct emac_instance *dev = dev_get_drvdata(&ofdev->dev);
2946
2947 DBG(dev, "remove" NL);
2948
2949 dev_set_drvdata(&ofdev->dev, NULL);
2950
2951 unregister_netdev(dev->ndev);
2952
61dbcece
BH		 2953 flush_scheduled_work();
2954
1d3bb996
DG		 2955 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2956 tah_detach(dev->tah_dev, dev->tah_port);
2957 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2958 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2959 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2960 zmii_detach(dev->zmii_dev, dev->zmii_port);
2961
2962 mal_unregister_commac(dev->mal, &dev->commac);
2963 emac_put_deps(dev);
2964
2965 emac_dbg_unregister(dev);
2966 iounmap(dev->emacp);
2967
2968 if (dev->wol_irq != NO_IRQ)
2969 irq_dispose_mapping(dev->wol_irq);
2970 if (dev->emac_irq != NO_IRQ)
2971 irq_dispose_mapping(dev->emac_irq);
2972
2973 kfree(dev->ndev);
2974
2975 return 0;
2976}
2977
2978/* XXX Features in here should be replaced by properties... */
2979static struct of_device_id emac_match[] =
2980{
2981 {
2982 .type = "network",
2983 .compatible = "ibm,emac",
2984 },
2985 {
2986 .type = "network",
2987 .compatible = "ibm,emac4",
2988 },
05781ccd
GE		 2989 {
2990 .type = "network",
2991 .compatible = "ibm,emac4sync",
2992 },
1d3bb996
DG		 2993 {},
2994};
e72701ac 2995MODULE_DEVICE_TABLE(of, emac_match);
1d3bb996
DG		 2996
2997static struct of_platform_driver emac_driver = {
2998 .name = "emac",
2999 .match_table = emac_match,
3000
3001 .probe = emac_probe,
3002 .remove = emac_remove,
3003};
3004
3005static void __init emac_make_bootlist(void)
3006{
3007 struct device_node *np = NULL;
3008 int j, max, i = 0, k;
3009 int cell_indices[EMAC_BOOT_LIST_SIZE];
3010
3011 /* Collect EMACs */
3012 while((np = of_find_all_nodes(np)) != NULL) {
3013 const u32 *idx;
3014
3015 if (of_match_node(emac_match, np) == NULL)
3016 continue;
3017 if (of_get_property(np, "unused", NULL))
3018 continue;
3019 idx = of_get_property(np, "cell-index", NULL);
3020 if (idx == NULL)
3021 continue;
3022 cell_indices[i] = *idx;
3023 emac_boot_list[i++] = of_node_get(np);
3024 if (i >= EMAC_BOOT_LIST_SIZE) {
3025 of_node_put(np);
3026 break;
3027 }
3028 }
3029 max = i;
3030
3031 /* Bubble sort them (doh, what a creative algorithm :-) */
3032 for (i = 0; max > 1 && (i < (max - 1)); i++)
3033 for (j = i; j < max; j++) {
3034 if (cell_indices[i] > cell_indices[j]) {
3035 np = emac_boot_list[i];
3036 emac_boot_list[i] = emac_boot_list[j];
3037 emac_boot_list[j] = np;
3038 k = cell_indices[i];
3039 cell_indices[i] = cell_indices[j];
3040 cell_indices[j] = k;
3041 }
3042 }
3043}
3044
3045static int __init emac_init(void)
3046{
3047 int rc;
3048
3049 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3050
3051 /* Init debug stuff */
3052 emac_init_debug();
3053
3054 /* Build EMAC boot list */
3055 emac_make_bootlist();
3056
3057 /* Init submodules */
3058 rc = mal_init();
3059 if (rc)
3060 goto err;
3061 rc = zmii_init();
3062 if (rc)
3063 goto err_mal;
3064 rc = rgmii_init();
3065 if (rc)
3066 goto err_zmii;
3067 rc = tah_init();
3068 if (rc)
3069 goto err_rgmii;
3070 rc = of_register_platform_driver(&emac_driver);
3071 if (rc)
3072 goto err_tah;
3073
3074 return 0;
3075
3076 err_tah:
3077 tah_exit();
3078 err_rgmii:
3079 rgmii_exit();
3080 err_zmii:
3081 zmii_exit();
3082 err_mal:
3083 mal_exit();
3084 err:
3085 return rc;
3086}
3087
3088static void __exit emac_exit(void)
3089{
3090 int i;
3091
3092 of_unregister_platform_driver(&emac_driver);
3093
3094 tah_exit();
3095 rgmii_exit();
3096 zmii_exit();
3097 mal_exit();
3098 emac_fini_debug();
3099
3100 /* Destroy EMAC boot list */
3101 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3102 if (emac_boot_list[i])
3103 of_node_put(emac_boot_list[i]);
3104}
3105
3106module_init(emac_init);
3107module_exit(emac_exit);
Clone of davem's net-next-2.6 tree