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1da177e4 | 1 | /* |
37448f7d | 2 | * drivers/net/ibm_emac/ibm_emac_debug.c |
1da177e4 | 3 | * |
37448f7d | 4 | * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines. |
1da177e4 | 5 | * |
37448f7d ES |
6 | * Copyright (c) 2004, 2005 Zultys Technologies |
7 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> | |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
37448f7d | 13 | * |
1da177e4 | 14 | */ |
37448f7d ES |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
1da177e4 LT |
17 | #include <linux/kernel.h> |
18 | #include <linux/netdevice.h> | |
37448f7d | 19 | #include <linux/sysrq.h> |
1da177e4 | 20 | #include <asm/io.h> |
1da177e4 | 21 | |
37448f7d ES |
22 | #include "ibm_emac_core.h" |
23 | ||
24 | static void emac_desc_dump(int idx, struct ocp_enet_private *p) | |
25 | { | |
26 | int i; | |
27 | printk("** EMAC%d TX BDs **\n" | |
28 | " tx_cnt = %d tx_slot = %d ack_slot = %d\n", | |
29 | idx, p->tx_cnt, p->tx_slot, p->ack_slot); | |
30 | for (i = 0; i < NUM_TX_BUFF / 2; ++i) | |
31 | printk | |
32 | ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n", | |
33 | i, p->tx_desc[i].data_ptr, p->tx_skb[i] ? 'V' : ' ', | |
34 | p->tx_desc[i].ctrl, p->tx_desc[i].data_len, | |
35 | NUM_TX_BUFF / 2 + i, | |
36 | p->tx_desc[NUM_TX_BUFF / 2 + i].data_ptr, | |
37 | p->tx_skb[NUM_TX_BUFF / 2 + i] ? 'V' : ' ', | |
38 | p->tx_desc[NUM_TX_BUFF / 2 + i].ctrl, | |
39 | p->tx_desc[NUM_TX_BUFF / 2 + i].data_len); | |
40 | ||
41 | printk("** EMAC%d RX BDs **\n" | |
42 | " rx_slot = %d rx_stopped = %d rx_skb_size = %d rx_sync_size = %d\n" | |
43 | " rx_sg_skb = 0x%p\n", | |
44 | idx, p->rx_slot, p->commac.rx_stopped, p->rx_skb_size, | |
45 | p->rx_sync_size, p->rx_sg_skb); | |
46 | for (i = 0; i < NUM_RX_BUFF / 2; ++i) | |
47 | printk | |
48 | ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n", | |
49 | i, p->rx_desc[i].data_ptr, p->rx_skb[i] ? 'V' : ' ', | |
50 | p->rx_desc[i].ctrl, p->rx_desc[i].data_len, | |
51 | NUM_RX_BUFF / 2 + i, | |
52 | p->rx_desc[NUM_RX_BUFF / 2 + i].data_ptr, | |
53 | p->rx_skb[NUM_RX_BUFF / 2 + i] ? 'V' : ' ', | |
54 | p->rx_desc[NUM_RX_BUFF / 2 + i].ctrl, | |
55 | p->rx_desc[NUM_RX_BUFF / 2 + i].data_len); | |
56 | } | |
57 | ||
58 | static void emac_mac_dump(int idx, struct ocp_enet_private *dev) | |
59 | { | |
b43de2d8 | 60 | struct emac_regs __iomem *p = dev->emacp; |
37448f7d ES |
61 | |
62 | printk("** EMAC%d registers **\n" | |
63 | "MR0 = 0x%08x MR1 = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x\n" | |
64 | "RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x\n" | |
65 | "IAR = %04x%08x VTPID = 0x%04x VTCI = 0x%04x\n" | |
66 | "IAHT: 0x%04x 0x%04x 0x%04x 0x%04x " | |
67 | "GAHT: 0x%04x 0x%04x 0x%04x 0x%04x\n" | |
68 | "LSA = %04x%08x IPGVR = 0x%04x\n" | |
69 | "STACR = 0x%08x TRTR = 0x%08x RWMR = 0x%08x\n" | |
70 | "OCTX = 0x%08x OCRX = 0x%08x IPCR = 0x%08x\n", | |
71 | idx, in_be32(&p->mr0), in_be32(&p->mr1), | |
72 | in_be32(&p->tmr0), in_be32(&p->tmr1), | |
73 | in_be32(&p->rmr), in_be32(&p->isr), in_be32(&p->iser), | |
74 | in_be32(&p->iahr), in_be32(&p->ialr), in_be32(&p->vtpid), | |
75 | in_be32(&p->vtci), | |
76 | in_be32(&p->iaht1), in_be32(&p->iaht2), in_be32(&p->iaht3), | |
77 | in_be32(&p->iaht4), | |
78 | in_be32(&p->gaht1), in_be32(&p->gaht2), in_be32(&p->gaht3), | |
79 | in_be32(&p->gaht4), | |
80 | in_be32(&p->lsah), in_be32(&p->lsal), in_be32(&p->ipgvr), | |
81 | in_be32(&p->stacr), in_be32(&p->trtr), in_be32(&p->rwmr), | |
82 | in_be32(&p->octx), in_be32(&p->ocrx), in_be32(&p->ipcr) | |
83 | ); | |
84 | ||
85 | emac_desc_dump(idx, dev); | |
86 | } | |
87 | ||
88 | static void emac_mal_dump(struct ibm_ocp_mal *mal) | |
89 | { | |
90 | struct ocp_func_mal_data *maldata = mal->def->additions; | |
91 | int i; | |
92 | ||
93 | printk("** MAL%d Registers **\n" | |
94 | "CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n" | |
95 | "TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n" | |
96 | "RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n", | |
97 | mal->def->index, | |
98 | get_mal_dcrn(mal, MAL_CFG), get_mal_dcrn(mal, MAL_ESR), | |
99 | get_mal_dcrn(mal, MAL_IER), | |
100 | get_mal_dcrn(mal, MAL_TXCASR), get_mal_dcrn(mal, MAL_TXCARR), | |
101 | get_mal_dcrn(mal, MAL_TXEOBISR), get_mal_dcrn(mal, MAL_TXDEIR), | |
102 | get_mal_dcrn(mal, MAL_RXCASR), get_mal_dcrn(mal, MAL_RXCARR), | |
103 | get_mal_dcrn(mal, MAL_RXEOBISR), get_mal_dcrn(mal, MAL_RXDEIR) | |
104 | ); | |
105 | ||
106 | printk("TX|"); | |
107 | for (i = 0; i < maldata->num_tx_chans; ++i) { | |
108 | if (i && !(i % 4)) | |
109 | printk("\n "); | |
110 | printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_TXCTPR(i))); | |
111 | } | |
112 | printk("\nRX|"); | |
113 | for (i = 0; i < maldata->num_rx_chans; ++i) { | |
114 | if (i && !(i % 4)) | |
115 | printk("\n "); | |
116 | printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_RXCTPR(i))); | |
117 | } | |
118 | printk("\n "); | |
119 | for (i = 0; i < maldata->num_rx_chans; ++i) { | |
120 | u32 r = get_mal_dcrn(mal, MAL_RCBS(i)); | |
121 | if (i && !(i % 3)) | |
122 | printk("\n "); | |
123 | printk("RCBS%d = 0x%08x (%d) ", i, r, r * 16); | |
124 | } | |
125 | printk("\n"); | |
126 | } | |
127 | ||
128 | static struct ocp_enet_private *__emacs[4]; | |
129 | static struct ibm_ocp_mal *__mals[1]; | |
1da177e4 | 130 | |
37448f7d | 131 | void emac_dbg_register(int idx, struct ocp_enet_private *dev) |
1da177e4 | 132 | { |
37448f7d ES |
133 | unsigned long flags; |
134 | ||
135 | if (idx >= sizeof(__emacs) / sizeof(__emacs[0])) { | |
136 | printk(KERN_WARNING | |
137 | "invalid index %d when registering EMAC for debugging\n", | |
138 | idx); | |
139 | return; | |
1da177e4 | 140 | } |
37448f7d ES |
141 | |
142 | local_irq_save(flags); | |
143 | __emacs[idx] = dev; | |
144 | local_irq_restore(flags); | |
1da177e4 LT |
145 | } |
146 | ||
37448f7d | 147 | void mal_dbg_register(int idx, struct ibm_ocp_mal *mal) |
1da177e4 | 148 | { |
37448f7d ES |
149 | unsigned long flags; |
150 | ||
151 | if (idx >= sizeof(__mals) / sizeof(__mals[0])) { | |
152 | printk(KERN_WARNING | |
153 | "invalid index %d when registering MAL for debugging\n", | |
154 | idx); | |
155 | return; | |
1da177e4 | 156 | } |
37448f7d ES |
157 | |
158 | local_irq_save(flags); | |
159 | __mals[idx] = mal; | |
160 | local_irq_restore(flags); | |
1da177e4 LT |
161 | } |
162 | ||
37448f7d | 163 | void emac_dbg_dump_all(void) |
1da177e4 | 164 | { |
37448f7d ES |
165 | unsigned int i; |
166 | unsigned long flags; | |
167 | ||
168 | local_irq_save(flags); | |
169 | ||
170 | for (i = 0; i < sizeof(__mals) / sizeof(__mals[0]); ++i) | |
171 | if (__mals[i]) | |
172 | emac_mal_dump(__mals[i]); | |
173 | ||
174 | for (i = 0; i < sizeof(__emacs) / sizeof(__emacs[0]); ++i) | |
175 | if (__emacs[i]) | |
176 | emac_mac_dump(i, __emacs[i]); | |
177 | ||
178 | local_irq_restore(flags); | |
1da177e4 LT |
179 | } |
180 | ||
37448f7d | 181 | #if defined(CONFIG_MAGIC_SYSRQ) |
7d12e780 | 182 | static void emac_sysrq_handler(int key, struct tty_struct *tty) |
1da177e4 | 183 | { |
37448f7d | 184 | emac_dbg_dump_all(); |
1da177e4 LT |
185 | } |
186 | ||
37448f7d ES |
187 | static struct sysrq_key_op emac_sysrq_op = { |
188 | .handler = emac_sysrq_handler, | |
189 | .help_msg = "emaC", | |
190 | .action_msg = "Show EMAC(s) status", | |
191 | }; | |
192 | ||
193 | int __init emac_init_debug(void) | |
1da177e4 | 194 | { |
37448f7d | 195 | return register_sysrq_key('c', &emac_sysrq_op); |
1da177e4 LT |
196 | } |
197 | ||
37448f7d | 198 | void __exit emac_fini_debug(void) |
1da177e4 | 199 | { |
37448f7d | 200 | unregister_sysrq_key('c', &emac_sysrq_op); |
1da177e4 LT |
201 | } |
202 | ||
37448f7d ES |
203 | #else |
204 | int __init emac_init_debug(void) | |
205 | { | |
206 | return 0; | |
207 | } | |
208 | void __exit emac_fini_debug(void) | |
1da177e4 | 209 | { |
1da177e4 | 210 | } |
37448f7d | 211 | #endif /* CONFIG_MAGIC_SYSRQ */ |