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1/* hamachi.c: A Packet Engines GNIC-II Gigabit Ethernet driver for Linux. */
2/*
3 Written 1998-2000 by Donald Becker.
4 Updates 2000 by Keith Underwood.
5
6aa20a22 6 This software may be used and distributed according to the terms of
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7 the GNU General Public License (GPL), incorporated herein by reference.
8 Drivers based on or derived from this code fall under the GPL and must
9 retain the authorship, copyright and license notice. This file is not
10 a complete program and may only be used when the entire operating
11 system is licensed under the GPL.
12
13 The author may be reached as becker@scyld.com, or C/O
14 Scyld Computing Corporation
15 410 Severn Ave., Suite 210
16 Annapolis MD 21403
17
18 This driver is for the Packet Engines GNIC-II PCI Gigabit Ethernet
19 adapter.
20
21 Support and updates available at
22 http://www.scyld.com/network/hamachi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
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24 or
25 http://www.parl.clemson.edu/~keithu/hamachi.html
26
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27*/
28
29#define DRV_NAME "hamachi"
d5b20697
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30#define DRV_VERSION "2.1"
31#define DRV_RELDATE "Sept 11, 2006"
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32
33
34/* A few user-configurable values. */
35
36static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
37#define final_version
38#define hamachi_debug debug
39/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
40static int max_interrupt_work = 40;
41static int mtu;
42/* Default values selected by testing on a dual processor PIII-450 */
43/* These six interrupt control parameters may be set directly when loading the
44 * module, or through the rx_params and tx_params variables
45 */
46static int max_rx_latency = 0x11;
47static int max_rx_gap = 0x05;
48static int min_rx_pkt = 0x18;
6aa20a22 49static int max_tx_latency = 0x00;
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50static int max_tx_gap = 0x00;
51static int min_tx_pkt = 0x30;
52
53/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
54 -Setting to > 1518 causes all frames to be copied
55 -Setting to 0 disables copies
56*/
57static int rx_copybreak;
58
59/* An override for the hardware detection of bus width.
60 Set to 1 to force 32 bit PCI bus detection. Set to 4 to force 64 bit.
61 Add 2 to disable parity detection.
62*/
63static int force32;
64
65
66/* Used to pass the media type, etc.
67 These exist for driver interoperability.
68 No media types are currently defined.
69 - The lower 4 bits are reserved for the media type.
70 - The next three bits may be set to one of the following:
71 0x00000000 : Autodetect PCI bus
72 0x00000010 : Force 32 bit PCI bus
73 0x00000020 : Disable parity detection
74 0x00000040 : Force 64 bit PCI bus
75 Default is autodetect
76 - The next bit can be used to force half-duplex. This is a bad
77 idea since no known implementations implement half-duplex, and,
78 in general, half-duplex for gigabit ethernet is a bad idea.
6aa20a22 79 0x00000080 : Force half-duplex
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80 Default is full-duplex.
81 - In the original driver, the ninth bit could be used to force
82 full-duplex. Maintain that for compatibility
83 0x00000200 : Force full-duplex
84*/
85#define MAX_UNITS 8 /* More are supported, limit only on options */
86static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
88/* The Hamachi chipset supports 3 parameters each for Rx and Tx
89 * interruput management. Parameters will be loaded as specified into
6aa20a22 90 * the TxIntControl and RxIntControl registers.
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91 *
92 * The registers are arranged as follows:
93 * 23 - 16 15 - 8 7 - 0
94 * _________________________________
95 * | min_pkt | max_gap | max_latency |
96 * ---------------------------------
97 * min_pkt : The minimum number of packets processed between
6aa20a22 98 * interrupts.
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99 * max_gap : The maximum inter-packet gap in units of 8.192 us
100 * max_latency : The absolute time between interrupts in units of 8.192 us
6aa20a22 101 *
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102 */
103static int rx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
104static int tx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
105
106/* Operational parameters that are set at compile time. */
107
108/* Keep the ring sizes a power of two for compile efficiency.
109 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
110 Making the Tx ring too large decreases the effectiveness of channel
111 bonding and packet priority.
112 There are no ill effects from too-large receive rings, except for
113 excessive memory usage */
114/* Empirically it appears that the Tx ring needs to be a little bigger
115 for these Gbit adapters or you get into an overrun condition really
116 easily. Also, things appear to work a bit better in back-to-back
117 configurations if the Rx ring is 8 times the size of the Tx ring
118*/
119#define TX_RING_SIZE 64
120#define RX_RING_SIZE 512
121#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct hamachi_desc)
122#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct hamachi_desc)
123
124/*
125 * Enable netdev_ioctl. Added interrupt coalescing parameter adjustment.
126 * 2/19/99 Pete Wyckoff <wyckoff@ca.sandia.gov>
127 */
128
129/* play with 64-bit addrlen; seems to be a teensy bit slower --pw */
130/* #define ADDRLEN 64 */
131
132/*
133 * RX_CHECKSUM turns on card-generated receive checksum generation for
134 * TCP and UDP packets. Otherwise the upper layers do the calculation.
135 * TX_CHECKSUM won't do anything too useful, even if it works. There's no
136 * easy mechanism by which to tell the TCP/UDP stack that it need not
137 * generate checksums for this device. But if somebody can find a way
138 * to get that to work, most of the card work is in here already.
139 * 3/10/1999 Pete Wyckoff <wyckoff@ca.sandia.gov>
140 */
141#undef TX_CHECKSUM
142#define RX_CHECKSUM
143
144/* Operational parameters that usually are not changed. */
145/* Time in jiffies before concluding the transmitter is hung. */
146#define TX_TIMEOUT (5*HZ)
147
148#include <linux/module.h>
149#include <linux/kernel.h>
150#include <linux/string.h>
151#include <linux/timer.h>
152#include <linux/time.h>
153#include <linux/errno.h>
154#include <linux/ioport.h>
155#include <linux/slab.h>
156#include <linux/interrupt.h>
157#include <linux/pci.h>
158#include <linux/init.h>
159#include <linux/ethtool.h>
160#include <linux/mii.h>
161#include <linux/netdevice.h>
162#include <linux/etherdevice.h>
163#include <linux/skbuff.h>
164#include <linux/ip.h>
165#include <linux/delay.h>
166#include <linux/bitops.h>
167
168#include <asm/uaccess.h>
169#include <asm/processor.h> /* Processor type for cache alignment. */
170#include <asm/io.h>
171#include <asm/unaligned.h>
172#include <asm/cache.h>
173
98683956 174static const char version[] __devinitconst =
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175KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"
176KERN_INFO " Some modifications by Eric kasten <kasten@nscl.msu.edu>\n"
177KERN_INFO " Further modifications by Keith Underwood <keithu@parl.clemson.edu>\n";
178
179
180/* IP_MF appears to be only defined in <netinet/ip.h>, however,
181 we need it for hardware checksumming support. FYI... some of
182 the definitions in <netinet/ip.h> conflict/duplicate those in
183 other linux headers causing many compiler warnings.
184*/
185#ifndef IP_MF
6aa20a22 186 #define IP_MF 0x2000 /* IP more frags from <netinet/ip.h> */
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187#endif
188
189/* Define IP_OFFSET to be IPOPT_OFFSET */
190#ifndef IP_OFFSET
191 #ifdef IPOPT_OFFSET
192 #define IP_OFFSET IPOPT_OFFSET
193 #else
194 #define IP_OFFSET 2
195 #endif
196#endif
197
198#define RUN_AT(x) (jiffies + (x))
199
f20badbe
AV
200#ifndef ADDRLEN
201#define ADDRLEN 32
202#endif
203
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204/* Condensed bus+endian portability operations. */
205#if ADDRLEN == 64
206#define cpu_to_leXX(addr) cpu_to_le64(addr)
8e985918 207#define leXX_to_cpu(addr) le64_to_cpu(addr)
6aa20a22 208#else
1da177e4 209#define cpu_to_leXX(addr) cpu_to_le32(addr)
8e985918 210#define leXX_to_cpu(addr) le32_to_cpu(addr)
6aa20a22 211#endif
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212
213
214/*
215 Theory of Operation
216
217I. Board Compatibility
218
219This device driver is designed for the Packet Engines "Hamachi"
220Gigabit Ethernet chip. The only PCA currently supported is the GNIC-II 64-bit
22166Mhz PCI card.
222
223II. Board-specific settings
224
225No jumpers exist on the board. The chip supports software correction of
226various motherboard wiring errors, however this driver does not support
227that feature.
228
229III. Driver operation
230
231IIIa. Ring buffers
232
233The Hamachi uses a typical descriptor based bus-master architecture.
234The descriptor list is similar to that used by the Digital Tulip.
235This driver uses two statically allocated fixed-size descriptor lists
236formed into rings by a branch from the final descriptor to the beginning of
237the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
238
239This driver uses a zero-copy receive and transmit scheme similar my other
240network drivers.
241The driver allocates full frame size skbuffs for the Rx ring buffers at
242open() time and passes the skb->data field to the Hamachi as receive data
243buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
244a fresh skbuff is allocated and the frame is copied to the new skbuff.
245When the incoming frame is larger, the skbuff is passed directly up the
246protocol stack and replaced by a newly allocated skbuff.
247
248The RX_COPYBREAK value is chosen to trade-off the memory wasted by
249using a full-sized skbuff for small frames vs. the copying costs of larger
250frames. Gigabit cards are typically used on generously configured machines
251and the underfilled buffers have negligible impact compared to the benefit of
252a single allocation size, so the default value of zero results in never
253copying packets.
254
255IIIb/c. Transmit/Receive Structure
256
257The Rx and Tx descriptor structure are straight-forward, with no historical
258baggage that must be explained. Unlike the awkward DBDMA structure, there
259are no unused fields or option bits that had only one allowable setting.
260
261Two details should be noted about the descriptors: The chip supports both 32
262bit and 64 bit address structures, and the length field is overwritten on
263the receive descriptors. The descriptor length is set in the control word
264for each channel. The development driver uses 32 bit addresses only, however
26564 bit addresses may be enabled for 64 bit architectures e.g. the Alpha.
266
267IIId. Synchronization
268
269This driver is very similar to my other network drivers.
270The driver runs as two independent, single-threaded flows of control. One
271is the send-packet routine, which enforces single-threaded use by the
272dev->tbusy flag. The other thread is the interrupt handler, which is single
273threaded by the hardware and other software.
274
275The send packet thread has partial control over the Tx ring and 'dev->tbusy'
276flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
277queue slot is empty, it clears the tbusy flag when finished otherwise it sets
278the 'hmp->tx_full' flag.
279
280The interrupt handler has exclusive control over the Rx ring and records stats
281from the Tx ring. After reaping the stats, it marks the Tx queue entry as
282empty by incrementing the dirty_tx mark. Iff the 'hmp->tx_full' flag is set, it
283clears both the tx_full and tbusy flags.
284
285IV. Notes
286
287Thanks to Kim Stearns of Packet Engines for providing a pair of GNIC-II boards.
288
289IVb. References
290
291Hamachi Engineering Design Specification, 5/15/97
292(Note: This version was marked "Confidential".)
293
294IVc. Errata
295
6aa20a22 296None noted.
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297
298V. Recent Changes
299
6aa20a22 30001/15/1999 EPK Enlargement of the TX and RX ring sizes. This appears
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301 to help avoid some stall conditions -- this needs further research.
302
6aa20a22 30301/15/1999 EPK Creation of the hamachi_tx function. This function cleans
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304 the Tx ring and is called from hamachi_start_xmit (this used to be
305 called from hamachi_interrupt but it tends to delay execution of the
306 interrupt handler and thus reduce bandwidth by reducing the latency
6aa20a22
JG
307 between hamachi_rx()'s). Notably, some modification has been made so
308 that the cleaning loop checks only to make sure that the DescOwn bit
309 isn't set in the status flag since the card is not required
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310 to set the entire flag to zero after processing.
311
6aa20a22 31201/15/1999 EPK In the hamachi_start_tx function, the Tx ring full flag is
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313 checked before attempting to add a buffer to the ring. If the ring is full
314 an attempt is made to free any dirty buffers and thus find space for
315 the new buffer or the function returns non-zero which should case the
316 scheduler to reschedule the buffer later.
317
6aa20a22
JG
31801/15/1999 EPK Some adjustments were made to the chip initialization.
319 End-to-end flow control should now be fully active and the interrupt
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320 algorithm vars have been changed. These could probably use further tuning.
321
32201/15/1999 EPK Added the max_{rx,tx}_latency options. These are used to
323 set the rx and tx latencies for the Hamachi interrupts. If you're having
324 problems with network stalls, try setting these to higher values.
325 Valid values are 0x00 through 0xff.
326
6aa20a22 32701/15/1999 EPK In general, the overall bandwidth has increased and
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328 latencies are better (sometimes by a factor of 2). Stalls are rare at
329 this point, however there still appears to be a bug somewhere between the
330 hardware and driver. TCP checksum errors under load also appear to be
331 eliminated at this point.
332
33301/18/1999 EPK Ensured that the DescEndRing bit was being set on both the
334 Rx and Tx rings. This appears to have been affecting whether a particular
335 peer-to-peer connection would hang under high load. I believe the Rx
336 rings was typically getting set correctly, but the Tx ring wasn't getting
337 the DescEndRing bit set during initialization. ??? Does this mean the
338 hamachi card is using the DescEndRing in processing even if a particular
6aa20a22 339 slot isn't in use -- hypothetically, the card might be searching the
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340 entire Tx ring for slots with the DescOwn bit set and then processing
341 them. If the DescEndRing bit isn't set, then it might just wander off
342 through memory until it hits a chunk of data with that bit set
343 and then looping back.
344
6aa20a22 34502/09/1999 EPK Added Michel Mueller's TxDMA Interrupt and Tx-timeout
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346 problem (TxCmd and RxCmd need only to be set when idle or stopped.
347
34802/09/1999 EPK Added code to check/reset dev->tbusy in hamachi_interrupt.
6aa20a22 349 (Michel Mueller pointed out the ``permanently busy'' potential
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350 problem here).
351
6aa20a22 35202/22/1999 EPK Added Pete Wyckoff's ioctl to control the Tx/Rx latencies.
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353
35402/23/1999 EPK Verified that the interrupt status field bits for Tx were
355 incorrectly defined and corrected (as per Michel Mueller).
356
35702/23/1999 EPK Corrected the Tx full check to check that at least 4 slots
358 were available before reseting the tbusy and tx_full flags
359 (as per Michel Mueller).
360
36103/11/1999 EPK Added Pete Wyckoff's hardware checksumming support.
362
36312/31/1999 KDU Cleaned up assorted things and added Don's code to force
36432 bit.
365
36602/20/2000 KDU Some of the control was just plain odd. Cleaned up the
367hamachi_start_xmit() and hamachi_interrupt() code. There is still some
6aa20a22 368re-structuring I would like to do.
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369
37003/01/2000 KDU Experimenting with a WIDE range of interrupt mitigation
371parameters on a dual P3-450 setup yielded the new default interrupt
372mitigation parameters. Tx should interrupt VERY infrequently due to
373Eric's scheme. Rx should be more often...
374
37503/13/2000 KDU Added a patch to make the Rx Checksum code interact
6aa20a22 376nicely with non-linux machines.
1da177e4 377
6aa20a22 37803/13/2000 KDU Experimented with some of the configuration values:
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379
380 -It seems that enabling PCI performance commands for descriptors
6aa20a22
JG
381 (changing RxDMACtrl and TxDMACtrl lower nibble from 5 to D) has minimal
382 performance impact for any of my tests. (ttcp, netpipe, netperf) I will
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383 leave them that way until I hear further feedback.
384
6aa20a22 385 -Increasing the PCI_LATENCY_TIMER to 130
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386 (2 + (burst size of 128 * (0 wait states + 1))) seems to slightly
387 degrade performance. Leaving default at 64 pending further information.
388
6aa20a22 38903/14/2000 KDU Further tuning:
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390
391 -adjusted boguscnt in hamachi_rx() to depend on interrupt
392 mitigation parameters chosen.
393
6aa20a22 394 -Selected a set of interrupt parameters based on some extensive testing.
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395 These may change with more testing.
396
397TO DO:
398
399-Consider borrowing from the acenic driver code to check PCI_COMMAND for
400PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in
401that case.
402
6aa20a22 403-fix the reset procedure. It doesn't quite work.
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404*/
405
406/* A few values that may be tweaked. */
407/* Size of each temporary Rx buffer, calculated as:
408 * 1518 bytes (ethernet packet) + 2 bytes (to get 8 byte alignment for
409 * the card) + 8 bytes of status info + 8 bytes for the Rx Checksum +
6aa20a22 410 * 2 more because we use skb_reserve.
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411 */
412#define PKT_BUF_SZ 1538
413
414/* For now, this is going to be set to the maximum size of an ethernet
415 * packet. Eventually, we may want to make it a variable that is
416 * related to the MTU
417 */
418#define MAX_FRAME_SIZE 1518
419
420/* The rest of these values should never change. */
421
422static void hamachi_timer(unsigned long data);
423
424enum capability_flags {CanHaveMII=1, };
f71e1309 425static const struct chip_info {
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426 u16 vendor_id, device_id, device_id_mask, pad;
427 const char *name;
428 void (*media_timer)(unsigned long data);
429 int flags;
430} chip_tbl[] = {
431 {0x1318, 0x0911, 0xffff, 0, "Hamachi GNIC-II", hamachi_timer, 0},
432 {0,},
433};
434
435/* Offsets to the Hamachi registers. Various sizes. */
436enum hamachi_offsets {
437 TxDMACtrl=0x00, TxCmd=0x04, TxStatus=0x06, TxPtr=0x08, TxCurPtr=0x10,
438 RxDMACtrl=0x20, RxCmd=0x24, RxStatus=0x26, RxPtr=0x28, RxCurPtr=0x30,
439 PCIClkMeas=0x060, MiscStatus=0x066, ChipRev=0x68, ChipReset=0x06B,
440 LEDCtrl=0x06C, VirtualJumpers=0x06D, GPIO=0x6E,
441 TxChecksum=0x074, RxChecksum=0x076,
442 TxIntrCtrl=0x078, RxIntrCtrl=0x07C,
443 InterruptEnable=0x080, InterruptClear=0x084, IntrStatus=0x088,
444 EventStatus=0x08C,
445 MACCnfg=0x0A0, FrameGap0=0x0A2, FrameGap1=0x0A4,
446 /* See enum MII_offsets below. */
447 MACCnfg2=0x0B0, RxDepth=0x0B8, FlowCtrl=0x0BC, MaxFrameSize=0x0CE,
448 AddrMode=0x0D0, StationAddr=0x0D2,
449 /* Gigabit AutoNegotiation. */
450 ANCtrl=0x0E0, ANStatus=0x0E2, ANXchngCtrl=0x0E4, ANAdvertise=0x0E8,
451 ANLinkPartnerAbility=0x0EA,
452 EECmdStatus=0x0F0, EEData=0x0F1, EEAddr=0x0F2,
453 FIFOcfg=0x0F8,
454};
455
456/* Offsets to the MII-mode registers. */
457enum MII_offsets {
458 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
459 MII_Status=0xAE,
460};
461
462/* Bits in the interrupt status/mask registers. */
463enum intr_status_bits {
464 IntrRxDone=0x01, IntrRxPCIFault=0x02, IntrRxPCIErr=0x04,
465 IntrTxDone=0x100, IntrTxPCIFault=0x200, IntrTxPCIErr=0x400,
466 LinkChange=0x10000, NegotiationChange=0x20000, StatsMax=0x40000, };
467
468/* The Hamachi Rx and Tx buffer descriptors. */
469struct hamachi_desc {
8e985918 470 __le32 status_n_length;
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471#if ADDRLEN == 64
472 u32 pad;
8e985918 473 __le64 addr;
1da177e4 474#else
8e985918 475 __le32 addr;
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476#endif
477};
478
479/* Bits in hamachi_desc.status_n_length */
480enum desc_status_bits {
6aa20a22 481 DescOwn=0x80000000, DescEndPacket=0x40000000, DescEndRing=0x20000000,
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482 DescIntr=0x10000000,
483};
484
485#define PRIV_ALIGN 15 /* Required alignment mask */
486#define MII_CNT 4
487struct hamachi_private {
488 /* Descriptor rings first for alignment. Tx requires a second descriptor
489 for status. */
490 struct hamachi_desc *rx_ring;
491 struct hamachi_desc *tx_ring;
492 struct sk_buff* rx_skbuff[RX_RING_SIZE];
493 struct sk_buff* tx_skbuff[TX_RING_SIZE];
494 dma_addr_t tx_ring_dma;
495 dma_addr_t rx_ring_dma;
496 struct net_device_stats stats;
497 struct timer_list timer; /* Media selection timer. */
498 /* Frequently used and paired value: keep adjacent for cache effect. */
499 spinlock_t lock;
500 int chip_id;
501 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
502 unsigned int cur_tx, dirty_tx;
503 unsigned int rx_buf_sz; /* Based on MTU+slack. */
504 unsigned int tx_full:1; /* The Tx queue is full. */
505 unsigned int duplex_lock:1;
506 unsigned int default_port:4; /* Last dev->if_port value. */
507 /* MII transceiver section. */
508 int mii_cnt; /* MII device addresses. */
509 struct mii_if_info mii_if; /* MII lib hooks/info */
510 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
511 u32 rx_int_var, tx_int_var; /* interrupt control variables */
512 u32 option; /* Hold on to a copy of the options */
513 struct pci_dev *pci_dev;
514 void __iomem *base;
515};
516
517MODULE_AUTHOR("Donald Becker <becker@scyld.com>, Eric Kasten <kasten@nscl.msu.edu>, Keith Underwood <keithu@parl.clemson.edu>");
518MODULE_DESCRIPTION("Packet Engines 'Hamachi' GNIC-II Gigabit Ethernet driver");
519MODULE_LICENSE("GPL");
520
521module_param(max_interrupt_work, int, 0);
522module_param(mtu, int, 0);
523module_param(debug, int, 0);
524module_param(min_rx_pkt, int, 0);
525module_param(max_rx_gap, int, 0);
526module_param(max_rx_latency, int, 0);
527module_param(min_tx_pkt, int, 0);
528module_param(max_tx_gap, int, 0);
529module_param(max_tx_latency, int, 0);
530module_param(rx_copybreak, int, 0);
531module_param_array(rx_params, int, NULL, 0);
532module_param_array(tx_params, int, NULL, 0);
533module_param_array(options, int, NULL, 0);
534module_param_array(full_duplex, int, NULL, 0);
535module_param(force32, int, 0);
536MODULE_PARM_DESC(max_interrupt_work, "GNIC-II maximum events handled per interrupt");
537MODULE_PARM_DESC(mtu, "GNIC-II MTU (all boards)");
538MODULE_PARM_DESC(debug, "GNIC-II debug level (0-7)");
539MODULE_PARM_DESC(min_rx_pkt, "GNIC-II minimum Rx packets processed between interrupts");
540MODULE_PARM_DESC(max_rx_gap, "GNIC-II maximum Rx inter-packet gap in 8.192 microsecond units");
541MODULE_PARM_DESC(max_rx_latency, "GNIC-II time between Rx interrupts in 8.192 microsecond units");
542MODULE_PARM_DESC(min_tx_pkt, "GNIC-II minimum Tx packets processed between interrupts");
543MODULE_PARM_DESC(max_tx_gap, "GNIC-II maximum Tx inter-packet gap in 8.192 microsecond units");
544MODULE_PARM_DESC(max_tx_latency, "GNIC-II time between Tx interrupts in 8.192 microsecond units");
545MODULE_PARM_DESC(rx_copybreak, "GNIC-II copy breakpoint for copy-only-tiny-frames");
546MODULE_PARM_DESC(rx_params, "GNIC-II min_rx_pkt+max_rx_gap+max_rx_latency");
547MODULE_PARM_DESC(tx_params, "GNIC-II min_tx_pkt+max_tx_gap+max_tx_latency");
548MODULE_PARM_DESC(options, "GNIC-II Bits 0-3: media type, bits 4-6: as force32, bit 7: half duplex, bit 9 full duplex");
549MODULE_PARM_DESC(full_duplex, "GNIC-II full duplex setting(s) (1)");
550MODULE_PARM_DESC(force32, "GNIC-II: Bit 0: 32 bit PCI, bit 1: disable parity, bit 2: 64 bit PCI (all boards)");
6aa20a22 551
1da177e4
LT
552static int read_eeprom(void __iomem *ioaddr, int location);
553static int mdio_read(struct net_device *dev, int phy_id, int location);
554static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
555static int hamachi_open(struct net_device *dev);
556static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
557static void hamachi_timer(unsigned long data);
558static void hamachi_tx_timeout(struct net_device *dev);
559static void hamachi_init_ring(struct net_device *dev);
560static int hamachi_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 561static irqreturn_t hamachi_interrupt(int irq, void *dev_instance);
1da177e4
LT
562static int hamachi_rx(struct net_device *dev);
563static inline int hamachi_tx(struct net_device *dev);
564static void hamachi_error(struct net_device *dev, int intr_status);
565static int hamachi_close(struct net_device *dev);
566static struct net_device_stats *hamachi_get_stats(struct net_device *dev);
567static void set_rx_mode(struct net_device *dev);
7282d491
JG
568static const struct ethtool_ops ethtool_ops;
569static const struct ethtool_ops ethtool_ops_no_mii;
1da177e4 570
a8652d23
SH
571static const struct net_device_ops hamachi_netdev_ops = {
572 .ndo_open = hamachi_open,
573 .ndo_stop = hamachi_close,
574 .ndo_start_xmit = hamachi_start_xmit,
575 .ndo_get_stats = hamachi_get_stats,
576 .ndo_set_multicast_list = set_rx_mode,
577 .ndo_change_mtu = eth_change_mtu,
578 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 579 .ndo_set_mac_address = eth_mac_addr,
a8652d23
SH
580 .ndo_tx_timeout = hamachi_tx_timeout,
581 .ndo_do_ioctl = netdev_ioctl,
582};
583
584
1da177e4
LT
585static int __devinit hamachi_init_one (struct pci_dev *pdev,
586 const struct pci_device_id *ent)
587{
588 struct hamachi_private *hmp;
589 int option, i, rx_int_var, tx_int_var, boguscnt;
590 int chip_id = ent->driver_data;
591 int irq;
592 void __iomem *ioaddr;
593 unsigned long base;
594 static int card_idx;
595 struct net_device *dev;
596 void *ring_space;
597 dma_addr_t ring_dma;
598 int ret = -ENOMEM;
599
600/* when built into the kernel, we only print version if device is found */
601#ifndef MODULE
602 static int printed_version;
603 if (!printed_version++)
604 printk(version);
605#endif
606
607 if (pci_enable_device(pdev)) {
608 ret = -EIO;
609 goto err_out;
610 }
611
612 base = pci_resource_start(pdev, 0);
613#ifdef __alpha__ /* Really "64 bit addrs" */
614 base |= (pci_resource_start(pdev, 1) << 32);
615#endif
616
617 pci_set_master(pdev);
618
619 i = pci_request_regions(pdev, DRV_NAME);
2e8a538d
JG
620 if (i)
621 return i;
1da177e4
LT
622
623 irq = pdev->irq;
624 ioaddr = ioremap(base, 0x400);
625 if (!ioaddr)
626 goto err_out_release;
627
628 dev = alloc_etherdev(sizeof(struct hamachi_private));
629 if (!dev)
630 goto err_out_iounmap;
631
1da177e4
LT
632 SET_NETDEV_DEV(dev, &pdev->dev);
633
634#ifdef TX_CHECKSUM
635 printk("check that skbcopy in ip_queue_xmit isn't happening\n");
636 dev->hard_header_len += 8; /* for cksum tag */
637#endif
638
639 for (i = 0; i < 6; i++)
640 dev->dev_addr[i] = 1 ? read_eeprom(ioaddr, 4 + i)
641 : readb(ioaddr + StationAddr + i);
642
643#if ! defined(final_version)
644 if (hamachi_debug > 4)
645 for (i = 0; i < 0x10; i++)
646 printk("%2.2x%s",
647 read_eeprom(ioaddr, i), i % 16 != 15 ? " " : "\n");
648#endif
649
650 hmp = netdev_priv(dev);
651 spin_lock_init(&hmp->lock);
652
653 hmp->mii_if.dev = dev;
654 hmp->mii_if.mdio_read = mdio_read;
655 hmp->mii_if.mdio_write = mdio_write;
656 hmp->mii_if.phy_id_mask = 0x1f;
657 hmp->mii_if.reg_num_mask = 0x1f;
658
659 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
660 if (!ring_space)
661 goto err_out_cleardev;
662 hmp->tx_ring = (struct hamachi_desc *)ring_space;
663 hmp->tx_ring_dma = ring_dma;
664
665 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
666 if (!ring_space)
667 goto err_out_unmap_tx;
668 hmp->rx_ring = (struct hamachi_desc *)ring_space;
669 hmp->rx_ring_dma = ring_dma;
670
671 /* Check for options being passed in */
672 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
673 if (dev->mem_start)
674 option = dev->mem_start;
675
676 /* If the bus size is misidentified, do the following. */
6aa20a22 677 force32 = force32 ? force32 :
1da177e4
LT
678 ((option >= 0) ? ((option & 0x00000070) >> 4) : 0 );
679 if (force32)
680 writeb(force32, ioaddr + VirtualJumpers);
681
682 /* Hmmm, do we really need to reset the chip???. */
683 writeb(0x01, ioaddr + ChipReset);
684
685 /* After a reset, the clock speed measurement of the PCI bus will not
686 * be valid for a moment. Wait for a little while until it is. If
687 * it takes more than 10ms, forget it.
688 */
6aa20a22 689 udelay(10);
1da177e4
LT
690 i = readb(ioaddr + PCIClkMeas);
691 for (boguscnt = 0; (!(i & 0x080)) && boguscnt < 1000; boguscnt++){
6aa20a22
JG
692 udelay(10);
693 i = readb(ioaddr + PCIClkMeas);
1da177e4
LT
694 }
695
696 hmp->base = ioaddr;
697 dev->base_addr = (unsigned long)ioaddr;
698 dev->irq = irq;
699 pci_set_drvdata(pdev, dev);
700
701 hmp->chip_id = chip_id;
702 hmp->pci_dev = pdev;
703
704 /* The lower four bits are the media type. */
705 if (option > 0) {
706 hmp->option = option;
707 if (option & 0x200)
708 hmp->mii_if.full_duplex = 1;
709 else if (option & 0x080)
710 hmp->mii_if.full_duplex = 0;
711 hmp->default_port = option & 15;
712 if (hmp->default_port)
713 hmp->mii_if.force_media = 1;
714 }
715 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
716 hmp->mii_if.full_duplex = 1;
717
718 /* lock the duplex mode if someone specified a value */
719 if (hmp->mii_if.full_duplex || (option & 0x080))
720 hmp->duplex_lock = 1;
721
722 /* Set interrupt tuning parameters */
723 max_rx_latency = max_rx_latency & 0x00ff;
724 max_rx_gap = max_rx_gap & 0x00ff;
725 min_rx_pkt = min_rx_pkt & 0x00ff;
726 max_tx_latency = max_tx_latency & 0x00ff;
727 max_tx_gap = max_tx_gap & 0x00ff;
728 min_tx_pkt = min_tx_pkt & 0x00ff;
729
730 rx_int_var = card_idx < MAX_UNITS ? rx_params[card_idx] : -1;
731 tx_int_var = card_idx < MAX_UNITS ? tx_params[card_idx] : -1;
6aa20a22 732 hmp->rx_int_var = rx_int_var >= 0 ? rx_int_var :
1da177e4 733 (min_rx_pkt << 16 | max_rx_gap << 8 | max_rx_latency);
6aa20a22 734 hmp->tx_int_var = tx_int_var >= 0 ? tx_int_var :
1da177e4
LT
735 (min_tx_pkt << 16 | max_tx_gap << 8 | max_tx_latency);
736
737
738 /* The Hamachi-specific entries in the device structure. */
a8652d23 739 dev->netdev_ops = &hamachi_netdev_ops;
1da177e4
LT
740 if (chip_tbl[hmp->chip_id].flags & CanHaveMII)
741 SET_ETHTOOL_OPS(dev, &ethtool_ops);
742 else
743 SET_ETHTOOL_OPS(dev, &ethtool_ops_no_mii);
1da177e4
LT
744 dev->watchdog_timeo = TX_TIMEOUT;
745 if (mtu)
746 dev->mtu = mtu;
747
748 i = register_netdev(dev);
749 if (i) {
750 ret = i;
751 goto err_out_unmap_rx;
752 }
753
e174961c 754 printk(KERN_INFO "%s: %s type %x at %p, %pM, IRQ %d.\n",
1da177e4 755 dev->name, chip_tbl[chip_id].name, readl(ioaddr + ChipRev),
e174961c 756 ioaddr, dev->dev_addr, irq);
1da177e4
LT
757 i = readb(ioaddr + PCIClkMeas);
758 printk(KERN_INFO "%s: %d-bit %d Mhz PCI bus (%d), Virtual Jumpers "
759 "%2.2x, LPA %4.4x.\n",
760 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32,
761 i ? 2000/(i&0x7f) : 0, i&0x7f, (int)readb(ioaddr + VirtualJumpers),
762 readw(ioaddr + ANLinkPartnerAbility));
763
764 if (chip_tbl[hmp->chip_id].flags & CanHaveMII) {
765 int phy, phy_idx = 0;
766 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
767 int mii_status = mdio_read(dev, phy, MII_BMSR);
768 if (mii_status != 0xffff &&
769 mii_status != 0x0000) {
770 hmp->phys[phy_idx++] = phy;
771 hmp->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
772 printk(KERN_INFO "%s: MII PHY found at address %d, status "
773 "0x%4.4x advertising %4.4x.\n",
774 dev->name, phy, mii_status, hmp->mii_if.advertising);
775 }
776 }
777 hmp->mii_cnt = phy_idx;
778 if (hmp->mii_cnt > 0)
779 hmp->mii_if.phy_id = hmp->phys[0];
780 else
781 memset(&hmp->mii_if, 0, sizeof(hmp->mii_if));
782 }
783 /* Configure gigabit autonegotiation. */
784 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
785 writew(0x08e0, ioaddr + ANAdvertise); /* Set our advertise word. */
786 writew(0x1000, ioaddr + ANCtrl); /* Enable negotiation */
787
788 card_idx++;
789 return 0;
790
791err_out_unmap_rx:
6aa20a22 792 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1da177e4
LT
793 hmp->rx_ring_dma);
794err_out_unmap_tx:
6aa20a22 795 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1da177e4
LT
796 hmp->tx_ring_dma);
797err_out_cleardev:
798 free_netdev (dev);
799err_out_iounmap:
800 iounmap(ioaddr);
801err_out_release:
802 pci_release_regions(pdev);
803err_out:
804 return ret;
805}
806
807static int __devinit read_eeprom(void __iomem *ioaddr, int location)
808{
809 int bogus_cnt = 1000;
810
811 /* We should check busy first - per docs -KDU */
812 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
813 writew(location, ioaddr + EEAddr);
814 writeb(0x02, ioaddr + EECmdStatus);
815 bogus_cnt = 1000;
816 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
817 if (hamachi_debug > 5)
818 printk(" EEPROM status is %2.2x after %d ticks.\n",
819 (int)readb(ioaddr + EECmdStatus), 1000- bogus_cnt);
820 return readb(ioaddr + EEData);
821}
822
823/* MII Managemen Data I/O accesses.
824 These routines assume the MDIO controller is idle, and do not exit until
825 the command is finished. */
826
827static int mdio_read(struct net_device *dev, int phy_id, int location)
828{
829 struct hamachi_private *hmp = netdev_priv(dev);
830 void __iomem *ioaddr = hmp->base;
831 int i;
832
833 /* We should check busy first - per docs -KDU */
834 for (i = 10000; i >= 0; i--)
835 if ((readw(ioaddr + MII_Status) & 1) == 0)
836 break;
837 writew((phy_id<<8) + location, ioaddr + MII_Addr);
838 writew(0x0001, ioaddr + MII_Cmd);
839 for (i = 10000; i >= 0; i--)
840 if ((readw(ioaddr + MII_Status) & 1) == 0)
841 break;
842 return readw(ioaddr + MII_Rd_Data);
843}
844
845static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
846{
847 struct hamachi_private *hmp = netdev_priv(dev);
848 void __iomem *ioaddr = hmp->base;
849 int i;
850
851 /* We should check busy first - per docs -KDU */
852 for (i = 10000; i >= 0; i--)
853 if ((readw(ioaddr + MII_Status) & 1) == 0)
854 break;
855 writew((phy_id<<8) + location, ioaddr + MII_Addr);
856 writew(value, ioaddr + MII_Wr_Data);
857
858 /* Wait for the command to finish. */
859 for (i = 10000; i >= 0; i--)
860 if ((readw(ioaddr + MII_Status) & 1) == 0)
861 break;
862 return;
863}
864
6aa20a22 865
1da177e4
LT
866static int hamachi_open(struct net_device *dev)
867{
868 struct hamachi_private *hmp = netdev_priv(dev);
869 void __iomem *ioaddr = hmp->base;
870 int i;
871 u32 rx_int_var, tx_int_var;
872 u16 fifo_info;
873
1fb9df5d 874 i = request_irq(dev->irq, &hamachi_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT
875 if (i)
876 return i;
877
878 if (hamachi_debug > 1)
879 printk(KERN_DEBUG "%s: hamachi_open() irq %d.\n",
880 dev->name, dev->irq);
881
882 hamachi_init_ring(dev);
883
884#if ADDRLEN == 64
885 /* writellll anyone ? */
8e985918
AV
886 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
887 writel(hmp->rx_ring_dma >> 32, ioaddr + RxPtr + 4);
888 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
889 writel(hmp->tx_ring_dma >> 32, ioaddr + TxPtr + 4);
1da177e4 890#else
8e985918
AV
891 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
892 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
1da177e4
LT
893#endif
894
6aa20a22 895 /* TODO: It would make sense to organize this as words since the card
1da177e4
LT
896 * documentation does. -KDU
897 */
898 for (i = 0; i < 6; i++)
899 writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
900
901 /* Initialize other registers: with so many this eventually this will
902 converted to an offset/value list. */
903
904 /* Configure the FIFO */
905 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6;
906 switch (fifo_info){
6aa20a22 907 case 0 :
1da177e4
LT
908 /* No FIFO */
909 writew(0x0000, ioaddr + FIFOcfg);
910 break;
6aa20a22 911 case 1 :
1da177e4
LT
912 /* Configure the FIFO for 512K external, 16K used for Tx. */
913 writew(0x0028, ioaddr + FIFOcfg);
914 break;
6aa20a22 915 case 2 :
1da177e4
LT
916 /* Configure the FIFO for 1024 external, 32K used for Tx. */
917 writew(0x004C, ioaddr + FIFOcfg);
918 break;
6aa20a22 919 case 3 :
1da177e4
LT
920 /* Configure the FIFO for 2048 external, 32K used for Tx. */
921 writew(0x006C, ioaddr + FIFOcfg);
922 break;
6aa20a22 923 default :
1da177e4
LT
924 printk(KERN_WARNING "%s: Unsupported external memory config!\n",
925 dev->name);
926 /* Default to no FIFO */
927 writew(0x0000, ioaddr + FIFOcfg);
928 break;
929 }
6aa20a22 930
1da177e4
LT
931 if (dev->if_port == 0)
932 dev->if_port = hmp->default_port;
933
934
935 /* Setting the Rx mode will start the Rx process. */
6aa20a22 936 /* If someone didn't choose a duplex, default to full-duplex */
1da177e4
LT
937 if (hmp->duplex_lock != 1)
938 hmp->mii_if.full_duplex = 1;
939
940 /* always 1, takes no more time to do it */
941 writew(0x0001, ioaddr + RxChecksum);
942#ifdef TX_CHECKSUM
943 writew(0x0001, ioaddr + TxChecksum);
944#else
945 writew(0x0000, ioaddr + TxChecksum);
946#endif
947 writew(0x8000, ioaddr + MACCnfg); /* Soft reset the MAC */
948 writew(0x215F, ioaddr + MACCnfg);
6aa20a22 949 writew(0x000C, ioaddr + FrameGap0);
1da177e4
LT
950 /* WHAT?!?!? Why isn't this documented somewhere? -KDU */
951 writew(0x1018, ioaddr + FrameGap1);
952 /* Why do we enable receives/transmits here? -KDU */
953 writew(0x0780, ioaddr + MACCnfg2); /* Upper 16 bits control LEDs. */
954 /* Enable automatic generation of flow control frames, period 0xffff. */
955 writel(0x0030FFFF, ioaddr + FlowCtrl);
956 writew(MAX_FRAME_SIZE, ioaddr + MaxFrameSize); /* dev->mtu+14 ??? */
957
958 /* Enable legacy links. */
959 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
960 /* Initial Link LED to blinking red. */
961 writeb(0x03, ioaddr + LEDCtrl);
962
963 /* Configure interrupt mitigation. This has a great effect on
964 performance, so systems tuning should start here!. */
965
966 rx_int_var = hmp->rx_int_var;
967 tx_int_var = hmp->tx_int_var;
968
969 if (hamachi_debug > 1) {
970 printk("max_tx_latency: %d, max_tx_gap: %d, min_tx_pkt: %d\n",
6aa20a22 971 tx_int_var & 0x00ff, (tx_int_var & 0x00ff00) >> 8,
1da177e4
LT
972 (tx_int_var & 0x00ff0000) >> 16);
973 printk("max_rx_latency: %d, max_rx_gap: %d, min_rx_pkt: %d\n",
6aa20a22 974 rx_int_var & 0x00ff, (rx_int_var & 0x00ff00) >> 8,
1da177e4
LT
975 (rx_int_var & 0x00ff0000) >> 16);
976 printk("rx_int_var: %x, tx_int_var: %x\n", rx_int_var, tx_int_var);
977 }
978
6aa20a22
JG
979 writel(tx_int_var, ioaddr + TxIntrCtrl);
980 writel(rx_int_var, ioaddr + RxIntrCtrl);
1da177e4
LT
981
982 set_rx_mode(dev);
983
984 netif_start_queue(dev);
985
986 /* Enable interrupts by setting the interrupt mask. */
987 writel(0x80878787, ioaddr + InterruptEnable);
988 writew(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
989
990 /* Configure and start the DMA channels. */
991 /* Burst sizes are in the low three bits: size = 4<<(val&7) */
992#if ADDRLEN == 64
993 writew(0x005D, ioaddr + RxDMACtrl); /* 128 dword bursts */
994 writew(0x005D, ioaddr + TxDMACtrl);
995#else
996 writew(0x001D, ioaddr + RxDMACtrl);
997 writew(0x001D, ioaddr + TxDMACtrl);
998#endif
999 writew(0x0001, ioaddr + RxCmd);
1000
1001 if (hamachi_debug > 2) {
1002 printk(KERN_DEBUG "%s: Done hamachi_open(), status: Rx %x Tx %x.\n",
1003 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus));
1004 }
1005 /* Set the timer to check for link beat. */
1006 init_timer(&hmp->timer);
1007 hmp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
1008 hmp->timer.data = (unsigned long)dev;
1009 hmp->timer.function = &hamachi_timer; /* timer handler */
1010 add_timer(&hmp->timer);
1011
1012 return 0;
1013}
1014
1015static inline int hamachi_tx(struct net_device *dev)
1016{
1017 struct hamachi_private *hmp = netdev_priv(dev);
1018
1019 /* Update the dirty pointer until we find an entry that is
1020 still owned by the card */
1021 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++) {
1022 int entry = hmp->dirty_tx % TX_RING_SIZE;
1023 struct sk_buff *skb;
1024
6aa20a22 1025 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1da177e4
LT
1026 break;
1027 /* Free the original skb. */
1028 skb = hmp->tx_skbuff[entry];
ddfce6bb 1029 if (skb) {
6aa20a22 1030 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1031 leXX_to_cpu(hmp->tx_ring[entry].addr),
1032 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1033 dev_kfree_skb(skb);
1034 hmp->tx_skbuff[entry] = NULL;
1035 }
1036 hmp->tx_ring[entry].status_n_length = 0;
6aa20a22 1037 if (entry >= TX_RING_SIZE-1)
1da177e4 1038 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
6aa20a22 1039 cpu_to_le32(DescEndRing);
1da177e4
LT
1040 hmp->stats.tx_packets++;
1041 }
1042
1043 return 0;
1044}
1045
1046static void hamachi_timer(unsigned long data)
1047{
1048 struct net_device *dev = (struct net_device *)data;
1049 struct hamachi_private *hmp = netdev_priv(dev);
1050 void __iomem *ioaddr = hmp->base;
1051 int next_tick = 10*HZ;
1052
1053 if (hamachi_debug > 2) {
1054 printk(KERN_INFO "%s: Hamachi Autonegotiation status %4.4x, LPA "
1055 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus),
1056 readw(ioaddr + ANLinkPartnerAbility));
1057 printk(KERN_INFO "%s: Autonegotiation regs %4.4x %4.4x %4.4x "
1058 "%4.4x %4.4x %4.4x.\n", dev->name,
1059 readw(ioaddr + 0x0e0),
1060 readw(ioaddr + 0x0e2),
1061 readw(ioaddr + 0x0e4),
1062 readw(ioaddr + 0x0e6),
1063 readw(ioaddr + 0x0e8),
1064 readw(ioaddr + 0x0eA));
1065 }
1066 /* We could do something here... nah. */
1067 hmp->timer.expires = RUN_AT(next_tick);
1068 add_timer(&hmp->timer);
1069}
1070
1071static void hamachi_tx_timeout(struct net_device *dev)
1072{
1073 int i;
1074 struct hamachi_private *hmp = netdev_priv(dev);
1075 void __iomem *ioaddr = hmp->base;
1076
1077 printk(KERN_WARNING "%s: Hamachi transmit timed out, status %8.8x,"
1078 " resetting...\n", dev->name, (int)readw(ioaddr + TxStatus));
1079
1080 {
1da177e4
LT
1081 printk(KERN_DEBUG " Rx ring %p: ", hmp->rx_ring);
1082 for (i = 0; i < RX_RING_SIZE; i++)
8e985918 1083 printk(" %8.8x", le32_to_cpu(hmp->rx_ring[i].status_n_length));
1da177e4
LT
1084 printk("\n"KERN_DEBUG" Tx ring %p: ", hmp->tx_ring);
1085 for (i = 0; i < TX_RING_SIZE; i++)
8e985918 1086 printk(" %4.4x", le32_to_cpu(hmp->tx_ring[i].status_n_length));
1da177e4
LT
1087 printk("\n");
1088 }
1089
6aa20a22 1090 /* Reinit the hardware and make sure the Rx and Tx processes
1da177e4
LT
1091 are up and running.
1092 */
1093 dev->if_port = 0;
1094 /* The right way to do Reset. -KDU
1095 * -Clear OWN bit in all Rx/Tx descriptors
1096 * -Wait 50 uS for channels to go idle
1097 * -Turn off MAC receiver
1098 * -Issue Reset
1099 */
6aa20a22 1100
1da177e4
LT
1101 for (i = 0; i < RX_RING_SIZE; i++)
1102 hmp->rx_ring[i].status_n_length &= cpu_to_le32(~DescOwn);
1103
1104 /* Presume that all packets in the Tx queue are gone if we have to
1105 * re-init the hardware.
1106 */
1107 for (i = 0; i < TX_RING_SIZE; i++){
1108 struct sk_buff *skb;
1109
1110 if (i >= TX_RING_SIZE - 1)
8e985918
AV
1111 hmp->tx_ring[i].status_n_length =
1112 cpu_to_le32(DescEndRing) |
1113 (hmp->tx_ring[i].status_n_length &
1114 cpu_to_le32(0x0000ffff));
6aa20a22 1115 else
8e985918 1116 hmp->tx_ring[i].status_n_length &= cpu_to_le32(0x0000ffff);
1da177e4
LT
1117 skb = hmp->tx_skbuff[i];
1118 if (skb){
8e985918 1119 pci_unmap_single(hmp->pci_dev, leXX_to_cpu(hmp->tx_ring[i].addr),
1da177e4
LT
1120 skb->len, PCI_DMA_TODEVICE);
1121 dev_kfree_skb(skb);
1122 hmp->tx_skbuff[i] = NULL;
1123 }
1124 }
1125
1126 udelay(60); /* Sleep 60 us just for safety sake */
1127 writew(0x0002, ioaddr + RxCmd); /* STOP Rx */
6aa20a22
JG
1128
1129 writeb(0x01, ioaddr + ChipReset); /* Reinit the hardware */
1da177e4
LT
1130
1131 hmp->tx_full = 0;
1132 hmp->cur_rx = hmp->cur_tx = 0;
1133 hmp->dirty_rx = hmp->dirty_tx = 0;
1134 /* Rx packets are also presumed lost; however, we need to make sure a
1135 * ring of buffers is in tact. -KDU
6aa20a22 1136 */
1da177e4
LT
1137 for (i = 0; i < RX_RING_SIZE; i++){
1138 struct sk_buff *skb = hmp->rx_skbuff[i];
1139
1140 if (skb){
8e985918
AV
1141 pci_unmap_single(hmp->pci_dev,
1142 leXX_to_cpu(hmp->rx_ring[i].addr),
1da177e4
LT
1143 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1144 dev_kfree_skb(skb);
1145 hmp->rx_skbuff[i] = NULL;
1146 }
1147 }
1148 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1149 for (i = 0; i < RX_RING_SIZE; i++) {
8eb60131 1150 struct sk_buff *skb = netdev_alloc_skb(dev, hmp->rx_buf_sz);
1da177e4
LT
1151 hmp->rx_skbuff[i] = skb;
1152 if (skb == NULL)
1153 break;
8eb60131 1154
1da177e4 1155 skb_reserve(skb, 2); /* 16 byte align the IP header. */
6aa20a22 1156 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1157 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
6aa20a22 1158 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1da177e4
LT
1159 DescEndPacket | DescIntr | (hmp->rx_buf_sz - 2));
1160 }
1161 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1162 /* Mark the last entry as wrapping the ring. */
1163 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1164
1165 /* Trigger an immediate transmit demand. */
cdd0db05 1166 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT
1167 hmp->stats.tx_errors++;
1168
1169 /* Restart the chip's Tx/Rx processes . */
1170 writew(0x0002, ioaddr + TxCmd); /* STOP Tx */
1171 writew(0x0001, ioaddr + TxCmd); /* START Tx */
1172 writew(0x0001, ioaddr + RxCmd); /* START Rx */
1173
1174 netif_wake_queue(dev);
1175}
1176
1177
1178/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1179static void hamachi_init_ring(struct net_device *dev)
1180{
1181 struct hamachi_private *hmp = netdev_priv(dev);
1182 int i;
1183
1184 hmp->tx_full = 0;
1185 hmp->cur_rx = hmp->cur_tx = 0;
1186 hmp->dirty_rx = hmp->dirty_tx = 0;
1187
1da177e4 1188 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
6aa20a22
JG
1189 * card needs room to do 8 byte alignment, +2 so we can reserve
1190 * the first 2 bytes, and +16 gets room for the status word from the
1da177e4
LT
1191 * card. -KDU
1192 */
6aa20a22 1193 hmp->rx_buf_sz = (dev->mtu <= 1492 ? PKT_BUF_SZ :
1da177e4
LT
1194 (((dev->mtu+26+7) & ~7) + 2 + 16));
1195
1196 /* Initialize all Rx descriptors. */
1197 for (i = 0; i < RX_RING_SIZE; i++) {
1198 hmp->rx_ring[i].status_n_length = 0;
1199 hmp->rx_skbuff[i] = NULL;
1200 }
1201 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1202 for (i = 0; i < RX_RING_SIZE; i++) {
1203 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz);
1204 hmp->rx_skbuff[i] = skb;
1205 if (skb == NULL)
1206 break;
1207 skb->dev = dev; /* Mark as being used by this device. */
1208 skb_reserve(skb, 2); /* 16 byte align the IP header. */
6aa20a22 1209 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1210 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4 1211 /* -2 because it doesn't REALLY have that first 2 bytes -KDU */
6aa20a22 1212 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1da177e4
LT
1213 DescEndPacket | DescIntr | (hmp->rx_buf_sz -2));
1214 }
1215 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1216 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1217
1218 for (i = 0; i < TX_RING_SIZE; i++) {
1219 hmp->tx_skbuff[i] = NULL;
1220 hmp->tx_ring[i].status_n_length = 0;
1221 }
1222 /* Mark the last entry of the ring */
1223 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1224
1225 return;
1226}
1227
1228
1229#ifdef TX_CHECKSUM
1230#define csum_add(it, val) \
1231do { \
1232 it += (u16) (val); \
1233 if (it & 0xffff0000) { \
1234 it &= 0xffff; \
1235 ++it; \
1236 } \
1237} while (0)
1238 /* printk("add %04x --> %04x\n", val, it); \ */
1239
1240/* uh->len already network format, do not swap */
1241#define pseudo_csum_udp(sum,ih,uh) do { \
1242 sum = 0; \
1243 csum_add(sum, (ih)->saddr >> 16); \
1244 csum_add(sum, (ih)->saddr & 0xffff); \
1245 csum_add(sum, (ih)->daddr >> 16); \
1246 csum_add(sum, (ih)->daddr & 0xffff); \
09640e63 1247 csum_add(sum, cpu_to_be16(IPPROTO_UDP)); \
1da177e4
LT
1248 csum_add(sum, (uh)->len); \
1249} while (0)
1250
1251/* swap len */
1252#define pseudo_csum_tcp(sum,ih,len) do { \
1253 sum = 0; \
1254 csum_add(sum, (ih)->saddr >> 16); \
1255 csum_add(sum, (ih)->saddr & 0xffff); \
1256 csum_add(sum, (ih)->daddr >> 16); \
1257 csum_add(sum, (ih)->daddr & 0xffff); \
09640e63 1258 csum_add(sum, cpu_to_be16(IPPROTO_TCP)); \
1da177e4
LT
1259 csum_add(sum, htons(len)); \
1260} while (0)
1261#endif
1262
1263static int hamachi_start_xmit(struct sk_buff *skb, struct net_device *dev)
1264{
1265 struct hamachi_private *hmp = netdev_priv(dev);
1266 unsigned entry;
1267 u16 status;
1268
6aa20a22 1269 /* Ok, now make sure that the queue has space before trying to
1da177e4
LT
1270 add another skbuff. if we return non-zero the scheduler
1271 should interpret this as a queue full and requeue the buffer
1272 for later.
1273 */
1274 if (hmp->tx_full) {
1275 /* We should NEVER reach this point -KDU */
1276 printk(KERN_WARNING "%s: Hamachi transmit queue full at slot %d.\n",dev->name, hmp->cur_tx);
1277
1278 /* Wake the potentially-idle transmit channel. */
1279 /* If we don't need to read status, DON'T -KDU */
1280 status=readw(hmp->base + TxStatus);
1281 if( !(status & 0x0001) || (status & 0x0002))
1282 writew(0x0001, hmp->base + TxCmd);
5b548140 1283 return NETDEV_TX_BUSY;
6aa20a22 1284 }
1da177e4
LT
1285
1286 /* Caution: the write order is important here, set the field
1287 with the "ownership" bits last. */
1288
1289 /* Calculate the next Tx descriptor entry. */
1290 entry = hmp->cur_tx % TX_RING_SIZE;
1291
1292 hmp->tx_skbuff[entry] = skb;
1293
1294#ifdef TX_CHECKSUM
1295 {
1296 /* tack on checksum tag */
1297 u32 tagval = 0;
1298 struct ethhdr *eh = (struct ethhdr *)skb->data;
09640e63 1299 if (eh->h_proto == cpu_to_be16(ETH_P_IP)) {
1da177e4
LT
1300 struct iphdr *ih = (struct iphdr *)((char *)eh + ETH_HLEN);
1301 if (ih->protocol == IPPROTO_UDP) {
1302 struct udphdr *uh
1303 = (struct udphdr *)((char *)ih + ih->ihl*4);
1304 u32 offset = ((unsigned char *)uh + 6) - skb->data;
1305 u32 pseudo;
1306 pseudo_csum_udp(pseudo, ih, uh);
1307 pseudo = htons(pseudo);
1308 printk("udp cksum was %04x, sending pseudo %04x\n",
1309 uh->check, pseudo);
1310 uh->check = 0; /* zero out uh->check before card calc */
1311 /*
1312 * start at 14 (skip ethhdr), store at offset (uh->check),
1313 * use pseudo value given.
1314 */
1315 tagval = (14 << 24) | (offset << 16) | pseudo;
1316 } else if (ih->protocol == IPPROTO_TCP) {
1317 printk("tcp, no auto cksum\n");
1318 }
1319 }
1320 *(u32 *)skb_push(skb, 8) = tagval;
1321 }
1322#endif
1323
6aa20a22 1324 hmp->tx_ring[entry].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1da177e4 1325 skb->data, skb->len, PCI_DMA_TODEVICE));
6aa20a22 1326
1da177e4
LT
1327 /* Hmmmm, could probably put a DescIntr on these, but the way
1328 the driver is currently coded makes Tx interrupts unnecessary
1329 since the clearing of the Tx ring is handled by the start_xmit
1330 routine. This organization helps mitigate the interrupts a
1331 bit and probably renders the max_tx_latency param useless.
6aa20a22 1332
1da177e4
LT
1333 Update: Putting a DescIntr bit on all of the descriptors and
1334 mitigating interrupt frequency with the tx_min_pkt parameter. -KDU
1335 */
1336 if (entry >= TX_RING_SIZE-1) /* Wrap ring */
1337 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1338 DescEndPacket | DescEndRing | DescIntr | skb->len);
1339 else
1340 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1341 DescEndPacket | DescIntr | skb->len);
1342 hmp->cur_tx++;
1343
1344 /* Non-x86 Todo: explicitly flush cache lines here. */
1345
1346 /* Wake the potentially-idle transmit channel. */
1347 /* If we don't need to read status, DON'T -KDU */
1348 status=readw(hmp->base + TxStatus);
1349 if( !(status & 0x0001) || (status & 0x0002))
1350 writew(0x0001, hmp->base + TxCmd);
1351
1352 /* Immediately before returning, let's clear as many entries as we can. */
1353 hamachi_tx(dev);
1354
1355 /* We should kick the bottom half here, since we are not accepting
1356 * interrupts with every packet. i.e. realize that Gigabit ethernet
1357 * can transmit faster than ordinary machines can load packets;
1358 * hence, any packet that got put off because we were in the transmit
1359 * routine should IMMEDIATELY get a chance to be re-queued. -KDU
1360 */
6aa20a22 1361 if ((hmp->cur_tx - hmp->dirty_tx) < (TX_RING_SIZE - 4))
1da177e4
LT
1362 netif_wake_queue(dev); /* Typical path */
1363 else {
1364 hmp->tx_full = 1;
1365 netif_stop_queue(dev);
1366 }
1da177e4
LT
1367
1368 if (hamachi_debug > 4) {
1369 printk(KERN_DEBUG "%s: Hamachi transmit frame #%d queued in slot %d.\n",
1370 dev->name, hmp->cur_tx, entry);
1371 }
6ed10654 1372 return NETDEV_TX_OK;
1da177e4
LT
1373}
1374
1375/* The interrupt handler does all of the Rx thread work and cleans up
1376 after the Tx thread. */
7d12e780 1377static irqreturn_t hamachi_interrupt(int irq, void *dev_instance)
1da177e4
LT
1378{
1379 struct net_device *dev = dev_instance;
1380 struct hamachi_private *hmp = netdev_priv(dev);
1381 void __iomem *ioaddr = hmp->base;
1382 long boguscnt = max_interrupt_work;
1383 int handled = 0;
1384
1385#ifndef final_version /* Can never occur. */
1386 if (dev == NULL) {
1387 printk (KERN_ERR "hamachi_interrupt(): irq %d for unknown device.\n", irq);
1388 return IRQ_NONE;
1389 }
1390#endif
1391
1392 spin_lock(&hmp->lock);
1393
1394 do {
1395 u32 intr_status = readl(ioaddr + InterruptClear);
1396
1397 if (hamachi_debug > 4)
1398 printk(KERN_DEBUG "%s: Hamachi interrupt, status %4.4x.\n",
1399 dev->name, intr_status);
1400
1401 if (intr_status == 0)
1402 break;
1403
1404 handled = 1;
1405
1406 if (intr_status & IntrRxDone)
1407 hamachi_rx(dev);
1408
1409 if (intr_status & IntrTxDone){
1410 /* This code should RARELY need to execute. After all, this is
1411 * a gigabit link, it should consume packets as fast as we put
1412 * them in AND we clear the Tx ring in hamachi_start_xmit().
6aa20a22 1413 */
1da177e4
LT
1414 if (hmp->tx_full){
1415 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++){
1416 int entry = hmp->dirty_tx % TX_RING_SIZE;
1417 struct sk_buff *skb;
1418
6aa20a22 1419 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1da177e4
LT
1420 break;
1421 skb = hmp->tx_skbuff[entry];
1422 /* Free the original skb. */
1423 if (skb){
6aa20a22 1424 pci_unmap_single(hmp->pci_dev,
8e985918 1425 leXX_to_cpu(hmp->tx_ring[entry].addr),
1da177e4
LT
1426 skb->len,
1427 PCI_DMA_TODEVICE);
1428 dev_kfree_skb_irq(skb);
1429 hmp->tx_skbuff[entry] = NULL;
1430 }
1431 hmp->tx_ring[entry].status_n_length = 0;
6aa20a22
JG
1432 if (entry >= TX_RING_SIZE-1)
1433 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
1da177e4
LT
1434 cpu_to_le32(DescEndRing);
1435 hmp->stats.tx_packets++;
1436 }
1437 if (hmp->cur_tx - hmp->dirty_tx < TX_RING_SIZE - 4){
1438 /* The ring is no longer full */
1439 hmp->tx_full = 0;
1440 netif_wake_queue(dev);
1441 }
1442 } else {
1443 netif_wake_queue(dev);
1444 }
1445 }
1446
1447
1448 /* Abnormal error summary/uncommon events handlers. */
1449 if (intr_status &
1450 (IntrTxPCIFault | IntrTxPCIErr | IntrRxPCIFault | IntrRxPCIErr |
1451 LinkChange | NegotiationChange | StatsMax))
1452 hamachi_error(dev, intr_status);
1453
1454 if (--boguscnt < 0) {
1455 printk(KERN_WARNING "%s: Too much work at interrupt, status=0x%4.4x.\n",
1456 dev->name, intr_status);
1457 break;
1458 }
1459 } while (1);
1460
1461 if (hamachi_debug > 3)
1462 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1463 dev->name, readl(ioaddr + IntrStatus));
1464
1465#ifndef final_version
1466 /* Code that should never be run! Perhaps remove after testing.. */
1467 {
1468 static int stopit = 10;
1469 if (dev->start == 0 && --stopit < 0) {
1470 printk(KERN_ERR "%s: Emergency stop, looping startup interrupt.\n",
1471 dev->name);
1472 free_irq(irq, dev);
1473 }
1474 }
1475#endif
1476
1477 spin_unlock(&hmp->lock);
1478 return IRQ_RETVAL(handled);
1479}
1480
1481/* This routine is logically part of the interrupt handler, but separated
1482 for clarity and better register allocation. */
1483static int hamachi_rx(struct net_device *dev)
1484{
1485 struct hamachi_private *hmp = netdev_priv(dev);
1486 int entry = hmp->cur_rx % RX_RING_SIZE;
1487 int boguscnt = (hmp->dirty_rx + RX_RING_SIZE) - hmp->cur_rx;
1488
1489 if (hamachi_debug > 4) {
1490 printk(KERN_DEBUG " In hamachi_rx(), entry %d status %4.4x.\n",
1491 entry, hmp->rx_ring[entry].status_n_length);
1492 }
1493
1494 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1495 while (1) {
1496 struct hamachi_desc *desc = &(hmp->rx_ring[entry]);
1497 u32 desc_status = le32_to_cpu(desc->status_n_length);
1498 u16 data_size = desc_status; /* Implicit truncate */
6aa20a22 1499 u8 *buf_addr;
1da177e4 1500 s32 frame_status;
6aa20a22 1501
1da177e4
LT
1502 if (desc_status & DescOwn)
1503 break;
1504 pci_dma_sync_single_for_cpu(hmp->pci_dev,
8e985918 1505 leXX_to_cpu(desc->addr),
1da177e4
LT
1506 hmp->rx_buf_sz,
1507 PCI_DMA_FROMDEVICE);
689be439 1508 buf_addr = (u8 *) hmp->rx_skbuff[entry]->data;
6caf52a4 1509 frame_status = get_unaligned_le32(&(buf_addr[data_size - 12]));
1da177e4
LT
1510 if (hamachi_debug > 4)
1511 printk(KERN_DEBUG " hamachi_rx() status was %8.8x.\n",
1512 frame_status);
1513 if (--boguscnt < 0)
1514 break;
1515 if ( ! (desc_status & DescEndPacket)) {
1516 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1517 "multiple buffers, entry %#x length %d status %4.4x!\n",
1518 dev->name, hmp->cur_rx, data_size, desc_status);
1519 printk(KERN_WARNING "%s: Oversized Ethernet frame %p vs %p.\n",
1520 dev->name, desc, &hmp->rx_ring[hmp->cur_rx % RX_RING_SIZE]);
1521 printk(KERN_WARNING "%s: Oversized Ethernet frame -- next status %x/%x last status %x.\n",
1522 dev->name,
8e985918
AV
1523 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0xffff0000,
1524 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0x0000ffff,
1525 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx-1) % RX_RING_SIZE].status_n_length));
1da177e4
LT
1526 hmp->stats.rx_length_errors++;
1527 } /* else Omit for prototype errata??? */
1528 if (frame_status & 0x00380000) {
1529 /* There was an error. */
1530 if (hamachi_debug > 2)
1531 printk(KERN_DEBUG " hamachi_rx() Rx error was %8.8x.\n",
1532 frame_status);
1533 hmp->stats.rx_errors++;
1534 if (frame_status & 0x00600000) hmp->stats.rx_length_errors++;
1535 if (frame_status & 0x00080000) hmp->stats.rx_frame_errors++;
1536 if (frame_status & 0x00100000) hmp->stats.rx_crc_errors++;
1537 if (frame_status < 0) hmp->stats.rx_dropped++;
1538 } else {
1539 struct sk_buff *skb;
1540 /* Omit CRC */
6aa20a22 1541 u16 pkt_len = (frame_status & 0x07ff) - 4;
1da177e4
LT
1542#ifdef RX_CHECKSUM
1543 u32 pfck = *(u32 *) &buf_addr[data_size - 8];
1544#endif
1545
1546
1547#ifndef final_version
1548 if (hamachi_debug > 4)
1549 printk(KERN_DEBUG " hamachi_rx() normal Rx pkt length %d"
1550 " of %d, bogus_cnt %d.\n",
1551 pkt_len, data_size, boguscnt);
1552 if (hamachi_debug > 5)
1553 printk(KERN_DEBUG"%s: rx status %8.8x %8.8x %8.8x %8.8x %8.8x.\n",
1554 dev->name,
1555 *(s32*)&(buf_addr[data_size - 20]),
1556 *(s32*)&(buf_addr[data_size - 16]),
1557 *(s32*)&(buf_addr[data_size - 12]),
1558 *(s32*)&(buf_addr[data_size - 8]),
1559 *(s32*)&(buf_addr[data_size - 4]));
1560#endif
1561 /* Check if the packet is long enough to accept without copying
1562 to a minimally-sized skbuff. */
1563 if (pkt_len < rx_copybreak
1564 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1565#ifdef RX_CHECKSUM
1566 printk(KERN_ERR "%s: rx_copybreak non-zero "
1567 "not good with RX_CHECKSUM\n", dev->name);
1568#endif
1da177e4
LT
1569 skb_reserve(skb, 2); /* 16 byte align the IP header */
1570 pci_dma_sync_single_for_cpu(hmp->pci_dev,
8e985918 1571 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1572 hmp->rx_buf_sz,
1573 PCI_DMA_FROMDEVICE);
1574 /* Call copy + cksum if available. */
1575#if 1 || USE_IP_COPYSUM
8c7b7faa
DM
1576 skb_copy_to_linear_data(skb,
1577 hmp->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT
1578 skb_put(skb, pkt_len);
1579#else
1580 memcpy(skb_put(skb, pkt_len), hmp->rx_ring_dma
1581 + entry*sizeof(*desc), pkt_len);
1582#endif
1583 pci_dma_sync_single_for_device(hmp->pci_dev,
8e985918 1584 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1585 hmp->rx_buf_sz,
1586 PCI_DMA_FROMDEVICE);
1587 } else {
6aa20a22 1588 pci_unmap_single(hmp->pci_dev,
8e985918 1589 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1590 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1591 skb_put(skb = hmp->rx_skbuff[entry], pkt_len);
1592 hmp->rx_skbuff[entry] = NULL;
1593 }
1594 skb->protocol = eth_type_trans(skb, dev);
1595
1596
1597#ifdef RX_CHECKSUM
1598 /* TCP or UDP on ipv4, DIX encoding */
1599 if (pfck>>24 == 0x91 || pfck>>24 == 0x51) {
1600 struct iphdr *ih = (struct iphdr *) skb->data;
1601 /* Check that IP packet is at least 46 bytes, otherwise,
1602 * there may be pad bytes included in the hardware checksum.
1603 * This wouldn't happen if everyone padded with 0.
1604 */
1605 if (ntohs(ih->tot_len) >= 46){
1606 /* don't worry about frags */
09640e63 1607 if (!(ih->frag_off & cpu_to_be16(IP_MF|IP_OFFSET))) {
1da177e4
LT
1608 u32 inv = *(u32 *) &buf_addr[data_size - 16];
1609 u32 *p = (u32 *) &buf_addr[data_size - 20];
1610 register u32 crc, p_r, p_r1;
1611
1612 if (inv & 4) {
1613 inv &= ~4;
1614 --p;
1615 }
1616 p_r = *p;
1617 p_r1 = *(p-1);
1618 switch (inv) {
6aa20a22 1619 case 0:
1da177e4
LT
1620 crc = (p_r & 0xffff) + (p_r >> 16);
1621 break;
6aa20a22 1622 case 1:
1da177e4 1623 crc = (p_r >> 16) + (p_r & 0xffff)
6aa20a22 1624 + (p_r1 >> 16 & 0xff00);
1da177e4 1625 break;
6aa20a22
JG
1626 case 2:
1627 crc = p_r + (p_r1 >> 16);
1da177e4 1628 break;
6aa20a22
JG
1629 case 3:
1630 crc = p_r + (p_r1 & 0xff00) + (p_r1 >> 16);
1da177e4
LT
1631 break;
1632 default: /*NOTREACHED*/ crc = 0;
1633 }
1634 if (crc & 0xffff0000) {
1635 crc &= 0xffff;
1636 ++crc;
1637 }
1638 /* tcp/udp will add in pseudo */
1639 skb->csum = ntohs(pfck & 0xffff);
1640 if (skb->csum > crc)
1641 skb->csum -= crc;
1642 else
1643 skb->csum += (~crc & 0xffff);
1644 /*
1645 * could do the pseudo myself and return
1646 * CHECKSUM_UNNECESSARY
1647 */
84fa7933 1648 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 1649 }
6aa20a22 1650 }
1da177e4
LT
1651 }
1652#endif /* RX_CHECKSUM */
1653
1654 netif_rx(skb);
1da177e4
LT
1655 hmp->stats.rx_packets++;
1656 }
1657 entry = (++hmp->cur_rx) % RX_RING_SIZE;
1658 }
1659
1660 /* Refill the Rx ring buffers. */
1661 for (; hmp->cur_rx - hmp->dirty_rx > 0; hmp->dirty_rx++) {
1662 struct hamachi_desc *desc;
1663
1664 entry = hmp->dirty_rx % RX_RING_SIZE;
1665 desc = &(hmp->rx_ring[entry]);
1666 if (hmp->rx_skbuff[entry] == NULL) {
1667 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz);
1668
1669 hmp->rx_skbuff[entry] = skb;
1670 if (skb == NULL)
1671 break; /* Better luck next round. */
1672 skb->dev = dev; /* Mark as being used by this device. */
1673 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
6aa20a22 1674 desc->addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1675 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT
1676 }
1677 desc->status_n_length = cpu_to_le32(hmp->rx_buf_sz);
1678 if (entry >= RX_RING_SIZE-1)
6aa20a22 1679 desc->status_n_length |= cpu_to_le32(DescOwn |
1da177e4
LT
1680 DescEndPacket | DescEndRing | DescIntr);
1681 else
6aa20a22 1682 desc->status_n_length |= cpu_to_le32(DescOwn |
1da177e4
LT
1683 DescEndPacket | DescIntr);
1684 }
1685
1686 /* Restart Rx engine if stopped. */
1687 /* If we don't need to check status, don't. -KDU */
1688 if (readw(hmp->base + RxStatus) & 0x0002)
1689 writew(0x0001, hmp->base + RxCmd);
1690
1691 return 0;
1692}
1693
1694/* This is more properly named "uncommon interrupt events", as it covers more
1695 than just errors. */
1696static void hamachi_error(struct net_device *dev, int intr_status)
1697{
1698 struct hamachi_private *hmp = netdev_priv(dev);
1699 void __iomem *ioaddr = hmp->base;
1700
1701 if (intr_status & (LinkChange|NegotiationChange)) {
1702 if (hamachi_debug > 1)
1703 printk(KERN_INFO "%s: Link changed: AutoNegotiation Ctrl"
1704 " %4.4x, Status %4.4x %4.4x Intr status %4.4x.\n",
1705 dev->name, readw(ioaddr + 0x0E0), readw(ioaddr + 0x0E2),
1706 readw(ioaddr + ANLinkPartnerAbility),
1707 readl(ioaddr + IntrStatus));
1708 if (readw(ioaddr + ANStatus) & 0x20)
1709 writeb(0x01, ioaddr + LEDCtrl);
1710 else
1711 writeb(0x03, ioaddr + LEDCtrl);
1712 }
1713 if (intr_status & StatsMax) {
1714 hamachi_get_stats(dev);
1715 /* Read the overflow bits to clear. */
1716 readl(ioaddr + 0x370);
1717 readl(ioaddr + 0x3F0);
1718 }
1719 if ((intr_status & ~(LinkChange|StatsMax|NegotiationChange|IntrRxDone|IntrTxDone))
1720 && hamachi_debug)
1721 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1722 dev->name, intr_status);
1723 /* Hmmmmm, it's not clear how to recover from PCI faults. */
1724 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1725 hmp->stats.tx_fifo_errors++;
1726 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1727 hmp->stats.rx_fifo_errors++;
1728}
1729
1730static int hamachi_close(struct net_device *dev)
1731{
1732 struct hamachi_private *hmp = netdev_priv(dev);
1733 void __iomem *ioaddr = hmp->base;
1734 struct sk_buff *skb;
1735 int i;
1736
1737 netif_stop_queue(dev);
1738
1739 if (hamachi_debug > 1) {
1740 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x Rx %4.4x Int %2.2x.\n",
1741 dev->name, readw(ioaddr + TxStatus),
1742 readw(ioaddr + RxStatus), readl(ioaddr + IntrStatus));
1743 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1744 dev->name, hmp->cur_tx, hmp->dirty_tx, hmp->cur_rx, hmp->dirty_rx);
1745 }
1746
1747 /* Disable interrupts by clearing the interrupt mask. */
1748 writel(0x0000, ioaddr + InterruptEnable);
1749
1750 /* Stop the chip's Tx and Rx processes. */
1751 writel(2, ioaddr + RxCmd);
1752 writew(2, ioaddr + TxCmd);
1753
1754#ifdef __i386__
1755 if (hamachi_debug > 2) {
1756 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1757 (int)hmp->tx_ring_dma);
1758 for (i = 0; i < TX_RING_SIZE; i++)
1759 printk(" %c #%d desc. %8.8x %8.8x.\n",
1760 readl(ioaddr + TxCurPtr) == (long)&hmp->tx_ring[i] ? '>' : ' ',
1761 i, hmp->tx_ring[i].status_n_length, hmp->tx_ring[i].addr);
1762 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1763 (int)hmp->rx_ring_dma);
1764 for (i = 0; i < RX_RING_SIZE; i++) {
1765 printk(KERN_DEBUG " %c #%d desc. %4.4x %8.8x\n",
1766 readl(ioaddr + RxCurPtr) == (long)&hmp->rx_ring[i] ? '>' : ' ',
1767 i, hmp->rx_ring[i].status_n_length, hmp->rx_ring[i].addr);
1768 if (hamachi_debug > 6) {
689be439 1769 if (*(u8*)hmp->rx_skbuff[i]->data != 0x69) {
1da177e4 1770 u16 *addr = (u16 *)
689be439 1771 hmp->rx_skbuff[i]->data;
1da177e4
LT
1772 int j;
1773
1774 for (j = 0; j < 0x50; j++)
1775 printk(" %4.4x", addr[j]);
1776 printk("\n");
1777 }
1778 }
1779 }
1780 }
1781#endif /* __i386__ debugging only */
1782
1783 free_irq(dev->irq, dev);
1784
1785 del_timer_sync(&hmp->timer);
1786
1787 /* Free all the skbuffs in the Rx queue. */
1788 for (i = 0; i < RX_RING_SIZE; i++) {
1789 skb = hmp->rx_skbuff[i];
1790 hmp->rx_ring[i].status_n_length = 0;
1da177e4 1791 if (skb) {
6aa20a22 1792 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1793 leXX_to_cpu(hmp->rx_ring[i].addr),
1794 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT
1795 dev_kfree_skb(skb);
1796 hmp->rx_skbuff[i] = NULL;
1797 }
8e985918 1798 hmp->rx_ring[i].addr = cpu_to_leXX(0xBADF00D0); /* An invalid address. */
1da177e4
LT
1799 }
1800 for (i = 0; i < TX_RING_SIZE; i++) {
1801 skb = hmp->tx_skbuff[i];
1802 if (skb) {
6aa20a22 1803 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1804 leXX_to_cpu(hmp->tx_ring[i].addr),
1805 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1806 dev_kfree_skb(skb);
1807 hmp->tx_skbuff[i] = NULL;
1808 }
1809 }
1810
1811 writeb(0x00, ioaddr + LEDCtrl);
1812
1813 return 0;
1814}
1815
1816static struct net_device_stats *hamachi_get_stats(struct net_device *dev)
1817{
1818 struct hamachi_private *hmp = netdev_priv(dev);
1819 void __iomem *ioaddr = hmp->base;
1820
1821 /* We should lock this segment of code for SMP eventually, although
1822 the vulnerability window is very small and statistics are
1823 non-critical. */
1824 /* Ok, what goes here? This appears to be stuck at 21 packets
1825 according to ifconfig. It does get incremented in hamachi_tx(),
1826 so I think I'll comment it out here and see if better things
1827 happen.
6aa20a22 1828 */
1da177e4
LT
1829 /* hmp->stats.tx_packets = readl(ioaddr + 0x000); */
1830
1831 hmp->stats.rx_bytes = readl(ioaddr + 0x330); /* Total Uni+Brd+Multi */
1832 hmp->stats.tx_bytes = readl(ioaddr + 0x3B0); /* Total Uni+Brd+Multi */
1833 hmp->stats.multicast = readl(ioaddr + 0x320); /* Multicast Rx */
1834
1835 hmp->stats.rx_length_errors = readl(ioaddr + 0x368); /* Over+Undersized */
1836 hmp->stats.rx_over_errors = readl(ioaddr + 0x35C); /* Jabber */
1837 hmp->stats.rx_crc_errors = readl(ioaddr + 0x360); /* Jabber */
1838 hmp->stats.rx_frame_errors = readl(ioaddr + 0x364); /* Symbol Errs */
1839 hmp->stats.rx_missed_errors = readl(ioaddr + 0x36C); /* Dropped */
1840
1841 return &hmp->stats;
1842}
1843
1844static void set_rx_mode(struct net_device *dev)
1845{
1846 struct hamachi_private *hmp = netdev_priv(dev);
1847 void __iomem *ioaddr = hmp->base;
1848
1849 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT
1850 writew(0x000F, ioaddr + AddrMode);
1851 } else if ((dev->mc_count > 63) || (dev->flags & IFF_ALLMULTI)) {
1852 /* Too many to match, or accept all multicasts. */
1853 writew(0x000B, ioaddr + AddrMode);
1854 } else if (dev->mc_count > 0) { /* Must use the CAM filter. */
1855 struct dev_mc_list *mclist;
1856 int i;
1857 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1858 i++, mclist = mclist->next) {
1859 writel(*(u32*)(mclist->dmi_addr), ioaddr + 0x100 + i*8);
1860 writel(0x20000 | (*(u16*)&mclist->dmi_addr[4]),
1861 ioaddr + 0x104 + i*8);
1862 }
1863 /* Clear remaining entries. */
1864 for (; i < 64; i++)
1865 writel(0, ioaddr + 0x104 + i*8);
1866 writew(0x0003, ioaddr + AddrMode);
1867 } else { /* Normal, unicast/broadcast-only mode. */
1868 writew(0x0001, ioaddr + AddrMode);
1869 }
1870}
1871
1872static int check_if_running(struct net_device *dev)
1873{
1874 if (!netif_running(dev))
1875 return -EINVAL;
1876 return 0;
1877}
1878
1879static void hamachi_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1880{
1881 struct hamachi_private *np = netdev_priv(dev);
1882 strcpy(info->driver, DRV_NAME);
1883 strcpy(info->version, DRV_VERSION);
1884 strcpy(info->bus_info, pci_name(np->pci_dev));
1885}
1886
1887static int hamachi_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1888{
1889 struct hamachi_private *np = netdev_priv(dev);
1890 spin_lock_irq(&np->lock);
1891 mii_ethtool_gset(&np->mii_if, ecmd);
1892 spin_unlock_irq(&np->lock);
1893 return 0;
1894}
1895
1896static int hamachi_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1897{
1898 struct hamachi_private *np = netdev_priv(dev);
1899 int res;
1900 spin_lock_irq(&np->lock);
1901 res = mii_ethtool_sset(&np->mii_if, ecmd);
1902 spin_unlock_irq(&np->lock);
1903 return res;
1904}
1905
1906static int hamachi_nway_reset(struct net_device *dev)
1907{
1908 struct hamachi_private *np = netdev_priv(dev);
1909 return mii_nway_restart(&np->mii_if);
1910}
1911
1912static u32 hamachi_get_link(struct net_device *dev)
1913{
1914 struct hamachi_private *np = netdev_priv(dev);
1915 return mii_link_ok(&np->mii_if);
1916}
1917
7282d491 1918static const struct ethtool_ops ethtool_ops = {
1da177e4
LT
1919 .begin = check_if_running,
1920 .get_drvinfo = hamachi_get_drvinfo,
1921 .get_settings = hamachi_get_settings,
1922 .set_settings = hamachi_set_settings,
1923 .nway_reset = hamachi_nway_reset,
1924 .get_link = hamachi_get_link,
1925};
1926
7282d491 1927static const struct ethtool_ops ethtool_ops_no_mii = {
1da177e4
LT
1928 .begin = check_if_running,
1929 .get_drvinfo = hamachi_get_drvinfo,
1930};
1931
1932static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1933{
1934 struct hamachi_private *np = netdev_priv(dev);
1935 struct mii_ioctl_data *data = if_mii(rq);
1936 int rc;
1937
1938 if (!netif_running(dev))
1939 return -EINVAL;
1940
1941 if (cmd == (SIOCDEVPRIVATE+3)) { /* set rx,tx intr params */
1942 u32 *d = (u32 *)&rq->ifr_ifru;
1943 /* Should add this check here or an ordinary user can do nasty
1944 * things. -KDU
1945 *
1946 * TODO: Shut down the Rx and Tx engines while doing this.
1947 */
1948 if (!capable(CAP_NET_ADMIN))
1949 return -EPERM;
1950 writel(d[0], np->base + TxIntrCtrl);
1951 writel(d[1], np->base + RxIntrCtrl);
1952 printk(KERN_NOTICE "%s: tx %08x, rx %08x intr\n", dev->name,
1953 (u32) readl(np->base + TxIntrCtrl),
1954 (u32) readl(np->base + RxIntrCtrl));
1955 rc = 0;
1956 }
1957
1958 else {
1959 spin_lock_irq(&np->lock);
1960 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1961 spin_unlock_irq(&np->lock);
1962 }
1963
1964 return rc;
1965}
1966
1967
1968static void __devexit hamachi_remove_one (struct pci_dev *pdev)
1969{
1970 struct net_device *dev = pci_get_drvdata(pdev);
1971
1972 if (dev) {
1973 struct hamachi_private *hmp = netdev_priv(dev);
1974
6aa20a22 1975 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1da177e4 1976 hmp->rx_ring_dma);
6aa20a22 1977 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1da177e4
LT
1978 hmp->tx_ring_dma);
1979 unregister_netdev(dev);
1980 iounmap(hmp->base);
1981 free_netdev(dev);
1982 pci_release_regions(pdev);
1983 pci_set_drvdata(pdev, NULL);
1984 }
1985}
1986
1987static struct pci_device_id hamachi_pci_tbl[] = {
1988 { 0x1318, 0x0911, PCI_ANY_ID, PCI_ANY_ID, },
1989 { 0, }
1990};
1991MODULE_DEVICE_TABLE(pci, hamachi_pci_tbl);
1992
1993static struct pci_driver hamachi_driver = {
1994 .name = DRV_NAME,
1995 .id_table = hamachi_pci_tbl,
1996 .probe = hamachi_init_one,
1997 .remove = __devexit_p(hamachi_remove_one),
1998};
1999
2000static int __init hamachi_init (void)
2001{
2002/* when a module, this is printed whether or not devices are found in probe */
2003#ifdef MODULE
2004 printk(version);
2005#endif
2006 return pci_register_driver(&hamachi_driver);
2007}
2008
2009static void __exit hamachi_exit (void)
2010{
2011 pci_unregister_driver(&hamachi_driver);
2012}
2013
2014
2015module_init(hamachi_init);
2016module_exit(hamachi_exit);