[net-next-2.6.git] / drivers / net / fsl_pq_mdio.c

/*
 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
 * Provides Bus interface for MIIM regs
 *
 * Author: Andy Fleming <afleming@freescale.com>
 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
 *
 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
 *
 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/crc32.h>
#include <linux/mii.h>
#include <linux/phy.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/ucc.h>

#include "gianfar.h"
#include "fsl_pq_mdio.h"

struct fsl_pq_mdio_priv {
	void __iomem *map;
	struct fsl_pq_mdio __iomem *regs;
};

/*
 * Write value to the PHY at mii_id at register regnum,
 * on the bus attached to the local interface, which may be different from the
 * generic mdio bus (tied to a single interface), waiting until the write is
 * done before returning. This is helpful in programming interfaces like
 * the TBI which control interfaces like onchip SERDES and are always tied to
 * the local mdio pins, which may not be the same as system mdio bus, used for
 * controlling the external PHYs, for example.
 */
int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
		int regnum, u16 value)
{
	/* Set the PHY address and the register address we want to write */
	out_be32(&regs->miimadd, (mii_id << 8) | regnum);

	/* Write out the value we want */
	out_be32(&regs->miimcon, value);

	/* Wait for the transaction to finish */
	while (in_be32(&regs->miimind) & MIIMIND_BUSY)
		cpu_relax();

	return 0;
}

/*
 * Read the bus for PHY at addr mii_id, register regnum, and
 * return the value.  Clears miimcom first.  All PHY operation
 * done on the bus attached to the local interface,
 * which may be different from the generic mdio bus
 * This is helpful in programming interfaces like
 * the TBI which, in turn, control interfaces like onchip SERDES
 * and are always tied to the local mdio pins, which may not be the
 * same as system mdio bus, used for controlling the external PHYs, for eg.
 */
int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
		int mii_id, int regnum)
{
	u16 value;

	/* Set the PHY address and the register address we want to read */
	out_be32(&regs->miimadd, (mii_id << 8) | regnum);

	/* Clear miimcom, and then initiate a read */
	out_be32(&regs->miimcom, 0);
	out_be32(&regs->miimcom, MII_READ_COMMAND);

	/* Wait for the transaction to finish */
	while (in_be32(&regs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
		cpu_relax();

	/* Grab the value of the register from miimstat */
	value = in_be32(&regs->miimstat);

	return value;
}

static struct fsl_pq_mdio __iomem *fsl_pq_mdio_get_regs(struct mii_bus *bus)
{
	struct fsl_pq_mdio_priv *priv = bus->priv;

	return priv->regs;
}

/*
 * Write value to the PHY at mii_id at register regnum,
 * on the bus, waiting until the write is done before returning.
 */
int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);

	/* Write to the local MII regs */
	return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value));
}

/*
 * Read the bus for PHY at addr mii_id, register regnum, and
 * return the value.  Clears miimcom first.
 */
int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);

	/* Read the local MII regs */
	return(fsl_pq_local_mdio_read(regs, mii_id, regnum));
}

/* Reset the MIIM registers, and wait for the bus to free */
static int fsl_pq_mdio_reset(struct mii_bus *bus)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
	int timeout = PHY_INIT_TIMEOUT;

	mutex_lock(&bus->mdio_lock);

	/* Reset the management interface */
	out_be32(&regs->miimcfg, MIIMCFG_RESET);

	/* Setup the MII Mgmt clock speed */
	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);

	/* Wait until the bus is free */
	while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
		cpu_relax();

	mutex_unlock(&bus->mdio_lock);

	if (timeout < 0) {
		printk(KERN_ERR "%s: The MII Bus is stuck!\n",
				bus->name);
		return -EBUSY;
	}

	return 0;
}

void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
{
	const u32 *addr;
	u64 taddr = OF_BAD_ADDR;

	addr = of_get_address(np, 0, NULL, NULL);
	if (addr)
		taddr = of_translate_address(np, addr);

	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
		(unsigned long long)taddr);
}
EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);

/* Scan the bus in reverse, looking for an empty spot */
static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
{
	int i;

	for (i = PHY_MAX_ADDR; i > 0; i--) {
		u32 phy_id;

		if (get_phy_id(new_bus, i, &phy_id))
			return -1;

		if (phy_id == 0xffffffff)
			break;
	}

	return i;
}


#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
{
	struct gfar __iomem *enet_regs;

	/*
	 * This is mildly evil, but so is our hardware for doing this.
	 * Also, we have to cast back to struct gfar because of
	 * definition weirdness done in gianfar.h.
	 */
	if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
		of_device_is_compatible(np, "fsl,gianfar-tbi") ||
		of_device_is_compatible(np, "gianfar")) {
		enet_regs = (struct gfar __iomem *)regs;
		return &enet_regs->tbipa;
	} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
			of_device_is_compatible(np, "fsl,etsec2-tbi")) {
		return of_iomap(np, 1);
	} else
		return NULL;
}
#endif


#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
{
	struct device_node *np = NULL;
	int err = 0;

	for_each_compatible_node(np, NULL, "ucc_geth") {
		struct resource tempres;

		err = of_address_to_resource(np, 0, &tempres);
		if (err)
			continue;

		/* if our mdio regs fall within this UCC regs range */
		if ((start >= tempres.start) && (end <= tempres.end)) {
			/* Find the id of the UCC */
			const u32 *id;

			id = of_get_property(np, "cell-index", NULL);
			if (!id) {
				id = of_get_property(np, "device-id", NULL);
				if (!id)
					continue;
			}

			*ucc_id = *id;

			return 0;
		}
	}

	if (err)
		return err;
	else
		return -EINVAL;
}
#endif


static int fsl_pq_mdio_probe(struct of_device *ofdev,
		const struct of_device_id *match)
{
	struct device_node *np = ofdev->dev.of_node;
	struct device_node *tbi;
	struct fsl_pq_mdio_priv *priv;
	struct fsl_pq_mdio __iomem *regs = NULL;
	void __iomem *map;
	u32 __iomem *tbipa;
	struct mii_bus *new_bus;
	int tbiaddr = -1;
	const u32 *addrp;
	u64 addr = 0, size = 0;
	int err;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	new_bus = mdiobus_alloc();
	if (!new_bus) {
		err = -ENOMEM;
		goto err_free_priv;
	}

	new_bus->name = "Freescale PowerQUICC MII Bus",
	new_bus->read = &fsl_pq_mdio_read,
	new_bus->write = &fsl_pq_mdio_write,
	new_bus->reset = &fsl_pq_mdio_reset,
	new_bus->priv = priv;
	fsl_pq_mdio_bus_name(new_bus->id, np);

	addrp = of_get_address(np, 0, &size, NULL);
	if (!addrp) {
		err = -EINVAL;
		goto err_free_bus;
	}

	/* Set the PHY base address */
	addr = of_translate_address(np, addrp);
	if (addr == OF_BAD_ADDR) {
		err = -EINVAL;
		goto err_free_bus;
	}

	map = ioremap(addr, size);
	if (!map) {
		err = -ENOMEM;
		goto err_free_bus;
	}
	priv->map = map;

	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
			of_device_is_compatible(np, "fsl,gianfar-tbi") ||
			of_device_is_compatible(np, "fsl,ucc-mdio") ||
			of_device_is_compatible(np, "ucc_geth_phy"))
		map -= offsetof(struct fsl_pq_mdio, miimcfg);
	regs = map;
	priv->regs = regs;

	new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);

	if (NULL == new_bus->irq) {
		err = -ENOMEM;
		goto err_unmap_regs;
	}

	new_bus->parent = &ofdev->dev;
	dev_set_drvdata(&ofdev->dev, new_bus);

	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
			of_device_is_compatible(np, "fsl,gianfar-tbi") ||
			of_device_is_compatible(np, "fsl,etsec2-mdio") ||
			of_device_is_compatible(np, "fsl,etsec2-tbi") ||
			of_device_is_compatible(np, "gianfar")) {
#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
		tbipa = get_gfar_tbipa(regs, np);
		if (!tbipa) {
			err = -EINVAL;
			goto err_free_irqs;
		}
#else
		err = -ENODEV;
		goto err_free_irqs;
#endif
	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
			of_device_is_compatible(np, "ucc_geth_phy")) {
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
		u32 id;
		static u32 mii_mng_master;

		tbipa = &regs->utbipar;

		if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
			goto err_free_irqs;

		if (!mii_mng_master) {
			mii_mng_master = id;
			ucc_set_qe_mux_mii_mng(id - 1);
		}
#else
		err = -ENODEV;
		goto err_free_irqs;
#endif
	} else {
		err = -ENODEV;
		goto err_free_irqs;
	}

	for_each_child_of_node(np, tbi) {
		if (!strncmp(tbi->type, "tbi-phy", 8))
			break;
	}

	if (tbi) {
		const u32 *prop = of_get_property(tbi, "reg", NULL);

		if (prop)
			tbiaddr = *prop;
	}

	if (tbiaddr == -1) {
		out_be32(tbipa, 0);

		tbiaddr = fsl_pq_mdio_find_free(new_bus);
	}

	/*
	 * We define TBIPA at 0 to be illegal, opting to fail for boards that
	 * have PHYs at 1-31, rather than change tbipa and rescan.
	 */
	if (tbiaddr == 0) {
		err = -EBUSY;

		goto err_free_irqs;
	}

	out_be32(tbipa, tbiaddr);

	err = of_mdiobus_register(new_bus, np);
	if (err) {
		printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
				new_bus->name);
		goto err_free_irqs;
	}

	return 0;

err_free_irqs:
	kfree(new_bus->irq);
err_unmap_regs:
	iounmap(priv->map);
err_free_bus:
	kfree(new_bus);
err_free_priv:
	kfree(priv);
	return err;
}


static int fsl_pq_mdio_remove(struct of_device *ofdev)
{
	struct device *device = &ofdev->dev;
	struct mii_bus *bus = dev_get_drvdata(device);
	struct fsl_pq_mdio_priv *priv = bus->priv;

	mdiobus_unregister(bus);

	dev_set_drvdata(device, NULL);

	iounmap(priv->map);
	bus->priv = NULL;
	mdiobus_free(bus);
	kfree(priv);

	return 0;
}

static struct of_device_id fsl_pq_mdio_match[] = {
	{
		.type = "mdio",
		.compatible = "ucc_geth_phy",
	},
	{
		.type = "mdio",
		.compatible = "gianfar",
	},
	{
		.compatible = "fsl,ucc-mdio",
	},
	{
		.compatible = "fsl,gianfar-tbi",
	},
	{
		.compatible = "fsl,gianfar-mdio",
	},
	{
		.compatible = "fsl,etsec2-tbi",
	},
	{
		.compatible = "fsl,etsec2-mdio",
	},
	{},
};
MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);

static struct of_platform_driver fsl_pq_mdio_driver = {
	.driver = {
		.name = "fsl-pq_mdio",
		.owner = THIS_MODULE,
		.of_match_table = fsl_pq_mdio_match,
	},
	.probe = fsl_pq_mdio_probe,
	.remove = fsl_pq_mdio_remove,
};

int __init fsl_pq_mdio_init(void)
{
	return of_register_platform_driver(&fsl_pq_mdio_driver);
}
module_init(fsl_pq_mdio_init);

void fsl_pq_mdio_exit(void)
{
	of_unregister_platform_driver(&fsl_pq_mdio_driver);
}
module_exit(fsl_pq_mdio_exit);
MODULE_LICENSE("GPL");
Commit	Line	Data
1577ecef AF	1	/*
	2	* Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
	3	* Provides Bus interface for MIIM regs
	4	*
	5	* Author: Andy Fleming <afleming@freescale.com>
1d2397d7	6	* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1577ecef	7	*
1d2397d7	8	* Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
1577ecef AF	9	*
	10	* Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/string.h>
	21	#include <linux/errno.h>
	22	#include <linux/unistd.h>
	23	#include <linux/slab.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/init.h>
	26	#include <linux/delay.h>
	27	#include <linux/netdevice.h>
	28	#include <linux/etherdevice.h>
	29	#include <linux/skbuff.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/mm.h>
	32	#include <linux/module.h>
	33	#include <linux/platform_device.h>
	34	#include <linux/crc32.h>
	35	#include <linux/mii.h>
	36	#include <linux/phy.h>
	37	#include <linux/of.h>
324931ba	38	#include <linux/of_mdio.h>
1577ecef AF	39	#include <linux/of_platform.h>
	40
	41	#include <asm/io.h>
	42	#include <asm/irq.h>
	43	#include <asm/uaccess.h>
	44	#include <asm/ucc.h>
	45
	46	#include "gianfar.h"
	47	#include "fsl_pq_mdio.h"
	48
b3319b10 AV	49	struct fsl_pq_mdio_priv {
	50	void __iomem *map;
	51	struct fsl_pq_mdio __iomem *regs;
	52	};
	53
1577ecef AF	54	/*
	55	* Write value to the PHY at mii_id at register regnum,
	56	* on the bus attached to the local interface, which may be different from the
	57	* generic mdio bus (tied to a single interface), waiting until the write is
	58	* done before returning. This is helpful in programming interfaces like
	59	* the TBI which control interfaces like onchip SERDES and are always tied to
	60	* the local mdio pins, which may not be the same as system mdio bus, used for
	61	* controlling the external PHYs, for example.
	62	*/
	63	int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
	64	int regnum, u16 value)
	65	{
	66	/* Set the PHY address and the register address we want to write */
	67	out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	68
	69	/* Write out the value we want */
	70	out_be32(&regs->miimcon, value);
	71
	72	/* Wait for the transaction to finish */
	73	while (in_be32(&regs->miimind) & MIIMIND_BUSY)
	74	cpu_relax();
	75
	76	return 0;
	77	}
	78
	79	/*
	80	* Read the bus for PHY at addr mii_id, register regnum, and
	81	* return the value. Clears miimcom first. All PHY operation
	82	* done on the bus attached to the local interface,
	83	* which may be different from the generic mdio bus
	84	* This is helpful in programming interfaces like
	85	* the TBI which, in turn, control interfaces like onchip SERDES
	86	* and are always tied to the local mdio pins, which may not be the
	87	* same as system mdio bus, used for controlling the external PHYs, for eg.
	88	*/
	89	int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
	90	int mii_id, int regnum)
	91	{
	92	u16 value;
	93
	94	/* Set the PHY address and the register address we want to read */
	95	out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	96
	97	/* Clear miimcom, and then initiate a read */
	98	out_be32(&regs->miimcom, 0);
	99	out_be32(&regs->miimcom, MII_READ_COMMAND);
	100
	101	/* Wait for the transaction to finish */
	102	while (in_be32(&regs->miimind) & (MIIMIND_NOTVALID \| MIIMIND_BUSY))
	103	cpu_relax();
	104
	105	/* Grab the value of the register from miimstat */
	106	value = in_be32(&regs->miimstat);
	107
	108	return value;
	109	}
	110
6748f60b AV	111	static struct fsl_pq_mdio __iomem fsl_pq_mdio_get_regs(struct mii_bus bus)
6748f60b AV	112	{
b3319b10 AV	113	struct fsl_pq_mdio_priv *priv = bus->priv;
	114
	115	return priv->regs;
6748f60b AV	116	}
6748f60b AV	117
1577ecef AF	118	/*
	119	* Write value to the PHY at mii_id at register regnum,
	120	* on the bus, waiting until the write is done before returning.
	121	*/
	122	int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
	123	{
6748f60b	124	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
1577ecef AF	125
	126	/* Write to the local MII regs */
	127	return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value));
	128	}
	129
	130	/*
	131	* Read the bus for PHY at addr mii_id, register regnum, and
	132	* return the value. Clears miimcom first.
	133	*/
	134	int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
	135	{
6748f60b	136	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
1577ecef AF	137
	138	/* Read the local MII regs */
	139	return(fsl_pq_local_mdio_read(regs, mii_id, regnum));
	140	}
	141
	142	/* Reset the MIIM registers, and wait for the bus to free */
	143	static int fsl_pq_mdio_reset(struct mii_bus *bus)
	144	{
6748f60b	145	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
508827ff	146	int timeout = PHY_INIT_TIMEOUT;
1577ecef AF	147
	148	mutex_lock(&bus->mdio_lock);
	149
	150	/* Reset the management interface */
	151	out_be32(&regs->miimcfg, MIIMCFG_RESET);
	152
	153	/* Setup the MII Mgmt clock speed */
	154	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
	155
	156	/* Wait until the bus is free */
	157	while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
	158	cpu_relax();
	159
	160	mutex_unlock(&bus->mdio_lock);
	161
508827ff	162	if (timeout < 0) {
1577ecef AF	163	printk(KERN_ERR "%s: The MII Bus is stuck!\n",
	164	bus->name);
	165	return -EBUSY;
	166	}
	167
	168	return 0;
	169	}
	170
1577ecef AF	171	void fsl_pq_mdio_bus_name(char name, struct device_node np)
1577ecef AF	172	{
18f27383 AV	173	const u32 *addr;
18f27383 AV	174	u64 taddr = OF_BAD_ADDR;
1577ecef	175
18f27383 AV	176	addr = of_get_address(np, 0, NULL, NULL);
	177	if (addr)
	178	taddr = of_translate_address(np, addr);
1577ecef	179
18f27383 AV	180	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
18f27383 AV	181	(unsigned long long)taddr);
1577ecef	182	}
b6bc978b	183	EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);
1577ecef AF	184
	185	/* Scan the bus in reverse, looking for an empty spot */
	186	static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
	187	{
	188	int i;
	189
	190	for (i = PHY_MAX_ADDR; i > 0; i--) {
	191	u32 phy_id;
	192
	193	if (get_phy_id(new_bus, i, &phy_id))
	194	return -1;
	195
	196	if (phy_id == 0xffffffff)
	197	break;
	198	}
	199
	200	return i;
	201	}
	202
	203
e2a61fa3	204	#if defined(CONFIG_GIANFAR) \|\| defined(CONFIG_GIANFAR_MODULE)
1d2397d7	205	static u32 __iomem get_gfar_tbipa(struct fsl_pq_mdio __iomem regs, struct device_node *np)
1577ecef AF	206	{
	207	struct gfar __iomem *enet_regs;
	208
	209	/*
	210	* This is mildly evil, but so is our hardware for doing this.
	211	* Also, we have to cast back to struct gfar because of
	212	* definition weirdness done in gianfar.h.
	213	*/
1d2397d7 SG	214	if(of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	215	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
	216	of_device_is_compatible(np, "gianfar")) {
	217	enet_regs = (struct gfar __iomem *)regs;
	218	return &enet_regs->tbipa;
	219	} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") \|\|
	220	of_device_is_compatible(np, "fsl,etsec2-tbi")) {
3b1fd3e5	221	return of_iomap(np, 1);
1d2397d7 SG	222	} else
1d2397d7 SG	223	return NULL;
1577ecef AF	224	}
	225	#endif
	226
	227
e2a61fa3	228	#if defined(CONFIG_UCC_GETH) \|\| defined(CONFIG_UCC_GETH_MODULE)
1577ecef AF	229	static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
	230	{
	231	struct device_node *np = NULL;
	232	int err = 0;
	233
	234	for_each_compatible_node(np, NULL, "ucc_geth") {
	235	struct resource tempres;
	236
	237	err = of_address_to_resource(np, 0, &tempres);
	238	if (err)
	239	continue;
	240
	241	/* if our mdio regs fall within this UCC regs range */
	242	if ((start >= tempres.start) && (end <= tempres.end)) {
	243	/* Find the id of the UCC */
	244	const u32 *id;
	245
	246	id = of_get_property(np, "cell-index", NULL);
	247	if (!id) {
	248	id = of_get_property(np, "device-id", NULL);
	249	if (!id)
	250	continue;
	251	}
	252
	253	ucc_id = id;
	254
	255	return 0;
	256	}
	257	}
	258
	259	if (err)
	260	return err;
	261	else
	262	return -EINVAL;
	263	}
	264	#endif
	265
	266
	267	static int fsl_pq_mdio_probe(struct of_device *ofdev,
	268	const struct of_device_id *match)
	269	{
61c7a080	270	struct device_node *np = ofdev->dev.of_node;
1577ecef	271	struct device_node *tbi;
b3319b10	272	struct fsl_pq_mdio_priv *priv;
1d2397d7	273	struct fsl_pq_mdio __iomem *regs = NULL;
2951d64e	274	void __iomem *map;
1577ecef AF	275	u32 __iomem *tbipa;
	276	struct mii_bus *new_bus;
	277	int tbiaddr = -1;
3b1fd3e5	278	const u32 *addrp;
2951d64e	279	u64 addr = 0, size = 0;
08d18f3b	280	int err;
1577ecef	281
b3319b10 AV	282	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	283	if (!priv)
	284	return -ENOMEM;
	285
1577ecef	286	new_bus = mdiobus_alloc();
08d18f3b AV	287	if (!new_bus) {
08d18f3b AV	288	err = -ENOMEM;
b3319b10	289	goto err_free_priv;
08d18f3b	290	}
1577ecef AF	291
	292	new_bus->name = "Freescale PowerQUICC MII Bus",
	293	new_bus->read = &fsl_pq_mdio_read,
	294	new_bus->write = &fsl_pq_mdio_write,
	295	new_bus->reset = &fsl_pq_mdio_reset,
b3319b10	296	new_bus->priv = priv;
1577ecef AF	297	fsl_pq_mdio_bus_name(new_bus->id, np);
1577ecef AF	298
3b1fd3e5 AV	299	addrp = of_get_address(np, 0, &size, NULL);
	300	if (!addrp) {
	301	err = -EINVAL;
	302	goto err_free_bus;
	303	}
	304
1577ecef	305	/* Set the PHY base address */
3b1fd3e5 AV	306	addr = of_translate_address(np, addrp);
	307	if (addr == OF_BAD_ADDR) {
	308	err = -EINVAL;
	309	goto err_free_bus;
	310	}
	311
2951d64e AV	312	map = ioremap(addr, size);
2951d64e AV	313	if (!map) {
1577ecef AF	314	err = -ENOMEM;
	315	goto err_free_bus;
	316	}
b3319b10	317	priv->map = map;
1577ecef	318
2951d64e AV	319	if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	320	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
	321	of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
	322	of_device_is_compatible(np, "ucc_geth_phy"))
	323	map -= offsetof(struct fsl_pq_mdio, miimcfg);
	324	regs = map;
b3319b10	325	priv->regs = regs;
1577ecef	326
324931ba	327	new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1577ecef AF	328
	329	if (NULL == new_bus->irq) {
	330	err = -ENOMEM;
	331	goto err_unmap_regs;
	332	}
	333
	334	new_bus->parent = &ofdev->dev;
	335	dev_set_drvdata(&ofdev->dev, new_bus);
	336
	337	if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
30196845	338	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
1d2397d7 SG	339	of_device_is_compatible(np, "fsl,etsec2-mdio") \|\|
1d2397d7 SG	340	of_device_is_compatible(np, "fsl,etsec2-tbi") \|\|
1577ecef	341	of_device_is_compatible(np, "gianfar")) {
e2a61fa3	342	#if defined(CONFIG_GIANFAR) \|\| defined(CONFIG_GIANFAR_MODULE)
1d2397d7 SG	343	tbipa = get_gfar_tbipa(regs, np);
	344	if (!tbipa) {
	345	err = -EINVAL;
	346	goto err_free_irqs;
	347	}
1577ecef AF	348	#else
	349	err = -ENODEV;
	350	goto err_free_irqs;
	351	#endif
	352	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
	353	of_device_is_compatible(np, "ucc_geth_phy")) {
e2a61fa3	354	#if defined(CONFIG_UCC_GETH) \|\| defined(CONFIG_UCC_GETH_MODULE)
1577ecef	355	u32 id;
fbcc0e2c	356	static u32 mii_mng_master;
1577ecef AF	357
	358	tbipa = &regs->utbipar;
	359
	360	if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
	361	goto err_free_irqs;
	362
fbcc0e2c HW	363	if (!mii_mng_master) {
	364	mii_mng_master = id;
	365	ucc_set_qe_mux_mii_mng(id - 1);
	366	}
1577ecef AF	367	#else
	368	err = -ENODEV;
	369	goto err_free_irqs;
	370	#endif
	371	} else {
	372	err = -ENODEV;
	373	goto err_free_irqs;
	374	}
	375
	376	for_each_child_of_node(np, tbi) {
	377	if (!strncmp(tbi->type, "tbi-phy", 8))
	378	break;
	379	}
	380
	381	if (tbi) {
	382	const u32 *prop = of_get_property(tbi, "reg", NULL);
	383
	384	if (prop)
	385	tbiaddr = *prop;
	386	}
	387
	388	if (tbiaddr == -1) {
	389	out_be32(tbipa, 0);
	390
	391	tbiaddr = fsl_pq_mdio_find_free(new_bus);
	392	}
	393
	394	/*
	395	* We define TBIPA at 0 to be illegal, opting to fail for boards that
	396	* have PHYs at 1-31, rather than change tbipa and rescan.
	397	*/
	398	if (tbiaddr == 0) {
	399	err = -EBUSY;
	400
	401	goto err_free_irqs;
	402	}
	403
	404	out_be32(tbipa, tbiaddr);
	405
324931ba	406	err = of_mdiobus_register(new_bus, np);
1577ecef AF	407	if (err) {
	408	printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
	409	new_bus->name);
	410	goto err_free_irqs;
	411	}
	412
	413	return 0;
	414
	415	err_free_irqs:
	416	kfree(new_bus->irq);
	417	err_unmap_regs:
b3319b10	418	iounmap(priv->map);
1577ecef AF	419	err_free_bus:
1577ecef AF	420	kfree(new_bus);
b3319b10 AV	421	err_free_priv:
b3319b10 AV	422	kfree(priv);
1577ecef AF	423	return err;
	424	}
	425
	426
	427	static int fsl_pq_mdio_remove(struct of_device *ofdev)
	428	{
	429	struct device *device = &ofdev->dev;
	430	struct mii_bus *bus = dev_get_drvdata(device);
b3319b10	431	struct fsl_pq_mdio_priv *priv = bus->priv;
1577ecef AF	432
	433	mdiobus_unregister(bus);
	434
	435	dev_set_drvdata(device, NULL);
	436
b3319b10	437	iounmap(priv->map);
1577ecef AF	438	bus->priv = NULL;
1577ecef AF	439	mdiobus_free(bus);
b3319b10	440	kfree(priv);
1577ecef AF	441
	442	return 0;
	443	}
	444
	445	static struct of_device_id fsl_pq_mdio_match[] = {
	446	{
	447	.type = "mdio",
	448	.compatible = "ucc_geth_phy",
	449	},
	450	{
	451	.type = "mdio",
	452	.compatible = "gianfar",
	453	},
	454	{
	455	.compatible = "fsl,ucc-mdio",
	456	},
	457	{
	458	.compatible = "fsl,gianfar-tbi",
	459	},
	460	{
	461	.compatible = "fsl,gianfar-mdio",
	462	},
1d2397d7 SG	463	{
	464	.compatible = "fsl,etsec2-tbi",
	465	},
	466	{
	467	.compatible = "fsl,etsec2-mdio",
	468	},
1577ecef AF	469	{},
1577ecef AF	470	};
e72701ac	471	MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
1577ecef AF	472
1577ecef AF	473	static struct of_platform_driver fsl_pq_mdio_driver = {
4018294b GL	474	.driver = {
	475	.name = "fsl-pq_mdio",
	476	.owner = THIS_MODULE,
	477	.of_match_table = fsl_pq_mdio_match,
	478	},
1577ecef AF	479	.probe = fsl_pq_mdio_probe,
1577ecef AF	480	.remove = fsl_pq_mdio_remove,
1577ecef AF	481	};
	482
	483	int __init fsl_pq_mdio_init(void)
	484	{
	485	return of_register_platform_driver(&fsl_pq_mdio_driver);
	486	}
434e7b0d	487	module_init(fsl_pq_mdio_init);
1577ecef AF	488
	489	void fsl_pq_mdio_exit(void)
	490	{
	491	of_unregister_platform_driver(&fsl_pq_mdio_driver);
	492	}
1577ecef	493	module_exit(fsl_pq_mdio_exit);
26062897	494	MODULE_LICENSE("GPL");