[net-next-2.6.git] / drivers / net / fsl_pq_mdio.c

/*
 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
 * Provides Bus interface for MIIM regs
 *
 * Author: Andy Fleming <afleming@freescale.com>
 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
 *
 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
 *
 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/crc32.h>
#include <linux/mii.h>
#include <linux/phy.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/ucc.h>

#include "gianfar.h"
#include "fsl_pq_mdio.h"

struct fsl_pq_mdio_priv {
	void __iomem *map;
	struct fsl_pq_mdio __iomem *regs;
};

/*
 * Write value to the PHY at mii_id at register regnum,
 * on the bus attached to the local interface, which may be different from the
 * generic mdio bus (tied to a single interface), waiting until the write is
 * done before returning. This is helpful in programming interfaces like
 * the TBI which control interfaces like onchip SERDES and are always tied to
 * the local mdio pins, which may not be the same as system mdio bus, used for
 * controlling the external PHYs, for example.
 */
int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
		int regnum, u16 value)
{
	/* Set the PHY address and the register address we want to write */
	out_be32(&regs->miimadd, (mii_id << 8) | regnum);

	/* Write out the value we want */
	out_be32(&regs->miimcon, value);

	/* Wait for the transaction to finish */
	while (in_be32(&regs->miimind) & MIIMIND_BUSY)
		cpu_relax();

	return 0;
}

/*
 * Read the bus for PHY at addr mii_id, register regnum, and
 * return the value.  Clears miimcom first.  All PHY operation
 * done on the bus attached to the local interface,
 * which may be different from the generic mdio bus
 * This is helpful in programming interfaces like
 * the TBI which, in turn, control interfaces like onchip SERDES
 * and are always tied to the local mdio pins, which may not be the
 * same as system mdio bus, used for controlling the external PHYs, for eg.
 */
int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
		int mii_id, int regnum)
{
	u16 value;

	/* Set the PHY address and the register address we want to read */
	out_be32(&regs->miimadd, (mii_id << 8) | regnum);

	/* Clear miimcom, and then initiate a read */
	out_be32(&regs->miimcom, 0);
	out_be32(&regs->miimcom, MII_READ_COMMAND);

	/* Wait for the transaction to finish */
	while (in_be32(&regs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
		cpu_relax();

	/* Grab the value of the register from miimstat */
	value = in_be32(&regs->miimstat);

	return value;
}

static struct fsl_pq_mdio __iomem *fsl_pq_mdio_get_regs(struct mii_bus *bus)
{
	struct fsl_pq_mdio_priv *priv = bus->priv;

	return priv->regs;
}

/*
 * Write value to the PHY at mii_id at register regnum,
 * on the bus, waiting until the write is done before returning.
 */
int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);

	/* Write to the local MII regs */
	return fsl_pq_local_mdio_write(regs, mii_id, regnum, value);
}

/*
 * Read the bus for PHY at addr mii_id, register regnum, and
 * return the value.  Clears miimcom first.
 */
int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);

	/* Read the local MII regs */
	return fsl_pq_local_mdio_read(regs, mii_id, regnum);
}

/* Reset the MIIM registers, and wait for the bus to free */
static int fsl_pq_mdio_reset(struct mii_bus *bus)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
	int timeout = PHY_INIT_TIMEOUT;

	mutex_lock(&bus->mdio_lock);

	/* Reset the management interface */
	out_be32(&regs->miimcfg, MIIMCFG_RESET);

	/* Setup the MII Mgmt clock speed */
	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);

	/* Wait until the bus is free */
	while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
		cpu_relax();

	mutex_unlock(&bus->mdio_lock);

	if (timeout < 0) {
		printk(KERN_ERR "%s: The MII Bus is stuck!\n",
				bus->name);
		return -EBUSY;
	}

	return 0;
}

void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
{
	const u32 *addr;
	u64 taddr = OF_BAD_ADDR;

	addr = of_get_address(np, 0, NULL, NULL);
	if (addr)
		taddr = of_translate_address(np, addr);

	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
		(unsigned long long)taddr);
}
EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);

/* Scan the bus in reverse, looking for an empty spot */
static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
{
	int i;

	for (i = PHY_MAX_ADDR; i > 0; i--) {
		u32 phy_id;

		if (get_phy_id(new_bus, i, &phy_id))
			return -1;

		if (phy_id == 0xffffffff)
			break;
	}

	return i;
}


#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
{
	struct gfar __iomem *enet_regs;

	/*
	 * This is mildly evil, but so is our hardware for doing this.
	 * Also, we have to cast back to struct gfar because of
	 * definition weirdness done in gianfar.h.
	 */
	if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
		of_device_is_compatible(np, "fsl,gianfar-tbi") ||
		of_device_is_compatible(np, "gianfar")) {
		enet_regs = (struct gfar __iomem *)regs;
		return &enet_regs->tbipa;
	} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
			of_device_is_compatible(np, "fsl,etsec2-tbi")) {
		return of_iomap(np, 1);
	} else
		return NULL;
}
#endif


#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
{
	struct device_node *np = NULL;
	int err = 0;

	for_each_compatible_node(np, NULL, "ucc_geth") {
		struct resource tempres;

		err = of_address_to_resource(np, 0, &tempres);
		if (err)
			continue;

		/* if our mdio regs fall within this UCC regs range */
		if ((start >= tempres.start) && (end <= tempres.end)) {
			/* Find the id of the UCC */
			const u32 *id;

			id = of_get_property(np, "cell-index", NULL);
			if (!id) {
				id = of_get_property(np, "device-id", NULL);
				if (!id)
					continue;
			}

			*ucc_id = *id;

			return 0;
		}
	}

	if (err)
		return err;
	else
		return -EINVAL;
}
#endif


static int fsl_pq_mdio_probe(struct platform_device *ofdev,
		const struct of_device_id *match)
{
	struct device_node *np = ofdev->dev.of_node;
	struct device_node *tbi;
	struct fsl_pq_mdio_priv *priv;
	struct fsl_pq_mdio __iomem *regs = NULL;
	void __iomem *map;
	u32 __iomem *tbipa;
	struct mii_bus *new_bus;
	int tbiaddr = -1;
	const u32 *addrp;
	u64 addr = 0, size = 0;
	int err;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	new_bus = mdiobus_alloc();
	if (!new_bus) {
		err = -ENOMEM;
		goto err_free_priv;
	}

	new_bus->name = "Freescale PowerQUICC MII Bus",
	new_bus->read = &fsl_pq_mdio_read,
	new_bus->write = &fsl_pq_mdio_write,
	new_bus->reset = &fsl_pq_mdio_reset,
	new_bus->priv = priv;
	fsl_pq_mdio_bus_name(new_bus->id, np);

	addrp = of_get_address(np, 0, &size, NULL);
	if (!addrp) {
		err = -EINVAL;
		goto err_free_bus;
	}

	/* Set the PHY base address */
	addr = of_translate_address(np, addrp);
	if (addr == OF_BAD_ADDR) {
		err = -EINVAL;
		goto err_free_bus;
	}

	map = ioremap(addr, size);
	if (!map) {
		err = -ENOMEM;
		goto err_free_bus;
	}
	priv->map = map;

	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
			of_device_is_compatible(np, "fsl,gianfar-tbi") ||
			of_device_is_compatible(np, "fsl,ucc-mdio") ||
			of_device_is_compatible(np, "ucc_geth_phy"))
		map -= offsetof(struct fsl_pq_mdio, miimcfg);
	regs = map;
	priv->regs = regs;

	new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);

	if (NULL == new_bus->irq) {
		err = -ENOMEM;
		goto err_unmap_regs;
	}

	new_bus->parent = &ofdev->dev;
	dev_set_drvdata(&ofdev->dev, new_bus);

	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
			of_device_is_compatible(np, "fsl,gianfar-tbi") ||
			of_device_is_compatible(np, "fsl,etsec2-mdio") ||
			of_device_is_compatible(np, "fsl,etsec2-tbi") ||
			of_device_is_compatible(np, "gianfar")) {
#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
		tbipa = get_gfar_tbipa(regs, np);
		if (!tbipa) {
			err = -EINVAL;
			goto err_free_irqs;
		}
#else
		err = -ENODEV;
		goto err_free_irqs;
#endif
	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
			of_device_is_compatible(np, "ucc_geth_phy")) {
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
		u32 id;
		static u32 mii_mng_master;

		tbipa = &regs->utbipar;

		if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
			goto err_free_irqs;

		if (!mii_mng_master) {
			mii_mng_master = id;
			ucc_set_qe_mux_mii_mng(id - 1);
		}
#else
		err = -ENODEV;
		goto err_free_irqs;
#endif
	} else {
		err = -ENODEV;
		goto err_free_irqs;
	}

	for_each_child_of_node(np, tbi) {
		if (!strncmp(tbi->type, "tbi-phy", 8))
			break;
	}

	if (tbi) {
		const u32 *prop = of_get_property(tbi, "reg", NULL);

		if (prop)
			tbiaddr = *prop;
	}

	if (tbiaddr == -1) {
		out_be32(tbipa, 0);

		tbiaddr = fsl_pq_mdio_find_free(new_bus);
	}

	/*
	 * We define TBIPA at 0 to be illegal, opting to fail for boards that
	 * have PHYs at 1-31, rather than change tbipa and rescan.
	 */
	if (tbiaddr == 0) {
		err = -EBUSY;

		goto err_free_irqs;
	}

	out_be32(tbipa, tbiaddr);

	err = of_mdiobus_register(new_bus, np);
	if (err) {
		printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
				new_bus->name);
		goto err_free_irqs;
	}

	return 0;

err_free_irqs:
	kfree(new_bus->irq);
err_unmap_regs:
	iounmap(priv->map);
err_free_bus:
	kfree(new_bus);
err_free_priv:
	kfree(priv);
	return err;
}


static int fsl_pq_mdio_remove(struct platform_device *ofdev)
{
	struct device *device = &ofdev->dev;
	struct mii_bus *bus = dev_get_drvdata(device);
	struct fsl_pq_mdio_priv *priv = bus->priv;

	mdiobus_unregister(bus);

	dev_set_drvdata(device, NULL);

	iounmap(priv->map);
	bus->priv = NULL;
	mdiobus_free(bus);
	kfree(priv);

	return 0;
}

static struct of_device_id fsl_pq_mdio_match[] = {
	{
		.type = "mdio",
		.compatible = "ucc_geth_phy",
	},
	{
		.type = "mdio",
		.compatible = "gianfar",
	},
	{
		.compatible = "fsl,ucc-mdio",
	},
	{
		.compatible = "fsl,gianfar-tbi",
	},
	{
		.compatible = "fsl,gianfar-mdio",
	},
	{
		.compatible = "fsl,etsec2-tbi",
	},
	{
		.compatible = "fsl,etsec2-mdio",
	},
	{},
};
MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);

static struct of_platform_driver fsl_pq_mdio_driver = {
	.driver = {
		.name = "fsl-pq_mdio",
		.owner = THIS_MODULE,
		.of_match_table = fsl_pq_mdio_match,
	},
	.probe = fsl_pq_mdio_probe,
	.remove = fsl_pq_mdio_remove,
};

int __init fsl_pq_mdio_init(void)
{
	return of_register_platform_driver(&fsl_pq_mdio_driver);
}
module_init(fsl_pq_mdio_init);

void fsl_pq_mdio_exit(void)
{
	of_unregister_platform_driver(&fsl_pq_mdio_driver);
}
module_exit(fsl_pq_mdio_exit);
MODULE_LICENSE("GPL");
Commit	Line	Data
1577ecef AF	1	/*
	2	* Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
	3	* Provides Bus interface for MIIM regs
	4	*
	5	* Author: Andy Fleming <afleming@freescale.com>
1d2397d7	6	* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1577ecef	7	*
1d2397d7	8	* Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
1577ecef AF	9	*
	10	* Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/string.h>
	21	#include <linux/errno.h>
	22	#include <linux/unistd.h>
	23	#include <linux/slab.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/init.h>
	26	#include <linux/delay.h>
	27	#include <linux/netdevice.h>
	28	#include <linux/etherdevice.h>
	29	#include <linux/skbuff.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/mm.h>
	32	#include <linux/module.h>
	33	#include <linux/platform_device.h>
	34	#include <linux/crc32.h>
	35	#include <linux/mii.h>
	36	#include <linux/phy.h>
	37	#include <linux/of.h>
22ae782f	38	#include <linux/of_address.h>
324931ba	39	#include <linux/of_mdio.h>
1577ecef AF	40	#include <linux/of_platform.h>
	41
	42	#include <asm/io.h>
	43	#include <asm/irq.h>
	44	#include <asm/uaccess.h>
	45	#include <asm/ucc.h>
	46
	47	#include "gianfar.h"
	48	#include "fsl_pq_mdio.h"
	49
b3319b10 AV	50	struct fsl_pq_mdio_priv {
	51	void __iomem *map;
	52	struct fsl_pq_mdio __iomem *regs;
	53	};
	54
1577ecef AF	55	/*
	56	* Write value to the PHY at mii_id at register regnum,
	57	* on the bus attached to the local interface, which may be different from the
	58	* generic mdio bus (tied to a single interface), waiting until the write is
	59	* done before returning. This is helpful in programming interfaces like
	60	* the TBI which control interfaces like onchip SERDES and are always tied to
	61	* the local mdio pins, which may not be the same as system mdio bus, used for
	62	* controlling the external PHYs, for example.
	63	*/
	64	int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
	65	int regnum, u16 value)
	66	{
	67	/* Set the PHY address and the register address we want to write */
	68	out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	69
	70	/* Write out the value we want */
	71	out_be32(&regs->miimcon, value);
	72
	73	/* Wait for the transaction to finish */
	74	while (in_be32(&regs->miimind) & MIIMIND_BUSY)
	75	cpu_relax();
	76
	77	return 0;
	78	}
	79
	80	/*
	81	* Read the bus for PHY at addr mii_id, register regnum, and
	82	* return the value. Clears miimcom first. All PHY operation
	83	* done on the bus attached to the local interface,
	84	* which may be different from the generic mdio bus
	85	* This is helpful in programming interfaces like
	86	* the TBI which, in turn, control interfaces like onchip SERDES
	87	* and are always tied to the local mdio pins, which may not be the
	88	* same as system mdio bus, used for controlling the external PHYs, for eg.
	89	*/
	90	int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
	91	int mii_id, int regnum)
	92	{
	93	u16 value;
	94
	95	/* Set the PHY address and the register address we want to read */
	96	out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	97
	98	/* Clear miimcom, and then initiate a read */
	99	out_be32(&regs->miimcom, 0);
	100	out_be32(&regs->miimcom, MII_READ_COMMAND);
	101
	102	/* Wait for the transaction to finish */
	103	while (in_be32(&regs->miimind) & (MIIMIND_NOTVALID \| MIIMIND_BUSY))
	104	cpu_relax();
	105
	106	/* Grab the value of the register from miimstat */
	107	value = in_be32(&regs->miimstat);
	108
	109	return value;
	110	}
	111
6748f60b AV	112	static struct fsl_pq_mdio __iomem fsl_pq_mdio_get_regs(struct mii_bus bus)
6748f60b AV	113	{
b3319b10 AV	114	struct fsl_pq_mdio_priv *priv = bus->priv;
	115
	116	return priv->regs;
6748f60b AV	117	}
6748f60b AV	118
1577ecef AF	119	/*
	120	* Write value to the PHY at mii_id at register regnum,
	121	* on the bus, waiting until the write is done before returning.
	122	*/
	123	int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
	124	{
6748f60b	125	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
1577ecef AF	126
1577ecef AF	127	/* Write to the local MII regs */
807540ba	128	return fsl_pq_local_mdio_write(regs, mii_id, regnum, value);
1577ecef AF	129	}
	130
	131	/*
	132	* Read the bus for PHY at addr mii_id, register regnum, and
	133	* return the value. Clears miimcom first.
	134	*/
	135	int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
	136	{
6748f60b	137	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
1577ecef AF	138
1577ecef AF	139	/* Read the local MII regs */
807540ba	140	return fsl_pq_local_mdio_read(regs, mii_id, regnum);
1577ecef AF	141	}
	142
	143	/* Reset the MIIM registers, and wait for the bus to free */
	144	static int fsl_pq_mdio_reset(struct mii_bus *bus)
	145	{
6748f60b	146	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
508827ff	147	int timeout = PHY_INIT_TIMEOUT;
1577ecef AF	148
	149	mutex_lock(&bus->mdio_lock);
	150
	151	/* Reset the management interface */
	152	out_be32(&regs->miimcfg, MIIMCFG_RESET);
	153
	154	/* Setup the MII Mgmt clock speed */
	155	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
	156
	157	/* Wait until the bus is free */
	158	while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
	159	cpu_relax();
	160
	161	mutex_unlock(&bus->mdio_lock);
	162
508827ff	163	if (timeout < 0) {
1577ecef AF	164	printk(KERN_ERR "%s: The MII Bus is stuck!\n",
	165	bus->name);
	166	return -EBUSY;
	167	}
	168
	169	return 0;
	170	}
	171
1577ecef AF	172	void fsl_pq_mdio_bus_name(char name, struct device_node np)
1577ecef AF	173	{
18f27383 AV	174	const u32 *addr;
18f27383 AV	175	u64 taddr = OF_BAD_ADDR;
1577ecef	176
18f27383 AV	177	addr = of_get_address(np, 0, NULL, NULL);
	178	if (addr)
	179	taddr = of_translate_address(np, addr);
1577ecef	180
18f27383 AV	181	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
18f27383 AV	182	(unsigned long long)taddr);
1577ecef	183	}
b6bc978b	184	EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);
1577ecef AF	185
	186	/* Scan the bus in reverse, looking for an empty spot */
	187	static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
	188	{
	189	int i;
	190
	191	for (i = PHY_MAX_ADDR; i > 0; i--) {
	192	u32 phy_id;
	193
	194	if (get_phy_id(new_bus, i, &phy_id))
	195	return -1;
	196
	197	if (phy_id == 0xffffffff)
	198	break;
	199	}
	200
	201	return i;
	202	}
	203
	204
e2a61fa3	205	#if defined(CONFIG_GIANFAR) \|\| defined(CONFIG_GIANFAR_MODULE)
1d2397d7	206	static u32 __iomem get_gfar_tbipa(struct fsl_pq_mdio __iomem regs, struct device_node *np)
1577ecef AF	207	{
	208	struct gfar __iomem *enet_regs;
	209
	210	/*
	211	* This is mildly evil, but so is our hardware for doing this.
	212	* Also, we have to cast back to struct gfar because of
	213	* definition weirdness done in gianfar.h.
	214	*/
1d2397d7 SG	215	if(of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	216	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
	217	of_device_is_compatible(np, "gianfar")) {
	218	enet_regs = (struct gfar __iomem *)regs;
	219	return &enet_regs->tbipa;
	220	} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") \|\|
	221	of_device_is_compatible(np, "fsl,etsec2-tbi")) {
3b1fd3e5	222	return of_iomap(np, 1);
1d2397d7 SG	223	} else
1d2397d7 SG	224	return NULL;
1577ecef AF	225	}
	226	#endif
	227
	228
e2a61fa3	229	#if defined(CONFIG_UCC_GETH) \|\| defined(CONFIG_UCC_GETH_MODULE)
1577ecef AF	230	static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
	231	{
	232	struct device_node *np = NULL;
	233	int err = 0;
	234
	235	for_each_compatible_node(np, NULL, "ucc_geth") {
	236	struct resource tempres;
	237
	238	err = of_address_to_resource(np, 0, &tempres);
	239	if (err)
	240	continue;
	241
	242	/* if our mdio regs fall within this UCC regs range */
	243	if ((start >= tempres.start) && (end <= tempres.end)) {
	244	/* Find the id of the UCC */
	245	const u32 *id;
	246
	247	id = of_get_property(np, "cell-index", NULL);
	248	if (!id) {
	249	id = of_get_property(np, "device-id", NULL);
	250	if (!id)
	251	continue;
	252	}
	253
	254	ucc_id = id;
	255
	256	return 0;
	257	}
	258	}
	259
	260	if (err)
	261	return err;
	262	else
	263	return -EINVAL;
	264	}
	265	#endif
	266
	267
2dc11581	268	static int fsl_pq_mdio_probe(struct platform_device *ofdev,
1577ecef AF	269	const struct of_device_id *match)
1577ecef AF	270	{
61c7a080	271	struct device_node *np = ofdev->dev.of_node;
1577ecef	272	struct device_node *tbi;
b3319b10	273	struct fsl_pq_mdio_priv *priv;
1d2397d7	274	struct fsl_pq_mdio __iomem *regs = NULL;
2951d64e	275	void __iomem *map;
1577ecef AF	276	u32 __iomem *tbipa;
	277	struct mii_bus *new_bus;
	278	int tbiaddr = -1;
3b1fd3e5	279	const u32 *addrp;
2951d64e	280	u64 addr = 0, size = 0;
08d18f3b	281	int err;
1577ecef	282
b3319b10 AV	283	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	284	if (!priv)
	285	return -ENOMEM;
	286
1577ecef	287	new_bus = mdiobus_alloc();
08d18f3b AV	288	if (!new_bus) {
08d18f3b AV	289	err = -ENOMEM;
b3319b10	290	goto err_free_priv;
08d18f3b	291	}
1577ecef AF	292
	293	new_bus->name = "Freescale PowerQUICC MII Bus",
	294	new_bus->read = &fsl_pq_mdio_read,
	295	new_bus->write = &fsl_pq_mdio_write,
	296	new_bus->reset = &fsl_pq_mdio_reset,
b3319b10	297	new_bus->priv = priv;
1577ecef AF	298	fsl_pq_mdio_bus_name(new_bus->id, np);
1577ecef AF	299
3b1fd3e5 AV	300	addrp = of_get_address(np, 0, &size, NULL);
	301	if (!addrp) {
	302	err = -EINVAL;
	303	goto err_free_bus;
	304	}
	305
1577ecef	306	/* Set the PHY base address */
3b1fd3e5 AV	307	addr = of_translate_address(np, addrp);
	308	if (addr == OF_BAD_ADDR) {
	309	err = -EINVAL;
	310	goto err_free_bus;
	311	}
	312
2951d64e AV	313	map = ioremap(addr, size);
2951d64e AV	314	if (!map) {
1577ecef AF	315	err = -ENOMEM;
	316	goto err_free_bus;
	317	}
b3319b10	318	priv->map = map;
1577ecef	319
2951d64e AV	320	if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	321	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
	322	of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
	323	of_device_is_compatible(np, "ucc_geth_phy"))
	324	map -= offsetof(struct fsl_pq_mdio, miimcfg);
	325	regs = map;
b3319b10	326	priv->regs = regs;
1577ecef	327
324931ba	328	new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1577ecef AF	329
	330	if (NULL == new_bus->irq) {
	331	err = -ENOMEM;
	332	goto err_unmap_regs;
	333	}
	334
	335	new_bus->parent = &ofdev->dev;
	336	dev_set_drvdata(&ofdev->dev, new_bus);
	337
	338	if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
30196845	339	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
1d2397d7 SG	340	of_device_is_compatible(np, "fsl,etsec2-mdio") \|\|
1d2397d7 SG	341	of_device_is_compatible(np, "fsl,etsec2-tbi") \|\|
1577ecef	342	of_device_is_compatible(np, "gianfar")) {
e2a61fa3	343	#if defined(CONFIG_GIANFAR) \|\| defined(CONFIG_GIANFAR_MODULE)
1d2397d7 SG	344	tbipa = get_gfar_tbipa(regs, np);
	345	if (!tbipa) {
	346	err = -EINVAL;
	347	goto err_free_irqs;
	348	}
1577ecef AF	349	#else
	350	err = -ENODEV;
	351	goto err_free_irqs;
	352	#endif
	353	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
	354	of_device_is_compatible(np, "ucc_geth_phy")) {
e2a61fa3	355	#if defined(CONFIG_UCC_GETH) \|\| defined(CONFIG_UCC_GETH_MODULE)
1577ecef	356	u32 id;
fbcc0e2c	357	static u32 mii_mng_master;
1577ecef AF	358
	359	tbipa = &regs->utbipar;
	360
	361	if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
	362	goto err_free_irqs;
	363
fbcc0e2c HW	364	if (!mii_mng_master) {
	365	mii_mng_master = id;
	366	ucc_set_qe_mux_mii_mng(id - 1);
	367	}
1577ecef AF	368	#else
	369	err = -ENODEV;
	370	goto err_free_irqs;
	371	#endif
	372	} else {
	373	err = -ENODEV;
	374	goto err_free_irqs;
	375	}
	376
	377	for_each_child_of_node(np, tbi) {
	378	if (!strncmp(tbi->type, "tbi-phy", 8))
	379	break;
	380	}
	381
	382	if (tbi) {
	383	const u32 *prop = of_get_property(tbi, "reg", NULL);
	384
	385	if (prop)
	386	tbiaddr = *prop;
	387	}
	388
	389	if (tbiaddr == -1) {
	390	out_be32(tbipa, 0);
	391
	392	tbiaddr = fsl_pq_mdio_find_free(new_bus);
	393	}
	394
	395	/*
	396	* We define TBIPA at 0 to be illegal, opting to fail for boards that
	397	* have PHYs at 1-31, rather than change tbipa and rescan.
	398	*/
	399	if (tbiaddr == 0) {
	400	err = -EBUSY;
	401
	402	goto err_free_irqs;
	403	}
	404
	405	out_be32(tbipa, tbiaddr);
	406
324931ba	407	err = of_mdiobus_register(new_bus, np);
1577ecef AF	408	if (err) {
	409	printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
	410	new_bus->name);
	411	goto err_free_irqs;
	412	}
	413
	414	return 0;
	415
	416	err_free_irqs:
	417	kfree(new_bus->irq);
	418	err_unmap_regs:
b3319b10	419	iounmap(priv->map);
1577ecef AF	420	err_free_bus:
1577ecef AF	421	kfree(new_bus);
b3319b10 AV	422	err_free_priv:
b3319b10 AV	423	kfree(priv);
1577ecef AF	424	return err;
	425	}
	426
	427
2dc11581	428	static int fsl_pq_mdio_remove(struct platform_device *ofdev)
1577ecef AF	429	{
	430	struct device *device = &ofdev->dev;
	431	struct mii_bus *bus = dev_get_drvdata(device);
b3319b10	432	struct fsl_pq_mdio_priv *priv = bus->priv;
1577ecef AF	433
	434	mdiobus_unregister(bus);
	435
	436	dev_set_drvdata(device, NULL);
	437
b3319b10	438	iounmap(priv->map);
1577ecef AF	439	bus->priv = NULL;
1577ecef AF	440	mdiobus_free(bus);
b3319b10	441	kfree(priv);
1577ecef AF	442
	443	return 0;
	444	}
	445
	446	static struct of_device_id fsl_pq_mdio_match[] = {
	447	{
	448	.type = "mdio",
	449	.compatible = "ucc_geth_phy",
	450	},
	451	{
	452	.type = "mdio",
	453	.compatible = "gianfar",
	454	},
	455	{
	456	.compatible = "fsl,ucc-mdio",
	457	},
	458	{
	459	.compatible = "fsl,gianfar-tbi",
	460	},
	461	{
	462	.compatible = "fsl,gianfar-mdio",
	463	},
1d2397d7 SG	464	{
	465	.compatible = "fsl,etsec2-tbi",
	466	},
	467	{
	468	.compatible = "fsl,etsec2-mdio",
	469	},
1577ecef AF	470	{},
1577ecef AF	471	};
e72701ac	472	MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
1577ecef AF	473
1577ecef AF	474	static struct of_platform_driver fsl_pq_mdio_driver = {
4018294b GL	475	.driver = {
	476	.name = "fsl-pq_mdio",
	477	.owner = THIS_MODULE,
	478	.of_match_table = fsl_pq_mdio_match,
	479	},
1577ecef AF	480	.probe = fsl_pq_mdio_probe,
1577ecef AF	481	.remove = fsl_pq_mdio_remove,
1577ecef AF	482	};
	483
	484	int __init fsl_pq_mdio_init(void)
	485	{
	486	return of_register_platform_driver(&fsl_pq_mdio_driver);
	487	}
434e7b0d	488	module_init(fsl_pq_mdio_init);
1577ecef AF	489
	490	void fsl_pq_mdio_exit(void)
	491	{
	492	of_unregister_platform_driver(&fsl_pq_mdio_driver);
	493	}
1577ecef	494	module_exit(fsl_pq_mdio_exit);
26062897	495	MODULE_LICENSE("GPL");