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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
1da177e4 LT |
20 | */ |
21 | ||
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/bitops.h> | |
6f501b17 SH |
39 | #include <linux/io.h> |
40 | #include <linux/irq.h> | |
196719ec | 41 | #include <linux/clk.h> |
ead73183 | 42 | #include <linux/platform_device.h> |
e6b043d5 | 43 | #include <linux/phy.h> |
1da177e4 | 44 | |
080853af | 45 | #include <asm/cacheflush.h> |
196719ec SH |
46 | |
47 | #ifndef CONFIG_ARCH_MXC | |
1da177e4 LT |
48 | #include <asm/coldfire.h> |
49 | #include <asm/mcfsim.h> | |
196719ec | 50 | #endif |
6f501b17 | 51 | |
1da177e4 | 52 | #include "fec.h" |
1da177e4 | 53 | |
196719ec SH |
54 | #ifdef CONFIG_ARCH_MXC |
55 | #include <mach/hardware.h> | |
56 | #define FEC_ALIGNMENT 0xf | |
57 | #else | |
58 | #define FEC_ALIGNMENT 0x3 | |
59 | #endif | |
60 | ||
ead73183 SH |
61 | /* |
62 | * Define the fixed address of the FEC hardware. | |
63 | */ | |
87f4abb4 | 64 | #if defined(CONFIG_M5272) |
1da177e4 LT |
65 | |
66 | static unsigned char fec_mac_default[] = { | |
67 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
68 | }; | |
69 | ||
70 | /* | |
71 | * Some hardware gets it MAC address out of local flash memory. | |
72 | * if this is non-zero then assume it is the address to get MAC from. | |
73 | */ | |
74 | #if defined(CONFIG_NETtel) | |
75 | #define FEC_FLASHMAC 0xf0006006 | |
76 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
77 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
78 | #elif defined(CONFIG_CANCam) |
79 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
80 | #elif defined (CONFIG_M5272C3) |
81 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
82 | #elif defined(CONFIG_MOD5272) | |
83 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
84 | #else |
85 | #define FEC_FLASHMAC 0 | |
86 | #endif | |
43be6366 | 87 | #endif /* CONFIG_M5272 */ |
ead73183 | 88 | |
1da177e4 LT |
89 | /* The number of Tx and Rx buffers. These are allocated from the page |
90 | * pool. The code may assume these are power of two, so it it best | |
91 | * to keep them that size. | |
92 | * We don't need to allocate pages for the transmitter. We just use | |
93 | * the skbuffer directly. | |
94 | */ | |
95 | #define FEC_ENET_RX_PAGES 8 | |
96 | #define FEC_ENET_RX_FRSIZE 2048 | |
97 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
98 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
99 | #define FEC_ENET_TX_FRSIZE 2048 | |
100 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
101 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
102 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
103 | ||
562d2f8c | 104 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 105 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
106 | #endif |
107 | ||
22f6b860 | 108 | /* Interrupt events/masks. */ |
1da177e4 LT |
109 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
110 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
111 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
112 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
113 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
114 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
115 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
116 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
117 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
118 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
119 | ||
120 | /* The FEC stores dest/src/type, data, and checksum for receive packets. | |
121 | */ | |
122 | #define PKT_MAXBUF_SIZE 1518 | |
123 | #define PKT_MINBUF_SIZE 64 | |
124 | #define PKT_MAXBLR_SIZE 1520 | |
125 | ||
126 | ||
127 | /* | |
6b265293 | 128 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
129 | * size bits. Other FEC hardware does not, so we need to take that into |
130 | * account when setting it. | |
131 | */ | |
562d2f8c | 132 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
196719ec | 133 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) |
1da177e4 LT |
134 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
135 | #else | |
136 | #define OPT_FRAME_SIZE 0 | |
137 | #endif | |
138 | ||
139 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
140 | * tx_bd_base always point to the base of the buffer descriptors. The | |
141 | * cur_rx and cur_tx point to the currently available buffer. | |
142 | * The dirty_tx tracks the current buffer that is being sent by the | |
143 | * controller. The cur_tx and dirty_tx are equal under both completely | |
144 | * empty and completely full conditions. The empty/ready indicator in | |
145 | * the buffer descriptor determines the actual condition. | |
146 | */ | |
147 | struct fec_enet_private { | |
148 | /* Hardware registers of the FEC device */ | |
f44d6305 | 149 | void __iomem *hwp; |
1da177e4 | 150 | |
cb84d6e7 GU |
151 | struct net_device *netdev; |
152 | ||
ead73183 SH |
153 | struct clk *clk; |
154 | ||
1da177e4 LT |
155 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
156 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
157 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
f0b3fbea | 158 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
1da177e4 LT |
159 | ushort skb_cur; |
160 | ushort skb_dirty; | |
161 | ||
22f6b860 | 162 | /* CPM dual port RAM relative addresses */ |
4661e75b | 163 | dma_addr_t bd_dma; |
22f6b860 | 164 | /* Address of Rx and Tx buffers */ |
2e28532f SH |
165 | struct bufdesc *rx_bd_base; |
166 | struct bufdesc *tx_bd_base; | |
167 | /* The next free ring entry */ | |
168 | struct bufdesc *cur_rx, *cur_tx; | |
22f6b860 | 169 | /* The ring entries to be free()ed */ |
2e28532f SH |
170 | struct bufdesc *dirty_tx; |
171 | ||
1da177e4 | 172 | uint tx_full; |
3b2b74ca SS |
173 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
174 | spinlock_t hw_lock; | |
1da177e4 | 175 | |
e6b043d5 | 176 | struct platform_device *pdev; |
1da177e4 | 177 | |
e6b043d5 | 178 | int opened; |
1da177e4 | 179 | |
e6b043d5 BW |
180 | /* Phylib and MDIO interface */ |
181 | struct mii_bus *mii_bus; | |
182 | struct phy_device *phy_dev; | |
183 | int mii_timeout; | |
184 | uint phy_speed; | |
1da177e4 | 185 | int index; |
1da177e4 | 186 | int link; |
1da177e4 | 187 | int full_duplex; |
1da177e4 LT |
188 | }; |
189 | ||
7d12e780 | 190 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
191 | static void fec_enet_tx(struct net_device *dev); |
192 | static void fec_enet_rx(struct net_device *dev); | |
193 | static int fec_enet_close(struct net_device *dev); | |
1da177e4 LT |
194 | static void fec_restart(struct net_device *dev, int duplex); |
195 | static void fec_stop(struct net_device *dev); | |
1da177e4 | 196 | |
e6b043d5 BW |
197 | /* FEC MII MMFR bits definition */ |
198 | #define FEC_MMFR_ST (1 << 30) | |
199 | #define FEC_MMFR_OP_READ (2 << 28) | |
200 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
201 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
202 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
203 | #define FEC_MMFR_TA (2 << 16) | |
204 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 205 | |
e6b043d5 | 206 | #define FEC_MII_TIMEOUT 10000 |
1da177e4 | 207 | |
22f6b860 SH |
208 | /* Transmitter timeout */ |
209 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 210 | |
1da177e4 LT |
211 | static int |
212 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
213 | { | |
f44d6305 | 214 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 215 | struct bufdesc *bdp; |
9555b31e | 216 | void *bufaddr; |
0e702ab3 | 217 | unsigned short status; |
3b2b74ca | 218 | unsigned long flags; |
1da177e4 | 219 | |
1da177e4 LT |
220 | if (!fep->link) { |
221 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 222 | return NETDEV_TX_BUSY; |
1da177e4 LT |
223 | } |
224 | ||
3b2b74ca | 225 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
226 | /* Fill in a Tx ring entry */ |
227 | bdp = fep->cur_tx; | |
228 | ||
0e702ab3 | 229 | status = bdp->cbd_sc; |
22f6b860 | 230 | |
0e702ab3 | 231 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
232 | /* Ooops. All transmit buffers are full. Bail out. |
233 | * This should not happen, since dev->tbusy should be set. | |
234 | */ | |
235 | printk("%s: tx queue full!.\n", dev->name); | |
3b2b74ca | 236 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
5b548140 | 237 | return NETDEV_TX_BUSY; |
1da177e4 | 238 | } |
1da177e4 | 239 | |
22f6b860 | 240 | /* Clear all of the status flags */ |
0e702ab3 | 241 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 242 | |
22f6b860 | 243 | /* Set buffer length and buffer pointer */ |
9555b31e | 244 | bufaddr = skb->data; |
1da177e4 LT |
245 | bdp->cbd_datlen = skb->len; |
246 | ||
247 | /* | |
22f6b860 SH |
248 | * On some FEC implementations data must be aligned on |
249 | * 4-byte boundaries. Use bounce buffers to copy data | |
250 | * and get it aligned. Ugh. | |
1da177e4 | 251 | */ |
9555b31e | 252 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
1da177e4 LT |
253 | unsigned int index; |
254 | index = bdp - fep->tx_bd_base; | |
6989f512 | 255 | memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len); |
9555b31e | 256 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
257 | } |
258 | ||
22f6b860 | 259 | /* Save skb pointer */ |
1da177e4 LT |
260 | fep->tx_skbuff[fep->skb_cur] = skb; |
261 | ||
09f75cd7 | 262 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 263 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 264 | |
1da177e4 LT |
265 | /* Push the data cache so the CPM does not get stale memory |
266 | * data. | |
267 | */ | |
9555b31e | 268 | bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr, |
f0b3fbea | 269 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 270 | |
0e702ab3 GU |
271 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
272 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 273 | */ |
0e702ab3 | 274 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 275 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 276 | bdp->cbd_sc = status; |
1da177e4 | 277 | |
1da177e4 | 278 | /* Trigger transmission start */ |
f44d6305 | 279 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 280 | |
22f6b860 SH |
281 | /* If this was the last BD in the ring, start at the beginning again. */ |
282 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 283 | bdp = fep->tx_bd_base; |
22f6b860 | 284 | else |
1da177e4 | 285 | bdp++; |
1da177e4 LT |
286 | |
287 | if (bdp == fep->dirty_tx) { | |
288 | fep->tx_full = 1; | |
289 | netif_stop_queue(dev); | |
290 | } | |
291 | ||
2e28532f | 292 | fep->cur_tx = bdp; |
1da177e4 | 293 | |
3b2b74ca | 294 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 | 295 | |
6ed10654 | 296 | return NETDEV_TX_OK; |
1da177e4 LT |
297 | } |
298 | ||
299 | static void | |
300 | fec_timeout(struct net_device *dev) | |
301 | { | |
302 | struct fec_enet_private *fep = netdev_priv(dev); | |
303 | ||
09f75cd7 | 304 | dev->stats.tx_errors++; |
1da177e4 | 305 | |
7dd6a2aa | 306 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
307 | netif_wake_queue(dev); |
308 | } | |
309 | ||
1da177e4 | 310 | static irqreturn_t |
7d12e780 | 311 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
312 | { |
313 | struct net_device *dev = dev_id; | |
f44d6305 | 314 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 315 | uint int_events; |
3b2b74ca | 316 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 317 | |
3b2b74ca | 318 | do { |
f44d6305 SH |
319 | int_events = readl(fep->hwp + FEC_IEVENT); |
320 | writel(int_events, fep->hwp + FEC_IEVENT); | |
1da177e4 | 321 | |
1da177e4 | 322 | if (int_events & FEC_ENET_RXF) { |
3b2b74ca | 323 | ret = IRQ_HANDLED; |
1da177e4 LT |
324 | fec_enet_rx(dev); |
325 | } | |
326 | ||
327 | /* Transmit OK, or non-fatal error. Update the buffer | |
f44d6305 SH |
328 | * descriptors. FEC handles all errors, we just discover |
329 | * them as part of the transmit process. | |
330 | */ | |
1da177e4 | 331 | if (int_events & FEC_ENET_TXF) { |
3b2b74ca | 332 | ret = IRQ_HANDLED; |
1da177e4 LT |
333 | fec_enet_tx(dev); |
334 | } | |
3b2b74ca SS |
335 | } while (int_events); |
336 | ||
337 | return ret; | |
1da177e4 LT |
338 | } |
339 | ||
340 | ||
341 | static void | |
342 | fec_enet_tx(struct net_device *dev) | |
343 | { | |
344 | struct fec_enet_private *fep; | |
2e28532f | 345 | struct bufdesc *bdp; |
0e702ab3 | 346 | unsigned short status; |
1da177e4 LT |
347 | struct sk_buff *skb; |
348 | ||
349 | fep = netdev_priv(dev); | |
81538e74 | 350 | spin_lock(&fep->hw_lock); |
1da177e4 LT |
351 | bdp = fep->dirty_tx; |
352 | ||
0e702ab3 | 353 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
f0b3fbea SH |
354 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
355 | break; | |
356 | ||
357 | dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
358 | bdp->cbd_bufaddr = 0; | |
1da177e4 LT |
359 | |
360 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
361 | /* Check for errors. */ | |
0e702ab3 | 362 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
363 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
364 | BD_ENET_TX_CSL)) { | |
09f75cd7 | 365 | dev->stats.tx_errors++; |
0e702ab3 | 366 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
09f75cd7 | 367 | dev->stats.tx_heartbeat_errors++; |
0e702ab3 | 368 | if (status & BD_ENET_TX_LC) /* Late collision */ |
09f75cd7 | 369 | dev->stats.tx_window_errors++; |
0e702ab3 | 370 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
09f75cd7 | 371 | dev->stats.tx_aborted_errors++; |
0e702ab3 | 372 | if (status & BD_ENET_TX_UN) /* Underrun */ |
09f75cd7 | 373 | dev->stats.tx_fifo_errors++; |
0e702ab3 | 374 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
09f75cd7 | 375 | dev->stats.tx_carrier_errors++; |
1da177e4 | 376 | } else { |
09f75cd7 | 377 | dev->stats.tx_packets++; |
1da177e4 LT |
378 | } |
379 | ||
0e702ab3 | 380 | if (status & BD_ENET_TX_READY) |
1da177e4 | 381 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 382 | |
1da177e4 LT |
383 | /* Deferred means some collisions occurred during transmit, |
384 | * but we eventually sent the packet OK. | |
385 | */ | |
0e702ab3 | 386 | if (status & BD_ENET_TX_DEF) |
09f75cd7 | 387 | dev->stats.collisions++; |
6aa20a22 | 388 | |
22f6b860 | 389 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
390 | dev_kfree_skb_any(skb); |
391 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
392 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 393 | |
22f6b860 | 394 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 395 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
396 | bdp = fep->tx_bd_base; |
397 | else | |
398 | bdp++; | |
6aa20a22 | 399 | |
22f6b860 | 400 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
401 | */ |
402 | if (fep->tx_full) { | |
403 | fep->tx_full = 0; | |
404 | if (netif_queue_stopped(dev)) | |
405 | netif_wake_queue(dev); | |
406 | } | |
407 | } | |
2e28532f | 408 | fep->dirty_tx = bdp; |
81538e74 | 409 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
410 | } |
411 | ||
412 | ||
413 | /* During a receive, the cur_rx points to the current incoming buffer. | |
414 | * When we update through the ring, if the next incoming buffer has | |
415 | * not been given to the system, we just set the empty indicator, | |
416 | * effectively tossing the packet. | |
417 | */ | |
418 | static void | |
419 | fec_enet_rx(struct net_device *dev) | |
420 | { | |
f44d6305 | 421 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 422 | struct bufdesc *bdp; |
0e702ab3 | 423 | unsigned short status; |
1da177e4 LT |
424 | struct sk_buff *skb; |
425 | ushort pkt_len; | |
426 | __u8 *data; | |
6aa20a22 | 427 | |
0e702ab3 GU |
428 | #ifdef CONFIG_M532x |
429 | flush_cache_all(); | |
6aa20a22 | 430 | #endif |
1da177e4 | 431 | |
81538e74 | 432 | spin_lock(&fep->hw_lock); |
3b2b74ca | 433 | |
1da177e4 LT |
434 | /* First, grab all of the stats for the incoming packet. |
435 | * These get messed up if we get called due to a busy condition. | |
436 | */ | |
437 | bdp = fep->cur_rx; | |
438 | ||
22f6b860 | 439 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 440 | |
22f6b860 SH |
441 | /* Since we have allocated space to hold a complete frame, |
442 | * the last indicator should be set. | |
443 | */ | |
444 | if ((status & BD_ENET_RX_LAST) == 0) | |
445 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 446 | |
22f6b860 SH |
447 | if (!fep->opened) |
448 | goto rx_processing_done; | |
1da177e4 | 449 | |
22f6b860 SH |
450 | /* Check for errors. */ |
451 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 452 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
22f6b860 SH |
453 | dev->stats.rx_errors++; |
454 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { | |
455 | /* Frame too long or too short. */ | |
456 | dev->stats.rx_length_errors++; | |
457 | } | |
458 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
459 | dev->stats.rx_frame_errors++; | |
460 | if (status & BD_ENET_RX_CR) /* CRC Error */ | |
461 | dev->stats.rx_crc_errors++; | |
462 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ | |
463 | dev->stats.rx_fifo_errors++; | |
1da177e4 | 464 | } |
1da177e4 | 465 | |
22f6b860 SH |
466 | /* Report late collisions as a frame error. |
467 | * On this error, the BD is closed, but we don't know what we | |
468 | * have in the buffer. So, just drop this frame on the floor. | |
469 | */ | |
470 | if (status & BD_ENET_RX_CL) { | |
471 | dev->stats.rx_errors++; | |
472 | dev->stats.rx_frame_errors++; | |
473 | goto rx_processing_done; | |
474 | } | |
1da177e4 | 475 | |
22f6b860 SH |
476 | /* Process the incoming frame. */ |
477 | dev->stats.rx_packets++; | |
478 | pkt_len = bdp->cbd_datlen; | |
479 | dev->stats.rx_bytes += pkt_len; | |
480 | data = (__u8*)__va(bdp->cbd_bufaddr); | |
1da177e4 | 481 | |
f0b3fbea SH |
482 | dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, |
483 | DMA_FROM_DEVICE); | |
ccdc4f19 | 484 | |
22f6b860 SH |
485 | /* This does 16 byte alignment, exactly what we need. |
486 | * The packet length includes FCS, but we don't want to | |
487 | * include that when passing upstream as it messes up | |
488 | * bridging applications. | |
489 | */ | |
8549889c | 490 | skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 491 | |
8549889c | 492 | if (unlikely(!skb)) { |
22f6b860 SH |
493 | printk("%s: Memory squeeze, dropping packet.\n", |
494 | dev->name); | |
495 | dev->stats.rx_dropped++; | |
496 | } else { | |
8549889c | 497 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
498 | skb_put(skb, pkt_len - 4); /* Make room */ |
499 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
500 | skb->protocol = eth_type_trans(skb, dev); | |
501 | netif_rx(skb); | |
502 | } | |
f0b3fbea SH |
503 | |
504 | bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, | |
505 | DMA_FROM_DEVICE); | |
22f6b860 SH |
506 | rx_processing_done: |
507 | /* Clear the status flags for this buffer */ | |
508 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 509 | |
22f6b860 SH |
510 | /* Mark the buffer empty */ |
511 | status |= BD_ENET_RX_EMPTY; | |
512 | bdp->cbd_sc = status; | |
6aa20a22 | 513 | |
22f6b860 SH |
514 | /* Update BD pointer to next entry */ |
515 | if (status & BD_ENET_RX_WRAP) | |
516 | bdp = fep->rx_bd_base; | |
517 | else | |
518 | bdp++; | |
519 | /* Doing this here will keep the FEC running while we process | |
520 | * incoming frames. On a heavily loaded network, we should be | |
521 | * able to keep up at the expense of system resources. | |
522 | */ | |
523 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
524 | } | |
2e28532f | 525 | fep->cur_rx = bdp; |
1da177e4 | 526 | |
81538e74 | 527 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
528 | } |
529 | ||
e6b043d5 BW |
530 | /* ------------------------------------------------------------------------- */ |
531 | #ifdef CONFIG_M5272 | |
532 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1da177e4 | 533 | { |
e6b043d5 BW |
534 | struct fec_enet_private *fep = netdev_priv(dev); |
535 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1da177e4 | 536 | |
e6b043d5 BW |
537 | if (FEC_FLASHMAC) { |
538 | /* | |
539 | * Get MAC address from FLASH. | |
540 | * If it is all 1's or 0's, use the default. | |
541 | */ | |
542 | iap = (unsigned char *)FEC_FLASHMAC; | |
543 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
544 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
545 | iap = fec_mac_default; | |
546 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
547 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
548 | iap = fec_mac_default; | |
f909b1ef | 549 | } else { |
e6b043d5 BW |
550 | *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW); |
551 | *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
552 | iap = &tmpaddr[0]; | |
1da177e4 LT |
553 | } |
554 | ||
e6b043d5 | 555 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 556 | |
e6b043d5 BW |
557 | /* Adjust MAC if using default MAC address */ |
558 | if (iap == fec_mac_default) | |
559 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 | 560 | } |
e6b043d5 | 561 | #endif |
1da177e4 | 562 | |
e6b043d5 | 563 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 564 | |
e6b043d5 BW |
565 | /* |
566 | * Phy section | |
567 | */ | |
568 | static void fec_enet_adjust_link(struct net_device *dev) | |
1da177e4 LT |
569 | { |
570 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 BW |
571 | struct phy_device *phy_dev = fep->phy_dev; |
572 | unsigned long flags; | |
1da177e4 | 573 | |
e6b043d5 | 574 | int status_change = 0; |
1da177e4 | 575 | |
e6b043d5 | 576 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 577 | |
e6b043d5 BW |
578 | /* Prevent a state halted on mii error */ |
579 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
580 | phy_dev->state = PHY_RESUMING; | |
581 | goto spin_unlock; | |
582 | } | |
1da177e4 | 583 | |
e6b043d5 BW |
584 | /* Duplex link change */ |
585 | if (phy_dev->link) { | |
586 | if (fep->full_duplex != phy_dev->duplex) { | |
587 | fec_restart(dev, phy_dev->duplex); | |
588 | status_change = 1; | |
589 | } | |
590 | } | |
1da177e4 | 591 | |
e6b043d5 BW |
592 | /* Link on or off change */ |
593 | if (phy_dev->link != fep->link) { | |
594 | fep->link = phy_dev->link; | |
595 | if (phy_dev->link) | |
596 | fec_restart(dev, phy_dev->duplex); | |
1da177e4 | 597 | else |
e6b043d5 BW |
598 | fec_stop(dev); |
599 | status_change = 1; | |
1da177e4 | 600 | } |
6aa20a22 | 601 | |
e6b043d5 BW |
602 | spin_unlock: |
603 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 604 | |
e6b043d5 BW |
605 | if (status_change) |
606 | phy_print_status(phy_dev); | |
607 | } | |
1da177e4 | 608 | |
6aa20a22 | 609 | /* |
e6b043d5 | 610 | * NOTE: a MII transaction is during around 25 us, so polling it... |
1da177e4 | 611 | */ |
e6b043d5 | 612 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 613 | { |
e6b043d5 BW |
614 | struct fec_enet_private *fep = bus->priv; |
615 | int timeout = FEC_MII_TIMEOUT; | |
1da177e4 | 616 | |
e6b043d5 | 617 | fep->mii_timeout = 0; |
1da177e4 | 618 | |
e6b043d5 BW |
619 | /* clear MII end of transfer bit*/ |
620 | writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); | |
621 | ||
622 | /* start a read op */ | |
623 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
624 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
625 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
626 | ||
627 | /* wait for end of transfer */ | |
628 | while (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_MII)) { | |
629 | cpu_relax(); | |
630 | if (timeout-- < 0) { | |
631 | fep->mii_timeout = 1; | |
632 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
633 | return -ETIMEDOUT; | |
634 | } | |
1da177e4 | 635 | } |
1da177e4 | 636 | |
e6b043d5 BW |
637 | /* return value */ |
638 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 639 | } |
6aa20a22 | 640 | |
e6b043d5 BW |
641 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
642 | u16 value) | |
1da177e4 | 643 | { |
e6b043d5 BW |
644 | struct fec_enet_private *fep = bus->priv; |
645 | int timeout = FEC_MII_TIMEOUT; | |
1da177e4 | 646 | |
e6b043d5 | 647 | fep->mii_timeout = 0; |
7dd6a2aa | 648 | |
e6b043d5 BW |
649 | /* clear MII end of transfer bit*/ |
650 | writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); | |
1da177e4 | 651 | |
e6b043d5 BW |
652 | /* start a read op */ |
653 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
654 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
655 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
656 | fep->hwp + FEC_MII_DATA); | |
657 | ||
658 | /* wait for end of transfer */ | |
659 | while (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_MII)) { | |
660 | cpu_relax(); | |
661 | if (timeout-- < 0) { | |
662 | fep->mii_timeout = 1; | |
663 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
664 | return -ETIMEDOUT; | |
665 | } | |
666 | } | |
1da177e4 | 667 | |
e6b043d5 BW |
668 | return 0; |
669 | } | |
1da177e4 | 670 | |
e6b043d5 | 671 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 672 | { |
e6b043d5 | 673 | return 0; |
1da177e4 LT |
674 | } |
675 | ||
e6b043d5 | 676 | static int fec_enet_mii_probe(struct net_device *dev) |
562d2f8c | 677 | { |
4cf1653a | 678 | struct fec_enet_private *fep = netdev_priv(dev); |
e6b043d5 BW |
679 | struct phy_device *phy_dev = NULL; |
680 | int phy_addr; | |
562d2f8c | 681 | |
e6b043d5 BW |
682 | /* find the first phy */ |
683 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
684 | if (fep->mii_bus->phy_map[phy_addr]) { | |
685 | phy_dev = fep->mii_bus->phy_map[phy_addr]; | |
686 | break; | |
687 | } | |
688 | } | |
562d2f8c | 689 | |
e6b043d5 BW |
690 | if (!phy_dev) { |
691 | printk(KERN_ERR "%s: no PHY found\n", dev->name); | |
692 | return -ENODEV; | |
693 | } | |
1da177e4 | 694 | |
e6b043d5 BW |
695 | /* attach the mac to the phy */ |
696 | phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), | |
697 | &fec_enet_adjust_link, 0, | |
698 | PHY_INTERFACE_MODE_MII); | |
699 | if (IS_ERR(phy_dev)) { | |
700 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
701 | return PTR_ERR(phy_dev); | |
702 | } | |
1da177e4 | 703 | |
e6b043d5 BW |
704 | /* mask with MAC supported features */ |
705 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
706 | phy_dev->advertising = phy_dev->supported; | |
1da177e4 | 707 | |
e6b043d5 BW |
708 | fep->phy_dev = phy_dev; |
709 | fep->link = 0; | |
710 | fep->full_duplex = 0; | |
1da177e4 | 711 | |
e6b043d5 | 712 | return 0; |
1da177e4 LT |
713 | } |
714 | ||
e6b043d5 | 715 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 716 | { |
e6b043d5 | 717 | struct net_device *dev = platform_get_drvdata(pdev); |
562d2f8c | 718 | struct fec_enet_private *fep = netdev_priv(dev); |
e6b043d5 | 719 | int err = -ENXIO, i; |
6b265293 | 720 | |
e6b043d5 | 721 | fep->mii_timeout = 0; |
1da177e4 | 722 | |
e6b043d5 BW |
723 | /* |
724 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
725 | */ | |
726 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; | |
727 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
1da177e4 | 728 | |
e6b043d5 BW |
729 | fep->mii_bus = mdiobus_alloc(); |
730 | if (fep->mii_bus == NULL) { | |
731 | err = -ENOMEM; | |
732 | goto err_out; | |
1da177e4 LT |
733 | } |
734 | ||
e6b043d5 BW |
735 | fep->mii_bus->name = "fec_enet_mii_bus"; |
736 | fep->mii_bus->read = fec_enet_mdio_read; | |
737 | fep->mii_bus->write = fec_enet_mdio_write; | |
738 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
739 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id); | |
740 | fep->mii_bus->priv = fep; | |
741 | fep->mii_bus->parent = &pdev->dev; | |
742 | ||
743 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
744 | if (!fep->mii_bus->irq) { | |
745 | err = -ENOMEM; | |
746 | goto err_out_free_mdiobus; | |
1da177e4 LT |
747 | } |
748 | ||
e6b043d5 BW |
749 | for (i = 0; i < PHY_MAX_ADDR; i++) |
750 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 751 | |
e6b043d5 | 752 | platform_set_drvdata(dev, fep->mii_bus); |
1da177e4 | 753 | |
e6b043d5 BW |
754 | if (mdiobus_register(fep->mii_bus)) |
755 | goto err_out_free_mdio_irq; | |
1da177e4 | 756 | |
e6b043d5 BW |
757 | if (fec_enet_mii_probe(dev) != 0) |
758 | goto err_out_unregister_bus; | |
6aa20a22 | 759 | |
e6b043d5 | 760 | return 0; |
1da177e4 | 761 | |
e6b043d5 BW |
762 | err_out_unregister_bus: |
763 | mdiobus_unregister(fep->mii_bus); | |
764 | err_out_free_mdio_irq: | |
765 | kfree(fep->mii_bus->irq); | |
766 | err_out_free_mdiobus: | |
767 | mdiobus_free(fep->mii_bus); | |
768 | err_out: | |
769 | return err; | |
1da177e4 LT |
770 | } |
771 | ||
e6b043d5 | 772 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 773 | { |
e6b043d5 BW |
774 | if (fep->phy_dev) |
775 | phy_disconnect(fep->phy_dev); | |
776 | mdiobus_unregister(fep->mii_bus); | |
777 | kfree(fep->mii_bus->irq); | |
778 | mdiobus_free(fep->mii_bus); | |
1da177e4 LT |
779 | } |
780 | ||
e6b043d5 BW |
781 | static int fec_enet_get_settings(struct net_device *dev, |
782 | struct ethtool_cmd *cmd) | |
1da177e4 LT |
783 | { |
784 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 | 785 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 786 | |
e6b043d5 BW |
787 | if (!phydev) |
788 | return -ENODEV; | |
1da177e4 | 789 | |
e6b043d5 | 790 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
791 | } |
792 | ||
e6b043d5 BW |
793 | static int fec_enet_set_settings(struct net_device *dev, |
794 | struct ethtool_cmd *cmd) | |
1da177e4 LT |
795 | { |
796 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 | 797 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 798 | |
e6b043d5 BW |
799 | if (!phydev) |
800 | return -ENODEV; | |
1da177e4 | 801 | |
e6b043d5 | 802 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
803 | } |
804 | ||
e6b043d5 BW |
805 | static void fec_enet_get_drvinfo(struct net_device *dev, |
806 | struct ethtool_drvinfo *info) | |
1da177e4 | 807 | { |
e6b043d5 | 808 | struct fec_enet_private *fep = netdev_priv(dev); |
6aa20a22 | 809 | |
e6b043d5 BW |
810 | strcpy(info->driver, fep->pdev->dev.driver->name); |
811 | strcpy(info->version, "Revision: 1.0"); | |
812 | strcpy(info->bus_info, dev_name(&dev->dev)); | |
1da177e4 LT |
813 | } |
814 | ||
e6b043d5 BW |
815 | static struct ethtool_ops fec_enet_ethtool_ops = { |
816 | .get_settings = fec_enet_get_settings, | |
817 | .set_settings = fec_enet_set_settings, | |
818 | .get_drvinfo = fec_enet_get_drvinfo, | |
819 | .get_link = ethtool_op_get_link, | |
820 | }; | |
1da177e4 | 821 | |
e6b043d5 | 822 | static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1da177e4 | 823 | { |
1da177e4 | 824 | struct fec_enet_private *fep = netdev_priv(dev); |
e6b043d5 | 825 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 826 | |
e6b043d5 BW |
827 | if (!netif_running(dev)) |
828 | return -EINVAL; | |
1da177e4 | 829 | |
e6b043d5 BW |
830 | if (!phydev) |
831 | return -ENODEV; | |
832 | ||
833 | return phy_mii_ioctl(phydev, if_mii(rq), cmd); | |
1da177e4 LT |
834 | } |
835 | ||
f0b3fbea SH |
836 | static void fec_enet_free_buffers(struct net_device *dev) |
837 | { | |
838 | struct fec_enet_private *fep = netdev_priv(dev); | |
839 | int i; | |
840 | struct sk_buff *skb; | |
841 | struct bufdesc *bdp; | |
842 | ||
843 | bdp = fep->rx_bd_base; | |
844 | for (i = 0; i < RX_RING_SIZE; i++) { | |
845 | skb = fep->rx_skbuff[i]; | |
846 | ||
847 | if (bdp->cbd_bufaddr) | |
848 | dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, | |
849 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); | |
850 | if (skb) | |
851 | dev_kfree_skb(skb); | |
852 | bdp++; | |
853 | } | |
854 | ||
855 | bdp = fep->tx_bd_base; | |
856 | for (i = 0; i < TX_RING_SIZE; i++) | |
857 | kfree(fep->tx_bounce[i]); | |
858 | } | |
859 | ||
860 | static int fec_enet_alloc_buffers(struct net_device *dev) | |
861 | { | |
862 | struct fec_enet_private *fep = netdev_priv(dev); | |
863 | int i; | |
864 | struct sk_buff *skb; | |
865 | struct bufdesc *bdp; | |
866 | ||
867 | bdp = fep->rx_bd_base; | |
868 | for (i = 0; i < RX_RING_SIZE; i++) { | |
869 | skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); | |
870 | if (!skb) { | |
871 | fec_enet_free_buffers(dev); | |
872 | return -ENOMEM; | |
873 | } | |
874 | fep->rx_skbuff[i] = skb; | |
875 | ||
876 | bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, | |
877 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); | |
878 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
879 | bdp++; | |
880 | } | |
881 | ||
882 | /* Set the last buffer to wrap. */ | |
883 | bdp--; | |
884 | bdp->cbd_sc |= BD_SC_WRAP; | |
885 | ||
886 | bdp = fep->tx_bd_base; | |
887 | for (i = 0; i < TX_RING_SIZE; i++) { | |
888 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
889 | ||
890 | bdp->cbd_sc = 0; | |
891 | bdp->cbd_bufaddr = 0; | |
892 | bdp++; | |
893 | } | |
894 | ||
895 | /* Set the last buffer to wrap. */ | |
896 | bdp--; | |
897 | bdp->cbd_sc |= BD_SC_WRAP; | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
1da177e4 LT |
902 | static int |
903 | fec_enet_open(struct net_device *dev) | |
904 | { | |
905 | struct fec_enet_private *fep = netdev_priv(dev); | |
f0b3fbea | 906 | int ret; |
1da177e4 LT |
907 | |
908 | /* I should reset the ring buffers here, but I don't yet know | |
909 | * a simple way to do that. | |
910 | */ | |
1da177e4 | 911 | |
f0b3fbea SH |
912 | ret = fec_enet_alloc_buffers(dev); |
913 | if (ret) | |
914 | return ret; | |
915 | ||
e6b043d5 BW |
916 | /* schedule a link state check */ |
917 | phy_start(fep->phy_dev); | |
1da177e4 LT |
918 | netif_start_queue(dev); |
919 | fep->opened = 1; | |
22f6b860 | 920 | return 0; |
1da177e4 LT |
921 | } |
922 | ||
923 | static int | |
924 | fec_enet_close(struct net_device *dev) | |
925 | { | |
926 | struct fec_enet_private *fep = netdev_priv(dev); | |
927 | ||
22f6b860 | 928 | /* Don't know what to do yet. */ |
1da177e4 | 929 | fep->opened = 0; |
e6b043d5 | 930 | phy_stop(fep->phy_dev); |
1da177e4 LT |
931 | netif_stop_queue(dev); |
932 | fec_stop(dev); | |
933 | ||
f0b3fbea SH |
934 | fec_enet_free_buffers(dev); |
935 | ||
1da177e4 LT |
936 | return 0; |
937 | } | |
938 | ||
1da177e4 LT |
939 | /* Set or clear the multicast filter for this adaptor. |
940 | * Skeleton taken from sunlance driver. | |
941 | * The CPM Ethernet implementation allows Multicast as well as individual | |
942 | * MAC address filtering. Some of the drivers check to make sure it is | |
943 | * a group multicast address, and discard those that are not. I guess I | |
944 | * will do the same for now, but just remove the test if you want | |
945 | * individual filtering as well (do the upper net layers want or support | |
946 | * this kind of feature?). | |
947 | */ | |
948 | ||
949 | #define HASH_BITS 6 /* #bits in hash */ | |
950 | #define CRC32_POLY 0xEDB88320 | |
951 | ||
952 | static void set_multicast_list(struct net_device *dev) | |
953 | { | |
f44d6305 | 954 | struct fec_enet_private *fep = netdev_priv(dev); |
22bedad3 | 955 | struct netdev_hw_addr *ha; |
48e2f183 | 956 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
957 | unsigned char hash; |
958 | ||
22f6b860 | 959 | if (dev->flags & IFF_PROMISC) { |
f44d6305 SH |
960 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
961 | tmp |= 0x8; | |
962 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
963 | return; |
964 | } | |
1da177e4 | 965 | |
4e831836 SH |
966 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
967 | tmp &= ~0x8; | |
968 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
969 | ||
970 | if (dev->flags & IFF_ALLMULTI) { | |
971 | /* Catch all multicast addresses, so set the | |
972 | * filter to all 1's | |
973 | */ | |
974 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
975 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
976 | ||
977 | return; | |
978 | } | |
979 | ||
980 | /* Clear filter and add the addresses in hash register | |
981 | */ | |
982 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
983 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
984 | ||
22bedad3 | 985 | netdev_for_each_mc_addr(ha, dev) { |
4e831836 | 986 | /* Only support group multicast for now */ |
22bedad3 | 987 | if (!(ha->addr[0] & 1)) |
4e831836 SH |
988 | continue; |
989 | ||
990 | /* calculate crc32 value of mac address */ | |
991 | crc = 0xffffffff; | |
992 | ||
22bedad3 JP |
993 | for (i = 0; i < dev->addr_len; i++) { |
994 | data = ha->addr[i]; | |
4e831836 SH |
995 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
996 | crc = (crc >> 1) ^ | |
997 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
998 | } |
999 | } | |
4e831836 SH |
1000 | |
1001 | /* only upper 6 bits (HASH_BITS) are used | |
1002 | * which point to specific bit in he hash registers | |
1003 | */ | |
1004 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1005 | ||
1006 | if (hash > 31) { | |
1007 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1008 | tmp |= 1 << (hash - 32); | |
1009 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1010 | } else { | |
1011 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1012 | tmp |= 1 << hash; | |
1013 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1014 | } | |
1da177e4 LT |
1015 | } |
1016 | } | |
1017 | ||
22f6b860 | 1018 | /* Set a MAC change in hardware. */ |
009fda83 SH |
1019 | static int |
1020 | fec_set_mac_address(struct net_device *dev, void *p) | |
1da177e4 | 1021 | { |
f44d6305 | 1022 | struct fec_enet_private *fep = netdev_priv(dev); |
009fda83 SH |
1023 | struct sockaddr *addr = p; |
1024 | ||
1025 | if (!is_valid_ether_addr(addr->sa_data)) | |
1026 | return -EADDRNOTAVAIL; | |
1027 | ||
1028 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
1da177e4 | 1029 | |
f44d6305 SH |
1030 | writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
1031 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), | |
1032 | fep->hwp + FEC_ADDR_LOW); | |
1033 | writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), | |
1034 | fep + FEC_ADDR_HIGH); | |
009fda83 | 1035 | return 0; |
1da177e4 LT |
1036 | } |
1037 | ||
009fda83 SH |
1038 | static const struct net_device_ops fec_netdev_ops = { |
1039 | .ndo_open = fec_enet_open, | |
1040 | .ndo_stop = fec_enet_close, | |
1041 | .ndo_start_xmit = fec_enet_start_xmit, | |
1042 | .ndo_set_multicast_list = set_multicast_list, | |
635ecaa7 | 1043 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1044 | .ndo_validate_addr = eth_validate_addr, |
1045 | .ndo_tx_timeout = fec_timeout, | |
1046 | .ndo_set_mac_address = fec_set_mac_address, | |
e6b043d5 | 1047 | .ndo_do_ioctl = fec_enet_ioctl, |
009fda83 SH |
1048 | }; |
1049 | ||
1da177e4 LT |
1050 | /* |
1051 | * XXX: We need to clean up on failure exits here. | |
ead73183 SH |
1052 | * |
1053 | * index is only used in legacy code | |
1da177e4 | 1054 | */ |
78abcb13 | 1055 | static int fec_enet_init(struct net_device *dev, int index) |
1da177e4 LT |
1056 | { |
1057 | struct fec_enet_private *fep = netdev_priv(dev); | |
f0b3fbea | 1058 | struct bufdesc *cbd_base; |
633e7533 | 1059 | struct bufdesc *bdp; |
f0b3fbea | 1060 | int i; |
1da177e4 | 1061 | |
8d4dd5cf SH |
1062 | /* Allocate memory for buffer descriptors. */ |
1063 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1064 | GFP_KERNEL); | |
1065 | if (!cbd_base) { | |
562d2f8c GU |
1066 | printk("FEC: allocate descriptor memory failed?\n"); |
1067 | return -ENOMEM; | |
1068 | } | |
1069 | ||
3b2b74ca | 1070 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1071 | |
1da177e4 | 1072 | fep->index = index; |
f44d6305 | 1073 | fep->hwp = (void __iomem *)dev->base_addr; |
cb84d6e7 | 1074 | fep->netdev = dev; |
1da177e4 | 1075 | |
ead73183 | 1076 | /* Set the Ethernet address */ |
43be6366 | 1077 | #ifdef CONFIG_M5272 |
1da177e4 | 1078 | fec_get_mac(dev); |
ead73183 SH |
1079 | #else |
1080 | { | |
1081 | unsigned long l; | |
f44d6305 | 1082 | l = readl(fep->hwp + FEC_ADDR_LOW); |
ead73183 SH |
1083 | dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24); |
1084 | dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16); | |
1085 | dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8); | |
1086 | dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0); | |
f44d6305 | 1087 | l = readl(fep->hwp + FEC_ADDR_HIGH); |
ead73183 SH |
1088 | dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24); |
1089 | dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16); | |
1090 | } | |
1091 | #endif | |
1da177e4 | 1092 | |
8d4dd5cf | 1093 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1094 | fep->rx_bd_base = cbd_base; |
1095 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1096 | ||
22f6b860 | 1097 | /* The FEC Ethernet specific entries in the device structure */ |
1da177e4 | 1098 | dev->watchdog_timeo = TX_TIMEOUT; |
009fda83 | 1099 | dev->netdev_ops = &fec_netdev_ops; |
e6b043d5 | 1100 | dev->ethtool_ops = &fec_enet_ethtool_ops; |
633e7533 RH |
1101 | |
1102 | /* Initialize the receive buffer descriptors. */ | |
1103 | bdp = fep->rx_bd_base; | |
1104 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1105 | ||
1106 | /* Initialize the BD for every fragment in the page. */ | |
1107 | bdp->cbd_sc = 0; | |
1108 | bdp++; | |
1109 | } | |
1110 | ||
1111 | /* Set the last buffer to wrap */ | |
1112 | bdp--; | |
1113 | bdp->cbd_sc |= BD_SC_WRAP; | |
1114 | ||
1115 | /* ...and the same for transmit */ | |
1116 | bdp = fep->tx_bd_base; | |
1117 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1118 | ||
1119 | /* Initialize the BD for every fragment in the page. */ | |
1120 | bdp->cbd_sc = 0; | |
1121 | bdp->cbd_bufaddr = 0; | |
1122 | bdp++; | |
1123 | } | |
1124 | ||
1125 | /* Set the last buffer to wrap */ | |
1126 | bdp--; | |
1127 | bdp->cbd_sc |= BD_SC_WRAP; | |
1128 | ||
ead73183 | 1129 | fec_restart(dev, 0); |
1da177e4 | 1130 | |
1da177e4 LT |
1131 | return 0; |
1132 | } | |
1133 | ||
1134 | /* This function is called to start or restart the FEC during a link | |
1135 | * change. This only happens when switching between half and full | |
1136 | * duplex. | |
1137 | */ | |
1138 | static void | |
1139 | fec_restart(struct net_device *dev, int duplex) | |
1140 | { | |
f44d6305 | 1141 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 LT |
1142 | int i; |
1143 | ||
f44d6305 SH |
1144 | /* Whack a reset. We should wait for this. */ |
1145 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
1146 | udelay(10); |
1147 | ||
f44d6305 SH |
1148 | /* Clear any outstanding interrupt. */ |
1149 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 1150 | |
f44d6305 SH |
1151 | /* Reset all multicast. */ |
1152 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1153 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
4f1ceb4b SH |
1154 | #ifndef CONFIG_M5272 |
1155 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
1156 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
1157 | #endif | |
1da177e4 | 1158 | |
f44d6305 SH |
1159 | /* Set maximum receive buffer size. */ |
1160 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 1161 | |
f44d6305 SH |
1162 | /* Set receive and transmit descriptor base. */ |
1163 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
2e28532f | 1164 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, |
f44d6305 | 1165 | fep->hwp + FEC_X_DES_START); |
1da177e4 LT |
1166 | |
1167 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
1168 | fep->cur_rx = fep->rx_bd_base; | |
1169 | ||
f44d6305 | 1170 | /* Reset SKB transmit buffers. */ |
1da177e4 | 1171 | fep->skb_cur = fep->skb_dirty = 0; |
22f6b860 SH |
1172 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
1173 | if (fep->tx_skbuff[i]) { | |
1da177e4 LT |
1174 | dev_kfree_skb_any(fep->tx_skbuff[i]); |
1175 | fep->tx_skbuff[i] = NULL; | |
1176 | } | |
1177 | } | |
1178 | ||
22f6b860 | 1179 | /* Enable MII mode */ |
1da177e4 | 1180 | if (duplex) { |
f44d6305 SH |
1181 | /* MII enable / FD enable */ |
1182 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); | |
1183 | writel(0x04, fep->hwp + FEC_X_CNTRL); | |
f909b1ef | 1184 | } else { |
f44d6305 SH |
1185 | /* MII enable / No Rcv on Xmit */ |
1186 | writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); | |
1187 | writel(0x0, fep->hwp + FEC_X_CNTRL); | |
1da177e4 LT |
1188 | } |
1189 | fep->full_duplex = duplex; | |
1190 | ||
22f6b860 | 1191 | /* Set MII speed */ |
f44d6305 | 1192 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1193 | |
22f6b860 | 1194 | /* And last, enable the transmit and receive processing */ |
f44d6305 SH |
1195 | writel(2, fep->hwp + FEC_ECNTRL); |
1196 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
6b265293 | 1197 | |
22f6b860 | 1198 | /* Enable interrupts we wish to service */ |
e6b043d5 | 1199 | writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->hwp + FEC_IMASK); |
1da177e4 LT |
1200 | } |
1201 | ||
1202 | static void | |
1203 | fec_stop(struct net_device *dev) | |
1204 | { | |
f44d6305 | 1205 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 1206 | |
22f6b860 | 1207 | /* We cannot expect a graceful transmit stop without link !!! */ |
f44d6305 SH |
1208 | if (fep->link) { |
1209 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
677177c5 | 1210 | udelay(10); |
f44d6305 | 1211 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) |
677177c5 | 1212 | printk("fec_stop : Graceful transmit stop did not complete !\n"); |
f44d6305 | 1213 | } |
1da177e4 | 1214 | |
f44d6305 SH |
1215 | /* Whack a reset. We should wait for this. */ |
1216 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
1217 | udelay(10); |
1218 | ||
f44d6305 SH |
1219 | /* Clear outstanding MII command interrupts. */ |
1220 | writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); | |
1da177e4 | 1221 | |
f44d6305 | 1222 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 LT |
1223 | } |
1224 | ||
ead73183 SH |
1225 | static int __devinit |
1226 | fec_probe(struct platform_device *pdev) | |
1227 | { | |
1228 | struct fec_enet_private *fep; | |
1229 | struct net_device *ndev; | |
1230 | int i, irq, ret = 0; | |
1231 | struct resource *r; | |
1232 | ||
1233 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1234 | if (!r) | |
1235 | return -ENXIO; | |
1236 | ||
1237 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1238 | if (!r) | |
1239 | return -EBUSY; | |
1240 | ||
1241 | /* Init network device */ | |
1242 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
1243 | if (!ndev) | |
1244 | return -ENOMEM; | |
1245 | ||
1246 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1247 | ||
1248 | /* setup board info structure */ | |
1249 | fep = netdev_priv(ndev); | |
1250 | memset(fep, 0, sizeof(*fep)); | |
1251 | ||
1252 | ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r)); | |
e6b043d5 | 1253 | fep->pdev = pdev; |
ead73183 SH |
1254 | |
1255 | if (!ndev->base_addr) { | |
1256 | ret = -ENOMEM; | |
1257 | goto failed_ioremap; | |
1258 | } | |
1259 | ||
1260 | platform_set_drvdata(pdev, ndev); | |
1261 | ||
1262 | /* This device has up to three irqs on some platforms */ | |
1263 | for (i = 0; i < 3; i++) { | |
1264 | irq = platform_get_irq(pdev, i); | |
1265 | if (i && irq < 0) | |
1266 | break; | |
1267 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1268 | if (ret) { | |
1269 | while (i >= 0) { | |
1270 | irq = platform_get_irq(pdev, i); | |
1271 | free_irq(irq, ndev); | |
1272 | i--; | |
1273 | } | |
1274 | goto failed_irq; | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | fep->clk = clk_get(&pdev->dev, "fec_clk"); | |
1279 | if (IS_ERR(fep->clk)) { | |
1280 | ret = PTR_ERR(fep->clk); | |
1281 | goto failed_clk; | |
1282 | } | |
1283 | clk_enable(fep->clk); | |
1284 | ||
1285 | ret = fec_enet_init(ndev, 0); | |
1286 | if (ret) | |
1287 | goto failed_init; | |
1288 | ||
e6b043d5 BW |
1289 | ret = fec_enet_mii_init(pdev); |
1290 | if (ret) | |
1291 | goto failed_mii_init; | |
1292 | ||
ead73183 SH |
1293 | ret = register_netdev(ndev); |
1294 | if (ret) | |
1295 | goto failed_register; | |
1296 | ||
e6b043d5 BW |
1297 | printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] " |
1298 | "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name, | |
1299 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
1300 | fep->phy_dev->irq); | |
1301 | ||
ead73183 SH |
1302 | return 0; |
1303 | ||
1304 | failed_register: | |
e6b043d5 BW |
1305 | fec_enet_mii_remove(fep); |
1306 | failed_mii_init: | |
ead73183 SH |
1307 | failed_init: |
1308 | clk_disable(fep->clk); | |
1309 | clk_put(fep->clk); | |
1310 | failed_clk: | |
1311 | for (i = 0; i < 3; i++) { | |
1312 | irq = platform_get_irq(pdev, i); | |
1313 | if (irq > 0) | |
1314 | free_irq(irq, ndev); | |
1315 | } | |
1316 | failed_irq: | |
1317 | iounmap((void __iomem *)ndev->base_addr); | |
1318 | failed_ioremap: | |
1319 | free_netdev(ndev); | |
1320 | ||
1321 | return ret; | |
1322 | } | |
1323 | ||
1324 | static int __devexit | |
1325 | fec_drv_remove(struct platform_device *pdev) | |
1326 | { | |
1327 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1328 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1329 | ||
1330 | platform_set_drvdata(pdev, NULL); | |
1331 | ||
1332 | fec_stop(ndev); | |
e6b043d5 | 1333 | fec_enet_mii_remove(fep); |
ead73183 SH |
1334 | clk_disable(fep->clk); |
1335 | clk_put(fep->clk); | |
1336 | iounmap((void __iomem *)ndev->base_addr); | |
1337 | unregister_netdev(ndev); | |
1338 | free_netdev(ndev); | |
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | static int | |
1343 | fec_suspend(struct platform_device *dev, pm_message_t state) | |
1344 | { | |
1345 | struct net_device *ndev = platform_get_drvdata(dev); | |
1346 | struct fec_enet_private *fep; | |
1347 | ||
1348 | if (ndev) { | |
1349 | fep = netdev_priv(ndev); | |
1350 | if (netif_running(ndev)) { | |
1351 | netif_device_detach(ndev); | |
1352 | fec_stop(ndev); | |
1353 | } | |
1354 | } | |
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int | |
1359 | fec_resume(struct platform_device *dev) | |
1360 | { | |
1361 | struct net_device *ndev = platform_get_drvdata(dev); | |
1362 | ||
1363 | if (ndev) { | |
1364 | if (netif_running(ndev)) { | |
1365 | fec_enet_init(ndev, 0); | |
1366 | netif_device_attach(ndev); | |
1367 | } | |
1368 | } | |
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | static struct platform_driver fec_driver = { | |
1373 | .driver = { | |
1374 | .name = "fec", | |
1375 | .owner = THIS_MODULE, | |
1376 | }, | |
1377 | .probe = fec_probe, | |
1378 | .remove = __devexit_p(fec_drv_remove), | |
1379 | .suspend = fec_suspend, | |
1380 | .resume = fec_resume, | |
1381 | }; | |
1382 | ||
1383 | static int __init | |
1384 | fec_enet_module_init(void) | |
1385 | { | |
1386 | printk(KERN_INFO "FEC Ethernet Driver\n"); | |
1387 | ||
1388 | return platform_driver_register(&fec_driver); | |
1389 | } | |
1390 | ||
1391 | static void __exit | |
1392 | fec_enet_cleanup(void) | |
1393 | { | |
1394 | platform_driver_unregister(&fec_driver); | |
1395 | } | |
1396 | ||
1397 | module_exit(fec_enet_cleanup); | |
1da177e4 LT |
1398 | module_init(fec_enet_module_init); |
1399 | ||
1400 | MODULE_LICENSE("GPL"); |