[net-next-2.6.git] / drivers / net / enic / enic_res.c

/*
 * Copyright 2008 Cisco Systems, Inc.  All rights reserved.
 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
 *
 * This program is free software; you may redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/netdevice.h>

#include "wq_enet_desc.h"
#include "rq_enet_desc.h"
#include "cq_enet_desc.h"
#include "vnic_resource.h"
#include "vnic_enet.h"
#include "vnic_dev.h"
#include "vnic_wq.h"
#include "vnic_rq.h"
#include "vnic_cq.h"
#include "vnic_intr.h"
#include "vnic_stats.h"
#include "vnic_nic.h"
#include "vnic_rss.h"
#include "enic_res.h"
#include "enic.h"

int enic_get_vnic_config(struct enic *enic)
{
	struct vnic_enet_config *c = &enic->config;
	int err;

	err = vnic_dev_mac_addr(enic->vdev, enic->mac_addr);
	if (err) {
		dev_err(enic_get_dev(enic),
			"Error getting MAC addr, %d\n", err);
		return err;
	}

#define GET_CONFIG(m) \
	do { \
		err = vnic_dev_spec(enic->vdev, \
			offsetof(struct vnic_enet_config, m), \
			sizeof(c->m), &c->m); \
		if (err) { \
			dev_err(enic_get_dev(enic), \
				"Error getting %s, %d\n", #m, err); \
			return err; \
		} \
	} while (0)

	GET_CONFIG(flags);
	GET_CONFIG(wq_desc_count);
	GET_CONFIG(rq_desc_count);
	GET_CONFIG(mtu);
	GET_CONFIG(intr_timer_type);
	GET_CONFIG(intr_mode);
	GET_CONFIG(intr_timer_usec);

	c->wq_desc_count =
		min_t(u32, ENIC_MAX_WQ_DESCS,
		max_t(u32, ENIC_MIN_WQ_DESCS,
		c->wq_desc_count));
	c->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */

	c->rq_desc_count =
		min_t(u32, ENIC_MAX_RQ_DESCS,
		max_t(u32, ENIC_MIN_RQ_DESCS,
		c->rq_desc_count));
	c->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */

	if (c->mtu == 0)
		c->mtu = 1500;
	c->mtu = min_t(u16, ENIC_MAX_MTU,
		max_t(u16, ENIC_MIN_MTU,
		c->mtu));

	c->intr_timer_usec = min_t(u32,
		INTR_COALESCE_HW_TO_USEC(VNIC_INTR_TIMER_MAX),
		c->intr_timer_usec);

	dev_info(enic_get_dev(enic), "vNIC MAC addr %pM wq/rq %d/%d\n",
		enic->mac_addr, c->wq_desc_count, c->rq_desc_count);
	dev_info(enic_get_dev(enic), "vNIC mtu %d csum tx/rx %d/%d "
		"tso/lro %d/%d intr timer %d usec\n",
		c->mtu, ENIC_SETTING(enic, TXCSUM),
		ENIC_SETTING(enic, RXCSUM), ENIC_SETTING(enic, TSO),
		ENIC_SETTING(enic, LRO), c->intr_timer_usec);

	return 0;
}

int enic_add_vlan(struct enic *enic, u16 vlanid)
{
	u64 a0 = vlanid, a1 = 0;
	int wait = 1000;
	int err;

	err = vnic_dev_cmd(enic->vdev, CMD_VLAN_ADD, &a0, &a1, wait);
	if (err)
		dev_err(enic_get_dev(enic), "Can't add vlan id, %d\n", err);

	return err;
}

int enic_del_vlan(struct enic *enic, u16 vlanid)
{
	u64 a0 = vlanid, a1 = 0;
	int wait = 1000;
	int err;

	err = vnic_dev_cmd(enic->vdev, CMD_VLAN_DEL, &a0, &a1, wait);
	if (err)
		dev_err(enic_get_dev(enic), "Can't delete vlan id, %d\n", err);

	return err;
}

int enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,
	u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable, u8 tso_ipid_split_en,
	u8 ig_vlan_strip_en)
{
	u64 a0, a1;
	u32 nic_cfg;
	int wait = 1000;

	vnic_set_nic_cfg(&nic_cfg, rss_default_cpu,
		rss_hash_type, rss_hash_bits, rss_base_cpu,
		rss_enable, tso_ipid_split_en, ig_vlan_strip_en);

	a0 = nic_cfg;
	a1 = 0;

	return vnic_dev_cmd(enic->vdev, CMD_NIC_CFG, &a0, &a1, wait);
}

int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len)
{
	u64 a0 = (u64)key_pa, a1 = len;
	int wait = 1000;

	return vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);
}

int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len)
{
	u64 a0 = (u64)cpu_pa, a1 = len;
	int wait = 1000;

	return vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);
}

void enic_free_vnic_resources(struct enic *enic)
{
	unsigned int i;

	for (i = 0; i < enic->wq_count; i++)
		vnic_wq_free(&enic->wq[i]);
	for (i = 0; i < enic->rq_count; i++)
		vnic_rq_free(&enic->rq[i]);
	for (i = 0; i < enic->cq_count; i++)
		vnic_cq_free(&enic->cq[i]);
	for (i = 0; i < enic->intr_count; i++)
		vnic_intr_free(&enic->intr[i]);
}

void enic_get_res_counts(struct enic *enic)
{
	enic->wq_count = min_t(int,
		vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ),
		ENIC_WQ_MAX);
	enic->rq_count = min_t(int,
		vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ),
		ENIC_RQ_MAX);
	enic->cq_count = min_t(int,
		vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ),
		ENIC_CQ_MAX);
	enic->intr_count = min_t(int,
		vnic_dev_get_res_count(enic->vdev, RES_TYPE_INTR_CTRL),
		ENIC_INTR_MAX);

	dev_info(enic_get_dev(enic),
		"vNIC resources avail: wq %d rq %d cq %d intr %d\n",
		enic->wq_count, enic->rq_count,
		enic->cq_count, enic->intr_count);
}

void enic_init_vnic_resources(struct enic *enic)
{
	enum vnic_dev_intr_mode intr_mode;
	unsigned int mask_on_assertion;
	unsigned int interrupt_offset;
	unsigned int error_interrupt_enable;
	unsigned int error_interrupt_offset;
	unsigned int cq_index;
	unsigned int i;

	intr_mode = vnic_dev_get_intr_mode(enic->vdev);

	/* Init RQ/WQ resources.
	 *
	 * RQ[0 - n-1] point to CQ[0 - n-1]
	 * WQ[0 - m-1] point to CQ[n - n+m-1]
	 *
	 * Error interrupt is not enabled for MSI.
	 */

	switch (intr_mode) {
	case VNIC_DEV_INTR_MODE_INTX:
	case VNIC_DEV_INTR_MODE_MSIX:
		error_interrupt_enable = 1;
		error_interrupt_offset = enic->intr_count - 2;
		break;
	default:
		error_interrupt_enable = 0;
		error_interrupt_offset = 0;
		break;
	}

	for (i = 0; i < enic->rq_count; i++) {
		cq_index = i;
		vnic_rq_init(&enic->rq[i],
			cq_index,
			error_interrupt_enable,
			error_interrupt_offset);
	}

	for (i = 0; i < enic->wq_count; i++) {
		cq_index = enic->rq_count + i;
		vnic_wq_init(&enic->wq[i],
			cq_index,
			error_interrupt_enable,
			error_interrupt_offset);
	}

	/* Init CQ resources
	 *
	 * CQ[0 - n+m-1] point to INTR[0] for INTx, MSI
	 * CQ[0 - n+m-1] point to INTR[0 - n+m-1] for MSI-X
	 */

	for (i = 0; i < enic->cq_count; i++) {

		switch (intr_mode) {
		case VNIC_DEV_INTR_MODE_MSIX:
			interrupt_offset = i;
			break;
		default:
			interrupt_offset = 0;
			break;
		}

		vnic_cq_init(&enic->cq[i],
			0 /* flow_control_enable */,
			1 /* color_enable */,
			0 /* cq_head */,
			0 /* cq_tail */,
			1 /* cq_tail_color */,
			1 /* interrupt_enable */,
			1 /* cq_entry_enable */,
			0 /* cq_message_enable */,
			interrupt_offset,
			0 /* cq_message_addr */);
	}

	/* Init INTR resources
	 *
	 * mask_on_assertion is not used for INTx due to the level-
	 * triggered nature of INTx
	 */

	switch (intr_mode) {
	case VNIC_DEV_INTR_MODE_MSI:
	case VNIC_DEV_INTR_MODE_MSIX:
		mask_on_assertion = 1;
		break;
	default:
		mask_on_assertion = 0;
		break;
	}

	for (i = 0; i < enic->intr_count; i++) {
		vnic_intr_init(&enic->intr[i],
			INTR_COALESCE_USEC_TO_HW(enic->config.intr_timer_usec),
			enic->config.intr_timer_type,
			mask_on_assertion);
	}
}

int enic_alloc_vnic_resources(struct enic *enic)
{
	enum vnic_dev_intr_mode intr_mode;
	unsigned int i;
	int err;

	intr_mode = vnic_dev_get_intr_mode(enic->vdev);

	dev_info(enic_get_dev(enic), "vNIC resources used:  "
		"wq %d rq %d cq %d intr %d intr mode %s\n",
		enic->wq_count, enic->rq_count,
		enic->cq_count, enic->intr_count,
		intr_mode == VNIC_DEV_INTR_MODE_INTX ? "legacy PCI INTx" :
		intr_mode == VNIC_DEV_INTR_MODE_MSI ? "MSI" :
		intr_mode == VNIC_DEV_INTR_MODE_MSIX ? "MSI-X" :
		"unknown");

	/* Allocate queue resources
	 */

	for (i = 0; i < enic->wq_count; i++) {
		err = vnic_wq_alloc(enic->vdev, &enic->wq[i], i,
			enic->config.wq_desc_count,
			sizeof(struct wq_enet_desc));
		if (err)
			goto err_out_cleanup;
	}

	for (i = 0; i < enic->rq_count; i++) {
		err = vnic_rq_alloc(enic->vdev, &enic->rq[i], i,
			enic->config.rq_desc_count,
			sizeof(struct rq_enet_desc));
		if (err)
			goto err_out_cleanup;
	}

	for (i = 0; i < enic->cq_count; i++) {
		if (i < enic->rq_count)
			err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
				enic->config.rq_desc_count,
				sizeof(struct cq_enet_rq_desc));
		else
			err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
				enic->config.wq_desc_count,
				sizeof(struct cq_enet_wq_desc));
		if (err)
			goto err_out_cleanup;
	}

	for (i = 0; i < enic->intr_count; i++) {
		err = vnic_intr_alloc(enic->vdev, &enic->intr[i], i);
		if (err)
			goto err_out_cleanup;
	}

	/* Hook remaining resource
	 */

	enic->legacy_pba = vnic_dev_get_res(enic->vdev,
		RES_TYPE_INTR_PBA_LEGACY, 0);
	if (!enic->legacy_pba && intr_mode == VNIC_DEV_INTR_MODE_INTX) {
		dev_err(enic_get_dev(enic),
			"Failed to hook legacy pba resource\n");
		err = -ENODEV;
		goto err_out_cleanup;
	}

	return 0;

err_out_cleanup:
	enic_free_vnic_resources(enic);

	return err;
}
Commit	Line	Data
01f2e4ea SF	1	/*
	2	* Copyright 2008 Cisco Systems, Inc. All rights reserved.
	3	* Copyright 2007 Nuova Systems, Inc. All rights reserved.
	4	*
	5	* This program is free software; you may redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	10	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	11	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	12	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	13	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	14	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	15	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	16	* SOFTWARE.
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/errno.h>
	22	#include <linux/types.h>
	23	#include <linux/pci.h>
	24	#include <linux/netdevice.h>
	25
	26	#include "wq_enet_desc.h"
	27	#include "rq_enet_desc.h"
	28	#include "cq_enet_desc.h"
	29	#include "vnic_resource.h"
	30	#include "vnic_enet.h"
	31	#include "vnic_dev.h"
	32	#include "vnic_wq.h"
	33	#include "vnic_rq.h"
	34	#include "vnic_cq.h"
	35	#include "vnic_intr.h"
	36	#include "vnic_stats.h"
	37	#include "vnic_nic.h"
	38	#include "vnic_rss.h"
	39	#include "enic_res.h"
	40	#include "enic.h"
	41
	42	int enic_get_vnic_config(struct enic *enic)
	43	{
	44	struct vnic_enet_config *c = &enic->config;
	45	int err;
	46
	47	err = vnic_dev_mac_addr(enic->vdev, enic->mac_addr);
	48	if (err) {
a7a79deb VK	49	dev_err(enic_get_dev(enic),
a7a79deb VK	50	"Error getting MAC addr, %d\n", err);
01f2e4ea SF	51	return err;
	52	}
	53
	54	#define GET_CONFIG(m) \
	55	do { \
	56	err = vnic_dev_spec(enic->vdev, \
	57	offsetof(struct vnic_enet_config, m), \
	58	sizeof(c->m), &c->m); \
	59	if (err) { \
a7a79deb	60	dev_err(enic_get_dev(enic), \
01f2e4ea SF	61	"Error getting %s, %d\n", #m, err); \
	62	return err; \
	63	} \
	64	} while (0)
	65
	66	GET_CONFIG(flags);
	67	GET_CONFIG(wq_desc_count);
	68	GET_CONFIG(rq_desc_count);
	69	GET_CONFIG(mtu);
01f2e4ea SF	70	GET_CONFIG(intr_timer_type);
01f2e4ea SF	71	GET_CONFIG(intr_mode);
7c844599	72	GET_CONFIG(intr_timer_usec);
01f2e4ea SF	73
	74	c->wq_desc_count =
	75	min_t(u32, ENIC_MAX_WQ_DESCS,
	76	max_t(u32, ENIC_MIN_WQ_DESCS,
	77	c->wq_desc_count));
bd249622	78	c->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
01f2e4ea SF	79
	80	c->rq_desc_count =
	81	min_t(u32, ENIC_MAX_RQ_DESCS,
	82	max_t(u32, ENIC_MIN_RQ_DESCS,
	83	c->rq_desc_count));
bd249622	84	c->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
01f2e4ea SF	85
	86	if (c->mtu == 0)
	87	c->mtu = 1500;
	88	c->mtu = min_t(u16, ENIC_MAX_MTU,
	89	max_t(u16, ENIC_MIN_MTU,
	90	c->mtu));
	91
7c844599 SF	92	c->intr_timer_usec = min_t(u32,
	93	INTR_COALESCE_HW_TO_USEC(VNIC_INTR_TIMER_MAX),
	94	c->intr_timer_usec);
01f2e4ea	95
a7a79deb	96	dev_info(enic_get_dev(enic), "vNIC MAC addr %pM wq/rq %d/%d\n",
7c510e4b	97	enic->mac_addr, c->wq_desc_count, c->rq_desc_count);
a7a79deb VK	98	dev_info(enic_get_dev(enic), "vNIC mtu %d csum tx/rx %d/%d "
a7a79deb VK	99	"tso/lro %d/%d intr timer %d usec\n",
01f2e4ea SF	100	c->mtu, ENIC_SETTING(enic, TXCSUM),
01f2e4ea SF	101	ENIC_SETTING(enic, RXCSUM), ENIC_SETTING(enic, TSO),
7c844599	102	ENIC_SETTING(enic, LRO), c->intr_timer_usec);
01f2e4ea SF	103
	104	return 0;
	105	}
	106
383ab92f	107	int enic_add_vlan(struct enic *enic, u16 vlanid)
01f2e4ea SF	108	{
	109	u64 a0 = vlanid, a1 = 0;
	110	int wait = 1000;
	111	int err;
	112
	113	err = vnic_dev_cmd(enic->vdev, CMD_VLAN_ADD, &a0, &a1, wait);
	114	if (err)
a7a79deb	115	dev_err(enic_get_dev(enic), "Can't add vlan id, %d\n", err);
383ab92f VK	116
383ab92f VK	117	return err;
01f2e4ea SF	118	}
01f2e4ea SF	119
383ab92f	120	int enic_del_vlan(struct enic *enic, u16 vlanid)
01f2e4ea SF	121	{
	122	u64 a0 = vlanid, a1 = 0;
	123	int wait = 1000;
	124	int err;
	125
	126	err = vnic_dev_cmd(enic->vdev, CMD_VLAN_DEL, &a0, &a1, wait);
	127	if (err)
a7a79deb	128	dev_err(enic_get_dev(enic), "Can't delete vlan id, %d\n", err);
383ab92f VK	129
383ab92f VK	130	return err;
01f2e4ea SF	131	}
	132
	133	int enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,
	134	u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable, u8 tso_ipid_split_en,
	135	u8 ig_vlan_strip_en)
	136	{
	137	u64 a0, a1;
	138	u32 nic_cfg;
	139	int wait = 1000;
	140
	141	vnic_set_nic_cfg(&nic_cfg, rss_default_cpu,
	142	rss_hash_type, rss_hash_bits, rss_base_cpu,
	143	rss_enable, tso_ipid_split_en, ig_vlan_strip_en);
	144
	145	a0 = nic_cfg;
	146	a1 = 0;
	147
	148	return vnic_dev_cmd(enic->vdev, CMD_NIC_CFG, &a0, &a1, wait);
	149	}
	150
6ba9cdc0 SF	151	int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len)
	152	{
	153	u64 a0 = (u64)key_pa, a1 = len;
	154	int wait = 1000;
	155
	156	return vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);
	157	}
	158
	159	int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len)
	160	{
	161	u64 a0 = (u64)cpu_pa, a1 = len;
	162	int wait = 1000;
	163
	164	return vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);
	165	}
	166
01f2e4ea SF	167	void enic_free_vnic_resources(struct enic *enic)
	168	{
	169	unsigned int i;
	170
	171	for (i = 0; i < enic->wq_count; i++)
	172	vnic_wq_free(&enic->wq[i]);
	173	for (i = 0; i < enic->rq_count; i++)
	174	vnic_rq_free(&enic->rq[i]);
	175	for (i = 0; i < enic->cq_count; i++)
	176	vnic_cq_free(&enic->cq[i]);
	177	for (i = 0; i < enic->intr_count; i++)
	178	vnic_intr_free(&enic->intr[i]);
	179	}
	180
	181	void enic_get_res_counts(struct enic *enic)
	182	{
6ba9cdc0 SF	183	enic->wq_count = min_t(int,
	184	vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ),
	185	ENIC_WQ_MAX);
	186	enic->rq_count = min_t(int,
	187	vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ),
	188	ENIC_RQ_MAX);
	189	enic->cq_count = min_t(int,
	190	vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ),
	191	ENIC_CQ_MAX);
	192	enic->intr_count = min_t(int,
	193	vnic_dev_get_res_count(enic->vdev, RES_TYPE_INTR_CTRL),
	194	ENIC_INTR_MAX);
01f2e4ea	195
a7a79deb VK	196	dev_info(enic_get_dev(enic),
a7a79deb VK	197	"vNIC resources avail: wq %d rq %d cq %d intr %d\n",
01f2e4ea SF	198	enic->wq_count, enic->rq_count,
	199	enic->cq_count, enic->intr_count);
	200	}
	201
	202	void enic_init_vnic_resources(struct enic *enic)
	203	{
	204	enum vnic_dev_intr_mode intr_mode;
	205	unsigned int mask_on_assertion;
	206	unsigned int interrupt_offset;
	207	unsigned int error_interrupt_enable;
	208	unsigned int error_interrupt_offset;
	209	unsigned int cq_index;
	210	unsigned int i;
	211
	212	intr_mode = vnic_dev_get_intr_mode(enic->vdev);
	213
	214	/* Init RQ/WQ resources.
	215	*
	216	* RQ[0 - n-1] point to CQ[0 - n-1]
	217	* WQ[0 - m-1] point to CQ[n - n+m-1]
	218	*
	219	* Error interrupt is not enabled for MSI.
	220	*/
	221
	222	switch (intr_mode) {
	223	case VNIC_DEV_INTR_MODE_INTX:
	224	case VNIC_DEV_INTR_MODE_MSIX:
	225	error_interrupt_enable = 1;
	226	error_interrupt_offset = enic->intr_count - 2;
	227	break;
	228	default:
	229	error_interrupt_enable = 0;
	230	error_interrupt_offset = 0;
	231	break;
	232	}
	233
	234	for (i = 0; i < enic->rq_count; i++) {
	235	cq_index = i;
	236	vnic_rq_init(&enic->rq[i],
	237	cq_index,
	238	error_interrupt_enable,
	239	error_interrupt_offset);
	240	}
	241
	242	for (i = 0; i < enic->wq_count; i++) {
	243	cq_index = enic->rq_count + i;
	244	vnic_wq_init(&enic->wq[i],
	245	cq_index,
	246	error_interrupt_enable,
	247	error_interrupt_offset);
	248	}
	249
	250	/* Init CQ resources
	251	*
	252	* CQ[0 - n+m-1] point to INTR[0] for INTx, MSI
	253	* CQ[0 - n+m-1] point to INTR[0 - n+m-1] for MSI-X
	254	*/
	255
	256	for (i = 0; i < enic->cq_count; i++) {
	257
	258	switch (intr_mode) {
	259	case VNIC_DEV_INTR_MODE_MSIX:
	260	interrupt_offset = i;
	261	break;
262	default:
263	interrupt_offset = 0;
264	break;
265	}
266
267	vnic_cq_init(&enic->cq[i],
268	0 /* flow_control_enable */,
269	1 /* color_enable */,
270	0 /* cq_head */,
271	0 /* cq_tail */,
272	1 /* cq_tail_color */,
273	1 /* interrupt_enable */,
274	1 /* cq_entry_enable */,
275	0 /* cq_message_enable */,
276	interrupt_offset,
277	0 /* cq_message_addr */);
278	}
279
280	/* Init INTR resources
281	*
282	* mask_on_assertion is not used for INTx due to the level-
283	* triggered nature of INTx
284	*/
285
286	switch (intr_mode) {
287	case VNIC_DEV_INTR_MODE_MSI:
288	case VNIC_DEV_INTR_MODE_MSIX:
289	mask_on_assertion = 1;
290	break;
291	default:
292	mask_on_assertion = 0;
293	break;
294	}
295
296	for (i = 0; i < enic->intr_count; i++) {
297	vnic_intr_init(&enic->intr[i],
7c844599	298	INTR_COALESCE_USEC_TO_HW(enic->config.intr_timer_usec),
01f2e4ea SF	299	enic->config.intr_timer_type,
	300	mask_on_assertion);
	301	}
01f2e4ea SF	302	}
	303
	304	int enic_alloc_vnic_resources(struct enic *enic)
	305	{
	306	enum vnic_dev_intr_mode intr_mode;
	307	unsigned int i;
	308	int err;
	309
	310	intr_mode = vnic_dev_get_intr_mode(enic->vdev);
	311
a7a79deb	312	dev_info(enic_get_dev(enic), "vNIC resources used: "
01f2e4ea SF	313	"wq %d rq %d cq %d intr %d intr mode %s\n",
	314	enic->wq_count, enic->rq_count,
	315	enic->cq_count, enic->intr_count,
	316	intr_mode == VNIC_DEV_INTR_MODE_INTX ? "legacy PCI INTx" :
	317	intr_mode == VNIC_DEV_INTR_MODE_MSI ? "MSI" :
	318	intr_mode == VNIC_DEV_INTR_MODE_MSIX ? "MSI-X" :
a7a79deb	319	"unknown");
01f2e4ea SF	320
	321	/* Allocate queue resources
	322	*/
	323
	324	for (i = 0; i < enic->wq_count; i++) {
	325	err = vnic_wq_alloc(enic->vdev, &enic->wq[i], i,
	326	enic->config.wq_desc_count,
	327	sizeof(struct wq_enet_desc));
	328	if (err)
	329	goto err_out_cleanup;
	330	}
	331
	332	for (i = 0; i < enic->rq_count; i++) {
	333	err = vnic_rq_alloc(enic->vdev, &enic->rq[i], i,
	334	enic->config.rq_desc_count,
	335	sizeof(struct rq_enet_desc));
	336	if (err)
	337	goto err_out_cleanup;
	338	}
	339
	340	for (i = 0; i < enic->cq_count; i++) {
	341	if (i < enic->rq_count)
	342	err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
	343	enic->config.rq_desc_count,
	344	sizeof(struct cq_enet_rq_desc));
	345	else
	346	err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
	347	enic->config.wq_desc_count,
	348	sizeof(struct cq_enet_wq_desc));
	349	if (err)
	350	goto err_out_cleanup;
	351	}
	352
	353	for (i = 0; i < enic->intr_count; i++) {
	354	err = vnic_intr_alloc(enic->vdev, &enic->intr[i], i);
	355	if (err)
	356	goto err_out_cleanup;
	357	}
	358
	359	/* Hook remaining resource
	360	*/
	361
	362	enic->legacy_pba = vnic_dev_get_res(enic->vdev,
	363	RES_TYPE_INTR_PBA_LEGACY, 0);
	364	if (!enic->legacy_pba && intr_mode == VNIC_DEV_INTR_MODE_INTX) {
a7a79deb VK	365	dev_err(enic_get_dev(enic),
a7a79deb VK	366	"Failed to hook legacy pba resource\n");
01f2e4ea SF	367	err = -ENODEV;
	368	goto err_out_cleanup;
	369	}
	370
	371	return 0;
	372
	373	err_out_cleanup:
	374	enic_free_vnic_resources(enic);
	375
	376	return err;
	377	}