[net-next-2.6.git] / drivers / net / enic / enic.h

/*
 * Copyright 2008 Cisco Systems, Inc.  All rights reserved.
 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
 *
 * This program is free software; you may redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef _ENIC_H_
#define _ENIC_H_

#include <linux/inet_lro.h>

#include "vnic_enet.h"
#include "vnic_dev.h"
#include "vnic_wq.h"
#include "vnic_rq.h"
#include "vnic_cq.h"
#include "vnic_intr.h"
#include "vnic_stats.h"
#include "vnic_rss.h"

#define DRV_NAME		"enic"
#define DRV_DESCRIPTION		"Cisco 10G Ethernet Driver"
#define DRV_VERSION		"1.1.0.100"
#define DRV_COPYRIGHT		"Copyright 2008-2009 Cisco Systems, Inc"
#define PFX			DRV_NAME ": "

#define ENIC_LRO_MAX_DESC	8
#define ENIC_LRO_MAX_AGGR	64

#define ENIC_BARS_MAX		6

enum enic_cq_index {
	ENIC_CQ_RQ,
	ENIC_CQ_WQ,
	ENIC_CQ_MAX,
};

enum enic_intx_intr_index {
	ENIC_INTX_WQ_RQ,
	ENIC_INTX_ERR,
	ENIC_INTX_NOTIFY,
	ENIC_INTX_MAX,
};

enum enic_msix_intr_index {
	ENIC_MSIX_RQ,
	ENIC_MSIX_WQ,
	ENIC_MSIX_ERR,
	ENIC_MSIX_NOTIFY,
	ENIC_MSIX_MAX,
};

struct enic_msix_entry {
	int requested;
	char devname[IFNAMSIZ];
	irqreturn_t (*isr)(int, void *);
	void *devid;
};

/* Per-instance private data structure */
struct enic {
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct vnic_enet_config config;
	struct vnic_dev_bar bar[ENIC_BARS_MAX];
	struct vnic_dev *vdev;
	struct timer_list notify_timer;
	struct work_struct reset;
	struct msix_entry msix_entry[ENIC_MSIX_MAX];
	struct enic_msix_entry msix[ENIC_MSIX_MAX];
	u32 msg_enable;
	spinlock_t devcmd_lock;
	u8 mac_addr[ETH_ALEN];
	u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN];
	unsigned int mc_count;
	int csum_rx_enabled;
	u32 port_mtu;

	/* work queue cache line section */
	____cacheline_aligned struct vnic_wq wq[1];
	spinlock_t wq_lock[1];
	unsigned int wq_count;
	struct vlan_group *vlan_group;

	/* receive queue cache line section */
	____cacheline_aligned struct vnic_rq rq[1];
	unsigned int rq_count;
	int (*rq_alloc_buf)(struct vnic_rq *rq);
	u64 rq_bad_fcs;
	struct napi_struct napi;
	struct net_lro_mgr lro_mgr;
	struct net_lro_desc lro_desc[ENIC_LRO_MAX_DESC];

	/* interrupt resource cache line section */
	____cacheline_aligned struct vnic_intr intr[ENIC_MSIX_MAX];
	unsigned int intr_count;
	u32 __iomem *legacy_pba;		/* memory-mapped */

	/* completion queue cache line section */
	____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
	unsigned int cq_count;
};

#endif /* _ENIC_H_ */
Commit	Line	Data
01f2e4ea SF	1	/*
	2	* Copyright 2008 Cisco Systems, Inc. All rights reserved.
	3	* Copyright 2007 Nuova Systems, Inc. All rights reserved.
	4	*
	5	* This program is free software; you may redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	10	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	11	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	12	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	13	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	14	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	15	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	16	* SOFTWARE.
	17	*
	18	*/
	19
	20	#ifndef _ENIC_H_
	21	#define _ENIC_H_
	22
	23	#include <linux/inet_lro.h>
	24
	25	#include "vnic_enet.h"
	26	#include "vnic_dev.h"
	27	#include "vnic_wq.h"
	28	#include "vnic_rq.h"
	29	#include "vnic_cq.h"
	30	#include "vnic_intr.h"
	31	#include "vnic_stats.h"
	32	#include "vnic_rss.h"
	33
	34	#define DRV_NAME "enic"
	35	#define DRV_DESCRIPTION "Cisco 10G Ethernet Driver"
27e6c7d3 SF	36	#define DRV_VERSION "1.1.0.100"
27e6c7d3 SF	37	#define DRV_COPYRIGHT "Copyright 2008-2009 Cisco Systems, Inc"
01f2e4ea SF	38	#define PFX DRV_NAME ": "
	39
	40	#define ENIC_LRO_MAX_DESC 8
	41	#define ENIC_LRO_MAX_AGGR 64
	42
27e6c7d3 SF	43	#define ENIC_BARS_MAX 6
27e6c7d3 SF	44
01f2e4ea SF	45	enum enic_cq_index {
	46	ENIC_CQ_RQ,
	47	ENIC_CQ_WQ,
	48	ENIC_CQ_MAX,
	49	};
	50
	51	enum enic_intx_intr_index {
	52	ENIC_INTX_WQ_RQ,
	53	ENIC_INTX_ERR,
	54	ENIC_INTX_NOTIFY,
	55	ENIC_INTX_MAX,
	56	};
	57
	58	enum enic_msix_intr_index {
	59	ENIC_MSIX_RQ,
	60	ENIC_MSIX_WQ,
	61	ENIC_MSIX_ERR,
	62	ENIC_MSIX_NOTIFY,
	63	ENIC_MSIX_MAX,
	64	};
	65
	66	struct enic_msix_entry {
	67	int requested;
	68	char devname[IFNAMSIZ];
	69	irqreturn_t (isr)(int, void );
	70	void *devid;
	71	};
	72
	73	/* Per-instance private data structure */
	74	struct enic {
	75	struct net_device *netdev;
	76	struct pci_dev *pdev;
	77	struct vnic_enet_config config;
27e6c7d3	78	struct vnic_dev_bar bar[ENIC_BARS_MAX];
01f2e4ea	79	struct vnic_dev *vdev;
01f2e4ea SF	80	struct timer_list notify_timer;
	81	struct work_struct reset;
	82	struct msix_entry msix_entry[ENIC_MSIX_MAX];
	83	struct enic_msix_entry msix[ENIC_MSIX_MAX];
	84	u32 msg_enable;
	85	spinlock_t devcmd_lock;
	86	u8 mac_addr[ETH_ALEN];
	87	u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN];
	88	unsigned int mc_count;
	89	int csum_rx_enabled;
	90	u32 port_mtu;
	91
	92	/* work queue cache line section */
	93	____cacheline_aligned struct vnic_wq wq[1];
	94	spinlock_t wq_lock[1];
	95	unsigned int wq_count;
	96	struct vlan_group *vlan_group;
	97
	98	/* receive queue cache line section */
	99	____cacheline_aligned struct vnic_rq rq[1];
	100	unsigned int rq_count;
	101	int (rq_alloc_buf)(struct vnic_rq rq);
bd9fb1a4	102	u64 rq_bad_fcs;
01f2e4ea SF	103	struct napi_struct napi;
	104	struct net_lro_mgr lro_mgr;
	105	struct net_lro_desc lro_desc[ENIC_LRO_MAX_DESC];
	106
	107	/* interrupt resource cache line section */
	108	____cacheline_aligned struct vnic_intr intr[ENIC_MSIX_MAX];
	109	unsigned int intr_count;
	110	u32 __iomem legacy_pba; / memory-mapped */
	111
	112	/* completion queue cache line section */
	113	____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
	114	unsigned int cq_count;
	115	};
	116
	117	#endif /* _ENIC_H_ */