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[net-next-2.6.git] / drivers / net / enc28j60.c
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3ec9c11d
CL		 1/*
2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
3 *
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/slab.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/tcp.h>
29#include <linux/skbuff.h>
30#include <linux/delay.h>
31#include <linux/spi/spi.h>
32
33#include "enc28j60_hw.h"
34
35#define DRV_NAME "enc28j60"
36#define DRV_VERSION "1.01"
37
38#define SPI_OPLEN 1
39
40#define ENC28J60_MSG_DEFAULT \
41 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
42
43/* Buffer size required for the largest SPI transfer (i.e., reading a
44 * frame). */
45#define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
46
47#define TX_TIMEOUT (4 * HZ)
48
49/* Max TX retries in case of collision as suggested by errata datasheet */
50#define MAX_TX_RETRYCOUNT 16
51
52enum {
53 RXFILTER_NORMAL,
54 RXFILTER_MULTI,
55 RXFILTER_PROMISC
56};
57
58/* Driver local data */
59struct enc28j60_net {
60 struct net_device *netdev;
61 struct spi_device *spi;
62 struct mutex lock;
63 struct sk_buff *tx_skb;
64 struct work_struct tx_work;
65 struct work_struct irq_work;
66 struct work_struct setrx_work;
67 struct work_struct restart_work;
68 u8 bank; /* current register bank selected */
69 u16 next_pk_ptr; /* next packet pointer within FIFO */
70 u16 max_pk_counter; /* statistics: max packet counter */
71 u16 tx_retry_count;
72 bool hw_enable;
73 bool full_duplex;
74 int rxfilter;
75 u32 msg_enable;
76 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
77};
78
79/* use ethtool to change the level for any given device */
80static struct {
81 u32 msg_enable;
82} debug = { -1 };
83
84/*
85 * SPI read buffer
86 * wait for the SPI transfer and copy received data to destination
87 */
88static int
89spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
90{
91 u8 *rx_buf = priv->spi_transfer_buf + 4;
92 u8 *tx_buf = priv->spi_transfer_buf;
93 struct spi_transfer t = {
94 .tx_buf = tx_buf,
95 .rx_buf = rx_buf,
96 .len = SPI_OPLEN + len,
97 };
98 struct spi_message msg;
99 int ret;
100
101 tx_buf[0] = ENC28J60_READ_BUF_MEM;
102 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */
103
104 spi_message_init(&msg);
105 spi_message_add_tail(&t, &msg);
106 ret = spi_sync(priv->spi, &msg);
107 if (ret == 0) {
108 memcpy(data, &rx_buf[SPI_OPLEN], len);
109 ret = msg.status;
110 }
111 if (ret && netif_msg_drv(priv))
112 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
b39d66a8 113 __func__, ret);
3ec9c11d
CL		 114
115 return ret;
116}
117
118/*
119 * SPI write buffer
120 */
121static int spi_write_buf(struct enc28j60_net *priv, int len,
122 const u8 *data)
123{
124 int ret;
125
126 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
127 ret = -EINVAL;
128 else {
129 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
130 memcpy(&priv->spi_transfer_buf[1], data, len);
131 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
132 if (ret && netif_msg_drv(priv))
133 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
b39d66a8 134 __func__, ret);
3ec9c11d
CL		 135 }
136 return ret;
137}
138
139/*
140 * basic SPI read operation
141 */
142static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
143 u8 addr)
144{
145 u8 tx_buf[2];
146 u8 rx_buf[4];
147 u8 val = 0;
148 int ret;
149 int slen = SPI_OPLEN;
150
151 /* do dummy read if needed */
152 if (addr & SPRD_MASK)
153 slen++;
154
155 tx_buf[0] = op | (addr & ADDR_MASK);
156 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
157 if (ret)
158 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
b39d66a8 159 __func__, ret);
3ec9c11d
CL		 160 else
161 val = rx_buf[slen - 1];
162
163 return val;
164}
165
166/*
167 * basic SPI write operation
168 */
169static int spi_write_op(struct enc28j60_net *priv, u8 op,
170 u8 addr, u8 val)
171{
172 int ret;
173
174 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
175 priv->spi_transfer_buf[1] = val;
176 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
177 if (ret && netif_msg_drv(priv))
178 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
b39d66a8 179 __func__, ret);
3ec9c11d
CL		 180 return ret;
181}
182
183static void enc28j60_soft_reset(struct enc28j60_net *priv)
184{
185 if (netif_msg_hw(priv))
b39d66a8 186 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 187
188 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
189 /* Errata workaround #1, CLKRDY check is unreliable,
190 * delay at least 1 mS instead */
191 udelay(2000);
192}
193
194/*
195 * select the current register bank if necessary
196 */
197static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
198{
199 if ((addr & BANK_MASK) != priv->bank) {
200 u8 b = (addr & BANK_MASK) >> 5;
201
202 if (b != (ECON1_BSEL1 | ECON1_BSEL0))
203 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
204 ECON1_BSEL1 | ECON1_BSEL0);
205 if (b != 0)
206 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, b);
207 priv->bank = (addr & BANK_MASK);
208 }
209}
210
211/*
212 * Register access routines through the SPI bus.
213 * Every register access comes in two flavours:
214 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
215 * atomically more than one register
216 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
217 *
218 * Some registers can be accessed through the bit field clear and
219 * bit field set to avoid a read modify write cycle.
220 */
221
222/*
223 * Register bit field Set
224 */
225static void nolock_reg_bfset(struct enc28j60_net *priv,
226 u8 addr, u8 mask)
227{
228 enc28j60_set_bank(priv, addr);
229 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
230}
231
232static void locked_reg_bfset(struct enc28j60_net *priv,
233 u8 addr, u8 mask)
234{
235 mutex_lock(&priv->lock);
236 nolock_reg_bfset(priv, addr, mask);
237 mutex_unlock(&priv->lock);
238}
239
240/*
241 * Register bit field Clear
242 */
243static void nolock_reg_bfclr(struct enc28j60_net *priv,
244 u8 addr, u8 mask)
245{
246 enc28j60_set_bank(priv, addr);
247 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
248}
249
250static void locked_reg_bfclr(struct enc28j60_net *priv,
251 u8 addr, u8 mask)
252{
253 mutex_lock(&priv->lock);
254 nolock_reg_bfclr(priv, addr, mask);
255 mutex_unlock(&priv->lock);
256}
257
258/*
259 * Register byte read
260 */
261static int nolock_regb_read(struct enc28j60_net *priv,
262 u8 address)
263{
264 enc28j60_set_bank(priv, address);
265 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
266}
267
268static int locked_regb_read(struct enc28j60_net *priv,
269 u8 address)
270{
271 int ret;
272
273 mutex_lock(&priv->lock);
274 ret = nolock_regb_read(priv, address);
275 mutex_unlock(&priv->lock);
276
277 return ret;
278}
279
280/*
281 * Register word read
282 */
283static int nolock_regw_read(struct enc28j60_net *priv,
284 u8 address)
285{
286 int rl, rh;
287
288 enc28j60_set_bank(priv, address);
289 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
290 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
291
292 return (rh << 8) | rl;
293}
294
295static int locked_regw_read(struct enc28j60_net *priv,
296 u8 address)
297{
298 int ret;
299
300 mutex_lock(&priv->lock);
301 ret = nolock_regw_read(priv, address);
302 mutex_unlock(&priv->lock);
303
304 return ret;
305}
306
307/*
308 * Register byte write
309 */
310static void nolock_regb_write(struct enc28j60_net *priv,
311 u8 address, u8 data)
312{
313 enc28j60_set_bank(priv, address);
314 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
315}
316
317static void locked_regb_write(struct enc28j60_net *priv,
318 u8 address, u8 data)
319{
320 mutex_lock(&priv->lock);
321 nolock_regb_write(priv, address, data);
322 mutex_unlock(&priv->lock);
323}
324
325/*
326 * Register word write
327 */
328static void nolock_regw_write(struct enc28j60_net *priv,
329 u8 address, u16 data)
330{
331 enc28j60_set_bank(priv, address);
332 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
333 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
334 (u8) (data >> 8));
335}
336
337static void locked_regw_write(struct enc28j60_net *priv,
338 u8 address, u16 data)
339{
340 mutex_lock(&priv->lock);
341 nolock_regw_write(priv, address, data);
342 mutex_unlock(&priv->lock);
343}
344
345/*
346 * Buffer memory read
347 * Select the starting address and execute a SPI buffer read
348 */
349static void enc28j60_mem_read(struct enc28j60_net *priv,
350 u16 addr, int len, u8 *data)
351{
352 mutex_lock(&priv->lock);
353 nolock_regw_write(priv, ERDPTL, addr);
354#ifdef CONFIG_ENC28J60_WRITEVERIFY
355 if (netif_msg_drv(priv)) {
356 u16 reg;
357 reg = nolock_regw_read(priv, ERDPTL);
358 if (reg != addr)
359 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
b39d66a8 360 "(0x%04x - 0x%04x)\n", __func__, reg, addr);
3ec9c11d
CL		 361 }
362#endif
363 spi_read_buf(priv, len, data);
364 mutex_unlock(&priv->lock);
365}
366
367/*
368 * Write packet to enc28j60 TX buffer memory
369 */
370static void
371enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
372{
373 mutex_lock(&priv->lock);
374 /* Set the write pointer to start of transmit buffer area */
375 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
376#ifdef CONFIG_ENC28J60_WRITEVERIFY
377 if (netif_msg_drv(priv)) {
378 u16 reg;
379 reg = nolock_regw_read(priv, EWRPTL);
380 if (reg != TXSTART_INIT)
381 printk(KERN_DEBUG DRV_NAME
382 ": %s() ERWPT:0x%04x != 0x%04x\n",
b39d66a8 383 __func__, reg, TXSTART_INIT);
3ec9c11d
CL		 384 }
385#endif
386 /* Set the TXND pointer to correspond to the packet size given */
387 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
388 /* write per-packet control byte */
389 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
390 if (netif_msg_hw(priv))
391 printk(KERN_DEBUG DRV_NAME
392 ": %s() after control byte ERWPT:0x%04x\n",
b39d66a8 393 __func__, nolock_regw_read(priv, EWRPTL));
3ec9c11d
CL		 394 /* copy the packet into the transmit buffer */
395 spi_write_buf(priv, len, data);
396 if (netif_msg_hw(priv))
397 printk(KERN_DEBUG DRV_NAME
398 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
b39d66a8 399 __func__, nolock_regw_read(priv, EWRPTL), len);
3ec9c11d
CL		 400 mutex_unlock(&priv->lock);
401}
402
7dac6f8d
DB		 403static unsigned long msec20_to_jiffies;
404
405static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
3ec9c11d 406{
7dac6f8d 407 unsigned long timeout = jiffies + msec20_to_jiffies;
3ec9c11d
CL		 408
409 /* 20 msec timeout read */
7dac6f8d 410 while ((nolock_regb_read(priv, reg) & mask) != val) {
3ec9c11d
CL		 411 if (time_after(jiffies, timeout)) {
412 if (netif_msg_drv(priv))
7dac6f8d
DB		 413 dev_dbg(&priv->spi->dev,
414 "reg %02x ready timeout!\n", reg);
415 return -ETIMEDOUT;
3ec9c11d
CL		 416 }
417 cpu_relax();
418 }
7dac6f8d
DB		 419 return 0;
420}
421
422/*
423 * Wait until the PHY operation is complete.
424 */
425static int wait_phy_ready(struct enc28j60_net *priv)
426{
427 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
3ec9c11d
CL		 428}
429
430/*
431 * PHY register read
432 * PHY registers are not accessed directly, but through the MII
433 */
434static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
435{
436 u16 ret;
437
438 mutex_lock(&priv->lock);
439 /* set the PHY register address */
440 nolock_regb_write(priv, MIREGADR, address);
441 /* start the register read operation */
442 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
443 /* wait until the PHY read completes */
444 wait_phy_ready(priv);
445 /* quit reading */
446 nolock_regb_write(priv, MICMD, 0x00);
447 /* return the data */
448 ret = nolock_regw_read(priv, MIRDL);
449 mutex_unlock(&priv->lock);
450
451 return ret;
452}
453
454static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
455{
456 int ret;
457
458 mutex_lock(&priv->lock);
459 /* set the PHY register address */
460 nolock_regb_write(priv, MIREGADR, address);
461 /* write the PHY data */
462 nolock_regw_write(priv, MIWRL, data);
463 /* wait until the PHY write completes and return */
464 ret = wait_phy_ready(priv);
465 mutex_unlock(&priv->lock);
466
467 return ret;
468}
469
470/*
471 * Program the hardware MAC address from dev->dev_addr.
472 */
473static int enc28j60_set_hw_macaddr(struct net_device *ndev)
474{
475 int ret;
476 struct enc28j60_net *priv = netdev_priv(ndev);
477
478 mutex_lock(&priv->lock);
479 if (!priv->hw_enable) {
e174961c 480 if (netif_msg_drv(priv))
3ec9c11d 481 printk(KERN_INFO DRV_NAME
e174961c
JB		 482 ": %s: Setting MAC address to %pM\n",
483 ndev->name, ndev->dev_addr);
3ec9c11d
CL		 484 /* NOTE: MAC address in ENC28J60 is byte-backward */
485 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
486 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
487 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
488 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
489 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
490 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
491 ret = 0;
492 } else {
493 if (netif_msg_drv(priv))
494 printk(KERN_DEBUG DRV_NAME
495 ": %s() Hardware must be disabled to set "
b39d66a8 496 "Mac address\n", __func__);
3ec9c11d
CL		 497 ret = -EBUSY;
498 }
499 mutex_unlock(&priv->lock);
500 return ret;
501}
502
503/*
504 * Store the new hardware address in dev->dev_addr, and update the MAC.
505 */
506static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
507{
508 struct sockaddr *address = addr;
509
510 if (netif_running(dev))
511 return -EBUSY;
512 if (!is_valid_ether_addr(address->sa_data))
513 return -EADDRNOTAVAIL;
514
515 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
516 return enc28j60_set_hw_macaddr(dev);
517}
518
519/*
520 * Debug routine to dump useful register contents
521 */
522static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
523{
524 mutex_lock(&priv->lock);
525 printk(KERN_DEBUG DRV_NAME " %s\n"
526 "HwRevID: 0x%02x\n"
527 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
528 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
529 "MAC : MACON1 MACON3 MACON4\n"
530 " 0x%02x 0x%02x 0x%02x\n"
531 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
532 " 0x%04x 0x%04x 0x%04x 0x%04x "
533 "0x%02x 0x%02x 0x%04x\n"
534 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
535 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
536 msg, nolock_regb_read(priv, EREVID),
537 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
538 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
539 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
540 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
541 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
542 nolock_regw_read(priv, ERXWRPTL),
543 nolock_regw_read(priv, ERXRDPTL),
544 nolock_regb_read(priv, ERXFCON),
545 nolock_regb_read(priv, EPKTCNT),
546 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
547 nolock_regw_read(priv, ETXNDL),
548 nolock_regb_read(priv, MACLCON1),
549 nolock_regb_read(priv, MACLCON2),
550 nolock_regb_read(priv, MAPHSUP));
551 mutex_unlock(&priv->lock);
552}
553
554/*
555 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
556 */
557static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
558{
559 u16 erxrdpt;
560
561 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
562 erxrdpt = end;
563 else
564 erxrdpt = next_packet_ptr - 1;
565
566 return erxrdpt;
567}
568
569static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
570{
571 u16 erxrdpt;
572
573 if (start > 0x1FFF || end > 0x1FFF || start > end) {
574 if (netif_msg_drv(priv))
575 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
b39d66a8 576 "bad parameters!\n", __func__, start, end);
3ec9c11d
CL		 577 return;
578 }
579 /* set receive buffer start + end */
580 priv->next_pk_ptr = start;
581 nolock_regw_write(priv, ERXSTL, start);
582 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
583 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
584 nolock_regw_write(priv, ERXNDL, end);
585}
586
587static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
588{
589 if (start > 0x1FFF || end > 0x1FFF || start > end) {
590 if (netif_msg_drv(priv))
591 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
b39d66a8 592 "bad parameters!\n", __func__, start, end);
3ec9c11d
CL		 593 return;
594 }
595 /* set transmit buffer start + end */
596 nolock_regw_write(priv, ETXSTL, start);
597 nolock_regw_write(priv, ETXNDL, end);
598}
599
7dac6f8d
DB		 600/*
601 * Low power mode shrinks power consumption about 100x, so we'd like
602 * the chip to be in that mode whenever it's inactive. (However, we
603 * can't stay in lowpower mode during suspend with WOL active.)
604 */
605static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
606{
607 if (netif_msg_drv(priv))
608 dev_dbg(&priv->spi->dev, "%s power...\n",
609 is_low ? "low" : "high");
610
611 mutex_lock(&priv->lock);
612 if (is_low) {
613 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
614 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
615 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
616 /* ECON2_VRPS was set during initialization */
617 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
618 } else {
619 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
620 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
621 /* caller sets ECON1_RXEN */
622 }
623 mutex_unlock(&priv->lock);
624}
625
3ec9c11d
CL		 626static int enc28j60_hw_init(struct enc28j60_net *priv)
627{
628 u8 reg;
629
630 if (netif_msg_drv(priv))
b39d66a8 631 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__,
3ec9c11d
CL		 632 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
633
634 mutex_lock(&priv->lock);
635 /* first reset the chip */
636 enc28j60_soft_reset(priv);
637 /* Clear ECON1 */
638 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
639 priv->bank = 0;
640 priv->hw_enable = false;
641 priv->tx_retry_count = 0;
642 priv->max_pk_counter = 0;
643 priv->rxfilter = RXFILTER_NORMAL;
7dac6f8d
DB		 644 /* enable address auto increment and voltage regulator powersave */
645 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
3ec9c11d
CL		 646
647 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
648 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
649 mutex_unlock(&priv->lock);
650
651 /*
652 * Check the RevID.
653 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
654 * damaged
655 */
656 reg = locked_regb_read(priv, EREVID);
657 if (netif_msg_drv(priv))
658 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
659 if (reg == 0x00 || reg == 0xff) {
660 if (netif_msg_drv(priv))
661 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
b39d66a8 662 __func__, reg);
3ec9c11d
CL		 663 return 0;
664 }
665
666 /* default filter mode: (unicast OR broadcast) AND crc valid */
667 locked_regb_write(priv, ERXFCON,
668 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
669
670 /* enable MAC receive */
671 locked_regb_write(priv, MACON1,
672 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
673 /* enable automatic padding and CRC operations */
674 if (priv->full_duplex) {
675 locked_regb_write(priv, MACON3,
676 MACON3_PADCFG0 | MACON3_TXCRCEN |
677 MACON3_FRMLNEN | MACON3_FULDPX);
678 /* set inter-frame gap (non-back-to-back) */
679 locked_regb_write(priv, MAIPGL, 0x12);
680 /* set inter-frame gap (back-to-back) */
681 locked_regb_write(priv, MABBIPG, 0x15);
682 } else {
683 locked_regb_write(priv, MACON3,
684 MACON3_PADCFG0 | MACON3_TXCRCEN |
685 MACON3_FRMLNEN);
686 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
687 /* set inter-frame gap (non-back-to-back) */
688 locked_regw_write(priv, MAIPGL, 0x0C12);
689 /* set inter-frame gap (back-to-back) */
690 locked_regb_write(priv, MABBIPG, 0x12);
691 }
692 /*
693 * MACLCON1 (default)
694 * MACLCON2 (default)
695 * Set the maximum packet size which the controller will accept
696 */
697 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
698
699 /* Configure LEDs */
700 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
701 return 0;
702
703 if (priv->full_duplex) {
704 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
705 return 0;
706 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
707 return 0;
708 } else {
709 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
710 return 0;
711 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
712 return 0;
713 }
714 if (netif_msg_hw(priv))
715 enc28j60_dump_regs(priv, "Hw initialized.");
716
717 return 1;
718}
719
720static void enc28j60_hw_enable(struct enc28j60_net *priv)
721{
7dac6f8d 722 /* enable interrupts */
3ec9c11d
CL		 723 if (netif_msg_hw(priv))
724 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
b39d66a8 725 __func__);
3ec9c11d
CL		 726
727 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
728
729 mutex_lock(&priv->lock);
730 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
731 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
732 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
733 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
734
735 /* enable receive logic */
736 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
737 priv->hw_enable = true;
738 mutex_unlock(&priv->lock);
739}
740
741static void enc28j60_hw_disable(struct enc28j60_net *priv)
742{
743 mutex_lock(&priv->lock);
744 /* disable interrutps and packet reception */
745 nolock_regb_write(priv, EIE, 0x00);
746 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
747 priv->hw_enable = false;
748 mutex_unlock(&priv->lock);
749}
750
751static int
752enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
753{
754 struct enc28j60_net *priv = netdev_priv(ndev);
755 int ret = 0;
756
757 if (!priv->hw_enable) {
7dac6f8d
DB		 758 /* link is in low power mode now; duplex setting
759 * will take effect on next enc28j60_hw_init().
760 */
761 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
3ec9c11d 762 priv->full_duplex = (duplex == DUPLEX_FULL);
7dac6f8d 763 else {
3ec9c11d
CL		 764 if (netif_msg_link(priv))
765 dev_warn(&ndev->dev,
766 "unsupported link setting\n");
767 ret = -EOPNOTSUPP;
768 }
769 } else {
770 if (netif_msg_link(priv))
771 dev_warn(&ndev->dev, "Warning: hw must be disabled "
772 "to set link mode\n");
773 ret = -EBUSY;
774 }
775 return ret;
776}
777
778/*
779 * Read the Transmit Status Vector
780 */
781static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
782{
783 int endptr;
784
785 endptr = locked_regw_read(priv, ETXNDL);
786 if (netif_msg_hw(priv))
787 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
788 endptr + 1);
789 enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv);
790}
791
792static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
793 u8 tsv[TSV_SIZE])
794{
795 u16 tmp1, tmp2;
796
797 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
798 tmp1 = tsv[1];
799 tmp1 <<= 8;
800 tmp1 |= tsv[0];
801
802 tmp2 = tsv[5];
803 tmp2 <<= 8;
804 tmp2 |= tsv[4];
805
806 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
807 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
808 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
809 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
810 TSV_GETBIT(tsv, TSV_TXCRCERROR),
811 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
812 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
813 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
814 "PacketDefer: %d, ExDefer: %d\n",
815 TSV_GETBIT(tsv, TSV_TXMULTICAST),
816 TSV_GETBIT(tsv, TSV_TXBROADCAST),
817 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
818 TSV_GETBIT(tsv, TSV_TXEXDEFER));
819 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
820 "Giant: %d, Underrun: %d\n",
821 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
822 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
823 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
824 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
825 "BackPressApp: %d, VLanTagFrame: %d\n",
826 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
827 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
828 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
829 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
830}
831
832/*
833 * Receive Status vector
834 */
835static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
836 u16 pk_ptr, int len, u16 sts)
837{
838 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
839 msg, pk_ptr);
840 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
841 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
842 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
843 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
844 RSV_GETBIT(sts, RSV_CRCERROR),
845 RSV_GETBIT(sts, RSV_LENCHECKERR),
846 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
847 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
848 "LongDropEvent: %d, CarrierEvent: %d\n",
849 RSV_GETBIT(sts, RSV_RXMULTICAST),
850 RSV_GETBIT(sts, RSV_RXBROADCAST),
851 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
852 RSV_GETBIT(sts, RSV_CARRIEREV));
853 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
854 " UnknownOp: %d, VLanTagFrame: %d\n",
855 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
856 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
857 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
858 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
859}
860
861static void dump_packet(const char *msg, int len, const char *data)
862{
863 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
864 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
865 data, len, true);
866}
867
868/*
869 * Hardware receive function.
870 * Read the buffer memory, update the FIFO pointer to free the buffer,
871 * check the status vector and decrement the packet counter.
872 */
873static void enc28j60_hw_rx(struct net_device *ndev)
874{
875 struct enc28j60_net *priv = netdev_priv(ndev);
876 struct sk_buff *skb = NULL;
877 u16 erxrdpt, next_packet, rxstat;
878 u8 rsv[RSV_SIZE];
879 int len;
880
881 if (netif_msg_rx_status(priv))
882 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
883 priv->next_pk_ptr);
884
885 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
886 if (netif_msg_rx_err(priv))
887 dev_err(&ndev->dev,
888 "%s() Invalid packet address!! 0x%04x\n",
b39d66a8 889 __func__, priv->next_pk_ptr);
3ec9c11d
CL		 890 /* packet address corrupted: reset RX logic */
891 mutex_lock(&priv->lock);
892 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
893 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
894 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
895 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
896 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
897 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
898 mutex_unlock(&priv->lock);
899 ndev->stats.rx_errors++;
900 return;
901 }
902 /* Read next packet pointer and rx status vector */
903 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
904
905 next_packet = rsv[1];
906 next_packet <<= 8;
907 next_packet |= rsv[0];
908
909 len = rsv[3];
910 len <<= 8;
911 len |= rsv[2];
912
913 rxstat = rsv[5];
914 rxstat <<= 8;
915 rxstat |= rsv[4];
916
917 if (netif_msg_rx_status(priv))
b39d66a8 918 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
3ec9c11d
CL		 919
920 if (!RSV_GETBIT(rxstat, RSV_RXOK)) {
921 if (netif_msg_rx_err(priv))
922 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
923 ndev->stats.rx_errors++;
924 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
925 ndev->stats.rx_crc_errors++;
926 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
927 ndev->stats.rx_frame_errors++;
928 } else {
02ff05c4 929 skb = dev_alloc_skb(len + NET_IP_ALIGN);
3ec9c11d
CL		 930 if (!skb) {
931 if (netif_msg_rx_err(priv))
932 dev_err(&ndev->dev,
933 "out of memory for Rx'd frame\n");
934 ndev->stats.rx_dropped++;
935 } else {
936 skb->dev = ndev;
02ff05c4 937 skb_reserve(skb, NET_IP_ALIGN);
3ec9c11d
CL		 938 /* copy the packet from the receive buffer */
939 enc28j60_mem_read(priv, priv->next_pk_ptr + sizeof(rsv),
940 len, skb_put(skb, len));
941 if (netif_msg_pktdata(priv))
b39d66a8 942 dump_packet(__func__, skb->len, skb->data);
3ec9c11d
CL		 943 skb->protocol = eth_type_trans(skb, ndev);
944 /* update statistics */
945 ndev->stats.rx_packets++;
946 ndev->stats.rx_bytes += len;
947 ndev->last_rx = jiffies;
948 netif_rx(skb);
949 }
950 }
951 /*
952 * Move the RX read pointer to the start of the next
953 * received packet.
954 * This frees the memory we just read out
955 */
956 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
957 if (netif_msg_hw(priv))
958 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
b39d66a8 959 __func__, erxrdpt);
3ec9c11d
CL		 960
961 mutex_lock(&priv->lock);
962 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
963#ifdef CONFIG_ENC28J60_WRITEVERIFY
964 if (netif_msg_drv(priv)) {
965 u16 reg;
966 reg = nolock_regw_read(priv, ERXRDPTL);
967 if (reg != erxrdpt)
968 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
b39d66a8 969 "error (0x%04x - 0x%04x)\n", __func__,
3ec9c11d
CL		 970 reg, erxrdpt);
971 }
972#endif
973 priv->next_pk_ptr = next_packet;
974 /* we are done with this packet, decrement the packet counter */
975 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
976 mutex_unlock(&priv->lock);
977}
978
979/*
980 * Calculate free space in RxFIFO
981 */
982static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
983{
984 int epkcnt, erxst, erxnd, erxwr, erxrd;
985 int free_space;
986
987 mutex_lock(&priv->lock);
988 epkcnt = nolock_regb_read(priv, EPKTCNT);
989 if (epkcnt >= 255)
990 free_space = -1;
991 else {
992 erxst = nolock_regw_read(priv, ERXSTL);
993 erxnd = nolock_regw_read(priv, ERXNDL);
994 erxwr = nolock_regw_read(priv, ERXWRPTL);
995 erxrd = nolock_regw_read(priv, ERXRDPTL);
996
997 if (erxwr > erxrd)
998 free_space = (erxnd - erxst) - (erxwr - erxrd);
999 else if (erxwr == erxrd)
1000 free_space = (erxnd - erxst);
1001 else
1002 free_space = erxrd - erxwr - 1;
1003 }
1004 mutex_unlock(&priv->lock);
1005 if (netif_msg_rx_status(priv))
1006 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
b39d66a8 1007 __func__, free_space);
3ec9c11d
CL		 1008 return free_space;
1009}
1010
1011/*
1012 * Access the PHY to determine link status
1013 */
1014static void enc28j60_check_link_status(struct net_device *ndev)
1015{
1016 struct enc28j60_net *priv = netdev_priv(ndev);
1017 u16 reg;
1018 int duplex;
1019
1020 reg = enc28j60_phy_read(priv, PHSTAT2);
1021 if (netif_msg_hw(priv))
1022 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
b39d66a8 1023 "PHSTAT2: %04x\n", __func__,
3ec9c11d
CL		 1024 enc28j60_phy_read(priv, PHSTAT1), reg);
1025 duplex = reg & PHSTAT2_DPXSTAT;
1026
1027 if (reg & PHSTAT2_LSTAT) {
1028 netif_carrier_on(ndev);
1029 if (netif_msg_ifup(priv))
1030 dev_info(&ndev->dev, "link up - %s\n",
1031 duplex ? "Full duplex" : "Half duplex");
1032 } else {
1033 if (netif_msg_ifdown(priv))
1034 dev_info(&ndev->dev, "link down\n");
1035 netif_carrier_off(ndev);
1036 }
1037}
1038
1039static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1040{
1041 struct enc28j60_net *priv = netdev_priv(ndev);
1042
1043 if (err)
1044 ndev->stats.tx_errors++;
1045 else
1046 ndev->stats.tx_packets++;
1047
1048 if (priv->tx_skb) {
1049 if (!err)
1050 ndev->stats.tx_bytes += priv->tx_skb->len;
1051 dev_kfree_skb(priv->tx_skb);
1052 priv->tx_skb = NULL;
1053 }
1054 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1055 netif_wake_queue(ndev);
1056}
1057
1058/*
1059 * RX handler
1060 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1061 * check EPKTCNT is the suggested workaround.
1062 * We don't need to clear interrupt flag, automatically done when
1063 * enc28j60_hw_rx() decrements the packet counter.
1064 * Returns how many packet processed.
1065 */
1066static int enc28j60_rx_interrupt(struct net_device *ndev)
1067{
1068 struct enc28j60_net *priv = netdev_priv(ndev);
1069 int pk_counter, ret;
1070
1071 pk_counter = locked_regb_read(priv, EPKTCNT);
1072 if (pk_counter && netif_msg_intr(priv))
1073 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1074 if (pk_counter > priv->max_pk_counter) {
1075 /* update statistics */
1076 priv->max_pk_counter = pk_counter;
1077 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1078 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1079 priv->max_pk_counter);
1080 }
1081 ret = pk_counter;
1082 while (pk_counter-- > 0)
1083 enc28j60_hw_rx(ndev);
1084
1085 return ret;
1086}
1087
1088static void enc28j60_irq_work_handler(struct work_struct *work)
1089{
1090 struct enc28j60_net *priv =
1091 container_of(work, struct enc28j60_net, irq_work);
1092 struct net_device *ndev = priv->netdev;
1093 int intflags, loop;
1094
1095 if (netif_msg_intr(priv))
b39d66a8 1096 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 1097 /* disable further interrupts */
1098 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1099
1100 do {
1101 loop = 0;
1102 intflags = locked_regb_read(priv, EIR);
1103 /* DMA interrupt handler (not currently used) */
1104 if ((intflags & EIR_DMAIF) != 0) {
1105 loop++;
1106 if (netif_msg_intr(priv))
1107 printk(KERN_DEBUG DRV_NAME
1108 ": intDMA(%d)\n", loop);
1109 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1110 }
1111 /* LINK changed handler */
1112 if ((intflags & EIR_LINKIF) != 0) {
1113 loop++;
1114 if (netif_msg_intr(priv))
1115 printk(KERN_DEBUG DRV_NAME
1116 ": intLINK(%d)\n", loop);
1117 enc28j60_check_link_status(ndev);
1118 /* read PHIR to clear the flag */
1119 enc28j60_phy_read(priv, PHIR);
1120 }
1121 /* TX complete handler */
1122 if ((intflags & EIR_TXIF) != 0) {
1123 bool err = false;
1124 loop++;
1125 if (netif_msg_intr(priv))
1126 printk(KERN_DEBUG DRV_NAME
1127 ": intTX(%d)\n", loop);
1128 priv->tx_retry_count = 0;
1129 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1130 if (netif_msg_tx_err(priv))
1131 dev_err(&ndev->dev,
1132 "Tx Error (aborted)\n");
1133 err = true;
1134 }
1135 if (netif_msg_tx_done(priv)) {
1136 u8 tsv[TSV_SIZE];
1137 enc28j60_read_tsv(priv, tsv);
1138 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1139 }
1140 enc28j60_tx_clear(ndev, err);
1141 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1142 }
1143 /* TX Error handler */
1144 if ((intflags & EIR_TXERIF) != 0) {
1145 u8 tsv[TSV_SIZE];
1146
1147 loop++;
1148 if (netif_msg_intr(priv))
1149 printk(KERN_DEBUG DRV_NAME
1150 ": intTXErr(%d)\n", loop);
1151 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1152 enc28j60_read_tsv(priv, tsv);
1153 if (netif_msg_tx_err(priv))
1154 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1155 /* Reset TX logic */
1156 mutex_lock(&priv->lock);
1157 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1158 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1159 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1160 mutex_unlock(&priv->lock);
1161 /* Transmit Late collision check for retransmit */
1162 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1163 if (netif_msg_tx_err(priv))
1164 printk(KERN_DEBUG DRV_NAME
1165 ": LateCollision TXErr (%d)\n",
1166 priv->tx_retry_count);
1167 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1168 locked_reg_bfset(priv, ECON1,
1169 ECON1_TXRTS);
1170 else
1171 enc28j60_tx_clear(ndev, true);
1172 } else
1173 enc28j60_tx_clear(ndev, true);
1174 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1175 }
1176 /* RX Error handler */
1177 if ((intflags & EIR_RXERIF) != 0) {
1178 loop++;
1179 if (netif_msg_intr(priv))
1180 printk(KERN_DEBUG DRV_NAME
1181 ": intRXErr(%d)\n", loop);
1182 /* Check free FIFO space to flag RX overrun */
1183 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1184 if (netif_msg_rx_err(priv))
1185 printk(KERN_DEBUG DRV_NAME
1186 ": RX Overrun\n");
1187 ndev->stats.rx_dropped++;
1188 }
1189 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1190 }
1191 /* RX handler */
1192 if (enc28j60_rx_interrupt(ndev))
1193 loop++;
1194 } while (loop);
1195
1196 /* re-enable interrupts */
1197 locked_reg_bfset(priv, EIE, EIE_INTIE);
1198 if (netif_msg_intr(priv))
b39d66a8 1199 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__);
3ec9c11d
CL		 1200}
1201
1202/*
1203 * Hardware transmit function.
1204 * Fill the buffer memory and send the contents of the transmit buffer
1205 * onto the network
1206 */
1207static void enc28j60_hw_tx(struct enc28j60_net *priv)
1208{
1209 if (netif_msg_tx_queued(priv))
1210 printk(KERN_DEBUG DRV_NAME
1211 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1212
1213 if (netif_msg_pktdata(priv))
b39d66a8 1214 dump_packet(__func__,
3ec9c11d
CL		 1215 priv->tx_skb->len, priv->tx_skb->data);
1216 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1217
1218#ifdef CONFIG_ENC28J60_WRITEVERIFY
1219 /* readback and verify written data */
1220 if (netif_msg_drv(priv)) {
1221 int test_len, k;
1222 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1223 int okflag;
1224
1225 test_len = priv->tx_skb->len;
1226 if (test_len > sizeof(test_buf))
1227 test_len = sizeof(test_buf);
1228
1229 /* + 1 to skip control byte */
1230 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1231 okflag = 1;
1232 for (k = 0; k < test_len; k++) {
1233 if (priv->tx_skb->data[k] != test_buf[k]) {
1234 printk(KERN_DEBUG DRV_NAME
1235 ": Error, %d location differ: "
1236 "0x%02x-0x%02x\n", k,
1237 priv->tx_skb->data[k], test_buf[k]);
1238 okflag = 0;
1239 }
1240 }
1241 if (!okflag)
1242 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1243 "verify ERROR!\n");
1244 }
1245#endif
1246 /* set TX request flag */
1247 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1248}
1249
1250static int enc28j60_send_packet(struct sk_buff *skb, struct net_device *dev)
1251{
1252 struct enc28j60_net *priv = netdev_priv(dev);
1253
1254 if (netif_msg_tx_queued(priv))
b39d66a8 1255 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 1256
1257 /* If some error occurs while trying to transmit this
1258 * packet, you should return '1' from this function.
1259 * In such a case you _may not_ do anything to the
1260 * SKB, it is still owned by the network queueing
1261 * layer when an error is returned. This means you
1262 * may not modify any SKB fields, you may not free
1263 * the SKB, etc.
1264 */
1265 netif_stop_queue(dev);
1266
1267 /* save the timestamp */
1268 priv->netdev->trans_start = jiffies;
1269 /* Remember the skb for deferred processing */
1270 priv->tx_skb = skb;
1271 schedule_work(&priv->tx_work);
1272
1273 return 0;
1274}
1275
1276static void enc28j60_tx_work_handler(struct work_struct *work)
1277{
1278 struct enc28j60_net *priv =
1279 container_of(work, struct enc28j60_net, tx_work);
1280
1281 /* actual delivery of data */
1282 enc28j60_hw_tx(priv);
1283}
1284
1285static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1286{
1287 struct enc28j60_net *priv = dev_id;
1288
1289 /*
1290 * Can't do anything in interrupt context because we need to
1291 * block (spi_sync() is blocking) so fire of the interrupt
1292 * handling workqueue.
1293 * Remember that we access enc28j60 registers through SPI bus
1294 * via spi_sync() call.
1295 */
1296 schedule_work(&priv->irq_work);
1297
1298 return IRQ_HANDLED;
1299}
1300
1301static void enc28j60_tx_timeout(struct net_device *ndev)
1302{
1303 struct enc28j60_net *priv = netdev_priv(ndev);
1304
1305 if (netif_msg_timer(priv))
1306 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1307
1308 ndev->stats.tx_errors++;
1309 /* can't restart safely under softirq */
1310 schedule_work(&priv->restart_work);
1311}
1312
1313/*
1314 * Open/initialize the board. This is called (in the current kernel)
1315 * sometime after booting when the 'ifconfig' program is run.
1316 *
1317 * This routine should set everything up anew at each open, even
1318 * registers that "should" only need to be set once at boot, so that
1319 * there is non-reboot way to recover if something goes wrong.
1320 */
1321static int enc28j60_net_open(struct net_device *dev)
1322{
1323 struct enc28j60_net *priv = netdev_priv(dev);
1324
1325 if (netif_msg_drv(priv))
b39d66a8 1326 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 1327
1328 if (!is_valid_ether_addr(dev->dev_addr)) {
e174961c
JB		 1329 if (netif_msg_ifup(priv))
1330 dev_err(&dev->dev, "invalid MAC address %pM\n",
1331 dev->dev_addr);
3ec9c11d
CL		 1332 return -EADDRNOTAVAIL;
1333 }
7dac6f8d
DB		 1334 /* Reset the hardware here (and take it out of low power mode) */
1335 enc28j60_lowpower(priv, false);
3ec9c11d
CL		 1336 enc28j60_hw_disable(priv);
1337 if (!enc28j60_hw_init(priv)) {
1338 if (netif_msg_ifup(priv))
1339 dev_err(&dev->dev, "hw_reset() failed\n");
1340 return -EINVAL;
1341 }
1342 /* Update the MAC address (in case user has changed it) */
1343 enc28j60_set_hw_macaddr(dev);
1344 /* Enable interrupts */
1345 enc28j60_hw_enable(priv);
1346 /* check link status */
1347 enc28j60_check_link_status(dev);
1348 /* We are now ready to accept transmit requests from
1349 * the queueing layer of the networking.
1350 */
1351 netif_start_queue(dev);
1352
1353 return 0;
1354}
1355
1356/* The inverse routine to net_open(). */
1357static int enc28j60_net_close(struct net_device *dev)
1358{
1359 struct enc28j60_net *priv = netdev_priv(dev);
1360
1361 if (netif_msg_drv(priv))
b39d66a8 1362 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 1363
1364 enc28j60_hw_disable(priv);
7dac6f8d 1365 enc28j60_lowpower(priv, true);
3ec9c11d
CL		 1366 netif_stop_queue(dev);
1367
1368 return 0;
1369}
1370
1371/*
1372 * Set or clear the multicast filter for this adapter
1373 * num_addrs == -1 Promiscuous mode, receive all packets
1374 * num_addrs == 0 Normal mode, filter out multicast packets
1375 * num_addrs > 0 Multicast mode, receive normal and MC packets
1376 */
1377static void enc28j60_set_multicast_list(struct net_device *dev)
1378{
1379 struct enc28j60_net *priv = netdev_priv(dev);
1380 int oldfilter = priv->rxfilter;
1381
1382 if (dev->flags & IFF_PROMISC) {
1383 if (netif_msg_link(priv))
1384 dev_info(&dev->dev, "promiscuous mode\n");
1385 priv->rxfilter = RXFILTER_PROMISC;
1386 } else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count) {
1387 if (netif_msg_link(priv))
1388 dev_info(&dev->dev, "%smulticast mode\n",
1389 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1390 priv->rxfilter = RXFILTER_MULTI;
1391 } else {
1392 if (netif_msg_link(priv))
1393 dev_info(&dev->dev, "normal mode\n");
1394 priv->rxfilter = RXFILTER_NORMAL;
1395 }
1396
1397 if (oldfilter != priv->rxfilter)
1398 schedule_work(&priv->setrx_work);
1399}
1400
1401static void enc28j60_setrx_work_handler(struct work_struct *work)
1402{
1403 struct enc28j60_net *priv =
1404 container_of(work, struct enc28j60_net, setrx_work);
1405
1406 if (priv->rxfilter == RXFILTER_PROMISC) {
1407 if (netif_msg_drv(priv))
1408 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1409 locked_regb_write(priv, ERXFCON, 0x00);
1410 } else if (priv->rxfilter == RXFILTER_MULTI) {
1411 if (netif_msg_drv(priv))
1412 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1413 locked_regb_write(priv, ERXFCON,
1414 ERXFCON_UCEN | ERXFCON_CRCEN |
1415 ERXFCON_BCEN | ERXFCON_MCEN);
1416 } else {
1417 if (netif_msg_drv(priv))
1418 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1419 locked_regb_write(priv, ERXFCON,
1420 ERXFCON_UCEN | ERXFCON_CRCEN |
1421 ERXFCON_BCEN);
1422 }
1423}
1424
1425static void enc28j60_restart_work_handler(struct work_struct *work)
1426{
1427 struct enc28j60_net *priv =
1428 container_of(work, struct enc28j60_net, restart_work);
1429 struct net_device *ndev = priv->netdev;
1430 int ret;
1431
1432 rtnl_lock();
1433 if (netif_running(ndev)) {
1434 enc28j60_net_close(ndev);
1435 ret = enc28j60_net_open(ndev);
1436 if (unlikely(ret)) {
1437 dev_info(&ndev->dev, " could not restart %d\n", ret);
1438 dev_close(ndev);
1439 }
1440 }
1441 rtnl_unlock();
1442}
1443
1444/* ......................... ETHTOOL SUPPORT ........................... */
1445
1446static void
1447enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1448{
1449 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1450 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1451 strlcpy(info->bus_info,
1452 dev->dev.parent->bus_id, sizeof(info->bus_info));
1453}
1454
1455static int
1456enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1457{
1458 struct enc28j60_net *priv = netdev_priv(dev);
1459
1460 cmd->transceiver = XCVR_INTERNAL;
1461 cmd->supported = SUPPORTED_10baseT_Half
1462 | SUPPORTED_10baseT_Full
1463 | SUPPORTED_TP;
1464 cmd->speed = SPEED_10;
1465 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1466 cmd->port = PORT_TP;
1467 cmd->autoneg = AUTONEG_DISABLE;
1468
1469 return 0;
1470}
1471
1472static int
1473enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1474{
1475 return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1476}
1477
1478static u32 enc28j60_get_msglevel(struct net_device *dev)
1479{
1480 struct enc28j60_net *priv = netdev_priv(dev);
1481 return priv->msg_enable;
1482}
1483
1484static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1485{
1486 struct enc28j60_net *priv = netdev_priv(dev);
1487 priv->msg_enable = val;
1488}
1489
1490static const struct ethtool_ops enc28j60_ethtool_ops = {
1491 .get_settings = enc28j60_get_settings,
1492 .set_settings = enc28j60_set_settings,
1493 .get_drvinfo = enc28j60_get_drvinfo,
1494 .get_msglevel = enc28j60_get_msglevel,
1495 .set_msglevel = enc28j60_set_msglevel,
1496};
1497
1498static int enc28j60_chipset_init(struct net_device *dev)
1499{
1500 struct enc28j60_net *priv = netdev_priv(dev);
1501
1502 return enc28j60_hw_init(priv);
1503}
1504
1505static int __devinit enc28j60_probe(struct spi_device *spi)
1506{
1507 struct net_device *dev;
1508 struct enc28j60_net *priv;
1509 int ret = 0;
1510
1511 if (netif_msg_drv(&debug))
1512 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1513 DRV_VERSION);
1514
1515 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1516 if (!dev) {
1517 if (netif_msg_drv(&debug))
1518 dev_err(&spi->dev, DRV_NAME
1519 ": unable to alloc new ethernet\n");
1520 ret = -ENOMEM;
1521 goto error_alloc;
1522 }
1523 priv = netdev_priv(dev);
1524
1525 priv->netdev = dev; /* priv to netdev reference */
1526 priv->spi = spi; /* priv to spi reference */
1527 priv->msg_enable = netif_msg_init(debug.msg_enable,
1528 ENC28J60_MSG_DEFAULT);
1529 mutex_init(&priv->lock);
1530 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1531 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1532 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1533 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1534 dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */
1535 SET_NETDEV_DEV(dev, &spi->dev);
1536
1537 if (!enc28j60_chipset_init(dev)) {
1538 if (netif_msg_probe(priv))
1539 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1540 ret = -EIO;
1541 goto error_irq;
1542 }
1543 random_ether_addr(dev->dev_addr);
1544 enc28j60_set_hw_macaddr(dev);
1545
c7b7b042
DB		 1546 /* Board setup must set the relevant edge trigger type;
1547 * level triggers won't currently work.
1548 */
1549 ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
3ec9c11d
CL		 1550 if (ret < 0) {
1551 if (netif_msg_probe(priv))
1552 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1553 "(ret = %d)\n", spi->irq, ret);
1554 goto error_irq;
1555 }
1556
1557 dev->if_port = IF_PORT_10BASET;
1558 dev->irq = spi->irq;
1559 dev->open = enc28j60_net_open;
1560 dev->stop = enc28j60_net_close;
1561 dev->hard_start_xmit = enc28j60_send_packet;
1562 dev->set_multicast_list = &enc28j60_set_multicast_list;
1563 dev->set_mac_address = enc28j60_set_mac_address;
1564 dev->tx_timeout = &enc28j60_tx_timeout;
1565 dev->watchdog_timeo = TX_TIMEOUT;
1566 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1567
7dac6f8d
DB		 1568 enc28j60_lowpower(priv, true);
1569
3ec9c11d
CL		 1570 ret = register_netdev(dev);
1571 if (ret) {
1572 if (netif_msg_probe(priv))
1573 dev_err(&spi->dev, "register netdev " DRV_NAME
1574 " failed (ret = %d)\n", ret);
1575 goto error_register;
1576 }
1577 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1578
1579 return 0;
1580
1581error_register:
1582 free_irq(spi->irq, priv);
1583error_irq:
1584 free_netdev(dev);
1585error_alloc:
1586 return ret;
1587}
1588
6fd65882 1589static int __devexit enc28j60_remove(struct spi_device *spi)
3ec9c11d
CL		 1590{
1591 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1592
1593 if (netif_msg_drv(priv))
1594 printk(KERN_DEBUG DRV_NAME ": remove\n");
1595
1596 unregister_netdev(priv->netdev);
1597 free_irq(spi->irq, priv);
1598 free_netdev(priv->netdev);
1599
1600 return 0;
1601}
1602
1603static struct spi_driver enc28j60_driver = {
1604 .driver = {
1605 .name = DRV_NAME,
3ec9c11d 1606 .owner = THIS_MODULE,
6fd65882 1607 },
3ec9c11d
CL		 1608 .probe = enc28j60_probe,
1609 .remove = __devexit_p(enc28j60_remove),
1610};
1611
1612static int __init enc28j60_init(void)
1613{
7dac6f8d
DB		 1614 msec20_to_jiffies = msecs_to_jiffies(20);
1615
3ec9c11d
CL		 1616 return spi_register_driver(&enc28j60_driver);
1617}
1618
1619module_init(enc28j60_init);
1620
1621static void __exit enc28j60_exit(void)
1622{
1623 spi_unregister_driver(&enc28j60_driver);
1624}
1625
1626module_exit(enc28j60_exit);
1627
1628MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1629MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1630MODULE_LICENSE("GPL");
1631module_param_named(debug, debug.msg_enable, int, 0);
1632MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
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