[net-next-2.6.git] / drivers / net / ehea / ehea.h

/*
 *  linux/drivers/net/ehea/ehea.h
 *
 *  eHEA ethernet device driver for IBM eServer System p
 *
 *  (C) Copyright IBM Corp. 2006
 *
 *  Authors:
 *       Christoph Raisch <raisch@de.ibm.com>
 *       Jan-Bernd Themann <themann@de.ibm.com>
 *       Thomas Klein <tklein@de.ibm.com>
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __EHEA_H__
#define __EHEA_H__

#include <linux/module.h>
#include <linux/ethtool.h>
#include <linux/vmalloc.h>
#include <linux/if_vlan.h>
#include <linux/inet_lro.h>

#include <asm/ibmebus.h>
#include <asm/abs_addr.h>
#include <asm/io.h>

#define DRV_NAME	"ehea"
#define DRV_VERSION	"EHEA_0105"

/* eHEA capability flags */
#define DLPAR_PORT_ADD_REM 1
#define DLPAR_MEM_ADD      2
#define DLPAR_MEM_REM      4
#define EHEA_CAPABILITIES  (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD | DLPAR_MEM_REM)

#define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
	| NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)

#define EHEA_MAX_ENTRIES_RQ1 32767
#define EHEA_MAX_ENTRIES_RQ2 16383
#define EHEA_MAX_ENTRIES_RQ3 16383
#define EHEA_MAX_ENTRIES_SQ  32767
#define EHEA_MIN_ENTRIES_QP  127

#define EHEA_SMALL_QUEUES
#define EHEA_NUM_TX_QP 1
#define EHEA_LRO_MAX_AGGR 64

#ifdef EHEA_SMALL_QUEUES
#define EHEA_MAX_CQE_COUNT      1023
#define EHEA_DEF_ENTRIES_SQ     1023
#define EHEA_DEF_ENTRIES_RQ1    4095
#define EHEA_DEF_ENTRIES_RQ2    1023
#define EHEA_DEF_ENTRIES_RQ3    1023
#else
#define EHEA_MAX_CQE_COUNT      4080
#define EHEA_DEF_ENTRIES_SQ     4080
#define EHEA_DEF_ENTRIES_RQ1    8160
#define EHEA_DEF_ENTRIES_RQ2    2040
#define EHEA_DEF_ENTRIES_RQ3    2040
#endif

#define EHEA_MAX_ENTRIES_EQ 20

#define EHEA_SG_SQ  2
#define EHEA_SG_RQ1 1
#define EHEA_SG_RQ2 0
#define EHEA_SG_RQ3 0

#define EHEA_MAX_PACKET_SIZE    9022	/* for jumbo frames */
#define EHEA_RQ2_PKT_SIZE       1522
#define EHEA_L_PKT_SIZE         256	/* low latency */

#define MAX_LRO_DESCRIPTORS 8

/* Send completion signaling */

/* Protection Domain Identifier */
#define EHEA_PD_ID        0xaabcdeff

#define EHEA_RQ2_THRESHOLD 	   1
#define EHEA_RQ3_THRESHOLD 	   9	/* use RQ3 threshold of 1522 bytes */

#define EHEA_SPEED_10G         10000
#define EHEA_SPEED_1G           1000
#define EHEA_SPEED_100M          100
#define EHEA_SPEED_10M            10
#define EHEA_SPEED_AUTONEG         0

/* Broadcast/Multicast registration types */
#define EHEA_BCMC_SCOPE_ALL	0x08
#define EHEA_BCMC_SCOPE_SINGLE	0x00
#define EHEA_BCMC_MULTICAST	0x04
#define EHEA_BCMC_BROADCAST	0x00
#define EHEA_BCMC_UNTAGGED	0x02
#define EHEA_BCMC_TAGGED	0x00
#define EHEA_BCMC_VLANID_ALL	0x01
#define EHEA_BCMC_VLANID_SINGLE	0x00

#define EHEA_CACHE_LINE          128

/* Memory Regions */
#define EHEA_MR_ACC_CTRL       0x00800000

#define EHEA_BUSMAP_START      0x8000000000000000ULL
#define EHEA_INVAL_ADDR        0xFFFFFFFFFFFFFFFFULL
#define EHEA_DIR_INDEX_SHIFT 13                   /* 8k Entries in 64k block */
#define EHEA_TOP_INDEX_SHIFT (EHEA_DIR_INDEX_SHIFT * 2)
#define EHEA_MAP_ENTRIES (1 << EHEA_DIR_INDEX_SHIFT)
#define EHEA_MAP_SIZE (0x10000)                   /* currently fixed map size */
#define EHEA_INDEX_MASK (EHEA_MAP_ENTRIES - 1)


#define EHEA_WATCH_DOG_TIMEOUT 10*HZ

/* utility functions */

#define ehea_info(fmt, args...) \
	printk(KERN_INFO DRV_NAME ": " fmt "\n", ## args)

#define ehea_error(fmt, args...) \
	printk(KERN_ERR DRV_NAME ": Error in %s: " fmt "\n", __func__, ## args)

#ifdef DEBUG
#define ehea_debug(fmt, args...) \
	printk(KERN_DEBUG DRV_NAME ": " fmt, ## args)
#else
#define ehea_debug(fmt, args...) do {} while (0)
#endif

void ehea_dump(void *adr, int len, char *msg);

#define EHEA_BMASK(pos, length) (((pos) << 16) + (length))

#define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))

#define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)

#define EHEA_BMASK_MASK(mask) \
	(0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))

#define EHEA_BMASK_SET(mask, value) \
	((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))

#define EHEA_BMASK_GET(mask, value) \
	(EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))

/*
 * Generic ehea page
 */
struct ehea_page {
	u8 entries[PAGE_SIZE];
};

/*
 * Generic queue in linux kernel virtual memory
 */
struct hw_queue {
	u64 current_q_offset;		/* current queue entry */
	struct ehea_page **queue_pages;	/* array of pages belonging to queue */
	u32 qe_size;			/* queue entry size */
	u32 queue_length;      		/* queue length allocated in bytes */
	u32 pagesize;
	u32 toggle_state;		/* toggle flag - per page */
	u32 reserved;			/* 64 bit alignment */
};

/*
 * For pSeries this is a 64bit memory address where
 * I/O memory is mapped into CPU address space
 */
struct h_epa {
	void __iomem *addr;
};

struct h_epa_user {
	u64 addr;
};

struct h_epas {
	struct h_epa kernel;	/* kernel space accessible resource,
				   set to 0 if unused */
	struct h_epa_user user;	/* user space accessible resource
				   set to 0 if unused */
};

/*
 * Memory map data structures
 */
struct ehea_dir_bmap
{
	u64 ent[EHEA_MAP_ENTRIES];
};
struct ehea_top_bmap
{
	struct ehea_dir_bmap *dir[EHEA_MAP_ENTRIES];
};
struct ehea_bmap
{
	struct ehea_top_bmap *top[EHEA_MAP_ENTRIES];
};

struct ehea_qp;
struct ehea_cq;
struct ehea_eq;
struct ehea_port;
struct ehea_av;

/*
 * Queue attributes passed to ehea_create_qp()
 */
struct ehea_qp_init_attr {
	/* input parameter */
	u32 qp_token;           /* queue token */
	u8 low_lat_rq1;
	u8 signalingtype;       /* cqe generation flag */
	u8 rq_count;            /* num of receive queues */
	u8 eqe_gen;             /* eqe generation flag */
	u16 max_nr_send_wqes;   /* max number of send wqes */
	u16 max_nr_rwqes_rq1;   /* max number of receive wqes */
	u16 max_nr_rwqes_rq2;
	u16 max_nr_rwqes_rq3;
	u8 wqe_size_enc_sq;
	u8 wqe_size_enc_rq1;
	u8 wqe_size_enc_rq2;
	u8 wqe_size_enc_rq3;
	u8 swqe_imm_data_len;   /* immediate data length for swqes */
	u16 port_nr;
	u16 rq2_threshold;
	u16 rq3_threshold;
	u64 send_cq_handle;
	u64 recv_cq_handle;
	u64 aff_eq_handle;

	/* output parameter */
	u32 qp_nr;
	u16 act_nr_send_wqes;
	u16 act_nr_rwqes_rq1;
	u16 act_nr_rwqes_rq2;
	u16 act_nr_rwqes_rq3;
	u8 act_wqe_size_enc_sq;
	u8 act_wqe_size_enc_rq1;
	u8 act_wqe_size_enc_rq2;
	u8 act_wqe_size_enc_rq3;
	u32 nr_sq_pages;
	u32 nr_rq1_pages;
	u32 nr_rq2_pages;
	u32 nr_rq3_pages;
	u32 liobn_sq;
	u32 liobn_rq1;
	u32 liobn_rq2;
	u32 liobn_rq3;
};

/*
 * Event Queue attributes, passed as parameter
 */
struct ehea_eq_attr {
	u32 type;
	u32 max_nr_of_eqes;
	u8 eqe_gen;        /* generate eqe flag */
	u64 eq_handle;
	u32 act_nr_of_eqes;
	u32 nr_pages;
	u32 ist1;          /* Interrupt service token */
	u32 ist2;
	u32 ist3;
	u32 ist4;
};


/*
 * Event Queue
 */
struct ehea_eq {
	struct ehea_adapter *adapter;
	struct hw_queue hw_queue;
	u64 fw_handle;
	struct h_epas epas;
	spinlock_t spinlock;
	struct ehea_eq_attr attr;
};

/*
 * HEA Queues
 */
struct ehea_qp {
	struct ehea_adapter *adapter;
	u64 fw_handle;			/* QP handle for firmware calls */
	struct hw_queue hw_squeue;
	struct hw_queue hw_rqueue1;
	struct hw_queue hw_rqueue2;
	struct hw_queue hw_rqueue3;
	struct h_epas epas;
	struct ehea_qp_init_attr init_attr;
};

/*
 * Completion Queue attributes
 */
struct ehea_cq_attr {
	/* input parameter */
	u32 max_nr_of_cqes;
	u32 cq_token;
	u64 eq_handle;

	/* output parameter */
	u32 act_nr_of_cqes;
	u32 nr_pages;
};

/*
 * Completion Queue
 */
struct ehea_cq {
	struct ehea_adapter *adapter;
	u64 fw_handle;
	struct hw_queue hw_queue;
	struct h_epas epas;
	struct ehea_cq_attr attr;
};

/*
 * Memory Region
 */
struct ehea_mr {
	struct ehea_adapter *adapter;
	u64 handle;
	u64 vaddr;
	u32 lkey;
};

/*
 * Port state information
 */
struct port_stats {
	int poll_receive_errors;
	int queue_stopped;
	int err_tcp_cksum;
	int err_ip_cksum;
	int err_frame_crc;
};

#define EHEA_IRQ_NAME_SIZE 20

/*
 * Queue SKB Array
 */
struct ehea_q_skb_arr {
	struct sk_buff **arr;		/* skb array for queue */
	int len;                	/* array length */
	int index;			/* array index */
	int os_skbs;			/* rq2/rq3 only: outstanding skbs */
};

/*
 * Port resources
 */
struct ehea_port_res {
	struct napi_struct napi;
	struct port_stats p_stats;
	struct ehea_mr send_mr;       	/* send memory region */
	struct ehea_mr recv_mr;       	/* receive memory region */
	spinlock_t xmit_lock;
	struct ehea_port *port;
	char int_recv_name[EHEA_IRQ_NAME_SIZE];
	char int_send_name[EHEA_IRQ_NAME_SIZE];
	struct ehea_qp *qp;
	struct ehea_cq *send_cq;
	struct ehea_cq *recv_cq;
	struct ehea_eq *eq;
	struct ehea_q_skb_arr rq1_skba;
	struct ehea_q_skb_arr rq2_skba;
	struct ehea_q_skb_arr rq3_skba;
	struct ehea_q_skb_arr sq_skba;
	int sq_skba_size;
	spinlock_t netif_queue;
	int queue_stopped;
	int swqe_refill_th;
	atomic_t swqe_avail;
	int swqe_ll_count;
	u32 swqe_id_counter;
	u64 tx_packets;
	u64 rx_packets;
	u32 poll_counter;
	struct net_lro_mgr lro_mgr;
	struct net_lro_desc lro_desc[MAX_LRO_DESCRIPTORS];
};


#define EHEA_MAX_PORTS 16

#define EHEA_NUM_PORTRES_FW_HANDLES    6  /* QP handle, SendCQ handle,
					     RecvCQ handle, EQ handle,
					     SendMR handle, RecvMR handle */
#define EHEA_NUM_PORT_FW_HANDLES       1  /* EQ handle */
#define EHEA_NUM_ADAPTER_FW_HANDLES    2  /* MR handle, NEQ handle */

struct ehea_adapter {
	u64 handle;
	struct of_device *ofdev;
	struct ehea_port *port[EHEA_MAX_PORTS];
	struct ehea_eq *neq;       /* notification event queue */
	struct tasklet_struct neq_tasklet;
	struct ehea_mr mr;
	u32 pd;                    /* protection domain */
	u64 max_mc_mac;            /* max number of multicast mac addresses */
	int active_ports;
	struct list_head list;
};


struct ehea_mc_list {
	struct list_head list;
	u64 macaddr;
};

/* kdump support */
struct ehea_fw_handle_entry {
	u64 adh;               /* Adapter Handle */
	u64 fwh;               /* Firmware Handle */
};

struct ehea_fw_handle_array {
	struct ehea_fw_handle_entry *arr;
	int num_entries;
	struct mutex lock;
};

struct ehea_bcmc_reg_entry {
	u64 adh;               /* Adapter Handle */
	u32 port_id;           /* Logical Port Id */
	u8 reg_type;           /* Registration Type */
	u64 macaddr;
};

struct ehea_bcmc_reg_array {
	struct ehea_bcmc_reg_entry *arr;
	int num_entries;
	spinlock_t lock;
};

#define EHEA_PORT_UP 1
#define EHEA_PORT_DOWN 0
#define EHEA_PHY_LINK_UP 1
#define EHEA_PHY_LINK_DOWN 0
#define EHEA_MAX_PORT_RES 16
struct ehea_port {
	struct ehea_adapter *adapter;	 /* adapter that owns this port */
	struct net_device *netdev;
	struct net_device_stats stats;
	struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
	struct of_device  ofdev; /* Open Firmware Device */
	struct ehea_mc_list *mc_list;	 /* Multicast MAC addresses */
	struct vlan_group *vgrp;
	struct ehea_eq *qp_eq;
	struct work_struct reset_task;
	struct mutex port_lock;
	char int_aff_name[EHEA_IRQ_NAME_SIZE];
	int allmulti;			 /* Indicates IFF_ALLMULTI state */
	int promisc;		 	 /* Indicates IFF_PROMISC state */
	int num_tx_qps;
	int num_add_tx_qps;
	int num_mcs;
	int resets;
	unsigned long flags;
	u64 mac_addr;
	u32 logical_port_id;
	u32 port_speed;
	u32 msg_enable;
	u32 sig_comp_iv;
	u32 state;
	u32 lro_max_aggr;
	u8 phy_link;
	u8 full_duplex;
	u8 autoneg;
	u8 num_def_qps;
};

struct port_res_cfg {
	int max_entries_rcq;
	int max_entries_scq;
	int max_entries_sq;
	int max_entries_rq1;
	int max_entries_rq2;
	int max_entries_rq3;
};

enum ehea_flag_bits {
	__EHEA_STOP_XFER,
	__EHEA_DISABLE_PORT_RESET
};

void ehea_set_ethtool_ops(struct net_device *netdev);
int ehea_sense_port_attr(struct ehea_port *port);
int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);

extern struct work_struct ehea_rereg_mr_task;

#endif	/* __EHEA_H__ */
Commit	Line	Data
7a291083 JBT	1	/*
	2	* linux/drivers/net/ehea/ehea.h
	3	*
	4	* eHEA ethernet device driver for IBM eServer System p
	5	*
	6	* (C) Copyright IBM Corp. 2006
	7	*
	8	* Authors:
	9	* Christoph Raisch <raisch@de.ibm.com>
	10	* Jan-Bernd Themann <themann@de.ibm.com>
	11	* Thomas Klein <tklein@de.ibm.com>
	12	*
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2, or (at your option)
	17	* any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	27	*/
	28
	29	#ifndef __EHEA_H__
	30	#define __EHEA_H__
	31
	32	#include <linux/module.h>
	33	#include <linux/ethtool.h>
	34	#include <linux/vmalloc.h>
	35	#include <linux/if_vlan.h>
d4dc4ec9	36	#include <linux/inet_lro.h>
7a291083 JBT	37
	38	#include <asm/ibmebus.h>
	39	#include <asm/abs_addr.h>
	40	#include <asm/io.h>
	41
	42	#define DRV_NAME "ehea"
099473c1	43	#define DRV_VERSION "EHEA_0105"
4c3ca4da	44
44c82152	45	/* eHEA capability flags */
4c3ca4da	46	#define DLPAR_PORT_ADD_REM 1
44c82152 TK	47	#define DLPAR_MEM_ADD 2
44c82152 TK	48	#define DLPAR_MEM_REM 4
b514f6b6	49	#define EHEA_CAPABILITIES (DLPAR_PORT_ADD_REM \| DLPAR_MEM_ADD \| DLPAR_MEM_REM)
7a291083 JBT	50
	51	#define EHEA_MSG_DEFAULT (NETIF_MSG_LINK \| NETIF_MSG_TIMER \
	52	\| NETIF_MSG_RX_ERR \| NETIF_MSG_TX_ERR)
	53
	54	#define EHEA_MAX_ENTRIES_RQ1 32767
	55	#define EHEA_MAX_ENTRIES_RQ2 16383
	56	#define EHEA_MAX_ENTRIES_RQ3 16383
	57	#define EHEA_MAX_ENTRIES_SQ 32767
	58	#define EHEA_MIN_ENTRIES_QP 127
	59
bff0a55f	60	#define EHEA_SMALL_QUEUES
7a291083	61	#define EHEA_NUM_TX_QP 1
d4dc4ec9	62	#define EHEA_LRO_MAX_AGGR 64
7a291083 JBT	63
	64	#ifdef EHEA_SMALL_QUEUES
	65	#define EHEA_MAX_CQE_COUNT 1023
	66	#define EHEA_DEF_ENTRIES_SQ 1023
	67	#define EHEA_DEF_ENTRIES_RQ1 4095
	68	#define EHEA_DEF_ENTRIES_RQ2 1023
	69	#define EHEA_DEF_ENTRIES_RQ3 1023
	70	#else
bff0a55f JBT	71	#define EHEA_MAX_CQE_COUNT 4080
	72	#define EHEA_DEF_ENTRIES_SQ 4080
	73	#define EHEA_DEF_ENTRIES_RQ1 8160
	74	#define EHEA_DEF_ENTRIES_RQ2 2040
	75	#define EHEA_DEF_ENTRIES_RQ3 2040
7a291083 JBT	76	#endif
	77
	78	#define EHEA_MAX_ENTRIES_EQ 20
	79
	80	#define EHEA_SG_SQ 2
	81	#define EHEA_SG_RQ1 1
	82	#define EHEA_SG_RQ2 0
	83	#define EHEA_SG_RQ3 0
	84
	85	#define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */
	86	#define EHEA_RQ2_PKT_SIZE 1522
	87	#define EHEA_L_PKT_SIZE 256 /* low latency */
	88
d4dc4ec9 JBT	89	#define MAX_LRO_DESCRIPTORS 8
d4dc4ec9 JBT	90
7a291083	91	/* Send completion signaling */
7a291083 JBT	92
	93	/* Protection Domain Identifier */
	94	#define EHEA_PD_ID 0xaabcdeff
	95
	96	#define EHEA_RQ2_THRESHOLD 1
	97	#define EHEA_RQ3_THRESHOLD 9 /* use RQ3 threshold of 1522 bytes */
	98
	99	#define EHEA_SPEED_10G 10000
	100	#define EHEA_SPEED_1G 1000
	101	#define EHEA_SPEED_100M 100
	102	#define EHEA_SPEED_10M 10
	103	#define EHEA_SPEED_AUTONEG 0
	104
	105	/* Broadcast/Multicast registration types */
	106	#define EHEA_BCMC_SCOPE_ALL 0x08
	107	#define EHEA_BCMC_SCOPE_SINGLE 0x00
	108	#define EHEA_BCMC_MULTICAST 0x04
	109	#define EHEA_BCMC_BROADCAST 0x00
	110	#define EHEA_BCMC_UNTAGGED 0x02
	111	#define EHEA_BCMC_TAGGED 0x00
	112	#define EHEA_BCMC_VLANID_ALL 0x01
	113	#define EHEA_BCMC_VLANID_SINGLE 0x00
	114
7a291083 JBT	115	#define EHEA_CACHE_LINE 128
	116
	117	/* Memory Regions */
7a291083	118	#define EHEA_MR_ACC_CTRL 0x00800000
7a291083	119
44c82152	120	#define EHEA_BUSMAP_START 0x8000000000000000ULL
48cfb14f HH	121	#define EHEA_INVAL_ADDR 0xFFFFFFFFFFFFFFFFULL
	122	#define EHEA_DIR_INDEX_SHIFT 13 /* 8k Entries in 64k block */
	123	#define EHEA_TOP_INDEX_SHIFT (EHEA_DIR_INDEX_SHIFT * 2)
	124	#define EHEA_MAP_ENTRIES (1 << EHEA_DIR_INDEX_SHIFT)
	125	#define EHEA_MAP_SIZE (0x10000) /* currently fixed map size */
	126	#define EHEA_INDEX_MASK (EHEA_MAP_ENTRIES - 1)
	127
44c82152	128
7a291083 JBT	129	#define EHEA_WATCH_DOG_TIMEOUT 10*HZ
	130
	131	/* utility functions */
	132
	133	#define ehea_info(fmt, args...) \
	134	printk(KERN_INFO DRV_NAME ": " fmt "\n", ## args)
	135
	136	#define ehea_error(fmt, args...) \
	137	printk(KERN_ERR DRV_NAME ": Error in %s: " fmt "\n", __func__, ## args)
	138
	139	#ifdef DEBUG
	140	#define ehea_debug(fmt, args...) \
	141	printk(KERN_DEBUG DRV_NAME ": " fmt, ## args)
	142	#else
	143	#define ehea_debug(fmt, args...) do {} while (0)
	144	#endif
	145
	146	void ehea_dump(void adr, int len, char msg);
	147
	148	#define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
	149
	150	#define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))
	151
	152	#define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
	153
	154	#define EHEA_BMASK_MASK(mask) \
	155	(0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))
	156
	157	#define EHEA_BMASK_SET(mask, value) \
d1d25aab	158	((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))
7a291083 JBT	159
7a291083 JBT	160	#define EHEA_BMASK_GET(mask, value) \
d1d25aab	161	(EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))
7a291083 JBT	162
	163	/*
	164	* Generic ehea page
	165	*/
	166	struct ehea_page {
	167	u8 entries[PAGE_SIZE];
	168	};
	169
	170	/*
	171	* Generic queue in linux kernel virtual memory
	172	*/
	173	struct hw_queue {
	174	u64 current_q_offset; /* current queue entry */
	175	struct ehea_page *queue_pages; / array of pages belonging to queue */
	176	u32 qe_size; /* queue entry size */
	177	u32 queue_length; /* queue length allocated in bytes */
	178	u32 pagesize;
	179	u32 toggle_state; /* toggle flag - per page */
	180	u32 reserved; /* 64 bit alignment */
	181	};
	182
	183	/*
	184	* For pSeries this is a 64bit memory address where
	185	* I/O memory is mapped into CPU address space
	186	*/
	187	struct h_epa {
	188	void __iomem *addr;
	189	};
	190
	191	struct h_epa_user {
	192	u64 addr;
	193	};
	194
	195	struct h_epas {
	196	struct h_epa kernel; /* kernel space accessible resource,
	197	set to 0 if unused */
	198	struct h_epa_user user; /* user space accessible resource
	199	set to 0 if unused */
	200	};
	201
48cfb14f HH	202	/*
	203	* Memory map data structures
	204	*/
	205	struct ehea_dir_bmap
	206	{
	207	u64 ent[EHEA_MAP_ENTRIES];
	208	};
	209	struct ehea_top_bmap
	210	{
	211	struct ehea_dir_bmap *dir[EHEA_MAP_ENTRIES];
	212	};
	213	struct ehea_bmap
	214	{
	215	struct ehea_top_bmap *top[EHEA_MAP_ENTRIES];
44c82152 TK	216	};
44c82152 TK	217
7a291083 JBT	218	struct ehea_qp;
	219	struct ehea_cq;
	220	struct ehea_eq;
	221	struct ehea_port;
	222	struct ehea_av;
	223
	224	/*
	225	* Queue attributes passed to ehea_create_qp()
	226	*/
	227	struct ehea_qp_init_attr {
d1d25aab	228	/* input parameter */
7a291083 JBT	229	u32 qp_token; /* queue token */
	230	u8 low_lat_rq1;
	231	u8 signalingtype; /* cqe generation flag */
	232	u8 rq_count; /* num of receive queues */
	233	u8 eqe_gen; /* eqe generation flag */
	234	u16 max_nr_send_wqes; /* max number of send wqes */
	235	u16 max_nr_rwqes_rq1; /* max number of receive wqes */
	236	u16 max_nr_rwqes_rq2;
	237	u16 max_nr_rwqes_rq3;
	238	u8 wqe_size_enc_sq;
	239	u8 wqe_size_enc_rq1;
	240	u8 wqe_size_enc_rq2;
	241	u8 wqe_size_enc_rq3;
	242	u8 swqe_imm_data_len; /* immediate data length for swqes */
	243	u16 port_nr;
	244	u16 rq2_threshold;
	245	u16 rq3_threshold;
	246	u64 send_cq_handle;
	247	u64 recv_cq_handle;
	248	u64 aff_eq_handle;
	249
d1d25aab	250	/* output parameter */
7a291083 JBT	251	u32 qp_nr;
	252	u16 act_nr_send_wqes;
	253	u16 act_nr_rwqes_rq1;
	254	u16 act_nr_rwqes_rq2;
	255	u16 act_nr_rwqes_rq3;
	256	u8 act_wqe_size_enc_sq;
	257	u8 act_wqe_size_enc_rq1;
	258	u8 act_wqe_size_enc_rq2;
	259	u8 act_wqe_size_enc_rq3;
	260	u32 nr_sq_pages;
	261	u32 nr_rq1_pages;
	262	u32 nr_rq2_pages;
	263	u32 nr_rq3_pages;
	264	u32 liobn_sq;
	265	u32 liobn_rq1;
	266	u32 liobn_rq2;
	267	u32 liobn_rq3;
	268	};
	269
	270	/*
98a1708d	271	* Event Queue attributes, passed as parameter
7a291083 JBT	272	*/
	273	struct ehea_eq_attr {
	274	u32 type;
	275	u32 max_nr_of_eqes;
	276	u8 eqe_gen; /* generate eqe flag */
	277	u64 eq_handle;
	278	u32 act_nr_of_eqes;
	279	u32 nr_pages;
	280	u32 ist1; /* Interrupt service token */
	281	u32 ist2;
	282	u32 ist3;
	283	u32 ist4;
	284	};
	285
	286
	287	/*
	288	* Event Queue
	289	*/
	290	struct ehea_eq {
	291	struct ehea_adapter *adapter;
	292	struct hw_queue hw_queue;
	293	u64 fw_handle;
	294	struct h_epas epas;
	295	spinlock_t spinlock;
	296	struct ehea_eq_attr attr;
	297	};
	298
	299	/*
	300	* HEA Queues
	301	*/
	302	struct ehea_qp {
	303	struct ehea_adapter *adapter;
	304	u64 fw_handle; /* QP handle for firmware calls */
	305	struct hw_queue hw_squeue;
	306	struct hw_queue hw_rqueue1;
	307	struct hw_queue hw_rqueue2;
	308	struct hw_queue hw_rqueue3;
	309	struct h_epas epas;
	310	struct ehea_qp_init_attr init_attr;
	311	};
	312
	313	/*
	314	* Completion Queue attributes
	315	*/
	316	struct ehea_cq_attr {
d1d25aab	317	/* input parameter */
7a291083 JBT	318	u32 max_nr_of_cqes;
	319	u32 cq_token;
	320	u64 eq_handle;
	321
d1d25aab	322	/* output parameter */
7a291083 JBT	323	u32 act_nr_of_cqes;
	324	u32 nr_pages;
	325	};
	326
	327	/*
	328	* Completion Queue
	329	*/
	330	struct ehea_cq {
	331	struct ehea_adapter *adapter;
	332	u64 fw_handle;
	333	struct hw_queue hw_queue;
	334	struct h_epas epas;
	335	struct ehea_cq_attr attr;
	336	};
	337
	338	/*
	339	* Memory Region
	340	*/
	341	struct ehea_mr {
e542aa6b	342	struct ehea_adapter *adapter;
7a291083 JBT	343	u64 handle;
	344	u64 vaddr;
	345	u32 lkey;
	346	};
	347
	348	/*
	349	* Port state information
	350	*/
acbddb59	351	struct port_stats {
7a291083	352	int poll_receive_errors;
7a291083	353	int queue_stopped;
acbddb59 JBT	354	int err_tcp_cksum;
	355	int err_ip_cksum;
	356	int err_frame_crc;
7a291083 JBT	357	};
	358
	359	#define EHEA_IRQ_NAME_SIZE 20
	360
	361	/*
	362	* Queue SKB Array
	363	*/
	364	struct ehea_q_skb_arr {
	365	struct sk_buff *arr; / skb array for queue */
	366	int len; /* array length */
	367	int index; /* array index */
	368	int os_skbs; /* rq2/rq3 only: outstanding skbs */
	369	};
	370
	371	/*
	372	* Port resources
	373	*/
	374	struct ehea_port_res {
bea3348e	375	struct napi_struct napi;
acbddb59	376	struct port_stats p_stats;
7a291083 JBT	377	struct ehea_mr send_mr; /* send memory region */
	378	struct ehea_mr recv_mr; /* receive memory region */
	379	spinlock_t xmit_lock;
	380	struct ehea_port *port;
	381	char int_recv_name[EHEA_IRQ_NAME_SIZE];
	382	char int_send_name[EHEA_IRQ_NAME_SIZE];
	383	struct ehea_qp *qp;
	384	struct ehea_cq *send_cq;
	385	struct ehea_cq *recv_cq;
18604c54	386	struct ehea_eq *eq;
7a291083 JBT	387	struct ehea_q_skb_arr rq1_skba;
	388	struct ehea_q_skb_arr rq2_skba;
	389	struct ehea_q_skb_arr rq3_skba;
	390	struct ehea_q_skb_arr sq_skba;
44fb3126	391	int sq_skba_size;
7a291083 JBT	392	spinlock_t netif_queue;
	393	int queue_stopped;
	394	int swqe_refill_th;
	395	atomic_t swqe_avail;
	396	int swqe_ll_count;
7a291083 JBT	397	u32 swqe_id_counter;
7a291083 JBT	398	u64 tx_packets;
7a291083 JBT	399	u64 rx_packets;
7a291083 JBT	400	u32 poll_counter;
d4dc4ec9 JBT	401	struct net_lro_mgr lro_mgr;
d4dc4ec9 JBT	402	struct net_lro_desc lro_desc[MAX_LRO_DESCRIPTORS];
7a291083 JBT	403	};
	404
	405
1acf2318	406	#define EHEA_MAX_PORTS 16
21eee2dd TK	407
	408	#define EHEA_NUM_PORTRES_FW_HANDLES 6 /* QP handle, SendCQ handle,
	409	RecvCQ handle, EQ handle,
	410	SendMR handle, RecvMR handle */
	411	#define EHEA_NUM_PORT_FW_HANDLES 1 /* EQ handle */
	412	#define EHEA_NUM_ADAPTER_FW_HANDLES 2 /* MR handle, NEQ handle */
	413
7a291083 JBT	414	struct ehea_adapter {
7a291083 JBT	415	u64 handle;
6b08f3ae	416	struct of_device *ofdev;
1acf2318	417	struct ehea_port *port[EHEA_MAX_PORTS];
7a291083	418	struct ehea_eq neq; / notification event queue */
7a291083 JBT	419	struct tasklet_struct neq_tasklet;
	420	struct ehea_mr mr;
	421	u32 pd; /* protection domain */
	422	u64 max_mc_mac; /* max number of multicast mac addresses */
44c82152 TK	423	int active_ports;
44c82152 TK	424	struct list_head list;
7a291083 JBT	425	};
	426
	427
	428	struct ehea_mc_list {
	429	struct list_head list;
	430	u64 macaddr;
	431	};
	432
21eee2dd TK	433	/* kdump support */
	434	struct ehea_fw_handle_entry {
	435	u64 adh; /* Adapter Handle */
	436	u64 fwh; /* Firmware Handle */
	437	};
	438
	439	struct ehea_fw_handle_array {
	440	struct ehea_fw_handle_entry *arr;
	441	int num_entries;
9f71a568	442	struct mutex lock;
21eee2dd TK	443	};
	444
	445	struct ehea_bcmc_reg_entry {
	446	u64 adh; /* Adapter Handle */
	447	u32 port_id; /* Logical Port Id */
	448	u8 reg_type; /* Registration Type */
	449	u64 macaddr;
	450	};
	451
	452	struct ehea_bcmc_reg_array {
	453	struct ehea_bcmc_reg_entry *arr;
	454	int num_entries;
5c2cec14	455	spinlock_t lock;
21eee2dd TK	456	};
21eee2dd TK	457
7a291083 JBT	458	#define EHEA_PORT_UP 1
7a291083 JBT	459	#define EHEA_PORT_DOWN 0
8759cf76 JBT	460	#define EHEA_PHY_LINK_UP 1
8759cf76 JBT	461	#define EHEA_PHY_LINK_DOWN 0
7a291083 JBT	462	#define EHEA_MAX_PORT_RES 16
	463	struct ehea_port {
	464	struct ehea_adapter adapter; / adapter that owns this port */
	465	struct net_device *netdev;
	466	struct net_device_stats stats;
	467	struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
1acf2318	468	struct of_device ofdev; /* Open Firmware Device */
7a291083 JBT	469	struct ehea_mc_list mc_list; / Multicast MAC addresses */
	470	struct vlan_group *vgrp;
	471	struct ehea_eq *qp_eq;
	472	struct work_struct reset_task;
a5af6ad3	473	struct mutex port_lock;
7a291083 JBT	474	char int_aff_name[EHEA_IRQ_NAME_SIZE];
	475	int allmulti; /* Indicates IFF_ALLMULTI state */
	476	int promisc; /* Indicates IFF_PROMISC state */
18604c54	477	int num_tx_qps;
7a291083	478	int num_add_tx_qps;
18604c54	479	int num_mcs;
7a291083	480	int resets;
48e4cc77	481	unsigned long flags;
7a291083 JBT	482	u64 mac_addr;
	483	u32 logical_port_id;
	484	u32 port_speed;
	485	u32 msg_enable;
	486	u32 sig_comp_iv;
	487	u32 state;
d4dc4ec9	488	u32 lro_max_aggr;
8759cf76	489	u8 phy_link;
7a291083 JBT	490	u8 full_duplex;
	491	u8 autoneg;
	492	u8 num_def_qps;
	493	};
	494
	495	struct port_res_cfg {
	496	int max_entries_rcq;
	497	int max_entries_scq;
	498	int max_entries_sq;
	499	int max_entries_rq1;
	500	int max_entries_rq2;
	501	int max_entries_rq3;
	502	};
	503
44c82152	504	enum ehea_flag_bits {
2f69ae01 JBT	505	__EHEA_STOP_XFER,
2f69ae01 JBT	506	__EHEA_DISABLE_PORT_RESET
44c82152	507	};
7a291083 JBT	508
	509	void ehea_set_ethtool_ops(struct net_device *netdev);
	510	int ehea_sense_port_attr(struct ehea_port *port);
	511	int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
	512
c6fa0b03 DM	513	extern struct work_struct ehea_rereg_mr_task;
c6fa0b03 DM	514
7a291083	515	#endif /* __EHEA_H__ */