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7a291083 JBT |
1 | /* |
2 | * linux/drivers/net/ehea/ehea.h | |
3 | * | |
4 | * eHEA ethernet device driver for IBM eServer System p | |
5 | * | |
6 | * (C) Copyright IBM Corp. 2006 | |
7 | * | |
8 | * Authors: | |
9 | * Christoph Raisch <raisch@de.ibm.com> | |
10 | * Jan-Bernd Themann <themann@de.ibm.com> | |
11 | * Thomas Klein <tklein@de.ibm.com> | |
12 | * | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2, or (at your option) | |
17 | * any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
27 | */ | |
28 | ||
29 | #ifndef __EHEA_H__ | |
30 | #define __EHEA_H__ | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/vmalloc.h> | |
35 | #include <linux/if_vlan.h> | |
36 | ||
37 | #include <asm/ibmebus.h> | |
38 | #include <asm/abs_addr.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #define DRV_NAME "ehea" | |
e542aa6b | 42 | #define DRV_VERSION "EHEA_0054" |
7a291083 JBT |
43 | |
44 | #define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \ | |
45 | | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) | |
46 | ||
47 | #define EHEA_MAX_ENTRIES_RQ1 32767 | |
48 | #define EHEA_MAX_ENTRIES_RQ2 16383 | |
49 | #define EHEA_MAX_ENTRIES_RQ3 16383 | |
50 | #define EHEA_MAX_ENTRIES_SQ 32767 | |
51 | #define EHEA_MIN_ENTRIES_QP 127 | |
52 | ||
bff0a55f | 53 | #define EHEA_SMALL_QUEUES |
7a291083 JBT |
54 | #define EHEA_NUM_TX_QP 1 |
55 | ||
56 | #ifdef EHEA_SMALL_QUEUES | |
57 | #define EHEA_MAX_CQE_COUNT 1023 | |
58 | #define EHEA_DEF_ENTRIES_SQ 1023 | |
59 | #define EHEA_DEF_ENTRIES_RQ1 4095 | |
60 | #define EHEA_DEF_ENTRIES_RQ2 1023 | |
61 | #define EHEA_DEF_ENTRIES_RQ3 1023 | |
62 | #else | |
bff0a55f JBT |
63 | #define EHEA_MAX_CQE_COUNT 4080 |
64 | #define EHEA_DEF_ENTRIES_SQ 4080 | |
65 | #define EHEA_DEF_ENTRIES_RQ1 8160 | |
66 | #define EHEA_DEF_ENTRIES_RQ2 2040 | |
67 | #define EHEA_DEF_ENTRIES_RQ3 2040 | |
7a291083 JBT |
68 | #endif |
69 | ||
70 | #define EHEA_MAX_ENTRIES_EQ 20 | |
71 | ||
72 | #define EHEA_SG_SQ 2 | |
73 | #define EHEA_SG_RQ1 1 | |
74 | #define EHEA_SG_RQ2 0 | |
75 | #define EHEA_SG_RQ3 0 | |
76 | ||
77 | #define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */ | |
78 | #define EHEA_RQ2_PKT_SIZE 1522 | |
79 | #define EHEA_L_PKT_SIZE 256 /* low latency */ | |
80 | ||
7a291083 JBT |
81 | /* Send completion signaling */ |
82 | #define EHEA_SIG_IV_LONG 1 | |
83 | ||
84 | /* Protection Domain Identifier */ | |
85 | #define EHEA_PD_ID 0xaabcdeff | |
86 | ||
87 | #define EHEA_RQ2_THRESHOLD 1 | |
88 | #define EHEA_RQ3_THRESHOLD 9 /* use RQ3 threshold of 1522 bytes */ | |
89 | ||
90 | #define EHEA_SPEED_10G 10000 | |
91 | #define EHEA_SPEED_1G 1000 | |
92 | #define EHEA_SPEED_100M 100 | |
93 | #define EHEA_SPEED_10M 10 | |
94 | #define EHEA_SPEED_AUTONEG 0 | |
95 | ||
96 | /* Broadcast/Multicast registration types */ | |
97 | #define EHEA_BCMC_SCOPE_ALL 0x08 | |
98 | #define EHEA_BCMC_SCOPE_SINGLE 0x00 | |
99 | #define EHEA_BCMC_MULTICAST 0x04 | |
100 | #define EHEA_BCMC_BROADCAST 0x00 | |
101 | #define EHEA_BCMC_UNTAGGED 0x02 | |
102 | #define EHEA_BCMC_TAGGED 0x00 | |
103 | #define EHEA_BCMC_VLANID_ALL 0x01 | |
104 | #define EHEA_BCMC_VLANID_SINGLE 0x00 | |
105 | ||
7a291083 JBT |
106 | #define EHEA_CACHE_LINE 128 |
107 | ||
108 | /* Memory Regions */ | |
109 | #define EHEA_MR_MAX_TX_PAGES 20 | |
110 | #define EHEA_MR_TX_DATA_PN 3 | |
111 | #define EHEA_MR_ACC_CTRL 0x00800000 | |
112 | #define EHEA_RWQES_PER_MR_RQ2 10 | |
113 | #define EHEA_RWQES_PER_MR_RQ3 10 | |
114 | ||
115 | #define EHEA_WATCH_DOG_TIMEOUT 10*HZ | |
116 | ||
117 | /* utility functions */ | |
118 | ||
119 | #define ehea_info(fmt, args...) \ | |
120 | printk(KERN_INFO DRV_NAME ": " fmt "\n", ## args) | |
121 | ||
122 | #define ehea_error(fmt, args...) \ | |
123 | printk(KERN_ERR DRV_NAME ": Error in %s: " fmt "\n", __func__, ## args) | |
124 | ||
125 | #ifdef DEBUG | |
126 | #define ehea_debug(fmt, args...) \ | |
127 | printk(KERN_DEBUG DRV_NAME ": " fmt, ## args) | |
128 | #else | |
129 | #define ehea_debug(fmt, args...) do {} while (0) | |
130 | #endif | |
131 | ||
132 | void ehea_dump(void *adr, int len, char *msg); | |
133 | ||
134 | #define EHEA_BMASK(pos, length) (((pos) << 16) + (length)) | |
135 | ||
136 | #define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1)) | |
137 | ||
138 | #define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff) | |
139 | ||
140 | #define EHEA_BMASK_MASK(mask) \ | |
141 | (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff)) | |
142 | ||
143 | #define EHEA_BMASK_SET(mask, value) \ | |
144 | ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask)) | |
145 | ||
146 | #define EHEA_BMASK_GET(mask, value) \ | |
147 | (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask))) | |
148 | ||
149 | /* | |
150 | * Generic ehea page | |
151 | */ | |
152 | struct ehea_page { | |
153 | u8 entries[PAGE_SIZE]; | |
154 | }; | |
155 | ||
156 | /* | |
157 | * Generic queue in linux kernel virtual memory | |
158 | */ | |
159 | struct hw_queue { | |
160 | u64 current_q_offset; /* current queue entry */ | |
161 | struct ehea_page **queue_pages; /* array of pages belonging to queue */ | |
162 | u32 qe_size; /* queue entry size */ | |
163 | u32 queue_length; /* queue length allocated in bytes */ | |
164 | u32 pagesize; | |
165 | u32 toggle_state; /* toggle flag - per page */ | |
166 | u32 reserved; /* 64 bit alignment */ | |
167 | }; | |
168 | ||
169 | /* | |
170 | * For pSeries this is a 64bit memory address where | |
171 | * I/O memory is mapped into CPU address space | |
172 | */ | |
173 | struct h_epa { | |
174 | void __iomem *addr; | |
175 | }; | |
176 | ||
177 | struct h_epa_user { | |
178 | u64 addr; | |
179 | }; | |
180 | ||
181 | struct h_epas { | |
182 | struct h_epa kernel; /* kernel space accessible resource, | |
183 | set to 0 if unused */ | |
184 | struct h_epa_user user; /* user space accessible resource | |
185 | set to 0 if unused */ | |
186 | }; | |
187 | ||
188 | struct ehea_qp; | |
189 | struct ehea_cq; | |
190 | struct ehea_eq; | |
191 | struct ehea_port; | |
192 | struct ehea_av; | |
193 | ||
194 | /* | |
195 | * Queue attributes passed to ehea_create_qp() | |
196 | */ | |
197 | struct ehea_qp_init_attr { | |
198 | /* input parameter */ | |
199 | u32 qp_token; /* queue token */ | |
200 | u8 low_lat_rq1; | |
201 | u8 signalingtype; /* cqe generation flag */ | |
202 | u8 rq_count; /* num of receive queues */ | |
203 | u8 eqe_gen; /* eqe generation flag */ | |
204 | u16 max_nr_send_wqes; /* max number of send wqes */ | |
205 | u16 max_nr_rwqes_rq1; /* max number of receive wqes */ | |
206 | u16 max_nr_rwqes_rq2; | |
207 | u16 max_nr_rwqes_rq3; | |
208 | u8 wqe_size_enc_sq; | |
209 | u8 wqe_size_enc_rq1; | |
210 | u8 wqe_size_enc_rq2; | |
211 | u8 wqe_size_enc_rq3; | |
212 | u8 swqe_imm_data_len; /* immediate data length for swqes */ | |
213 | u16 port_nr; | |
214 | u16 rq2_threshold; | |
215 | u16 rq3_threshold; | |
216 | u64 send_cq_handle; | |
217 | u64 recv_cq_handle; | |
218 | u64 aff_eq_handle; | |
219 | ||
220 | /* output parameter */ | |
221 | u32 qp_nr; | |
222 | u16 act_nr_send_wqes; | |
223 | u16 act_nr_rwqes_rq1; | |
224 | u16 act_nr_rwqes_rq2; | |
225 | u16 act_nr_rwqes_rq3; | |
226 | u8 act_wqe_size_enc_sq; | |
227 | u8 act_wqe_size_enc_rq1; | |
228 | u8 act_wqe_size_enc_rq2; | |
229 | u8 act_wqe_size_enc_rq3; | |
230 | u32 nr_sq_pages; | |
231 | u32 nr_rq1_pages; | |
232 | u32 nr_rq2_pages; | |
233 | u32 nr_rq3_pages; | |
234 | u32 liobn_sq; | |
235 | u32 liobn_rq1; | |
236 | u32 liobn_rq2; | |
237 | u32 liobn_rq3; | |
238 | }; | |
239 | ||
240 | /* | |
241 | * Event Queue attributes, passed as paramter | |
242 | */ | |
243 | struct ehea_eq_attr { | |
244 | u32 type; | |
245 | u32 max_nr_of_eqes; | |
246 | u8 eqe_gen; /* generate eqe flag */ | |
247 | u64 eq_handle; | |
248 | u32 act_nr_of_eqes; | |
249 | u32 nr_pages; | |
250 | u32 ist1; /* Interrupt service token */ | |
251 | u32 ist2; | |
252 | u32 ist3; | |
253 | u32 ist4; | |
254 | }; | |
255 | ||
256 | ||
257 | /* | |
258 | * Event Queue | |
259 | */ | |
260 | struct ehea_eq { | |
261 | struct ehea_adapter *adapter; | |
262 | struct hw_queue hw_queue; | |
263 | u64 fw_handle; | |
264 | struct h_epas epas; | |
265 | spinlock_t spinlock; | |
266 | struct ehea_eq_attr attr; | |
267 | }; | |
268 | ||
269 | /* | |
270 | * HEA Queues | |
271 | */ | |
272 | struct ehea_qp { | |
273 | struct ehea_adapter *adapter; | |
274 | u64 fw_handle; /* QP handle for firmware calls */ | |
275 | struct hw_queue hw_squeue; | |
276 | struct hw_queue hw_rqueue1; | |
277 | struct hw_queue hw_rqueue2; | |
278 | struct hw_queue hw_rqueue3; | |
279 | struct h_epas epas; | |
280 | struct ehea_qp_init_attr init_attr; | |
281 | }; | |
282 | ||
283 | /* | |
284 | * Completion Queue attributes | |
285 | */ | |
286 | struct ehea_cq_attr { | |
287 | /* input parameter */ | |
288 | u32 max_nr_of_cqes; | |
289 | u32 cq_token; | |
290 | u64 eq_handle; | |
291 | ||
292 | /* output parameter */ | |
293 | u32 act_nr_of_cqes; | |
294 | u32 nr_pages; | |
295 | }; | |
296 | ||
297 | /* | |
298 | * Completion Queue | |
299 | */ | |
300 | struct ehea_cq { | |
301 | struct ehea_adapter *adapter; | |
302 | u64 fw_handle; | |
303 | struct hw_queue hw_queue; | |
304 | struct h_epas epas; | |
305 | struct ehea_cq_attr attr; | |
306 | }; | |
307 | ||
308 | /* | |
309 | * Memory Region | |
310 | */ | |
311 | struct ehea_mr { | |
e542aa6b | 312 | struct ehea_adapter *adapter; |
7a291083 JBT |
313 | u64 handle; |
314 | u64 vaddr; | |
315 | u32 lkey; | |
316 | }; | |
317 | ||
318 | /* | |
319 | * Port state information | |
320 | */ | |
321 | struct port_state { | |
322 | int poll_max_processed; | |
323 | int poll_receive_errors; | |
324 | int ehea_poll; | |
325 | int queue_stopped; | |
326 | int min_swqe_avail; | |
327 | u64 sqc_stop_sum; | |
328 | int pkt_send; | |
329 | int pkt_xmit; | |
330 | int send_tasklet; | |
331 | int nwqe; | |
332 | }; | |
333 | ||
334 | #define EHEA_IRQ_NAME_SIZE 20 | |
335 | ||
336 | /* | |
337 | * Queue SKB Array | |
338 | */ | |
339 | struct ehea_q_skb_arr { | |
340 | struct sk_buff **arr; /* skb array for queue */ | |
341 | int len; /* array length */ | |
342 | int index; /* array index */ | |
343 | int os_skbs; /* rq2/rq3 only: outstanding skbs */ | |
344 | }; | |
345 | ||
346 | /* | |
347 | * Port resources | |
348 | */ | |
349 | struct ehea_port_res { | |
350 | struct ehea_mr send_mr; /* send memory region */ | |
351 | struct ehea_mr recv_mr; /* receive memory region */ | |
352 | spinlock_t xmit_lock; | |
353 | struct ehea_port *port; | |
354 | char int_recv_name[EHEA_IRQ_NAME_SIZE]; | |
355 | char int_send_name[EHEA_IRQ_NAME_SIZE]; | |
356 | struct ehea_qp *qp; | |
357 | struct ehea_cq *send_cq; | |
358 | struct ehea_cq *recv_cq; | |
18604c54 JBT |
359 | struct ehea_eq *eq; |
360 | struct net_device *d_netdev; | |
7a291083 JBT |
361 | spinlock_t send_lock; |
362 | struct ehea_q_skb_arr rq1_skba; | |
363 | struct ehea_q_skb_arr rq2_skba; | |
364 | struct ehea_q_skb_arr rq3_skba; | |
365 | struct ehea_q_skb_arr sq_skba; | |
366 | spinlock_t netif_queue; | |
367 | int queue_stopped; | |
368 | int swqe_refill_th; | |
369 | atomic_t swqe_avail; | |
370 | int swqe_ll_count; | |
371 | int swqe_count; | |
372 | u32 swqe_id_counter; | |
373 | u64 tx_packets; | |
7a291083 JBT |
374 | spinlock_t recv_lock; |
375 | struct port_state p_state; | |
376 | u64 rx_packets; | |
377 | u32 poll_counter; | |
378 | }; | |
379 | ||
380 | ||
1acf2318 | 381 | #define EHEA_MAX_PORTS 16 |
7a291083 JBT |
382 | struct ehea_adapter { |
383 | u64 handle; | |
1acf2318 JBT |
384 | struct ibmebus_dev *ebus_dev; |
385 | struct ehea_port *port[EHEA_MAX_PORTS]; | |
7a291083 JBT |
386 | struct ehea_eq *neq; /* notification event queue */ |
387 | struct workqueue_struct *ehea_wq; | |
388 | struct tasklet_struct neq_tasklet; | |
389 | struct ehea_mr mr; | |
390 | u32 pd; /* protection domain */ | |
391 | u64 max_mc_mac; /* max number of multicast mac addresses */ | |
392 | }; | |
393 | ||
394 | ||
395 | struct ehea_mc_list { | |
396 | struct list_head list; | |
397 | u64 macaddr; | |
398 | }; | |
399 | ||
400 | #define EHEA_PORT_UP 1 | |
401 | #define EHEA_PORT_DOWN 0 | |
402 | #define EHEA_MAX_PORT_RES 16 | |
403 | struct ehea_port { | |
404 | struct ehea_adapter *adapter; /* adapter that owns this port */ | |
405 | struct net_device *netdev; | |
406 | struct net_device_stats stats; | |
407 | struct ehea_port_res port_res[EHEA_MAX_PORT_RES]; | |
1acf2318 | 408 | struct of_device ofdev; /* Open Firmware Device */ |
7a291083 JBT |
409 | struct ehea_mc_list *mc_list; /* Multicast MAC addresses */ |
410 | struct vlan_group *vgrp; | |
411 | struct ehea_eq *qp_eq; | |
412 | struct work_struct reset_task; | |
413 | struct semaphore port_lock; | |
414 | char int_aff_name[EHEA_IRQ_NAME_SIZE]; | |
415 | int allmulti; /* Indicates IFF_ALLMULTI state */ | |
416 | int promisc; /* Indicates IFF_PROMISC state */ | |
18604c54 | 417 | int num_tx_qps; |
7a291083 | 418 | int num_add_tx_qps; |
18604c54 | 419 | int num_mcs; |
7a291083 JBT |
420 | int resets; |
421 | u64 mac_addr; | |
422 | u32 logical_port_id; | |
423 | u32 port_speed; | |
424 | u32 msg_enable; | |
425 | u32 sig_comp_iv; | |
426 | u32 state; | |
427 | u8 full_duplex; | |
428 | u8 autoneg; | |
429 | u8 num_def_qps; | |
430 | }; | |
431 | ||
432 | struct port_res_cfg { | |
433 | int max_entries_rcq; | |
434 | int max_entries_scq; | |
435 | int max_entries_sq; | |
436 | int max_entries_rq1; | |
437 | int max_entries_rq2; | |
438 | int max_entries_rq3; | |
439 | }; | |
440 | ||
441 | ||
442 | void ehea_set_ethtool_ops(struct net_device *netdev); | |
443 | int ehea_sense_port_attr(struct ehea_port *port); | |
444 | int ehea_set_portspeed(struct ehea_port *port, u32 port_speed); | |
445 | ||
446 | #endif /* __EHEA_H__ */ |