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[net-next-2.6.git] / drivers / net / e1000e / e1000.h
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bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
c7e54b1b 4 Copyright(c) 1999 - 2009 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
34#include <linux/types.h>
35#include <linux/timer.h>
36#include <linux/workqueue.h>
37#include <linux/io.h>
38#include <linux/netdevice.h>
d8014dbc 39#include <linux/pci.h>
bc7f75fa
AK		 40
41#include "hw.h"
42
43struct e1000_info;
44
44defeb3 45#define e_dbg(format, arg...) \
8544b9f7 46 netdev_dbg(hw->adapter->netdev, format, ## arg)
44defeb3 47#define e_err(format, arg...) \
8544b9f7 48 netdev_err(adapter->netdev, format, ## arg)
44defeb3 49#define e_info(format, arg...) \
8544b9f7 50 netdev_info(adapter->netdev, format, ## arg)
44defeb3 51#define e_warn(format, arg...) \
8544b9f7 52 netdev_warn(adapter->netdev, format, ## arg)
44defeb3 53#define e_notice(format, arg...) \
8544b9f7 54 netdev_notice(adapter->netdev, format, ## arg)
bc7f75fa
AK		 55
56
98a1708d 57/* Interrupt modes, as used by the IntMode parameter */
4662e82b
BA		 58#define E1000E_INT_MODE_LEGACY 0
59#define E1000E_INT_MODE_MSI 1
60#define E1000E_INT_MODE_MSIX 2
61
ad68076e 62/* Tx/Rx descriptor defines */
bc7f75fa
AK		 63#define E1000_DEFAULT_TXD 256
64#define E1000_MAX_TXD 4096
7b1be198 65#define E1000_MIN_TXD 64
bc7f75fa
AK		 66
67#define E1000_DEFAULT_RXD 256
68#define E1000_MAX_RXD 4096
7b1be198 69#define E1000_MIN_RXD 64
bc7f75fa 70
de5b3077
AK		 71#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
72#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
73
bc7f75fa
AK		 74/* Early Receive defines */
75#define E1000_ERT_2048 0x100
76
77#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
78
79/* How many Tx Descriptors do we need to call netif_wake_queue ? */
80/* How many Rx Buffers do we bundle into one write to the hardware ? */
81#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
82
83#define AUTO_ALL_MODES 0
84#define E1000_EEPROM_APME 0x0400
85
86#define E1000_MNG_VLAN_NONE (-1)
87
88/* Number of packet split data buffers (not including the header buffer) */
89#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
90
2adc55c9
BA		 91#define DEFAULT_JUMBO 9234
92
a4f58f54
BA		 93/* BM/HV Specific Registers */
94#define BM_PORT_CTRL_PAGE 769
95
96#define PHY_UPPER_SHIFT 21
97#define BM_PHY_REG(page, reg) \
98 (((reg) & MAX_PHY_REG_ADDRESS) |\
99 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
100 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
101
102/* PHY Wakeup Registers and defines */
103#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
104#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
105#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
106#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
107#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
108#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
109#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
110#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
111#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
112
113#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
114#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
115#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
116#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
117#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
118#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
119#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
120
121#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
122#define HV_SCC_LOWER PHY_REG(778, 17)
123#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
124#define HV_ECOL_LOWER PHY_REG(778, 19)
125#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
126#define HV_MCC_LOWER PHY_REG(778, 21)
127#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
128#define HV_LATECOL_LOWER PHY_REG(778, 24)
129#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
130#define HV_COLC_LOWER PHY_REG(778, 26)
131#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
132#define HV_DC_LOWER PHY_REG(778, 28)
133#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
134#define HV_TNCRS_LOWER PHY_REG(778, 30)
135
38eb394e
BA		 136#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
137
1d5846b9
BA		 138/* BM PHY Copper Specific Status */
139#define BM_CS_STATUS 17
140#define BM_CS_STATUS_LINK_UP 0x0400
141#define BM_CS_STATUS_RESOLVED 0x0800
142#define BM_CS_STATUS_SPEED_MASK 0xC000
143#define BM_CS_STATUS_SPEED_1000 0x8000
144
145/* 82577 Mobile Phy Status Register */
146#define HV_M_STATUS 26
147#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
148#define HV_M_STATUS_SPEED_MASK 0x0300
149#define HV_M_STATUS_SPEED_1000 0x0200
150#define HV_M_STATUS_LINK_UP 0x0040
151
23606cf5
RW		 152/* Time to wait before putting the device into D3 if there's no link (in ms). */
153#define LINK_TIMEOUT 100
154
bc7f75fa
AK		 155enum e1000_boards {
156 board_82571,
157 board_82572,
158 board_82573,
4662e82b 159 board_82574,
8c81c9c3 160 board_82583,
bc7f75fa
AK		 161 board_80003es2lan,
162 board_ich8lan,
163 board_ich9lan,
f4187b56 164 board_ich10lan,
a4f58f54 165 board_pchlan,
bc7f75fa
AK		 166};
167
168struct e1000_queue_stats {
169 u64 packets;
170 u64 bytes;
171};
172
173struct e1000_ps_page {
174 struct page *page;
175 u64 dma; /* must be u64 - written to hw */
176};
177
178/*
179 * wrappers around a pointer to a socket buffer,
180 * so a DMA handle can be stored along with the buffer
181 */
182struct e1000_buffer {
183 dma_addr_t dma;
184 struct sk_buff *skb;
185 union {
ad68076e 186 /* Tx */
bc7f75fa
AK		 187 struct {
188 unsigned long time_stamp;
189 u16 length;
190 u16 next_to_watch;
03b1320d 191 u16 mapped_as_page;
bc7f75fa 192 };
ad68076e 193 /* Rx */
03b1320d
AD		 194 struct {
195 /* arrays of page information for packet split */
196 struct e1000_ps_page *ps_pages;
197 struct page *page;
198 };
bc7f75fa 199 };
bc7f75fa
AK		 200};
201
202struct e1000_ring {
203 void *desc; /* pointer to ring memory */
204 dma_addr_t dma; /* phys address of ring */
205 unsigned int size; /* length of ring in bytes */
206 unsigned int count; /* number of desc. in ring */
207
208 u16 next_to_use;
209 u16 next_to_clean;
210
211 u16 head;
212 u16 tail;
213
214 /* array of buffer information structs */
215 struct e1000_buffer *buffer_info;
216
4662e82b
BA		 217 char name[IFNAMSIZ + 5];
218 u32 ims_val;
219 u32 itr_val;
220 u16 itr_register;
221 int set_itr;
222
bc7f75fa
AK		 223 struct sk_buff *rx_skb_top;
224
225 struct e1000_queue_stats stats;
226};
227
7c25769f
BA		 228/* PHY register snapshot values */
229struct e1000_phy_regs {
230 u16 bmcr; /* basic mode control register */
231 u16 bmsr; /* basic mode status register */
232 u16 advertise; /* auto-negotiation advertisement */
233 u16 lpa; /* link partner ability register */
234 u16 expansion; /* auto-negotiation expansion reg */
235 u16 ctrl1000; /* 1000BASE-T control register */
236 u16 stat1000; /* 1000BASE-T status register */
237 u16 estatus; /* extended status register */
238};
239
bc7f75fa
AK		 240/* board specific private data structure */
241struct e1000_adapter {
242 struct timer_list watchdog_timer;
243 struct timer_list phy_info_timer;
244 struct timer_list blink_timer;
245
246 struct work_struct reset_task;
247 struct work_struct watchdog_task;
248
249 const struct e1000_info *ei;
250
251 struct vlan_group *vlgrp;
252 u32 bd_number;
253 u32 rx_buffer_len;
254 u16 mng_vlan_id;
255 u16 link_speed;
256 u16 link_duplex;
84527590 257 u16 eeprom_vers;
bc7f75fa 258
bc7f75fa
AK		 259 /* track device up/down/testing state */
260 unsigned long state;
261
262 /* Interrupt Throttle Rate */
263 u32 itr;
264 u32 itr_setting;
265 u16 tx_itr;
266 u16 rx_itr;
267
268 /*
ad68076e 269 * Tx
bc7f75fa
AK		 270 */
271 struct e1000_ring *tx_ring /* One per active queue */
272 ____cacheline_aligned_in_smp;
273
274 struct napi_struct napi;
275
276 unsigned long tx_queue_len;
277 unsigned int restart_queue;
278 u32 txd_cmd;
279
280 bool detect_tx_hung;
281 u8 tx_timeout_factor;
282
283 u32 tx_int_delay;
284 u32 tx_abs_int_delay;
285
286 unsigned int total_tx_bytes;
287 unsigned int total_tx_packets;
288 unsigned int total_rx_bytes;
289 unsigned int total_rx_packets;
290
ad68076e 291 /* Tx stats */
bc7f75fa
AK		 292 u64 tpt_old;
293 u64 colc_old;
7c25769f
BA		 294 u32 gotc;
295 u64 gotc_old;
bc7f75fa
AK		 296 u32 tx_timeout_count;
297 u32 tx_fifo_head;
298 u32 tx_head_addr;
299 u32 tx_fifo_size;
300 u32 tx_dma_failed;
301
302 /*
ad68076e 303 * Rx
bc7f75fa
AK		 304 */
305 bool (*clean_rx) (struct e1000_adapter *adapter,
306 int *work_done, int work_to_do)
307 ____cacheline_aligned_in_smp;
308 void (*alloc_rx_buf) (struct e1000_adapter *adapter,
309 int cleaned_count);
310 struct e1000_ring *rx_ring;
311
312 u32 rx_int_delay;
313 u32 rx_abs_int_delay;
314
ad68076e 315 /* Rx stats */
bc7f75fa
AK		 316 u64 hw_csum_err;
317 u64 hw_csum_good;
318 u64 rx_hdr_split;
7c25769f
BA		 319 u32 gorc;
320 u64 gorc_old;
bc7f75fa
AK		 321 u32 alloc_rx_buff_failed;
322 u32 rx_dma_failed;
323
324 unsigned int rx_ps_pages;
325 u16 rx_ps_bsize0;
318a94d6
JK		 326 u32 max_frame_size;
327 u32 min_frame_size;
bc7f75fa
AK		 328
329 /* OS defined structs */
330 struct net_device *netdev;
331 struct pci_dev *pdev;
bc7f75fa
AK		 332
333 /* structs defined in e1000_hw.h */
334 struct e1000_hw hw;
335
336 struct e1000_hw_stats stats;
337 struct e1000_phy_info phy_info;
338 struct e1000_phy_stats phy_stats;
339
7c25769f
BA		 340 /* Snapshot of PHY registers */
341 struct e1000_phy_regs phy_regs;
342
bc7f75fa
AK		 343 struct e1000_ring test_tx_ring;
344 struct e1000_ring test_rx_ring;
345 u32 test_icr;
346
347 u32 msg_enable;
4662e82b
BA		 348 struct msix_entry *msix_entries;
349 int int_mode;
350 u32 eiac_mask;
bc7f75fa
AK		 351
352 u32 eeprom_wol;
353 u32 wol;
354 u32 pba;
2adc55c9 355 u32 max_hw_frame_size;
bc7f75fa 356
318a94d6 357 bool fc_autoneg;
bc7f75fa
AK		 358
359 unsigned long led_status;
360
361 unsigned int flags;
eb7c3adb 362 unsigned int flags2;
a8f88ff5
JB		 363 struct work_struct downshift_task;
364 struct work_struct update_phy_task;
a4f58f54 365 struct work_struct led_blink_task;
41cec6f1 366 struct work_struct print_hang_task;
23606cf5
RW		 367
368 bool idle_check;
bc7f75fa
AK		 369};
370
371struct e1000_info {
372 enum e1000_mac_type mac;
373 unsigned int flags;
eb7c3adb 374 unsigned int flags2;
bc7f75fa 375 u32 pba;
2adc55c9 376 u32 max_hw_frame_size;
69e3fd8c 377 s32 (*get_variants)(struct e1000_adapter *);
bc7f75fa
AK		 378 struct e1000_mac_operations *mac_ops;
379 struct e1000_phy_operations *phy_ops;
380 struct e1000_nvm_operations *nvm_ops;
381};
382
383/* hardware capability, feature, and workaround flags */
384#define FLAG_HAS_AMT (1 << 0)
385#define FLAG_HAS_FLASH (1 << 1)
386#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
387#define FLAG_HAS_WOL (1 << 3)
388#define FLAG_HAS_ERT (1 << 4)
389#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
390#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
391#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
4a770358 392#define FLAG_READ_ONLY_NVM (1 << 8)
97ac8cae 393#define FLAG_IS_ICH (1 << 9)
4662e82b 394#define FLAG_HAS_MSIX (1 << 10)
bc7f75fa
AK		 395#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
396#define FLAG_IS_QUAD_PORT_A (1 << 12)
397#define FLAG_IS_QUAD_PORT (1 << 13)
398#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
399#define FLAG_APME_IN_WUC (1 << 15)
400#define FLAG_APME_IN_CTRL3 (1 << 16)
401#define FLAG_APME_CHECK_PORT_B (1 << 17)
402#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
403#define FLAG_NO_WAKE_UCAST (1 << 19)
404#define FLAG_MNG_PT_ENABLED (1 << 20)
405#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
406#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
407#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
408#define FLAG_RX_NEEDS_RESTART (1 << 24)
409#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
410#define FLAG_SMART_POWER_DOWN (1 << 26)
411#define FLAG_MSI_ENABLED (1 << 27)
412#define FLAG_RX_CSUM_ENABLED (1 << 28)
413#define FLAG_TSO_FORCE (1 << 29)
318a94d6 414#define FLAG_RX_RESTART_NOW (1 << 30)
f8d59f78 415#define FLAG_MSI_TEST_FAILED (1 << 31)
bc7f75fa 416
eb7c3adb
JK		 417/* CRC Stripping defines */
418#define FLAG2_CRC_STRIPPING (1 << 0)
a4f58f54 419#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
b94b5028 420#define FLAG2_IS_DISCARDING (1 << 2)
eb7c3adb 421
bc7f75fa
AK		 422#define E1000_RX_DESC_PS(R, i) \
423 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
424#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
425#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
426#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
427#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
428
429enum e1000_state_t {
430 __E1000_TESTING,
431 __E1000_RESETTING,
432 __E1000_DOWN
433};
434
435enum latency_range {
436 lowest_latency = 0,
437 low_latency = 1,
438 bulk_latency = 2,
439 latency_invalid = 255
440};
441
442extern char e1000e_driver_name[];
443extern const char e1000e_driver_version[];
444
445extern void e1000e_check_options(struct e1000_adapter *adapter);
446extern void e1000e_set_ethtool_ops(struct net_device *netdev);
447
448extern int e1000e_up(struct e1000_adapter *adapter);
449extern void e1000e_down(struct e1000_adapter *adapter);
450extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
451extern void e1000e_reset(struct e1000_adapter *adapter);
452extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
453extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
454extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
455extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
456extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
457extern void e1000e_update_stats(struct e1000_adapter *adapter);
b405e8df 458extern bool e1000e_has_link(struct e1000_adapter *adapter);
4662e82b
BA		 459extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
460extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
bc7f75fa
AK		 461
462extern unsigned int copybreak;
463
464extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
465
466extern struct e1000_info e1000_82571_info;
467extern struct e1000_info e1000_82572_info;
468extern struct e1000_info e1000_82573_info;
4662e82b 469extern struct e1000_info e1000_82574_info;
8c81c9c3 470extern struct e1000_info e1000_82583_info;
bc7f75fa
AK		 471extern struct e1000_info e1000_ich8_info;
472extern struct e1000_info e1000_ich9_info;
f4187b56 473extern struct e1000_info e1000_ich10_info;
a4f58f54 474extern struct e1000_info e1000_pch_info;
bc7f75fa
AK		 475extern struct e1000_info e1000_es2_info;
476
69e3fd8c 477extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
bc7f75fa
AK		 478
479extern s32 e1000e_commit_phy(struct e1000_hw *hw);
480
481extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
482
483extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
484extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
485
4a770358 486extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 487extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
488 bool state);
489extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
490extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
97ac8cae 491extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
bb436b20 492extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
bc7f75fa
AK		 493
494extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
495extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
496extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
a4f58f54 497extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
bc7f75fa
AK		 498extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
499extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
500extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
501extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
f4d2dd4c
BA		 502extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
503extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
bc7f75fa
AK		 504extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
505extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
506extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
507extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
508extern s32 e1000e_id_led_init(struct e1000_hw *hw);
509extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
510extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
511extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
512extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
513extern s32 e1000e_setup_link(struct e1000_hw *hw);
caaddaf8 514extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
bc7f75fa 515extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
e2de3eb6
JK		 516extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
517 u8 *mc_addr_list,
ab8932f3 518 u32 mc_addr_count);
bc7f75fa
AK		 519extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
520extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
521extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
522extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
523extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
524extern void e1000e_config_collision_dist(struct e1000_hw *hw);
525extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
526extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
527extern s32 e1000e_blink_led(struct e1000_hw *hw);
caaddaf8 528extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
608f8a0d 529extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
bc7f75fa
AK		 530extern void e1000e_reset_adaptive(struct e1000_hw *hw);
531extern void e1000e_update_adaptive(struct e1000_hw *hw);
532
533extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
534extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
535extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
536extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
537extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
538extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
539extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
540extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 541extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
542 u16 *data);
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AK		 543extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
544extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
545extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 546extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
547 u16 data);
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AK		 548extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
549extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
550extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
551extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
552extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
553extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
554extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
f4187b56 555extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
bc7f75fa 556extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
97ac8cae
BA		 557extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
558extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
559extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
4662e82b
BA		 560extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
561extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa
AK		 562extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
563extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 564extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
565 u16 data);
bc7f75fa 566extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 567extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
568 u16 *data);
bc7f75fa
AK		 569extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
570 u32 usec_interval, bool *success);
571extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
17f208de
BA		 572extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
573extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
2d9498f3
DG		 574extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
575extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa 576extern s32 e1000e_check_downshift(struct e1000_hw *hw);
a4f58f54 577extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 578extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
579 u16 *data);
a4f58f54 580extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 581extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
582 u16 data);
a4f58f54
BA		 583extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
584extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
585extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
586extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
587extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
588extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
bc7f75fa 589
0be84010
BA		 590extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
591extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
592extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
593extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
594extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
595
bc7f75fa
AK		 596static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
597{
94d8186a 598 return hw->phy.ops.reset(hw);
bc7f75fa
AK		 599}
600
601static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
602{
603 return hw->phy.ops.check_reset_block(hw);
604}
605
606static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
607{
94d8186a 608 return hw->phy.ops.read_reg(hw, offset, data);
bc7f75fa
AK		 609}
610
611static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
612{
94d8186a 613 return hw->phy.ops.write_reg(hw, offset, data);
bc7f75fa
AK		 614}
615
616static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
617{
618 return hw->phy.ops.get_cable_length(hw);
619}
620
621extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
622extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
623extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
624extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
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AK		 625extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
626extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
627extern void e1000e_release_nvm(struct e1000_hw *hw);
628extern void e1000e_reload_nvm(struct e1000_hw *hw);
608f8a0d
BA		 629extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
630
631static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
632{
633 if (hw->mac.ops.read_mac_addr)
634 return hw->mac.ops.read_mac_addr(hw);
635
636 return e1000_read_mac_addr_generic(hw);
637}
bc7f75fa
AK		 638
639static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
640{
94d8186a 641 return hw->nvm.ops.validate(hw);
bc7f75fa
AK		 642}
643
644static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
645{
94d8186a 646 return hw->nvm.ops.update(hw);
bc7f75fa
AK		 647}
648
649static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
650{
94d8186a 651 return hw->nvm.ops.read(hw, offset, words, data);
bc7f75fa
AK		 652}
653
654static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
655{
94d8186a 656 return hw->nvm.ops.write(hw, offset, words, data);
bc7f75fa
AK		 657}
658
659static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
660{
94d8186a 661 return hw->phy.ops.get_info(hw);
bc7f75fa
AK		 662}
663
4662e82b
BA		 664static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
665{
666 return hw->mac.ops.check_mng_mode(hw);
667}
668
669extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
bc7f75fa
AK		 670extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
671extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
672
673static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
674{
675 return readl(hw->hw_addr + reg);
676}
677
678static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
679{
680 writel(val, hw->hw_addr + reg);
681}
682
683#endif /* _E1000_H_ */
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