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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
55 | ||
4662e82b BA |
56 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
57 | ||
bc7f75fa AK |
58 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
59 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
60 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 61 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
62 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
63 | u16 words, u16 *data); | |
64 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
65 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
66 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
67 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
caaddaf8 | 68 | static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
4662e82b BA |
69 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
70 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 71 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
bc7f75fa AK |
72 | |
73 | /** | |
74 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
75 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
76 | **/ |
77 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
78 | { | |
79 | struct e1000_phy_info *phy = &hw->phy; | |
80 | s32 ret_val; | |
81 | ||
318a94d6 | 82 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
83 | phy->type = e1000_phy_none; |
84 | return 0; | |
85 | } | |
86 | ||
87 | phy->addr = 1; | |
88 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
89 | phy->reset_delay_us = 100; | |
90 | ||
91 | switch (hw->mac.type) { | |
92 | case e1000_82571: | |
93 | case e1000_82572: | |
94 | phy->type = e1000_phy_igp_2; | |
95 | break; | |
96 | case e1000_82573: | |
97 | phy->type = e1000_phy_m88; | |
98 | break; | |
4662e82b | 99 | case e1000_82574: |
8c81c9c3 | 100 | case e1000_82583: |
4662e82b BA |
101 | phy->type = e1000_phy_bm; |
102 | break; | |
bc7f75fa AK |
103 | default: |
104 | return -E1000_ERR_PHY; | |
105 | break; | |
106 | } | |
107 | ||
108 | /* This can only be done after all function pointers are setup. */ | |
109 | ret_val = e1000_get_phy_id_82571(hw); | |
110 | ||
111 | /* Verify phy id */ | |
112 | switch (hw->mac.type) { | |
113 | case e1000_82571: | |
114 | case e1000_82572: | |
115 | if (phy->id != IGP01E1000_I_PHY_ID) | |
116 | return -E1000_ERR_PHY; | |
117 | break; | |
118 | case e1000_82573: | |
119 | if (phy->id != M88E1111_I_PHY_ID) | |
120 | return -E1000_ERR_PHY; | |
121 | break; | |
4662e82b | 122 | case e1000_82574: |
8c81c9c3 | 123 | case e1000_82583: |
4662e82b BA |
124 | if (phy->id != BME1000_E_PHY_ID_R2) |
125 | return -E1000_ERR_PHY; | |
126 | break; | |
bc7f75fa AK |
127 | default: |
128 | return -E1000_ERR_PHY; | |
129 | break; | |
130 | } | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | /** | |
136 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
137 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
138 | **/ |
139 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
140 | { | |
141 | struct e1000_nvm_info *nvm = &hw->nvm; | |
142 | u32 eecd = er32(EECD); | |
143 | u16 size; | |
144 | ||
145 | nvm->opcode_bits = 8; | |
146 | nvm->delay_usec = 1; | |
147 | switch (nvm->override) { | |
148 | case e1000_nvm_override_spi_large: | |
149 | nvm->page_size = 32; | |
150 | nvm->address_bits = 16; | |
151 | break; | |
152 | case e1000_nvm_override_spi_small: | |
153 | nvm->page_size = 8; | |
154 | nvm->address_bits = 8; | |
155 | break; | |
156 | default: | |
157 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
158 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
159 | break; | |
160 | } | |
161 | ||
162 | switch (hw->mac.type) { | |
163 | case e1000_82573: | |
4662e82b | 164 | case e1000_82574: |
8c81c9c3 | 165 | case e1000_82583: |
bc7f75fa AK |
166 | if (((eecd >> 15) & 0x3) == 0x3) { |
167 | nvm->type = e1000_nvm_flash_hw; | |
168 | nvm->word_size = 2048; | |
ad68076e BA |
169 | /* |
170 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
171 | * to Flash update issue. |
172 | */ | |
173 | eecd &= ~E1000_EECD_AUPDEN; | |
174 | ew32(EECD, eecd); | |
175 | break; | |
176 | } | |
177 | /* Fall Through */ | |
178 | default: | |
ad68076e | 179 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
180 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
181 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
182 | /* |
183 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
184 | * for setting word_size. |
185 | */ | |
186 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
187 | |
188 | /* EEPROM access above 16k is unsupported */ | |
189 | if (size > 14) | |
190 | size = 14; | |
bc7f75fa AK |
191 | nvm->word_size = 1 << size; |
192 | break; | |
193 | } | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
198 | /** | |
199 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
200 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
201 | **/ |
202 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
203 | { | |
204 | struct e1000_hw *hw = &adapter->hw; | |
205 | struct e1000_mac_info *mac = &hw->mac; | |
206 | struct e1000_mac_operations *func = &mac->ops; | |
23a2d1b2 DG |
207 | u32 swsm = 0; |
208 | u32 swsm2 = 0; | |
209 | bool force_clear_smbi = false; | |
bc7f75fa AK |
210 | |
211 | /* Set media type */ | |
212 | switch (adapter->pdev->device) { | |
213 | case E1000_DEV_ID_82571EB_FIBER: | |
214 | case E1000_DEV_ID_82572EI_FIBER: | |
215 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 216 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
217 | break; |
218 | case E1000_DEV_ID_82571EB_SERDES: | |
219 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
220 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
221 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 222 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
223 | break; |
224 | default: | |
318a94d6 | 225 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
226 | break; |
227 | } | |
228 | ||
229 | /* Set mta register count */ | |
230 | mac->mta_reg_count = 128; | |
231 | /* Set rar entry count */ | |
232 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
233 | /* Set if manageability features are enabled. */ | |
564ea9bb BA |
234 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) |
235 | ? true : false; | |
bc7f75fa AK |
236 | |
237 | /* check for link */ | |
318a94d6 | 238 | switch (hw->phy.media_type) { |
bc7f75fa AK |
239 | case e1000_media_type_copper: |
240 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
241 | func->check_for_link = e1000e_check_for_copper_link; | |
242 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
243 | break; | |
244 | case e1000_media_type_fiber: | |
ad68076e BA |
245 | func->setup_physical_interface = |
246 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 247 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
248 | func->get_link_up_info = |
249 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
250 | break; |
251 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
252 | func->setup_physical_interface = |
253 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 254 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
255 | func->get_link_up_info = |
256 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
257 | break; |
258 | default: | |
259 | return -E1000_ERR_CONFIG; | |
260 | break; | |
261 | } | |
262 | ||
4662e82b BA |
263 | switch (hw->mac.type) { |
264 | case e1000_82574: | |
8c81c9c3 | 265 | case e1000_82583: |
4662e82b BA |
266 | func->check_mng_mode = e1000_check_mng_mode_82574; |
267 | func->led_on = e1000_led_on_82574; | |
268 | break; | |
269 | default: | |
270 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
271 | func->led_on = e1000e_led_on_generic; | |
272 | break; | |
273 | } | |
274 | ||
23a2d1b2 DG |
275 | /* |
276 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
277 | * first NVM or PHY acess. This should be done for single-port | |
278 | * devices, and for one port only on dual-port devices so that | |
279 | * for those devices we can still use the SMBI lock to synchronize | |
280 | * inter-port accesses to the PHY & NVM. | |
281 | */ | |
282 | switch (hw->mac.type) { | |
283 | case e1000_82571: | |
284 | case e1000_82572: | |
285 | swsm2 = er32(SWSM2); | |
286 | ||
287 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
288 | /* Only do this for the first interface on this card */ | |
289 | ew32(SWSM2, | |
290 | swsm2 | E1000_SWSM2_LOCK); | |
291 | force_clear_smbi = true; | |
292 | } else | |
293 | force_clear_smbi = false; | |
294 | break; | |
295 | default: | |
296 | force_clear_smbi = true; | |
297 | break; | |
298 | } | |
299 | ||
300 | if (force_clear_smbi) { | |
301 | /* Make sure SWSM.SMBI is clear */ | |
302 | swsm = er32(SWSM); | |
303 | if (swsm & E1000_SWSM_SMBI) { | |
304 | /* This bit should not be set on a first interface, and | |
305 | * indicates that the bootagent or EFI code has | |
306 | * improperly left this bit enabled | |
307 | */ | |
3bb99fe2 | 308 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
309 | } |
310 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
311 | } | |
312 | ||
313 | /* | |
314 | * Initialze device specific counter of SMBI acquisition | |
315 | * timeouts. | |
316 | */ | |
317 | hw->dev_spec.e82571.smb_counter = 0; | |
318 | ||
bc7f75fa AK |
319 | return 0; |
320 | } | |
321 | ||
69e3fd8c | 322 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
323 | { |
324 | struct e1000_hw *hw = &adapter->hw; | |
325 | static int global_quad_port_a; /* global port a indication */ | |
326 | struct pci_dev *pdev = adapter->pdev; | |
327 | u16 eeprom_data = 0; | |
328 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; | |
329 | s32 rc; | |
330 | ||
331 | rc = e1000_init_mac_params_82571(adapter); | |
332 | if (rc) | |
333 | return rc; | |
334 | ||
335 | rc = e1000_init_nvm_params_82571(hw); | |
336 | if (rc) | |
337 | return rc; | |
338 | ||
339 | rc = e1000_init_phy_params_82571(hw); | |
340 | if (rc) | |
341 | return rc; | |
342 | ||
343 | /* tag quad port adapters first, it's used below */ | |
344 | switch (pdev->device) { | |
345 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
346 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
347 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 348 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
349 | adapter->flags |= FLAG_IS_QUAD_PORT; |
350 | /* mark the first port */ | |
351 | if (global_quad_port_a == 0) | |
352 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
353 | /* Reset for multiple quad port adapters */ | |
354 | global_quad_port_a++; | |
355 | if (global_quad_port_a == 4) | |
356 | global_quad_port_a = 0; | |
357 | break; | |
358 | default: | |
359 | break; | |
360 | } | |
361 | ||
362 | switch (adapter->hw.mac.type) { | |
363 | case e1000_82571: | |
364 | /* these dual ports don't have WoL on port B at all */ | |
365 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
366 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
367 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
368 | (is_port_b)) | |
369 | adapter->flags &= ~FLAG_HAS_WOL; | |
370 | /* quad ports only support WoL on port A */ | |
371 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 372 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 373 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
374 | /* Does not support WoL on any port */ |
375 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
376 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa AK |
377 | break; |
378 | ||
379 | case e1000_82573: | |
380 | if (pdev->device == E1000_DEV_ID_82573L) { | |
e243455d BA |
381 | if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, |
382 | &eeprom_data) < 0) | |
383 | break; | |
2adc55c9 BA |
384 | if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) { |
385 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; | |
386 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
387 | } | |
bc7f75fa AK |
388 | } |
389 | break; | |
390 | default: | |
391 | break; | |
392 | } | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | /** | |
398 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
399 | * @hw: pointer to the HW structure | |
400 | * | |
401 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
402 | * revision in the hardware structure. | |
403 | **/ | |
404 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
405 | { | |
406 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
407 | s32 ret_val; |
408 | u16 phy_id = 0; | |
bc7f75fa AK |
409 | |
410 | switch (hw->mac.type) { | |
411 | case e1000_82571: | |
412 | case e1000_82572: | |
ad68076e BA |
413 | /* |
414 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
415 | * In this case, we cannot access the PHY until the |
416 | * configuration is done. So we explicitly set the | |
ad68076e BA |
417 | * PHY ID. |
418 | */ | |
bc7f75fa AK |
419 | phy->id = IGP01E1000_I_PHY_ID; |
420 | break; | |
421 | case e1000_82573: | |
422 | return e1000e_get_phy_id(hw); | |
423 | break; | |
4662e82b | 424 | case e1000_82574: |
8c81c9c3 | 425 | case e1000_82583: |
4662e82b BA |
426 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
427 | if (ret_val) | |
428 | return ret_val; | |
429 | ||
430 | phy->id = (u32)(phy_id << 16); | |
431 | udelay(20); | |
432 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
433 | if (ret_val) | |
434 | return ret_val; | |
435 | ||
436 | phy->id |= (u32)(phy_id); | |
437 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
438 | break; | |
bc7f75fa AK |
439 | default: |
440 | return -E1000_ERR_PHY; | |
441 | break; | |
442 | } | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | /** | |
448 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
449 | * @hw: pointer to the HW structure | |
450 | * | |
451 | * Acquire the HW semaphore to access the PHY or NVM | |
452 | **/ | |
453 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
454 | { | |
455 | u32 swsm; | |
23a2d1b2 DG |
456 | s32 sw_timeout = hw->nvm.word_size + 1; |
457 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
458 | s32 i = 0; |
459 | ||
23a2d1b2 DG |
460 | /* |
461 | * If we have timedout 3 times on trying to acquire | |
462 | * the inter-port SMBI semaphore, there is old code | |
463 | * operating on the other port, and it is not | |
464 | * releasing SMBI. Modify the number of times that | |
465 | * we try for the semaphore to interwork with this | |
466 | * older code. | |
467 | */ | |
468 | if (hw->dev_spec.e82571.smb_counter > 2) | |
469 | sw_timeout = 1; | |
470 | ||
471 | /* Get the SW semaphore */ | |
472 | while (i < sw_timeout) { | |
473 | swsm = er32(SWSM); | |
474 | if (!(swsm & E1000_SWSM_SMBI)) | |
475 | break; | |
476 | ||
477 | udelay(50); | |
478 | i++; | |
479 | } | |
480 | ||
481 | if (i == sw_timeout) { | |
3bb99fe2 | 482 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
483 | hw->dev_spec.e82571.smb_counter++; |
484 | } | |
bc7f75fa | 485 | /* Get the FW semaphore. */ |
23a2d1b2 | 486 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
487 | swsm = er32(SWSM); |
488 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
489 | ||
490 | /* Semaphore acquired if bit latched */ | |
491 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
492 | break; | |
493 | ||
494 | udelay(50); | |
495 | } | |
496 | ||
23a2d1b2 | 497 | if (i == fw_timeout) { |
bc7f75fa | 498 | /* Release semaphores */ |
23a2d1b2 | 499 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 500 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
501 | return -E1000_ERR_NVM; |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | /** | |
508 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
509 | * @hw: pointer to the HW structure | |
510 | * | |
511 | * Release hardware semaphore used to access the PHY or NVM | |
512 | **/ | |
513 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
514 | { | |
515 | u32 swsm; | |
516 | ||
517 | swsm = er32(SWSM); | |
23a2d1b2 | 518 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
519 | ew32(SWSM, swsm); |
520 | } | |
521 | ||
522 | /** | |
523 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
524 | * @hw: pointer to the HW structure | |
525 | * | |
526 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
527 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
528 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
529 | * hardware semaphore. | |
530 | **/ | |
531 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
532 | { | |
533 | s32 ret_val; | |
534 | ||
535 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
536 | if (ret_val) | |
537 | return ret_val; | |
538 | ||
8c81c9c3 AD |
539 | switch (hw->mac.type) { |
540 | case e1000_82573: | |
541 | case e1000_82574: | |
542 | case e1000_82583: | |
543 | break; | |
544 | default: | |
bc7f75fa | 545 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
546 | break; |
547 | } | |
bc7f75fa AK |
548 | |
549 | if (ret_val) | |
550 | e1000_put_hw_semaphore_82571(hw); | |
551 | ||
552 | return ret_val; | |
553 | } | |
554 | ||
555 | /** | |
556 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
557 | * @hw: pointer to the HW structure | |
558 | * | |
559 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
560 | **/ | |
561 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
562 | { | |
563 | e1000e_release_nvm(hw); | |
564 | e1000_put_hw_semaphore_82571(hw); | |
565 | } | |
566 | ||
567 | /** | |
568 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
569 | * @hw: pointer to the HW structure | |
570 | * @offset: offset within the EEPROM to be written to | |
571 | * @words: number of words to write | |
572 | * @data: 16 bit word(s) to be written to the EEPROM | |
573 | * | |
574 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
575 | * | |
576 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 577 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
578 | **/ |
579 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
580 | u16 *data) | |
581 | { | |
582 | s32 ret_val; | |
583 | ||
584 | switch (hw->mac.type) { | |
585 | case e1000_82573: | |
4662e82b | 586 | case e1000_82574: |
8c81c9c3 | 587 | case e1000_82583: |
bc7f75fa AK |
588 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
589 | break; | |
590 | case e1000_82571: | |
591 | case e1000_82572: | |
592 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
593 | break; | |
594 | default: | |
595 | ret_val = -E1000_ERR_NVM; | |
596 | break; | |
597 | } | |
598 | ||
599 | return ret_val; | |
600 | } | |
601 | ||
602 | /** | |
603 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
604 | * @hw: pointer to the HW structure | |
605 | * | |
606 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
607 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
608 | * value to the EEPROM. | |
609 | **/ | |
610 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
611 | { | |
612 | u32 eecd; | |
613 | s32 ret_val; | |
614 | u16 i; | |
615 | ||
616 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
617 | if (ret_val) | |
618 | return ret_val; | |
619 | ||
ad68076e BA |
620 | /* |
621 | * If our nvm is an EEPROM, then we're done | |
622 | * otherwise, commit the checksum to the flash NVM. | |
623 | */ | |
bc7f75fa AK |
624 | if (hw->nvm.type != e1000_nvm_flash_hw) |
625 | return ret_val; | |
626 | ||
627 | /* Check for pending operations. */ | |
628 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
629 | msleep(1); | |
630 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
631 | break; | |
632 | } | |
633 | ||
634 | if (i == E1000_FLASH_UPDATES) | |
635 | return -E1000_ERR_NVM; | |
636 | ||
637 | /* Reset the firmware if using STM opcode. */ | |
638 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
639 | /* |
640 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
641 | * in two write cycles. |
642 | */ | |
643 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
644 | e1e_flush(); | |
645 | ew32(HICR, E1000_HICR_FW_RESET); | |
646 | } | |
647 | ||
648 | /* Commit the write to flash */ | |
649 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
650 | ew32(EECD, eecd); | |
651 | ||
652 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
653 | msleep(1); | |
654 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
655 | break; | |
656 | } | |
657 | ||
658 | if (i == E1000_FLASH_UPDATES) | |
659 | return -E1000_ERR_NVM; | |
660 | ||
661 | return 0; | |
662 | } | |
663 | ||
664 | /** | |
665 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
666 | * @hw: pointer to the HW structure | |
667 | * | |
668 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
669 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
670 | **/ | |
671 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
672 | { | |
673 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
674 | e1000_fix_nvm_checksum_82571(hw); | |
675 | ||
676 | return e1000e_validate_nvm_checksum_generic(hw); | |
677 | } | |
678 | ||
679 | /** | |
680 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
681 | * @hw: pointer to the HW structure | |
682 | * @offset: offset within the EEPROM to be written to | |
683 | * @words: number of words to write | |
684 | * @data: 16 bit word(s) to be written to the EEPROM | |
685 | * | |
686 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
687 | * command has completed before trying to write the next word. After write | |
688 | * poll for completion. | |
689 | * | |
690 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 691 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
692 | **/ |
693 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
694 | u16 words, u16 *data) | |
695 | { | |
696 | struct e1000_nvm_info *nvm = &hw->nvm; | |
a708dd88 | 697 | u32 i, eewr = 0; |
bc7f75fa AK |
698 | s32 ret_val = 0; |
699 | ||
ad68076e BA |
700 | /* |
701 | * A check for invalid values: offset too large, too many words, | |
702 | * and not enough words. | |
703 | */ | |
bc7f75fa AK |
704 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
705 | (words == 0)) { | |
3bb99fe2 | 706 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
707 | return -E1000_ERR_NVM; |
708 | } | |
709 | ||
710 | for (i = 0; i < words; i++) { | |
711 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
712 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
713 | E1000_NVM_RW_REG_START; | |
714 | ||
715 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
716 | if (ret_val) | |
717 | break; | |
718 | ||
719 | ew32(EEWR, eewr); | |
720 | ||
721 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
722 | if (ret_val) | |
723 | break; | |
724 | } | |
725 | ||
726 | return ret_val; | |
727 | } | |
728 | ||
729 | /** | |
730 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
731 | * @hw: pointer to the HW structure | |
732 | * | |
733 | * Reads the management control register for the config done bit to be set. | |
734 | **/ | |
735 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
736 | { | |
737 | s32 timeout = PHY_CFG_TIMEOUT; | |
738 | ||
739 | while (timeout) { | |
740 | if (er32(EEMNGCTL) & | |
741 | E1000_NVM_CFG_DONE_PORT_0) | |
742 | break; | |
743 | msleep(1); | |
744 | timeout--; | |
745 | } | |
746 | if (!timeout) { | |
3bb99fe2 | 747 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
748 | return -E1000_ERR_RESET; |
749 | } | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | /** | |
755 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
756 | * @hw: pointer to the HW structure | |
564ea9bb | 757 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
758 | * |
759 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
760 | * this function also disables smart speed and vice versa. LPLU will not be | |
761 | * activated unless the device autonegotiation advertisement meets standards | |
762 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
763 | * pointer entry point only called by PHY setup routines. | |
764 | **/ | |
765 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
766 | { | |
767 | struct e1000_phy_info *phy = &hw->phy; | |
768 | s32 ret_val; | |
769 | u16 data; | |
770 | ||
771 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
772 | if (ret_val) | |
773 | return ret_val; | |
774 | ||
775 | if (active) { | |
776 | data |= IGP02E1000_PM_D0_LPLU; | |
777 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
778 | if (ret_val) | |
779 | return ret_val; | |
780 | ||
781 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
782 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
783 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
784 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
785 | if (ret_val) | |
786 | return ret_val; | |
787 | } else { | |
788 | data &= ~IGP02E1000_PM_D0_LPLU; | |
789 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
790 | /* |
791 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
792 | * during Dx states where the power conservation is most |
793 | * important. During driver activity we should enable | |
ad68076e BA |
794 | * SmartSpeed, so performance is maintained. |
795 | */ | |
bc7f75fa AK |
796 | if (phy->smart_speed == e1000_smart_speed_on) { |
797 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 798 | &data); |
bc7f75fa AK |
799 | if (ret_val) |
800 | return ret_val; | |
801 | ||
802 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
803 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 804 | data); |
bc7f75fa AK |
805 | if (ret_val) |
806 | return ret_val; | |
807 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
808 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 809 | &data); |
bc7f75fa AK |
810 | if (ret_val) |
811 | return ret_val; | |
812 | ||
813 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
814 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 815 | data); |
bc7f75fa AK |
816 | if (ret_val) |
817 | return ret_val; | |
818 | } | |
819 | } | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
824 | /** | |
825 | * e1000_reset_hw_82571 - Reset hardware | |
826 | * @hw: pointer to the HW structure | |
827 | * | |
fe401674 | 828 | * This resets the hardware into a known state. |
bc7f75fa AK |
829 | **/ |
830 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
831 | { | |
a708dd88 | 832 | u32 ctrl, extcnf_ctrl, ctrl_ext, icr; |
bc7f75fa AK |
833 | s32 ret_val; |
834 | u16 i = 0; | |
835 | ||
ad68076e BA |
836 | /* |
837 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
838 | * on the last TLP read/write transaction when MAC is reset. |
839 | */ | |
840 | ret_val = e1000e_disable_pcie_master(hw); | |
841 | if (ret_val) | |
3bb99fe2 | 842 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 843 | |
3bb99fe2 | 844 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
845 | ew32(IMC, 0xffffffff); |
846 | ||
847 | ew32(RCTL, 0); | |
848 | ew32(TCTL, E1000_TCTL_PSP); | |
849 | e1e_flush(); | |
850 | ||
851 | msleep(10); | |
852 | ||
ad68076e BA |
853 | /* |
854 | * Must acquire the MDIO ownership before MAC reset. | |
855 | * Ownership defaults to firmware after a reset. | |
856 | */ | |
8c81c9c3 AD |
857 | switch (hw->mac.type) { |
858 | case e1000_82573: | |
859 | case e1000_82574: | |
860 | case e1000_82583: | |
bc7f75fa AK |
861 | extcnf_ctrl = er32(EXTCNF_CTRL); |
862 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
863 | ||
864 | do { | |
865 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
866 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
867 | ||
868 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
869 | break; | |
870 | ||
871 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
872 | ||
873 | msleep(2); | |
874 | i++; | |
875 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
8c81c9c3 AD |
876 | break; |
877 | default: | |
878 | break; | |
bc7f75fa AK |
879 | } |
880 | ||
881 | ctrl = er32(CTRL); | |
882 | ||
3bb99fe2 | 883 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
884 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
885 | ||
886 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
887 | udelay(10); | |
888 | ctrl_ext = er32(CTRL_EXT); | |
889 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
890 | ew32(CTRL_EXT, ctrl_ext); | |
891 | e1e_flush(); | |
892 | } | |
893 | ||
894 | ret_val = e1000e_get_auto_rd_done(hw); | |
895 | if (ret_val) | |
896 | /* We don't want to continue accessing MAC registers. */ | |
897 | return ret_val; | |
898 | ||
ad68076e BA |
899 | /* |
900 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
901 | * Need to wait for Phy configuration completion before accessing |
902 | * NVM and Phy. | |
903 | */ | |
8c81c9c3 AD |
904 | |
905 | switch (hw->mac.type) { | |
906 | case e1000_82573: | |
907 | case e1000_82574: | |
908 | case e1000_82583: | |
bc7f75fa | 909 | msleep(25); |
8c81c9c3 AD |
910 | break; |
911 | default: | |
912 | break; | |
913 | } | |
bc7f75fa AK |
914 | |
915 | /* Clear any pending interrupt events. */ | |
916 | ew32(IMC, 0xffffffff); | |
917 | icr = er32(ICR); | |
918 | ||
93ca1610 BH |
919 | if (hw->mac.type == e1000_82571 && |
920 | hw->dev_spec.e82571.alt_mac_addr_is_present) | |
921 | e1000e_set_laa_state_82571(hw, true); | |
922 | ||
c9523379 | 923 | /* Reinitialize the 82571 serdes link state machine */ |
924 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
925 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
926 | ||
bc7f75fa AK |
927 | return 0; |
928 | } | |
929 | ||
930 | /** | |
931 | * e1000_init_hw_82571 - Initialize hardware | |
932 | * @hw: pointer to the HW structure | |
933 | * | |
934 | * This inits the hardware readying it for operation. | |
935 | **/ | |
936 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
937 | { | |
938 | struct e1000_mac_info *mac = &hw->mac; | |
939 | u32 reg_data; | |
940 | s32 ret_val; | |
a708dd88 | 941 | u16 i, rar_count = mac->rar_entry_count; |
bc7f75fa AK |
942 | |
943 | e1000_initialize_hw_bits_82571(hw); | |
944 | ||
945 | /* Initialize identification LED */ | |
946 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 947 | if (ret_val) |
3bb99fe2 | 948 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 949 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
950 | |
951 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 952 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 953 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
954 | |
955 | /* Setup the receive address. */ | |
ad68076e BA |
956 | /* |
957 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
958 | * 82571, we must reserve a RAR for it to work around an issue where |
959 | * resetting one port will reload the MAC on the other port. | |
960 | */ | |
961 | if (e1000e_get_laa_state_82571(hw)) | |
962 | rar_count--; | |
963 | e1000e_init_rx_addrs(hw, rar_count); | |
964 | ||
965 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 966 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
967 | for (i = 0; i < mac->mta_reg_count; i++) |
968 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
969 | ||
970 | /* Setup link and flow control */ | |
971 | ret_val = e1000_setup_link_82571(hw); | |
972 | ||
973 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 974 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
975 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
976 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
977 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 978 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
979 | |
980 | /* ...for both queues. */ | |
8c81c9c3 AD |
981 | switch (mac->type) { |
982 | case e1000_82573: | |
983 | case e1000_82574: | |
984 | case e1000_82583: | |
985 | e1000e_enable_tx_pkt_filtering(hw); | |
986 | reg_data = er32(GCR); | |
987 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
988 | ew32(GCR, reg_data); | |
989 | break; | |
990 | default: | |
e9ec2c0f | 991 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
992 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
993 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
994 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 995 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 996 | break; |
bc7f75fa AK |
997 | } |
998 | ||
ad68076e BA |
999 | /* |
1000 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1001 | * important that we do this after we have tried to establish link |
1002 | * because the symbol error count will increment wildly if there | |
1003 | * is no link. | |
1004 | */ | |
1005 | e1000_clear_hw_cntrs_82571(hw); | |
1006 | ||
1007 | return ret_val; | |
1008 | } | |
1009 | ||
1010 | /** | |
1011 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1012 | * @hw: pointer to the HW structure | |
1013 | * | |
1014 | * Initializes required hardware-dependent bits needed for normal operation. | |
1015 | **/ | |
1016 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1017 | { | |
1018 | u32 reg; | |
1019 | ||
1020 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1021 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1022 | reg |= (1 << 22); |
e9ec2c0f | 1023 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1024 | |
1025 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1026 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1027 | reg |= (1 << 22); |
e9ec2c0f | 1028 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1029 | |
1030 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1031 | reg = er32(TARC(0)); |
bc7f75fa AK |
1032 | reg &= ~(0xF << 27); /* 30:27 */ |
1033 | switch (hw->mac.type) { | |
1034 | case e1000_82571: | |
1035 | case e1000_82572: | |
1036 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1037 | break; | |
1038 | default: | |
1039 | break; | |
1040 | } | |
e9ec2c0f | 1041 | ew32(TARC(0), reg); |
bc7f75fa AK |
1042 | |
1043 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1044 | reg = er32(TARC(1)); |
bc7f75fa AK |
1045 | switch (hw->mac.type) { |
1046 | case e1000_82571: | |
1047 | case e1000_82572: | |
1048 | reg &= ~((1 << 29) | (1 << 30)); | |
1049 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1050 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1051 | reg &= ~(1 << 28); | |
1052 | else | |
1053 | reg |= (1 << 28); | |
e9ec2c0f | 1054 | ew32(TARC(1), reg); |
bc7f75fa AK |
1055 | break; |
1056 | default: | |
1057 | break; | |
1058 | } | |
1059 | ||
1060 | /* Device Control */ | |
8c81c9c3 AD |
1061 | switch (hw->mac.type) { |
1062 | case e1000_82573: | |
1063 | case e1000_82574: | |
1064 | case e1000_82583: | |
bc7f75fa AK |
1065 | reg = er32(CTRL); |
1066 | reg &= ~(1 << 29); | |
1067 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1068 | break; |
1069 | default: | |
1070 | break; | |
bc7f75fa AK |
1071 | } |
1072 | ||
1073 | /* Extended Device Control */ | |
8c81c9c3 AD |
1074 | switch (hw->mac.type) { |
1075 | case e1000_82573: | |
1076 | case e1000_82574: | |
1077 | case e1000_82583: | |
bc7f75fa AK |
1078 | reg = er32(CTRL_EXT); |
1079 | reg &= ~(1 << 23); | |
1080 | reg |= (1 << 22); | |
1081 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1082 | break; |
1083 | default: | |
1084 | break; | |
bc7f75fa | 1085 | } |
4662e82b | 1086 | |
6ea7ae1d AD |
1087 | if (hw->mac.type == e1000_82571) { |
1088 | reg = er32(PBA_ECC); | |
1089 | reg |= E1000_PBA_ECC_CORR_EN; | |
1090 | ew32(PBA_ECC, reg); | |
1091 | } | |
5df3f0ea | 1092 | /* |
1093 | * Workaround for hardware errata. | |
1094 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1095 | */ | |
1096 | ||
1097 | if ((hw->mac.type == e1000_82571) || | |
1098 | (hw->mac.type == e1000_82572)) { | |
1099 | reg = er32(CTRL_EXT); | |
1100 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1101 | ew32(CTRL_EXT, reg); | |
1102 | } | |
1103 | ||
6ea7ae1d | 1104 | |
78272bba | 1105 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1106 | switch (hw->mac.type) { |
1107 | case e1000_82574: | |
1108 | case e1000_82583: | |
4662e82b BA |
1109 | reg = er32(GCR); |
1110 | reg |= (1 << 22); | |
1111 | ew32(GCR, reg); | |
78272bba | 1112 | |
84efb7b9 BA |
1113 | /* |
1114 | * Workaround for hardware errata. | |
1115 | * apply workaround for hardware errata documented in errata | |
1116 | * docs Fixes issue where some error prone or unreliable PCIe | |
1117 | * completions are occurring, particularly with ASPM enabled. | |
1118 | * Without fix, issue can cause tx timeouts. | |
1119 | */ | |
78272bba JB |
1120 | reg = er32(GCR2); |
1121 | reg |= 1; | |
1122 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1123 | break; |
1124 | default: | |
1125 | break; | |
4662e82b BA |
1126 | } |
1127 | ||
1128 | return; | |
bc7f75fa AK |
1129 | } |
1130 | ||
1131 | /** | |
caaddaf8 | 1132 | * e1000_clear_vfta_82571 - Clear VLAN filter table |
bc7f75fa AK |
1133 | * @hw: pointer to the HW structure |
1134 | * | |
1135 | * Clears the register array which contains the VLAN filter table by | |
1136 | * setting all the values to 0. | |
1137 | **/ | |
caaddaf8 | 1138 | static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
bc7f75fa AK |
1139 | { |
1140 | u32 offset; | |
1141 | u32 vfta_value = 0; | |
1142 | u32 vfta_offset = 0; | |
1143 | u32 vfta_bit_in_reg = 0; | |
1144 | ||
8c81c9c3 AD |
1145 | switch (hw->mac.type) { |
1146 | case e1000_82573: | |
1147 | case e1000_82574: | |
1148 | case e1000_82583: | |
bc7f75fa | 1149 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1150 | /* |
1151 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1152 | * a single VLAN ID. The following operations |
1153 | * determine which 32b entry (i.e. offset) into the | |
1154 | * array we want to set the VLAN ID (i.e. bit) of | |
1155 | * the manageability unit. | |
1156 | */ | |
1157 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1158 | E1000_VFTA_ENTRY_SHIFT) & | |
1159 | E1000_VFTA_ENTRY_MASK; | |
1160 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1161 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1162 | } | |
8c81c9c3 AD |
1163 | break; |
1164 | default: | |
1165 | break; | |
bc7f75fa AK |
1166 | } |
1167 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1168 | /* |
1169 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1170 | * manageability VLAN ID, then clear all bits except that of |
1171 | * the manageability unit. | |
1172 | */ | |
1173 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1174 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1175 | e1e_flush(); | |
1176 | } | |
1177 | } | |
1178 | ||
4662e82b BA |
1179 | /** |
1180 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1181 | * @hw: pointer to the HW structure | |
1182 | * | |
1183 | * Reads the NVM Initialization Control Word 2 and returns true | |
1184 | * (>0) if any manageability is enabled, else false (0). | |
1185 | **/ | |
1186 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1187 | { | |
1188 | u16 data; | |
1189 | ||
1190 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1191 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1192 | } | |
1193 | ||
1194 | /** | |
1195 | * e1000_led_on_82574 - Turn LED on | |
1196 | * @hw: pointer to the HW structure | |
1197 | * | |
1198 | * Turn LED on. | |
1199 | **/ | |
1200 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1201 | { | |
1202 | u32 ctrl; | |
1203 | u32 i; | |
1204 | ||
1205 | ctrl = hw->mac.ledctl_mode2; | |
1206 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1207 | /* | |
1208 | * If no link, then turn LED on by setting the invert bit | |
1209 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1210 | */ | |
1211 | for (i = 0; i < 4; i++) | |
1212 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1213 | E1000_LEDCTL_MODE_LED_ON) | |
1214 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1215 | } | |
1216 | ew32(LEDCTL, ctrl); | |
1217 | ||
1218 | return 0; | |
1219 | } | |
1220 | ||
bc7f75fa | 1221 | /** |
e2de3eb6 | 1222 | * e1000_update_mc_addr_list_82571 - Update Multicast addresses |
bc7f75fa AK |
1223 | * @hw: pointer to the HW structure |
1224 | * @mc_addr_list: array of multicast addresses to program | |
1225 | * @mc_addr_count: number of multicast addresses to program | |
1226 | * @rar_used_count: the first RAR register free to program | |
1227 | * @rar_count: total number of supported Receive Address Registers | |
1228 | * | |
1229 | * Updates the Receive Address Registers and Multicast Table Array. | |
1230 | * The caller must have a packed mc_addr_list of multicast addresses. | |
1231 | * The parameter rar_count will usually be hw->mac.rar_entry_count | |
1232 | * unless there are workarounds that change this. | |
1233 | **/ | |
e2de3eb6 | 1234 | static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, |
bc7f75fa AK |
1235 | u8 *mc_addr_list, |
1236 | u32 mc_addr_count, | |
1237 | u32 rar_used_count, | |
1238 | u32 rar_count) | |
1239 | { | |
1240 | if (e1000e_get_laa_state_82571(hw)) | |
1241 | rar_count--; | |
1242 | ||
e2de3eb6 JK |
1243 | e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, |
1244 | rar_used_count, rar_count); | |
bc7f75fa AK |
1245 | } |
1246 | ||
1247 | /** | |
1248 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1249 | * @hw: pointer to the HW structure | |
1250 | * | |
1251 | * Determines which flow control settings to use, then configures flow | |
1252 | * control. Calls the appropriate media-specific link configuration | |
1253 | * function. Assuming the adapter has a valid link partner, a valid link | |
1254 | * should be established. Assumes the hardware has previously been reset | |
1255 | * and the transmitter and receiver are not enabled. | |
1256 | **/ | |
1257 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1258 | { | |
ad68076e BA |
1259 | /* |
1260 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1261 | * the default flow control setting, so we explicitly |
1262 | * set it to full. | |
1263 | */ | |
8c81c9c3 AD |
1264 | switch (hw->mac.type) { |
1265 | case e1000_82573: | |
1266 | case e1000_82574: | |
1267 | case e1000_82583: | |
1268 | if (hw->fc.requested_mode == e1000_fc_default) | |
1269 | hw->fc.requested_mode = e1000_fc_full; | |
1270 | break; | |
1271 | default: | |
1272 | break; | |
1273 | } | |
bc7f75fa AK |
1274 | |
1275 | return e1000e_setup_link(hw); | |
1276 | } | |
1277 | ||
1278 | /** | |
1279 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1280 | * @hw: pointer to the HW structure | |
1281 | * | |
1282 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1283 | * for link, once link is established calls to configure collision distance | |
1284 | * and flow control are called. | |
1285 | **/ | |
1286 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1287 | { | |
1288 | u32 ctrl; | |
1289 | u32 led_ctrl; | |
1290 | s32 ret_val; | |
1291 | ||
1292 | ctrl = er32(CTRL); | |
1293 | ctrl |= E1000_CTRL_SLU; | |
1294 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1295 | ew32(CTRL, ctrl); | |
1296 | ||
1297 | switch (hw->phy.type) { | |
1298 | case e1000_phy_m88: | |
4662e82b | 1299 | case e1000_phy_bm: |
bc7f75fa AK |
1300 | ret_val = e1000e_copper_link_setup_m88(hw); |
1301 | break; | |
1302 | case e1000_phy_igp_2: | |
1303 | ret_val = e1000e_copper_link_setup_igp(hw); | |
1304 | /* Setup activity LED */ | |
1305 | led_ctrl = er32(LEDCTL); | |
1306 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1307 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1308 | ew32(LEDCTL, led_ctrl); | |
1309 | break; | |
1310 | default: | |
1311 | return -E1000_ERR_PHY; | |
1312 | break; | |
1313 | } | |
1314 | ||
1315 | if (ret_val) | |
1316 | return ret_val; | |
1317 | ||
1318 | ret_val = e1000e_setup_copper_link(hw); | |
1319 | ||
1320 | return ret_val; | |
1321 | } | |
1322 | ||
1323 | /** | |
1324 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1325 | * @hw: pointer to the HW structure | |
1326 | * | |
1327 | * Configures collision distance and flow control for fiber and serdes links. | |
1328 | * Upon successful setup, poll for link. | |
1329 | **/ | |
1330 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1331 | { | |
1332 | switch (hw->mac.type) { | |
1333 | case e1000_82571: | |
1334 | case e1000_82572: | |
ad68076e BA |
1335 | /* |
1336 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1337 | * of reset to take the adapter out of that mode. So we |
1338 | * have to explicitly take the adapter out of loopback | |
489815ce | 1339 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1340 | * if another tool failed to take it out of loopback mode. |
1341 | */ | |
ad68076e | 1342 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1343 | break; |
1344 | default: | |
1345 | break; | |
1346 | } | |
1347 | ||
1348 | return e1000e_setup_fiber_serdes_link(hw); | |
1349 | } | |
1350 | ||
c9523379 | 1351 | /** |
1352 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1353 | * @hw: pointer to the HW structure | |
1354 | * | |
1355 | * Checks for link up on the hardware. If link is not up and we have | |
1356 | * a signal, then we need to force link up. | |
1357 | **/ | |
f6370117 | 1358 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1359 | { |
1360 | struct e1000_mac_info *mac = &hw->mac; | |
1361 | u32 rxcw; | |
1362 | u32 ctrl; | |
1363 | u32 status; | |
1364 | s32 ret_val = 0; | |
1365 | ||
1366 | ctrl = er32(CTRL); | |
1367 | status = er32(STATUS); | |
1368 | rxcw = er32(RXCW); | |
1369 | ||
1370 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1371 | ||
1372 | /* Receiver is synchronized with no invalid bits. */ | |
1373 | switch (mac->serdes_link_state) { | |
1374 | case e1000_serdes_link_autoneg_complete: | |
1375 | if (!(status & E1000_STATUS_LU)) { | |
1376 | /* | |
1377 | * We have lost link, retry autoneg before | |
1378 | * reporting link failure | |
1379 | */ | |
1380 | mac->serdes_link_state = | |
1381 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1382 | e_dbg("AN_UP -> AN_PROG\n"); |
c9523379 | 1383 | } |
1384 | break; | |
1385 | ||
1386 | case e1000_serdes_link_forced_up: | |
1387 | /* | |
1388 | * If we are receiving /C/ ordered sets, re-enable | |
1389 | * auto-negotiation in the TXCW register and disable | |
1390 | * forced link in the Device Control register in an | |
1391 | * attempt to auto-negotiate with our link partner. | |
1392 | */ | |
1393 | if (rxcw & E1000_RXCW_C) { | |
1394 | /* Enable autoneg, and unforce link up */ | |
1395 | ew32(TXCW, mac->txcw); | |
1396 | ew32(CTRL, | |
1397 | (ctrl & ~E1000_CTRL_SLU)); | |
1398 | mac->serdes_link_state = | |
1399 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1400 | e_dbg("FORCED_UP -> AN_PROG\n"); |
c9523379 | 1401 | } |
1402 | break; | |
1403 | ||
1404 | case e1000_serdes_link_autoneg_progress: | |
1405 | /* | |
1406 | * If the LU bit is set in the STATUS register, | |
1407 | * autoneg has completed sucessfully. If not, | |
1408 | * try foring the link because the far end may be | |
1409 | * available but not capable of autonegotiation. | |
1410 | */ | |
1411 | if (status & E1000_STATUS_LU) { | |
1412 | mac->serdes_link_state = | |
1413 | e1000_serdes_link_autoneg_complete; | |
3bb99fe2 | 1414 | e_dbg("AN_PROG -> AN_UP\n"); |
c9523379 | 1415 | } else { |
1416 | /* | |
1417 | * Disable autoneg, force link up and | |
1418 | * full duplex, and change state to forced | |
1419 | */ | |
1420 | ew32(TXCW, | |
1421 | (mac->txcw & ~E1000_TXCW_ANE)); | |
1422 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
1423 | ew32(CTRL, ctrl); | |
1424 | ||
1425 | /* Configure Flow Control after link up. */ | |
1426 | ret_val = | |
1427 | e1000e_config_fc_after_link_up(hw); | |
1428 | if (ret_val) { | |
3bb99fe2 | 1429 | e_dbg("Error config flow control\n"); |
c9523379 | 1430 | break; |
1431 | } | |
1432 | mac->serdes_link_state = | |
1433 | e1000_serdes_link_forced_up; | |
3bb99fe2 | 1434 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1435 | } |
1436 | mac->serdes_has_link = true; | |
1437 | break; | |
1438 | ||
1439 | case e1000_serdes_link_down: | |
1440 | default: | |
1441 | /* The link was down but the receiver has now gained | |
1442 | * valid sync, so lets see if we can bring the link | |
1443 | * up. */ | |
1444 | ew32(TXCW, mac->txcw); | |
1445 | ew32(CTRL, | |
1446 | (ctrl & ~E1000_CTRL_SLU)); | |
1447 | mac->serdes_link_state = | |
1448 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1449 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1450 | break; |
1451 | } | |
1452 | } else { | |
1453 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1454 | mac->serdes_has_link = false; | |
1455 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1456 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1457 | } else { |
1458 | /* | |
1459 | * We have sync, and can tolerate one | |
1460 | * invalid (IV) codeword before declaring | |
1461 | * link down, so reread to look again | |
1462 | */ | |
1463 | udelay(10); | |
1464 | rxcw = er32(RXCW); | |
1465 | if (rxcw & E1000_RXCW_IV) { | |
1466 | mac->serdes_link_state = e1000_serdes_link_down; | |
1467 | mac->serdes_has_link = false; | |
3bb99fe2 | 1468 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1469 | } |
1470 | } | |
1471 | } | |
1472 | ||
1473 | return ret_val; | |
1474 | } | |
1475 | ||
bc7f75fa AK |
1476 | /** |
1477 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1478 | * @hw: pointer to the HW structure | |
1479 | * @data: pointer to the NVM (EEPROM) | |
1480 | * | |
1481 | * Read the EEPROM for the current default LED configuration. If the | |
1482 | * LED configuration is not valid, set to a valid LED configuration. | |
1483 | **/ | |
1484 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1485 | { | |
1486 | s32 ret_val; | |
1487 | ||
1488 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1489 | if (ret_val) { | |
3bb99fe2 | 1490 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1491 | return ret_val; |
1492 | } | |
1493 | ||
8c81c9c3 AD |
1494 | switch (hw->mac.type) { |
1495 | case e1000_82573: | |
1496 | case e1000_82574: | |
1497 | case e1000_82583: | |
1498 | if (*data == ID_LED_RESERVED_F746) | |
1499 | *data = ID_LED_DEFAULT_82573; | |
1500 | break; | |
1501 | default: | |
1502 | if (*data == ID_LED_RESERVED_0000 || | |
1503 | *data == ID_LED_RESERVED_FFFF) | |
1504 | *data = ID_LED_DEFAULT; | |
1505 | break; | |
1506 | } | |
bc7f75fa AK |
1507 | |
1508 | return 0; | |
1509 | } | |
1510 | ||
1511 | /** | |
1512 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1513 | * @hw: pointer to the HW structure | |
1514 | * | |
489815ce | 1515 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1516 | **/ |
1517 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1518 | { | |
1519 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1520 | return false; |
bc7f75fa AK |
1521 | |
1522 | return hw->dev_spec.e82571.laa_is_present; | |
1523 | } | |
1524 | ||
1525 | /** | |
1526 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1527 | * @hw: pointer to the HW structure | |
1528 | * @state: enable/disable locally administered address | |
1529 | * | |
489815ce | 1530 | * Enable/Disable the current locally administers address state. |
bc7f75fa AK |
1531 | **/ |
1532 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1533 | { | |
1534 | if (hw->mac.type != e1000_82571) | |
1535 | return; | |
1536 | ||
1537 | hw->dev_spec.e82571.laa_is_present = state; | |
1538 | ||
1539 | /* If workaround is activated... */ | |
1540 | if (state) | |
ad68076e BA |
1541 | /* |
1542 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1543 | * between the time RAR[0] gets clobbered and the time it |
1544 | * gets fixed, the actual LAA is in one of the RARs and no | |
1545 | * incoming packets directed to this port are dropped. | |
1546 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1547 | */ | |
1548 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1549 | } | |
1550 | ||
1551 | /** | |
1552 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1553 | * @hw: pointer to the HW structure | |
1554 | * | |
1555 | * Verifies that the EEPROM has completed the update. After updating the | |
1556 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1557 | * the checksum fix is not implemented, we need to set the bit and update | |
1558 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1559 | * we need to return bad checksum. | |
1560 | **/ | |
1561 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1562 | { | |
1563 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1564 | s32 ret_val; | |
1565 | u16 data; | |
1566 | ||
1567 | if (nvm->type != e1000_nvm_flash_hw) | |
1568 | return 0; | |
1569 | ||
ad68076e BA |
1570 | /* |
1571 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1572 | * 10h-12h. Checksum may need to be fixed. |
1573 | */ | |
1574 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1575 | if (ret_val) | |
1576 | return ret_val; | |
1577 | ||
1578 | if (!(data & 0x10)) { | |
ad68076e BA |
1579 | /* |
1580 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1581 | * when the checksum has already been fixed. If |
1582 | * the checksum is still wrong and this bit is a | |
1583 | * 1, we need to return bad checksum. Otherwise, | |
1584 | * we need to set this bit to a 1 and update the | |
1585 | * checksum. | |
1586 | */ | |
1587 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1588 | if (ret_val) | |
1589 | return ret_val; | |
1590 | ||
1591 | if (!(data & 0x8000)) { | |
1592 | data |= 0x8000; | |
1593 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1594 | if (ret_val) | |
1595 | return ret_val; | |
1596 | ret_val = e1000e_update_nvm_checksum(hw); | |
1597 | } | |
1598 | } | |
1599 | ||
1600 | return 0; | |
1601 | } | |
1602 | ||
1603 | /** | |
1604 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1605 | * @hw: pointer to the HW structure | |
1606 | * | |
1607 | * Clears the hardware counters by reading the counter registers. | |
1608 | **/ | |
1609 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1610 | { | |
bc7f75fa AK |
1611 | e1000e_clear_hw_cntrs_base(hw); |
1612 | ||
99673d9b BA |
1613 | er32(PRC64); |
1614 | er32(PRC127); | |
1615 | er32(PRC255); | |
1616 | er32(PRC511); | |
1617 | er32(PRC1023); | |
1618 | er32(PRC1522); | |
1619 | er32(PTC64); | |
1620 | er32(PTC127); | |
1621 | er32(PTC255); | |
1622 | er32(PTC511); | |
1623 | er32(PTC1023); | |
1624 | er32(PTC1522); | |
1625 | ||
1626 | er32(ALGNERRC); | |
1627 | er32(RXERRC); | |
1628 | er32(TNCRS); | |
1629 | er32(CEXTERR); | |
1630 | er32(TSCTC); | |
1631 | er32(TSCTFC); | |
1632 | ||
1633 | er32(MGTPRC); | |
1634 | er32(MGTPDC); | |
1635 | er32(MGTPTC); | |
1636 | ||
1637 | er32(IAC); | |
1638 | er32(ICRXOC); | |
1639 | ||
1640 | er32(ICRXPTC); | |
1641 | er32(ICRXATC); | |
1642 | er32(ICTXPTC); | |
1643 | er32(ICTXATC); | |
1644 | er32(ICTXQEC); | |
1645 | er32(ICTXQMTC); | |
1646 | er32(ICRXDMTC); | |
bc7f75fa AK |
1647 | } |
1648 | ||
1649 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1650 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1651 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1652 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1653 | .cleanup_led = e1000e_cleanup_led_generic, |
1654 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1655 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1656 | /* .get_link_up_info: media type dependent */ | |
4662e82b | 1657 | /* .led_on: mac type dependent */ |
bc7f75fa | 1658 | .led_off = e1000e_led_off_generic, |
e2de3eb6 | 1659 | .update_mc_addr_list = e1000_update_mc_addr_list_82571, |
caaddaf8 BA |
1660 | .write_vfta = e1000_write_vfta_generic, |
1661 | .clear_vfta = e1000_clear_vfta_82571, | |
bc7f75fa AK |
1662 | .reset_hw = e1000_reset_hw_82571, |
1663 | .init_hw = e1000_init_hw_82571, | |
1664 | .setup_link = e1000_setup_link_82571, | |
1665 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1666 | .setup_led = e1000e_setup_led_generic, |
bc7f75fa AK |
1667 | }; |
1668 | ||
1669 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
94d8186a | 1670 | .acquire = e1000_get_hw_semaphore_82571, |
bc7f75fa | 1671 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1672 | .commit = NULL, |
bc7f75fa AK |
1673 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1674 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1675 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1676 | .get_info = e1000e_get_phy_info_igp, |
1677 | .read_reg = e1000e_read_phy_reg_igp, | |
1678 | .release = e1000_put_hw_semaphore_82571, | |
1679 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1680 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1681 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1682 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1683 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1684 | }; |
1685 | ||
1686 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
94d8186a | 1687 | .acquire = e1000_get_hw_semaphore_82571, |
bc7f75fa | 1688 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1689 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1690 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1691 | .get_cfg_done = e1000e_get_cfg_done, | |
1692 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1693 | .get_info = e1000e_get_phy_info_m88, |
1694 | .read_reg = e1000e_read_phy_reg_m88, | |
1695 | .release = e1000_put_hw_semaphore_82571, | |
1696 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1697 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1698 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1699 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1700 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1701 | }; |
1702 | ||
4662e82b | 1703 | static struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1704 | .acquire = e1000_get_hw_semaphore_82571, |
4662e82b | 1705 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1706 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1707 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1708 | .get_cfg_done = e1000e_get_cfg_done, | |
1709 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1710 | .get_info = e1000e_get_phy_info_m88, |
1711 | .read_reg = e1000e_read_phy_reg_bm2, | |
1712 | .release = e1000_put_hw_semaphore_82571, | |
1713 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1714 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1715 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1716 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1717 | .cfg_on_link_up = NULL, |
4662e82b BA |
1718 | }; |
1719 | ||
bc7f75fa | 1720 | static struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1721 | .acquire = e1000_acquire_nvm_82571, |
1722 | .read = e1000e_read_nvm_eerd, | |
1723 | .release = e1000_release_nvm_82571, | |
1724 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1725 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1726 | .validate = e1000_validate_nvm_checksum_82571, |
1727 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1728 | }; |
1729 | ||
1730 | struct e1000_info e1000_82571_info = { | |
1731 | .mac = e1000_82571, | |
1732 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1733 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1734 | | FLAG_HAS_WOL |
1735 | | FLAG_APME_IN_CTRL3 | |
1736 | | FLAG_RX_CSUM_ENABLED | |
1737 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1738 | | FLAG_HAS_SMART_POWER_DOWN |
1739 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1740 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1741 | | FLAG_APME_CHECK_PORT_B, | |
1742 | .pba = 38, | |
2adc55c9 | 1743 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1744 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1745 | .mac_ops = &e82571_mac_ops, |
1746 | .phy_ops = &e82_phy_ops_igp, | |
1747 | .nvm_ops = &e82571_nvm_ops, | |
1748 | }; | |
1749 | ||
1750 | struct e1000_info e1000_82572_info = { | |
1751 | .mac = e1000_82572, | |
1752 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1753 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1754 | | FLAG_HAS_WOL |
1755 | | FLAG_APME_IN_CTRL3 | |
1756 | | FLAG_RX_CSUM_ENABLED | |
1757 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1758 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
1759 | .pba = 38, | |
2adc55c9 | 1760 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1761 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1762 | .mac_ops = &e82571_mac_ops, |
1763 | .phy_ops = &e82_phy_ops_igp, | |
1764 | .nvm_ops = &e82571_nvm_ops, | |
1765 | }; | |
1766 | ||
1767 | struct e1000_info e1000_82573_info = { | |
1768 | .mac = e1000_82573, | |
1769 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1770 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1771 | | FLAG_HAS_WOL |
1772 | | FLAG_APME_IN_CTRL3 | |
1773 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
1774 | | FLAG_HAS_SMART_POWER_DOWN |
1775 | | FLAG_HAS_AMT | |
bc7f75fa AK |
1776 | | FLAG_HAS_ERT |
1777 | | FLAG_HAS_SWSM_ON_LOAD, | |
1778 | .pba = 20, | |
2adc55c9 | 1779 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 1780 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1781 | .mac_ops = &e82571_mac_ops, |
1782 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1783 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1784 | }; |
1785 | ||
4662e82b BA |
1786 | struct e1000_info e1000_82574_info = { |
1787 | .mac = e1000_82574, | |
1788 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1789 | | FLAG_HAS_MSIX | |
1790 | | FLAG_HAS_JUMBO_FRAMES | |
1791 | | FLAG_HAS_WOL | |
1792 | | FLAG_APME_IN_CTRL3 | |
1793 | | FLAG_RX_CSUM_ENABLED | |
1794 | | FLAG_HAS_SMART_POWER_DOWN | |
1795 | | FLAG_HAS_AMT | |
1796 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1797 | .pba = 20, | |
a825e00c | 1798 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
1799 | .get_variants = e1000_get_variants_82571, |
1800 | .mac_ops = &e82571_mac_ops, | |
1801 | .phy_ops = &e82_phy_ops_bm, | |
1802 | .nvm_ops = &e82571_nvm_ops, | |
1803 | }; | |
1804 | ||
8c81c9c3 AD |
1805 | struct e1000_info e1000_82583_info = { |
1806 | .mac = e1000_82583, | |
1807 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1808 | | FLAG_HAS_WOL | |
1809 | | FLAG_APME_IN_CTRL3 | |
1810 | | FLAG_RX_CSUM_ENABLED | |
1811 | | FLAG_HAS_SMART_POWER_DOWN | |
1812 | | FLAG_HAS_AMT | |
1813 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1814 | .pba = 20, | |
a825e00c | 1815 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
8c81c9c3 AD |
1816 | .get_variants = e1000_get_variants_82571, |
1817 | .mac_ops = &e82571_mac_ops, | |
1818 | .phy_ops = &e82_phy_ops_bm, | |
1819 | .nvm_ops = &e82571_nvm_ops, | |
1820 | }; | |
1821 |