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e1000: Esb2 wol link cycle bug and uninitialized registers
[net-next-2.6.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
0f15a8fa
JK		 32 * 7.0.33 3-Feb-2006
33 * o Added another fix for the pass false carrier bit
34 * 7.0.32 24-Jan-2006
35 * o Need to rebuild with noew version number for the pass false carrier
36 * fix in e1000_hw.c
37 * 7.0.30 18-Jan-2006
38 * o fixup for tso workaround to disable it for pci-x
39 * o fix mem leak on 82542
40 * o fixes for 10 Mb/s connections and incorrect stats
41 * 7.0.28 01/06/2006
42 * o hardware workaround to only set "speed mode" bit for 1G link.
43 * 7.0.26 12/23/2005
44 * o wake on lan support modified for device ID 10B5
45 * o fix dhcp + vlan issue not making it to the iAMT firmware
46 * 7.0.24 12/9/2005
47 * o New hardware support for the Gigabit NIC embedded in the south bridge
48 * o Fixes to the recycling logic (skb->tail) from IBM LTC
73629bbc
JB		 49 * 6.3.9 12/16/2005
50 * o incorporate fix for recycled skbs from IBM LTC
51 * 6.3.7 11/18/2005
52 * o Honor eeprom setting for enabling/disabling Wake On Lan
53 * 6.3.5 11/17/2005
54 * o Fix memory leak in rx ring handling for PCI Express adapters
55 * 6.3.4 11/8/05
56 * o Patch from Jesper Juhl to remove redundant NULL checks for kfree
57 * 6.3.2 9/20/05
58 * o Render logic that sets/resets DRV_LOAD as inline functions to
59 * avoid code replication. If f/w is AMT then set DRV_LOAD only when
60 * network interface is open.
61 * o Handle DRV_LOAD set/reset in cases where AMT uses VLANs.
62 * o Adjust PBA partioning for Jumbo frames using MTU size and not
63 * rx_buffer_len
64 * 6.3.1 9/19/05
65 * o Use adapter->tx_timeout_factor in Tx Hung Detect logic
0f15a8fa 66 * (e1000_clean_tx_irq)
73629bbc 67 * o Support for 8086:10B5 device (Quad Port)
1da177e4
LT		 68 */
69
70char e1000_driver_name[] = "e1000";
3ad2cc67 71static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 72#ifndef CONFIG_E1000_NAPI
73#define DRIVERNAPI
74#else
75#define DRIVERNAPI "-NAPI"
76#endif
c1605eb3 77#define DRV_VERSION "7.0.33-k2"DRIVERNAPI
1da177e4 78char e1000_driver_version[] = DRV_VERSION;
3ad2cc67 79static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 80
81/* e1000_pci_tbl - PCI Device ID Table
82 *
83 * Last entry must be all 0s
84 *
85 * Macro expands to...
86 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
87 */
88static struct pci_device_id e1000_pci_tbl[] = {
89 INTEL_E1000_ETHERNET_DEVICE(0x1000),
90 INTEL_E1000_ETHERNET_DEVICE(0x1001),
91 INTEL_E1000_ETHERNET_DEVICE(0x1004),
92 INTEL_E1000_ETHERNET_DEVICE(0x1008),
93 INTEL_E1000_ETHERNET_DEVICE(0x1009),
94 INTEL_E1000_ETHERNET_DEVICE(0x100C),
95 INTEL_E1000_ETHERNET_DEVICE(0x100D),
96 INTEL_E1000_ETHERNET_DEVICE(0x100E),
97 INTEL_E1000_ETHERNET_DEVICE(0x100F),
98 INTEL_E1000_ETHERNET_DEVICE(0x1010),
99 INTEL_E1000_ETHERNET_DEVICE(0x1011),
100 INTEL_E1000_ETHERNET_DEVICE(0x1012),
101 INTEL_E1000_ETHERNET_DEVICE(0x1013),
102 INTEL_E1000_ETHERNET_DEVICE(0x1014),
103 INTEL_E1000_ETHERNET_DEVICE(0x1015),
104 INTEL_E1000_ETHERNET_DEVICE(0x1016),
105 INTEL_E1000_ETHERNET_DEVICE(0x1017),
106 INTEL_E1000_ETHERNET_DEVICE(0x1018),
107 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 108 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 109 INTEL_E1000_ETHERNET_DEVICE(0x101D),
110 INTEL_E1000_ETHERNET_DEVICE(0x101E),
111 INTEL_E1000_ETHERNET_DEVICE(0x1026),
112 INTEL_E1000_ETHERNET_DEVICE(0x1027),
113 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 114 INTEL_E1000_ETHERNET_DEVICE(0x105E),
115 INTEL_E1000_ETHERNET_DEVICE(0x105F),
116 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 117 INTEL_E1000_ETHERNET_DEVICE(0x1075),
118 INTEL_E1000_ETHERNET_DEVICE(0x1076),
119 INTEL_E1000_ETHERNET_DEVICE(0x1077),
120 INTEL_E1000_ETHERNET_DEVICE(0x1078),
121 INTEL_E1000_ETHERNET_DEVICE(0x1079),
122 INTEL_E1000_ETHERNET_DEVICE(0x107A),
123 INTEL_E1000_ETHERNET_DEVICE(0x107B),
124 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 125 INTEL_E1000_ETHERNET_DEVICE(0x107D),
126 INTEL_E1000_ETHERNET_DEVICE(0x107E),
127 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 128 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 129 INTEL_E1000_ETHERNET_DEVICE(0x108B),
130 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 131 INTEL_E1000_ETHERNET_DEVICE(0x1096),
132 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 133 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 134 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 135 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 136 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
1da177e4
LT		 137 /* required last entry */
138 {0,}
139};
140
141MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
142
3ad2cc67 143static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 144 struct e1000_tx_ring *txdr);
3ad2cc67 145static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 146 struct e1000_rx_ring *rxdr);
3ad2cc67 147static void e1000_free_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 148 struct e1000_tx_ring *tx_ring);
3ad2cc67 149static void e1000_free_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 150 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 151
152/* Local Function Prototypes */
153
154static int e1000_init_module(void);
155static void e1000_exit_module(void);
156static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
157static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 158static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 159static int e1000_sw_init(struct e1000_adapter *adapter);
160static int e1000_open(struct net_device *netdev);
161static int e1000_close(struct net_device *netdev);
162static void e1000_configure_tx(struct e1000_adapter *adapter);
163static void e1000_configure_rx(struct e1000_adapter *adapter);
164static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 165static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
166static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
167static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
168 struct e1000_tx_ring *tx_ring);
169static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
170 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 171static void e1000_set_multi(struct net_device *netdev);
172static void e1000_update_phy_info(unsigned long data);
173static void e1000_watchdog(unsigned long data);
174static void e1000_watchdog_task(struct e1000_adapter *adapter);
175static void e1000_82547_tx_fifo_stall(unsigned long data);
176static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
177static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
178static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
179static int e1000_set_mac(struct net_device *netdev, void *p);
180static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 181static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
182 struct e1000_tx_ring *tx_ring);
1da177e4 183#ifdef CONFIG_E1000_NAPI
581d708e 184static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 185static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 186 struct e1000_rx_ring *rx_ring,
1da177e4 187 int *work_done, int work_to_do);
2d7edb92 188static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 189 struct e1000_rx_ring *rx_ring,
2d7edb92 190 int *work_done, int work_to_do);
1da177e4 191#else
581d708e
MC		 192static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
193 struct e1000_rx_ring *rx_ring);
194static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
195 struct e1000_rx_ring *rx_ring);
1da177e4 196#endif
581d708e 197static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 198 struct e1000_rx_ring *rx_ring,
199 int cleaned_count);
581d708e 200static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 201 struct e1000_rx_ring *rx_ring,
202 int cleaned_count);
1da177e4
LT		 203static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
204static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
205 int cmd);
1da177e4
LT		 206static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
207static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
208static void e1000_tx_timeout(struct net_device *dev);
87041639 209static void e1000_reset_task(struct net_device *dev);
1da177e4
LT		 210static void e1000_smartspeed(struct e1000_adapter *adapter);
211static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
212 struct sk_buff *skb);
213
214static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
215static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
216static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
217static void e1000_restore_vlan(struct e1000_adapter *adapter);
218
1da177e4 219#ifdef CONFIG_PM
977e74b5 220static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 221static int e1000_resume(struct pci_dev *pdev);
222#endif
223
224#ifdef CONFIG_NET_POLL_CONTROLLER
225/* for netdump / net console */
226static void e1000_netpoll (struct net_device *netdev);
227#endif
228
24025e4e 229
1da177e4
LT		 230static struct pci_driver e1000_driver = {
231 .name = e1000_driver_name,
232 .id_table = e1000_pci_tbl,
233 .probe = e1000_probe,
234 .remove = __devexit_p(e1000_remove),
235 /* Power Managment Hooks */
236#ifdef CONFIG_PM
237 .suspend = e1000_suspend,
238 .resume = e1000_resume
239#endif
240};
241
242MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
243MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
244MODULE_LICENSE("GPL");
245MODULE_VERSION(DRV_VERSION);
246
247static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
248module_param(debug, int, 0);
249MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
250
251/**
252 * e1000_init_module - Driver Registration Routine
253 *
254 * e1000_init_module is the first routine called when the driver is
255 * loaded. All it does is register with the PCI subsystem.
256 **/
257
258static int __init
259e1000_init_module(void)
260{
261 int ret;
262 printk(KERN_INFO "%s - version %s\n",
263 e1000_driver_string, e1000_driver_version);
264
265 printk(KERN_INFO "%s\n", e1000_copyright);
266
267 ret = pci_module_init(&e1000_driver);
8b378def 268
1da177e4
LT		 269 return ret;
270}
271
272module_init(e1000_init_module);
273
274/**
275 * e1000_exit_module - Driver Exit Cleanup Routine
276 *
277 * e1000_exit_module is called just before the driver is removed
278 * from memory.
279 **/
280
281static void __exit
282e1000_exit_module(void)
283{
1da177e4
LT		 284 pci_unregister_driver(&e1000_driver);
285}
286
287module_exit(e1000_exit_module);
288
289/**
290 * e1000_irq_disable - Mask off interrupt generation on the NIC
291 * @adapter: board private structure
292 **/
293
294static inline void
295e1000_irq_disable(struct e1000_adapter *adapter)
296{
297 atomic_inc(&adapter->irq_sem);
298 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
299 E1000_WRITE_FLUSH(&adapter->hw);
300 synchronize_irq(adapter->pdev->irq);
301}
302
303/**
304 * e1000_irq_enable - Enable default interrupt generation settings
305 * @adapter: board private structure
306 **/
307
308static inline void
309e1000_irq_enable(struct e1000_adapter *adapter)
310{
96838a40 311 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 312 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
313 E1000_WRITE_FLUSH(&adapter->hw);
314 }
315}
3ad2cc67
AB		 316
317static void
2d7edb92
MC		 318e1000_update_mng_vlan(struct e1000_adapter *adapter)
319{
320 struct net_device *netdev = adapter->netdev;
321 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
322 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 323 if (adapter->vlgrp) {
324 if (!adapter->vlgrp->vlan_devices[vid]) {
325 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 326 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
327 e1000_vlan_rx_add_vid(netdev, vid);
328 adapter->mng_vlan_id = vid;
329 } else
330 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 331
332 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
333 (vid != old_vid) &&
2d7edb92
MC		 334 !adapter->vlgrp->vlan_devices[old_vid])
335 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 336 } else
337 adapter->mng_vlan_id = vid;
2d7edb92
MC		 338 }
339}
b55ccb35
JK		 340
341/**
342 * e1000_release_hw_control - release control of the h/w to f/w
343 * @adapter: address of board private structure
344 *
345 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
346 * For ASF and Pass Through versions of f/w this means that the
347 * driver is no longer loaded. For AMT version (only with 82573) i
348 * of the f/w this means that the netowrk i/f is closed.
349 *
350 **/
351
352static inline void
353e1000_release_hw_control(struct e1000_adapter *adapter)
354{
355 uint32_t ctrl_ext;
356 uint32_t swsm;
357
358 /* Let firmware taken over control of h/w */
359 switch (adapter->hw.mac_type) {
360 case e1000_82571:
361 case e1000_82572:
4cc15f54 362 case e1000_80003es2lan:
b55ccb35
JK		 363 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
364 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
365 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
366 break;
367 case e1000_82573:
368 swsm = E1000_READ_REG(&adapter->hw, SWSM);
369 E1000_WRITE_REG(&adapter->hw, SWSM,
370 swsm & ~E1000_SWSM_DRV_LOAD);
371 default:
372 break;
373 }
374}
375
376/**
377 * e1000_get_hw_control - get control of the h/w from f/w
378 * @adapter: address of board private structure
379 *
380 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
381 * For ASF and Pass Through versions of f/w this means that
382 * the driver is loaded. For AMT version (only with 82573)
383 * of the f/w this means that the netowrk i/f is open.
384 *
385 **/
386
387static inline void
388e1000_get_hw_control(struct e1000_adapter *adapter)
389{
390 uint32_t ctrl_ext;
391 uint32_t swsm;
392 /* Let firmware know the driver has taken over */
393 switch (adapter->hw.mac_type) {
394 case e1000_82571:
395 case e1000_82572:
4cc15f54 396 case e1000_80003es2lan:
b55ccb35
JK		 397 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
398 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
399 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
400 break;
401 case e1000_82573:
402 swsm = E1000_READ_REG(&adapter->hw, SWSM);
403 E1000_WRITE_REG(&adapter->hw, SWSM,
404 swsm | E1000_SWSM_DRV_LOAD);
405 break;
406 default:
407 break;
408 }
409}
410
1da177e4
LT		 411int
412e1000_up(struct e1000_adapter *adapter)
413{
414 struct net_device *netdev = adapter->netdev;
581d708e 415 int i, err;
1da177e4
LT		 416
417 /* hardware has been reset, we need to reload some things */
418
419 /* Reset the PHY if it was previously powered down */
96838a40 420 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 421 uint16_t mii_reg;
422 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
96838a40 423 if (mii_reg & MII_CR_POWER_DOWN)
4cc15f54 424 e1000_phy_hw_reset(&adapter->hw);
1da177e4
LT		 425 }
426
427 e1000_set_multi(netdev);
428
429 e1000_restore_vlan(adapter);
430
431 e1000_configure_tx(adapter);
432 e1000_setup_rctl(adapter);
433 e1000_configure_rx(adapter);
72d64a43
JK		 434 /* call E1000_DESC_UNUSED which always leaves
435 * at least 1 descriptor unused to make sure
436 * next_to_use != next_to_clean */
f56799ea 437 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 438 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 439 adapter->alloc_rx_buf(adapter, ring,
440 E1000_DESC_UNUSED(ring));
f56799ea 441 }
1da177e4 442
fa4f7ef3 443#ifdef CONFIG_PCI_MSI
96838a40 444 if (adapter->hw.mac_type > e1000_82547_rev_2) {
fa4f7ef3 445 adapter->have_msi = TRUE;
96838a40 446 if ((err = pci_enable_msi(adapter->pdev))) {
fa4f7ef3
MC		 447 DPRINTK(PROBE, ERR,
448 "Unable to allocate MSI interrupt Error: %d\n", err);
449 adapter->have_msi = FALSE;
450 }
451 }
452#endif
96838a40 453 if ((err = request_irq(adapter->pdev->irq, &e1000_intr,
1da177e4 454 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 455 netdev->name, netdev))) {
456 DPRINTK(PROBE, ERR,
457 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 458 return err;
2648345f 459 }
1da177e4 460
7bfa4816
JK		 461 adapter->tx_queue_len = netdev->tx_queue_len;
462
1da177e4 463 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 464
465#ifdef CONFIG_E1000_NAPI
466 netif_poll_enable(netdev);
467#endif
5de55624
MC		 468 e1000_irq_enable(adapter);
469
1da177e4
LT		 470 return 0;
471}
472
473void
474e1000_down(struct e1000_adapter *adapter)
475{
476 struct net_device *netdev = adapter->netdev;
57128197
JK		 477 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
478 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 479
480 e1000_irq_disable(adapter);
c1605eb3 481
1da177e4 482 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3 483#ifdef CONFIG_PCI_MSI
96838a40 484 if (adapter->hw.mac_type > e1000_82547_rev_2 &&
fa4f7ef3
MC		 485 adapter->have_msi == TRUE)
486 pci_disable_msi(adapter->pdev);
487#endif
1da177e4
LT		 488 del_timer_sync(&adapter->tx_fifo_stall_timer);
489 del_timer_sync(&adapter->watchdog_timer);
490 del_timer_sync(&adapter->phy_info_timer);
491
492#ifdef CONFIG_E1000_NAPI
493 netif_poll_disable(netdev);
494#endif
7bfa4816 495 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 496 adapter->link_speed = 0;
497 adapter->link_duplex = 0;
498 netif_carrier_off(netdev);
499 netif_stop_queue(netdev);
500
501 e1000_reset(adapter);
581d708e
MC		 502 e1000_clean_all_tx_rings(adapter);
503 e1000_clean_all_rx_rings(adapter);
1da177e4 504
57128197
JK		 505 /* Power down the PHY so no link is implied when interface is down *
506 * The PHY cannot be powered down if any of the following is TRUE *
507 * (a) WoL is enabled
508 * (b) AMT is active
509 * (c) SoL/IDER session is active */
510 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 511 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 512 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
513 !mng_mode_enabled &&
514 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 515 uint16_t mii_reg;
516 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
517 mii_reg |= MII_CR_POWER_DOWN;
518 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 519 mdelay(1);
1da177e4
LT		 520 }
521}
522
523void
524e1000_reset(struct e1000_adapter *adapter)
525{
2d7edb92 526 uint32_t pba, manc;
1125ecbc 527 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 528
529 /* Repartition Pba for greater than 9k mtu
530 * To take effect CTRL.RST is required.
531 */
532
2d7edb92
MC		 533 switch (adapter->hw.mac_type) {
534 case e1000_82547:
0e6ef3e0 535 case e1000_82547_rev_2:
2d7edb92
MC		 536 pba = E1000_PBA_30K;
537 break;
868d5309
MC		 538 case e1000_82571:
539 case e1000_82572:
6418ecc6 540 case e1000_80003es2lan:
868d5309
MC		 541 pba = E1000_PBA_38K;
542 break;
2d7edb92
MC		 543 case e1000_82573:
544 pba = E1000_PBA_12K;
545 break;
546 default:
547 pba = E1000_PBA_48K;
548 break;
549 }
550
96838a40 551 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 552 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 553 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 554
555
96838a40 556 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 557 adapter->tx_fifo_head = 0;
558 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
559 adapter->tx_fifo_size =
560 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
561 atomic_set(&adapter->tx_fifo_stall, 0);
562 }
2d7edb92 563
1da177e4
LT		 564 E1000_WRITE_REG(&adapter->hw, PBA, pba);
565
566 /* flow control settings */
f11b7f85
JK		 567 /* Set the FC high water mark to 90% of the FIFO size.
568 * Required to clear last 3 LSB */
569 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
570
571 adapter->hw.fc_high_water = fc_high_water_mark;
572 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 573 if (adapter->hw.mac_type == e1000_80003es2lan)
574 adapter->hw.fc_pause_time = 0xFFFF;
575 else
576 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 577 adapter->hw.fc_send_xon = 1;
578 adapter->hw.fc = adapter->hw.original_fc;
579
2d7edb92 580 /* Allow time for pending master requests to run */
1da177e4 581 e1000_reset_hw(&adapter->hw);
96838a40 582 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 583 E1000_WRITE_REG(&adapter->hw, WUC, 0);
96838a40 584 if (e1000_init_hw(&adapter->hw))
1da177e4 585 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 586 e1000_update_mng_vlan(adapter);
1da177e4
LT		 587 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
588 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
589
590 e1000_reset_adaptive(&adapter->hw);
591 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 592 if (adapter->en_mng_pt) {
593 manc = E1000_READ_REG(&adapter->hw, MANC);
594 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
595 E1000_WRITE_REG(&adapter->hw, MANC, manc);
596 }
1da177e4
LT		 597}
598
599/**
600 * e1000_probe - Device Initialization Routine
601 * @pdev: PCI device information struct
602 * @ent: entry in e1000_pci_tbl
603 *
604 * Returns 0 on success, negative on failure
605 *
606 * e1000_probe initializes an adapter identified by a pci_dev structure.
607 * The OS initialization, configuring of the adapter private structure,
608 * and a hardware reset occur.
609 **/
610
611static int __devinit
612e1000_probe(struct pci_dev *pdev,
613 const struct pci_device_id *ent)
614{
615 struct net_device *netdev;
616 struct e1000_adapter *adapter;
2d7edb92 617 unsigned long mmio_start, mmio_len;
2d7edb92 618
1da177e4 619 static int cards_found = 0;
84916829 620 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
2d7edb92 621 int i, err, pci_using_dac;
1da177e4
LT		 622 uint16_t eeprom_data;
623 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 624 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 625 return err;
626
96838a40 627 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 628 pci_using_dac = 1;
629 } else {
96838a40 630 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 631 E1000_ERR("No usable DMA configuration, aborting\n");
632 return err;
633 }
634 pci_using_dac = 0;
635 }
636
96838a40 637 if ((err = pci_request_regions(pdev, e1000_driver_name)))
1da177e4
LT		 638 return err;
639
640 pci_set_master(pdev);
641
642 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
96838a40 643 if (!netdev) {
1da177e4
LT		 644 err = -ENOMEM;
645 goto err_alloc_etherdev;
646 }
647
648 SET_MODULE_OWNER(netdev);
649 SET_NETDEV_DEV(netdev, &pdev->dev);
650
651 pci_set_drvdata(pdev, netdev);
60490fe0 652 adapter = netdev_priv(netdev);
1da177e4
LT		 653 adapter->netdev = netdev;
654 adapter->pdev = pdev;
655 adapter->hw.back = adapter;
656 adapter->msg_enable = (1 << debug) - 1;
657
658 mmio_start = pci_resource_start(pdev, BAR_0);
659 mmio_len = pci_resource_len(pdev, BAR_0);
660
661 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
96838a40 662 if (!adapter->hw.hw_addr) {
1da177e4
LT		 663 err = -EIO;
664 goto err_ioremap;
665 }
666
96838a40
JB		 667 for (i = BAR_1; i <= BAR_5; i++) {
668 if (pci_resource_len(pdev, i) == 0)
1da177e4 669 continue;
96838a40 670 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 671 adapter->hw.io_base = pci_resource_start(pdev, i);
672 break;
673 }
674 }
675
676 netdev->open = &e1000_open;
677 netdev->stop = &e1000_close;
678 netdev->hard_start_xmit = &e1000_xmit_frame;
679 netdev->get_stats = &e1000_get_stats;
680 netdev->set_multicast_list = &e1000_set_multi;
681 netdev->set_mac_address = &e1000_set_mac;
682 netdev->change_mtu = &e1000_change_mtu;
683 netdev->do_ioctl = &e1000_ioctl;
684 e1000_set_ethtool_ops(netdev);
685 netdev->tx_timeout = &e1000_tx_timeout;
686 netdev->watchdog_timeo = 5 * HZ;
687#ifdef CONFIG_E1000_NAPI
688 netdev->poll = &e1000_clean;
689 netdev->weight = 64;
690#endif
691 netdev->vlan_rx_register = e1000_vlan_rx_register;
692 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
693 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
694#ifdef CONFIG_NET_POLL_CONTROLLER
695 netdev->poll_controller = e1000_netpoll;
696#endif
697 strcpy(netdev->name, pci_name(pdev));
698
699 netdev->mem_start = mmio_start;
700 netdev->mem_end = mmio_start + mmio_len;
701 netdev->base_addr = adapter->hw.io_base;
702
703 adapter->bd_number = cards_found;
704
705 /* setup the private structure */
706
96838a40 707 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 708 goto err_sw_init;
709
96838a40 710 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
2d7edb92
MC		 711 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
712
84916829
JK		 713 /* if ksp3, indicate if it's port a being setup */
714 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
715 e1000_ksp3_port_a == 0)
716 adapter->ksp3_port_a = 1;
717 e1000_ksp3_port_a++;
718 /* Reset for multiple KP3 adapters */
719 if (e1000_ksp3_port_a == 4)
720 e1000_ksp3_port_a = 0;
721
96838a40 722 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 723 netdev->features = NETIF_F_SG |
724 NETIF_F_HW_CSUM |
725 NETIF_F_HW_VLAN_TX |
726 NETIF_F_HW_VLAN_RX |
727 NETIF_F_HW_VLAN_FILTER;
728 }
729
730#ifdef NETIF_F_TSO
96838a40 731 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 732 (adapter->hw.mac_type != e1000_82547))
733 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 734
735#ifdef NETIF_F_TSO_IPV6
96838a40 736 if (adapter->hw.mac_type > e1000_82547_rev_2)
2d7edb92
MC		 737 netdev->features |= NETIF_F_TSO_IPV6;
738#endif
1da177e4 739#endif
96838a40 740 if (pci_using_dac)
1da177e4
LT		 741 netdev->features |= NETIF_F_HIGHDMA;
742
743 /* hard_start_xmit is safe against parallel locking */
744 netdev->features |= NETIF_F_LLTX;
745
2d7edb92
MC		 746 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
747
96838a40 748 /* before reading the EEPROM, reset the controller to
1da177e4 749 * put the device in a known good starting state */
96838a40 750
1da177e4
LT		 751 e1000_reset_hw(&adapter->hw);
752
753 /* make sure the EEPROM is good */
754
96838a40 755 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4
LT		 756 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
757 err = -EIO;
758 goto err_eeprom;
759 }
760
761 /* copy the MAC address out of the EEPROM */
762
96838a40 763 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 764 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
765 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 766 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 767
96838a40 768 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 769 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
770 err = -EIO;
771 goto err_eeprom;
772 }
773
774 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
775
776 e1000_get_bus_info(&adapter->hw);
777
778 init_timer(&adapter->tx_fifo_stall_timer);
779 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
780 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
781
782 init_timer(&adapter->watchdog_timer);
783 adapter->watchdog_timer.function = &e1000_watchdog;
784 adapter->watchdog_timer.data = (unsigned long) adapter;
785
786 INIT_WORK(&adapter->watchdog_task,
787 (void (*)(void *))e1000_watchdog_task, adapter);
788
789 init_timer(&adapter->phy_info_timer);
790 adapter->phy_info_timer.function = &e1000_update_phy_info;
791 adapter->phy_info_timer.data = (unsigned long) adapter;
792
87041639
JK		 793 INIT_WORK(&adapter->reset_task,
794 (void (*)(void *))e1000_reset_task, netdev);
1da177e4
LT		 795
796 /* we're going to reset, so assume we have no link for now */
797
798 netif_carrier_off(netdev);
799 netif_stop_queue(netdev);
800
801 e1000_check_options(adapter);
802
803 /* Initial Wake on LAN setting
804 * If APM wake is enabled in the EEPROM,
805 * enable the ACPI Magic Packet filter
806 */
807
96838a40 808 switch (adapter->hw.mac_type) {
1da177e4
LT		 809 case e1000_82542_rev2_0:
810 case e1000_82542_rev2_1:
811 case e1000_82543:
812 break;
813 case e1000_82544:
814 e1000_read_eeprom(&adapter->hw,
815 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
816 eeprom_apme_mask = E1000_EEPROM_82544_APM;
817 break;
818 case e1000_82546:
819 case e1000_82546_rev_3:
fd803241 820 case e1000_82571:
6418ecc6 821 case e1000_80003es2lan:
96838a40 822 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 823 e1000_read_eeprom(&adapter->hw,
824 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
825 break;
826 }
827 /* Fall Through */
828 default:
829 e1000_read_eeprom(&adapter->hw,
830 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
831 break;
832 }
96838a40 833 if (eeprom_data & eeprom_apme_mask)
1da177e4
LT		 834 adapter->wol |= E1000_WUFC_MAG;
835
fb3d47d4
JK		 836 /* print bus type/speed/width info */
837 {
838 struct e1000_hw *hw = &adapter->hw;
839 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
840 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
841 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
842 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
843 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
844 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
845 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
846 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
847 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
848 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
849 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
850 "32-bit"));
851 }
852
853 for (i = 0; i < 6; i++)
854 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
855
1da177e4
LT		 856 /* reset the hardware with the new settings */
857 e1000_reset(adapter);
858
b55ccb35
JK		 859 /* If the controller is 82573 and f/w is AMT, do not set
860 * DRV_LOAD until the interface is up. For all other cases,
861 * let the f/w know that the h/w is now under the control
862 * of the driver. */
863 if (adapter->hw.mac_type != e1000_82573 ||
864 !e1000_check_mng_mode(&adapter->hw))
865 e1000_get_hw_control(adapter);
2d7edb92 866
1da177e4 867 strcpy(netdev->name, "eth%d");
96838a40 868 if ((err = register_netdev(netdev)))
1da177e4
LT		 869 goto err_register;
870
871 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
872
873 cards_found++;
874 return 0;
875
876err_register:
877err_sw_init:
878err_eeprom:
879 iounmap(adapter->hw.hw_addr);
880err_ioremap:
881 free_netdev(netdev);
882err_alloc_etherdev:
883 pci_release_regions(pdev);
884 return err;
885}
886
887/**
888 * e1000_remove - Device Removal Routine
889 * @pdev: PCI device information struct
890 *
891 * e1000_remove is called by the PCI subsystem to alert the driver
892 * that it should release a PCI device. The could be caused by a
893 * Hot-Plug event, or because the driver is going to be removed from
894 * memory.
895 **/
896
897static void __devexit
898e1000_remove(struct pci_dev *pdev)
899{
900 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 901 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 902 uint32_t manc;
581d708e
MC		 903#ifdef CONFIG_E1000_NAPI
904 int i;
905#endif
1da177e4 906
be2b28ed
JG		 907 flush_scheduled_work();
908
96838a40 909 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 910 adapter->hw.media_type == e1000_media_type_copper) {
911 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 912 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 913 manc |= E1000_MANC_ARP_EN;
914 E1000_WRITE_REG(&adapter->hw, MANC, manc);
915 }
916 }
917
b55ccb35
JK		 918 /* Release control of h/w to f/w. If f/w is AMT enabled, this
919 * would have already happened in close and is redundant. */
920 e1000_release_hw_control(adapter);
2d7edb92 921
1da177e4 922 unregister_netdev(netdev);
581d708e 923#ifdef CONFIG_E1000_NAPI
f56799ea 924 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 925 dev_put(&adapter->polling_netdev[i]);
581d708e 926#endif
1da177e4 927
96838a40 928 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 929 e1000_phy_hw_reset(&adapter->hw);
1da177e4 930
24025e4e
MC		 931 kfree(adapter->tx_ring);
932 kfree(adapter->rx_ring);
933#ifdef CONFIG_E1000_NAPI
934 kfree(adapter->polling_netdev);
935#endif
936
1da177e4
LT		 937 iounmap(adapter->hw.hw_addr);
938 pci_release_regions(pdev);
939
940 free_netdev(netdev);
941
942 pci_disable_device(pdev);
943}
944
945/**
946 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
947 * @adapter: board private structure to initialize
948 *
949 * e1000_sw_init initializes the Adapter private data structure.
950 * Fields are initialized based on PCI device information and
951 * OS network device settings (MTU size).
952 **/
953
954static int __devinit
955e1000_sw_init(struct e1000_adapter *adapter)
956{
957 struct e1000_hw *hw = &adapter->hw;
958 struct net_device *netdev = adapter->netdev;
959 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 960#ifdef CONFIG_E1000_NAPI
961 int i;
962#endif
1da177e4
LT		 963
964 /* PCI config space info */
965
966 hw->vendor_id = pdev->vendor;
967 hw->device_id = pdev->device;
968 hw->subsystem_vendor_id = pdev->subsystem_vendor;
969 hw->subsystem_id = pdev->subsystem_device;
970
971 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
972
973 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
974
975 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 976 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 977 hw->max_frame_size = netdev->mtu +
978 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
979 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
980
981 /* identify the MAC */
982
96838a40 983 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 984 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
985 return -EIO;
986 }
987
988 /* initialize eeprom parameters */
989
96838a40 990 if (e1000_init_eeprom_params(hw)) {
2d7edb92
MC		 991 E1000_ERR("EEPROM initialization failed\n");
992 return -EIO;
993 }
1da177e4 994
96838a40 995 switch (hw->mac_type) {
1da177e4
LT		 996 default:
997 break;
998 case e1000_82541:
999 case e1000_82547:
1000 case e1000_82541_rev_2:
1001 case e1000_82547_rev_2:
1002 hw->phy_init_script = 1;
1003 break;
1004 }
1005
1006 e1000_set_media_type(hw);
1007
1008 hw->wait_autoneg_complete = FALSE;
1009 hw->tbi_compatibility_en = TRUE;
1010 hw->adaptive_ifs = TRUE;
1011
1012 /* Copper options */
1013
96838a40 1014 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1015 hw->mdix = AUTO_ALL_MODES;
1016 hw->disable_polarity_correction = FALSE;
1017 hw->master_slave = E1000_MASTER_SLAVE;
1018 }
1019
f56799ea
JK		 1020 adapter->num_tx_queues = 1;
1021 adapter->num_rx_queues = 1;
581d708e
MC		 1022
1023 if (e1000_alloc_queues(adapter)) {
1024 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1025 return -ENOMEM;
1026 }
1027
1028#ifdef CONFIG_E1000_NAPI
f56799ea 1029 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1030 adapter->polling_netdev[i].priv = adapter;
1031 adapter->polling_netdev[i].poll = &e1000_clean;
1032 adapter->polling_netdev[i].weight = 64;
1033 dev_hold(&adapter->polling_netdev[i]);
1034 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1035 }
7bfa4816 1036 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1037#endif
1038
1da177e4
LT		 1039 atomic_set(&adapter->irq_sem, 1);
1040 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1041
1042 return 0;
1043}
1044
581d708e
MC		 1045/**
1046 * e1000_alloc_queues - Allocate memory for all rings
1047 * @adapter: board private structure to initialize
1048 *
1049 * We allocate one ring per queue at run-time since we don't know the
1050 * number of queues at compile-time. The polling_netdev array is
1051 * intended for Multiqueue, but should work fine with a single queue.
1052 **/
1053
1054static int __devinit
1055e1000_alloc_queues(struct e1000_adapter *adapter)
1056{
1057 int size;
1058
f56799ea 1059 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1060 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1061 if (!adapter->tx_ring)
1062 return -ENOMEM;
1063 memset(adapter->tx_ring, 0, size);
1064
f56799ea 1065 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1066 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1067 if (!adapter->rx_ring) {
1068 kfree(adapter->tx_ring);
1069 return -ENOMEM;
1070 }
1071 memset(adapter->rx_ring, 0, size);
1072
1073#ifdef CONFIG_E1000_NAPI
f56799ea 1074 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1075 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1076 if (!adapter->polling_netdev) {
1077 kfree(adapter->tx_ring);
1078 kfree(adapter->rx_ring);
1079 return -ENOMEM;
1080 }
1081 memset(adapter->polling_netdev, 0, size);
1082#endif
1083
1084 return E1000_SUCCESS;
1085}
1086
1da177e4
LT		 1087/**
1088 * e1000_open - Called when a network interface is made active
1089 * @netdev: network interface device structure
1090 *
1091 * Returns 0 on success, negative value on failure
1092 *
1093 * The open entry point is called when a network interface is made
1094 * active by the system (IFF_UP). At this point all resources needed
1095 * for transmit and receive operations are allocated, the interrupt
1096 * handler is registered with the OS, the watchdog timer is started,
1097 * and the stack is notified that the interface is ready.
1098 **/
1099
1100static int
1101e1000_open(struct net_device *netdev)
1102{
60490fe0 1103 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1104 int err;
1105
1106 /* allocate transmit descriptors */
1107
581d708e 1108 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1109 goto err_setup_tx;
1110
1111 /* allocate receive descriptors */
1112
581d708e 1113 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1114 goto err_setup_rx;
1115
96838a40 1116 if ((err = e1000_up(adapter)))
1da177e4 1117 goto err_up;
2d7edb92 1118 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1119 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1120 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1121 e1000_update_mng_vlan(adapter);
1122 }
1da177e4 1123
b55ccb35
JK		 1124 /* If AMT is enabled, let the firmware know that the network
1125 * interface is now open */
1126 if (adapter->hw.mac_type == e1000_82573 &&
1127 e1000_check_mng_mode(&adapter->hw))
1128 e1000_get_hw_control(adapter);
1129
1da177e4
LT		 1130 return E1000_SUCCESS;
1131
1132err_up:
581d708e 1133 e1000_free_all_rx_resources(adapter);
1da177e4 1134err_setup_rx:
581d708e 1135 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1136err_setup_tx:
1137 e1000_reset(adapter);
1138
1139 return err;
1140}
1141
1142/**
1143 * e1000_close - Disables a network interface
1144 * @netdev: network interface device structure
1145 *
1146 * Returns 0, this is not allowed to fail
1147 *
1148 * The close entry point is called when an interface is de-activated
1149 * by the OS. The hardware is still under the drivers control, but
1150 * needs to be disabled. A global MAC reset is issued to stop the
1151 * hardware, and all transmit and receive resources are freed.
1152 **/
1153
1154static int
1155e1000_close(struct net_device *netdev)
1156{
60490fe0 1157 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1158
1159 e1000_down(adapter);
1160
581d708e
MC		 1161 e1000_free_all_tx_resources(adapter);
1162 e1000_free_all_rx_resources(adapter);
1da177e4 1163
96838a40 1164 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1165 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1166 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1167 }
b55ccb35
JK		 1168
1169 /* If AMT is enabled, let the firmware know that the network
1170 * interface is now closed */
1171 if (adapter->hw.mac_type == e1000_82573 &&
1172 e1000_check_mng_mode(&adapter->hw))
1173 e1000_release_hw_control(adapter);
1174
1da177e4
LT		 1175 return 0;
1176}
1177
1178/**
1179 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1180 * @adapter: address of board private structure
2d7edb92
MC		 1181 * @start: address of beginning of memory
1182 * @len: length of memory
1da177e4
LT		 1183 **/
1184static inline boolean_t
1185e1000_check_64k_bound(struct e1000_adapter *adapter,
1186 void *start, unsigned long len)
1187{
1188 unsigned long begin = (unsigned long) start;
1189 unsigned long end = begin + len;
1190
2648345f
MC		 1191 /* First rev 82545 and 82546 need to not allow any memory
1192 * write location to cross 64k boundary due to errata 23 */
1da177e4 1193 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1194 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1195 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1196 }
1197
1198 return TRUE;
1199}
1200
1201/**
1202 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1203 * @adapter: board private structure
581d708e 1204 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1205 *
1206 * Return 0 on success, negative on failure
1207 **/
1208
3ad2cc67 1209static int
581d708e
MC		 1210e1000_setup_tx_resources(struct e1000_adapter *adapter,
1211 struct e1000_tx_ring *txdr)
1da177e4 1212{
1da177e4
LT		 1213 struct pci_dev *pdev = adapter->pdev;
1214 int size;
1215
1216 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1217
1218 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
96838a40 1219 if (!txdr->buffer_info) {
2648345f
MC		 1220 DPRINTK(PROBE, ERR,
1221 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1222 return -ENOMEM;
1223 }
1224 memset(txdr->buffer_info, 0, size);
1225
1226 /* round up to nearest 4K */
1227
1228 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1229 E1000_ROUNDUP(txdr->size, 4096);
1230
1231 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1232 if (!txdr->desc) {
1da177e4 1233setup_tx_desc_die:
1da177e4 1234 vfree(txdr->buffer_info);
2648345f
MC		 1235 DPRINTK(PROBE, ERR,
1236 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1237 return -ENOMEM;
1238 }
1239
2648345f 1240 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1241 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1242 void *olddesc = txdr->desc;
1243 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1244 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1245 "at %p\n", txdr->size, txdr->desc);
1246 /* Try again, without freeing the previous */
1da177e4 1247 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1248 /* Failed allocation, critical failure */
96838a40 1249 if (!txdr->desc) {
1da177e4
LT		 1250 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1251 goto setup_tx_desc_die;
1252 }
1253
1254 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1255 /* give up */
2648345f
MC		 1256 pci_free_consistent(pdev, txdr->size, txdr->desc,
1257 txdr->dma);
1da177e4
LT		 1258 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1259 DPRINTK(PROBE, ERR,
2648345f
MC		 1260 "Unable to allocate aligned memory "
1261 "for the transmit descriptor ring\n");
1da177e4
LT		 1262 vfree(txdr->buffer_info);
1263 return -ENOMEM;
1264 } else {
2648345f 1265 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1266 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1267 }
1268 }
1269 memset(txdr->desc, 0, txdr->size);
1270
1271 txdr->next_to_use = 0;
1272 txdr->next_to_clean = 0;
2ae76d98 1273 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1274
1275 return 0;
1276}
1277
581d708e
MC		 1278/**
1279 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1280 * (Descriptors) for all queues
1281 * @adapter: board private structure
1282 *
1283 * If this function returns with an error, then it's possible one or
1284 * more of the rings is populated (while the rest are not). It is the
1285 * callers duty to clean those orphaned rings.
1286 *
1287 * Return 0 on success, negative on failure
1288 **/
1289
1290int
1291e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1292{
1293 int i, err = 0;
1294
f56799ea 1295 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1296 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1297 if (err) {
1298 DPRINTK(PROBE, ERR,
1299 "Allocation for Tx Queue %u failed\n", i);
1300 break;
1301 }
1302 }
1303
1304 return err;
1305}
1306
1da177e4
LT		 1307/**
1308 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1309 * @adapter: board private structure
1310 *
1311 * Configure the Tx unit of the MAC after a reset.
1312 **/
1313
1314static void
1315e1000_configure_tx(struct e1000_adapter *adapter)
1316{
581d708e
MC		 1317 uint64_t tdba;
1318 struct e1000_hw *hw = &adapter->hw;
1319 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1320 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1321
1322 /* Setup the HW Tx Head and Tail descriptor pointers */
1323
f56799ea 1324 switch (adapter->num_tx_queues) {
24025e4e
MC		 1325 case 1:
1326 default:
581d708e
MC		 1327 tdba = adapter->tx_ring[0].dma;
1328 tdlen = adapter->tx_ring[0].count *
1329 sizeof(struct e1000_tx_desc);
1330 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1331 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1332 E1000_WRITE_REG(hw, TDLEN, tdlen);
1333 E1000_WRITE_REG(hw, TDH, 0);
1334 E1000_WRITE_REG(hw, TDT, 0);
1335 adapter->tx_ring[0].tdh = E1000_TDH;
1336 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1337 break;
1338 }
1da177e4
LT		 1339
1340 /* Set the default values for the Tx Inter Packet Gap timer */
1341
0fadb059
JK		 1342 if (hw->media_type == e1000_media_type_fiber ||
1343 hw->media_type == e1000_media_type_internal_serdes)
1344 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1345 else
1346 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1347
581d708e 1348 switch (hw->mac_type) {
1da177e4
LT		 1349 case e1000_82542_rev2_0:
1350 case e1000_82542_rev2_1:
1351 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1352 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1353 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1354 break;
87041639
JK		 1355 case e1000_80003es2lan:
1356 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1357 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1358 break;
1da177e4 1359 default:
0fadb059
JK		 1360 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1361 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1362 break;
1da177e4 1363 }
0fadb059
JK		 1364 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1365 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1366 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1367
1368 /* Set the Tx Interrupt Delay register */
1369
581d708e
MC		 1370 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1371 if (hw->mac_type >= e1000_82540)
1372 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1373
1374 /* Program the Transmit Control Register */
1375
581d708e 1376 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1377
1378 tctl &= ~E1000_TCTL_CT;
7e6c9861 1379 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1380 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1381
7e6c9861
JK		 1382#ifdef DISABLE_MULR
1383 /* disable Multiple Reads for debugging */
1384 tctl &= ~E1000_TCTL_MULR;
1385#endif
1da177e4 1386
2ae76d98
MC		 1387 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1388 tarc = E1000_READ_REG(hw, TARC0);
1389 tarc |= ((1 << 25) | (1 << 21));
1390 E1000_WRITE_REG(hw, TARC0, tarc);
1391 tarc = E1000_READ_REG(hw, TARC1);
1392 tarc |= (1 << 25);
1393 if (tctl & E1000_TCTL_MULR)
1394 tarc &= ~(1 << 28);
1395 else
1396 tarc |= (1 << 28);
1397 E1000_WRITE_REG(hw, TARC1, tarc);
87041639
JK		 1398 } else if (hw->mac_type == e1000_80003es2lan) {
1399 tarc = E1000_READ_REG(hw, TARC0);
1400 tarc |= 1;
1401 if (hw->media_type == e1000_media_type_internal_serdes)
1402 tarc |= (1 << 20);
1403 E1000_WRITE_REG(hw, TARC0, tarc);
1404 tarc = E1000_READ_REG(hw, TARC1);
1405 tarc |= 1;
1406 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1407 }
1408
581d708e 1409 e1000_config_collision_dist(hw);
1da177e4
LT		 1410
1411 /* Setup Transmit Descriptor Settings for eop descriptor */
1412 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1413 E1000_TXD_CMD_IFCS;
1414
581d708e 1415 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1416 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1417 else
1418 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1419
1420 /* Cache if we're 82544 running in PCI-X because we'll
1421 * need this to apply a workaround later in the send path. */
581d708e
MC		 1422 if (hw->mac_type == e1000_82544 &&
1423 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1424 adapter->pcix_82544 = 1;
7e6c9861
JK		 1425
1426 E1000_WRITE_REG(hw, TCTL, tctl);
1427
1da177e4
LT		 1428}
1429
1430/**
1431 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1432 * @adapter: board private structure
581d708e 1433 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1434 *
1435 * Returns 0 on success, negative on failure
1436 **/
1437
3ad2cc67 1438static int
581d708e
MC		 1439e1000_setup_rx_resources(struct e1000_adapter *adapter,
1440 struct e1000_rx_ring *rxdr)
1da177e4 1441{
1da177e4 1442 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1443 int size, desc_len;
1da177e4
LT		 1444
1445 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1446 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1447 if (!rxdr->buffer_info) {
2648345f
MC		 1448 DPRINTK(PROBE, ERR,
1449 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1450 return -ENOMEM;
1451 }
1452 memset(rxdr->buffer_info, 0, size);
1453
2d7edb92
MC		 1454 size = sizeof(struct e1000_ps_page) * rxdr->count;
1455 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1456 if (!rxdr->ps_page) {
2d7edb92
MC		 1457 vfree(rxdr->buffer_info);
1458 DPRINTK(PROBE, ERR,
1459 "Unable to allocate memory for the receive descriptor ring\n");
1460 return -ENOMEM;
1461 }
1462 memset(rxdr->ps_page, 0, size);
1463
1464 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1465 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1466 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1467 vfree(rxdr->buffer_info);
1468 kfree(rxdr->ps_page);
1469 DPRINTK(PROBE, ERR,
1470 "Unable to allocate memory for the receive descriptor ring\n");
1471 return -ENOMEM;
1472 }
1473 memset(rxdr->ps_page_dma, 0, size);
1474
96838a40 1475 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1476 desc_len = sizeof(struct e1000_rx_desc);
1477 else
1478 desc_len = sizeof(union e1000_rx_desc_packet_split);
1479
1da177e4
LT		 1480 /* Round up to nearest 4K */
1481
2d7edb92 1482 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1483 E1000_ROUNDUP(rxdr->size, 4096);
1484
1485 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1486
581d708e
MC		 1487 if (!rxdr->desc) {
1488 DPRINTK(PROBE, ERR,
1489 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1490setup_rx_desc_die:
1da177e4 1491 vfree(rxdr->buffer_info);
2d7edb92
MC		 1492 kfree(rxdr->ps_page);
1493 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1494 return -ENOMEM;
1495 }
1496
2648345f 1497 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1498 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1499 void *olddesc = rxdr->desc;
1500 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1501 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1502 "at %p\n", rxdr->size, rxdr->desc);
1503 /* Try again, without freeing the previous */
1da177e4 1504 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1505 /* Failed allocation, critical failure */
581d708e 1506 if (!rxdr->desc) {
1da177e4 1507 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1508 DPRINTK(PROBE, ERR,
1509 "Unable to allocate memory "
1510 "for the receive descriptor ring\n");
1da177e4
LT		 1511 goto setup_rx_desc_die;
1512 }
1513
1514 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1515 /* give up */
2648345f
MC		 1516 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1517 rxdr->dma);
1da177e4 1518 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1519 DPRINTK(PROBE, ERR,
1520 "Unable to allocate aligned memory "
1521 "for the receive descriptor ring\n");
581d708e 1522 goto setup_rx_desc_die;
1da177e4 1523 } else {
2648345f 1524 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1525 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1526 }
1527 }
1528 memset(rxdr->desc, 0, rxdr->size);
1529
1530 rxdr->next_to_clean = 0;
1531 rxdr->next_to_use = 0;
1532
1533 return 0;
1534}
1535
581d708e
MC		 1536/**
1537 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1538 * (Descriptors) for all queues
1539 * @adapter: board private structure
1540 *
1541 * If this function returns with an error, then it's possible one or
1542 * more of the rings is populated (while the rest are not). It is the
1543 * callers duty to clean those orphaned rings.
1544 *
1545 * Return 0 on success, negative on failure
1546 **/
1547
1548int
1549e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1550{
1551 int i, err = 0;
1552
f56799ea 1553 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1554 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1555 if (err) {
1556 DPRINTK(PROBE, ERR,
1557 "Allocation for Rx Queue %u failed\n", i);
1558 break;
1559 }
1560 }
1561
1562 return err;
1563}
1564
1da177e4 1565/**
2648345f 1566 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1567 * @adapter: Board private structure
1568 **/
e4c811c9
MC		 1569#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1570 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1571static void
1572e1000_setup_rctl(struct e1000_adapter *adapter)
1573{
2d7edb92
MC		 1574 uint32_t rctl, rfctl;
1575 uint32_t psrctl = 0;
35ec56bb 1576#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1577 uint32_t pages = 0;
1578#endif
1da177e4
LT		 1579
1580 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1581
1582 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1583
1584 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1585 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1586 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1587
0fadb059
JK		 1588 if (adapter->hw.mac_type > e1000_82543)
1589 rctl |= E1000_RCTL_SECRC;
1590
1591 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1592 rctl |= E1000_RCTL_SBP;
1593 else
1594 rctl &= ~E1000_RCTL_SBP;
1595
2d7edb92
MC		 1596 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1597 rctl &= ~E1000_RCTL_LPE;
1598 else
1599 rctl |= E1000_RCTL_LPE;
1600
1da177e4 1601 /* Setup buffer sizes */
96838a40 1602 if (adapter->hw.mac_type >= e1000_82571) {
2d7edb92
MC		 1603 /* We can now specify buffers in 1K increments.
1604 * BSIZE and BSEX are ignored in this case. */
1605 rctl |= adapter->rx_buffer_len << 0x11;
1606 } else {
1607 rctl &= ~E1000_RCTL_SZ_4096;
a1415ee6
JK		 1608 rctl |= E1000_RCTL_BSEX;
1609 switch (adapter->rx_buffer_len) {
1610 case E1000_RXBUFFER_2048:
1611 default:
1612 rctl |= E1000_RCTL_SZ_2048;
1613 rctl &= ~E1000_RCTL_BSEX;
1614 break;
1615 case E1000_RXBUFFER_4096:
1616 rctl |= E1000_RCTL_SZ_4096;
1617 break;
1618 case E1000_RXBUFFER_8192:
1619 rctl |= E1000_RCTL_SZ_8192;
1620 break;
1621 case E1000_RXBUFFER_16384:
1622 rctl |= E1000_RCTL_SZ_16384;
1623 break;
1624 }
2d7edb92
MC		 1625 }
1626
35ec56bb 1627#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1628 /* 82571 and greater support packet-split where the protocol
1629 * header is placed in skb->data and the packet data is
1630 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1631 * In the case of a non-split, skb->data is linearly filled,
1632 * followed by the page buffers. Therefore, skb->data is
1633 * sized to hold the largest protocol header.
1634 */
e4c811c9
MC		 1635 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1636 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1637 PAGE_SIZE <= 16384)
1638 adapter->rx_ps_pages = pages;
1639 else
1640 adapter->rx_ps_pages = 0;
2d7edb92 1641#endif
e4c811c9 1642 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1643 /* Configure extra packet-split registers */
1644 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1645 rfctl |= E1000_RFCTL_EXTEN;
1646 /* disable IPv6 packet split support */
1647 rfctl |= E1000_RFCTL_IPV6_DIS;
1648 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1649
1650 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
96838a40 1651
2d7edb92
MC		 1652 psrctl |= adapter->rx_ps_bsize0 >>
1653 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1654
1655 switch (adapter->rx_ps_pages) {
1656 case 3:
1657 psrctl |= PAGE_SIZE <<
1658 E1000_PSRCTL_BSIZE3_SHIFT;
1659 case 2:
1660 psrctl |= PAGE_SIZE <<
1661 E1000_PSRCTL_BSIZE2_SHIFT;
1662 case 1:
1663 psrctl |= PAGE_SIZE >>
1664 E1000_PSRCTL_BSIZE1_SHIFT;
1665 break;
1666 }
2d7edb92
MC		 1667
1668 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1669 }
1670
1671 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1672}
1673
1674/**
1675 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1676 * @adapter: board private structure
1677 *
1678 * Configure the Rx unit of the MAC after a reset.
1679 **/
1680
1681static void
1682e1000_configure_rx(struct e1000_adapter *adapter)
1683{
581d708e
MC		 1684 uint64_t rdba;
1685 struct e1000_hw *hw = &adapter->hw;
1686 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 1687
e4c811c9 1688 if (adapter->rx_ps_pages) {
0f15a8fa 1689 /* this is a 32 byte descriptor */
581d708e 1690 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1691 sizeof(union e1000_rx_desc_packet_split);
1692 adapter->clean_rx = e1000_clean_rx_irq_ps;
1693 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1694 } else {
581d708e
MC		 1695 rdlen = adapter->rx_ring[0].count *
1696 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1697 adapter->clean_rx = e1000_clean_rx_irq;
1698 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1699 }
1da177e4
LT		 1700
1701 /* disable receives while setting up the descriptors */
581d708e
MC		 1702 rctl = E1000_READ_REG(hw, RCTL);
1703 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1704
1705 /* set the Receive Delay Timer Register */
581d708e 1706 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1707
581d708e
MC		 1708 if (hw->mac_type >= e1000_82540) {
1709 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1710 if (adapter->itr > 1)
581d708e 1711 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1712 1000000000 / (adapter->itr * 256));
1713 }
1714
2ae76d98 1715 if (hw->mac_type >= e1000_82571) {
2ae76d98 1716 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1717 /* Reset delay timers after every interrupt */
2ae76d98 1718 ctrl_ext |= E1000_CTRL_EXT_CANC;
1e613fd9
JK		 1719#ifdef CONFIG_E1000_NAPI
1720 /* Auto-Mask interrupts upon ICR read. */
1721 ctrl_ext |= E1000_CTRL_EXT_IAME;
1722#endif
2ae76d98 1723 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1724 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1725 E1000_WRITE_FLUSH(hw);
1726 }
1727
581d708e
MC		 1728 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1729 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1730 switch (adapter->num_rx_queues) {
24025e4e
MC		 1731 case 1:
1732 default:
581d708e
MC		 1733 rdba = adapter->rx_ring[0].dma;
1734 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1735 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1736 E1000_WRITE_REG(hw, RDLEN, rdlen);
1737 E1000_WRITE_REG(hw, RDH, 0);
1738 E1000_WRITE_REG(hw, RDT, 0);
1739 adapter->rx_ring[0].rdh = E1000_RDH;
1740 adapter->rx_ring[0].rdt = E1000_RDT;
1741 break;
24025e4e
MC		 1742 }
1743
1da177e4 1744 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1745 if (hw->mac_type >= e1000_82543) {
1746 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1747 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1748 rxcsum |= E1000_RXCSUM_TUOFL;
1749
868d5309 1750 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1751 * Must be used in conjunction with packet-split. */
96838a40
JB		 1752 if ((hw->mac_type >= e1000_82571) &&
1753 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1754 rxcsum |= E1000_RXCSUM_IPPCSE;
1755 }
1756 } else {
1757 rxcsum &= ~E1000_RXCSUM_TUOFL;
1758 /* don't need to clear IPPCSE as it defaults to 0 */
1759 }
581d708e 1760 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 1761 }
1762
581d708e
MC		 1763 if (hw->mac_type == e1000_82573)
1764 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1765
1da177e4 1766 /* Enable Receives */
581d708e 1767 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1768}
1769
1770/**
581d708e 1771 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1772 * @adapter: board private structure
581d708e 1773 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1774 *
1775 * Free all transmit software resources
1776 **/
1777
3ad2cc67 1778static void
581d708e
MC		 1779e1000_free_tx_resources(struct e1000_adapter *adapter,
1780 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1781{
1782 struct pci_dev *pdev = adapter->pdev;
1783
581d708e 1784 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1785
581d708e
MC		 1786 vfree(tx_ring->buffer_info);
1787 tx_ring->buffer_info = NULL;
1da177e4 1788
581d708e 1789 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1790
581d708e
MC		 1791 tx_ring->desc = NULL;
1792}
1793
1794/**
1795 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1796 * @adapter: board private structure
1797 *
1798 * Free all transmit software resources
1799 **/
1800
1801void
1802e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1803{
1804 int i;
1805
f56799ea 1806 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1807 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1808}
1809
1810static inline void
1811e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1812 struct e1000_buffer *buffer_info)
1813{
96838a40 1814 if (buffer_info->dma) {
2648345f
MC		 1815 pci_unmap_page(adapter->pdev,
1816 buffer_info->dma,
1817 buffer_info->length,
1818 PCI_DMA_TODEVICE);
1da177e4 1819 }
8241e35e 1820 if (buffer_info->skb)
1da177e4 1821 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1822 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1823}
1824
1825/**
1826 * e1000_clean_tx_ring - Free Tx Buffers
1827 * @adapter: board private structure
581d708e 1828 * @tx_ring: ring to be cleaned
1da177e4
LT		 1829 **/
1830
1831static void
581d708e
MC		 1832e1000_clean_tx_ring(struct e1000_adapter *adapter,
1833 struct e1000_tx_ring *tx_ring)
1da177e4 1834{
1da177e4
LT		 1835 struct e1000_buffer *buffer_info;
1836 unsigned long size;
1837 unsigned int i;
1838
1839 /* Free all the Tx ring sk_buffs */
1840
96838a40 1841 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 1842 buffer_info = &tx_ring->buffer_info[i];
1843 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1844 }
1845
1846 size = sizeof(struct e1000_buffer) * tx_ring->count;
1847 memset(tx_ring->buffer_info, 0, size);
1848
1849 /* Zero out the descriptor ring */
1850
1851 memset(tx_ring->desc, 0, tx_ring->size);
1852
1853 tx_ring->next_to_use = 0;
1854 tx_ring->next_to_clean = 0;
fd803241 1855 tx_ring->last_tx_tso = 0;
1da177e4 1856
581d708e
MC		 1857 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1858 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1859}
1860
1861/**
1862 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1863 * @adapter: board private structure
1864 **/
1865
1866static void
1867e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1868{
1869 int i;
1870
f56799ea 1871 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1872 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1873}
1874
1875/**
1876 * e1000_free_rx_resources - Free Rx Resources
1877 * @adapter: board private structure
581d708e 1878 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1879 *
1880 * Free all receive software resources
1881 **/
1882
3ad2cc67 1883static void
581d708e
MC		 1884e1000_free_rx_resources(struct e1000_adapter *adapter,
1885 struct e1000_rx_ring *rx_ring)
1da177e4 1886{
1da177e4
LT		 1887 struct pci_dev *pdev = adapter->pdev;
1888
581d708e 1889 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1890
1891 vfree(rx_ring->buffer_info);
1892 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1893 kfree(rx_ring->ps_page);
1894 rx_ring->ps_page = NULL;
1895 kfree(rx_ring->ps_page_dma);
1896 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1897
1898 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1899
1900 rx_ring->desc = NULL;
1901}
1902
1903/**
581d708e 1904 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 1905 * @adapter: board private structure
581d708e
MC		 1906 *
1907 * Free all receive software resources
1908 **/
1909
1910void
1911e1000_free_all_rx_resources(struct e1000_adapter *adapter)
1912{
1913 int i;
1914
f56799ea 1915 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 1916 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
1917}
1918
1919/**
1920 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1921 * @adapter: board private structure
1922 * @rx_ring: ring to free buffers from
1da177e4
LT		 1923 **/
1924
1925static void
581d708e
MC		 1926e1000_clean_rx_ring(struct e1000_adapter *adapter,
1927 struct e1000_rx_ring *rx_ring)
1da177e4 1928{
1da177e4 1929 struct e1000_buffer *buffer_info;
2d7edb92
MC		 1930 struct e1000_ps_page *ps_page;
1931 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 1932 struct pci_dev *pdev = adapter->pdev;
1933 unsigned long size;
2d7edb92 1934 unsigned int i, j;
1da177e4
LT		 1935
1936 /* Free all the Rx ring sk_buffs */
96838a40 1937 for (i = 0; i < rx_ring->count; i++) {
1da177e4 1938 buffer_info = &rx_ring->buffer_info[i];
96838a40 1939 if (buffer_info->skb) {
1da177e4
LT		 1940 pci_unmap_single(pdev,
1941 buffer_info->dma,
1942 buffer_info->length,
1943 PCI_DMA_FROMDEVICE);
1944
1945 dev_kfree_skb(buffer_info->skb);
1946 buffer_info->skb = NULL;
997f5cbd
JK		 1947 }
1948 ps_page = &rx_ring->ps_page[i];
1949 ps_page_dma = &rx_ring->ps_page_dma[i];
1950 for (j = 0; j < adapter->rx_ps_pages; j++) {
1951 if (!ps_page->ps_page[j]) break;
1952 pci_unmap_page(pdev,
1953 ps_page_dma->ps_page_dma[j],
1954 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1955 ps_page_dma->ps_page_dma[j] = 0;
1956 put_page(ps_page->ps_page[j]);
1957 ps_page->ps_page[j] = NULL;
1da177e4
LT		 1958 }
1959 }
1960
1961 size = sizeof(struct e1000_buffer) * rx_ring->count;
1962 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 1963 size = sizeof(struct e1000_ps_page) * rx_ring->count;
1964 memset(rx_ring->ps_page, 0, size);
1965 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
1966 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 1967
1968 /* Zero out the descriptor ring */
1969
1970 memset(rx_ring->desc, 0, rx_ring->size);
1971
1972 rx_ring->next_to_clean = 0;
1973 rx_ring->next_to_use = 0;
1974
581d708e
MC		 1975 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
1976 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
1977}
1978
1979/**
1980 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
1981 * @adapter: board private structure
1982 **/
1983
1984static void
1985e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
1986{
1987 int i;
1988
f56799ea 1989 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 1990 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 1991}
1992
1993/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
1994 * and memory write and invalidate disabled for certain operations
1995 */
1996static void
1997e1000_enter_82542_rst(struct e1000_adapter *adapter)
1998{
1999 struct net_device *netdev = adapter->netdev;
2000 uint32_t rctl;
2001
2002 e1000_pci_clear_mwi(&adapter->hw);
2003
2004 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2005 rctl |= E1000_RCTL_RST;
2006 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2007 E1000_WRITE_FLUSH(&adapter->hw);
2008 mdelay(5);
2009
96838a40 2010 if (netif_running(netdev))
581d708e 2011 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2012}
2013
2014static void
2015e1000_leave_82542_rst(struct e1000_adapter *adapter)
2016{
2017 struct net_device *netdev = adapter->netdev;
2018 uint32_t rctl;
2019
2020 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2021 rctl &= ~E1000_RCTL_RST;
2022 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2023 E1000_WRITE_FLUSH(&adapter->hw);
2024 mdelay(5);
2025
96838a40 2026 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2027 e1000_pci_set_mwi(&adapter->hw);
2028
96838a40 2029 if (netif_running(netdev)) {
72d64a43
JK		 2030 /* No need to loop, because 82542 supports only 1 queue */
2031 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2032 e1000_configure_rx(adapter);
72d64a43 2033 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2034 }
2035}
2036
2037/**
2038 * e1000_set_mac - Change the Ethernet Address of the NIC
2039 * @netdev: network interface device structure
2040 * @p: pointer to an address structure
2041 *
2042 * Returns 0 on success, negative on failure
2043 **/
2044
2045static int
2046e1000_set_mac(struct net_device *netdev, void *p)
2047{
60490fe0 2048 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2049 struct sockaddr *addr = p;
2050
96838a40 2051 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2052 return -EADDRNOTAVAIL;
2053
2054 /* 82542 2.0 needs to be in reset to write receive address registers */
2055
96838a40 2056 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2057 e1000_enter_82542_rst(adapter);
2058
2059 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2060 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2061
2062 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2063
868d5309
MC		 2064 /* With 82571 controllers, LAA may be overwritten (with the default)
2065 * due to controller reset from the other port. */
2066 if (adapter->hw.mac_type == e1000_82571) {
2067 /* activate the work around */
2068 adapter->hw.laa_is_present = 1;
2069
96838a40
JB		 2070 /* Hold a copy of the LAA in RAR[14] This is done so that
2071 * between the time RAR[0] gets clobbered and the time it
2072 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2073 * of the RARs and no incoming packets directed to this port
96838a40 2074 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2075 * RAR[14] */
96838a40 2076 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2077 E1000_RAR_ENTRIES - 1);
2078 }
2079
96838a40 2080 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2081 e1000_leave_82542_rst(adapter);
2082
2083 return 0;
2084}
2085
2086/**
2087 * e1000_set_multi - Multicast and Promiscuous mode set
2088 * @netdev: network interface device structure
2089 *
2090 * The set_multi entry point is called whenever the multicast address
2091 * list or the network interface flags are updated. This routine is
2092 * responsible for configuring the hardware for proper multicast,
2093 * promiscuous mode, and all-multi behavior.
2094 **/
2095
2096static void
2097e1000_set_multi(struct net_device *netdev)
2098{
60490fe0 2099 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2100 struct e1000_hw *hw = &adapter->hw;
2101 struct dev_mc_list *mc_ptr;
2102 uint32_t rctl;
2103 uint32_t hash_value;
868d5309 2104 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2105
868d5309
MC		 2106 /* reserve RAR[14] for LAA over-write work-around */
2107 if (adapter->hw.mac_type == e1000_82571)
2108 rar_entries--;
1da177e4 2109
2648345f
MC		 2110 /* Check for Promiscuous and All Multicast modes */
2111
1da177e4
LT		 2112 rctl = E1000_READ_REG(hw, RCTL);
2113
96838a40 2114 if (netdev->flags & IFF_PROMISC) {
1da177e4 2115 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2116 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2117 rctl |= E1000_RCTL_MPE;
2118 rctl &= ~E1000_RCTL_UPE;
2119 } else {
2120 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2121 }
2122
2123 E1000_WRITE_REG(hw, RCTL, rctl);
2124
2125 /* 82542 2.0 needs to be in reset to write receive address registers */
2126
96838a40 2127 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2128 e1000_enter_82542_rst(adapter);
2129
2130 /* load the first 14 multicast address into the exact filters 1-14
2131 * RAR 0 is used for the station MAC adddress
2132 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2133 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2134 */
2135 mc_ptr = netdev->mc_list;
2136
96838a40 2137 for (i = 1; i < rar_entries; i++) {
868d5309 2138 if (mc_ptr) {
1da177e4
LT		 2139 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2140 mc_ptr = mc_ptr->next;
2141 } else {
2142 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2143 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2144 }
2145 }
2146
2147 /* clear the old settings from the multicast hash table */
2148
96838a40 2149 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
1da177e4
LT		 2150 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2151
2152 /* load any remaining addresses into the hash table */
2153
96838a40 2154 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2155 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2156 e1000_mta_set(hw, hash_value);
2157 }
2158
96838a40 2159 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2160 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2161}
2162
2163/* Need to wait a few seconds after link up to get diagnostic information from
2164 * the phy */
2165
2166static void
2167e1000_update_phy_info(unsigned long data)
2168{
2169 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2170 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2171}
2172
2173/**
2174 * e1000_82547_tx_fifo_stall - Timer Call-back
2175 * @data: pointer to adapter cast into an unsigned long
2176 **/
2177
2178static void
2179e1000_82547_tx_fifo_stall(unsigned long data)
2180{
2181 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2182 struct net_device *netdev = adapter->netdev;
2183 uint32_t tctl;
2184
96838a40
JB		 2185 if (atomic_read(&adapter->tx_fifo_stall)) {
2186 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2187 E1000_READ_REG(&adapter->hw, TDH)) &&
2188 (E1000_READ_REG(&adapter->hw, TDFT) ==
2189 E1000_READ_REG(&adapter->hw, TDFH)) &&
2190 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2191 E1000_READ_REG(&adapter->hw, TDFHS))) {
2192 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2193 E1000_WRITE_REG(&adapter->hw, TCTL,
2194 tctl & ~E1000_TCTL_EN);
2195 E1000_WRITE_REG(&adapter->hw, TDFT,
2196 adapter->tx_head_addr);
2197 E1000_WRITE_REG(&adapter->hw, TDFH,
2198 adapter->tx_head_addr);
2199 E1000_WRITE_REG(&adapter->hw, TDFTS,
2200 adapter->tx_head_addr);
2201 E1000_WRITE_REG(&adapter->hw, TDFHS,
2202 adapter->tx_head_addr);
2203 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2204 E1000_WRITE_FLUSH(&adapter->hw);
2205
2206 adapter->tx_fifo_head = 0;
2207 atomic_set(&adapter->tx_fifo_stall, 0);
2208 netif_wake_queue(netdev);
2209 } else {
2210 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2211 }
2212 }
2213}
2214
2215/**
2216 * e1000_watchdog - Timer Call-back
2217 * @data: pointer to adapter cast into an unsigned long
2218 **/
2219static void
2220e1000_watchdog(unsigned long data)
2221{
2222 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2223
2224 /* Do the rest outside of interrupt context */
2225 schedule_work(&adapter->watchdog_task);
2226}
2227
2228static void
2229e1000_watchdog_task(struct e1000_adapter *adapter)
2230{
2231 struct net_device *netdev = adapter->netdev;
545c67c0 2232 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2233 uint32_t link, tctl;
1da177e4
LT		 2234
2235 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2236 if (adapter->hw.mac_type == e1000_82573) {
2237 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2238 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2239 e1000_update_mng_vlan(adapter);
96838a40 2240 }
1da177e4 2241
96838a40 2242 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2243 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2244 link = !adapter->hw.serdes_link_down;
2245 else
2246 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2247
96838a40
JB		 2248 if (link) {
2249 if (!netif_carrier_ok(netdev)) {
1da177e4
LT		 2250 e1000_get_speed_and_duplex(&adapter->hw,
2251 &adapter->link_speed,
2252 &adapter->link_duplex);
2253
2254 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2255 adapter->link_speed,
2256 adapter->link_duplex == FULL_DUPLEX ?
2257 "Full Duplex" : "Half Duplex");
2258
7e6c9861
JK		 2259 /* tweak tx_queue_len according to speed/duplex
2260 * and adjust the timeout factor */
66a2b0a3
JK		 2261 netdev->tx_queue_len = adapter->tx_queue_len;
2262 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2263 adapter->txb2b = 1;
2264 switch (adapter->link_speed) {
2265 case SPEED_10:
2266 adapter->txb2b = 0;
2267 netdev->tx_queue_len = 10;
2268 adapter->tx_timeout_factor = 8;
2269 break;
2270 case SPEED_100:
2271 adapter->txb2b = 0;
2272 netdev->tx_queue_len = 100;
2273 /* maybe add some timeout factor ? */
2274 break;
2275 }
2276
2277 if ((adapter->hw.mac_type == e1000_82571 ||
2278 adapter->hw.mac_type == e1000_82572) &&
2279 adapter->txb2b == 0) {
2280#define SPEED_MODE_BIT (1 << 21)
2281 uint32_t tarc0;
2282 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2283 tarc0 &= ~SPEED_MODE_BIT;
2284 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2285 }
2286
2287#ifdef NETIF_F_TSO
2288 /* disable TSO for pcie and 10/100 speeds, to avoid
2289 * some hardware issues */
2290 if (!adapter->tso_force &&
2291 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2292 switch (adapter->link_speed) {
2293 case SPEED_10:
66a2b0a3 2294 case SPEED_100:
7e6c9861
JK		 2295 DPRINTK(PROBE,INFO,
2296 "10/100 speed: disabling TSO\n");
2297 netdev->features &= ~NETIF_F_TSO;
2298 break;
2299 case SPEED_1000:
2300 netdev->features |= NETIF_F_TSO;
2301 break;
2302 default:
2303 /* oops */
66a2b0a3
JK		 2304 break;
2305 }
2306 }
7e6c9861
JK		 2307#endif
2308
2309 /* enable transmits in the hardware, need to do this
2310 * after setting TARC0 */
2311 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2312 tctl |= E1000_TCTL_EN;
2313 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2314
1da177e4
LT		 2315 netif_carrier_on(netdev);
2316 netif_wake_queue(netdev);
2317 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2318 adapter->smartspeed = 0;
2319 }
2320 } else {
96838a40 2321 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2322 adapter->link_speed = 0;
2323 adapter->link_duplex = 0;
2324 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2325 netif_carrier_off(netdev);
2326 netif_stop_queue(netdev);
2327 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
87041639
JK		 2328
2329 /* 80003ES2LAN workaround--
2330 * For packet buffer work-around on link down event;
2331 * disable receives in the ISR and
2332 * reset device here in the watchdog
2333 */
2334 if (adapter->hw.mac_type == e1000_80003es2lan) {
2335 /* reset device */
2336 schedule_work(&adapter->reset_task);
2337 }
1da177e4
LT		 2338 }
2339
2340 e1000_smartspeed(adapter);
2341 }
2342
2343 e1000_update_stats(adapter);
2344
2345 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2346 adapter->tpt_old = adapter->stats.tpt;
2347 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2348 adapter->colc_old = adapter->stats.colc;
2349
2350 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2351 adapter->gorcl_old = adapter->stats.gorcl;
2352 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2353 adapter->gotcl_old = adapter->stats.gotcl;
2354
2355 e1000_update_adaptive(&adapter->hw);
2356
f56799ea 2357 if (!netif_carrier_ok(netdev)) {
581d708e 2358 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2359 /* We've lost link, so the controller stops DMA,
2360 * but we've got queued Tx work that's never going
2361 * to get done, so reset controller to flush Tx.
2362 * (Do the reset outside of interrupt context). */
87041639
JK		 2363 adapter->tx_timeout_count++;
2364 schedule_work(&adapter->reset_task);
1da177e4
LT		 2365 }
2366 }
2367
2368 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2369 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2370 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2371 * asymmetrical Tx or Rx gets ITR=8000; everyone
2372 * else is between 2000-8000. */
2373 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2374 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2375 adapter->gotcl - adapter->gorcl :
2376 adapter->gorcl - adapter->gotcl) / 10000;
2377 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2378 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2379 }
2380
2381 /* Cause software interrupt to ensure rx ring is cleaned */
2382 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2383
2648345f 2384 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2385 adapter->detect_tx_hung = TRUE;
2386
96838a40 2387 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2388 * reset from the other port. Set the appropriate LAA in RAR[0] */
2389 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2390 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2391
1da177e4
LT		 2392 /* Reset the timer */
2393 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2394}
2395
2396#define E1000_TX_FLAGS_CSUM 0x00000001
2397#define E1000_TX_FLAGS_VLAN 0x00000002
2398#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2399#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2400#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2401#define E1000_TX_FLAGS_VLAN_SHIFT 16
2402
2403static inline int
581d708e
MC		 2404e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2405 struct sk_buff *skb)
1da177e4
LT		 2406{
2407#ifdef NETIF_F_TSO
2408 struct e1000_context_desc *context_desc;
545c67c0 2409 struct e1000_buffer *buffer_info;
1da177e4
LT		 2410 unsigned int i;
2411 uint32_t cmd_length = 0;
2d7edb92 2412 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2413 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2414 int err;
2415
96838a40 2416 if (skb_shinfo(skb)->tso_size) {
1da177e4
LT		 2417 if (skb_header_cloned(skb)) {
2418 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2419 if (err)
2420 return err;
2421 }
2422
2423 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2424 mss = skb_shinfo(skb)->tso_size;
96838a40 2425 if (skb->protocol == ntohs(ETH_P_IP)) {
2d7edb92
MC		 2426 skb->nh.iph->tot_len = 0;
2427 skb->nh.iph->check = 0;
2428 skb->h.th->check =
2429 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2430 skb->nh.iph->daddr,
2431 0,
2432 IPPROTO_TCP,
2433 0);
2434 cmd_length = E1000_TXD_CMD_IP;
2435 ipcse = skb->h.raw - skb->data - 1;
2436#ifdef NETIF_F_TSO_IPV6
96838a40 2437 } else if (skb->protocol == ntohs(ETH_P_IPV6)) {
2d7edb92
MC		 2438 skb->nh.ipv6h->payload_len = 0;
2439 skb->h.th->check =
2440 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2441 &skb->nh.ipv6h->daddr,
2442 0,
2443 IPPROTO_TCP,
2444 0);
2445 ipcse = 0;
2446#endif
2447 }
1da177e4
LT		 2448 ipcss = skb->nh.raw - skb->data;
2449 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2450 tucss = skb->h.raw - skb->data;
2451 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2452 tucse = 0;
2453
2454 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2455 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2456
581d708e
MC		 2457 i = tx_ring->next_to_use;
2458 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2459 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2460
2461 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2462 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2463 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2464 context_desc->upper_setup.tcp_fields.tucss = tucss;
2465 context_desc->upper_setup.tcp_fields.tucso = tucso;
2466 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2467 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2468 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2469 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2470
545c67c0
JK		 2471 buffer_info->time_stamp = jiffies;
2472
581d708e
MC		 2473 if (++i == tx_ring->count) i = 0;
2474 tx_ring->next_to_use = i;
1da177e4 2475
8241e35e 2476 return TRUE;
1da177e4
LT		 2477 }
2478#endif
2479
8241e35e 2480 return FALSE;
1da177e4
LT		 2481}
2482
2483static inline boolean_t
581d708e
MC		 2484e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2485 struct sk_buff *skb)
1da177e4
LT		 2486{
2487 struct e1000_context_desc *context_desc;
545c67c0 2488 struct e1000_buffer *buffer_info;
1da177e4
LT		 2489 unsigned int i;
2490 uint8_t css;
2491
96838a40 2492 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1da177e4
LT		 2493 css = skb->h.raw - skb->data;
2494
581d708e 2495 i = tx_ring->next_to_use;
545c67c0 2496 buffer_info = &tx_ring->buffer_info[i];
581d708e 2497 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2498
2499 context_desc->upper_setup.tcp_fields.tucss = css;
2500 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2501 context_desc->upper_setup.tcp_fields.tucse = 0;
2502 context_desc->tcp_seg_setup.data = 0;
2503 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2504
545c67c0
JK		 2505 buffer_info->time_stamp = jiffies;
2506
581d708e
MC		 2507 if (unlikely(++i == tx_ring->count)) i = 0;
2508 tx_ring->next_to_use = i;
1da177e4
LT		 2509
2510 return TRUE;
2511 }
2512
2513 return FALSE;
2514}
2515
2516#define E1000_MAX_TXD_PWR 12
2517#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2518
2519static inline int
581d708e
MC		 2520e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2521 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2522 unsigned int nr_frags, unsigned int mss)
1da177e4 2523{
1da177e4
LT		 2524 struct e1000_buffer *buffer_info;
2525 unsigned int len = skb->len;
2526 unsigned int offset = 0, size, count = 0, i;
2527 unsigned int f;
2528 len -= skb->data_len;
2529
2530 i = tx_ring->next_to_use;
2531
96838a40 2532 while (len) {
1da177e4
LT		 2533 buffer_info = &tx_ring->buffer_info[i];
2534 size = min(len, max_per_txd);
2535#ifdef NETIF_F_TSO
fd803241
JK		 2536 /* Workaround for Controller erratum --
2537 * descriptor for non-tso packet in a linear SKB that follows a
2538 * tso gets written back prematurely before the data is fully
0f15a8fa 2539 * DMA'd to the controller */
fd803241 2540 if (!skb->data_len && tx_ring->last_tx_tso &&
0f15a8fa 2541 !skb_shinfo(skb)->tso_size) {
fd803241
JK		 2542 tx_ring->last_tx_tso = 0;
2543 size -= 4;
2544 }
2545
1da177e4
LT		 2546 /* Workaround for premature desc write-backs
2547 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2548 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2549 size -= 4;
2550#endif
97338bde
MC		 2551 /* work-around for errata 10 and it applies
2552 * to all controllers in PCI-X mode
2553 * The fix is to make sure that the first descriptor of a
2554 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2555 */
96838a40 2556 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2557 (size > 2015) && count == 0))
2558 size = 2015;
96838a40 2559
1da177e4
LT		 2560 /* Workaround for potential 82544 hang in PCI-X. Avoid
2561 * terminating buffers within evenly-aligned dwords. */
96838a40 2562 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2563 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2564 size > 4))
2565 size -= 4;
2566
2567 buffer_info->length = size;
2568 buffer_info->dma =
2569 pci_map_single(adapter->pdev,
2570 skb->data + offset,
2571 size,
2572 PCI_DMA_TODEVICE);
2573 buffer_info->time_stamp = jiffies;
2574
2575 len -= size;
2576 offset += size;
2577 count++;
96838a40 2578 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2579 }
2580
96838a40 2581 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2582 struct skb_frag_struct *frag;
2583
2584 frag = &skb_shinfo(skb)->frags[f];
2585 len = frag->size;
2586 offset = frag->page_offset;
2587
96838a40 2588 while (len) {
1da177e4
LT		 2589 buffer_info = &tx_ring->buffer_info[i];
2590 size = min(len, max_per_txd);
2591#ifdef NETIF_F_TSO
2592 /* Workaround for premature desc write-backs
2593 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2594 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2595 size -= 4;
2596#endif
2597 /* Workaround for potential 82544 hang in PCI-X.
2598 * Avoid terminating buffers within evenly-aligned
2599 * dwords. */
96838a40 2600 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2601 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2602 size > 4))
2603 size -= 4;
2604
2605 buffer_info->length = size;
2606 buffer_info->dma =
2607 pci_map_page(adapter->pdev,
2608 frag->page,
2609 offset,
2610 size,
2611 PCI_DMA_TODEVICE);
2612 buffer_info->time_stamp = jiffies;
2613
2614 len -= size;
2615 offset += size;
2616 count++;
96838a40 2617 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2618 }
2619 }
2620
2621 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2622 tx_ring->buffer_info[i].skb = skb;
2623 tx_ring->buffer_info[first].next_to_watch = i;
2624
2625 return count;
2626}
2627
2628static inline void
581d708e
MC		 2629e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2630 int tx_flags, int count)
1da177e4 2631{
1da177e4
LT		 2632 struct e1000_tx_desc *tx_desc = NULL;
2633 struct e1000_buffer *buffer_info;
2634 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2635 unsigned int i;
2636
96838a40 2637 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2638 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2639 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2640 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2641
96838a40 2642 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2643 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2644 }
2645
96838a40 2646 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2647 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2648 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2649 }
2650
96838a40 2651 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2652 txd_lower |= E1000_TXD_CMD_VLE;
2653 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2654 }
2655
2656 i = tx_ring->next_to_use;
2657
96838a40 2658 while (count--) {
1da177e4
LT		 2659 buffer_info = &tx_ring->buffer_info[i];
2660 tx_desc = E1000_TX_DESC(*tx_ring, i);
2661 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2662 tx_desc->lower.data =
2663 cpu_to_le32(txd_lower | buffer_info->length);
2664 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2665 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2666 }
2667
2668 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2669
2670 /* Force memory writes to complete before letting h/w
2671 * know there are new descriptors to fetch. (Only
2672 * applicable for weak-ordered memory model archs,
2673 * such as IA-64). */
2674 wmb();
2675
2676 tx_ring->next_to_use = i;
581d708e 2677 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2678}
2679
2680/**
2681 * 82547 workaround to avoid controller hang in half-duplex environment.
2682 * The workaround is to avoid queuing a large packet that would span
2683 * the internal Tx FIFO ring boundary by notifying the stack to resend
2684 * the packet at a later time. This gives the Tx FIFO an opportunity to
2685 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2686 * to the beginning of the Tx FIFO.
2687 **/
2688
2689#define E1000_FIFO_HDR 0x10
2690#define E1000_82547_PAD_LEN 0x3E0
2691
2692static inline int
2693e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2694{
2695 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2696 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2697
2698 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2699
96838a40 2700 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2701 goto no_fifo_stall_required;
2702
96838a40 2703 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2704 return 1;
2705
96838a40 2706 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2707 atomic_set(&adapter->tx_fifo_stall, 1);
2708 return 1;
2709 }
2710
2711no_fifo_stall_required:
2712 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2713 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2714 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2715 return 0;
2716}
2717
2d7edb92
MC		 2718#define MINIMUM_DHCP_PACKET_SIZE 282
2719static inline int
2720e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2721{
2722 struct e1000_hw *hw = &adapter->hw;
2723 uint16_t length, offset;
96838a40
JB		 2724 if (vlan_tx_tag_present(skb)) {
2725 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2726 ( adapter->hw.mng_cookie.status &
2727 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2728 return 0;
2729 }
20a44028 2730 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 2731 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2732 if ((htons(ETH_P_IP) == eth->h_proto)) {
2733 const struct iphdr *ip =
2d7edb92 2734 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2735 if (IPPROTO_UDP == ip->protocol) {
2736 struct udphdr *udp =
2737 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2738 (ip->ihl << 2));
96838a40 2739 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2740 offset = (uint8_t *)udp + 8 - skb->data;
2741 length = skb->len - offset;
2742
2743 return e1000_mng_write_dhcp_info(hw,
96838a40 2744 (uint8_t *)udp + 8,
2d7edb92
MC		 2745 length);
2746 }
2747 }
2748 }
2749 }
2750 return 0;
2751}
2752
1da177e4
LT		 2753#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2754static int
2755e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2756{
60490fe0 2757 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2758 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2759 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2760 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2761 unsigned int tx_flags = 0;
2762 unsigned int len = skb->len;
2763 unsigned long flags;
2764 unsigned int nr_frags = 0;
2765 unsigned int mss = 0;
2766 int count = 0;
96838a40 2767 int tso;
1da177e4
LT		 2768 unsigned int f;
2769 len -= skb->data_len;
2770
581d708e 2771 tx_ring = adapter->tx_ring;
24025e4e 2772
581d708e 2773 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2774 dev_kfree_skb_any(skb);
2775 return NETDEV_TX_OK;
2776 }
2777
2778#ifdef NETIF_F_TSO
2779 mss = skb_shinfo(skb)->tso_size;
2648345f 2780 /* The controller does a simple calculation to
1da177e4
LT		 2781 * make sure there is enough room in the FIFO before
2782 * initiating the DMA for each buffer. The calc is:
2783 * 4 = ceil(buffer len/mss). To make sure we don't
2784 * overrun the FIFO, adjust the max buffer len if mss
2785 * drops. */
96838a40 2786 if (mss) {
9a3056da 2787 uint8_t hdr_len;
1da177e4
LT		 2788 max_per_txd = min(mss << 2, max_per_txd);
2789 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 2790
9f687888 2791 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
9a3056da
JK		 2792 * points to just header, pull a few bytes of payload from
2793 * frags into skb->data */
2794 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
9f687888
JK		 2795 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
2796 switch (adapter->hw.mac_type) {
2797 unsigned int pull_size;
2798 case e1000_82571:
2799 case e1000_82572:
2800 case e1000_82573:
2801 pull_size = min((unsigned int)4, skb->data_len);
2802 if (!__pskb_pull_tail(skb, pull_size)) {
2803 printk(KERN_ERR
2804 "__pskb_pull_tail failed.\n");
2805 dev_kfree_skb_any(skb);
749dfc70 2806 return NETDEV_TX_OK;
9f687888
JK		 2807 }
2808 len = skb->len - skb->data_len;
2809 break;
2810 default:
2811 /* do nothing */
2812 break;
d74bbd3b 2813 }
9a3056da 2814 }
1da177e4
LT		 2815 }
2816
9a3056da 2817 /* reserve a descriptor for the offload context */
96838a40 2818 if ((mss) || (skb->ip_summed == CHECKSUM_HW))
1da177e4 2819 count++;
2648345f 2820 count++;
1da177e4 2821#else
96838a40 2822 if (skb->ip_summed == CHECKSUM_HW)
1da177e4
LT		 2823 count++;
2824#endif
fd803241
JK		 2825
2826#ifdef NETIF_F_TSO
2827 /* Controller Erratum workaround */
2828 if (!skb->data_len && tx_ring->last_tx_tso &&
0f15a8fa 2829 !skb_shinfo(skb)->tso_size)
fd803241
JK		 2830 count++;
2831#endif
2832
1da177e4
LT		 2833 count += TXD_USE_COUNT(len, max_txd_pwr);
2834
96838a40 2835 if (adapter->pcix_82544)
1da177e4
LT		 2836 count++;
2837
96838a40 2838 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 2839 * in PCI-X mode, so add one more descriptor to the count
2840 */
96838a40 2841 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2842 (len > 2015)))
2843 count++;
2844
1da177e4 2845 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 2846 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 2847 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2848 max_txd_pwr);
96838a40 2849 if (adapter->pcix_82544)
1da177e4
LT		 2850 count += nr_frags;
2851
0f15a8fa
JK		 2852
2853 if (adapter->hw.tx_pkt_filtering &&
2854 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 2855 e1000_transfer_dhcp_info(adapter, skb);
2856
581d708e
MC		 2857 local_irq_save(flags);
2858 if (!spin_trylock(&tx_ring->tx_lock)) {
2859 /* Collision - tell upper layer to requeue */
2860 local_irq_restore(flags);
2861 return NETDEV_TX_LOCKED;
2862 }
1da177e4
LT		 2863
2864 /* need: count + 2 desc gap to keep tail from touching
2865 * head, otherwise try next time */
581d708e 2866 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2867 netif_stop_queue(netdev);
581d708e 2868 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2869 return NETDEV_TX_BUSY;
2870 }
2871
96838a40
JB		 2872 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
2873 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4
LT		 2874 netif_stop_queue(netdev);
2875 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2876 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2877 return NETDEV_TX_BUSY;
2878 }
2879 }
2880
96838a40 2881 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 2882 tx_flags |= E1000_TX_FLAGS_VLAN;
2883 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2884 }
2885
581d708e 2886 first = tx_ring->next_to_use;
96838a40 2887
581d708e 2888 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2889 if (tso < 0) {
2890 dev_kfree_skb_any(skb);
581d708e 2891 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2892 return NETDEV_TX_OK;
2893 }
2894
fd803241
JK		 2895 if (likely(tso)) {
2896 tx_ring->last_tx_tso = 1;
1da177e4 2897 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 2898 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2899 tx_flags |= E1000_TX_FLAGS_CSUM;
2900
2d7edb92 2901 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2902 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2903 * no longer assume, we must. */
581d708e 2904 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 2905 tx_flags |= E1000_TX_FLAGS_IPV4;
2906
581d708e
MC		 2907 e1000_tx_queue(adapter, tx_ring, tx_flags,
2908 e1000_tx_map(adapter, tx_ring, skb, first,
2909 max_per_txd, nr_frags, mss));
1da177e4
LT		 2910
2911 netdev->trans_start = jiffies;
2912
2913 /* Make sure there is space in the ring for the next send. */
581d708e 2914 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2915 netif_stop_queue(netdev);
2916
581d708e 2917 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2918 return NETDEV_TX_OK;
2919}
2920
2921/**
2922 * e1000_tx_timeout - Respond to a Tx Hang
2923 * @netdev: network interface device structure
2924 **/
2925
2926static void
2927e1000_tx_timeout(struct net_device *netdev)
2928{
60490fe0 2929 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2930
2931 /* Do the reset outside of interrupt context */
87041639
JK		 2932 adapter->tx_timeout_count++;
2933 schedule_work(&adapter->reset_task);
1da177e4
LT		 2934}
2935
2936static void
87041639 2937e1000_reset_task(struct net_device *netdev)
1da177e4 2938{
60490fe0 2939 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2940
2941 e1000_down(adapter);
2942 e1000_up(adapter);
2943}
2944
2945/**
2946 * e1000_get_stats - Get System Network Statistics
2947 * @netdev: network interface device structure
2948 *
2949 * Returns the address of the device statistics structure.
2950 * The statistics are actually updated from the timer callback.
2951 **/
2952
2953static struct net_device_stats *
2954e1000_get_stats(struct net_device *netdev)
2955{
60490fe0 2956 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2957
6b7660cd 2958 /* only return the current stats */
1da177e4
LT		 2959 return &adapter->net_stats;
2960}
2961
2962/**
2963 * e1000_change_mtu - Change the Maximum Transfer Unit
2964 * @netdev: network interface device structure
2965 * @new_mtu: new value for maximum frame size
2966 *
2967 * Returns 0 on success, negative on failure
2968 **/
2969
2970static int
2971e1000_change_mtu(struct net_device *netdev, int new_mtu)
2972{
60490fe0 2973 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2974 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 2975 uint16_t eeprom_data = 0;
1da177e4 2976
96838a40
JB		 2977 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
2978 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2979 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 2980 return -EINVAL;
2d7edb92 2981 }
1da177e4 2982
997f5cbd
JK		 2983 /* Adapter-specific max frame size limits. */
2984 switch (adapter->hw.mac_type) {
2985 case e1000_82542_rev2_0:
2986 case e1000_82542_rev2_1:
997f5cbd
JK		 2987 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2988 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 2989 return -EINVAL;
2d7edb92 2990 }
997f5cbd 2991 break;
85b22eb6
JK		 2992 case e1000_82573:
2993 /* only enable jumbo frames if ASPM is disabled completely
2994 * this means both bits must be zero in 0x1A bits 3:2 */
2995 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
2996 &eeprom_data);
2997 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
2998 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2999 DPRINTK(PROBE, ERR,
3000 "Jumbo Frames not supported.\n");
3001 return -EINVAL;
3002 }
3003 break;
3004 }
3005 /* fall through to get support */
997f5cbd
JK		 3006 case e1000_82571:
3007 case e1000_82572:
87041639 3008 case e1000_80003es2lan:
997f5cbd
JK		 3009#define MAX_STD_JUMBO_FRAME_SIZE 9234
3010 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3011 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3012 return -EINVAL;
3013 }
3014 break;
3015 default:
3016 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3017 break;
1da177e4
LT		 3018 }
3019
997f5cbd 3020
997f5cbd 3021 if (adapter->hw.mac_type > e1000_82547_rev_2) {
a1415ee6 3022 adapter->rx_buffer_len = max_frame;
997f5cbd 3023 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
a1415ee6
JK		 3024 } else {
3025 if(unlikely((adapter->hw.mac_type < e1000_82543) &&
3026 (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
3027 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
3028 "on 82542\n");
3029 return -EINVAL;
3030 } else {
3031 if(max_frame <= E1000_RXBUFFER_2048)
3032 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3033 else if(max_frame <= E1000_RXBUFFER_4096)
3034 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3035 else if(max_frame <= E1000_RXBUFFER_8192)
3036 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3037 else if(max_frame <= E1000_RXBUFFER_16384)
3038 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3039 }
3040 }
997f5cbd 3041
2d7edb92
MC		 3042 netdev->mtu = new_mtu;
3043
96838a40 3044 if (netif_running(netdev)) {
1da177e4
LT		 3045 e1000_down(adapter);
3046 e1000_up(adapter);
3047 }
3048
1da177e4
LT		 3049 adapter->hw.max_frame_size = max_frame;
3050
3051 return 0;
3052}
3053
3054/**
3055 * e1000_update_stats - Update the board statistics counters
3056 * @adapter: board private structure
3057 **/
3058
3059void
3060e1000_update_stats(struct e1000_adapter *adapter)
3061{
3062 struct e1000_hw *hw = &adapter->hw;
3063 unsigned long flags;
3064 uint16_t phy_tmp;
3065
3066#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3067
3068 spin_lock_irqsave(&adapter->stats_lock, flags);
3069
3070 /* these counters are modified from e1000_adjust_tbi_stats,
3071 * called from the interrupt context, so they must only
3072 * be written while holding adapter->stats_lock
3073 */
3074
3075 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3076 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3077 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3078 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3079 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3080 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3081 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3082 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3083 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3084 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3085 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3086 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3087 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3088
3089 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3090 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3091 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3092 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3093 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3094 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3095 adapter->stats.dc += E1000_READ_REG(hw, DC);
3096 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3097 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3098 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3099 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3100 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3101 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3102 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3103 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3104 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3105 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3106 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3107 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3108 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3109 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3110 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3111 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3112 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3113 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3114 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3115 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3116 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3117 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3118 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3119 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3120 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3121 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3122 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3123
3124 /* used for adaptive IFS */
3125
3126 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3127 adapter->stats.tpt += hw->tx_packet_delta;
3128 hw->collision_delta = E1000_READ_REG(hw, COLC);
3129 adapter->stats.colc += hw->collision_delta;
3130
96838a40 3131 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3132 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3133 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3134 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3135 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3136 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3137 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3138 }
96838a40 3139 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3140 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3141 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3142 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3143 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3144 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3145 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3146 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3147 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3148 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3149 }
1da177e4
LT		 3150
3151 /* Fill out the OS statistics structure */
3152
3153 adapter->net_stats.rx_packets = adapter->stats.gprc;
3154 adapter->net_stats.tx_packets = adapter->stats.gptc;
3155 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3156 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3157 adapter->net_stats.multicast = adapter->stats.mprc;
3158 adapter->net_stats.collisions = adapter->stats.colc;
3159
3160 /* Rx Errors */
3161
87041639
JK		 3162 /* RLEC on some newer hardware can be incorrect so build
3163 * our own version based on RUC and ROC */
1da177e4
LT		 3164 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3165 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3166 adapter->stats.ruc + adapter->stats.roc +
3167 adapter->stats.cexterr;
6b7660cd 3168 adapter->net_stats.rx_dropped = 0;
87041639
JK		 3169 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3170 adapter->stats.roc;
1da177e4
LT		 3171 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3172 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3173 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3174
3175 /* Tx Errors */
3176
3177 adapter->net_stats.tx_errors = adapter->stats.ecol +
3178 adapter->stats.latecol;
3179 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3180 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3181 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3182
3183 /* Tx Dropped needs to be maintained elsewhere */
3184
3185 /* Phy Stats */
3186
96838a40
JB		 3187 if (hw->media_type == e1000_media_type_copper) {
3188 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3189 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3190 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3191 adapter->phy_stats.idle_errors += phy_tmp;
3192 }
3193
96838a40 3194 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3195 (hw->phy_type == e1000_phy_m88) &&
3196 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3197 adapter->phy_stats.receive_errors += phy_tmp;
3198 }
3199
3200 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3201}
3202
3203/**
3204 * e1000_intr - Interrupt Handler
3205 * @irq: interrupt number
3206 * @data: pointer to a network interface device structure
3207 * @pt_regs: CPU registers structure
3208 **/
3209
3210static irqreturn_t
3211e1000_intr(int irq, void *data, struct pt_regs *regs)
3212{
3213 struct net_device *netdev = data;
60490fe0 3214 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3215 struct e1000_hw *hw = &adapter->hw;
87041639 3216 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3217#ifndef CONFIG_E1000_NAPI
581d708e 3218 int i;
1e613fd9
JK		 3219#else
3220 /* Interrupt Auto-Mask...upon reading ICR,
3221 * interrupts are masked. No need for the
3222 * IMC write, but it does mean we should
3223 * account for it ASAP. */
3224 if (likely(hw->mac_type >= e1000_82571))
3225 atomic_inc(&adapter->irq_sem);
be2b28ed 3226#endif
1da177e4 3227
1e613fd9
JK		 3228 if (unlikely(!icr)) {
3229#ifdef CONFIG_E1000_NAPI
3230 if (hw->mac_type >= e1000_82571)
3231 e1000_irq_enable(adapter);
3232#endif
1da177e4 3233 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3234 }
1da177e4 3235
96838a40 3236 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3237 hw->get_link_status = 1;
87041639
JK		 3238 /* 80003ES2LAN workaround--
3239 * For packet buffer work-around on link down event;
3240 * disable receives here in the ISR and
3241 * reset adapter in watchdog
3242 */
3243 if (netif_carrier_ok(netdev) &&
3244 (adapter->hw.mac_type == e1000_80003es2lan)) {
3245 /* disable receives */
3246 rctl = E1000_READ_REG(hw, RCTL);
3247 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3248 }
1da177e4
LT		 3249 mod_timer(&adapter->watchdog_timer, jiffies);
3250 }
3251
3252#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3253 if (unlikely(hw->mac_type < e1000_82571)) {
3254 atomic_inc(&adapter->irq_sem);
3255 E1000_WRITE_REG(hw, IMC, ~0);
3256 E1000_WRITE_FLUSH(hw);
3257 }
581d708e
MC		 3258 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3259 __netif_rx_schedule(&adapter->polling_netdev[0]);
3260 else
3261 e1000_irq_enable(adapter);
c1605eb3 3262#else
1da177e4 3263 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3264 * Due to Hub Link bus being occupied, an interrupt
3265 * de-assertion message is not able to be sent.
3266 * When an interrupt assertion message is generated later,
3267 * two messages are re-ordered and sent out.
3268 * That causes APIC to think 82547 is in de-assertion
3269 * state, while 82547 is in assertion state, resulting
3270 * in dead lock. Writing IMC forces 82547 into
3271 * de-assertion state.
3272 */
3273 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3274 atomic_inc(&adapter->irq_sem);
2648345f 3275 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3276 }
3277
96838a40
JB		 3278 for (i = 0; i < E1000_MAX_INTR; i++)
3279 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3280 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3281 break;
3282
96838a40 3283 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3284 e1000_irq_enable(adapter);
581d708e 3285
c1605eb3 3286#endif
1da177e4
LT		 3287
3288 return IRQ_HANDLED;
3289}
3290
3291#ifdef CONFIG_E1000_NAPI
3292/**
3293 * e1000_clean - NAPI Rx polling callback
3294 * @adapter: board private structure
3295 **/
3296
3297static int
581d708e 3298e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3299{
581d708e
MC		 3300 struct e1000_adapter *adapter;
3301 int work_to_do = min(*budget, poll_dev->quota);
38bd3b26 3302 int tx_cleaned = 0, i = 0, work_done = 0;
581d708e
MC		 3303
3304 /* Must NOT use netdev_priv macro here. */
3305 adapter = poll_dev->priv;
3306
3307 /* Keep link state information with original netdev */
3308 if (!netif_carrier_ok(adapter->netdev))
3309 goto quit_polling;
2648345f 3310
581d708e
MC		 3311 while (poll_dev != &adapter->polling_netdev[i]) {
3312 i++;
5d9428de 3313 BUG_ON(i == adapter->num_rx_queues);
581d708e
MC		 3314 }
3315
8241e35e
JK		 3316 if (likely(adapter->num_tx_queues == 1)) {
3317 /* e1000_clean is called per-cpu. This lock protects
3318 * tx_ring[0] from being cleaned by multiple cpus
3319 * simultaneously. A failure obtaining the lock means
3320 * tx_ring[0] is currently being cleaned anyway. */
3321 if (spin_trylock(&adapter->tx_queue_lock)) {
3322 tx_cleaned = e1000_clean_tx_irq(adapter,
3323 &adapter->tx_ring[0]);
3324 spin_unlock(&adapter->tx_queue_lock);
3325 }
3326 } else
3327 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3328
581d708e
MC		 3329 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3330 &work_done, work_to_do);
1da177e4
LT		 3331
3332 *budget -= work_done;
581d708e 3333 poll_dev->quota -= work_done;
96838a40 3334
2b02893e 3335 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3336 if ((!tx_cleaned && (work_done == 0)) ||
581d708e
MC		 3337 !netif_running(adapter->netdev)) {
3338quit_polling:
3339 netif_rx_complete(poll_dev);
1da177e4
LT		 3340 e1000_irq_enable(adapter);
3341 return 0;
3342 }
3343
3344 return 1;
3345}
3346
3347#endif
3348/**
3349 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3350 * @adapter: board private structure
3351 **/
3352
3353static boolean_t
581d708e
MC		 3354e1000_clean_tx_irq(struct e1000_adapter *adapter,
3355 struct e1000_tx_ring *tx_ring)
1da177e4 3356{
1da177e4
LT		 3357 struct net_device *netdev = adapter->netdev;
3358 struct e1000_tx_desc *tx_desc, *eop_desc;
3359 struct e1000_buffer *buffer_info;
3360 unsigned int i, eop;
2a1af5d7
JK		 3361#ifdef CONFIG_E1000_NAPI
3362 unsigned int count = 0;
3363#endif
1da177e4
LT		 3364 boolean_t cleaned = FALSE;
3365
3366 i = tx_ring->next_to_clean;
3367 eop = tx_ring->buffer_info[i].next_to_watch;
3368 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3369
581d708e 3370 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3371 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3372 tx_desc = E1000_TX_DESC(*tx_ring, i);
3373 buffer_info = &tx_ring->buffer_info[i];
3374 cleaned = (i == eop);
3375
fd803241 3376 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3377 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3378
96838a40 3379 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3380 }
581d708e 3381
7bfa4816 3382
1da177e4
LT		 3383 eop = tx_ring->buffer_info[i].next_to_watch;
3384 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3385#ifdef CONFIG_E1000_NAPI
3386#define E1000_TX_WEIGHT 64
3387 /* weight of a sort for tx, to avoid endless transmit cleanup */
3388 if (count++ == E1000_TX_WEIGHT) break;
3389#endif
1da177e4
LT		 3390 }
3391
3392 tx_ring->next_to_clean = i;
3393
581d708e 3394 spin_lock(&tx_ring->tx_lock);
1da177e4 3395
96838a40 3396 if (unlikely(cleaned && netif_queue_stopped(netdev) &&
1da177e4
LT		 3397 netif_carrier_ok(netdev)))
3398 netif_wake_queue(netdev);
3399
581d708e 3400 spin_unlock(&tx_ring->tx_lock);
2648345f 3401
581d708e 3402 if (adapter->detect_tx_hung) {
2648345f 3403 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3404 * check with the clearing of time_stamp and movement of i */
3405 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3406 if (tx_ring->buffer_info[eop].dma &&
3407 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 3408 (adapter->tx_timeout_factor * HZ))
70b8f1e1 3409 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3410 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3411
3412 /* detected Tx unit hang */
c6963ef5 3413 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3414 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3415 " TDH <%x>\n"
3416 " TDT <%x>\n"
3417 " next_to_use <%x>\n"
3418 " next_to_clean <%x>\n"
3419 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3420 " time_stamp <%lx>\n"
3421 " next_to_watch <%x>\n"
3422 " jiffies <%lx>\n"
3423 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3424 (unsigned long)((tx_ring - adapter->tx_ring) /
3425 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3426 readl(adapter->hw.hw_addr + tx_ring->tdh),
3427 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3428 tx_ring->next_to_use,
392137fa
JK		 3429 tx_ring->next_to_clean,
3430 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3431 eop,
3432 jiffies,
3433 eop_desc->upper.fields.status);
1da177e4 3434 netif_stop_queue(netdev);
70b8f1e1 3435 }
1da177e4 3436 }
1da177e4
LT		 3437 return cleaned;
3438}
3439
3440/**
3441 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3442 * @adapter: board private structure
3443 * @status_err: receive descriptor status and error fields
3444 * @csum: receive descriptor csum field
3445 * @sk_buff: socket buffer with received data
1da177e4
LT		 3446 **/
3447
3448static inline void
3449e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3450 uint32_t status_err, uint32_t csum,
3451 struct sk_buff *skb)
1da177e4 3452{
2d7edb92
MC		 3453 uint16_t status = (uint16_t)status_err;
3454 uint8_t errors = (uint8_t)(status_err >> 24);
3455 skb->ip_summed = CHECKSUM_NONE;
3456
1da177e4 3457 /* 82543 or newer only */
96838a40 3458 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3459 /* Ignore Checksum bit is set */
96838a40 3460 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3461 /* TCP/UDP checksum error bit is set */
96838a40 3462 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3463 /* let the stack verify checksum errors */
1da177e4 3464 adapter->hw_csum_err++;
2d7edb92
MC		 3465 return;
3466 }
3467 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3468 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3469 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3470 return;
1da177e4 3471 } else {
96838a40 3472 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3473 return;
3474 }
3475 /* It must be a TCP or UDP packet with a valid checksum */
3476 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3477 /* TCP checksum is good */
3478 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3479 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3480 /* IP fragment with UDP payload */
3481 /* Hardware complements the payload checksum, so we undo it
3482 * and then put the value in host order for further stack use.
3483 */
3484 csum = ntohl(csum ^ 0xFFFF);
3485 skb->csum = csum;
3486 skb->ip_summed = CHECKSUM_HW;
1da177e4 3487 }
2d7edb92 3488 adapter->hw_csum_good++;
1da177e4
LT		 3489}
3490
3491/**
2d7edb92 3492 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3493 * @adapter: board private structure
3494 **/
3495
3496static boolean_t
3497#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3498e1000_clean_rx_irq(struct e1000_adapter *adapter,
3499 struct e1000_rx_ring *rx_ring,
3500 int *work_done, int work_to_do)
1da177e4 3501#else
581d708e
MC		 3502e1000_clean_rx_irq(struct e1000_adapter *adapter,
3503 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3504#endif
3505{
1da177e4
LT		 3506 struct net_device *netdev = adapter->netdev;
3507 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 3508 struct e1000_rx_desc *rx_desc, *next_rxd;
3509 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 3510 unsigned long flags;
3511 uint32_t length;
3512 uint8_t last_byte;
3513 unsigned int i;
72d64a43 3514 int cleaned_count = 0;
a1415ee6 3515 boolean_t cleaned = FALSE;
1da177e4
LT		 3516
3517 i = rx_ring->next_to_clean;
3518 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3519 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3520
b92ff8ee 3521 while (rx_desc->status & E1000_RXD_STAT_DD) {
86c3d59f 3522 struct sk_buff *skb, *next_skb;
a292ca6e 3523 u8 status;
1da177e4 3524#ifdef CONFIG_E1000_NAPI
96838a40 3525 if (*work_done >= work_to_do)
1da177e4
LT		 3526 break;
3527 (*work_done)++;
3528#endif
a292ca6e 3529 status = rx_desc->status;
b92ff8ee 3530 skb = buffer_info->skb;
86c3d59f
JB		 3531 buffer_info->skb = NULL;
3532
30320be8
JK		 3533 prefetch(skb->data - NET_IP_ALIGN);
3534
86c3d59f
JB		 3535 if (++i == rx_ring->count) i = 0;
3536 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 3537 prefetch(next_rxd);
3538
86c3d59f
JB		 3539 next_buffer = &rx_ring->buffer_info[i];
3540 next_skb = next_buffer->skb;
30320be8 3541 prefetch(next_skb->data - NET_IP_ALIGN);
86c3d59f 3542
72d64a43
JK		 3543 cleaned = TRUE;
3544 cleaned_count++;
a292ca6e
JK		 3545 pci_unmap_single(pdev,
3546 buffer_info->dma,
3547 buffer_info->length,
1da177e4
LT		 3548 PCI_DMA_FROMDEVICE);
3549
1da177e4
LT		 3550 length = le16_to_cpu(rx_desc->length);
3551
a1415ee6
JK		 3552 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3553 /* All receives must fit into a single buffer */
3554 E1000_DBG("%s: Receive packet consumed multiple"
3555 " buffers\n", netdev->name);
3556 dev_kfree_skb_irq(skb);
1da177e4
LT		 3557 goto next_desc;
3558 }
3559
96838a40 3560 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3561 last_byte = *(skb->data + length - 1);
b92ff8ee 3562 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3563 rx_desc->errors, length, last_byte)) {
3564 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3565 e1000_tbi_adjust_stats(&adapter->hw,
3566 &adapter->stats,
1da177e4
LT		 3567 length, skb->data);
3568 spin_unlock_irqrestore(&adapter->stats_lock,
3569 flags);
3570 length--;
3571 } else {
3572 dev_kfree_skb_irq(skb);
3573 goto next_desc;
3574 }
3575 }
3576
a292ca6e
JK		 3577 /* code added for copybreak, this should improve
3578 * performance for small packets with large amounts
3579 * of reassembly being done in the stack */
3580#define E1000_CB_LENGTH 256
a1415ee6 3581 if (length < E1000_CB_LENGTH) {
a292ca6e
JK		 3582 struct sk_buff *new_skb =
3583 dev_alloc_skb(length + NET_IP_ALIGN);
3584 if (new_skb) {
3585 skb_reserve(new_skb, NET_IP_ALIGN);
3586 new_skb->dev = netdev;
3587 memcpy(new_skb->data - NET_IP_ALIGN,
3588 skb->data - NET_IP_ALIGN,
3589 length + NET_IP_ALIGN);
3590 /* save the skb in buffer_info as good */
3591 buffer_info->skb = skb;
3592 skb = new_skb;
3593 skb_put(skb, length);
3594 }
a1415ee6
JK		 3595 } else
3596 skb_put(skb, length);
a292ca6e
JK		 3597
3598 /* end copybreak code */
1da177e4
LT		 3599
3600 /* Receive Checksum Offload */
a292ca6e
JK		 3601 e1000_rx_checksum(adapter,
3602 (uint32_t)(status) |
2d7edb92 3603 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 3604 le16_to_cpu(rx_desc->csum), skb);
96838a40 3605
1da177e4
LT		 3606 skb->protocol = eth_type_trans(skb, netdev);
3607#ifdef CONFIG_E1000_NAPI
96838a40 3608 if (unlikely(adapter->vlgrp &&
a292ca6e 3609 (status & E1000_RXD_STAT_VP))) {
1da177e4 3610 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3611 le16_to_cpu(rx_desc->special) &
3612 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3613 } else {
3614 netif_receive_skb(skb);
3615 }
3616#else /* CONFIG_E1000_NAPI */
96838a40 3617 if (unlikely(adapter->vlgrp &&
b92ff8ee 3618 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3619 vlan_hwaccel_rx(skb, adapter->vlgrp,
3620 le16_to_cpu(rx_desc->special) &
3621 E1000_RXD_SPC_VLAN_MASK);
3622 } else {
3623 netif_rx(skb);
3624 }
3625#endif /* CONFIG_E1000_NAPI */
3626 netdev->last_rx = jiffies;
3627
3628next_desc:
3629 rx_desc->status = 0;
1da177e4 3630
72d64a43
JK		 3631 /* return some buffers to hardware, one at a time is too slow */
3632 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3633 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3634 cleaned_count = 0;
3635 }
3636
30320be8 3637 /* use prefetched values */
86c3d59f
JB		 3638 rx_desc = next_rxd;
3639 buffer_info = next_buffer;
1da177e4 3640 }
1da177e4 3641 rx_ring->next_to_clean = i;
72d64a43
JK		 3642
3643 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3644 if (cleaned_count)
3645 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3646
3647 return cleaned;
3648}
3649
3650/**
3651 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3652 * @adapter: board private structure
3653 **/
3654
3655static boolean_t
3656#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3657e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3658 struct e1000_rx_ring *rx_ring,
3659 int *work_done, int work_to_do)
2d7edb92 3660#else
581d708e
MC		 3661e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3662 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3663#endif
3664{
86c3d59f 3665 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 3666 struct net_device *netdev = adapter->netdev;
3667 struct pci_dev *pdev = adapter->pdev;
86c3d59f 3668 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 3669 struct e1000_ps_page *ps_page;
3670 struct e1000_ps_page_dma *ps_page_dma;
86c3d59f 3671 struct sk_buff *skb, *next_skb;
2d7edb92
MC		 3672 unsigned int i, j;
3673 uint32_t length, staterr;
72d64a43 3674 int cleaned_count = 0;
2d7edb92
MC		 3675 boolean_t cleaned = FALSE;
3676
3677 i = rx_ring->next_to_clean;
3678 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3679 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92 3680
96838a40 3681 while (staterr & E1000_RXD_STAT_DD) {
30320be8 3682 buffer_info = &rx_ring->buffer_info[i];
2d7edb92
MC		 3683 ps_page = &rx_ring->ps_page[i];
3684 ps_page_dma = &rx_ring->ps_page_dma[i];
3685#ifdef CONFIG_E1000_NAPI
96838a40 3686 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3687 break;
3688 (*work_done)++;
3689#endif
86c3d59f
JB		 3690 skb = buffer_info->skb;
3691
30320be8
JK		 3692 /* in the packet split case this is header only */
3693 prefetch(skb->data - NET_IP_ALIGN);
3694
86c3d59f
JB		 3695 if (++i == rx_ring->count) i = 0;
3696 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 3697 prefetch(next_rxd);
3698
86c3d59f
JB		 3699 next_buffer = &rx_ring->buffer_info[i];
3700 next_skb = next_buffer->skb;
30320be8 3701 prefetch(next_skb->data - NET_IP_ALIGN);
86c3d59f 3702
2d7edb92 3703 cleaned = TRUE;
72d64a43 3704 cleaned_count++;
2d7edb92
MC		 3705 pci_unmap_single(pdev, buffer_info->dma,
3706 buffer_info->length,
3707 PCI_DMA_FROMDEVICE);
3708
96838a40 3709 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3710 E1000_DBG("%s: Packet Split buffers didn't pick up"
3711 " the full packet\n", netdev->name);
3712 dev_kfree_skb_irq(skb);
3713 goto next_desc;
3714 }
1da177e4 3715
96838a40 3716 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3717 dev_kfree_skb_irq(skb);
3718 goto next_desc;
3719 }
3720
3721 length = le16_to_cpu(rx_desc->wb.middle.length0);
3722
96838a40 3723 if (unlikely(!length)) {
2d7edb92
MC		 3724 E1000_DBG("%s: Last part of the packet spanning"
3725 " multiple descriptors\n", netdev->name);
3726 dev_kfree_skb_irq(skb);
3727 goto next_desc;
3728 }
3729
3730 /* Good Receive */
3731 skb_put(skb, length);
3732
dc7c6add
JK		 3733 {
3734 /* this looks ugly, but it seems compiler issues make it
3735 more efficient than reusing j */
3736 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
3737
3738 /* page alloc/put takes too long and effects small packet
3739 * throughput, so unsplit small packets and save the alloc/put*/
3740 if (l1 && ((length + l1) < E1000_CB_LENGTH)) {
3741 u8 *vaddr;
3742 /* there is no documentation about how to call
3743 * kmap_atomic, so we can't hold the mapping
3744 * very long */
3745 pci_dma_sync_single_for_cpu(pdev,
3746 ps_page_dma->ps_page_dma[0],
3747 PAGE_SIZE,
3748 PCI_DMA_FROMDEVICE);
3749 vaddr = kmap_atomic(ps_page->ps_page[0],
3750 KM_SKB_DATA_SOFTIRQ);
3751 memcpy(skb->tail, vaddr, l1);
3752 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
3753 pci_dma_sync_single_for_device(pdev,
3754 ps_page_dma->ps_page_dma[0],
3755 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3756 skb_put(skb, l1);
3757 length += l1;
3758 goto copydone;
3759 } /* if */
3760 }
3761
96838a40 3762 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 3763 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 3764 break;
2d7edb92
MC		 3765 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3766 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3767 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 3768 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
3769 length);
2d7edb92 3770 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 3771 skb->len += length;
3772 skb->data_len += length;
3773 }
3774
dc7c6add 3775copydone:
2d7edb92 3776 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 3777 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 3778 skb->protocol = eth_type_trans(skb, netdev);
3779
96838a40 3780 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 3781 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 3782 adapter->rx_hdr_split++;
2d7edb92 3783#ifdef CONFIG_E1000_NAPI
96838a40 3784 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3785 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3786 le16_to_cpu(rx_desc->wb.middle.vlan) &
3787 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3788 } else {
3789 netif_receive_skb(skb);
3790 }
3791#else /* CONFIG_E1000_NAPI */
96838a40 3792 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3793 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3794 le16_to_cpu(rx_desc->wb.middle.vlan) &
3795 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3796 } else {
3797 netif_rx(skb);
3798 }
3799#endif /* CONFIG_E1000_NAPI */
3800 netdev->last_rx = jiffies;
3801
3802next_desc:
c3d7a3a4 3803 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 3804 buffer_info->skb = NULL;
2d7edb92 3805
72d64a43
JK		 3806 /* return some buffers to hardware, one at a time is too slow */
3807 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3808 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3809 cleaned_count = 0;
3810 }
3811
30320be8 3812 /* use prefetched values */
86c3d59f
JB		 3813 rx_desc = next_rxd;
3814 buffer_info = next_buffer;
3815
683a38f3 3816 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3817 }
3818 rx_ring->next_to_clean = i;
72d64a43
JK		 3819
3820 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3821 if (cleaned_count)
3822 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3823
3824 return cleaned;
3825}
3826
3827/**
2d7edb92 3828 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3829 * @adapter: address of board private structure
3830 **/
3831
3832static void
581d708e 3833e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3834 struct e1000_rx_ring *rx_ring,
a292ca6e 3835 int cleaned_count)
1da177e4 3836{
1da177e4
LT		 3837 struct net_device *netdev = adapter->netdev;
3838 struct pci_dev *pdev = adapter->pdev;
3839 struct e1000_rx_desc *rx_desc;
3840 struct e1000_buffer *buffer_info;
3841 struct sk_buff *skb;
2648345f
MC		 3842 unsigned int i;
3843 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3844
3845 i = rx_ring->next_to_use;
3846 buffer_info = &rx_ring->buffer_info[i];
3847
a292ca6e
JK		 3848 while (cleaned_count--) {
3849 if (!(skb = buffer_info->skb))
3850 skb = dev_alloc_skb(bufsz);
3851 else {
3852 skb_trim(skb, 0);
3853 goto map_skb;
3854 }
3855
96838a40 3856 if (unlikely(!skb)) {
1da177e4 3857 /* Better luck next round */
72d64a43 3858 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 3859 break;
3860 }
3861
2648345f 3862 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3863 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3864 struct sk_buff *oldskb = skb;
2648345f
MC		 3865 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3866 "at %p\n", bufsz, skb->data);
3867 /* Try again, without freeing the previous */
1da177e4 3868 skb = dev_alloc_skb(bufsz);
2648345f 3869 /* Failed allocation, critical failure */
1da177e4
LT		 3870 if (!skb) {
3871 dev_kfree_skb(oldskb);
3872 break;
3873 }
2648345f 3874
1da177e4
LT		 3875 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3876 /* give up */
3877 dev_kfree_skb(skb);
3878 dev_kfree_skb(oldskb);
3879 break; /* while !buffer_info->skb */
3880 } else {
2648345f 3881 /* Use new allocation */
1da177e4
LT		 3882 dev_kfree_skb(oldskb);
3883 }
3884 }
1da177e4
LT		 3885 /* Make buffer alignment 2 beyond a 16 byte boundary
3886 * this will result in a 16 byte aligned IP header after
3887 * the 14 byte MAC header is removed
3888 */
3889 skb_reserve(skb, NET_IP_ALIGN);
3890
3891 skb->dev = netdev;
3892
3893 buffer_info->skb = skb;
3894 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 3895map_skb:
1da177e4
LT		 3896 buffer_info->dma = pci_map_single(pdev,
3897 skb->data,
3898 adapter->rx_buffer_len,
3899 PCI_DMA_FROMDEVICE);
3900
2648345f
MC		 3901 /* Fix for errata 23, can't cross 64kB boundary */
3902 if (!e1000_check_64k_bound(adapter,
3903 (void *)(unsigned long)buffer_info->dma,
3904 adapter->rx_buffer_len)) {
3905 DPRINTK(RX_ERR, ERR,
3906 "dma align check failed: %u bytes at %p\n",
3907 adapter->rx_buffer_len,
3908 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3909 dev_kfree_skb(skb);
3910 buffer_info->skb = NULL;
3911
2648345f 3912 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3913 adapter->rx_buffer_len,
3914 PCI_DMA_FROMDEVICE);
3915
3916 break; /* while !buffer_info->skb */
3917 }
1da177e4
LT		 3918 rx_desc = E1000_RX_DESC(*rx_ring, i);
3919 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3920
96838a40
JB		 3921 if (unlikely(++i == rx_ring->count))
3922 i = 0;
1da177e4
LT		 3923 buffer_info = &rx_ring->buffer_info[i];
3924 }
3925
b92ff8ee
JB		 3926 if (likely(rx_ring->next_to_use != i)) {
3927 rx_ring->next_to_use = i;
3928 if (unlikely(i-- == 0))
3929 i = (rx_ring->count - 1);
3930
3931 /* Force memory writes to complete before letting h/w
3932 * know there are new descriptors to fetch. (Only
3933 * applicable for weak-ordered memory model archs,
3934 * such as IA-64). */
3935 wmb();
3936 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
3937 }
1da177e4
LT		 3938}
3939
2d7edb92
MC		 3940/**
3941 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3942 * @adapter: address of board private structure
3943 **/
3944
3945static void
581d708e 3946e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 3947 struct e1000_rx_ring *rx_ring,
3948 int cleaned_count)
2d7edb92 3949{
2d7edb92
MC		 3950 struct net_device *netdev = adapter->netdev;
3951 struct pci_dev *pdev = adapter->pdev;
3952 union e1000_rx_desc_packet_split *rx_desc;
3953 struct e1000_buffer *buffer_info;
3954 struct e1000_ps_page *ps_page;
3955 struct e1000_ps_page_dma *ps_page_dma;
3956 struct sk_buff *skb;
3957 unsigned int i, j;
3958
3959 i = rx_ring->next_to_use;
3960 buffer_info = &rx_ring->buffer_info[i];
3961 ps_page = &rx_ring->ps_page[i];
3962 ps_page_dma = &rx_ring->ps_page_dma[i];
3963
72d64a43 3964 while (cleaned_count--) {
2d7edb92
MC		 3965 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3966
96838a40 3967 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 3968 if (j < adapter->rx_ps_pages) {
3969 if (likely(!ps_page->ps_page[j])) {
3970 ps_page->ps_page[j] =
3971 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 3972 if (unlikely(!ps_page->ps_page[j])) {
3973 adapter->alloc_rx_buff_failed++;
e4c811c9 3974 goto no_buffers;
b92ff8ee 3975 }
e4c811c9
MC		 3976 ps_page_dma->ps_page_dma[j] =
3977 pci_map_page(pdev,
3978 ps_page->ps_page[j],
3979 0, PAGE_SIZE,
3980 PCI_DMA_FROMDEVICE);
3981 }
3982 /* Refresh the desc even if buffer_addrs didn't
96838a40 3983 * change because each write-back erases
e4c811c9
MC		 3984 * this info.
3985 */
3986 rx_desc->read.buffer_addr[j+1] =
3987 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3988 } else
3989 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 3990 }
3991
3992 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3993
b92ff8ee
JB		 3994 if (unlikely(!skb)) {
3995 adapter->alloc_rx_buff_failed++;
2d7edb92 3996 break;
b92ff8ee 3997 }
2d7edb92
MC		 3998
3999 /* Make buffer alignment 2 beyond a 16 byte boundary
4000 * this will result in a 16 byte aligned IP header after
4001 * the 14 byte MAC header is removed
4002 */
4003 skb_reserve(skb, NET_IP_ALIGN);
4004
4005 skb->dev = netdev;
4006
4007 buffer_info->skb = skb;
4008 buffer_info->length = adapter->rx_ps_bsize0;
4009 buffer_info->dma = pci_map_single(pdev, skb->data,
4010 adapter->rx_ps_bsize0,
4011 PCI_DMA_FROMDEVICE);
4012
4013 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4014
96838a40 4015 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4016 buffer_info = &rx_ring->buffer_info[i];
4017 ps_page = &rx_ring->ps_page[i];
4018 ps_page_dma = &rx_ring->ps_page_dma[i];
4019 }
4020
4021no_buffers:
b92ff8ee
JB		 4022 if (likely(rx_ring->next_to_use != i)) {
4023 rx_ring->next_to_use = i;
4024 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4025
4026 /* Force memory writes to complete before letting h/w
4027 * know there are new descriptors to fetch. (Only
4028 * applicable for weak-ordered memory model archs,
4029 * such as IA-64). */
4030 wmb();
4031 /* Hardware increments by 16 bytes, but packet split
4032 * descriptors are 32 bytes...so we increment tail
4033 * twice as much.
4034 */
4035 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4036 }
2d7edb92
MC		 4037}
4038
1da177e4
LT		 4039/**
4040 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4041 * @adapter:
4042 **/
4043
4044static void
4045e1000_smartspeed(struct e1000_adapter *adapter)
4046{
4047 uint16_t phy_status;
4048 uint16_t phy_ctrl;
4049
96838a40 4050 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4051 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4052 return;
4053
96838a40 4054 if (adapter->smartspeed == 0) {
1da177e4
LT		 4055 /* If Master/Slave config fault is asserted twice,
4056 * we assume back-to-back */
4057 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4058 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4059 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4060 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4061 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4062 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4063 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4064 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4065 phy_ctrl);
4066 adapter->smartspeed++;
96838a40 4067 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4068 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4069 &phy_ctrl)) {
4070 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4071 MII_CR_RESTART_AUTO_NEG);
4072 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4073 phy_ctrl);
4074 }
4075 }
4076 return;
96838a40 4077 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4078 /* If still no link, perhaps using 2/3 pair cable */
4079 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4080 phy_ctrl |= CR_1000T_MS_ENABLE;
4081 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4082 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4083 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4084 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4085 MII_CR_RESTART_AUTO_NEG);
4086 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4087 }
4088 }
4089 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4090 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4091 adapter->smartspeed = 0;
4092}
4093
4094/**
4095 * e1000_ioctl -
4096 * @netdev:
4097 * @ifreq:
4098 * @cmd:
4099 **/
4100
4101static int
4102e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4103{
4104 switch (cmd) {
4105 case SIOCGMIIPHY:
4106 case SIOCGMIIREG:
4107 case SIOCSMIIREG:
4108 return e1000_mii_ioctl(netdev, ifr, cmd);
4109 default:
4110 return -EOPNOTSUPP;
4111 }
4112}
4113
4114/**
4115 * e1000_mii_ioctl -
4116 * @netdev:
4117 * @ifreq:
4118 * @cmd:
4119 **/
4120
4121static int
4122e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4123{
60490fe0 4124 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4125 struct mii_ioctl_data *data = if_mii(ifr);
4126 int retval;
4127 uint16_t mii_reg;
4128 uint16_t spddplx;
97876fc6 4129 unsigned long flags;
1da177e4 4130
96838a40 4131 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4132 return -EOPNOTSUPP;
4133
4134 switch (cmd) {
4135 case SIOCGMIIPHY:
4136 data->phy_id = adapter->hw.phy_addr;
4137 break;
4138 case SIOCGMIIREG:
96838a40 4139 if (!capable(CAP_NET_ADMIN))
1da177e4 4140 return -EPERM;
97876fc6 4141 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4142 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4143 &data->val_out)) {
4144 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4145 return -EIO;
97876fc6
MC		 4146 }
4147 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4148 break;
4149 case SIOCSMIIREG:
96838a40 4150 if (!capable(CAP_NET_ADMIN))
1da177e4 4151 return -EPERM;
96838a40 4152 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4153 return -EFAULT;
4154 mii_reg = data->val_in;
97876fc6 4155 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4156 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4157 mii_reg)) {
4158 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4159 return -EIO;
97876fc6 4160 }
cb764326 4161 if (adapter->hw.phy_type == e1000_media_type_copper) {
1da177e4
LT		 4162 switch (data->reg_num) {
4163 case PHY_CTRL:
96838a40 4164 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4165 break;
96838a40 4166 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4167 adapter->hw.autoneg = 1;
4168 adapter->hw.autoneg_advertised = 0x2F;
4169 } else {
4170 if (mii_reg & 0x40)
4171 spddplx = SPEED_1000;
4172 else if (mii_reg & 0x2000)
4173 spddplx = SPEED_100;
4174 else
4175 spddplx = SPEED_10;
4176 spddplx += (mii_reg & 0x100)
cb764326
JK		 4177 ? DUPLEX_FULL :
4178 DUPLEX_HALF;
1da177e4
LT		 4179 retval = e1000_set_spd_dplx(adapter,
4180 spddplx);
96838a40 4181 if (retval) {
97876fc6 4182 spin_unlock_irqrestore(
96838a40 4183 &adapter->stats_lock,
97876fc6 4184 flags);
1da177e4 4185 return retval;
97876fc6 4186 }
1da177e4 4187 }
96838a40 4188 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4189 e1000_down(adapter);
4190 e1000_up(adapter);
4191 } else
4192 e1000_reset(adapter);
4193 break;
4194 case M88E1000_PHY_SPEC_CTRL:
4195 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4196 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4197 spin_unlock_irqrestore(
4198 &adapter->stats_lock, flags);
1da177e4 4199 return -EIO;
97876fc6 4200 }
1da177e4
LT		 4201 break;
4202 }
4203 } else {
4204 switch (data->reg_num) {
4205 case PHY_CTRL:
96838a40 4206 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4207 break;
96838a40 4208 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4209 e1000_down(adapter);
4210 e1000_up(adapter);
4211 } else
4212 e1000_reset(adapter);
4213 break;
4214 }
4215 }
97876fc6 4216 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4217 break;
4218 default:
4219 return -EOPNOTSUPP;
4220 }
4221 return E1000_SUCCESS;
4222}
4223
4224void
4225e1000_pci_set_mwi(struct e1000_hw *hw)
4226{
4227 struct e1000_adapter *adapter = hw->back;
2648345f 4228 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4229
96838a40 4230 if (ret_val)
2648345f 4231 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4232}
4233
4234void
4235e1000_pci_clear_mwi(struct e1000_hw *hw)
4236{
4237 struct e1000_adapter *adapter = hw->back;
4238
4239 pci_clear_mwi(adapter->pdev);
4240}
4241
4242void
4243e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4244{
4245 struct e1000_adapter *adapter = hw->back;
4246
4247 pci_read_config_word(adapter->pdev, reg, value);
4248}
4249
4250void
4251e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4252{
4253 struct e1000_adapter *adapter = hw->back;
4254
4255 pci_write_config_word(adapter->pdev, reg, *value);
4256}
4257
4258uint32_t
4259e1000_io_read(struct e1000_hw *hw, unsigned long port)
4260{
4261 return inl(port);
4262}
4263
4264void
4265e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4266{
4267 outl(value, port);
4268}
4269
4270static void
4271e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4272{
60490fe0 4273 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4274 uint32_t ctrl, rctl;
4275
4276 e1000_irq_disable(adapter);
4277 adapter->vlgrp = grp;
4278
96838a40 4279 if (grp) {
1da177e4
LT		 4280 /* enable VLAN tag insert/strip */
4281 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4282 ctrl |= E1000_CTRL_VME;
4283 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4284
4285 /* enable VLAN receive filtering */
4286 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4287 rctl |= E1000_RCTL_VFE;
4288 rctl &= ~E1000_RCTL_CFIEN;
4289 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4290 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4291 } else {
4292 /* disable VLAN tag insert/strip */
4293 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4294 ctrl &= ~E1000_CTRL_VME;
4295 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4296
4297 /* disable VLAN filtering */
4298 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4299 rctl &= ~E1000_RCTL_VFE;
4300 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
96838a40 4301 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
2d7edb92
MC		 4302 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4303 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4304 }
1da177e4
LT		 4305 }
4306
4307 e1000_irq_enable(adapter);
4308}
4309
4310static void
4311e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4312{
60490fe0 4313 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4314 uint32_t vfta, index;
96838a40
JB		 4315
4316 if ((adapter->hw.mng_cookie.status &
4317 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4318 (vid == adapter->mng_vlan_id))
2d7edb92 4319 return;
1da177e4
LT		 4320 /* add VID to filter table */
4321 index = (vid >> 5) & 0x7F;
4322 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4323 vfta |= (1 << (vid & 0x1F));
4324 e1000_write_vfta(&adapter->hw, index, vfta);
4325}
4326
4327static void
4328e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4329{
60490fe0 4330 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4331 uint32_t vfta, index;
4332
4333 e1000_irq_disable(adapter);
4334
96838a40 4335 if (adapter->vlgrp)
1da177e4
LT		 4336 adapter->vlgrp->vlan_devices[vid] = NULL;
4337
4338 e1000_irq_enable(adapter);
4339
96838a40
JB		 4340 if ((adapter->hw.mng_cookie.status &
4341 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4342 (vid == adapter->mng_vlan_id)) {
4343 /* release control to f/w */
4344 e1000_release_hw_control(adapter);
2d7edb92 4345 return;
ff147013
JK		 4346 }
4347
1da177e4
LT		 4348 /* remove VID from filter table */
4349 index = (vid >> 5) & 0x7F;
4350 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4351 vfta &= ~(1 << (vid & 0x1F));
4352 e1000_write_vfta(&adapter->hw, index, vfta);
4353}
4354
4355static void
4356e1000_restore_vlan(struct e1000_adapter *adapter)
4357{
4358 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4359
96838a40 4360 if (adapter->vlgrp) {
1da177e4 4361 uint16_t vid;
96838a40
JB		 4362 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4363 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4364 continue;
4365 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4366 }
4367 }
4368}
4369
4370int
4371e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4372{
4373 adapter->hw.autoneg = 0;
4374
6921368f 4375 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4376 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4377 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4378 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4379 return -EINVAL;
4380 }
4381
96838a40 4382 switch (spddplx) {
1da177e4
LT		 4383 case SPEED_10 + DUPLEX_HALF:
4384 adapter->hw.forced_speed_duplex = e1000_10_half;
4385 break;
4386 case SPEED_10 + DUPLEX_FULL:
4387 adapter->hw.forced_speed_duplex = e1000_10_full;
4388 break;
4389 case SPEED_100 + DUPLEX_HALF:
4390 adapter->hw.forced_speed_duplex = e1000_100_half;
4391 break;
4392 case SPEED_100 + DUPLEX_FULL:
4393 adapter->hw.forced_speed_duplex = e1000_100_full;
4394 break;
4395 case SPEED_1000 + DUPLEX_FULL:
4396 adapter->hw.autoneg = 1;
4397 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4398 break;
4399 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4400 default:
2648345f 4401 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4402 return -EINVAL;
4403 }
4404 return 0;
4405}
4406
b6a1d5f8 4407#ifdef CONFIG_PM
0f15a8fa
JK		 4408/* Save/restore 16 or 64 dwords of PCI config space depending on which
4409 * bus we're on (PCI(X) vs. PCI-E)
2f82665f
JB		 4410 */
4411#define PCIE_CONFIG_SPACE_LEN 256
4412#define PCI_CONFIG_SPACE_LEN 64
4413static int
4414e1000_pci_save_state(struct e1000_adapter *adapter)
4415{
4416 struct pci_dev *dev = adapter->pdev;
4417 int size;
4418 int i;
0f15a8fa 4419
2f82665f
JB		 4420 if (adapter->hw.mac_type >= e1000_82571)
4421 size = PCIE_CONFIG_SPACE_LEN;
4422 else
4423 size = PCI_CONFIG_SPACE_LEN;
4424
4425 WARN_ON(adapter->config_space != NULL);
4426
4427 adapter->config_space = kmalloc(size, GFP_KERNEL);
4428 if (!adapter->config_space) {
4429 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4430 return -ENOMEM;
4431 }
4432 for (i = 0; i < (size / 4); i++)
4433 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4434 return 0;
4435}
4436
4437static void
4438e1000_pci_restore_state(struct e1000_adapter *adapter)
4439{
4440 struct pci_dev *dev = adapter->pdev;
4441 int size;
4442 int i;
0f15a8fa 4443
2f82665f
JB		 4444 if (adapter->config_space == NULL)
4445 return;
0f15a8fa 4446
2f82665f
JB		 4447 if (adapter->hw.mac_type >= e1000_82571)
4448 size = PCIE_CONFIG_SPACE_LEN;
4449 else
4450 size = PCI_CONFIG_SPACE_LEN;
4451 for (i = 0; i < (size / 4); i++)
4452 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4453 kfree(adapter->config_space);
4454 adapter->config_space = NULL;
4455 return;
4456}
4457#endif /* CONFIG_PM */
4458
1da177e4 4459static int
829ca9a3 4460e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4461{
4462 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4463 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4464 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4465 uint32_t wufc = adapter->wol;
240b1710 4466 int retval = 0;
1da177e4
LT		 4467
4468 netif_device_detach(netdev);
4469
96838a40 4470 if (netif_running(netdev))
1da177e4
LT		 4471 e1000_down(adapter);
4472
2f82665f 4473#ifdef CONFIG_PM
0f15a8fa
JK		 4474 /* Implement our own version of pci_save_state(pdev) because pci-
4475 * express adapters have 256-byte config spaces. */
2f82665f
JB		 4476 retval = e1000_pci_save_state(adapter);
4477 if (retval)
4478 return retval;
4479#endif
4480
1da177e4 4481 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4482 if (status & E1000_STATUS_LU)
1da177e4
LT		 4483 wufc &= ~E1000_WUFC_LNKC;
4484
96838a40 4485 if (wufc) {
1da177e4
LT		 4486 e1000_setup_rctl(adapter);
4487 e1000_set_multi(netdev);
4488
4489 /* turn on all-multi mode if wake on multicast is enabled */
96838a40 4490 if (adapter->wol & E1000_WUFC_MC) {
1da177e4
LT		 4491 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4492 rctl |= E1000_RCTL_MPE;
4493 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4494 }
4495
96838a40 4496 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4497 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4498 /* advertise wake from D3Cold */
4499 #define E1000_CTRL_ADVD3WUC 0x00100000
4500 /* phy power management enable */
4501 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4502 ctrl |= E1000_CTRL_ADVD3WUC |
4503 E1000_CTRL_EN_PHY_PWR_MGMT;
4504 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4505 }
4506
96838a40 4507 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4508 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4509 /* keep the laser running in D3 */
4510 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4511 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4512 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4513 }
4514
2d7edb92
MC		 4515 /* Allow time for pending master requests to run */
4516 e1000_disable_pciex_master(&adapter->hw);
4517
1da177e4
LT		 4518 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4519 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 4520 pci_enable_wake(pdev, PCI_D3hot, 1);
4521 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4522 } else {
4523 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4524 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 4525 pci_enable_wake(pdev, PCI_D3hot, 0);
4526 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4527 }
4528
96838a40 4529 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4530 adapter->hw.media_type == e1000_media_type_copper) {
4531 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4532 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4533 manc |= E1000_MANC_ARP_EN;
4534 E1000_WRITE_REG(&adapter->hw, MANC, manc);
d0e027db
AK		 4535 pci_enable_wake(pdev, PCI_D3hot, 1);
4536 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4537 }
4538 }
4539
b55ccb35
JK		 4540 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4541 * would have already happened in close and is redundant. */
4542 e1000_release_hw_control(adapter);
2d7edb92 4543
1da177e4 4544 pci_disable_device(pdev);
240b1710 4545
d0e027db 4546 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4547
4548 return 0;
4549}
4550
2f82665f 4551#ifdef CONFIG_PM
1da177e4
LT		 4552static int
4553e1000_resume(struct pci_dev *pdev)
4554{
4555 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4556 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4557 uint32_t manc, ret_val;
1da177e4 4558
d0e027db 4559 pci_set_power_state(pdev, PCI_D0);
2f82665f 4560 e1000_pci_restore_state(adapter);
2b02893e 4561 ret_val = pci_enable_device(pdev);
a4cb847d 4562 pci_set_master(pdev);
1da177e4 4563
d0e027db
AK		 4564 pci_enable_wake(pdev, PCI_D3hot, 0);
4565 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4566
4567 e1000_reset(adapter);
4568 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4569
96838a40 4570 if (netif_running(netdev))
1da177e4
LT		 4571 e1000_up(adapter);
4572
4573 netif_device_attach(netdev);
4574
96838a40 4575 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4576 adapter->hw.media_type == e1000_media_type_copper) {
4577 manc = E1000_READ_REG(&adapter->hw, MANC);
4578 manc &= ~(E1000_MANC_ARP_EN);
4579 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4580 }
4581
b55ccb35
JK		 4582 /* If the controller is 82573 and f/w is AMT, do not set
4583 * DRV_LOAD until the interface is up. For all other cases,
4584 * let the f/w know that the h/w is now under the control
4585 * of the driver. */
4586 if (adapter->hw.mac_type != e1000_82573 ||
4587 !e1000_check_mng_mode(&adapter->hw))
4588 e1000_get_hw_control(adapter);
2d7edb92 4589
1da177e4
LT		 4590 return 0;
4591}
4592#endif
1da177e4
LT		 4593#ifdef CONFIG_NET_POLL_CONTROLLER
4594/*
4595 * Polling 'interrupt' - used by things like netconsole to send skbs
4596 * without having to re-enable interrupts. It's not called while
4597 * the interrupt routine is executing.
4598 */
4599static void
2648345f 4600e1000_netpoll(struct net_device *netdev)
1da177e4 4601{
60490fe0 4602 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4603 disable_irq(adapter->pdev->irq);
4604 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4605 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4606#ifndef CONFIG_E1000_NAPI
4607 adapter->clean_rx(adapter, adapter->rx_ring);
4608#endif
1da177e4
LT		 4609 enable_irq(adapter->pdev->irq);
4610}
4611#endif
4612
4613/* e1000_main.c */
Clone of davem's net-next-2.6 tree