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1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
120a5d0d 27 */
1da177e4
LT		 28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33#include "e1000_hw.h"
34
406874a7 35static s32 e1000_check_downshift(struct e1000_hw *hw);
64798845
JP		 36static s32 e1000_check_polarity(struct e1000_hw *hw,
37 e1000_rev_polarity *polarity);
35574764
NN		 38static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39static void e1000_clear_vfta(struct e1000_hw *hw);
406874a7 40static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
64798845 41 bool link_up);
406874a7
JP		 42static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
406874a7 44static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
64798845
JP		 45static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
46 u16 *max_length);
406874a7 47static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
406874a7 48static s32 e1000_id_led_init(struct e1000_hw *hw);
35574764 49static void e1000_init_rx_addrs(struct e1000_hw *hw);
64798845
JP		 50static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
51 struct e1000_phy_info *phy_info);
64798845
JP		 52static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
53 struct e1000_phy_info *phy_info);
406874a7 54static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
406874a7
JP		 55static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57static s32 e1000_set_phy_type(struct e1000_hw *hw);
1da177e4 58static void e1000_phy_init_script(struct e1000_hw *hw);
406874a7
JP		 59static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
120a5d0d 66static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
406874a7
JP		 67static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
120a5d0d 70 u16 words, u16 *data);
64798845
JP		 71static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
72 u16 words, u16 *data);
406874a7
JP		 73static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
64798845 76static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
406874a7 77static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
64798845 78 u16 phy_data);
120a5d0d 79static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
64798845 80 u16 *phy_data);
406874a7
JP		 81static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
1da177e4
LT		 83static void e1000_release_eeprom(struct e1000_hw *hw);
84static void e1000_standby_eeprom(struct e1000_hw *hw);
406874a7
JP		 85static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87static s32 e1000_set_phy_mode(struct e1000_hw *hw);
120a5d0d
JB		 88static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
89 u16 *data);
90static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
91 u16 *data);
1da177e4
LT		 92
93/* IGP cable length table */
94static const
120a5d0d
JB		 95u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
102 100,
103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
104 110, 110,
105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
106 120, 120
107};
1da177e4 108
78566fec
CL		 109static DEFINE_SPINLOCK(e1000_eeprom_lock);
110
120a5d0d
JB		 111/**
112 * e1000_set_phy_type - Set the phy type member in the hw struct.
113 * @hw: Struct containing variables accessed by shared code
114 */
64798845 115static s32 e1000_set_phy_type(struct e1000_hw *hw)
1da177e4 116{
120a5d0d 117 DEBUGFUNC("e1000_set_phy_type");
1da177e4 118
120a5d0d
JB		 119 if (hw->mac_type == e1000_undefined)
120 return -E1000_ERR_PHY_TYPE;
1da177e4 121
120a5d0d
JB		 122 switch (hw->phy_id) {
123 case M88E1000_E_PHY_ID:
124 case M88E1000_I_PHY_ID:
125 case M88E1011_I_PHY_ID:
126 case M88E1111_I_PHY_ID:
127 hw->phy_type = e1000_phy_m88;
128 break;
129 case IGP01E1000_I_PHY_ID:
130 if (hw->mac_type == e1000_82541 ||
131 hw->mac_type == e1000_82541_rev_2 ||
132 hw->mac_type == e1000_82547 ||
133 hw->mac_type == e1000_82547_rev_2) {
134 hw->phy_type = e1000_phy_igp;
135 break;
136 }
137 default:
138 /* Should never have loaded on this device */
139 hw->phy_type = e1000_phy_undefined;
140 return -E1000_ERR_PHY_TYPE;
141 }
1da177e4 142
120a5d0d
JB		 143 return E1000_SUCCESS;
144}
1da177e4 145
120a5d0d
JB		 146/**
147 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
148 * @hw: Struct containing variables accessed by shared code
149 */
150static void e1000_phy_init_script(struct e1000_hw *hw)
151{
152 u32 ret_val;
153 u16 phy_saved_data;
154
155 DEBUGFUNC("e1000_phy_init_script");
156
157 if (hw->phy_init_script) {
158 msleep(20);
159
160 /* Save off the current value of register 0x2F5B to be restored at
161 * the end of this routine. */
162 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
163
164 /* Disabled the PHY transmitter */
165 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
166 msleep(20);
167
168 e1000_write_phy_reg(hw, 0x0000, 0x0140);
169 msleep(5);
170
171 switch (hw->mac_type) {
172 case e1000_82541:
173 case e1000_82547:
174 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
175 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
176 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
177 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
178 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
179 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
180 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
181 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
182 e1000_write_phy_reg(hw, 0x2010, 0x0008);
183 break;
1da177e4 184
120a5d0d
JB		 185 case e1000_82541_rev_2:
186 case e1000_82547_rev_2:
187 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
188 break;
189 default:
190 break;
191 }
1da177e4 192
120a5d0d
JB		 193 e1000_write_phy_reg(hw, 0x0000, 0x3300);
194 msleep(20);
195
196 /* Now enable the transmitter */
197 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
198
199 if (hw->mac_type == e1000_82547) {
200 u16 fused, fine, coarse;
201
202 /* Move to analog registers page */
203 e1000_read_phy_reg(hw,
204 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
205 &fused);
206
207 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
208 e1000_read_phy_reg(hw,
209 IGP01E1000_ANALOG_FUSE_STATUS,
210 &fused);
211
212 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
213 coarse =
214 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
215
216 if (coarse >
217 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
218 coarse -=
219 IGP01E1000_ANALOG_FUSE_COARSE_10;
220 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
221 } else if (coarse ==
222 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
223 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
224
225 fused =
226 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
227 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
228 (coarse &
229 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
230
231 e1000_write_phy_reg(hw,
232 IGP01E1000_ANALOG_FUSE_CONTROL,
233 fused);
234 e1000_write_phy_reg(hw,
235 IGP01E1000_ANALOG_FUSE_BYPASS,
236 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
237 }
238 }
239 }
1da177e4
LT		 240}
241
120a5d0d
JB		 242/**
243 * e1000_set_mac_type - Set the mac type member in the hw struct.
244 * @hw: Struct containing variables accessed by shared code
245 */
64798845 246s32 e1000_set_mac_type(struct e1000_hw *hw)
1da177e4 247{
bd2371eb
JG		 248 DEBUGFUNC("e1000_set_mac_type");
249
250 switch (hw->device_id) {
251 case E1000_DEV_ID_82542:
252 switch (hw->revision_id) {
253 case E1000_82542_2_0_REV_ID:
254 hw->mac_type = e1000_82542_rev2_0;
255 break;
256 case E1000_82542_2_1_REV_ID:
257 hw->mac_type = e1000_82542_rev2_1;
258 break;
259 default:
260 /* Invalid 82542 revision ID */
261 return -E1000_ERR_MAC_TYPE;
262 }
263 break;
264 case E1000_DEV_ID_82543GC_FIBER:
265 case E1000_DEV_ID_82543GC_COPPER:
266 hw->mac_type = e1000_82543;
267 break;
268 case E1000_DEV_ID_82544EI_COPPER:
269 case E1000_DEV_ID_82544EI_FIBER:
270 case E1000_DEV_ID_82544GC_COPPER:
271 case E1000_DEV_ID_82544GC_LOM:
272 hw->mac_type = e1000_82544;
273 break;
274 case E1000_DEV_ID_82540EM:
275 case E1000_DEV_ID_82540EM_LOM:
276 case E1000_DEV_ID_82540EP:
277 case E1000_DEV_ID_82540EP_LOM:
278 case E1000_DEV_ID_82540EP_LP:
279 hw->mac_type = e1000_82540;
280 break;
281 case E1000_DEV_ID_82545EM_COPPER:
282 case E1000_DEV_ID_82545EM_FIBER:
283 hw->mac_type = e1000_82545;
284 break;
285 case E1000_DEV_ID_82545GM_COPPER:
286 case E1000_DEV_ID_82545GM_FIBER:
287 case E1000_DEV_ID_82545GM_SERDES:
288 hw->mac_type = e1000_82545_rev_3;
289 break;
290 case E1000_DEV_ID_82546EB_COPPER:
291 case E1000_DEV_ID_82546EB_FIBER:
292 case E1000_DEV_ID_82546EB_QUAD_COPPER:
293 hw->mac_type = e1000_82546;
294 break;
295 case E1000_DEV_ID_82546GB_COPPER:
296 case E1000_DEV_ID_82546GB_FIBER:
297 case E1000_DEV_ID_82546GB_SERDES:
298 case E1000_DEV_ID_82546GB_PCIE:
299 case E1000_DEV_ID_82546GB_QUAD_COPPER:
300 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
301 hw->mac_type = e1000_82546_rev_3;
302 break;
303 case E1000_DEV_ID_82541EI:
304 case E1000_DEV_ID_82541EI_MOBILE:
305 case E1000_DEV_ID_82541ER_LOM:
306 hw->mac_type = e1000_82541;
307 break;
308 case E1000_DEV_ID_82541ER:
309 case E1000_DEV_ID_82541GI:
310 case E1000_DEV_ID_82541GI_LF:
311 case E1000_DEV_ID_82541GI_MOBILE:
312 hw->mac_type = e1000_82541_rev_2;
313 break;
314 case E1000_DEV_ID_82547EI:
315 case E1000_DEV_ID_82547EI_MOBILE:
316 hw->mac_type = e1000_82547;
317 break;
318 case E1000_DEV_ID_82547GI:
319 hw->mac_type = e1000_82547_rev_2;
320 break;
bd2371eb
JG		 321 default:
322 /* Should never have loaded on this device */
323 return -E1000_ERR_MAC_TYPE;
324 }
325
326 switch (hw->mac_type) {
bd2371eb
JG		 327 case e1000_82541:
328 case e1000_82547:
329 case e1000_82541_rev_2:
330 case e1000_82547_rev_2:
c3033b01 331 hw->asf_firmware_present = true;
bd2371eb
JG		 332 break;
333 default:
334 break;
335 }
336
167fb284
JG		 337 /* The 82543 chip does not count tx_carrier_errors properly in
338 * FD mode
339 */
340 if (hw->mac_type == e1000_82543)
c3033b01 341 hw->bad_tx_carr_stats_fd = true;
167fb284 342
15e376b4 343 if (hw->mac_type > e1000_82544)
c3033b01 344 hw->has_smbus = true;
bb8e3311 345
bd2371eb 346 return E1000_SUCCESS;
1da177e4
LT		 347}
348
120a5d0d
JB		 349/**
350 * e1000_set_media_type - Set media type and TBI compatibility.
351 * @hw: Struct containing variables accessed by shared code
352 */
64798845 353void e1000_set_media_type(struct e1000_hw *hw)
1da177e4 354{
120a5d0d
JB		 355 u32 status;
356
357 DEBUGFUNC("e1000_set_media_type");
358
359 if (hw->mac_type != e1000_82543) {
360 /* tbi_compatibility is only valid on 82543 */
361 hw->tbi_compatibility_en = false;
362 }
363
364 switch (hw->device_id) {
365 case E1000_DEV_ID_82545GM_SERDES:
366 case E1000_DEV_ID_82546GB_SERDES:
367 hw->media_type = e1000_media_type_internal_serdes;
368 break;
369 default:
370 switch (hw->mac_type) {
371 case e1000_82542_rev2_0:
372 case e1000_82542_rev2_1:
373 hw->media_type = e1000_media_type_fiber;
374 break;
375 default:
376 status = er32(STATUS);
377 if (status & E1000_STATUS_TBIMODE) {
378 hw->media_type = e1000_media_type_fiber;
379 /* tbi_compatibility not valid on fiber */
380 hw->tbi_compatibility_en = false;
381 } else {
382 hw->media_type = e1000_media_type_copper;
383 }
384 break;
385 }
386 }
1da177e4
LT		 387}
388
120a5d0d
JB		 389/**
390 * e1000_reset_hw: reset the hardware completely
391 * @hw: Struct containing variables accessed by shared code
1da177e4 392 *
120a5d0d
JB		 393 * Reset the transmit and receive units; mask and clear all interrupts.
394 */
64798845 395s32 e1000_reset_hw(struct e1000_hw *hw)
1da177e4 396{
120a5d0d
JB		 397 u32 ctrl;
398 u32 ctrl_ext;
399 u32 icr;
400 u32 manc;
401 u32 led_ctrl;
402 s32 ret_val;
403
404 DEBUGFUNC("e1000_reset_hw");
405
406 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
407 if (hw->mac_type == e1000_82542_rev2_0) {
408 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
409 e1000_pci_clear_mwi(hw);
410 }
411
412 /* Clear interrupt mask to stop board from generating interrupts */
413 DEBUGOUT("Masking off all interrupts\n");
414 ew32(IMC, 0xffffffff);
415
416 /* Disable the Transmit and Receive units. Then delay to allow
417 * any pending transactions to complete before we hit the MAC with
418 * the global reset.
419 */
420 ew32(RCTL, 0);
421 ew32(TCTL, E1000_TCTL_PSP);
422 E1000_WRITE_FLUSH();
423
424 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
425 hw->tbi_compatibility_on = false;
426
427 /* Delay to allow any outstanding PCI transactions to complete before
428 * resetting the device
429 */
430 msleep(10);
431
432 ctrl = er32(CTRL);
433
434 /* Must reset the PHY before resetting the MAC */
435 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
436 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
437 msleep(5);
438 }
439
440 /* Issue a global reset to the MAC. This will reset the chip's
441 * transmit, receive, DMA, and link units. It will not effect
442 * the current PCI configuration. The global reset bit is self-
443 * clearing, and should clear within a microsecond.
444 */
445 DEBUGOUT("Issuing a global reset to MAC\n");
446
447 switch (hw->mac_type) {
448 case e1000_82544:
449 case e1000_82540:
450 case e1000_82545:
451 case e1000_82546:
452 case e1000_82541:
453 case e1000_82541_rev_2:
454 /* These controllers can't ack the 64-bit write when issuing the
455 * reset, so use IO-mapping as a workaround to issue the reset */
456 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
457 break;
458 case e1000_82545_rev_3:
459 case e1000_82546_rev_3:
460 /* Reset is performed on a shadow of the control register */
461 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
462 break;
463 default:
464 ew32(CTRL, (ctrl | E1000_CTRL_RST));
465 break;
466 }
467
468 /* After MAC reset, force reload of EEPROM to restore power-on settings to
469 * device. Later controllers reload the EEPROM automatically, so just wait
470 * for reload to complete.
471 */
472 switch (hw->mac_type) {
473 case e1000_82542_rev2_0:
474 case e1000_82542_rev2_1:
475 case e1000_82543:
476 case e1000_82544:
477 /* Wait for reset to complete */
478 udelay(10);
479 ctrl_ext = er32(CTRL_EXT);
480 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
481 ew32(CTRL_EXT, ctrl_ext);
482 E1000_WRITE_FLUSH();
483 /* Wait for EEPROM reload */
484 msleep(2);
485 break;
486 case e1000_82541:
487 case e1000_82541_rev_2:
488 case e1000_82547:
489 case e1000_82547_rev_2:
490 /* Wait for EEPROM reload */
491 msleep(20);
492 break;
493 default:
494 /* Auto read done will delay 5ms or poll based on mac type */
495 ret_val = e1000_get_auto_rd_done(hw);
496 if (ret_val)
497 return ret_val;
498 break;
499 }
500
501 /* Disable HW ARPs on ASF enabled adapters */
502 if (hw->mac_type >= e1000_82540) {
503 manc = er32(MANC);
504 manc &= ~(E1000_MANC_ARP_EN);
505 ew32(MANC, manc);
506 }
507
508 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
509 e1000_phy_init_script(hw);
510
511 /* Configure activity LED after PHY reset */
512 led_ctrl = er32(LEDCTL);
513 led_ctrl &= IGP_ACTIVITY_LED_MASK;
514 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
515 ew32(LEDCTL, led_ctrl);
516 }
517
518 /* Clear interrupt mask to stop board from generating interrupts */
519 DEBUGOUT("Masking off all interrupts\n");
520 ew32(IMC, 0xffffffff);
521
522 /* Clear any pending interrupt events. */
523 icr = er32(ICR);
524
525 /* If MWI was previously enabled, reenable it. */
526 if (hw->mac_type == e1000_82542_rev2_0) {
527 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
528 e1000_pci_set_mwi(hw);
529 }
530
531 return E1000_SUCCESS;
1da177e4
LT		 532}
533
120a5d0d
JB		 534/**
535 * e1000_init_hw: Performs basic configuration of the adapter.
536 * @hw: Struct containing variables accessed by shared code
1da177e4
LT		 537 *
538 * Assumes that the controller has previously been reset and is in a
539 * post-reset uninitialized state. Initializes the receive address registers,
540 * multicast table, and VLAN filter table. Calls routines to setup link
541 * configuration and flow control settings. Clears all on-chip counters. Leaves
542 * the transmit and receive units disabled and uninitialized.
120a5d0d 543 */
64798845 544s32 e1000_init_hw(struct e1000_hw *hw)
1da177e4 545{
120a5d0d
JB		 546 u32 ctrl;
547 u32 i;
548 s32 ret_val;
549 u32 mta_size;
550 u32 ctrl_ext;
551
552 DEBUGFUNC("e1000_init_hw");
553
554 /* Initialize Identification LED */
555 ret_val = e1000_id_led_init(hw);
556 if (ret_val) {
557 DEBUGOUT("Error Initializing Identification LED\n");
558 return ret_val;
559 }
560
561 /* Set the media type and TBI compatibility */
562 e1000_set_media_type(hw);
563
564 /* Disabling VLAN filtering. */
565 DEBUGOUT("Initializing the IEEE VLAN\n");
566 if (hw->mac_type < e1000_82545_rev_3)
567 ew32(VET, 0);
568 e1000_clear_vfta(hw);
569
570 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
571 if (hw->mac_type == e1000_82542_rev2_0) {
572 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
573 e1000_pci_clear_mwi(hw);
574 ew32(RCTL, E1000_RCTL_RST);
575 E1000_WRITE_FLUSH();
576 msleep(5);
577 }
578
579 /* Setup the receive address. This involves initializing all of the Receive
580 * Address Registers (RARs 0 - 15).
581 */
582 e1000_init_rx_addrs(hw);
583
584 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
585 if (hw->mac_type == e1000_82542_rev2_0) {
586 ew32(RCTL, 0);
587 E1000_WRITE_FLUSH();
588 msleep(1);
589 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
590 e1000_pci_set_mwi(hw);
591 }
592
593 /* Zero out the Multicast HASH table */
594 DEBUGOUT("Zeroing the MTA\n");
595 mta_size = E1000_MC_TBL_SIZE;
596 for (i = 0; i < mta_size; i++) {
597 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
598 /* use write flush to prevent Memory Write Block (MWB) from
599 * occurring when accessing our register space */
600 E1000_WRITE_FLUSH();
601 }
602
603 /* Set the PCI priority bit correctly in the CTRL register. This
604 * determines if the adapter gives priority to receives, or if it
605 * gives equal priority to transmits and receives. Valid only on
606 * 82542 and 82543 silicon.
607 */
608 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
609 ctrl = er32(CTRL);
610 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
611 }
612
613 switch (hw->mac_type) {
614 case e1000_82545_rev_3:
615 case e1000_82546_rev_3:
616 break;
617 default:
618 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
619 if (hw->bus_type == e1000_bus_type_pcix
620 && e1000_pcix_get_mmrbc(hw) > 2048)
621 e1000_pcix_set_mmrbc(hw, 2048);
622 break;
623 }
624
625 /* Call a subroutine to configure the link and setup flow control. */
626 ret_val = e1000_setup_link(hw);
627
628 /* Set the transmit descriptor write-back policy */
629 if (hw->mac_type > e1000_82544) {
630 ctrl = er32(TXDCTL);
631 ctrl =
632 (ctrl & ~E1000_TXDCTL_WTHRESH) |
633 E1000_TXDCTL_FULL_TX_DESC_WB;
634 ew32(TXDCTL, ctrl);
635 }
636
637 /* Clear all of the statistics registers (clear on read). It is
638 * important that we do this after we have tried to establish link
639 * because the symbol error count will increment wildly if there
640 * is no link.
641 */
642 e1000_clear_hw_cntrs(hw);
643
644 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
645 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
646 ctrl_ext = er32(CTRL_EXT);
647 /* Relaxed ordering must be disabled to avoid a parity
648 * error crash in a PCI slot. */
649 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
650 ew32(CTRL_EXT, ctrl_ext);
651 }
652
653 return ret_val;
1da177e4
LT		 654}
655
120a5d0d
JB		 656/**
657 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
658 * @hw: Struct containing variables accessed by shared code.
659 */
64798845 660static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1da177e4 661{
120a5d0d
JB		 662 u16 eeprom_data;
663 s32 ret_val;
664
665 DEBUGFUNC("e1000_adjust_serdes_amplitude");
666
667 if (hw->media_type != e1000_media_type_internal_serdes)
668 return E1000_SUCCESS;
669
670 switch (hw->mac_type) {
671 case e1000_82545_rev_3:
672 case e1000_82546_rev_3:
673 break;
674 default:
675 return E1000_SUCCESS;
676 }
677
678 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
679 &eeprom_data);
680 if (ret_val) {
681 return ret_val;
682 }
683
684 if (eeprom_data != EEPROM_RESERVED_WORD) {
685 /* Adjust SERDES output amplitude only. */
686 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
687 ret_val =
688 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
689 if (ret_val)
690 return ret_val;
691 }
692
693 return E1000_SUCCESS;
1da177e4
LT		 694}
695
120a5d0d
JB		 696/**
697 * e1000_setup_link - Configures flow control and link settings.
698 * @hw: Struct containing variables accessed by shared code
1da177e4 699 *
120a5d0d 700 * Determines which flow control settings to use. Calls the appropriate media-
1da177e4
LT		 701 * specific link configuration function. Configures the flow control settings.
702 * Assuming the adapter has a valid link partner, a valid link should be
703 * established. Assumes the hardware has previously been reset and the
704 * transmitter and receiver are not enabled.
120a5d0d 705 */
64798845 706s32 e1000_setup_link(struct e1000_hw *hw)
1da177e4 707{
120a5d0d
JB		 708 u32 ctrl_ext;
709 s32 ret_val;
710 u16 eeprom_data;
711
712 DEBUGFUNC("e1000_setup_link");
713
714 /* Read and store word 0x0F of the EEPROM. This word contains bits
715 * that determine the hardware's default PAUSE (flow control) mode,
716 * a bit that determines whether the HW defaults to enabling or
717 * disabling auto-negotiation, and the direction of the
718 * SW defined pins. If there is no SW over-ride of the flow
719 * control setting, then the variable hw->fc will
720 * be initialized based on a value in the EEPROM.
721 */
722 if (hw->fc == E1000_FC_DEFAULT) {
723 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
724 1, &eeprom_data);
725 if (ret_val) {
726 DEBUGOUT("EEPROM Read Error\n");
727 return -E1000_ERR_EEPROM;
728 }
729 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
730 hw->fc = E1000_FC_NONE;
731 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
732 EEPROM_WORD0F_ASM_DIR)
733 hw->fc = E1000_FC_TX_PAUSE;
734 else
735 hw->fc = E1000_FC_FULL;
736 }
1da177e4 737
120a5d0d
JB		 738 /* We want to save off the original Flow Control configuration just
739 * in case we get disconnected and then reconnected into a different
740 * hub or switch with different Flow Control capabilities.
741 */
742 if (hw->mac_type == e1000_82542_rev2_0)
743 hw->fc &= (~E1000_FC_TX_PAUSE);
1da177e4 744
120a5d0d
JB		 745 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
746 hw->fc &= (~E1000_FC_RX_PAUSE);
1da177e4 747
120a5d0d 748 hw->original_fc = hw->fc;
1da177e4 749
120a5d0d 750 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1da177e4 751
120a5d0d
JB		 752 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
753 * polarity value for the SW controlled pins, and setup the
754 * Extended Device Control reg with that info.
755 * This is needed because one of the SW controlled pins is used for
756 * signal detection. So this should be done before e1000_setup_pcs_link()
757 * or e1000_phy_setup() is called.
758 */
759 if (hw->mac_type == e1000_82543) {
760 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
761 1, &eeprom_data);
762 if (ret_val) {
763 DEBUGOUT("EEPROM Read Error\n");
764 return -E1000_ERR_EEPROM;
765 }
766 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
767 SWDPIO__EXT_SHIFT);
768 ew32(CTRL_EXT, ctrl_ext);
769 }
1da177e4 770
120a5d0d
JB		 771 /* Call the necessary subroutine to configure the link. */
772 ret_val = (hw->media_type == e1000_media_type_copper) ?
773 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
2d7edb92 774
120a5d0d
JB		 775 /* Initialize the flow control address, type, and PAUSE timer
776 * registers to their default values. This is done even if flow
777 * control is disabled, because it does not hurt anything to
778 * initialize these registers.
779 */
780 DEBUGOUT
781 ("Initializing the Flow Control address, type and timer regs\n");
2d7edb92 782
120a5d0d
JB		 783 ew32(FCT, FLOW_CONTROL_TYPE);
784 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
785 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
2d7edb92 786
120a5d0d 787 ew32(FCTTV, hw->fc_pause_time);
1da177e4 788
120a5d0d
JB		 789 /* Set the flow control receive threshold registers. Normally,
790 * these registers will be set to a default threshold that may be
791 * adjusted later by the driver's runtime code. However, if the
792 * ability to transmit pause frames in not enabled, then these
793 * registers will be set to 0.
794 */
795 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
796 ew32(FCRTL, 0);
797 ew32(FCRTH, 0);
798 } else {
799 /* We need to set up the Receive Threshold high and low water marks
800 * as well as (optionally) enabling the transmission of XON frames.
801 */
802 if (hw->fc_send_xon) {
803 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
804 ew32(FCRTH, hw->fc_high_water);
805 } else {
806 ew32(FCRTL, hw->fc_low_water);
807 ew32(FCRTH, hw->fc_high_water);
808 }
809 }
810 return ret_val;
1da177e4
LT		 811}
812
120a5d0d
JB		 813/**
814 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
815 * @hw: Struct containing variables accessed by shared code
816 *
817 * Manipulates Physical Coding Sublayer functions in order to configure
818 * link. Assumes the hardware has been previously reset and the transmitter
819 * and receiver are not enabled.
820 */
821static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1da177e4 822{
120a5d0d
JB		 823 u32 ctrl;
824 u32 status;
825 u32 txcw = 0;
826 u32 i;
827 u32 signal = 0;
828 s32 ret_val;
829
830 DEBUGFUNC("e1000_setup_fiber_serdes_link");
831
832 /* On adapters with a MAC newer than 82544, SWDP 1 will be
833 * set when the optics detect a signal. On older adapters, it will be
834 * cleared when there is a signal. This applies to fiber media only.
835 * If we're on serdes media, adjust the output amplitude to value
836 * set in the EEPROM.
837 */
838 ctrl = er32(CTRL);
839 if (hw->media_type == e1000_media_type_fiber)
840 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
841
842 ret_val = e1000_adjust_serdes_amplitude(hw);
843 if (ret_val)
844 return ret_val;
845
846 /* Take the link out of reset */
847 ctrl &= ~(E1000_CTRL_LRST);
848
849 /* Adjust VCO speed to improve BER performance */
850 ret_val = e1000_set_vco_speed(hw);
851 if (ret_val)
852 return ret_val;
853
854 e1000_config_collision_dist(hw);
855
856 /* Check for a software override of the flow control settings, and setup
857 * the device accordingly. If auto-negotiation is enabled, then software
858 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
859 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
860 * auto-negotiation is disabled, then software will have to manually
861 * configure the two flow control enable bits in the CTRL register.
862 *
863 * The possible values of the "fc" parameter are:
864 * 0: Flow control is completely disabled
865 * 1: Rx flow control is enabled (we can receive pause frames, but
866 * not send pause frames).
867 * 2: Tx flow control is enabled (we can send pause frames but we do
868 * not support receiving pause frames).
869 * 3: Both Rx and TX flow control (symmetric) are enabled.
870 */
871 switch (hw->fc) {
872 case E1000_FC_NONE:
873 /* Flow control is completely disabled by a software over-ride. */
874 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
875 break;
876 case E1000_FC_RX_PAUSE:
877 /* RX Flow control is enabled and TX Flow control is disabled by a
878 * software over-ride. Since there really isn't a way to advertise
879 * that we are capable of RX Pause ONLY, we will advertise that we
880 * support both symmetric and asymmetric RX PAUSE. Later, we will
881 * disable the adapter's ability to send PAUSE frames.
882 */
883 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
884 break;
885 case E1000_FC_TX_PAUSE:
886 /* TX Flow control is enabled, and RX Flow control is disabled, by a
887 * software over-ride.
888 */
889 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
890 break;
891 case E1000_FC_FULL:
892 /* Flow control (both RX and TX) is enabled by a software over-ride. */
893 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
894 break;
895 default:
896 DEBUGOUT("Flow control param set incorrectly\n");
897 return -E1000_ERR_CONFIG;
898 break;
899 }
1da177e4 900
120a5d0d
JB		 901 /* Since auto-negotiation is enabled, take the link out of reset (the link
902 * will be in reset, because we previously reset the chip). This will
903 * restart auto-negotiation. If auto-negotiation is successful then the
904 * link-up status bit will be set and the flow control enable bits (RFCE
905 * and TFCE) will be set according to their negotiated value.
906 */
907 DEBUGOUT("Auto-negotiation enabled\n");
0fadb059 908
120a5d0d
JB		 909 ew32(TXCW, txcw);
910 ew32(CTRL, ctrl);
911 E1000_WRITE_FLUSH();
1da177e4 912
120a5d0d
JB		 913 hw->txcw = txcw;
914 msleep(1);
1da177e4 915
120a5d0d
JB		 916 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
917 * indication in the Device Status Register. Time-out if a link isn't
918 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
919 * less than 500 milliseconds even if the other end is doing it in SW).
920 * For internal serdes, we just assume a signal is present, then poll.
921 */
922 if (hw->media_type == e1000_media_type_internal_serdes ||
923 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
924 DEBUGOUT("Looking for Link\n");
925 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
926 msleep(10);
927 status = er32(STATUS);
928 if (status & E1000_STATUS_LU)
929 break;
930 }
931 if (i == (LINK_UP_TIMEOUT / 10)) {
932 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
933 hw->autoneg_failed = 1;
934 /* AutoNeg failed to achieve a link, so we'll call
935 * e1000_check_for_link. This routine will force the link up if
936 * we detect a signal. This will allow us to communicate with
937 * non-autonegotiating link partners.
938 */
939 ret_val = e1000_check_for_link(hw);
940 if (ret_val) {
941 DEBUGOUT("Error while checking for link\n");
942 return ret_val;
943 }
944 hw->autoneg_failed = 0;
945 } else {
946 hw->autoneg_failed = 0;
947 DEBUGOUT("Valid Link Found\n");
948 }
949 } else {
950 DEBUGOUT("No Signal Detected\n");
951 }
952 return E1000_SUCCESS;
1da177e4
LT		 953}
954
120a5d0d
JB		 955/**
956 * e1000_copper_link_preconfig - early configuration for copper
957 * @hw: Struct containing variables accessed by shared code
958 *
959 * Make sure we have a valid PHY and change PHY mode before link setup.
960 */
961static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1da177e4 962{
120a5d0d
JB		 963 u32 ctrl;
964 s32 ret_val;
965 u16 phy_data;
966
967 DEBUGFUNC("e1000_copper_link_preconfig");
968
969 ctrl = er32(CTRL);
970 /* With 82543, we need to force speed and duplex on the MAC equal to what
971 * the PHY speed and duplex configuration is. In addition, we need to
972 * perform a hardware reset on the PHY to take it out of reset.
973 */
974 if (hw->mac_type > e1000_82543) {
975 ctrl |= E1000_CTRL_SLU;
976 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
977 ew32(CTRL, ctrl);
978 } else {
979 ctrl |=
980 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
981 ew32(CTRL, ctrl);
982 ret_val = e1000_phy_hw_reset(hw);
983 if (ret_val)
984 return ret_val;
985 }
986
987 /* Make sure we have a valid PHY */
988 ret_val = e1000_detect_gig_phy(hw);
989 if (ret_val) {
990 DEBUGOUT("Error, did not detect valid phy.\n");
991 return ret_val;
992 }
d6dbee86 993 DEBUGOUT1("Phy ID = %x\n", hw->phy_id);
120a5d0d
JB		 994
995 /* Set PHY to class A mode (if necessary) */
996 ret_val = e1000_set_phy_mode(hw);
997 if (ret_val)
998 return ret_val;
999
1000 if ((hw->mac_type == e1000_82545_rev_3) ||
1001 (hw->mac_type == e1000_82546_rev_3)) {
1002 ret_val =
1003 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1004 phy_data |= 0x00000008;
1005 ret_val =
1006 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1007 }
1008
1009 if (hw->mac_type <= e1000_82543 ||
1010 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1011 hw->mac_type == e1000_82541_rev_2
1012 || hw->mac_type == e1000_82547_rev_2)
1013 hw->phy_reset_disable = false;
1014
1015 return E1000_SUCCESS;
1da177e4
LT		 1016}
1017
120a5d0d
JB		 1018/**
1019 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1020 * @hw: Struct containing variables accessed by shared code
1021 */
1022static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1023{
1024 u32 led_ctrl;
1025 s32 ret_val;
1026 u16 phy_data;
1027
1028 DEBUGFUNC("e1000_copper_link_igp_setup");
1029
1030 if (hw->phy_reset_disable)
1031 return E1000_SUCCESS;
1032
1033 ret_val = e1000_phy_reset(hw);
1034 if (ret_val) {
1035 DEBUGOUT("Error Resetting the PHY\n");
1036 return ret_val;
1037 }
1038
1039 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1040 msleep(15);
1041 /* Configure activity LED after PHY reset */
1042 led_ctrl = er32(LEDCTL);
1043 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1044 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1045 ew32(LEDCTL, led_ctrl);
1046
1047 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1048 if (hw->phy_type == e1000_phy_igp) {
1049 /* disable lplu d3 during driver init */
1050 ret_val = e1000_set_d3_lplu_state(hw, false);
1051 if (ret_val) {
1052 DEBUGOUT("Error Disabling LPLU D3\n");
1053 return ret_val;
1054 }
1055 }
1056
1057 /* Configure mdi-mdix settings */
1058 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1059 if (ret_val)
1060 return ret_val;
1061
1062 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1063 hw->dsp_config_state = e1000_dsp_config_disabled;
1064 /* Force MDI for earlier revs of the IGP PHY */
1065 phy_data &=
1066 ~(IGP01E1000_PSCR_AUTO_MDIX |
1067 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1068 hw->mdix = 1;
1069
1070 } else {
1071 hw->dsp_config_state = e1000_dsp_config_enabled;
1072 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1073
1074 switch (hw->mdix) {
1075 case 1:
1076 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1077 break;
1078 case 2:
1079 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1080 break;
1081 case 0:
1082 default:
1083 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1084 break;
1085 }
1086 }
1087 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1088 if (ret_val)
1089 return ret_val;
1090
1091 /* set auto-master slave resolution settings */
1092 if (hw->autoneg) {
1093 e1000_ms_type phy_ms_setting = hw->master_slave;
1094
1095 if (hw->ffe_config_state == e1000_ffe_config_active)
1096 hw->ffe_config_state = e1000_ffe_config_enabled;
1097
1098 if (hw->dsp_config_state == e1000_dsp_config_activated)
1099 hw->dsp_config_state = e1000_dsp_config_enabled;
1100
1101 /* when autonegotiation advertisement is only 1000Mbps then we
1102 * should disable SmartSpeed and enable Auto MasterSlave
1103 * resolution as hardware default. */
1104 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1105 /* Disable SmartSpeed */
1106 ret_val =
1107 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1108 &phy_data);
1109 if (ret_val)
1110 return ret_val;
1111 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1112 ret_val =
1113 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1114 phy_data);
1115 if (ret_val)
1116 return ret_val;
1117 /* Set auto Master/Slave resolution process */
1118 ret_val =
1119 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1120 if (ret_val)
1121 return ret_val;
1122 phy_data &= ~CR_1000T_MS_ENABLE;
1123 ret_val =
1124 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1125 if (ret_val)
1126 return ret_val;
1127 }
1128
1129 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1130 if (ret_val)
1131 return ret_val;
1132
1133 /* load defaults for future use */
1134 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1135 ((phy_data & CR_1000T_MS_VALUE) ?
1136 e1000_ms_force_master :
1137 e1000_ms_force_slave) : e1000_ms_auto;
1138
1139 switch (phy_ms_setting) {
1140 case e1000_ms_force_master:
1141 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1142 break;
1143 case e1000_ms_force_slave:
1144 phy_data |= CR_1000T_MS_ENABLE;
1145 phy_data &= ~(CR_1000T_MS_VALUE);
1146 break;
1147 case e1000_ms_auto:
1148 phy_data &= ~CR_1000T_MS_ENABLE;
1149 default:
1150 break;
1151 }
1152 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1153 if (ret_val)
1154 return ret_val;
1155 }
1156
1157 return E1000_SUCCESS;
1158}
1159
1160/**
1161 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1162 * @hw: Struct containing variables accessed by shared code
1163 */
1164static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1165{
1166 s32 ret_val;
1167 u16 phy_data;
1168
1169 DEBUGFUNC("e1000_copper_link_mgp_setup");
1170
1171 if (hw->phy_reset_disable)
1172 return E1000_SUCCESS;
1173
1174 /* Enable CRS on TX. This must be set for half-duplex operation. */
1175 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1176 if (ret_val)
1177 return ret_val;
1178
1179 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1180
1181 /* Options:
1182 * MDI/MDI-X = 0 (default)
1183 * 0 - Auto for all speeds
1184 * 1 - MDI mode
1185 * 2 - MDI-X mode
1186 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1187 */
1188 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1189
1190 switch (hw->mdix) {
1191 case 1:
1192 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1193 break;
1194 case 2:
1195 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1196 break;
1197 case 3:
1198 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1199 break;
1200 case 0:
1201 default:
1202 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1203 break;
1204 }
1205
1206 /* Options:
1207 * disable_polarity_correction = 0 (default)
1208 * Automatic Correction for Reversed Cable Polarity
1209 * 0 - Disabled
1210 * 1 - Enabled
1211 */
1212 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1213 if (hw->disable_polarity_correction == 1)
1214 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1215 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1216 if (ret_val)
1217 return ret_val;
1218
1219 if (hw->phy_revision < M88E1011_I_REV_4) {
1220 /* Force TX_CLK in the Extended PHY Specific Control Register
1221 * to 25MHz clock.
1222 */
1223 ret_val =
1224 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1225 &phy_data);
1226 if (ret_val)
1227 return ret_val;
1228
1229 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1230
1231 if ((hw->phy_revision == E1000_REVISION_2) &&
1232 (hw->phy_id == M88E1111_I_PHY_ID)) {
1233 /* Vidalia Phy, set the downshift counter to 5x */
1234 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1235 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1236 ret_val = e1000_write_phy_reg(hw,
1237 M88E1000_EXT_PHY_SPEC_CTRL,
1238 phy_data);
1239 if (ret_val)
1240 return ret_val;
1241 } else {
1242 /* Configure Master and Slave downshift values */
1243 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1244 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1245 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1246 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1247 ret_val = e1000_write_phy_reg(hw,
1248 M88E1000_EXT_PHY_SPEC_CTRL,
1249 phy_data);
1250 if (ret_val)
1251 return ret_val;
1252 }
1253 }
1254
1255 /* SW Reset the PHY so all changes take effect */
1256 ret_val = e1000_phy_reset(hw);
1257 if (ret_val) {
1258 DEBUGOUT("Error Resetting the PHY\n");
1259 return ret_val;
1260 }
1261
1262 return E1000_SUCCESS;
1263}
1264
1265/**
1266 * e1000_copper_link_autoneg - setup auto-neg
1267 * @hw: Struct containing variables accessed by shared code
1da177e4 1268 *
120a5d0d
JB		 1269 * Setup auto-negotiation and flow control advertisements,
1270 * and then perform auto-negotiation.
1271 */
1272static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1273{
1274 s32 ret_val;
1275 u16 phy_data;
1276
1277 DEBUGFUNC("e1000_copper_link_autoneg");
1278
1279 /* Perform some bounds checking on the hw->autoneg_advertised
1280 * parameter. If this variable is zero, then set it to the default.
1281 */
1282 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1283
1284 /* If autoneg_advertised is zero, we assume it was not defaulted
1285 * by the calling code so we set to advertise full capability.
1286 */
1287 if (hw->autoneg_advertised == 0)
1288 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1289
1290 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1291 ret_val = e1000_phy_setup_autoneg(hw);
1292 if (ret_val) {
1293 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1294 return ret_val;
1295 }
1296 DEBUGOUT("Restarting Auto-Neg\n");
1297
1298 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1299 * the Auto Neg Restart bit in the PHY control register.
1300 */
1301 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1302 if (ret_val)
1303 return ret_val;
1304
1305 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1306 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1307 if (ret_val)
1308 return ret_val;
1309
1310 /* Does the user want to wait for Auto-Neg to complete here, or
1311 * check at a later time (for example, callback routine).
1312 */
1313 if (hw->wait_autoneg_complete) {
1314 ret_val = e1000_wait_autoneg(hw);
1315 if (ret_val) {
1316 DEBUGOUT
1317 ("Error while waiting for autoneg to complete\n");
1318 return ret_val;
1319 }
1320 }
1321
1322 hw->get_link_status = true;
1323
1324 return E1000_SUCCESS;
1325}
1326
1327/**
1328 * e1000_copper_link_postconfig - post link setup
1329 * @hw: Struct containing variables accessed by shared code
1da177e4 1330 *
120a5d0d
JB		 1331 * Config the MAC and the PHY after link is up.
1332 * 1) Set up the MAC to the current PHY speed/duplex
1333 * if we are on 82543. If we
1334 * are on newer silicon, we only need to configure
1335 * collision distance in the Transmit Control Register.
1336 * 2) Set up flow control on the MAC to that established with
1337 * the link partner.
1338 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1339 */
1340static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1341{
1342 s32 ret_val;
1343 DEBUGFUNC("e1000_copper_link_postconfig");
1344
1345 if (hw->mac_type >= e1000_82544) {
1346 e1000_config_collision_dist(hw);
1347 } else {
1348 ret_val = e1000_config_mac_to_phy(hw);
1349 if (ret_val) {
1350 DEBUGOUT("Error configuring MAC to PHY settings\n");
1351 return ret_val;
1352 }
1353 }
1354 ret_val = e1000_config_fc_after_link_up(hw);
1355 if (ret_val) {
1356 DEBUGOUT("Error Configuring Flow Control\n");
1357 return ret_val;
1358 }
1359
1360 /* Config DSP to improve Giga link quality */
1361 if (hw->phy_type == e1000_phy_igp) {
1362 ret_val = e1000_config_dsp_after_link_change(hw, true);
1363 if (ret_val) {
1364 DEBUGOUT("Error Configuring DSP after link up\n");
1365 return ret_val;
1366 }
1367 }
1368
1369 return E1000_SUCCESS;
1370}
1371
1372/**
1373 * e1000_setup_copper_link - phy/speed/duplex setting
1374 * @hw: Struct containing variables accessed by shared code
1375 *
1376 * Detects which PHY is present and sets up the speed and duplex
1377 */
1378static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1379{
1380 s32 ret_val;
1381 u16 i;
1382 u16 phy_data;
1383
1384 DEBUGFUNC("e1000_setup_copper_link");
1385
1386 /* Check if it is a valid PHY and set PHY mode if necessary. */
1387 ret_val = e1000_copper_link_preconfig(hw);
1388 if (ret_val)
1389 return ret_val;
1390
1391 if (hw->phy_type == e1000_phy_igp) {
1392 ret_val = e1000_copper_link_igp_setup(hw);
1393 if (ret_val)
1394 return ret_val;
1395 } else if (hw->phy_type == e1000_phy_m88) {
1396 ret_val = e1000_copper_link_mgp_setup(hw);
1397 if (ret_val)
1398 return ret_val;
1399 }
1400
1401 if (hw->autoneg) {
1402 /* Setup autoneg and flow control advertisement
1403 * and perform autonegotiation */
1404 ret_val = e1000_copper_link_autoneg(hw);
1405 if (ret_val)
1406 return ret_val;
1407 } else {
1408 /* PHY will be set to 10H, 10F, 100H,or 100F
1409 * depending on value from forced_speed_duplex. */
1410 DEBUGOUT("Forcing speed and duplex\n");
1411 ret_val = e1000_phy_force_speed_duplex(hw);
1412 if (ret_val) {
1413 DEBUGOUT("Error Forcing Speed and Duplex\n");
1414 return ret_val;
1415 }
1416 }
1417
1418 /* Check link status. Wait up to 100 microseconds for link to become
1419 * valid.
1420 */
1421 for (i = 0; i < 10; i++) {
1422 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1423 if (ret_val)
1424 return ret_val;
1425 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1426 if (ret_val)
1427 return ret_val;
1428
1429 if (phy_data & MII_SR_LINK_STATUS) {
1430 /* Config the MAC and PHY after link is up */
1431 ret_val = e1000_copper_link_postconfig(hw);
1432 if (ret_val)
1433 return ret_val;
1434
1435 DEBUGOUT("Valid link established!!!\n");
1436 return E1000_SUCCESS;
1437 }
1438 udelay(10);
1439 }
1440
1441 DEBUGOUT("Unable to establish link!!!\n");
1442 return E1000_SUCCESS;
1443}
1444
1445/**
1446 * e1000_phy_setup_autoneg - phy settings
1447 * @hw: Struct containing variables accessed by shared code
1448 *
1449 * Configures PHY autoneg and flow control advertisement settings
1450 */
1451s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1452{
1453 s32 ret_val;
1454 u16 mii_autoneg_adv_reg;
1455 u16 mii_1000t_ctrl_reg;
1456
1457 DEBUGFUNC("e1000_phy_setup_autoneg");
1458
1459 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1460 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1461 if (ret_val)
1462 return ret_val;
1463
1464 /* Read the MII 1000Base-T Control Register (Address 9). */
1465 ret_val =
1466 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1467 if (ret_val)
1468 return ret_val;
1469
1470 /* Need to parse both autoneg_advertised and fc and set up
1471 * the appropriate PHY registers. First we will parse for
1472 * autoneg_advertised software override. Since we can advertise
1473 * a plethora of combinations, we need to check each bit
1474 * individually.
1475 */
1476
1477 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1478 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1479 * the 1000Base-T Control Register (Address 9).
1480 */
1481 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1482 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1483
1484 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1485
1486 /* Do we want to advertise 10 Mb Half Duplex? */
1487 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1488 DEBUGOUT("Advertise 10mb Half duplex\n");
1489 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1490 }
1491
1492 /* Do we want to advertise 10 Mb Full Duplex? */
1493 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1494 DEBUGOUT("Advertise 10mb Full duplex\n");
1495 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1496 }
1497
1498 /* Do we want to advertise 100 Mb Half Duplex? */
1499 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1500 DEBUGOUT("Advertise 100mb Half duplex\n");
1501 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1502 }
1503
1504 /* Do we want to advertise 100 Mb Full Duplex? */
1505 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1506 DEBUGOUT("Advertise 100mb Full duplex\n");
1507 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1508 }
1509
1510 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1511 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1512 DEBUGOUT
1513 ("Advertise 1000mb Half duplex requested, request denied!\n");
1514 }
1515
1516 /* Do we want to advertise 1000 Mb Full Duplex? */
1517 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1518 DEBUGOUT("Advertise 1000mb Full duplex\n");
1519 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1520 }
1521
1522 /* Check for a software override of the flow control settings, and
1523 * setup the PHY advertisement registers accordingly. If
1524 * auto-negotiation is enabled, then software will have to set the
1525 * "PAUSE" bits to the correct value in the Auto-Negotiation
1526 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1527 *
1528 * The possible values of the "fc" parameter are:
1529 * 0: Flow control is completely disabled
1530 * 1: Rx flow control is enabled (we can receive pause frames
1531 * but not send pause frames).
1532 * 2: Tx flow control is enabled (we can send pause frames
1533 * but we do not support receiving pause frames).
1534 * 3: Both Rx and TX flow control (symmetric) are enabled.
1535 * other: No software override. The flow control configuration
1536 * in the EEPROM is used.
1537 */
1538 switch (hw->fc) {
1539 case E1000_FC_NONE: /* 0 */
1540 /* Flow control (RX & TX) is completely disabled by a
1541 * software over-ride.
1542 */
1543 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1544 break;
1545 case E1000_FC_RX_PAUSE: /* 1 */
1546 /* RX Flow control is enabled, and TX Flow control is
1547 * disabled, by a software over-ride.
1548 */
1549 /* Since there really isn't a way to advertise that we are
1550 * capable of RX Pause ONLY, we will advertise that we
1551 * support both symmetric and asymmetric RX PAUSE. Later
1552 * (in e1000_config_fc_after_link_up) we will disable the
1553 *hw's ability to send PAUSE frames.
1554 */
1555 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1556 break;
1557 case E1000_FC_TX_PAUSE: /* 2 */
1558 /* TX Flow control is enabled, and RX Flow control is
1559 * disabled, by a software over-ride.
1560 */
1561 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1562 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1563 break;
1564 case E1000_FC_FULL: /* 3 */
1565 /* Flow control (both RX and TX) is enabled by a software
1566 * over-ride.
1567 */
1568 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1569 break;
1570 default:
1571 DEBUGOUT("Flow control param set incorrectly\n");
1572 return -E1000_ERR_CONFIG;
1573 }
1574
1575 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1576 if (ret_val)
1577 return ret_val;
1578
1579 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1580
1581 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1582 if (ret_val)
1583 return ret_val;
1584
1585 return E1000_SUCCESS;
1586}
1587
1588/**
1589 * e1000_phy_force_speed_duplex - force link settings
1590 * @hw: Struct containing variables accessed by shared code
1591 *
1592 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1593 */
1594static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1595{
1596 u32 ctrl;
1597 s32 ret_val;
1598 u16 mii_ctrl_reg;
1599 u16 mii_status_reg;
1600 u16 phy_data;
1601 u16 i;
1602
1603 DEBUGFUNC("e1000_phy_force_speed_duplex");
1604
1605 /* Turn off Flow control if we are forcing speed and duplex. */
1606 hw->fc = E1000_FC_NONE;
1607
1608 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1609
1610 /* Read the Device Control Register. */
1611 ctrl = er32(CTRL);
1612
1613 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1614 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1615 ctrl &= ~(DEVICE_SPEED_MASK);
1616
1617 /* Clear the Auto Speed Detect Enable bit. */
1618 ctrl &= ~E1000_CTRL_ASDE;
1619
1620 /* Read the MII Control Register. */
1621 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1622 if (ret_val)
1623 return ret_val;
1624
1625 /* We need to disable autoneg in order to force link and duplex. */
1626
1627 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1628
1629 /* Are we forcing Full or Half Duplex? */
1630 if (hw->forced_speed_duplex == e1000_100_full ||
1631 hw->forced_speed_duplex == e1000_10_full) {
1632 /* We want to force full duplex so we SET the full duplex bits in the
1633 * Device and MII Control Registers.
1634 */
1635 ctrl |= E1000_CTRL_FD;
1636 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1637 DEBUGOUT("Full Duplex\n");
1638 } else {
1639 /* We want to force half duplex so we CLEAR the full duplex bits in
1640 * the Device and MII Control Registers.
1641 */
1642 ctrl &= ~E1000_CTRL_FD;
1643 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1644 DEBUGOUT("Half Duplex\n");
1645 }
1646
1647 /* Are we forcing 100Mbps??? */
1648 if (hw->forced_speed_duplex == e1000_100_full ||
1649 hw->forced_speed_duplex == e1000_100_half) {
1650 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1651 ctrl |= E1000_CTRL_SPD_100;
1652 mii_ctrl_reg |= MII_CR_SPEED_100;
1653 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1654 DEBUGOUT("Forcing 100mb ");
1655 } else {
1656 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1657 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1658 mii_ctrl_reg |= MII_CR_SPEED_10;
1659 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1660 DEBUGOUT("Forcing 10mb ");
1661 }
1662
1663 e1000_config_collision_dist(hw);
1664
1665 /* Write the configured values back to the Device Control Reg. */
1666 ew32(CTRL, ctrl);
1667
1668 if (hw->phy_type == e1000_phy_m88) {
1669 ret_val =
1670 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1671 if (ret_val)
1672 return ret_val;
1673
1674 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1675 * forced whenever speed are duplex are forced.
1676 */
1677 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1678 ret_val =
1679 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1680 if (ret_val)
1681 return ret_val;
1682
d6dbee86 1683 DEBUGOUT1("M88E1000 PSCR: %x\n", phy_data);
120a5d0d
JB		 1684
1685 /* Need to reset the PHY or these changes will be ignored */
1686 mii_ctrl_reg |= MII_CR_RESET;
1687
1688 /* Disable MDI-X support for 10/100 */
1689 } else {
1690 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1691 * forced whenever speed or duplex are forced.
1692 */
1693 ret_val =
1694 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1695 if (ret_val)
1696 return ret_val;
1697
1698 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1699 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1700
1701 ret_val =
1702 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1703 if (ret_val)
1704 return ret_val;
1705 }
1706
1707 /* Write back the modified PHY MII control register. */
1708 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1709 if (ret_val)
1710 return ret_val;
1711
1712 udelay(1);
1713
1714 /* The wait_autoneg_complete flag may be a little misleading here.
1715 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1716 * But we do want to delay for a period while forcing only so we
1717 * don't generate false No Link messages. So we will wait here
1718 * only if the user has set wait_autoneg_complete to 1, which is
1719 * the default.
1720 */
1721 if (hw->wait_autoneg_complete) {
1722 /* We will wait for autoneg to complete. */
1723 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1724 mii_status_reg = 0;
1725
1726 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1727 for (i = PHY_FORCE_TIME; i > 0; i--) {
1728 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1729 * to be set.
1730 */
1731 ret_val =
1732 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1733 if (ret_val)
1734 return ret_val;
1735
1736 ret_val =
1737 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1738 if (ret_val)
1739 return ret_val;
1740
1741 if (mii_status_reg & MII_SR_LINK_STATUS)
1742 break;
1743 msleep(100);
1744 }
1745 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1746 /* We didn't get link. Reset the DSP and wait again for link. */
1747 ret_val = e1000_phy_reset_dsp(hw);
1748 if (ret_val) {
1749 DEBUGOUT("Error Resetting PHY DSP\n");
1750 return ret_val;
1751 }
1752 }
1753 /* This loop will early-out if the link condition has been met. */
1754 for (i = PHY_FORCE_TIME; i > 0; i--) {
1755 if (mii_status_reg & MII_SR_LINK_STATUS)
1756 break;
1757 msleep(100);
1758 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1759 * to be set.
1760 */
1761 ret_val =
1762 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1763 if (ret_val)
1764 return ret_val;
1765
1766 ret_val =
1767 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1768 if (ret_val)
1769 return ret_val;
1770 }
1771 }
1772
1773 if (hw->phy_type == e1000_phy_m88) {
1774 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1775 * Extended PHY Specific Control Register to 25MHz clock. This value
1776 * defaults back to a 2.5MHz clock when the PHY is reset.
1777 */
1778 ret_val =
1779 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1780 &phy_data);
1781 if (ret_val)
1782 return ret_val;
1783
1784 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1785 ret_val =
1786 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1787 phy_data);
1788 if (ret_val)
1789 return ret_val;
1790
1791 /* In addition, because of the s/w reset above, we need to enable CRS on
1792 * TX. This must be set for both full and half duplex operation.
1793 */
1794 ret_val =
1795 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1796 if (ret_val)
1797 return ret_val;
1798
1799 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1800 ret_val =
1801 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1802 if (ret_val)
1803 return ret_val;
1804
1805 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
1806 && (!hw->autoneg)
1807 && (hw->forced_speed_duplex == e1000_10_full
1808 || hw->forced_speed_duplex == e1000_10_half)) {
1809 ret_val = e1000_polarity_reversal_workaround(hw);
1810 if (ret_val)
1811 return ret_val;
1812 }
1813 }
1814 return E1000_SUCCESS;
1815}
1816
1817/**
1818 * e1000_config_collision_dist - set collision distance register
1819 * @hw: Struct containing variables accessed by shared code
1820 *
1821 * Sets the collision distance in the Transmit Control register.
1822 * Link should have been established previously. Reads the speed and duplex
1823 * information from the Device Status register.
1824 */
1825void e1000_config_collision_dist(struct e1000_hw *hw)
1826{
1827 u32 tctl, coll_dist;
1828
1829 DEBUGFUNC("e1000_config_collision_dist");
1830
1831 if (hw->mac_type < e1000_82543)
1832 coll_dist = E1000_COLLISION_DISTANCE_82542;
1833 else
1834 coll_dist = E1000_COLLISION_DISTANCE;
1835
1836 tctl = er32(TCTL);
1837
1838 tctl &= ~E1000_TCTL_COLD;
1839 tctl |= coll_dist << E1000_COLD_SHIFT;
1840
1841 ew32(TCTL, tctl);
1842 E1000_WRITE_FLUSH();
1843}
1844
1845/**
1846 * e1000_config_mac_to_phy - sync phy and mac settings
1847 * @hw: Struct containing variables accessed by shared code
1848 * @mii_reg: data to write to the MII control register
1849 *
1850 * Sets MAC speed and duplex settings to reflect the those in the PHY
1851 * The contents of the PHY register containing the needed information need to
1852 * be passed in.
1853 */
1854static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1855{
1856 u32 ctrl;
1857 s32 ret_val;
1858 u16 phy_data;
1859
1860 DEBUGFUNC("e1000_config_mac_to_phy");
1861
1862 /* 82544 or newer MAC, Auto Speed Detection takes care of
1863 * MAC speed/duplex configuration.*/
1864 if (hw->mac_type >= e1000_82544)
1865 return E1000_SUCCESS;
1866
1867 /* Read the Device Control Register and set the bits to Force Speed
1868 * and Duplex.
1869 */
1870 ctrl = er32(CTRL);
1871 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1872 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1873
1874 /* Set up duplex in the Device Control and Transmit Control
1875 * registers depending on negotiated values.
1876 */
1877 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1878 if (ret_val)
1879 return ret_val;
1880
1881 if (phy_data & M88E1000_PSSR_DPLX)
1882 ctrl |= E1000_CTRL_FD;
1883 else
1884 ctrl &= ~E1000_CTRL_FD;
1885
1886 e1000_config_collision_dist(hw);
1887
1888 /* Set up speed in the Device Control register depending on
1889 * negotiated values.
1890 */
1891 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1892 ctrl |= E1000_CTRL_SPD_1000;
1893 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1894 ctrl |= E1000_CTRL_SPD_100;
1895
1896 /* Write the configured values back to the Device Control Reg. */
1897 ew32(CTRL, ctrl);
1898 return E1000_SUCCESS;
1899}
1900
1901/**
1902 * e1000_force_mac_fc - force flow control settings
1903 * @hw: Struct containing variables accessed by shared code
1904 *
1905 * Forces the MAC's flow control settings.
1da177e4
LT		 1906 * Sets the TFCE and RFCE bits in the device control register to reflect
1907 * the adapter settings. TFCE and RFCE need to be explicitly set by
1908 * software when a Copper PHY is used because autonegotiation is managed
1909 * by the PHY rather than the MAC. Software must also configure these
1910 * bits when link is forced on a fiber connection.
120a5d0d 1911 */
64798845 1912s32 e1000_force_mac_fc(struct e1000_hw *hw)
1da177e4 1913{
120a5d0d
JB		 1914 u32 ctrl;
1915
1916 DEBUGFUNC("e1000_force_mac_fc");
1917
1918 /* Get the current configuration of the Device Control Register */
1919 ctrl = er32(CTRL);
1920
1921 /* Because we didn't get link via the internal auto-negotiation
1922 * mechanism (we either forced link or we got link via PHY
1923 * auto-neg), we have to manually enable/disable transmit an
1924 * receive flow control.
1925 *
1926 * The "Case" statement below enables/disable flow control
1927 * according to the "hw->fc" parameter.
1928 *
1929 * The possible values of the "fc" parameter are:
1930 * 0: Flow control is completely disabled
1931 * 1: Rx flow control is enabled (we can receive pause
1932 * frames but not send pause frames).
1933 * 2: Tx flow control is enabled (we can send pause frames
1934 * frames but we do not receive pause frames).
1935 * 3: Both Rx and TX flow control (symmetric) is enabled.
1936 * other: No other values should be possible at this point.
1937 */
1938
1939 switch (hw->fc) {
1940 case E1000_FC_NONE:
1941 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1942 break;
1943 case E1000_FC_RX_PAUSE:
1944 ctrl &= (~E1000_CTRL_TFCE);
1945 ctrl |= E1000_CTRL_RFCE;
1946 break;
1947 case E1000_FC_TX_PAUSE:
1948 ctrl &= (~E1000_CTRL_RFCE);
1949 ctrl |= E1000_CTRL_TFCE;
1950 break;
1951 case E1000_FC_FULL:
1952 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1953 break;
1954 default:
1955 DEBUGOUT("Flow control param set incorrectly\n");
1956 return -E1000_ERR_CONFIG;
1957 }
1958
1959 /* Disable TX Flow Control for 82542 (rev 2.0) */
1960 if (hw->mac_type == e1000_82542_rev2_0)
1961 ctrl &= (~E1000_CTRL_TFCE);
1962
1963 ew32(CTRL, ctrl);
1964 return E1000_SUCCESS;
1da177e4
LT		 1965}
1966
120a5d0d
JB		 1967/**
1968 * e1000_config_fc_after_link_up - configure flow control after autoneg
1969 * @hw: Struct containing variables accessed by shared code
1da177e4 1970 *
120a5d0d 1971 * Configures flow control settings after link is established
1da177e4
LT		 1972 * Should be called immediately after a valid link has been established.
1973 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1974 * and autonegotiation is enabled, the MAC flow control settings will be set
1975 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
120a5d0d
JB		 1976 * and RFCE bits will be automatically set to the negotiated flow control mode.
1977 */
64798845 1978static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1da177e4 1979{
120a5d0d
JB		 1980 s32 ret_val;
1981 u16 mii_status_reg;
1982 u16 mii_nway_adv_reg;
1983 u16 mii_nway_lp_ability_reg;
1984 u16 speed;
1985 u16 duplex;
1986
1987 DEBUGFUNC("e1000_config_fc_after_link_up");
1988
1989 /* Check for the case where we have fiber media and auto-neg failed
1990 * so we had to force link. In this case, we need to force the
1991 * configuration of the MAC to match the "fc" parameter.
1992 */
1993 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
1994 || ((hw->media_type == e1000_media_type_internal_serdes)
1995 && (hw->autoneg_failed))
1996 || ((hw->media_type == e1000_media_type_copper)
1997 && (!hw->autoneg))) {
1998 ret_val = e1000_force_mac_fc(hw);
1999 if (ret_val) {
2000 DEBUGOUT("Error forcing flow control settings\n");
2001 return ret_val;
2002 }
2003 }
2004
2005 /* Check for the case where we have copper media and auto-neg is
2006 * enabled. In this case, we need to check and see if Auto-Neg
2007 * has completed, and if so, how the PHY and link partner has
2008 * flow control configured.
2009 */
2010 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2011 /* Read the MII Status Register and check to see if AutoNeg
2012 * has completed. We read this twice because this reg has
2013 * some "sticky" (latched) bits.
2014 */
2015 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2016 if (ret_val)
2017 return ret_val;
2018 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2019 if (ret_val)
2020 return ret_val;
2021
2022 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2023 /* The AutoNeg process has completed, so we now need to
2024 * read both the Auto Negotiation Advertisement Register
2025 * (Address 4) and the Auto_Negotiation Base Page Ability
2026 * Register (Address 5) to determine how flow control was
2027 * negotiated.
2028 */
2029 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2030 &mii_nway_adv_reg);
2031 if (ret_val)
2032 return ret_val;
2033 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2034 &mii_nway_lp_ability_reg);
2035 if (ret_val)
2036 return ret_val;
2037
2038 /* Two bits in the Auto Negotiation Advertisement Register
2039 * (Address 4) and two bits in the Auto Negotiation Base
2040 * Page Ability Register (Address 5) determine flow control
2041 * for both the PHY and the link partner. The following
2042 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2043 * 1999, describes these PAUSE resolution bits and how flow
2044 * control is determined based upon these settings.
2045 * NOTE: DC = Don't Care
2046 *
2047 * LOCAL DEVICE | LINK PARTNER
2048 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2049 *-------|---------|-------|---------|--------------------
2050 * 0 | 0 | DC | DC | E1000_FC_NONE
2051 * 0 | 1 | 0 | DC | E1000_FC_NONE
2052 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2053 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2054 * 1 | 0 | 0 | DC | E1000_FC_NONE
2055 * 1 | DC | 1 | DC | E1000_FC_FULL
2056 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2057 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2058 *
2059 */
2060 /* Are both PAUSE bits set to 1? If so, this implies
2061 * Symmetric Flow Control is enabled at both ends. The
2062 * ASM_DIR bits are irrelevant per the spec.
2063 *
2064 * For Symmetric Flow Control:
2065 *
2066 * LOCAL DEVICE | LINK PARTNER
2067 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2068 *-------|---------|-------|---------|--------------------
2069 * 1 | DC | 1 | DC | E1000_FC_FULL
2070 *
2071 */
2072 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2073 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2074 /* Now we need to check if the user selected RX ONLY
2075 * of pause frames. In this case, we had to advertise
2076 * FULL flow control because we could not advertise RX
2077 * ONLY. Hence, we must now check to see if we need to
2078 * turn OFF the TRANSMISSION of PAUSE frames.
2079 */
2080 if (hw->original_fc == E1000_FC_FULL) {
2081 hw->fc = E1000_FC_FULL;
2082 DEBUGOUT("Flow Control = FULL.\n");
2083 } else {
2084 hw->fc = E1000_FC_RX_PAUSE;
2085 DEBUGOUT
2086 ("Flow Control = RX PAUSE frames only.\n");
2087 }
2088 }
2089 /* For receiving PAUSE frames ONLY.
2090 *
2091 * LOCAL DEVICE | LINK PARTNER
2092 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2093 *-------|---------|-------|---------|--------------------
2094 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2095 *
2096 */
2097 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2098 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2099 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2100 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2101 {
2102 hw->fc = E1000_FC_TX_PAUSE;
2103 DEBUGOUT
2104 ("Flow Control = TX PAUSE frames only.\n");
2105 }
2106 /* For transmitting PAUSE frames ONLY.
2107 *
2108 * LOCAL DEVICE | LINK PARTNER
2109 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2110 *-------|---------|-------|---------|--------------------
2111 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2112 *
2113 */
2114 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2115 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2116 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2117 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2118 {
2119 hw->fc = E1000_FC_RX_PAUSE;
2120 DEBUGOUT
2121 ("Flow Control = RX PAUSE frames only.\n");
2122 }
2123 /* Per the IEEE spec, at this point flow control should be
2124 * disabled. However, we want to consider that we could
2125 * be connected to a legacy switch that doesn't advertise
2126 * desired flow control, but can be forced on the link
2127 * partner. So if we advertised no flow control, that is
2128 * what we will resolve to. If we advertised some kind of
2129 * receive capability (Rx Pause Only or Full Flow Control)
2130 * and the link partner advertised none, we will configure
2131 * ourselves to enable Rx Flow Control only. We can do
2132 * this safely for two reasons: If the link partner really
2133 * didn't want flow control enabled, and we enable Rx, no
2134 * harm done since we won't be receiving any PAUSE frames
2135 * anyway. If the intent on the link partner was to have
2136 * flow control enabled, then by us enabling RX only, we
2137 * can at least receive pause frames and process them.
2138 * This is a good idea because in most cases, since we are
2139 * predominantly a server NIC, more times than not we will
2140 * be asked to delay transmission of packets than asking
2141 * our link partner to pause transmission of frames.
2142 */
2143 else if ((hw->original_fc == E1000_FC_NONE ||
2144 hw->original_fc == E1000_FC_TX_PAUSE) ||
2145 hw->fc_strict_ieee) {
2146 hw->fc = E1000_FC_NONE;
2147 DEBUGOUT("Flow Control = NONE.\n");
2148 } else {
2149 hw->fc = E1000_FC_RX_PAUSE;
2150 DEBUGOUT
2151 ("Flow Control = RX PAUSE frames only.\n");
2152 }
2153
2154 /* Now we need to do one last check... If we auto-
2155 * negotiated to HALF DUPLEX, flow control should not be
2156 * enabled per IEEE 802.3 spec.
2157 */
2158 ret_val =
2159 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2160 if (ret_val) {
2161 DEBUGOUT
2162 ("Error getting link speed and duplex\n");
2163 return ret_val;
2164 }
2165
2166 if (duplex == HALF_DUPLEX)
2167 hw->fc = E1000_FC_NONE;
2168
2169 /* Now we call a subroutine to actually force the MAC
2170 * controller to use the correct flow control settings.
2171 */
2172 ret_val = e1000_force_mac_fc(hw);
2173 if (ret_val) {
2174 DEBUGOUT
2175 ("Error forcing flow control settings\n");
2176 return ret_val;
2177 }
2178 } else {
2179 DEBUGOUT
2180 ("Copper PHY and Auto Neg has not completed.\n");
2181 }
2182 }
2183 return E1000_SUCCESS;
1da177e4
LT		 2184}
2185
be0f0719 2186/**
120a5d0d
JB		 2187 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2188 * @hw: pointer to the HW structure
be0f0719 2189 *
120a5d0d
JB		 2190 * Checks for link up on the hardware. If link is not up and we have
2191 * a signal, then we need to force link up.
2192 */
11b7f7b3 2193static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
be0f0719
JB		 2194{
2195 u32 rxcw;
2196 u32 ctrl;
2197 u32 status;
2198 s32 ret_val = E1000_SUCCESS;
2199
2200 DEBUGFUNC("e1000_check_for_serdes_link_generic");
2201
2202 ctrl = er32(CTRL);
2203 status = er32(STATUS);
2204 rxcw = er32(RXCW);
2205
2206 /*
2207 * If we don't have link (auto-negotiation failed or link partner
2208 * cannot auto-negotiate), and our link partner is not trying to
2209 * auto-negotiate with us (we are receiving idles or data),
2210 * we need to force link up. We also need to give auto-negotiation
2211 * time to complete.
2212 */
2213 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2214 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2215 if (hw->autoneg_failed == 0) {
2216 hw->autoneg_failed = 1;
2217 goto out;
2218 }
2219 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
2220
2221 /* Disable auto-negotiation in the TXCW register */
2222 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2223
2224 /* Force link-up and also force full-duplex. */
2225 ctrl = er32(CTRL);
2226 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2227 ew32(CTRL, ctrl);
2228
2229 /* Configure Flow Control after forcing link up. */
2230 ret_val = e1000_config_fc_after_link_up(hw);
2231 if (ret_val) {
2232 DEBUGOUT("Error configuring flow control\n");
2233 goto out;
2234 }
2235 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2236 /*
2237 * If we are forcing link and we are receiving /C/ ordered
2238 * sets, re-enable auto-negotiation in the TXCW register
2239 * and disable forced link in the Device Control register
2240 * in an attempt to auto-negotiate with our link partner.
2241 */
2242 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2243 ew32(TXCW, hw->txcw);
2244 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2245
2246 hw->serdes_has_link = true;
2247 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2248 /*
2249 * If we force link for non-auto-negotiation switch, check
2250 * link status based on MAC synchronization for internal
2251 * serdes media type.
2252 */
2253 /* SYNCH bit and IV bit are sticky. */
2254 udelay(10);
2255 rxcw = er32(RXCW);
2256 if (rxcw & E1000_RXCW_SYNCH) {
2257 if (!(rxcw & E1000_RXCW_IV)) {
2258 hw->serdes_has_link = true;
2259 DEBUGOUT("SERDES: Link up - forced.\n");
2260 }
2261 } else {
2262 hw->serdes_has_link = false;
2263 DEBUGOUT("SERDES: Link down - force failed.\n");
2264 }
2265 }
2266
2267 if (E1000_TXCW_ANE & er32(TXCW)) {
2268 status = er32(STATUS);
2269 if (status & E1000_STATUS_LU) {
2270 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2271 udelay(10);
2272 rxcw = er32(RXCW);
2273 if (rxcw & E1000_RXCW_SYNCH) {
2274 if (!(rxcw & E1000_RXCW_IV)) {
2275 hw->serdes_has_link = true;
2276 DEBUGOUT("SERDES: Link up - autoneg "
120a5d0d 2277 "completed successfully.\n");
be0f0719
JB		 2278 } else {
2279 hw->serdes_has_link = false;
2280 DEBUGOUT("SERDES: Link down - invalid"
120a5d0d
JB		 2281 "codewords detected in autoneg.\n");
2282 }
2283 } else {
2284 hw->serdes_has_link = false;
2285 DEBUGOUT("SERDES: Link down - no sync.\n");
2286 }
2287 } else {
2288 hw->serdes_has_link = false;
2289 DEBUGOUT("SERDES: Link down - autoneg failed\n");
2290 }
2291 }
2292
2293 out:
2294 return ret_val;
2295}
2296
2297/**
2298 * e1000_check_for_link
2299 * @hw: Struct containing variables accessed by shared code
2300 *
2301 * Checks to see if the link status of the hardware has changed.
2302 * Called by any function that needs to check the link status of the adapter.
2303 */
2304s32 e1000_check_for_link(struct e1000_hw *hw)
2305{
2306 u32 rxcw = 0;
2307 u32 ctrl;
2308 u32 status;
2309 u32 rctl;
2310 u32 icr;
2311 u32 signal = 0;
2312 s32 ret_val;
2313 u16 phy_data;
2314
2315 DEBUGFUNC("e1000_check_for_link");
2316
2317 ctrl = er32(CTRL);
2318 status = er32(STATUS);
2319
2320 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2321 * set when the optics detect a signal. On older adapters, it will be
2322 * cleared when there is a signal. This applies to fiber media only.
2323 */
2324 if ((hw->media_type == e1000_media_type_fiber) ||
2325 (hw->media_type == e1000_media_type_internal_serdes)) {
2326 rxcw = er32(RXCW);
2327
2328 if (hw->media_type == e1000_media_type_fiber) {
2329 signal =
2330 (hw->mac_type >
2331 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2332 if (status & E1000_STATUS_LU)
2333 hw->get_link_status = false;
2334 }
2335 }
2336
2337 /* If we have a copper PHY then we only want to go out to the PHY
2338 * registers to see if Auto-Neg has completed and/or if our link
2339 * status has changed. The get_link_status flag will be set if we
2340 * receive a Link Status Change interrupt or we have Rx Sequence
2341 * Errors.
2342 */
2343 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2344 /* First we want to see if the MII Status Register reports
2345 * link. If so, then we want to get the current speed/duplex
2346 * of the PHY.
2347 * Read the register twice since the link bit is sticky.
2348 */
2349 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2350 if (ret_val)
2351 return ret_val;
2352 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2353 if (ret_val)
2354 return ret_val;
2355
2356 if (phy_data & MII_SR_LINK_STATUS) {
2357 hw->get_link_status = false;
2358 /* Check if there was DownShift, must be checked immediately after
2359 * link-up */
2360 e1000_check_downshift(hw);
2361
2362 /* If we are on 82544 or 82543 silicon and speed/duplex
2363 * are forced to 10H or 10F, then we will implement the polarity
2364 * reversal workaround. We disable interrupts first, and upon
2365 * returning, place the devices interrupt state to its previous
2366 * value except for the link status change interrupt which will
2367 * happen due to the execution of this workaround.
2368 */
2369
2370 if ((hw->mac_type == e1000_82544
2371 || hw->mac_type == e1000_82543) && (!hw->autoneg)
2372 && (hw->forced_speed_duplex == e1000_10_full
2373 || hw->forced_speed_duplex == e1000_10_half)) {
2374 ew32(IMC, 0xffffffff);
2375 ret_val =
2376 e1000_polarity_reversal_workaround(hw);
2377 icr = er32(ICR);
2378 ew32(ICS, (icr & ~E1000_ICS_LSC));
2379 ew32(IMS, IMS_ENABLE_MASK);
2380 }
2381
2382 } else {
2383 /* No link detected */
2384 e1000_config_dsp_after_link_change(hw, false);
2385 return 0;
2386 }
2387
2388 /* If we are forcing speed/duplex, then we simply return since
2389 * we have already determined whether we have link or not.
2390 */
2391 if (!hw->autoneg)
2392 return -E1000_ERR_CONFIG;
2393
2394 /* optimize the dsp settings for the igp phy */
2395 e1000_config_dsp_after_link_change(hw, true);
2396
2397 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2398 * have Si on board that is 82544 or newer, Auto
2399 * Speed Detection takes care of MAC speed/duplex
2400 * configuration. So we only need to configure Collision
2401 * Distance in the MAC. Otherwise, we need to force
2402 * speed/duplex on the MAC to the current PHY speed/duplex
2403 * settings.
2404 */
2405 if (hw->mac_type >= e1000_82544)
2406 e1000_config_collision_dist(hw);
2407 else {
2408 ret_val = e1000_config_mac_to_phy(hw);
2409 if (ret_val) {
2410 DEBUGOUT
2411 ("Error configuring MAC to PHY settings\n");
2412 return ret_val;
2413 }
2414 }
2415
2416 /* Configure Flow Control now that Auto-Neg has completed. First, we
2417 * need to restore the desired flow control settings because we may
2418 * have had to re-autoneg with a different link partner.
2419 */
2420 ret_val = e1000_config_fc_after_link_up(hw);
2421 if (ret_val) {
2422 DEBUGOUT("Error configuring flow control\n");
2423 return ret_val;
2424 }
2425
2426 /* At this point we know that we are on copper and we have
2427 * auto-negotiated link. These are conditions for checking the link
2428 * partner capability register. We use the link speed to determine if
2429 * TBI compatibility needs to be turned on or off. If the link is not
2430 * at gigabit speed, then TBI compatibility is not needed. If we are
2431 * at gigabit speed, we turn on TBI compatibility.
2432 */
2433 if (hw->tbi_compatibility_en) {
2434 u16 speed, duplex;
2435 ret_val =
2436 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2437 if (ret_val) {
2438 DEBUGOUT
2439 ("Error getting link speed and duplex\n");
2440 return ret_val;
2441 }
2442 if (speed != SPEED_1000) {
2443 /* If link speed is not set to gigabit speed, we do not need
2444 * to enable TBI compatibility.
2445 */
2446 if (hw->tbi_compatibility_on) {
2447 /* If we previously were in the mode, turn it off. */
2448 rctl = er32(RCTL);
2449 rctl &= ~E1000_RCTL_SBP;
2450 ew32(RCTL, rctl);
2451 hw->tbi_compatibility_on = false;
be0f0719
JB		 2452 }
2453 } else {
120a5d0d
JB		 2454 /* If TBI compatibility is was previously off, turn it on. For
2455 * compatibility with a TBI link partner, we will store bad
2456 * packets. Some frames have an additional byte on the end and
2457 * will look like CRC errors to to the hardware.
2458 */
2459 if (!hw->tbi_compatibility_on) {
2460 hw->tbi_compatibility_on = true;
2461 rctl = er32(RCTL);
2462 rctl |= E1000_RCTL_SBP;
2463 ew32(RCTL, rctl);
2464 }
be0f0719 2465 }
be0f0719
JB		 2466 }
2467 }
2468
120a5d0d
JB		 2469 if ((hw->media_type == e1000_media_type_fiber) ||
2470 (hw->media_type == e1000_media_type_internal_serdes))
2471 e1000_check_for_serdes_link_generic(hw);
2472
2473 return E1000_SUCCESS;
1da177e4
LT		 2474}
2475
120a5d0d
JB		 2476/**
2477 * e1000_get_speed_and_duplex
2478 * @hw: Struct containing variables accessed by shared code
2479 * @speed: Speed of the connection
2480 * @duplex: Duplex setting of the connection
2481
1da177e4 2482 * Detects the current speed and duplex settings of the hardware.
120a5d0d 2483 */
64798845 2484s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1da177e4 2485{
120a5d0d
JB		 2486 u32 status;
2487 s32 ret_val;
2488 u16 phy_data;
2489
2490 DEBUGFUNC("e1000_get_speed_and_duplex");
2491
2492 if (hw->mac_type >= e1000_82543) {
2493 status = er32(STATUS);
2494 if (status & E1000_STATUS_SPEED_1000) {
2495 *speed = SPEED_1000;
2496 DEBUGOUT("1000 Mbs, ");
2497 } else if (status & E1000_STATUS_SPEED_100) {
2498 *speed = SPEED_100;
2499 DEBUGOUT("100 Mbs, ");
2500 } else {
2501 *speed = SPEED_10;
2502 DEBUGOUT("10 Mbs, ");
2503 }
2504
2505 if (status & E1000_STATUS_FD) {
2506 *duplex = FULL_DUPLEX;
2507 DEBUGOUT("Full Duplex\n");
2508 } else {
2509 *duplex = HALF_DUPLEX;
2510 DEBUGOUT(" Half Duplex\n");
2511 }
2512 } else {
2513 DEBUGOUT("1000 Mbs, Full Duplex\n");
2514 *speed = SPEED_1000;
2515 *duplex = FULL_DUPLEX;
2516 }
2517
2518 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2519 * if it is operating at half duplex. Here we set the duplex settings to
2520 * match the duplex in the link partner's capabilities.
2521 */
2522 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2523 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2524 if (ret_val)
2525 return ret_val;
2526
2527 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2528 *duplex = HALF_DUPLEX;
2529 else {
2530 ret_val =
2531 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2532 if (ret_val)
2533 return ret_val;
2534 if ((*speed == SPEED_100
2535 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
2536 || (*speed == SPEED_10
2537 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2538 *duplex = HALF_DUPLEX;
2539 }
2540 }
2541
2542 return E1000_SUCCESS;
1da177e4
LT		 2543}
2544
120a5d0d
JB		 2545/**
2546 * e1000_wait_autoneg
2547 * @hw: Struct containing variables accessed by shared code
2548 *
2549 * Blocks until autoneg completes or times out (~4.5 seconds)
2550 */
64798845 2551static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1da177e4 2552{
120a5d0d
JB		 2553 s32 ret_val;
2554 u16 i;
2555 u16 phy_data;
2556
2557 DEBUGFUNC("e1000_wait_autoneg");
2558 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2559
2560 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2561 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2562 /* Read the MII Status Register and wait for Auto-Neg
2563 * Complete bit to be set.
2564 */
2565 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2566 if (ret_val)
2567 return ret_val;
2568 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2569 if (ret_val)
2570 return ret_val;
2571 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2572 return E1000_SUCCESS;
2573 }
2574 msleep(100);
2575 }
2576 return E1000_SUCCESS;
1da177e4
LT		 2577}
2578
120a5d0d
JB		 2579/**
2580 * e1000_raise_mdi_clk - Raises the Management Data Clock
2581 * @hw: Struct containing variables accessed by shared code
2582 * @ctrl: Device control register's current value
2583 */
64798845 2584static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
1da177e4 2585{
120a5d0d
JB		 2586 /* Raise the clock input to the Management Data Clock (by setting the MDC
2587 * bit), and then delay 10 microseconds.
2588 */
2589 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2590 E1000_WRITE_FLUSH();
2591 udelay(10);
1da177e4
LT		 2592}
2593
120a5d0d
JB		 2594/**
2595 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2596 * @hw: Struct containing variables accessed by shared code
2597 * @ctrl: Device control register's current value
2598 */
64798845 2599static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
1da177e4 2600{
120a5d0d
JB		 2601 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2602 * bit), and then delay 10 microseconds.
2603 */
2604 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2605 E1000_WRITE_FLUSH();
2606 udelay(10);
1da177e4
LT		 2607}
2608
120a5d0d
JB		 2609/**
2610 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2611 * @hw: Struct containing variables accessed by shared code
2612 * @data: Data to send out to the PHY
2613 * @count: Number of bits to shift out
2614 *
2615 * Bits are shifted out in MSB to LSB order.
2616 */
64798845 2617static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
1da177e4 2618{
120a5d0d
JB		 2619 u32 ctrl;
2620 u32 mask;
2621
2622 /* We need to shift "count" number of bits out to the PHY. So, the value
2623 * in the "data" parameter will be shifted out to the PHY one bit at a
2624 * time. In order to do this, "data" must be broken down into bits.
2625 */
2626 mask = 0x01;
2627 mask <<= (count - 1);
2628
2629 ctrl = er32(CTRL);
2630
2631 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2632 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2633
2634 while (mask) {
2635 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2636 * then raising and lowering the Management Data Clock. A "0" is
2637 * shifted out to the PHY by setting the MDIO bit to "0" and then
2638 * raising and lowering the clock.
2639 */
2640 if (data & mask)
2641 ctrl |= E1000_CTRL_MDIO;
2642 else
2643 ctrl &= ~E1000_CTRL_MDIO;
2644
2645 ew32(CTRL, ctrl);
2646 E1000_WRITE_FLUSH();
2647
2648 udelay(10);
2649
2650 e1000_raise_mdi_clk(hw, &ctrl);
2651 e1000_lower_mdi_clk(hw, &ctrl);
2652
2653 mask = mask >> 1;
2654 }
1da177e4
LT		 2655}
2656
120a5d0d
JB		 2657/**
2658 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2659 * @hw: Struct containing variables accessed by shared code
2660 *
2661 * Bits are shifted in in MSB to LSB order.
2662 */
64798845 2663static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
1da177e4 2664{
120a5d0d
JB		 2665 u32 ctrl;
2666 u16 data = 0;
2667 u8 i;
2668
2669 /* In order to read a register from the PHY, we need to shift in a total
2670 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2671 * to avoid contention on the MDIO pin when a read operation is performed.
2672 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2673 * by raising the input to the Management Data Clock (setting the MDC bit),
2674 * and then reading the value of the MDIO bit.
2675 */
2676 ctrl = er32(CTRL);
2677
2678 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2679 ctrl &= ~E1000_CTRL_MDIO_DIR;
2680 ctrl &= ~E1000_CTRL_MDIO;
2681
2682 ew32(CTRL, ctrl);
2683 E1000_WRITE_FLUSH();
2684
2685 /* Raise and Lower the clock before reading in the data. This accounts for
2686 * the turnaround bits. The first clock occurred when we clocked out the
2687 * last bit of the Register Address.
2688 */
2689 e1000_raise_mdi_clk(hw, &ctrl);
2690 e1000_lower_mdi_clk(hw, &ctrl);
2691
2692 for (data = 0, i = 0; i < 16; i++) {
2693 data = data << 1;
2694 e1000_raise_mdi_clk(hw, &ctrl);
2695 ctrl = er32(CTRL);
2696 /* Check to see if we shifted in a "1". */
2697 if (ctrl & E1000_CTRL_MDIO)
2698 data |= 1;
2699 e1000_lower_mdi_clk(hw, &ctrl);
2700 }
2701
2702 e1000_raise_mdi_clk(hw, &ctrl);
2703 e1000_lower_mdi_clk(hw, &ctrl);
2704
2705 return data;
1da177e4
LT		 2706}
2707
120a5d0d
JB		 2708
2709/**
2710 * e1000_read_phy_reg - read a phy register
2711 * @hw: Struct containing variables accessed by shared code
2712 * @reg_addr: address of the PHY register to read
2713 *
2714 * Reads the value from a PHY register, if the value is on a specific non zero
2715 * page, sets the page first.
2716 */
64798845 2717s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
1da177e4 2718{
120a5d0d 2719 u32 ret_val;
1da177e4 2720
120a5d0d 2721 DEBUGFUNC("e1000_read_phy_reg");
1da177e4 2722
120a5d0d
JB		 2723 if ((hw->phy_type == e1000_phy_igp) &&
2724 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2725 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2726 (u16) reg_addr);
2727 if (ret_val)
2728 return ret_val;
2729 }
2730
2731 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2732 phy_data);
1da177e4 2733
120a5d0d 2734 return ret_val;
1da177e4
LT		 2735}
2736
64798845
JP		 2737static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2738 u16 *phy_data)
1da177e4 2739{
120a5d0d
JB		 2740 u32 i;
2741 u32 mdic = 0;
2742 const u32 phy_addr = 1;
2743
2744 DEBUGFUNC("e1000_read_phy_reg_ex");
2745
2746 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2747 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2748 return -E1000_ERR_PARAM;
2749 }
2750
2751 if (hw->mac_type > e1000_82543) {
2752 /* Set up Op-code, Phy Address, and register address in the MDI
2753 * Control register. The MAC will take care of interfacing with the
2754 * PHY to retrieve the desired data.
2755 */
2756 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2757 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2758 (E1000_MDIC_OP_READ));
2759
2760 ew32(MDIC, mdic);
2761
2762 /* Poll the ready bit to see if the MDI read completed */
2763 for (i = 0; i < 64; i++) {
2764 udelay(50);
2765 mdic = er32(MDIC);
2766 if (mdic & E1000_MDIC_READY)
2767 break;
2768 }
2769 if (!(mdic & E1000_MDIC_READY)) {
2770 DEBUGOUT("MDI Read did not complete\n");
2771 return -E1000_ERR_PHY;
2772 }
2773 if (mdic & E1000_MDIC_ERROR) {
2774 DEBUGOUT("MDI Error\n");
2775 return -E1000_ERR_PHY;
2776 }
2777 *phy_data = (u16) mdic;
2778 } else {
2779 /* We must first send a preamble through the MDIO pin to signal the
2780 * beginning of an MII instruction. This is done by sending 32
2781 * consecutive "1" bits.
2782 */
2783 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2784
2785 /* Now combine the next few fields that are required for a read
2786 * operation. We use this method instead of calling the
2787 * e1000_shift_out_mdi_bits routine five different times. The format of
2788 * a MII read instruction consists of a shift out of 14 bits and is
2789 * defined as follows:
2790 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2791 * followed by a shift in of 18 bits. This first two bits shifted in
2792 * are TurnAround bits used to avoid contention on the MDIO pin when a
2793 * READ operation is performed. These two bits are thrown away
2794 * followed by a shift in of 16 bits which contains the desired data.
2795 */
2796 mdic = ((reg_addr) | (phy_addr << 5) |
2797 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2798
2799 e1000_shift_out_mdi_bits(hw, mdic, 14);
2800
2801 /* Now that we've shifted out the read command to the MII, we need to
2802 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2803 * register address.
2804 */
2805 *phy_data = e1000_shift_in_mdi_bits(hw);
2806 }
2807 return E1000_SUCCESS;
1da177e4
LT		 2808}
2809
120a5d0d
JB		 2810/**
2811 * e1000_write_phy_reg - write a phy register
2812 *
2813 * @hw: Struct containing variables accessed by shared code
2814 * @reg_addr: address of the PHY register to write
2815 * @data: data to write to the PHY
2816
2817 * Writes a value to a PHY register
2818 */
64798845 2819s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
1da177e4 2820{
120a5d0d 2821 u32 ret_val;
1da177e4 2822
120a5d0d 2823 DEBUGFUNC("e1000_write_phy_reg");
1da177e4 2824
120a5d0d
JB		 2825 if ((hw->phy_type == e1000_phy_igp) &&
2826 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2827 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2828 (u16) reg_addr);
2829 if (ret_val)
2830 return ret_val;
2831 }
1da177e4 2832
120a5d0d
JB		 2833 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2834 phy_data);
1da177e4 2835
120a5d0d 2836 return ret_val;
1da177e4
LT		 2837}
2838
64798845
JP		 2839static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2840 u16 phy_data)
1da177e4 2841{
120a5d0d
JB		 2842 u32 i;
2843 u32 mdic = 0;
2844 const u32 phy_addr = 1;
2845
2846 DEBUGFUNC("e1000_write_phy_reg_ex");
2847
2848 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2849 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2850 return -E1000_ERR_PARAM;
2851 }
2852
2853 if (hw->mac_type > e1000_82543) {
2854 /* Set up Op-code, Phy Address, register address, and data intended
2855 * for the PHY register in the MDI Control register. The MAC will take
2856 * care of interfacing with the PHY to send the desired data.
2857 */
2858 mdic = (((u32) phy_data) |
2859 (reg_addr << E1000_MDIC_REG_SHIFT) |
2860 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2861 (E1000_MDIC_OP_WRITE));
2862
2863 ew32(MDIC, mdic);
2864
2865 /* Poll the ready bit to see if the MDI read completed */
2866 for (i = 0; i < 641; i++) {
2867 udelay(5);
2868 mdic = er32(MDIC);
2869 if (mdic & E1000_MDIC_READY)
2870 break;
2871 }
2872 if (!(mdic & E1000_MDIC_READY)) {
2873 DEBUGOUT("MDI Write did not complete\n");
2874 return -E1000_ERR_PHY;
2875 }
2876 } else {
2877 /* We'll need to use the SW defined pins to shift the write command
2878 * out to the PHY. We first send a preamble to the PHY to signal the
2879 * beginning of the MII instruction. This is done by sending 32
2880 * consecutive "1" bits.
2881 */
2882 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2883
2884 /* Now combine the remaining required fields that will indicate a
2885 * write operation. We use this method instead of calling the
2886 * e1000_shift_out_mdi_bits routine for each field in the command. The
2887 * format of a MII write instruction is as follows:
2888 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2889 */
2890 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2891 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2892 mdic <<= 16;
2893 mdic |= (u32) phy_data;
2894
2895 e1000_shift_out_mdi_bits(hw, mdic, 32);
2896 }
2897
2898 return E1000_SUCCESS;
1da177e4
LT		 2899}
2900
120a5d0d
JB		 2901/**
2902 * e1000_phy_hw_reset - reset the phy, hardware style
2903 * @hw: Struct containing variables accessed by shared code
2904 *
2905 * Returns the PHY to the power-on reset state
2906 */
64798845 2907s32 e1000_phy_hw_reset(struct e1000_hw *hw)
1da177e4 2908{
120a5d0d
JB		 2909 u32 ctrl, ctrl_ext;
2910 u32 led_ctrl;
2911 s32 ret_val;
2912
2913 DEBUGFUNC("e1000_phy_hw_reset");
2914
2915 DEBUGOUT("Resetting Phy...\n");
2916
2917 if (hw->mac_type > e1000_82543) {
2918 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2919 * bit. Then, take it out of reset.
2920 * For e1000 hardware, we delay for 10ms between the assert
2921 * and deassert.
2922 */
2923 ctrl = er32(CTRL);
2924 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2925 E1000_WRITE_FLUSH();
2926
2927 msleep(10);
2928
2929 ew32(CTRL, ctrl);
2930 E1000_WRITE_FLUSH();
2931
2932 } else {
2933 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2934 * bit to put the PHY into reset. Then, take it out of reset.
2935 */
2936 ctrl_ext = er32(CTRL_EXT);
2937 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2938 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2939 ew32(CTRL_EXT, ctrl_ext);
2940 E1000_WRITE_FLUSH();
2941 msleep(10);
2942 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2943 ew32(CTRL_EXT, ctrl_ext);
2944 E1000_WRITE_FLUSH();
2945 }
2946 udelay(150);
2947
2948 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2949 /* Configure activity LED after PHY reset */
2950 led_ctrl = er32(LEDCTL);
2951 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2952 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2953 ew32(LEDCTL, led_ctrl);
2954 }
2955
2956 /* Wait for FW to finish PHY configuration. */
2957 ret_val = e1000_get_phy_cfg_done(hw);
2958 if (ret_val != E1000_SUCCESS)
2959 return ret_val;
2960
2961 return ret_val;
1da177e4
LT		 2962}
2963
120a5d0d
JB		 2964/**
2965 * e1000_phy_reset - reset the phy to commit settings
2966 * @hw: Struct containing variables accessed by shared code
2967 *
2968 * Resets the PHY
2969 * Sets bit 15 of the MII Control register
2970 */
64798845 2971s32 e1000_phy_reset(struct e1000_hw *hw)
1da177e4 2972{
120a5d0d
JB		 2973 s32 ret_val;
2974 u16 phy_data;
2975
2976 DEBUGFUNC("e1000_phy_reset");
2977
2978 switch (hw->phy_type) {
2979 case e1000_phy_igp:
2980 ret_val = e1000_phy_hw_reset(hw);
2981 if (ret_val)
2982 return ret_val;
2983 break;
2984 default:
2985 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2986 if (ret_val)
2987 return ret_val;
2988
2989 phy_data |= MII_CR_RESET;
2990 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2991 if (ret_val)
2992 return ret_val;
2993
2994 udelay(1);
2995 break;
2996 }
2997
2998 if (hw->phy_type == e1000_phy_igp)
2999 e1000_phy_init_script(hw);
3000
3001 return E1000_SUCCESS;
1da177e4
LT		 3002}
3003
120a5d0d
JB		 3004/**
3005 * e1000_detect_gig_phy - check the phy type
3006 * @hw: Struct containing variables accessed by shared code
3007 *
3008 * Probes the expected PHY address for known PHY IDs
3009 */
64798845 3010static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
1da177e4 3011{
120a5d0d
JB		 3012 s32 phy_init_status, ret_val;
3013 u16 phy_id_high, phy_id_low;
3014 bool match = false;
3015
3016 DEBUGFUNC("e1000_detect_gig_phy");
3017
3018 if (hw->phy_id != 0)
3019 return E1000_SUCCESS;
3020
3021 /* Read the PHY ID Registers to identify which PHY is onboard. */
3022 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3023 if (ret_val)
3024 return ret_val;
3025
3026 hw->phy_id = (u32) (phy_id_high << 16);
3027 udelay(20);
3028 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3029 if (ret_val)
3030 return ret_val;
3031
3032 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
3033 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
3034
3035 switch (hw->mac_type) {
3036 case e1000_82543:
3037 if (hw->phy_id == M88E1000_E_PHY_ID)
3038 match = true;
3039 break;
3040 case e1000_82544:
3041 if (hw->phy_id == M88E1000_I_PHY_ID)
3042 match = true;
3043 break;
3044 case e1000_82540:
3045 case e1000_82545:
3046 case e1000_82545_rev_3:
3047 case e1000_82546:
3048 case e1000_82546_rev_3:
3049 if (hw->phy_id == M88E1011_I_PHY_ID)
3050 match = true;
3051 break;
3052 case e1000_82541:
3053 case e1000_82541_rev_2:
3054 case e1000_82547:
3055 case e1000_82547_rev_2:
3056 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3057 match = true;
3058 break;
3059 default:
3060 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3061 return -E1000_ERR_CONFIG;
3062 }
3063 phy_init_status = e1000_set_phy_type(hw);
3064
3065 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3066 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3067 return E1000_SUCCESS;
3068 }
3069 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3070 return -E1000_ERR_PHY;
1da177e4
LT		 3071}
3072
120a5d0d
JB		 3073/**
3074 * e1000_phy_reset_dsp - reset DSP
3075 * @hw: Struct containing variables accessed by shared code
3076 *
3077 * Resets the PHY's DSP
3078 */
64798845 3079static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
1da177e4 3080{
120a5d0d
JB		 3081 s32 ret_val;
3082 DEBUGFUNC("e1000_phy_reset_dsp");
3083
3084 do {
3085 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3086 if (ret_val)
3087 break;
3088 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3089 if (ret_val)
3090 break;
3091 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3092 if (ret_val)
3093 break;
3094 ret_val = E1000_SUCCESS;
3095 } while (0);
3096
3097 return ret_val;
1da177e4
LT		 3098}
3099
120a5d0d
JB		 3100/**
3101 * e1000_phy_igp_get_info - get igp specific registers
3102 * @hw: Struct containing variables accessed by shared code
3103 * @phy_info: PHY information structure
3104 *
3105 * Get PHY information from various PHY registers for igp PHY only.
3106 */
64798845
JP		 3107static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3108 struct e1000_phy_info *phy_info)
1da177e4 3109{
120a5d0d
JB		 3110 s32 ret_val;
3111 u16 phy_data, min_length, max_length, average;
3112 e1000_rev_polarity polarity;
3113
3114 DEBUGFUNC("e1000_phy_igp_get_info");
3115
3116 /* The downshift status is checked only once, after link is established,
3117 * and it stored in the hw->speed_downgraded parameter. */
3118 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3119
3120 /* IGP01E1000 does not need to support it. */
3121 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3122
3123 /* IGP01E1000 always correct polarity reversal */
3124 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3125
3126 /* Check polarity status */
3127 ret_val = e1000_check_polarity(hw, &polarity);
3128 if (ret_val)
3129 return ret_val;
3130
3131 phy_info->cable_polarity = polarity;
3132
3133 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3134 if (ret_val)
3135 return ret_val;
3136
3137 phy_info->mdix_mode =
3138 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3139 IGP01E1000_PSSR_MDIX_SHIFT);
3140
3141 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3142 IGP01E1000_PSSR_SPEED_1000MBPS) {
3143 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3144 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3145 if (ret_val)
3146 return ret_val;
3147
3148 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3149 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3150 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3151 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3152 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3153 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3154
3155 /* Get cable length */
3156 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3157 if (ret_val)
3158 return ret_val;
3159
3160 /* Translate to old method */
3161 average = (max_length + min_length) / 2;
3162
3163 if (average <= e1000_igp_cable_length_50)
3164 phy_info->cable_length = e1000_cable_length_50;
3165 else if (average <= e1000_igp_cable_length_80)
3166 phy_info->cable_length = e1000_cable_length_50_80;
3167 else if (average <= e1000_igp_cable_length_110)
3168 phy_info->cable_length = e1000_cable_length_80_110;
3169 else if (average <= e1000_igp_cable_length_140)
3170 phy_info->cable_length = e1000_cable_length_110_140;
3171 else
3172 phy_info->cable_length = e1000_cable_length_140;
3173 }
1da177e4 3174
120a5d0d
JB		 3175 return E1000_SUCCESS;
3176}
d37ea5d5 3177
120a5d0d
JB		 3178/**
3179 * e1000_phy_m88_get_info - get m88 specific registers
3180 * @hw: Struct containing variables accessed by shared code
3181 * @phy_info: PHY information structure
3182 *
3183 * Get PHY information from various PHY registers for m88 PHY only.
3184 */
64798845
JP		 3185static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3186 struct e1000_phy_info *phy_info)
1da177e4 3187{
120a5d0d
JB		 3188 s32 ret_val;
3189 u16 phy_data;
3190 e1000_rev_polarity polarity;
3191
3192 DEBUGFUNC("e1000_phy_m88_get_info");
3193
3194 /* The downshift status is checked only once, after link is established,
3195 * and it stored in the hw->speed_downgraded parameter. */
3196 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3197
3198 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3199 if (ret_val)
3200 return ret_val;
3201
3202 phy_info->extended_10bt_distance =
3203 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3204 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3205 e1000_10bt_ext_dist_enable_lower :
3206 e1000_10bt_ext_dist_enable_normal;
3207
3208 phy_info->polarity_correction =
3209 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3210 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3211 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3212
3213 /* Check polarity status */
3214 ret_val = e1000_check_polarity(hw, &polarity);
3215 if (ret_val)
3216 return ret_val;
3217 phy_info->cable_polarity = polarity;
3218
3219 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3220 if (ret_val)
3221 return ret_val;
3222
3223 phy_info->mdix_mode =
3224 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3225 M88E1000_PSSR_MDIX_SHIFT);
3226
3227 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3228 /* Cable Length Estimation and Local/Remote Receiver Information
3229 * are only valid at 1000 Mbps.
3230 */
3231 phy_info->cable_length =
3232 (e1000_cable_length) ((phy_data &
3233 M88E1000_PSSR_CABLE_LENGTH) >>
3234 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3235
3236 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3237 if (ret_val)
3238 return ret_val;
3239
3240 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3241 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3242 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3243 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3244 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3245 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3246
3247 }
3248
3249 return E1000_SUCCESS;
1da177e4
LT		 3250}
3251
120a5d0d
JB		 3252/**
3253 * e1000_phy_get_info - request phy info
3254 * @hw: Struct containing variables accessed by shared code
3255 * @phy_info: PHY information structure
3256 *
3257 * Get PHY information from various PHY registers
3258 */
64798845 3259s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
1da177e4 3260{
120a5d0d
JB		 3261 s32 ret_val;
3262 u16 phy_data;
3263
3264 DEBUGFUNC("e1000_phy_get_info");
3265
3266 phy_info->cable_length = e1000_cable_length_undefined;
3267 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3268 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3269 phy_info->downshift = e1000_downshift_undefined;
3270 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3271 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3272 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3273 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3274
3275 if (hw->media_type != e1000_media_type_copper) {
3276 DEBUGOUT("PHY info is only valid for copper media\n");
3277 return -E1000_ERR_CONFIG;
3278 }
3279
3280 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3281 if (ret_val)
3282 return ret_val;
3283
3284 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3285 if (ret_val)
3286 return ret_val;
3287
3288 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3289 DEBUGOUT("PHY info is only valid if link is up\n");
3290 return -E1000_ERR_CONFIG;
3291 }
3292
3293 if (hw->phy_type == e1000_phy_igp)
3294 return e1000_phy_igp_get_info(hw, phy_info);
3295 else
3296 return e1000_phy_m88_get_info(hw, phy_info);
1da177e4
LT		 3297}
3298
64798845 3299s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
1da177e4 3300{
120a5d0d 3301 DEBUGFUNC("e1000_validate_mdi_settings");
1da177e4 3302
120a5d0d
JB		 3303 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3304 DEBUGOUT("Invalid MDI setting detected\n");
3305 hw->mdix = 1;
3306 return -E1000_ERR_CONFIG;
3307 }
3308 return E1000_SUCCESS;
3309}
1da177e4 3310
120a5d0d
JB		 3311/**
3312 * e1000_init_eeprom_params - initialize sw eeprom vars
3313 * @hw: Struct containing variables accessed by shared code
3314 *
1da177e4 3315 * Sets up eeprom variables in the hw struct. Must be called after mac_type
1532ecea 3316 * is configured.
120a5d0d 3317 */
64798845 3318s32 e1000_init_eeprom_params(struct e1000_hw *hw)
1da177e4 3319{
120a5d0d
JB		 3320 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3321 u32 eecd = er32(EECD);
3322 s32 ret_val = E1000_SUCCESS;
3323 u16 eeprom_size;
3324
3325 DEBUGFUNC("e1000_init_eeprom_params");
3326
3327 switch (hw->mac_type) {
3328 case e1000_82542_rev2_0:
3329 case e1000_82542_rev2_1:
3330 case e1000_82543:
3331 case e1000_82544:
3332 eeprom->type = e1000_eeprom_microwire;
3333 eeprom->word_size = 64;
3334 eeprom->opcode_bits = 3;
3335 eeprom->address_bits = 6;
3336 eeprom->delay_usec = 50;
120a5d0d
JB		 3337 break;
3338 case e1000_82540:
3339 case e1000_82545:
3340 case e1000_82545_rev_3:
3341 case e1000_82546:
3342 case e1000_82546_rev_3:
3343 eeprom->type = e1000_eeprom_microwire;
3344 eeprom->opcode_bits = 3;
3345 eeprom->delay_usec = 50;
3346 if (eecd & E1000_EECD_SIZE) {
3347 eeprom->word_size = 256;
3348 eeprom->address_bits = 8;
3349 } else {
3350 eeprom->word_size = 64;
3351 eeprom->address_bits = 6;
3352 }
120a5d0d
JB		 3353 break;
3354 case e1000_82541:
3355 case e1000_82541_rev_2:
3356 case e1000_82547:
3357 case e1000_82547_rev_2:
3358 if (eecd & E1000_EECD_TYPE) {
3359 eeprom->type = e1000_eeprom_spi;
3360 eeprom->opcode_bits = 8;
3361 eeprom->delay_usec = 1;
3362 if (eecd & E1000_EECD_ADDR_BITS) {
3363 eeprom->page_size = 32;
3364 eeprom->address_bits = 16;
3365 } else {
3366 eeprom->page_size = 8;
3367 eeprom->address_bits = 8;
3368 }
3369 } else {
3370 eeprom->type = e1000_eeprom_microwire;
3371 eeprom->opcode_bits = 3;
3372 eeprom->delay_usec = 50;
3373 if (eecd & E1000_EECD_ADDR_BITS) {
3374 eeprom->word_size = 256;
3375 eeprom->address_bits = 8;
3376 } else {
3377 eeprom->word_size = 64;
3378 eeprom->address_bits = 6;
3379 }
3380 }
120a5d0d
JB		 3381 break;
3382 default:
3383 break;
3384 }
3385
3386 if (eeprom->type == e1000_eeprom_spi) {
3387 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3388 * 32KB (incremented by powers of 2).
3389 */
3390 /* Set to default value for initial eeprom read. */
3391 eeprom->word_size = 64;
3392 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3393 if (ret_val)
3394 return ret_val;
3395 eeprom_size =
3396 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3397 /* 256B eeprom size was not supported in earlier hardware, so we
3398 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3399 * is never the result used in the shifting logic below. */
3400 if (eeprom_size)
3401 eeprom_size++;
3402
3403 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3404 }
3405 return ret_val;
1da177e4
LT		 3406}
3407
120a5d0d
JB		 3408/**
3409 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3410 * @hw: Struct containing variables accessed by shared code
3411 * @eecd: EECD's current value
3412 */
64798845 3413static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
1da177e4 3414{
120a5d0d
JB		 3415 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3416 * wait <delay> microseconds.
3417 */
3418 *eecd = *eecd | E1000_EECD_SK;
3419 ew32(EECD, *eecd);
3420 E1000_WRITE_FLUSH();
3421 udelay(hw->eeprom.delay_usec);
1da177e4
LT		 3422}
3423
120a5d0d
JB		 3424/**
3425 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3426 * @hw: Struct containing variables accessed by shared code
3427 * @eecd: EECD's current value
3428 */
64798845 3429static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
1da177e4 3430{
120a5d0d
JB		 3431 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3432 * wait 50 microseconds.
3433 */
3434 *eecd = *eecd & ~E1000_EECD_SK;
3435 ew32(EECD, *eecd);
3436 E1000_WRITE_FLUSH();
3437 udelay(hw->eeprom.delay_usec);
1da177e4
LT		 3438}
3439
120a5d0d
JB		 3440/**
3441 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3442 * @hw: Struct containing variables accessed by shared code
3443 * @data: data to send to the EEPROM
3444 * @count: number of bits to shift out
3445 */
64798845 3446static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
1da177e4 3447{
120a5d0d
JB		 3448 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3449 u32 eecd;
3450 u32 mask;
3451
3452 /* We need to shift "count" bits out to the EEPROM. So, value in the
3453 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3454 * In order to do this, "data" must be broken down into bits.
3455 */
3456 mask = 0x01 << (count - 1);
3457 eecd = er32(EECD);
3458 if (eeprom->type == e1000_eeprom_microwire) {
3459 eecd &= ~E1000_EECD_DO;
3460 } else if (eeprom->type == e1000_eeprom_spi) {
3461 eecd |= E1000_EECD_DO;
3462 }
3463 do {
3464 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3465 * and then raising and then lowering the clock (the SK bit controls
3466 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3467 * by setting "DI" to "0" and then raising and then lowering the clock.
3468 */
3469 eecd &= ~E1000_EECD_DI;
3470
3471 if (data & mask)
3472 eecd |= E1000_EECD_DI;
3473
3474 ew32(EECD, eecd);
3475 E1000_WRITE_FLUSH();
3476
3477 udelay(eeprom->delay_usec);
3478
3479 e1000_raise_ee_clk(hw, &eecd);
3480 e1000_lower_ee_clk(hw, &eecd);
3481
3482 mask = mask >> 1;
3483
3484 } while (mask);
3485
3486 /* We leave the "DI" bit set to "0" when we leave this routine. */
3487 eecd &= ~E1000_EECD_DI;
3488 ew32(EECD, eecd);
1da177e4
LT		 3489}
3490
120a5d0d
JB		 3491/**
3492 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3493 * @hw: Struct containing variables accessed by shared code
3494 * @count: number of bits to shift in
3495 */
64798845 3496static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
1da177e4 3497{
120a5d0d
JB		 3498 u32 eecd;
3499 u32 i;
3500 u16 data;
3501
3502 /* In order to read a register from the EEPROM, we need to shift 'count'
3503 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3504 * input to the EEPROM (setting the SK bit), and then reading the value of
3505 * the "DO" bit. During this "shifting in" process the "DI" bit should
3506 * always be clear.
3507 */
1da177e4 3508
120a5d0d 3509 eecd = er32(EECD);
1da177e4 3510
120a5d0d
JB		 3511 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3512 data = 0;
1da177e4 3513
120a5d0d
JB		 3514 for (i = 0; i < count; i++) {
3515 data = data << 1;
3516 e1000_raise_ee_clk(hw, &eecd);
1da177e4 3517
120a5d0d 3518 eecd = er32(EECD);
1da177e4 3519
120a5d0d
JB		 3520 eecd &= ~(E1000_EECD_DI);
3521 if (eecd & E1000_EECD_DO)
3522 data |= 1;
1da177e4 3523
120a5d0d
JB		 3524 e1000_lower_ee_clk(hw, &eecd);
3525 }
1da177e4 3526
120a5d0d 3527 return data;
1da177e4
LT		 3528}
3529
120a5d0d
JB		 3530/**
3531 * e1000_acquire_eeprom - Prepares EEPROM for access
3532 * @hw: Struct containing variables accessed by shared code
1da177e4
LT		 3533 *
3534 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3535 * function should be called before issuing a command to the EEPROM.
120a5d0d 3536 */
64798845 3537static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
1da177e4 3538{
120a5d0d
JB		 3539 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3540 u32 eecd, i = 0;
3541
3542 DEBUGFUNC("e1000_acquire_eeprom");
3543
3544 eecd = er32(EECD);
3545
3546 /* Request EEPROM Access */
3547 if (hw->mac_type > e1000_82544) {
3548 eecd |= E1000_EECD_REQ;
3549 ew32(EECD, eecd);
3550 eecd = er32(EECD);
3551 while ((!(eecd & E1000_EECD_GNT)) &&
3552 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3553 i++;
3554 udelay(5);
3555 eecd = er32(EECD);
3556 }
3557 if (!(eecd & E1000_EECD_GNT)) {
3558 eecd &= ~E1000_EECD_REQ;
3559 ew32(EECD, eecd);
3560 DEBUGOUT("Could not acquire EEPROM grant\n");
3561 return -E1000_ERR_EEPROM;
3562 }
3563 }
3564
3565 /* Setup EEPROM for Read/Write */
3566
3567 if (eeprom->type == e1000_eeprom_microwire) {
3568 /* Clear SK and DI */
3569 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3570 ew32(EECD, eecd);
3571
3572 /* Set CS */
3573 eecd |= E1000_EECD_CS;
3574 ew32(EECD, eecd);
3575 } else if (eeprom->type == e1000_eeprom_spi) {
3576 /* Clear SK and CS */
3577 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3578 ew32(EECD, eecd);
3579 udelay(1);
3580 }
3581
3582 return E1000_SUCCESS;
1da177e4
LT		 3583}
3584
120a5d0d
JB		 3585/**
3586 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3587 * @hw: Struct containing variables accessed by shared code
3588 */
64798845 3589static void e1000_standby_eeprom(struct e1000_hw *hw)
1da177e4 3590{
120a5d0d
JB		 3591 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3592 u32 eecd;
3593
3594 eecd = er32(EECD);
3595
3596 if (eeprom->type == e1000_eeprom_microwire) {
3597 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3598 ew32(EECD, eecd);
3599 E1000_WRITE_FLUSH();
3600 udelay(eeprom->delay_usec);
3601
3602 /* Clock high */
3603 eecd |= E1000_EECD_SK;
3604 ew32(EECD, eecd);
3605 E1000_WRITE_FLUSH();
3606 udelay(eeprom->delay_usec);
3607
3608 /* Select EEPROM */
3609 eecd |= E1000_EECD_CS;
3610 ew32(EECD, eecd);
3611 E1000_WRITE_FLUSH();
3612 udelay(eeprom->delay_usec);
3613
3614 /* Clock low */
3615 eecd &= ~E1000_EECD_SK;
3616 ew32(EECD, eecd);
3617 E1000_WRITE_FLUSH();
3618 udelay(eeprom->delay_usec);
3619 } else if (eeprom->type == e1000_eeprom_spi) {
3620 /* Toggle CS to flush commands */
3621 eecd |= E1000_EECD_CS;
3622 ew32(EECD, eecd);
3623 E1000_WRITE_FLUSH();
3624 udelay(eeprom->delay_usec);
3625 eecd &= ~E1000_EECD_CS;
3626 ew32(EECD, eecd);
3627 E1000_WRITE_FLUSH();
3628 udelay(eeprom->delay_usec);
3629 }
1da177e4
LT		 3630}
3631
120a5d0d
JB		 3632/**
3633 * e1000_release_eeprom - drop chip select
3634 * @hw: Struct containing variables accessed by shared code
1da177e4 3635 *
120a5d0d
JB		 3636 * Terminates a command by inverting the EEPROM's chip select pin
3637 */
64798845 3638static void e1000_release_eeprom(struct e1000_hw *hw)
1da177e4 3639{
120a5d0d 3640 u32 eecd;
1da177e4 3641
120a5d0d 3642 DEBUGFUNC("e1000_release_eeprom");
1da177e4 3643
120a5d0d 3644 eecd = er32(EECD);
1da177e4 3645
120a5d0d
JB		 3646 if (hw->eeprom.type == e1000_eeprom_spi) {
3647 eecd |= E1000_EECD_CS; /* Pull CS high */
3648 eecd &= ~E1000_EECD_SK; /* Lower SCK */
1da177e4 3649
120a5d0d 3650 ew32(EECD, eecd);
1da177e4 3651
120a5d0d
JB		 3652 udelay(hw->eeprom.delay_usec);
3653 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3654 /* cleanup eeprom */
1da177e4 3655
120a5d0d
JB		 3656 /* CS on Microwire is active-high */
3657 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
1da177e4 3658
120a5d0d 3659 ew32(EECD, eecd);
1da177e4 3660
120a5d0d
JB		 3661 /* Rising edge of clock */
3662 eecd |= E1000_EECD_SK;
3663 ew32(EECD, eecd);
3664 E1000_WRITE_FLUSH();
3665 udelay(hw->eeprom.delay_usec);
1da177e4 3666
120a5d0d
JB		 3667 /* Falling edge of clock */
3668 eecd &= ~E1000_EECD_SK;
3669 ew32(EECD, eecd);
3670 E1000_WRITE_FLUSH();
3671 udelay(hw->eeprom.delay_usec);
3672 }
1da177e4 3673
120a5d0d
JB		 3674 /* Stop requesting EEPROM access */
3675 if (hw->mac_type > e1000_82544) {
3676 eecd &= ~E1000_EECD_REQ;
3677 ew32(EECD, eecd);
3678 }
1da177e4
LT		 3679}
3680
120a5d0d
JB		 3681/**
3682 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3683 * @hw: Struct containing variables accessed by shared code
3684 */
64798845 3685static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
1da177e4 3686{
120a5d0d
JB		 3687 u16 retry_count = 0;
3688 u8 spi_stat_reg;
3689
3690 DEBUGFUNC("e1000_spi_eeprom_ready");
3691
3692 /* Read "Status Register" repeatedly until the LSB is cleared. The
3693 * EEPROM will signal that the command has been completed by clearing
3694 * bit 0 of the internal status register. If it's not cleared within
3695 * 5 milliseconds, then error out.
3696 */
3697 retry_count = 0;
3698 do {
3699 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3700 hw->eeprom.opcode_bits);
3701 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3702 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3703 break;
3704
3705 udelay(5);
3706 retry_count += 5;
3707
3708 e1000_standby_eeprom(hw);
3709 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3710
3711 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3712 * only 0-5mSec on 5V devices)
3713 */
3714 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3715 DEBUGOUT("SPI EEPROM Status error\n");
3716 return -E1000_ERR_EEPROM;
3717 }
3718
3719 return E1000_SUCCESS;
1da177e4
LT		 3720}
3721
120a5d0d
JB		 3722/**
3723 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3724 * @hw: Struct containing variables accessed by shared code
3725 * @offset: offset of word in the EEPROM to read
3726 * @data: word read from the EEPROM
3727 * @words: number of words to read
3728 */
64798845 3729s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
78566fec 3730{
120a5d0d
JB		 3731 s32 ret;
3732 spin_lock(&e1000_eeprom_lock);
3733 ret = e1000_do_read_eeprom(hw, offset, words, data);
3734 spin_unlock(&e1000_eeprom_lock);
3735 return ret;
78566fec
CL		 3736}
3737
120a5d0d
JB		 3738static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3739 u16 *data)
1da177e4 3740{
120a5d0d
JB		 3741 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3742 u32 i = 0;
3743
3744 DEBUGFUNC("e1000_read_eeprom");
3745
3746 /* If eeprom is not yet detected, do so now */
3747 if (eeprom->word_size == 0)
3748 e1000_init_eeprom_params(hw);
3749
3750 /* A check for invalid values: offset too large, too many words, and not
3751 * enough words.
3752 */
3753 if ((offset >= eeprom->word_size)
3754 || (words > eeprom->word_size - offset) || (words == 0)) {
3755 DEBUGOUT2
3756 ("\"words\" parameter out of bounds. Words = %d, size = %d\n",
3757 offset, eeprom->word_size);
3758 return -E1000_ERR_EEPROM;
3759 }
3760
3761 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3762 * directly. In this case, we need to acquire the EEPROM so that
3763 * FW or other port software does not interrupt.
3764 */
8f601b2d
JB		 3765 /* Prepare the EEPROM for bit-bang reading */
3766 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3767 return -E1000_ERR_EEPROM;
120a5d0d
JB		 3768
3769 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3770 * acquired the EEPROM at this point, so any returns should release it */
3771 if (eeprom->type == e1000_eeprom_spi) {
3772 u16 word_in;
3773 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3774
3775 if (e1000_spi_eeprom_ready(hw)) {
3776 e1000_release_eeprom(hw);
3777 return -E1000_ERR_EEPROM;
3778 }
3779
3780 e1000_standby_eeprom(hw);
3781
3782 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3783 if ((eeprom->address_bits == 8) && (offset >= 128))
3784 read_opcode |= EEPROM_A8_OPCODE_SPI;
3785
3786 /* Send the READ command (opcode + addr) */
3787 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3788 e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3789 eeprom->address_bits);
3790
3791 /* Read the data. The address of the eeprom internally increments with
3792 * each byte (spi) being read, saving on the overhead of eeprom setup
3793 * and tear-down. The address counter will roll over if reading beyond
3794 * the size of the eeprom, thus allowing the entire memory to be read
3795 * starting from any offset. */
3796 for (i = 0; i < words; i++) {
3797 word_in = e1000_shift_in_ee_bits(hw, 16);
3798 data[i] = (word_in >> 8) | (word_in << 8);
3799 }
3800 } else if (eeprom->type == e1000_eeprom_microwire) {
3801 for (i = 0; i < words; i++) {
3802 /* Send the READ command (opcode + addr) */
3803 e1000_shift_out_ee_bits(hw,
3804 EEPROM_READ_OPCODE_MICROWIRE,
3805 eeprom->opcode_bits);
3806 e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3807 eeprom->address_bits);
3808
3809 /* Read the data. For microwire, each word requires the overhead
3810 * of eeprom setup and tear-down. */
3811 data[i] = e1000_shift_in_ee_bits(hw, 16);
3812 e1000_standby_eeprom(hw);
3813 }
3814 }
3815
3816 /* End this read operation */
3817 e1000_release_eeprom(hw);
3818
3819 return E1000_SUCCESS;
1da177e4
LT		 3820}
3821
120a5d0d
JB		 3822/**
3823 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
3824 * @hw: Struct containing variables accessed by shared code
2d7edb92
MC		 3825 *
3826 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3827 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3828 * valid.
120a5d0d 3829 */
64798845 3830s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
2d7edb92 3831{
120a5d0d
JB		 3832 u16 checksum = 0;
3833 u16 i, eeprom_data;
3834
3835 DEBUGFUNC("e1000_validate_eeprom_checksum");
3836
3837 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3838 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3839 DEBUGOUT("EEPROM Read Error\n");
3840 return -E1000_ERR_EEPROM;
3841 }
3842 checksum += eeprom_data;
3843 }
3844
3845 if (checksum == (u16) EEPROM_SUM)
3846 return E1000_SUCCESS;
3847 else {
3848 DEBUGOUT("EEPROM Checksum Invalid\n");
3849 return -E1000_ERR_EEPROM;
3850 }
2d7edb92
MC		 3851}
3852
120a5d0d
JB		 3853/**
3854 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
3855 * @hw: Struct containing variables accessed by shared code
2d7edb92
MC		 3856 *
3857 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3858 * Writes the difference to word offset 63 of the EEPROM.
120a5d0d 3859 */
64798845 3860s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
2d7edb92 3861{
120a5d0d
JB		 3862 u16 checksum = 0;
3863 u16 i, eeprom_data;
3864
3865 DEBUGFUNC("e1000_update_eeprom_checksum");
3866
3867 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3868 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3869 DEBUGOUT("EEPROM Read Error\n");
3870 return -E1000_ERR_EEPROM;
3871 }
3872 checksum += eeprom_data;
3873 }
3874 checksum = (u16) EEPROM_SUM - checksum;
3875 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3876 DEBUGOUT("EEPROM Write Error\n");
3877 return -E1000_ERR_EEPROM;
3878 }
3879 return E1000_SUCCESS;
1da177e4
LT		 3880}
3881
120a5d0d
JB		 3882/**
3883 * e1000_write_eeprom - write words to the different EEPROM types.
3884 * @hw: Struct containing variables accessed by shared code
3885 * @offset: offset within the EEPROM to be written to
3886 * @words: number of words to write
3887 * @data: 16 bit word to be written to the EEPROM
1da177e4
LT		 3888 *
3889 * If e1000_update_eeprom_checksum is not called after this function, the
3890 * EEPROM will most likely contain an invalid checksum.
120a5d0d 3891 */
64798845 3892s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
78566fec 3893{
120a5d0d
JB		 3894 s32 ret;
3895 spin_lock(&e1000_eeprom_lock);
3896 ret = e1000_do_write_eeprom(hw, offset, words, data);
3897 spin_unlock(&e1000_eeprom_lock);
3898 return ret;
78566fec
CL		 3899}
3900
120a5d0d
JB		 3901static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3902 u16 *data)
1da177e4 3903{
120a5d0d
JB		 3904 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3905 s32 status = 0;
3906
3907 DEBUGFUNC("e1000_write_eeprom");
3908
3909 /* If eeprom is not yet detected, do so now */
3910 if (eeprom->word_size == 0)
3911 e1000_init_eeprom_params(hw);
3912
3913 /* A check for invalid values: offset too large, too many words, and not
3914 * enough words.
3915 */
3916 if ((offset >= eeprom->word_size)
3917 || (words > eeprom->word_size - offset) || (words == 0)) {
3918 DEBUGOUT("\"words\" parameter out of bounds\n");
3919 return -E1000_ERR_EEPROM;
3920 }
3921
120a5d0d
JB		 3922 /* Prepare the EEPROM for writing */
3923 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3924 return -E1000_ERR_EEPROM;
3925
3926 if (eeprom->type == e1000_eeprom_microwire) {
3927 status = e1000_write_eeprom_microwire(hw, offset, words, data);
3928 } else {
3929 status = e1000_write_eeprom_spi(hw, offset, words, data);
3930 msleep(10);
3931 }
3932
3933 /* Done with writing */
3934 e1000_release_eeprom(hw);
3935
3936 return status;
1da177e4
LT		 3937}
3938
120a5d0d
JB		 3939/**
3940 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
3941 * @hw: Struct containing variables accessed by shared code
3942 * @offset: offset within the EEPROM to be written to
3943 * @words: number of words to write
3944 * @data: pointer to array of 8 bit words to be written to the EEPROM
3945 */
64798845
JP		 3946static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
3947 u16 *data)
1da177e4 3948{
120a5d0d
JB		 3949 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3950 u16 widx = 0;
1da177e4 3951
120a5d0d 3952 DEBUGFUNC("e1000_write_eeprom_spi");
1da177e4 3953
120a5d0d
JB		 3954 while (widx < words) {
3955 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
1da177e4 3956
120a5d0d
JB		 3957 if (e1000_spi_eeprom_ready(hw))
3958 return -E1000_ERR_EEPROM;
1da177e4 3959
120a5d0d 3960 e1000_standby_eeprom(hw);
1da177e4 3961
120a5d0d
JB		 3962 /* Send the WRITE ENABLE command (8 bit opcode ) */
3963 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3964 eeprom->opcode_bits);
1da177e4 3965
120a5d0d 3966 e1000_standby_eeprom(hw);
1da177e4 3967
120a5d0d
JB		 3968 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3969 if ((eeprom->address_bits == 8) && (offset >= 128))
3970 write_opcode |= EEPROM_A8_OPCODE_SPI;
1da177e4 3971
120a5d0d
JB		 3972 /* Send the Write command (8-bit opcode + addr) */
3973 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
1da177e4 3974
120a5d0d
JB		 3975 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
3976 eeprom->address_bits);
1da177e4 3977
120a5d0d 3978 /* Send the data */
1da177e4 3979
120a5d0d
JB		 3980 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3981 while (widx < words) {
3982 u16 word_out = data[widx];
3983 word_out = (word_out >> 8) | (word_out << 8);
3984 e1000_shift_out_ee_bits(hw, word_out, 16);
3985 widx++;
1da177e4 3986
120a5d0d
JB		 3987 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3988 * operation, while the smaller eeproms are capable of an 8-byte
3989 * PAGE WRITE operation. Break the inner loop to pass new address
3990 */
3991 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
3992 e1000_standby_eeprom(hw);
3993 break;
3994 }
3995 }
3996 }
1da177e4 3997
120a5d0d 3998 return E1000_SUCCESS;
1da177e4
LT		 3999}
4000
120a5d0d
JB		 4001/**
4002 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4003 * @hw: Struct containing variables accessed by shared code
4004 * @offset: offset within the EEPROM to be written to
4005 * @words: number of words to write
4006 * @data: pointer to array of 8 bit words to be written to the EEPROM
4007 */
64798845
JP		 4008static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4009 u16 words, u16 *data)
1da177e4 4010{
120a5d0d
JB		 4011 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4012 u32 eecd;
4013 u16 words_written = 0;
4014 u16 i = 0;
4015
4016 DEBUGFUNC("e1000_write_eeprom_microwire");
4017
4018 /* Send the write enable command to the EEPROM (3-bit opcode plus
4019 * 6/8-bit dummy address beginning with 11). It's less work to include
4020 * the 11 of the dummy address as part of the opcode than it is to shift
4021 * it over the correct number of bits for the address. This puts the
4022 * EEPROM into write/erase mode.
4023 */
4024 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4025 (u16) (eeprom->opcode_bits + 2));
4026
4027 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4028
4029 /* Prepare the EEPROM */
4030 e1000_standby_eeprom(hw);
4031
4032 while (words_written < words) {
4033 /* Send the Write command (3-bit opcode + addr) */
4034 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4035 eeprom->opcode_bits);
4036
4037 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
4038 eeprom->address_bits);
4039
4040 /* Send the data */
4041 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4042
4043 /* Toggle the CS line. This in effect tells the EEPROM to execute
4044 * the previous command.
4045 */
4046 e1000_standby_eeprom(hw);
4047
4048 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4049 * signal that the command has been completed by raising the DO signal.
4050 * If DO does not go high in 10 milliseconds, then error out.
4051 */
4052 for (i = 0; i < 200; i++) {
4053 eecd = er32(EECD);
4054 if (eecd & E1000_EECD_DO)
4055 break;
4056 udelay(50);
4057 }
4058 if (i == 200) {
4059 DEBUGOUT("EEPROM Write did not complete\n");
4060 return -E1000_ERR_EEPROM;
4061 }
4062
4063 /* Recover from write */
4064 e1000_standby_eeprom(hw);
4065
4066 words_written++;
4067 }
4068
4069 /* Send the write disable command to the EEPROM (3-bit opcode plus
4070 * 6/8-bit dummy address beginning with 10). It's less work to include
4071 * the 10 of the dummy address as part of the opcode than it is to shift
4072 * it over the correct number of bits for the address. This takes the
4073 * EEPROM out of write/erase mode.
4074 */
4075 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4076 (u16) (eeprom->opcode_bits + 2));
4077
4078 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4079
4080 return E1000_SUCCESS;
1da177e4
LT		 4081}
4082
120a5d0d
JB		 4083/**
4084 * e1000_read_mac_addr - read the adapters MAC from eeprom
4085 * @hw: Struct containing variables accessed by shared code
4086 *
1da177e4
LT		 4087 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4088 * second function of dual function devices
120a5d0d 4089 */
64798845 4090s32 e1000_read_mac_addr(struct e1000_hw *hw)
1da177e4 4091{
120a5d0d
JB		 4092 u16 offset;
4093 u16 eeprom_data, i;
4094
4095 DEBUGFUNC("e1000_read_mac_addr");
4096
4097 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4098 offset = i >> 1;
4099 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4100 DEBUGOUT("EEPROM Read Error\n");
4101 return -E1000_ERR_EEPROM;
4102 }
4103 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
4104 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
4105 }
4106
4107 switch (hw->mac_type) {
4108 default:
4109 break;
4110 case e1000_82546:
4111 case e1000_82546_rev_3:
4112 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4113 hw->perm_mac_addr[5] ^= 0x01;
4114 break;
4115 }
4116
4117 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4118 hw->mac_addr[i] = hw->perm_mac_addr[i];
4119 return E1000_SUCCESS;
1da177e4
LT		 4120}
4121
120a5d0d
JB		 4122/**
4123 * e1000_init_rx_addrs - Initializes receive address filters.
4124 * @hw: Struct containing variables accessed by shared code
1da177e4
LT		 4125 *
4126 * Places the MAC address in receive address register 0 and clears the rest
120a5d0d 4127 * of the receive address registers. Clears the multicast table. Assumes
1da177e4 4128 * the receiver is in reset when the routine is called.
120a5d0d 4129 */
64798845 4130static void e1000_init_rx_addrs(struct e1000_hw *hw)
1da177e4 4131{
120a5d0d
JB		 4132 u32 i;
4133 u32 rar_num;
1da177e4 4134
120a5d0d 4135 DEBUGFUNC("e1000_init_rx_addrs");
1da177e4 4136
120a5d0d
JB		 4137 /* Setup the receive address. */
4138 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1da177e4 4139
120a5d0d 4140 e1000_rar_set(hw, hw->mac_addr, 0);
1da177e4 4141
120a5d0d 4142 rar_num = E1000_RAR_ENTRIES;
868d5309 4143
120a5d0d
JB		 4144 /* Zero out the other 15 receive addresses. */
4145 DEBUGOUT("Clearing RAR[1-15]\n");
4146 for (i = 1; i < rar_num; i++) {
4147 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4148 E1000_WRITE_FLUSH();
4149 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4150 E1000_WRITE_FLUSH();
4151 }
1da177e4
LT		 4152}
4153
120a5d0d
JB		 4154/**
4155 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4156 * @hw: Struct containing variables accessed by shared code
4157 * @mc_addr: the multicast address to hash
4158 */
64798845 4159u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
1da177e4 4160{
120a5d0d
JB		 4161 u32 hash_value = 0;
4162
4163 /* The portion of the address that is used for the hash table is
4164 * determined by the mc_filter_type setting.
4165 */
4166 switch (hw->mc_filter_type) {
4167 /* [0] [1] [2] [3] [4] [5]
4168 * 01 AA 00 12 34 56
4169 * LSB MSB
4170 */
4171 case 0:
4172 /* [47:36] i.e. 0x563 for above example address */
4173 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
4174 break;
4175 case 1:
4176 /* [46:35] i.e. 0xAC6 for above example address */
4177 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
4178 break;
4179 case 2:
4180 /* [45:34] i.e. 0x5D8 for above example address */
4181 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
4182 break;
4183 case 3:
4184 /* [43:32] i.e. 0x634 for above example address */
4185 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
4186 break;
4187 }
4188
4189 hash_value &= 0xFFF;
4190 return hash_value;
1da177e4
LT		 4191}
4192
120a5d0d
JB		 4193/**
4194 * e1000_rar_set - Puts an ethernet address into a receive address register.
4195 * @hw: Struct containing variables accessed by shared code
4196 * @addr: Address to put into receive address register
4197 * @index: Receive address register to write
4198 */
64798845 4199void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
1da177e4 4200{
120a5d0d
JB		 4201 u32 rar_low, rar_high;
4202
4203 /* HW expects these in little endian so we reverse the byte order
4204 * from network order (big endian) to little endian
4205 */
4206 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
4207 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
4208 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
4209
4210 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4211 * unit hang.
4212 *
4213 * Description:
4214 * If there are any Rx frames queued up or otherwise present in the HW
4215 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4216 * hang. To work around this issue, we have to disable receives and
4217 * flush out all Rx frames before we enable RSS. To do so, we modify we
4218 * redirect all Rx traffic to manageability and then reset the HW.
4219 * This flushes away Rx frames, and (since the redirections to
4220 * manageability persists across resets) keeps new ones from coming in
4221 * while we work. Then, we clear the Address Valid AV bit for all MAC
4222 * addresses and undo the re-direction to manageability.
4223 * Now, frames are coming in again, but the MAC won't accept them, so
4224 * far so good. We now proceed to initialize RSS (if necessary) and
4225 * configure the Rx unit. Last, we re-enable the AV bits and continue
4226 * on our merry way.
4227 */
4228 switch (hw->mac_type) {
4229 default:
4230 /* Indicate to hardware the Address is Valid. */
4231 rar_high |= E1000_RAH_AV;
4232 break;
4233 }
4234
4235 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4236 E1000_WRITE_FLUSH();
4237 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4238 E1000_WRITE_FLUSH();
1da177e4
LT		 4239}
4240
120a5d0d
JB		 4241/**
4242 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4243 * @hw: Struct containing variables accessed by shared code
4244 * @offset: Offset in VLAN filer table to write
4245 * @value: Value to write into VLAN filter table
4246 */
64798845 4247void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
1da177e4 4248{
120a5d0d
JB		 4249 u32 temp;
4250
4251 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4252 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4253 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4254 E1000_WRITE_FLUSH();
4255 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4256 E1000_WRITE_FLUSH();
4257 } else {
4258 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4259 E1000_WRITE_FLUSH();
4260 }
1da177e4
LT		 4261}
4262
120a5d0d
JB		 4263/**
4264 * e1000_clear_vfta - Clears the VLAN filer table
4265 * @hw: Struct containing variables accessed by shared code
4266 */
64798845 4267static void e1000_clear_vfta(struct e1000_hw *hw)
1da177e4 4268{
120a5d0d
JB		 4269 u32 offset;
4270 u32 vfta_value = 0;
4271 u32 vfta_offset = 0;
4272 u32 vfta_bit_in_reg = 0;
4273
4274 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4275 /* If the offset we want to clear is the same offset of the
4276 * manageability VLAN ID, then clear all bits except that of the
4277 * manageability unit */
4278 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4279 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4280 E1000_WRITE_FLUSH();
4281 }
1da177e4
LT		 4282}
4283
64798845 4284static s32 e1000_id_led_init(struct e1000_hw *hw)
1da177e4 4285{
120a5d0d
JB		 4286 u32 ledctl;
4287 const u32 ledctl_mask = 0x000000FF;
4288 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4289 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4290 u16 eeprom_data, i, temp;
4291 const u16 led_mask = 0x0F;
4292
4293 DEBUGFUNC("e1000_id_led_init");
4294
4295 if (hw->mac_type < e1000_82540) {
4296 /* Nothing to do */
4297 return E1000_SUCCESS;
4298 }
4299
4300 ledctl = er32(LEDCTL);
4301 hw->ledctl_default = ledctl;
4302 hw->ledctl_mode1 = hw->ledctl_default;
4303 hw->ledctl_mode2 = hw->ledctl_default;
4304
4305 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4306 DEBUGOUT("EEPROM Read Error\n");
4307 return -E1000_ERR_EEPROM;
4308 }
4309
4310 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4311 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4312 eeprom_data = ID_LED_DEFAULT;
4313 }
4314
4315 for (i = 0; i < 4; i++) {
4316 temp = (eeprom_data >> (i << 2)) & led_mask;
4317 switch (temp) {
4318 case ID_LED_ON1_DEF2:
4319 case ID_LED_ON1_ON2:
4320 case ID_LED_ON1_OFF2:
4321 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4322 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4323 break;
4324 case ID_LED_OFF1_DEF2:
4325 case ID_LED_OFF1_ON2:
4326 case ID_LED_OFF1_OFF2:
4327 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4328 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4329 break;
4330 default:
4331 /* Do nothing */
4332 break;
4333 }
4334 switch (temp) {
4335 case ID_LED_DEF1_ON2:
4336 case ID_LED_ON1_ON2:
4337 case ID_LED_OFF1_ON2:
4338 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4339 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4340 break;
4341 case ID_LED_DEF1_OFF2:
4342 case ID_LED_ON1_OFF2:
4343 case ID_LED_OFF1_OFF2:
4344 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4345 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4346 break;
4347 default:
4348 /* Do nothing */
4349 break;
4350 }
4351 }
4352 return E1000_SUCCESS;
1da177e4
LT		 4353}
4354
120a5d0d
JB		 4355/**
4356 * e1000_setup_led
4357 * @hw: Struct containing variables accessed by shared code
1da177e4 4358 *
120a5d0d
JB		 4359 * Prepares SW controlable LED for use and saves the current state of the LED.
4360 */
64798845 4361s32 e1000_setup_led(struct e1000_hw *hw)
1da177e4 4362{
120a5d0d
JB		 4363 u32 ledctl;
4364 s32 ret_val = E1000_SUCCESS;
4365
4366 DEBUGFUNC("e1000_setup_led");
4367
4368 switch (hw->mac_type) {
4369 case e1000_82542_rev2_0:
4370 case e1000_82542_rev2_1:
4371 case e1000_82543:
4372 case e1000_82544:
4373 /* No setup necessary */
4374 break;
4375 case e1000_82541:
4376 case e1000_82547:
4377 case e1000_82541_rev_2:
4378 case e1000_82547_rev_2:
4379 /* Turn off PHY Smart Power Down (if enabled) */
4380 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4381 &hw->phy_spd_default);
4382 if (ret_val)
4383 return ret_val;
4384 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4385 (u16) (hw->phy_spd_default &
4386 ~IGP01E1000_GMII_SPD));
4387 if (ret_val)
4388 return ret_val;
4389 /* Fall Through */
4390 default:
4391 if (hw->media_type == e1000_media_type_fiber) {
4392 ledctl = er32(LEDCTL);
4393 /* Save current LEDCTL settings */
4394 hw->ledctl_default = ledctl;
4395 /* Turn off LED0 */
4396 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4397 E1000_LEDCTL_LED0_BLINK |
4398 E1000_LEDCTL_LED0_MODE_MASK);
4399 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4400 E1000_LEDCTL_LED0_MODE_SHIFT);
4401 ew32(LEDCTL, ledctl);
4402 } else if (hw->media_type == e1000_media_type_copper)
4403 ew32(LEDCTL, hw->ledctl_mode1);
4404 break;
4405 }
4406
4407 return E1000_SUCCESS;
1da177e4
LT		 4408}
4409
120a5d0d
JB		 4410/**
4411 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4412 * @hw: Struct containing variables accessed by shared code
4413 */
64798845 4414s32 e1000_cleanup_led(struct e1000_hw *hw)
1da177e4 4415{
120a5d0d
JB		 4416 s32 ret_val = E1000_SUCCESS;
4417
4418 DEBUGFUNC("e1000_cleanup_led");
4419
4420 switch (hw->mac_type) {
4421 case e1000_82542_rev2_0:
4422 case e1000_82542_rev2_1:
4423 case e1000_82543:
4424 case e1000_82544:
4425 /* No cleanup necessary */
4426 break;
4427 case e1000_82541:
4428 case e1000_82547:
4429 case e1000_82541_rev_2:
4430 case e1000_82547_rev_2:
4431 /* Turn on PHY Smart Power Down (if previously enabled) */
4432 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4433 hw->phy_spd_default);
4434 if (ret_val)
4435 return ret_val;
4436 /* Fall Through */
4437 default:
4438 /* Restore LEDCTL settings */
4439 ew32(LEDCTL, hw->ledctl_default);
4440 break;
4441 }
4442
4443 return E1000_SUCCESS;
1da177e4
LT		 4444}
4445
120a5d0d
JB		 4446/**
4447 * e1000_led_on - Turns on the software controllable LED
4448 * @hw: Struct containing variables accessed by shared code
4449 */
64798845 4450s32 e1000_led_on(struct e1000_hw *hw)
1da177e4 4451{
120a5d0d
JB		 4452 u32 ctrl = er32(CTRL);
4453
4454 DEBUGFUNC("e1000_led_on");
4455
4456 switch (hw->mac_type) {
4457 case e1000_82542_rev2_0:
4458 case e1000_82542_rev2_1:
4459 case e1000_82543:
4460 /* Set SW Defineable Pin 0 to turn on the LED */
4461 ctrl |= E1000_CTRL_SWDPIN0;
4462 ctrl |= E1000_CTRL_SWDPIO0;
4463 break;
4464 case e1000_82544:
4465 if (hw->media_type == e1000_media_type_fiber) {
4466 /* Set SW Defineable Pin 0 to turn on the LED */
4467 ctrl |= E1000_CTRL_SWDPIN0;
4468 ctrl |= E1000_CTRL_SWDPIO0;
4469 } else {
4470 /* Clear SW Defineable Pin 0 to turn on the LED */
4471 ctrl &= ~E1000_CTRL_SWDPIN0;
4472 ctrl |= E1000_CTRL_SWDPIO0;
4473 }
4474 break;
4475 default:
4476 if (hw->media_type == e1000_media_type_fiber) {
4477 /* Clear SW Defineable Pin 0 to turn on the LED */
4478 ctrl &= ~E1000_CTRL_SWDPIN0;
4479 ctrl |= E1000_CTRL_SWDPIO0;
4480 } else if (hw->media_type == e1000_media_type_copper) {
4481 ew32(LEDCTL, hw->ledctl_mode2);
4482 return E1000_SUCCESS;
4483 }
4484 break;
4485 }
4486
4487 ew32(CTRL, ctrl);
4488
4489 return E1000_SUCCESS;
1da177e4
LT		 4490}
4491
120a5d0d
JB		 4492/**
4493 * e1000_led_off - Turns off the software controllable LED
4494 * @hw: Struct containing variables accessed by shared code
4495 */
64798845 4496s32 e1000_led_off(struct e1000_hw *hw)
1da177e4 4497{
120a5d0d
JB		 4498 u32 ctrl = er32(CTRL);
4499
4500 DEBUGFUNC("e1000_led_off");
4501
4502 switch (hw->mac_type) {
4503 case e1000_82542_rev2_0:
4504 case e1000_82542_rev2_1:
4505 case e1000_82543:
4506 /* Clear SW Defineable Pin 0 to turn off the LED */
4507 ctrl &= ~E1000_CTRL_SWDPIN0;
4508 ctrl |= E1000_CTRL_SWDPIO0;
4509 break;
4510 case e1000_82544:
4511 if (hw->media_type == e1000_media_type_fiber) {
4512 /* Clear SW Defineable Pin 0 to turn off the LED */
4513 ctrl &= ~E1000_CTRL_SWDPIN0;
4514 ctrl |= E1000_CTRL_SWDPIO0;
4515 } else {
4516 /* Set SW Defineable Pin 0 to turn off the LED */
4517 ctrl |= E1000_CTRL_SWDPIN0;
4518 ctrl |= E1000_CTRL_SWDPIO0;
4519 }
4520 break;
4521 default:
4522 if (hw->media_type == e1000_media_type_fiber) {
4523 /* Set SW Defineable Pin 0 to turn off the LED */
4524 ctrl |= E1000_CTRL_SWDPIN0;
4525 ctrl |= E1000_CTRL_SWDPIO0;
4526 } else if (hw->media_type == e1000_media_type_copper) {
4527 ew32(LEDCTL, hw->ledctl_mode1);
4528 return E1000_SUCCESS;
4529 }
4530 break;
4531 }
4532
4533 ew32(CTRL, ctrl);
4534
4535 return E1000_SUCCESS;
1da177e4
LT		 4536}
4537
120a5d0d
JB		 4538/**
4539 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4540 * @hw: Struct containing variables accessed by shared code
4541 */
64798845 4542static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
1da177e4 4543{
120a5d0d
JB		 4544 volatile u32 temp;
4545
4546 temp = er32(CRCERRS);
4547 temp = er32(SYMERRS);
4548 temp = er32(MPC);
4549 temp = er32(SCC);
4550 temp = er32(ECOL);
4551 temp = er32(MCC);
4552 temp = er32(LATECOL);
4553 temp = er32(COLC);
4554 temp = er32(DC);
4555 temp = er32(SEC);
4556 temp = er32(RLEC);
4557 temp = er32(XONRXC);
4558 temp = er32(XONTXC);
4559 temp = er32(XOFFRXC);
4560 temp = er32(XOFFTXC);
4561 temp = er32(FCRUC);
4562
4563 temp = er32(PRC64);
4564 temp = er32(PRC127);
4565 temp = er32(PRC255);
4566 temp = er32(PRC511);
4567 temp = er32(PRC1023);
4568 temp = er32(PRC1522);
4569
4570 temp = er32(GPRC);
4571 temp = er32(BPRC);
4572 temp = er32(MPRC);
4573 temp = er32(GPTC);
4574 temp = er32(GORCL);
4575 temp = er32(GORCH);
4576 temp = er32(GOTCL);
4577 temp = er32(GOTCH);
4578 temp = er32(RNBC);
4579 temp = er32(RUC);
4580 temp = er32(RFC);
4581 temp = er32(ROC);
4582 temp = er32(RJC);
4583 temp = er32(TORL);
4584 temp = er32(TORH);
4585 temp = er32(TOTL);
4586 temp = er32(TOTH);
4587 temp = er32(TPR);
4588 temp = er32(TPT);
4589
4590 temp = er32(PTC64);
4591 temp = er32(PTC127);
4592 temp = er32(PTC255);
4593 temp = er32(PTC511);
4594 temp = er32(PTC1023);
4595 temp = er32(PTC1522);
4596
4597 temp = er32(MPTC);
4598 temp = er32(BPTC);
4599
4600 if (hw->mac_type < e1000_82543)
4601 return;
4602
4603 temp = er32(ALGNERRC);
4604 temp = er32(RXERRC);
4605 temp = er32(TNCRS);
4606 temp = er32(CEXTERR);
4607 temp = er32(TSCTC);
4608 temp = er32(TSCTFC);
4609
4610 if (hw->mac_type <= e1000_82544)
4611 return;
4612
4613 temp = er32(MGTPRC);
4614 temp = er32(MGTPDC);
4615 temp = er32(MGTPTC);
1da177e4
LT		 4616}
4617
120a5d0d
JB		 4618/**
4619 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4620 * @hw: Struct containing variables accessed by shared code
1da177e4
LT		 4621 *
4622 * Call this after e1000_init_hw. You may override the IFS defaults by setting
c3033b01 4623 * hw->ifs_params_forced to true. However, you must initialize hw->
1da177e4
LT		 4624 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4625 * before calling this function.
120a5d0d 4626 */
64798845 4627void e1000_reset_adaptive(struct e1000_hw *hw)
1da177e4 4628{
120a5d0d
JB		 4629 DEBUGFUNC("e1000_reset_adaptive");
4630
4631 if (hw->adaptive_ifs) {
4632 if (!hw->ifs_params_forced) {
4633 hw->current_ifs_val = 0;
4634 hw->ifs_min_val = IFS_MIN;
4635 hw->ifs_max_val = IFS_MAX;
4636 hw->ifs_step_size = IFS_STEP;
4637 hw->ifs_ratio = IFS_RATIO;
4638 }
4639 hw->in_ifs_mode = false;
4640 ew32(AIT, 0);
4641 } else {
4642 DEBUGOUT("Not in Adaptive IFS mode!\n");
4643 }
1da177e4
LT		 4644}
4645
120a5d0d
JB		 4646/**
4647 * e1000_update_adaptive - update adaptive IFS
4648 * @hw: Struct containing variables accessed by shared code
4649 * @tx_packets: Number of transmits since last callback
4650 * @total_collisions: Number of collisions since last callback
4651 *
1da177e4
LT		 4652 * Called during the callback/watchdog routine to update IFS value based on
4653 * the ratio of transmits to collisions.
120a5d0d 4654 */
64798845 4655void e1000_update_adaptive(struct e1000_hw *hw)
1da177e4 4656{
120a5d0d
JB		 4657 DEBUGFUNC("e1000_update_adaptive");
4658
4659 if (hw->adaptive_ifs) {
4660 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
4661 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4662 hw->in_ifs_mode = true;
4663 if (hw->current_ifs_val < hw->ifs_max_val) {
4664 if (hw->current_ifs_val == 0)
4665 hw->current_ifs_val =
4666 hw->ifs_min_val;
4667 else
4668 hw->current_ifs_val +=
4669 hw->ifs_step_size;
4670 ew32(AIT, hw->current_ifs_val);
4671 }
4672 }
4673 } else {
4674 if (hw->in_ifs_mode
4675 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4676 hw->current_ifs_val = 0;
4677 hw->in_ifs_mode = false;
4678 ew32(AIT, 0);
4679 }
4680 }
4681 } else {
4682 DEBUGOUT("Not in Adaptive IFS mode!\n");
4683 }
1da177e4
LT		 4684}
4685
120a5d0d
JB		 4686/**
4687 * e1000_tbi_adjust_stats
4688 * @hw: Struct containing variables accessed by shared code
4689 * @frame_len: The length of the frame in question
4690 * @mac_addr: The Ethernet destination address of the frame in question
1da177e4 4691 *
120a5d0d
JB		 4692 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4693 */
64798845
JP		 4694void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
4695 u32 frame_len, u8 *mac_addr)
1da177e4 4696{
120a5d0d
JB		 4697 u64 carry_bit;
4698
4699 /* First adjust the frame length. */
4700 frame_len--;
4701 /* We need to adjust the statistics counters, since the hardware
4702 * counters overcount this packet as a CRC error and undercount
4703 * the packet as a good packet
4704 */
4705 /* This packet should not be counted as a CRC error. */
4706 stats->crcerrs--;
4707 /* This packet does count as a Good Packet Received. */
4708 stats->gprc++;
4709
4710 /* Adjust the Good Octets received counters */
4711 carry_bit = 0x80000000 & stats->gorcl;
4712 stats->gorcl += frame_len;
4713 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4714 * Received Count) was one before the addition,
4715 * AND it is zero after, then we lost the carry out,
4716 * need to add one to Gorch (Good Octets Received Count High).
4717 * This could be simplified if all environments supported
4718 * 64-bit integers.
4719 */
4720 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
4721 stats->gorch++;
4722 /* Is this a broadcast or multicast? Check broadcast first,
4723 * since the test for a multicast frame will test positive on
4724 * a broadcast frame.
4725 */
4726 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
4727 /* Broadcast packet */
4728 stats->bprc++;
4729 else if (*mac_addr & 0x01)
4730 /* Multicast packet */
4731 stats->mprc++;
4732
4733 if (frame_len == hw->max_frame_size) {
4734 /* In this case, the hardware has overcounted the number of
4735 * oversize frames.
4736 */
4737 if (stats->roc > 0)
4738 stats->roc--;
4739 }
4740
4741 /* Adjust the bin counters when the extra byte put the frame in the
4742 * wrong bin. Remember that the frame_len was adjusted above.
4743 */
4744 if (frame_len == 64) {
4745 stats->prc64++;
4746 stats->prc127--;
4747 } else if (frame_len == 127) {
4748 stats->prc127++;
4749 stats->prc255--;
4750 } else if (frame_len == 255) {
4751 stats->prc255++;
4752 stats->prc511--;
4753 } else if (frame_len == 511) {
4754 stats->prc511++;
4755 stats->prc1023--;
4756 } else if (frame_len == 1023) {
4757 stats->prc1023++;
4758 stats->prc1522--;
4759 } else if (frame_len == 1522) {
4760 stats->prc1522++;
4761 }
1da177e4
LT		 4762}
4763
120a5d0d
JB		 4764/**
4765 * e1000_get_bus_info
4766 * @hw: Struct containing variables accessed by shared code
1da177e4 4767 *
120a5d0d
JB		 4768 * Gets the current PCI bus type, speed, and width of the hardware
4769 */
64798845 4770void e1000_get_bus_info(struct e1000_hw *hw)
1da177e4 4771{
120a5d0d
JB		 4772 u32 status;
4773
4774 switch (hw->mac_type) {
4775 case e1000_82542_rev2_0:
4776 case e1000_82542_rev2_1:
4777 hw->bus_type = e1000_bus_type_pci;
4778 hw->bus_speed = e1000_bus_speed_unknown;
4779 hw->bus_width = e1000_bus_width_unknown;
4780 break;
4781 default:
4782 status = er32(STATUS);
4783 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4784 e1000_bus_type_pcix : e1000_bus_type_pci;
4785
4786 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4787 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4788 e1000_bus_speed_66 : e1000_bus_speed_120;
4789 } else if (hw->bus_type == e1000_bus_type_pci) {
4790 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4791 e1000_bus_speed_66 : e1000_bus_speed_33;
4792 } else {
4793 switch (status & E1000_STATUS_PCIX_SPEED) {
4794 case E1000_STATUS_PCIX_SPEED_66:
4795 hw->bus_speed = e1000_bus_speed_66;
4796 break;
4797 case E1000_STATUS_PCIX_SPEED_100:
4798 hw->bus_speed = e1000_bus_speed_100;
4799 break;
4800 case E1000_STATUS_PCIX_SPEED_133:
4801 hw->bus_speed = e1000_bus_speed_133;
4802 break;
4803 default:
4804 hw->bus_speed = e1000_bus_speed_reserved;
4805 break;
4806 }
4807 }
4808 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4809 e1000_bus_width_64 : e1000_bus_width_32;
4810 break;
4811 }
1da177e4 4812}
1da177e4 4813
120a5d0d
JB		 4814/**
4815 * e1000_write_reg_io
4816 * @hw: Struct containing variables accessed by shared code
4817 * @offset: offset to write to
4818 * @value: value to write
4819 *
1da177e4
LT		 4820 * Writes a value to one of the devices registers using port I/O (as opposed to
4821 * memory mapped I/O). Only 82544 and newer devices support port I/O.
120a5d0d 4822 */
64798845 4823static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
1da177e4 4824{
120a5d0d
JB		 4825 unsigned long io_addr = hw->io_base;
4826 unsigned long io_data = hw->io_base + 4;
1da177e4 4827
120a5d0d
JB		 4828 e1000_io_write(hw, io_addr, offset);
4829 e1000_io_write(hw, io_data, value);
1da177e4
LT		 4830}
4831
120a5d0d
JB		 4832/**
4833 * e1000_get_cable_length - Estimates the cable length.
4834 * @hw: Struct containing variables accessed by shared code
4835 * @min_length: The estimated minimum length
4836 * @max_length: The estimated maximum length
1da177e4
LT		 4837 *
4838 * returns: - E1000_ERR_XXX
4839 * E1000_SUCCESS
4840 *
4841 * This function always returns a ranged length (minimum & maximum).
4842 * So for M88 phy's, this function interprets the one value returned from the
4843 * register to the minimum and maximum range.
4844 * For IGP phy's, the function calculates the range by the AGC registers.
120a5d0d 4845 */
64798845
JP		 4846static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4847 u16 *max_length)
1da177e4 4848{
120a5d0d
JB		 4849 s32 ret_val;
4850 u16 agc_value = 0;
4851 u16 i, phy_data;
4852 u16 cable_length;
4853
4854 DEBUGFUNC("e1000_get_cable_length");
4855
4856 *min_length = *max_length = 0;
4857
4858 /* Use old method for Phy older than IGP */
4859 if (hw->phy_type == e1000_phy_m88) {
4860
4861 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4862 &phy_data);
4863 if (ret_val)
4864 return ret_val;
4865 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4866 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4867
4868 /* Convert the enum value to ranged values */
4869 switch (cable_length) {
4870 case e1000_cable_length_50:
4871 *min_length = 0;
4872 *max_length = e1000_igp_cable_length_50;
4873 break;
4874 case e1000_cable_length_50_80:
4875 *min_length = e1000_igp_cable_length_50;
4876 *max_length = e1000_igp_cable_length_80;
4877 break;
4878 case e1000_cable_length_80_110:
4879 *min_length = e1000_igp_cable_length_80;
4880 *max_length = e1000_igp_cable_length_110;
4881 break;
4882 case e1000_cable_length_110_140:
4883 *min_length = e1000_igp_cable_length_110;
4884 *max_length = e1000_igp_cable_length_140;
4885 break;
4886 case e1000_cable_length_140:
4887 *min_length = e1000_igp_cable_length_140;
4888 *max_length = e1000_igp_cable_length_170;
4889 break;
4890 default:
4891 return -E1000_ERR_PHY;
4892 break;
4893 }
4894 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4895 u16 cur_agc_value;
4896 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4897 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4898 { IGP01E1000_PHY_AGC_A,
4899 IGP01E1000_PHY_AGC_B,
4900 IGP01E1000_PHY_AGC_C,
4901 IGP01E1000_PHY_AGC_D
4902 };
4903 /* Read the AGC registers for all channels */
4904 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4905
4906 ret_val =
4907 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4908 if (ret_val)
4909 return ret_val;
4910
4911 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4912
4913 /* Value bound check. */
4914 if ((cur_agc_value >=
4915 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
4916 || (cur_agc_value == 0))
4917 return -E1000_ERR_PHY;
4918
4919 agc_value += cur_agc_value;
4920
4921 /* Update minimal AGC value. */
4922 if (min_agc_value > cur_agc_value)
4923 min_agc_value = cur_agc_value;
4924 }
4925
4926 /* Remove the minimal AGC result for length < 50m */
4927 if (agc_value <
4928 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4929 agc_value -= min_agc_value;
4930
4931 /* Get the average length of the remaining 3 channels */
4932 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4933 } else {
4934 /* Get the average length of all the 4 channels. */
4935 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4936 }
4937
4938 /* Set the range of the calculated length. */
4939 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4940 IGP01E1000_AGC_RANGE) > 0) ?
4941 (e1000_igp_cable_length_table[agc_value] -
4942 IGP01E1000_AGC_RANGE) : 0;
4943 *max_length = e1000_igp_cable_length_table[agc_value] +
4944 IGP01E1000_AGC_RANGE;
4945 }
4946
4947 return E1000_SUCCESS;
1da177e4
LT		 4948}
4949
120a5d0d
JB		 4950/**
4951 * e1000_check_polarity - Check the cable polarity
4952 * @hw: Struct containing variables accessed by shared code
4953 * @polarity: output parameter : 0 - Polarity is not reversed
1da177e4
LT		 4954 * 1 - Polarity is reversed.
4955 *
4956 * returns: - E1000_ERR_XXX
4957 * E1000_SUCCESS
4958 *
025dfdaf 4959 * For phy's older than IGP, this function simply reads the polarity bit in the
1da177e4
LT		 4960 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4961 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4962 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4963 * IGP01E1000_PHY_PCS_INIT_REG.
120a5d0d 4964 */
64798845
JP		 4965static s32 e1000_check_polarity(struct e1000_hw *hw,
4966 e1000_rev_polarity *polarity)
1da177e4 4967{
120a5d0d
JB		 4968 s32 ret_val;
4969 u16 phy_data;
4970
4971 DEBUGFUNC("e1000_check_polarity");
4972
4973 if (hw->phy_type == e1000_phy_m88) {
4974 /* return the Polarity bit in the Status register. */
4975 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4976 &phy_data);
4977 if (ret_val)
4978 return ret_val;
4979 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
4980 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
4981 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4982
4983 } else if (hw->phy_type == e1000_phy_igp) {
4984 /* Read the Status register to check the speed */
4985 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4986 &phy_data);
4987 if (ret_val)
4988 return ret_val;
4989
4990 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4991 * find the polarity status */
4992 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4993 IGP01E1000_PSSR_SPEED_1000MBPS) {
4994
4995 /* Read the GIG initialization PCS register (0x00B4) */
4996 ret_val =
4997 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4998 &phy_data);
4999 if (ret_val)
5000 return ret_val;
5001
5002 /* Check the polarity bits */
5003 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5004 e1000_rev_polarity_reversed :
5005 e1000_rev_polarity_normal;
5006 } else {
5007 /* For 10 Mbps, read the polarity bit in the status register. (for
5008 * 100 Mbps this bit is always 0) */
5009 *polarity =
5010 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5011 e1000_rev_polarity_reversed :
5012 e1000_rev_polarity_normal;
5013 }
5014 }
5015 return E1000_SUCCESS;
1da177e4
LT		 5016}
5017
120a5d0d
JB		 5018/**
5019 * e1000_check_downshift - Check if Downshift occurred
5020 * @hw: Struct containing variables accessed by shared code
5021 * @downshift: output parameter : 0 - No Downshift occurred.
5022 * 1 - Downshift occurred.
1da177e4
LT		 5023 *
5024 * returns: - E1000_ERR_XXX
76c224bc 5025 * E1000_SUCCESS
1da177e4 5026 *
025dfdaf 5027 * For phy's older than IGP, this function reads the Downshift bit in the Phy
1da177e4
LT		 5028 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5029 * Link Health register. In IGP this bit is latched high, so the driver must
5030 * read it immediately after link is established.
120a5d0d 5031 */
64798845 5032static s32 e1000_check_downshift(struct e1000_hw *hw)
1da177e4 5033{
120a5d0d
JB		 5034 s32 ret_val;
5035 u16 phy_data;
5036
5037 DEBUGFUNC("e1000_check_downshift");
5038
5039 if (hw->phy_type == e1000_phy_igp) {
5040 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5041 &phy_data);
5042 if (ret_val)
5043 return ret_val;
5044
5045 hw->speed_downgraded =
5046 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5047 } else if (hw->phy_type == e1000_phy_m88) {
5048 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5049 &phy_data);
5050 if (ret_val)
5051 return ret_val;
5052
5053 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5054 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5055 }
2d7edb92 5056
120a5d0d 5057 return E1000_SUCCESS;
1da177e4
LT		 5058}
5059
120a5d0d
JB		 5060/**
5061 * e1000_config_dsp_after_link_change
5062 * @hw: Struct containing variables accessed by shared code
5063 * @link_up: was link up at the time this was called
1da177e4
LT		 5064 *
5065 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5066 * E1000_SUCCESS at any other case.
5067 *
120a5d0d
JB		 5068 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5069 * gigabit link is achieved to improve link quality.
5070 */
1da177e4 5071
64798845 5072static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
1da177e4 5073{
120a5d0d
JB		 5074 s32 ret_val;
5075 u16 phy_data, phy_saved_data, speed, duplex, i;
5076 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5077 { IGP01E1000_PHY_AGC_PARAM_A,
5078 IGP01E1000_PHY_AGC_PARAM_B,
5079 IGP01E1000_PHY_AGC_PARAM_C,
5080 IGP01E1000_PHY_AGC_PARAM_D
5081 };
5082 u16 min_length, max_length;
5083
5084 DEBUGFUNC("e1000_config_dsp_after_link_change");
5085
5086 if (hw->phy_type != e1000_phy_igp)
5087 return E1000_SUCCESS;
5088
5089 if (link_up) {
5090 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5091 if (ret_val) {
5092 DEBUGOUT("Error getting link speed and duplex\n");
5093 return ret_val;
5094 }
5095
5096 if (speed == SPEED_1000) {
5097
5098 ret_val =
5099 e1000_get_cable_length(hw, &min_length,
5100 &max_length);
5101 if (ret_val)
5102 return ret_val;
5103
5104 if ((hw->dsp_config_state == e1000_dsp_config_enabled)
5105 && min_length >= e1000_igp_cable_length_50) {
5106
5107 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5108 ret_val =
5109 e1000_read_phy_reg(hw,
5110 dsp_reg_array[i],
5111 &phy_data);
5112 if (ret_val)
5113 return ret_val;
5114
5115 phy_data &=
5116 ~IGP01E1000_PHY_EDAC_MU_INDEX;
5117
5118 ret_val =
5119 e1000_write_phy_reg(hw,
5120 dsp_reg_array
5121 [i], phy_data);
5122 if (ret_val)
5123 return ret_val;
5124 }
5125 hw->dsp_config_state =
5126 e1000_dsp_config_activated;
5127 }
5128
5129 if ((hw->ffe_config_state == e1000_ffe_config_enabled)
5130 && (min_length < e1000_igp_cable_length_50)) {
5131
5132 u16 ffe_idle_err_timeout =
5133 FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5134 u32 idle_errs = 0;
5135
5136 /* clear previous idle error counts */
5137 ret_val =
5138 e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5139 &phy_data);
5140 if (ret_val)
5141 return ret_val;
5142
5143 for (i = 0; i < ffe_idle_err_timeout; i++) {
5144 udelay(1000);
5145 ret_val =
5146 e1000_read_phy_reg(hw,
5147 PHY_1000T_STATUS,
5148 &phy_data);
5149 if (ret_val)
5150 return ret_val;
5151
5152 idle_errs +=
5153 (phy_data &
5154 SR_1000T_IDLE_ERROR_CNT);
5155 if (idle_errs >
5156 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
5157 {
5158 hw->ffe_config_state =
5159 e1000_ffe_config_active;
5160
5161 ret_val =
5162 e1000_write_phy_reg(hw,
5163 IGP01E1000_PHY_DSP_FFE,
5164 IGP01E1000_PHY_DSP_FFE_CM_CP);
5165 if (ret_val)
5166 return ret_val;
5167 break;
5168 }
5169
5170 if (idle_errs)
5171 ffe_idle_err_timeout =
5172 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5173 }
5174 }
5175 }
5176 } else {
5177 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5178 /* Save off the current value of register 0x2F5B to be restored at
5179 * the end of the routines. */
5180 ret_val =
5181 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5182
5183 if (ret_val)
5184 return ret_val;
5185
5186 /* Disable the PHY transmitter */
5187 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5188
5189 if (ret_val)
5190 return ret_val;
5191
5192 mdelay(20);
5193
5194 ret_val = e1000_write_phy_reg(hw, 0x0000,
5195 IGP01E1000_IEEE_FORCE_GIGA);
5196 if (ret_val)
5197 return ret_val;
5198 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5199 ret_val =
5200 e1000_read_phy_reg(hw, dsp_reg_array[i],
5201 &phy_data);
5202 if (ret_val)
5203 return ret_val;
5204
5205 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5206 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5207
5208 ret_val =
5209 e1000_write_phy_reg(hw, dsp_reg_array[i],
5210 phy_data);
5211 if (ret_val)
5212 return ret_val;
5213 }
5214
5215 ret_val = e1000_write_phy_reg(hw, 0x0000,
5216 IGP01E1000_IEEE_RESTART_AUTONEG);
5217 if (ret_val)
5218 return ret_val;
5219
5220 mdelay(20);
5221
5222 /* Now enable the transmitter */
5223 ret_val =
5224 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5225
5226 if (ret_val)
5227 return ret_val;
5228
5229 hw->dsp_config_state = e1000_dsp_config_enabled;
5230 }
5231
5232 if (hw->ffe_config_state == e1000_ffe_config_active) {
5233 /* Save off the current value of register 0x2F5B to be restored at
5234 * the end of the routines. */
5235 ret_val =
5236 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5237
5238 if (ret_val)
5239 return ret_val;
5240
5241 /* Disable the PHY transmitter */
5242 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5243
5244 if (ret_val)
5245 return ret_val;
5246
5247 mdelay(20);
5248
5249 ret_val = e1000_write_phy_reg(hw, 0x0000,
5250 IGP01E1000_IEEE_FORCE_GIGA);
5251 if (ret_val)
5252 return ret_val;
5253 ret_val =
5254 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5255 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5256 if (ret_val)
5257 return ret_val;
5258
5259 ret_val = e1000_write_phy_reg(hw, 0x0000,
5260 IGP01E1000_IEEE_RESTART_AUTONEG);
5261 if (ret_val)
5262 return ret_val;
5263
5264 mdelay(20);
5265
5266 /* Now enable the transmitter */
5267 ret_val =
5268 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5269
5270 if (ret_val)
5271 return ret_val;
5272
5273 hw->ffe_config_state = e1000_ffe_config_enabled;
5274 }
5275 }
5276 return E1000_SUCCESS;
1da177e4
LT		 5277}
5278
120a5d0d
JB		 5279/**
5280 * e1000_set_phy_mode - Set PHY to class A mode
5281 * @hw: Struct containing variables accessed by shared code
5282 *
1da177e4
LT		 5283 * Assumes the following operations will follow to enable the new class mode.
5284 * 1. Do a PHY soft reset
5285 * 2. Restart auto-negotiation or force link.
120a5d0d 5286 */
64798845 5287static s32 e1000_set_phy_mode(struct e1000_hw *hw)
1da177e4 5288{
120a5d0d
JB		 5289 s32 ret_val;
5290 u16 eeprom_data;
5291
5292 DEBUGFUNC("e1000_set_phy_mode");
5293
5294 if ((hw->mac_type == e1000_82545_rev_3) &&
5295 (hw->media_type == e1000_media_type_copper)) {
5296 ret_val =
5297 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5298 &eeprom_data);
5299 if (ret_val) {
5300 return ret_val;
5301 }
5302
5303 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5304 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5305 ret_val =
5306 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5307 0x000B);
5308 if (ret_val)
5309 return ret_val;
5310 ret_val =
5311 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5312 0x8104);
5313 if (ret_val)
5314 return ret_val;
5315
5316 hw->phy_reset_disable = false;
5317 }
5318 }
5319
5320 return E1000_SUCCESS;
1da177e4
LT		 5321}
5322
120a5d0d
JB		 5323/**
5324 * e1000_set_d3_lplu_state - set d3 link power state
5325 * @hw: Struct containing variables accessed by shared code
5326 * @active: true to enable lplu false to disable lplu.
1da177e4
LT		 5327 *
5328 * This function sets the lplu state according to the active flag. When
5329 * activating lplu this function also disables smart speed and vise versa.
120a5d0d 5330 * lplu will not be activated unless the device autonegotiation advertisement
1da177e4 5331 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
1da177e4
LT		 5332 *
5333 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5334 * E1000_SUCCESS at any other case.
120a5d0d 5335 */
64798845 5336static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1da177e4 5337{
120a5d0d
JB		 5338 s32 ret_val;
5339 u16 phy_data;
5340 DEBUGFUNC("e1000_set_d3_lplu_state");
5341
5342 if (hw->phy_type != e1000_phy_igp)
5343 return E1000_SUCCESS;
5344
5345 /* During driver activity LPLU should not be used or it will attain link
5346 * from the lowest speeds starting from 10Mbps. The capability is used for
5347 * Dx transitions and states */
5348 if (hw->mac_type == e1000_82541_rev_2
5349 || hw->mac_type == e1000_82547_rev_2) {
5350 ret_val =
5351 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5352 if (ret_val)
5353 return ret_val;
5354 }
5355
5356 if (!active) {
5357 if (hw->mac_type == e1000_82541_rev_2 ||
5358 hw->mac_type == e1000_82547_rev_2) {
5359 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5360 ret_val =
5361 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5362 phy_data);
5363 if (ret_val)
5364 return ret_val;
5365 }
5366
5367 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5368 * Dx states where the power conservation is most important. During
5369 * driver activity we should enable SmartSpeed, so performance is
5370 * maintained. */
5371 if (hw->smart_speed == e1000_smart_speed_on) {
5372 ret_val =
5373 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5374 &phy_data);
5375 if (ret_val)
5376 return ret_val;
5377
5378 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5379 ret_val =
5380 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5381 phy_data);
5382 if (ret_val)
5383 return ret_val;
5384 } else if (hw->smart_speed == e1000_smart_speed_off) {
5385 ret_val =
5386 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5387 &phy_data);
5388 if (ret_val)
5389 return ret_val;
5390
5391 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5392 ret_val =
5393 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5394 phy_data);
5395 if (ret_val)
5396 return ret_val;
5397 }
5398 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5399 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5400 || (hw->autoneg_advertised ==
5401 AUTONEG_ADVERTISE_10_100_ALL)) {
5402
5403 if (hw->mac_type == e1000_82541_rev_2 ||
5404 hw->mac_type == e1000_82547_rev_2) {
5405 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5406 ret_val =
5407 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5408 phy_data);
5409 if (ret_val)
5410 return ret_val;
5411 }
5412
5413 /* When LPLU is enabled we should disable SmartSpeed */
5414 ret_val =
5415 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5416 &phy_data);
5417 if (ret_val)
5418 return ret_val;
5419
5420 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5421 ret_val =
5422 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5423 phy_data);
5424 if (ret_val)
5425 return ret_val;
5426
5427 }
5428 return E1000_SUCCESS;
2d7edb92
MC		 5429}
5430
120a5d0d
JB		 5431/**
5432 * e1000_set_vco_speed
5433 * @hw: Struct containing variables accessed by shared code
2d7edb92 5434 *
120a5d0d
JB		 5435 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5436 */
1532ecea 5437static s32 e1000_set_vco_speed(struct e1000_hw *hw)
2d7edb92 5438{
120a5d0d
JB		 5439 s32 ret_val;
5440 u16 default_page = 0;
5441 u16 phy_data;
2d7edb92 5442
120a5d0d 5443 DEBUGFUNC("e1000_set_vco_speed");
2d7edb92 5444
120a5d0d
JB		 5445 switch (hw->mac_type) {
5446 case e1000_82545_rev_3:
5447 case e1000_82546_rev_3:
5448 break;
5449 default:
5450 return E1000_SUCCESS;
5451 }
1da177e4 5452
120a5d0d 5453 /* Set PHY register 30, page 5, bit 8 to 0 */
1da177e4 5454
120a5d0d
JB		 5455 ret_val =
5456 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5457 if (ret_val)
5458 return ret_val;
1da177e4 5459
120a5d0d
JB		 5460 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5461 if (ret_val)
5462 return ret_val;
1da177e4 5463
120a5d0d
JB		 5464 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5465 if (ret_val)
5466 return ret_val;
1da177e4 5467
120a5d0d
JB		 5468 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5469 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5470 if (ret_val)
5471 return ret_val;
1da177e4 5472
120a5d0d 5473 /* Set PHY register 30, page 4, bit 11 to 1 */
1da177e4 5474
120a5d0d
JB		 5475 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5476 if (ret_val)
5477 return ret_val;
1da177e4 5478
120a5d0d
JB		 5479 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5480 if (ret_val)
5481 return ret_val;
1da177e4 5482
120a5d0d
JB		 5483 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5484 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5485 if (ret_val)
5486 return ret_val;
1da177e4 5487
120a5d0d
JB		 5488 ret_val =
5489 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5490 if (ret_val)
5491 return ret_val;
1da177e4 5492
120a5d0d 5493 return E1000_SUCCESS;
1da177e4
LT		 5494}
5495
1da177e4 5496
120a5d0d
JB		 5497/**
5498 * e1000_enable_mng_pass_thru - check for bmc pass through
5499 * @hw: Struct containing variables accessed by shared code
2d7edb92 5500 *
120a5d0d 5501 * Verifies the hardware needs to allow ARPs to be processed by the host
c3033b01 5502 * returns: - true/false
120a5d0d 5503 */
64798845 5504u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
2d7edb92 5505{
120a5d0d
JB		 5506 u32 manc;
5507
5508 if (hw->asf_firmware_present) {
5509 manc = er32(MANC);
5510
5511 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5512 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5513 return false;
5514 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5515 return true;
5516 }
5517 return false;
2d7edb92
MC		 5518}
5519
64798845 5520static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
2d7edb92 5521{
120a5d0d
JB		 5522 s32 ret_val;
5523 u16 mii_status_reg;
5524 u16 i;
5525
5526 /* Polarity reversal workaround for forced 10F/10H links. */
5527
5528 /* Disable the transmitter on the PHY */
5529
5530 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5531 if (ret_val)
5532 return ret_val;
5533 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5534 if (ret_val)
5535 return ret_val;
5536
5537 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5538 if (ret_val)
5539 return ret_val;
5540
5541 /* This loop will early-out if the NO link condition has been met. */
5542 for (i = PHY_FORCE_TIME; i > 0; i--) {
5543 /* Read the MII Status Register and wait for Link Status bit
5544 * to be clear.
5545 */
5546
5547 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5548 if (ret_val)
5549 return ret_val;
5550
5551 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5552 if (ret_val)
5553 return ret_val;
5554
5555 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5556 break;
5557 mdelay(100);
5558 }
5559
5560 /* Recommended delay time after link has been lost */
5561 mdelay(1000);
5562
5563 /* Now we will re-enable th transmitter on the PHY */
5564
5565 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5566 if (ret_val)
5567 return ret_val;
5568 mdelay(50);
5569 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5570 if (ret_val)
5571 return ret_val;
5572 mdelay(50);
5573 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5574 if (ret_val)
5575 return ret_val;
5576 mdelay(50);
5577 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5578 if (ret_val)
5579 return ret_val;
5580
5581 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5582 if (ret_val)
5583 return ret_val;
5584
5585 /* This loop will early-out if the link condition has been met. */
5586 for (i = PHY_FORCE_TIME; i > 0; i--) {
5587 /* Read the MII Status Register and wait for Link Status bit
5588 * to be set.
5589 */
5590
5591 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5592 if (ret_val)
5593 return ret_val;
5594
5595 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5596 if (ret_val)
5597 return ret_val;
5598
5599 if (mii_status_reg & MII_SR_LINK_STATUS)
5600 break;
5601 mdelay(100);
5602 }
5603 return E1000_SUCCESS;
1da177e4
LT		 5604}
5605
120a5d0d
JB		 5606/**
5607 * e1000_get_auto_rd_done
5608 * @hw: Struct containing variables accessed by shared code
2d7edb92 5609 *
1532ecea 5610 * Check for EEPROM Auto Read bit done.
1532ecea
JB		 5611 * returns: - E1000_ERR_RESET if fail to reset MAC
5612 * E1000_SUCCESS at any other case.
120a5d0d 5613 */
1532ecea 5614static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
2d7edb92 5615{
120a5d0d
JB		 5616 DEBUGFUNC("e1000_get_auto_rd_done");
5617 msleep(5);
5618 return E1000_SUCCESS;
1532ecea 5619}
2d7edb92 5620
120a5d0d
JB		 5621/**
5622 * e1000_get_phy_cfg_done
5623 * @hw: Struct containing variables accessed by shared code
1532ecea 5624 *
120a5d0d 5625 * Checks if the PHY configuration is done
1532ecea
JB		 5626 * returns: - E1000_ERR_RESET if fail to reset MAC
5627 * E1000_SUCCESS at any other case.
120a5d0d 5628 */
1532ecea
JB		 5629static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5630{
120a5d0d
JB		 5631 DEBUGFUNC("e1000_get_phy_cfg_done");
5632 mdelay(10);
5633 return E1000_SUCCESS;
2d7edb92 5634}
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