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1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
05479938
JB		 5
6 This program is free software; you can redistribute it and/or modify it
0abb6eb1
AK		 7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
05479938 9
0abb6eb1 10 This program is distributed in the hope it will be useful, but WITHOUT
05479938
JB		 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
05479938 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
05479938 18
0abb6eb1
AK		 19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
05479938 21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
0abb6eb1 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
0a0863af 97 * IV. Receive
1da177e4
LT		 98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
7734f6e6
DA		 109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
1da177e4
LT		 116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
0a0863af 123 * scenario where all Rx resources have been indicated and none re-
1da177e4
LT		 124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
ac7c6669
OM		 142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
72001762
AM		 146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
1da177e4
LT		 148 */
149
fa05e1ad
JP		 150#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
151
1da177e4
LT		 152#include <linux/module.h>
153#include <linux/moduleparam.h>
154#include <linux/kernel.h>
155#include <linux/types.h>
d43c36dc 156#include <linux/sched.h>
1da177e4
LT		 157#include <linux/slab.h>
158#include <linux/delay.h>
159#include <linux/init.h>
160#include <linux/pci.h>
1e7f0bd8 161#include <linux/dma-mapping.h>
98468efd 162#include <linux/dmapool.h>
1da177e4
LT		 163#include <linux/netdevice.h>
164#include <linux/etherdevice.h>
165#include <linux/mii.h>
166#include <linux/if_vlan.h>
167#include <linux/skbuff.h>
168#include <linux/ethtool.h>
169#include <linux/string.h>
9ac32e1b 170#include <linux/firmware.h>
401da6ae 171#include <linux/rtnetlink.h>
1da177e4
LT		 172#include <asm/unaligned.h>
173
174
175#define DRV_NAME "e100"
4e1dc97d 176#define DRV_EXT "-NAPI"
b55de80e 177#define DRV_VERSION "3.5.24-k2"DRV_EXT
1da177e4 178#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
4e1dc97d 179#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
1da177e4
LT		 180
181#define E100_WATCHDOG_PERIOD (2 * HZ)
182#define E100_NAPI_WEIGHT 16
183
9ac32e1b
JSR		 184#define FIRMWARE_D101M "e100/d101m_ucode.bin"
185#define FIRMWARE_D101S "e100/d101s_ucode.bin"
186#define FIRMWARE_D102E "e100/d102e_ucode.bin"
187
1da177e4
LT		 188MODULE_DESCRIPTION(DRV_DESCRIPTION);
189MODULE_AUTHOR(DRV_COPYRIGHT);
190MODULE_LICENSE("GPL");
191MODULE_VERSION(DRV_VERSION);
9ac32e1b
JSR		 192MODULE_FIRMWARE(FIRMWARE_D101M);
193MODULE_FIRMWARE(FIRMWARE_D101S);
194MODULE_FIRMWARE(FIRMWARE_D102E);
1da177e4
LT		 195
196static int debug = 3;
8fb6f732 197static int eeprom_bad_csum_allow = 0;
27345bb6 198static int use_io = 0;
1da177e4 199module_param(debug, int, 0);
8fb6f732 200module_param(eeprom_bad_csum_allow, int, 0);
27345bb6 201module_param(use_io, int, 0);
1da177e4 202MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
8fb6f732 203MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
27345bb6 204MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
1da177e4
LT		 205
206#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
207 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
208 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
a3aa1884 209static DEFINE_PCI_DEVICE_TABLE(e100_id_table) = {
1da177e4
LT		 210 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
211 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
213 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
214 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
218 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
219 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
224 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
225 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
232 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
233 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
234 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
042e2fb7
MC		 240 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
241 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
242 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
b55de80e 245 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
1da177e4
LT		 246 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
247 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
248 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
249 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
250 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
042e2fb7 251 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
1da177e4
LT		 252 { 0, }
253};
254MODULE_DEVICE_TABLE(pci, e100_id_table);
255
256enum mac {
257 mac_82557_D100_A = 0,
258 mac_82557_D100_B = 1,
259 mac_82557_D100_C = 2,
260 mac_82558_D101_A4 = 4,
261 mac_82558_D101_B0 = 5,
262 mac_82559_D101M = 8,
263 mac_82559_D101S = 9,
264 mac_82550_D102 = 12,
265 mac_82550_D102_C = 13,
266 mac_82551_E = 14,
267 mac_82551_F = 15,
268 mac_82551_10 = 16,
269 mac_unknown = 0xFF,
270};
271
272enum phy {
273 phy_100a = 0x000003E0,
274 phy_100c = 0x035002A8,
275 phy_82555_tx = 0x015002A8,
276 phy_nsc_tx = 0x5C002000,
277 phy_82562_et = 0x033002A8,
278 phy_82562_em = 0x032002A8,
279 phy_82562_ek = 0x031002A8,
280 phy_82562_eh = 0x017002A8,
b55de80e 281 phy_82552_v = 0xd061004d,
1da177e4
LT		 282 phy_unknown = 0xFFFFFFFF,
283};
284
285/* CSR (Control/Status Registers) */
286struct csr {
287 struct {
288 u8 status;
289 u8 stat_ack;
290 u8 cmd_lo;
291 u8 cmd_hi;
292 u32 gen_ptr;
293 } scb;
294 u32 port;
295 u16 flash_ctrl;
296 u8 eeprom_ctrl_lo;
297 u8 eeprom_ctrl_hi;
298 u32 mdi_ctrl;
299 u32 rx_dma_count;
300};
301
302enum scb_status {
7734f6e6 303 rus_no_res = 0x08,
1da177e4
LT		 304 rus_ready = 0x10,
305 rus_mask = 0x3C,
306};
307
ca93ca42
JG		 308enum ru_state {
309 RU_SUSPENDED = 0,
310 RU_RUNNING = 1,
311 RU_UNINITIALIZED = -1,
312};
313
1da177e4
LT		 314enum scb_stat_ack {
315 stat_ack_not_ours = 0x00,
316 stat_ack_sw_gen = 0x04,
317 stat_ack_rnr = 0x10,
318 stat_ack_cu_idle = 0x20,
319 stat_ack_frame_rx = 0x40,
320 stat_ack_cu_cmd_done = 0x80,
321 stat_ack_not_present = 0xFF,
322 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
323 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
324};
325
326enum scb_cmd_hi {
327 irq_mask_none = 0x00,
328 irq_mask_all = 0x01,
329 irq_sw_gen = 0x02,
330};
331
332enum scb_cmd_lo {
333 cuc_nop = 0x00,
334 ruc_start = 0x01,
335 ruc_load_base = 0x06,
336 cuc_start = 0x10,
337 cuc_resume = 0x20,
338 cuc_dump_addr = 0x40,
339 cuc_dump_stats = 0x50,
340 cuc_load_base = 0x60,
341 cuc_dump_reset = 0x70,
342};
343
344enum cuc_dump {
345 cuc_dump_complete = 0x0000A005,
346 cuc_dump_reset_complete = 0x0000A007,
347};
05479938 348
1da177e4
LT		 349enum port {
350 software_reset = 0x0000,
351 selftest = 0x0001,
352 selective_reset = 0x0002,
353};
354
355enum eeprom_ctrl_lo {
356 eesk = 0x01,
357 eecs = 0x02,
358 eedi = 0x04,
359 eedo = 0x08,
360};
361
362enum mdi_ctrl {
363 mdi_write = 0x04000000,
364 mdi_read = 0x08000000,
365 mdi_ready = 0x10000000,
366};
367
368enum eeprom_op {
369 op_write = 0x05,
370 op_read = 0x06,
371 op_ewds = 0x10,
372 op_ewen = 0x13,
373};
374
375enum eeprom_offsets {
376 eeprom_cnfg_mdix = 0x03,
72001762 377 eeprom_phy_iface = 0x06,
1da177e4
LT		 378 eeprom_id = 0x0A,
379 eeprom_config_asf = 0x0D,
380 eeprom_smbus_addr = 0x90,
381};
382
383enum eeprom_cnfg_mdix {
384 eeprom_mdix_enabled = 0x0080,
385};
386
72001762
AM		 387enum eeprom_phy_iface {
388 NoSuchPhy = 0,
389 I82553AB,
390 I82553C,
391 I82503,
392 DP83840,
393 S80C240,
394 S80C24,
395 I82555,
396 DP83840A = 10,
397};
398
1da177e4
LT		 399enum eeprom_id {
400 eeprom_id_wol = 0x0020,
401};
402
403enum eeprom_config_asf {
404 eeprom_asf = 0x8000,
405 eeprom_gcl = 0x4000,
406};
407
408enum cb_status {
409 cb_complete = 0x8000,
410 cb_ok = 0x2000,
411};
412
413enum cb_command {
414 cb_nop = 0x0000,
415 cb_iaaddr = 0x0001,
416 cb_config = 0x0002,
417 cb_multi = 0x0003,
418 cb_tx = 0x0004,
419 cb_ucode = 0x0005,
420 cb_dump = 0x0006,
421 cb_tx_sf = 0x0008,
422 cb_cid = 0x1f00,
423 cb_i = 0x2000,
424 cb_s = 0x4000,
425 cb_el = 0x8000,
426};
427
428struct rfd {
aaf918ba
AV		 429 __le16 status;
430 __le16 command;
431 __le32 link;
432 __le32 rbd;
433 __le16 actual_size;
434 __le16 size;
1da177e4
LT		 435};
436
437struct rx {
438 struct rx *next, *prev;
439 struct sk_buff *skb;
440 dma_addr_t dma_addr;
441};
442
443#if defined(__BIG_ENDIAN_BITFIELD)
444#define X(a,b) b,a
445#else
446#define X(a,b) a,b
447#endif
448struct config {
449/*0*/ u8 X(byte_count:6, pad0:2);
450/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
451/*2*/ u8 adaptive_ifs;
452/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
453 term_write_cache_line:1), pad3:4);
454/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
455/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
456/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
457 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
458 rx_discard_overruns:1), rx_save_bad_frames:1);
459/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
460 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
461 tx_dynamic_tbd:1);
462/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
463/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
464 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
465/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
466 loopback:2);
467/*11*/ u8 X(linear_priority:3, pad11:5);
468/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
469/*13*/ u8 ip_addr_lo;
470/*14*/ u8 ip_addr_hi;
471/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
472 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
473 pad15_2:1), crs_or_cdt:1);
474/*16*/ u8 fc_delay_lo;
475/*17*/ u8 fc_delay_hi;
476/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
477 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
478/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
479 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
480 full_duplex_force:1), full_duplex_pin:1);
481/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
482/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
483/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
484 u8 pad_d102[9];
485};
486
487#define E100_MAX_MULTICAST_ADDRS 64
488struct multi {
aaf918ba 489 __le16 count;
1da177e4
LT		 490 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
491};
492
493/* Important: keep total struct u32-aligned */
494#define UCODE_SIZE 134
495struct cb {
aaf918ba
AV		 496 __le16 status;
497 __le16 command;
498 __le32 link;
1da177e4
LT		 499 union {
500 u8 iaaddr[ETH_ALEN];
aaf918ba 501 __le32 ucode[UCODE_SIZE];
1da177e4
LT		 502 struct config config;
503 struct multi multi;
504 struct {
505 u32 tbd_array;
506 u16 tcb_byte_count;
507 u8 threshold;
508 u8 tbd_count;
509 struct {
aaf918ba
AV		 510 __le32 buf_addr;
511 __le16 size;
1da177e4
LT		 512 u16 eol;
513 } tbd;
514 } tcb;
aaf918ba 515 __le32 dump_buffer_addr;
1da177e4
LT		 516 } u;
517 struct cb *next, *prev;
518 dma_addr_t dma_addr;
519 struct sk_buff *skb;
520};
521
522enum loopback {
523 lb_none = 0, lb_mac = 1, lb_phy = 3,
524};
525
526struct stats {
aaf918ba 527 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
1da177e4
LT		 528 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
529 tx_multiple_collisions, tx_total_collisions;
aaf918ba 530 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
1da177e4
LT		 531 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
532 rx_short_frame_errors;
aaf918ba
AV		 533 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
534 __le16 xmt_tco_frames, rcv_tco_frames;
535 __le32 complete;
1da177e4
LT		 536};
537
538struct mem {
539 struct {
540 u32 signature;
541 u32 result;
542 } selftest;
543 struct stats stats;
544 u8 dump_buf[596];
545};
546
547struct param_range {
548 u32 min;
549 u32 max;
550 u32 count;
551};
552
553struct params {
554 struct param_range rfds;
555 struct param_range cbs;
556};
557
558struct nic {
559 /* Begin: frequently used values: keep adjacent for cache effect */
560 u32 msg_enable ____cacheline_aligned;
561 struct net_device *netdev;
562 struct pci_dev *pdev;
72001762 563 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
1da177e4
LT		 564
565 struct rx *rxs ____cacheline_aligned;
566 struct rx *rx_to_use;
567 struct rx *rx_to_clean;
568 struct rfd blank_rfd;
ca93ca42 569 enum ru_state ru_running;
1da177e4
LT		 570
571 spinlock_t cb_lock ____cacheline_aligned;
572 spinlock_t cmd_lock;
573 struct csr __iomem *csr;
574 enum scb_cmd_lo cuc_cmd;
575 unsigned int cbs_avail;
bea3348e 576 struct napi_struct napi;
1da177e4
LT		 577 struct cb *cbs;
578 struct cb *cb_to_use;
579 struct cb *cb_to_send;
580 struct cb *cb_to_clean;
aaf918ba 581 __le16 tx_command;
1da177e4
LT		 582 /* End: frequently used values: keep adjacent for cache effect */
583
584 enum {
585 ich = (1 << 0),
586 promiscuous = (1 << 1),
587 multicast_all = (1 << 2),
588 wol_magic = (1 << 3),
589 ich_10h_workaround = (1 << 4),
590 } flags ____cacheline_aligned;
591
592 enum mac mac;
593 enum phy phy;
594 struct params params;
1da177e4
LT		 595 struct timer_list watchdog;
596 struct timer_list blink_timer;
597 struct mii_if_info mii;
2acdb1e0 598 struct work_struct tx_timeout_task;
1da177e4
LT		 599 enum loopback loopback;
600
601 struct mem *mem;
602 dma_addr_t dma_addr;
603
98468efd 604 struct pci_pool *cbs_pool;
1da177e4
LT		 605 dma_addr_t cbs_dma_addr;
606 u8 adaptive_ifs;
607 u8 tx_threshold;
608 u32 tx_frames;
609 u32 tx_collisions;
610 u32 tx_deferred;
611 u32 tx_single_collisions;
612 u32 tx_multiple_collisions;
613 u32 tx_fc_pause;
614 u32 tx_tco_frames;
615
616 u32 rx_fc_pause;
617 u32 rx_fc_unsupported;
618 u32 rx_tco_frames;
619 u32 rx_over_length_errors;
620
1da177e4
LT		 621 u16 leds;
622 u16 eeprom_wc;
aaf918ba 623 __le16 eeprom[256];
ac7c6669 624 spinlock_t mdio_lock;
7e15b0c9 625 const struct firmware *fw;
1da177e4
LT		 626};
627
628static inline void e100_write_flush(struct nic *nic)
629{
630 /* Flush previous PCI writes through intermediate bridges
631 * by doing a benign read */
27345bb6 632 (void)ioread8(&nic->csr->scb.status);
1da177e4
LT		 633}
634
858119e1 635static void e100_enable_irq(struct nic *nic)
1da177e4
LT		 636{
637 unsigned long flags;
638
639 spin_lock_irqsave(&nic->cmd_lock, flags);
27345bb6 640 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
1da177e4 641 e100_write_flush(nic);
ad8c48ad 642 spin_unlock_irqrestore(&nic->cmd_lock, flags);
1da177e4
LT		 643}
644
858119e1 645static void e100_disable_irq(struct nic *nic)
1da177e4
LT		 646{
647 unsigned long flags;
648
649 spin_lock_irqsave(&nic->cmd_lock, flags);
27345bb6 650 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
1da177e4 651 e100_write_flush(nic);
ad8c48ad 652 spin_unlock_irqrestore(&nic->cmd_lock, flags);
1da177e4
LT		 653}
654
655static void e100_hw_reset(struct nic *nic)
656{
657 /* Put CU and RU into idle with a selective reset to get
658 * device off of PCI bus */
27345bb6 659 iowrite32(selective_reset, &nic->csr->port);
1da177e4
LT		 660 e100_write_flush(nic); udelay(20);
661
662 /* Now fully reset device */
27345bb6 663 iowrite32(software_reset, &nic->csr->port);
1da177e4
LT		 664 e100_write_flush(nic); udelay(20);
665
666 /* Mask off our interrupt line - it's unmasked after reset */
667 e100_disable_irq(nic);
668}
669
670static int e100_self_test(struct nic *nic)
671{
672 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
673
674 /* Passing the self-test is a pretty good indication
675 * that the device can DMA to/from host memory */
676
677 nic->mem->selftest.signature = 0;
678 nic->mem->selftest.result = 0xFFFFFFFF;
679
27345bb6 680 iowrite32(selftest | dma_addr, &nic->csr->port);
1da177e4
LT		 681 e100_write_flush(nic);
682 /* Wait 10 msec for self-test to complete */
683 msleep(10);
684
685 /* Interrupts are enabled after self-test */
686 e100_disable_irq(nic);
687
688 /* Check results of self-test */
f26251eb 689 if (nic->mem->selftest.result != 0) {
fa05e1ad
JP		 690 netif_err(nic, hw, nic->netdev,
691 "Self-test failed: result=0x%08X\n",
692 nic->mem->selftest.result);
1da177e4
LT		 693 return -ETIMEDOUT;
694 }
f26251eb 695 if (nic->mem->selftest.signature == 0) {
fa05e1ad 696 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n");
1da177e4
LT		 697 return -ETIMEDOUT;
698 }
699
700 return 0;
701}
702
aaf918ba 703static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
1da177e4
LT		 704{
705 u32 cmd_addr_data[3];
706 u8 ctrl;
707 int i, j;
708
709 /* Three cmds: write/erase enable, write data, write/erase disable */
710 cmd_addr_data[0] = op_ewen << (addr_len - 2);
711 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
aaf918ba 712 le16_to_cpu(data);
1da177e4
LT		 713 cmd_addr_data[2] = op_ewds << (addr_len - 2);
714
715 /* Bit-bang cmds to write word to eeprom */
f26251eb 716 for (j = 0; j < 3; j++) {
1da177e4
LT		 717
718 /* Chip select */
27345bb6 719 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 720 e100_write_flush(nic); udelay(4);
721
f26251eb 722 for (i = 31; i >= 0; i--) {
1da177e4
LT		 723 ctrl = (cmd_addr_data[j] & (1 << i)) ?
724 eecs | eedi : eecs;
27345bb6 725 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 726 e100_write_flush(nic); udelay(4);
727
27345bb6 728 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 729 e100_write_flush(nic); udelay(4);
730 }
731 /* Wait 10 msec for cmd to complete */
732 msleep(10);
733
734 /* Chip deselect */
27345bb6 735 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 736 e100_write_flush(nic); udelay(4);
737 }
738};
739
740/* General technique stolen from the eepro100 driver - very clever */
aaf918ba 741static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
1da177e4
LT		 742{
743 u32 cmd_addr_data;
744 u16 data = 0;
745 u8 ctrl;
746 int i;
747
748 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
749
750 /* Chip select */
27345bb6 751 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 752 e100_write_flush(nic); udelay(4);
753
754 /* Bit-bang to read word from eeprom */
f26251eb 755 for (i = 31; i >= 0; i--) {
1da177e4 756 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
27345bb6 757 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
1da177e4 758 e100_write_flush(nic); udelay(4);
05479938 759
27345bb6 760 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4 761 e100_write_flush(nic); udelay(4);
05479938 762
1da177e4
LT		 763 /* Eeprom drives a dummy zero to EEDO after receiving
764 * complete address. Use this to adjust addr_len. */
27345bb6 765 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
f26251eb 766 if (!(ctrl & eedo) && i > 16) {
1da177e4
LT		 767 *addr_len -= (i - 16);
768 i = 17;
769 }
05479938 770
1da177e4
LT		 771 data = (data << 1) | (ctrl & eedo ? 1 : 0);
772 }
773
774 /* Chip deselect */
27345bb6 775 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 776 e100_write_flush(nic); udelay(4);
777
aaf918ba 778 return cpu_to_le16(data);
1da177e4
LT		 779};
780
781/* Load entire EEPROM image into driver cache and validate checksum */
782static int e100_eeprom_load(struct nic *nic)
783{
784 u16 addr, addr_len = 8, checksum = 0;
785
786 /* Try reading with an 8-bit addr len to discover actual addr len */
787 e100_eeprom_read(nic, &addr_len, 0);
788 nic->eeprom_wc = 1 << addr_len;
789
f26251eb 790 for (addr = 0; addr < nic->eeprom_wc; addr++) {
1da177e4 791 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
f26251eb 792 if (addr < nic->eeprom_wc - 1)
aaf918ba 793 checksum += le16_to_cpu(nic->eeprom[addr]);
1da177e4
LT		 794 }
795
796 /* The checksum, stored in the last word, is calculated such that
797 * the sum of words should be 0xBABA */
aaf918ba 798 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
fa05e1ad 799 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n");
8fb6f732
DM		 800 if (!eeprom_bad_csum_allow)
801 return -EAGAIN;
1da177e4
LT		 802 }
803
804 return 0;
805}
806
807/* Save (portion of) driver EEPROM cache to device and update checksum */
808static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
809{
810 u16 addr, addr_len = 8, checksum = 0;
811
812 /* Try reading with an 8-bit addr len to discover actual addr len */
813 e100_eeprom_read(nic, &addr_len, 0);
814 nic->eeprom_wc = 1 << addr_len;
815
f26251eb 816 if (start + count >= nic->eeprom_wc)
1da177e4
LT		 817 return -EINVAL;
818
f26251eb 819 for (addr = start; addr < start + count; addr++)
1da177e4
LT		 820 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
821
822 /* The checksum, stored in the last word, is calculated such that
823 * the sum of words should be 0xBABA */
f26251eb 824 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
aaf918ba
AV		 825 checksum += le16_to_cpu(nic->eeprom[addr]);
826 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
1da177e4
LT		 827 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
828 nic->eeprom[nic->eeprom_wc - 1]);
829
830 return 0;
831}
832
962082b6 833#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
e6280f26 834#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
858119e1 835static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
1da177e4
LT		 836{
837 unsigned long flags;
838 unsigned int i;
839 int err = 0;
840
841 spin_lock_irqsave(&nic->cmd_lock, flags);
842
843 /* Previous command is accepted when SCB clears */
f26251eb
BA		 844 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
845 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
1da177e4
LT		 846 break;
847 cpu_relax();
f26251eb 848 if (unlikely(i > E100_WAIT_SCB_FAST))
1da177e4
LT		 849 udelay(5);
850 }
f26251eb 851 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
1da177e4
LT		 852 err = -EAGAIN;
853 goto err_unlock;
854 }
855
f26251eb 856 if (unlikely(cmd != cuc_resume))
27345bb6
JB		 857 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
858 iowrite8(cmd, &nic->csr->scb.cmd_lo);
1da177e4
LT		 859
860err_unlock:
861 spin_unlock_irqrestore(&nic->cmd_lock, flags);
862
863 return err;
864}
865
858119e1 866static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
1da177e4
LT		 867 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
868{
869 struct cb *cb;
870 unsigned long flags;
871 int err = 0;
872
873 spin_lock_irqsave(&nic->cb_lock, flags);
874
f26251eb 875 if (unlikely(!nic->cbs_avail)) {
1da177e4
LT		 876 err = -ENOMEM;
877 goto err_unlock;
878 }
879
880 cb = nic->cb_to_use;
881 nic->cb_to_use = cb->next;
882 nic->cbs_avail--;
883 cb->skb = skb;
884
f26251eb 885 if (unlikely(!nic->cbs_avail))
1da177e4
LT		 886 err = -ENOSPC;
887
888 cb_prepare(nic, cb, skb);
889
890 /* Order is important otherwise we'll be in a race with h/w:
891 * set S-bit in current first, then clear S-bit in previous. */
892 cb->command |= cpu_to_le16(cb_s);
893 wmb();
894 cb->prev->command &= cpu_to_le16(~cb_s);
895
f26251eb
BA		 896 while (nic->cb_to_send != nic->cb_to_use) {
897 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
1da177e4
LT		 898 nic->cb_to_send->dma_addr))) {
899 /* Ok, here's where things get sticky. It's
900 * possible that we can't schedule the command
901 * because the controller is too busy, so
902 * let's just queue the command and try again
903 * when another command is scheduled. */
f26251eb 904 if (err == -ENOSPC) {
962082b6
MC		 905 //request a reset
906 schedule_work(&nic->tx_timeout_task);
907 }
1da177e4
LT		 908 break;
909 } else {
910 nic->cuc_cmd = cuc_resume;
911 nic->cb_to_send = nic->cb_to_send->next;
912 }
913 }
914
915err_unlock:
916 spin_unlock_irqrestore(&nic->cb_lock, flags);
917
918 return err;
919}
920
72001762
AM		 921static int mdio_read(struct net_device *netdev, int addr, int reg)
922{
923 struct nic *nic = netdev_priv(netdev);
924 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
925}
926
927static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
928{
929 struct nic *nic = netdev_priv(netdev);
930
931 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
932}
933
934/* the standard mdio_ctrl() function for usual MII-compliant hardware */
935static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
1da177e4
LT		 936{
937 u32 data_out = 0;
938 unsigned int i;
ac7c6669 939 unsigned long flags;
1da177e4 940
ac7c6669
OM		 941
942 /*
943 * Stratus87247: we shouldn't be writing the MDI control
944 * register until the Ready bit shows True. Also, since
945 * manipulation of the MDI control registers is a multi-step
946 * procedure it should be done under lock.
947 */
948 spin_lock_irqsave(&nic->mdio_lock, flags);
949 for (i = 100; i; --i) {
27345bb6 950 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
ac7c6669
OM		 951 break;
952 udelay(20);
953 }
954 if (unlikely(!i)) {
fa05e1ad 955 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n");
ac7c6669
OM		 956 spin_unlock_irqrestore(&nic->mdio_lock, flags);
957 return 0; /* No way to indicate timeout error */
958 }
27345bb6 959 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
1da177e4 960
ac7c6669 961 for (i = 0; i < 100; i++) {
1da177e4 962 udelay(20);
27345bb6 963 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
1da177e4
LT		 964 break;
965 }
ac7c6669 966 spin_unlock_irqrestore(&nic->mdio_lock, flags);
fa05e1ad
JP		 967 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
968 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
969 dir == mdi_read ? "READ" : "WRITE",
970 addr, reg, data, data_out);
1da177e4
LT		 971 return (u16)data_out;
972}
973
72001762
AM		 974/* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
975static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
976 u32 addr,
977 u32 dir,
978 u32 reg,
979 u16 data)
980{
981 if ((reg == MII_BMCR) && (dir == mdi_write)) {
982 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
983 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
984 MII_ADVERTISE);
985
986 /*
987 * Workaround Si issue where sometimes the part will not
988 * autoneg to 100Mbps even when advertised.
989 */
990 if (advert & ADVERTISE_100FULL)
991 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
992 else if (advert & ADVERTISE_100HALF)
993 data |= BMCR_SPEED100;
994 }
995 }
996 return mdio_ctrl_hw(nic, addr, dir, reg, data);
1da177e4
LT		 997}
998
72001762
AM		 999/* Fully software-emulated mdio_ctrl() function for cards without
1000 * MII-compliant PHYs.
1001 * For now, this is mainly geared towards 80c24 support; in case of further
1002 * requirements for other types (i82503, ...?) either extend this mechanism
1003 * or split it, whichever is cleaner.
1004 */
1005static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1006 u32 addr,
1007 u32 dir,
1008 u32 reg,
1009 u16 data)
1010{
1011 /* might need to allocate a netdev_priv'ed register array eventually
1012 * to be able to record state changes, but for now
1013 * some fully hardcoded register handling ought to be ok I guess. */
1014
1015 if (dir == mdi_read) {
1016 switch (reg) {
1017 case MII_BMCR:
1018 /* Auto-negotiation, right? */
1019 return BMCR_ANENABLE |
1020 BMCR_FULLDPLX;
1021 case MII_BMSR:
1022 return BMSR_LSTATUS /* for mii_link_ok() */ |
1023 BMSR_ANEGCAPABLE |
1024 BMSR_10FULL;
1025 case MII_ADVERTISE:
1026 /* 80c24 is a "combo card" PHY, right? */
1027 return ADVERTISE_10HALF |
1028 ADVERTISE_10FULL;
1029 default:
fa05e1ad
JP		 1030 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1031 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1032 dir == mdi_read ? "READ" : "WRITE",
1033 addr, reg, data);
72001762
AM		 1034 return 0xFFFF;
1035 }
1036 } else {
1037 switch (reg) {
1038 default:
fa05e1ad
JP		 1039 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1040 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1041 dir == mdi_read ? "READ" : "WRITE",
1042 addr, reg, data);
72001762
AM		 1043 return 0xFFFF;
1044 }
b55de80e 1045 }
72001762
AM		 1046}
1047static inline int e100_phy_supports_mii(struct nic *nic)
1048{
1049 /* for now, just check it by comparing whether we
1050 are using MII software emulation.
1051 */
1052 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1da177e4
LT		 1053}
1054
1055static void e100_get_defaults(struct nic *nic)
1056{
2afecc04
JB		 1057 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1058 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1da177e4 1059
1da177e4 1060 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
44c10138 1061 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
f26251eb 1062 if (nic->mac == mac_unknown)
1da177e4
LT		 1063 nic->mac = mac_82557_D100_A;
1064
1065 nic->params.rfds = rfds;
1066 nic->params.cbs = cbs;
1067
1068 /* Quadwords to DMA into FIFO before starting frame transmit */
1069 nic->tx_threshold = 0xE0;
1070
0a0863af 1071 /* no interrupt for every tx completion, delay = 256us if not 557 */
962082b6
MC		 1072 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1073 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1da177e4
LT		 1074
1075 /* Template for a freshly allocated RFD */
7734f6e6 1076 nic->blank_rfd.command = 0;
1172899a 1077 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1da177e4
LT		 1078 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1079
1080 /* MII setup */
1081 nic->mii.phy_id_mask = 0x1F;
1082 nic->mii.reg_num_mask = 0x1F;
1083 nic->mii.dev = nic->netdev;
1084 nic->mii.mdio_read = mdio_read;
1085 nic->mii.mdio_write = mdio_write;
1086}
1087
1088static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1089{
1090 struct config *config = &cb->u.config;
1091 u8 *c = (u8 *)config;
1092
1093 cb->command = cpu_to_le16(cb_config);
1094
1095 memset(config, 0, sizeof(struct config));
1096
1097 config->byte_count = 0x16; /* bytes in this struct */
1098 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1099 config->direct_rx_dma = 0x1; /* reserved */
1100 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1101 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1102 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1103 config->tx_underrun_retry = 0x3; /* # of underrun retries */
72001762
AM		 1104 if (e100_phy_supports_mii(nic))
1105 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1da177e4
LT		 1106 config->pad10 = 0x6;
1107 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1108 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1109 config->ifs = 0x6; /* x16 = inter frame spacing */
1110 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1111 config->pad15_1 = 0x1;
1112 config->pad15_2 = 0x1;
1113 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1114 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1115 config->tx_padding = 0x1; /* 1=pad short frames */
1116 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1117 config->pad18 = 0x1;
1118 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1119 config->pad20_1 = 0x1F;
1120 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1121 config->pad21_1 = 0x5;
1122
1123 config->adaptive_ifs = nic->adaptive_ifs;
1124 config->loopback = nic->loopback;
1125
f26251eb 1126 if (nic->mii.force_media && nic->mii.full_duplex)
1da177e4
LT		 1127 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1128
f26251eb 1129 if (nic->flags & promiscuous || nic->loopback) {
1da177e4
LT		 1130 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1131 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1132 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1133 }
1134
f26251eb 1135 if (nic->flags & multicast_all)
1da177e4
LT		 1136 config->multicast_all = 0x1; /* 1=accept, 0=no */
1137
6bdacb1a 1138 /* disable WoL when up */
f26251eb 1139 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1da177e4
LT		 1140 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1141
f26251eb 1142 if (nic->mac >= mac_82558_D101_A4) {
1da177e4
LT		 1143 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1144 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1145 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1146 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
44e4925e 1147 if (nic->mac >= mac_82559_D101M) {
1da177e4 1148 config->tno_intr = 0x1; /* TCO stats enable */
44e4925e
DG		 1149 /* Enable TCO in extended config */
1150 if (nic->mac >= mac_82551_10) {
1151 config->byte_count = 0x20; /* extended bytes */
1152 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1153 }
1154 } else {
1da177e4 1155 config->standard_stat_counter = 0x0;
44e4925e 1156 }
1da177e4
LT		 1157 }
1158
fa05e1ad
JP		 1159 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1160 "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1161 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1162 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1163 "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1164 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1165 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1166 "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1167 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1da177e4
LT		 1168}
1169
2afecc04
JB		 1170/*************************************************************************
1171* CPUSaver parameters
1172*
1173* All CPUSaver parameters are 16-bit literals that are part of a
1174* "move immediate value" instruction. By changing the value of
1175* the literal in the instruction before the code is loaded, the
1176* driver can change the algorithm.
1177*
0779bf2d 1178* INTDELAY - This loads the dead-man timer with its initial value.
05479938 1179* When this timer expires the interrupt is asserted, and the
2afecc04
JB		 1180* timer is reset each time a new packet is received. (see
1181* BUNDLEMAX below to set the limit on number of chained packets)
1182* The current default is 0x600 or 1536. Experiments show that
1183* the value should probably stay within the 0x200 - 0x1000.
1184*
05479938 1185* BUNDLEMAX -
2afecc04
JB		 1186* This sets the maximum number of frames that will be bundled. In
1187* some situations, such as the TCP windowing algorithm, it may be
1188* better to limit the growth of the bundle size than let it go as
1189* high as it can, because that could cause too much added latency.
1190* The default is six, because this is the number of packets in the
1191* default TCP window size. A value of 1 would make CPUSaver indicate
1192* an interrupt for every frame received. If you do not want to put
1193* a limit on the bundle size, set this value to xFFFF.
1194*
05479938 1195* BUNDLESMALL -
2afecc04
JB		 1196* This contains a bit-mask describing the minimum size frame that
1197* will be bundled. The default masks the lower 7 bits, which means
1198* that any frame less than 128 bytes in length will not be bundled,
1199* but will instead immediately generate an interrupt. This does
1200* not affect the current bundle in any way. Any frame that is 128
1201* bytes or large will be bundled normally. This feature is meant
1202* to provide immediate indication of ACK frames in a TCP environment.
1203* Customers were seeing poor performance when a machine with CPUSaver
1204* enabled was sending but not receiving. The delay introduced when
1205* the ACKs were received was enough to reduce total throughput, because
1206* the sender would sit idle until the ACK was finally seen.
1207*
1208* The current default is 0xFF80, which masks out the lower 7 bits.
1209* This means that any frame which is x7F (127) bytes or smaller
05479938 1210* will cause an immediate interrupt. Because this value must be a
2afecc04
JB		 1211* bit mask, there are only a few valid values that can be used. To
1212* turn this feature off, the driver can write the value xFFFF to the
1213* lower word of this instruction (in the same way that the other
1214* parameters are used). Likewise, a value of 0xF800 (2047) would
1215* cause an interrupt to be generated for every frame, because all
1216* standard Ethernet frames are <= 2047 bytes in length.
1217*************************************************************************/
1218
05479938 1219/* if you wish to disable the ucode functionality, while maintaining the
2afecc04
JB		 1220 * workarounds it provides, set the following defines to:
1221 * BUNDLESMALL 0
1222 * BUNDLEMAX 1
1223 * INTDELAY 1
1224 */
1225#define BUNDLESMALL 1
1226#define BUNDLEMAX (u16)6
1227#define INTDELAY (u16)1536 /* 0x600 */
1228
9ac32e1b
JSR		 1229/* Initialize firmware */
1230static const struct firmware *e100_request_firmware(struct nic *nic)
1231{
1232 const char *fw_name;
7e15b0c9 1233 const struct firmware *fw = nic->fw;
9ac32e1b 1234 u8 timer, bundle, min_size;
7e15b0c9 1235 int err = 0;
9ac32e1b 1236
2afecc04
JB		 1237 /* do not load u-code for ICH devices */
1238 if (nic->flags & ich)
9ac32e1b 1239 return NULL;
2afecc04 1240
44c10138 1241 /* Search for ucode match against h/w revision */
9ac32e1b
JSR		 1242 if (nic->mac == mac_82559_D101M)
1243 fw_name = FIRMWARE_D101M;
1244 else if (nic->mac == mac_82559_D101S)
1245 fw_name = FIRMWARE_D101S;
1246 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1247 fw_name = FIRMWARE_D102E;
1248 else /* No ucode on other devices */
1249 return NULL;
1250
7e15b0c9
DG		 1251 /* If the firmware has not previously been loaded, request a pointer
1252 * to it. If it was previously loaded, we are reinitializing the
1253 * adapter, possibly in a resume from hibernate, in which case
1254 * request_firmware() cannot be used.
1255 */
1256 if (!fw)
1257 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1258
9ac32e1b 1259 if (err) {
fa05e1ad
JP		 1260 netif_err(nic, probe, nic->netdev,
1261 "Failed to load firmware \"%s\": %d\n",
1262 fw_name, err);
9ac32e1b
JSR		 1263 return ERR_PTR(err);
1264 }
7e15b0c9 1265
9ac32e1b
JSR		 1266 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1267 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1268 if (fw->size != UCODE_SIZE * 4 + 3) {
fa05e1ad
JP		 1269 netif_err(nic, probe, nic->netdev,
1270 "Firmware \"%s\" has wrong size %zu\n",
1271 fw_name, fw->size);
9ac32e1b
JSR		 1272 release_firmware(fw);
1273 return ERR_PTR(-EINVAL);
2afecc04
JB		 1274 }
1275
9ac32e1b
JSR		 1276 /* Read timer, bundle and min_size from end of firmware blob */
1277 timer = fw->data[UCODE_SIZE * 4];
1278 bundle = fw->data[UCODE_SIZE * 4 + 1];
1279 min_size = fw->data[UCODE_SIZE * 4 + 2];
1280
1281 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1282 min_size >= UCODE_SIZE) {
fa05e1ad
JP		 1283 netif_err(nic, probe, nic->netdev,
1284 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1285 fw_name, timer, bundle, min_size);
9ac32e1b
JSR		 1286 release_firmware(fw);
1287 return ERR_PTR(-EINVAL);
1288 }
7e15b0c9
DG		 1289
1290 /* OK, firmware is validated and ready to use. Save a pointer
1291 * to it in the nic */
1292 nic->fw = fw;
9ac32e1b 1293 return fw;
24180333
JB		 1294}
1295
9ac32e1b
JSR		 1296static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1297 struct sk_buff *skb)
24180333 1298{
9ac32e1b
JSR		 1299 const struct firmware *fw = (void *)skb;
1300 u8 timer, bundle, min_size;
1301
1302 /* It's not a real skb; we just abused the fact that e100_exec_cb
1303 will pass it through to here... */
1304 cb->skb = NULL;
1305
1306 /* firmware is stored as little endian already */
1307 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1308
1309 /* Read timer, bundle and min_size from end of firmware blob */
1310 timer = fw->data[UCODE_SIZE * 4];
1311 bundle = fw->data[UCODE_SIZE * 4 + 1];
1312 min_size = fw->data[UCODE_SIZE * 4 + 2];
1313
1314 /* Insert user-tunable settings in cb->u.ucode */
1315 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1316 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1317 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1318 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1319 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1320 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1321
1322 cb->command = cpu_to_le16(cb_ucode | cb_el);
1323}
1324
1325static inline int e100_load_ucode_wait(struct nic *nic)
1326{
1327 const struct firmware *fw;
24180333
JB		 1328 int err = 0, counter = 50;
1329 struct cb *cb = nic->cb_to_clean;
1330
9ac32e1b
JSR		 1331 fw = e100_request_firmware(nic);
1332 /* If it's NULL, then no ucode is required */
1333 if (!fw || IS_ERR(fw))
1334 return PTR_ERR(fw);
1335
1336 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
fa05e1ad
JP		 1337 netif_err(nic, probe, nic->netdev,
1338 "ucode cmd failed with error %d\n", err);
05479938 1339
24180333
JB		 1340 /* must restart cuc */
1341 nic->cuc_cmd = cuc_start;
1342
1343 /* wait for completion */
1344 e100_write_flush(nic);
1345 udelay(10);
1346
1347 /* wait for possibly (ouch) 500ms */
1348 while (!(cb->status & cpu_to_le16(cb_complete))) {
1349 msleep(10);
1350 if (!--counter) break;
1351 }
05479938 1352
3a4fa0a2 1353 /* ack any interrupts, something could have been set */
27345bb6 1354 iowrite8(~0, &nic->csr->scb.stat_ack);
24180333
JB		 1355
1356 /* if the command failed, or is not OK, notify and return */
1357 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
fa05e1ad 1358 netif_err(nic, probe, nic->netdev, "ucode load failed\n");
24180333
JB		 1359 err = -EPERM;
1360 }
05479938 1361
24180333 1362 return err;
1da177e4
LT		 1363}
1364
1365static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1366 struct sk_buff *skb)
1367{
1368 cb->command = cpu_to_le16(cb_iaaddr);
1369 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1370}
1371
1372static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1373{
1374 cb->command = cpu_to_le16(cb_dump);
1375 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1376 offsetof(struct mem, dump_buf));
1377}
1378
72001762
AM		 1379static int e100_phy_check_without_mii(struct nic *nic)
1380{
1381 u8 phy_type;
1382 int without_mii;
1383
1384 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1385
1386 switch (phy_type) {
1387 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1388 case I82503: /* Non-MII PHY; UNTESTED! */
1389 case S80C24: /* Non-MII PHY; tested and working */
1390 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1391 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1392 * doesn't have a programming interface of any sort. The
1393 * media is sensed automatically based on how the link partner
1394 * is configured. This is, in essence, manual configuration.
1395 */
fa05e1ad
JP		 1396 netif_info(nic, probe, nic->netdev,
1397 "found MII-less i82503 or 80c24 or other PHY\n");
72001762
AM		 1398
1399 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1400 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1401
1402 /* these might be needed for certain MII-less cards...
1403 * nic->flags |= ich;
1404 * nic->flags |= ich_10h_workaround; */
1405
1406 without_mii = 1;
1407 break;
1408 default:
1409 without_mii = 0;
1410 break;
1411 }
1412 return without_mii;
1413}
1414
1da177e4
LT		 1415#define NCONFIG_AUTO_SWITCH 0x0080
1416#define MII_NSC_CONG MII_RESV1
1417#define NSC_CONG_ENABLE 0x0100
1418#define NSC_CONG_TXREADY 0x0400
1419#define ADVERTISE_FC_SUPPORTED 0x0400
1420static int e100_phy_init(struct nic *nic)
1421{
1422 struct net_device *netdev = nic->netdev;
1423 u32 addr;
1424 u16 bmcr, stat, id_lo, id_hi, cong;
1425
1426 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
f26251eb 1427 for (addr = 0; addr < 32; addr++) {
1da177e4
LT		 1428 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1429 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1430 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1431 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
f26251eb 1432 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1da177e4
LT		 1433 break;
1434 }
72001762
AM		 1435 if (addr == 32) {
1436 /* uhoh, no PHY detected: check whether we seem to be some
1437 * weird, rare variant which is *known* to not have any MII.
1438 * But do this AFTER MII checking only, since this does
1439 * lookup of EEPROM values which may easily be unreliable. */
1440 if (e100_phy_check_without_mii(nic))
1441 return 0; /* simply return and hope for the best */
1442 else {
1443 /* for unknown cases log a fatal error */
fa05e1ad
JP		 1444 netif_err(nic, hw, nic->netdev,
1445 "Failed to locate any known PHY, aborting\n");
72001762
AM		 1446 return -EAGAIN;
1447 }
1448 } else
fa05e1ad
JP		 1449 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1450 "phy_addr = %d\n", nic->mii.phy_id);
1da177e4 1451
1da177e4
LT		 1452 /* Get phy ID */
1453 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1454 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1455 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
fa05e1ad
JP		 1456 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1457 "phy ID = 0x%08X\n", nic->phy);
1da177e4 1458
8fbd962e
BA		 1459 /* Select the phy and isolate the rest */
1460 for (addr = 0; addr < 32; addr++) {
1461 if (addr != nic->mii.phy_id) {
1462 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1463 } else if (nic->phy != phy_82552_v) {
1464 bmcr = mdio_read(netdev, addr, MII_BMCR);
1465 mdio_write(netdev, addr, MII_BMCR,
1466 bmcr & ~BMCR_ISOLATE);
1467 }
1468 }
1469 /*
1470 * Workaround for 82552:
1471 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1472 * other phy_id's) using bmcr value from addr discovery loop above.
1473 */
1474 if (nic->phy == phy_82552_v)
1475 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1476 bmcr & ~BMCR_ISOLATE);
1477
1da177e4
LT		 1478 /* Handle National tx phys */
1479#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
f26251eb 1480 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1da177e4
LT		 1481 /* Disable congestion control */
1482 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1483 cong |= NSC_CONG_TXREADY;
1484 cong &= ~NSC_CONG_ENABLE;
1485 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1486 }
1487
b55de80e
BA		 1488 if (nic->phy == phy_82552_v) {
1489 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1490
72001762
AM		 1491 /* assign special tweaked mdio_ctrl() function */
1492 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1493
b55de80e
BA		 1494 /* Workaround Si not advertising flow-control during autoneg */
1495 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1496 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1497
1498 /* Reset for the above changes to take effect */
1499 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1500 bmcr |= BMCR_RESET;
1501 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1502 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
60ffa478
JK		 1503 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1504 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1505 /* enable/disable MDI/MDI-X auto-switching. */
1506 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1507 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
64895145 1508 }
1da177e4
LT		 1509
1510 return 0;
1511}
1512
1513static int e100_hw_init(struct nic *nic)
1514{
1515 int err;
1516
1517 e100_hw_reset(nic);
1518
fa05e1ad 1519 netif_err(nic, hw, nic->netdev, "e100_hw_init\n");
f26251eb 1520 if (!in_interrupt() && (err = e100_self_test(nic)))
1da177e4
LT		 1521 return err;
1522
f26251eb 1523 if ((err = e100_phy_init(nic)))
1da177e4 1524 return err;
f26251eb 1525 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1da177e4 1526 return err;
f26251eb 1527 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1da177e4 1528 return err;
9ac32e1b 1529 if ((err = e100_load_ucode_wait(nic)))
1da177e4 1530 return err;
f26251eb 1531 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1da177e4 1532 return err;
f26251eb 1533 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1da177e4 1534 return err;
f26251eb 1535 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1da177e4
LT		 1536 nic->dma_addr + offsetof(struct mem, stats))))
1537 return err;
f26251eb 1538 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1da177e4
LT		 1539 return err;
1540
1541 e100_disable_irq(nic);
1542
1543 return 0;
1544}
1545
1546static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1547{
1548 struct net_device *netdev = nic->netdev;
22bedad3 1549 struct netdev_hw_addr *ha;
4cd24eaf 1550 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1da177e4
LT		 1551
1552 cb->command = cpu_to_le16(cb_multi);
1553 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
48e2f183 1554 i = 0;
22bedad3 1555 netdev_for_each_mc_addr(ha, netdev) {
48e2f183
JP		 1556 if (i == count)
1557 break;
22bedad3 1558 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr,
1da177e4 1559 ETH_ALEN);
48e2f183 1560 }
1da177e4
LT		 1561}
1562
1563static void e100_set_multicast_list(struct net_device *netdev)
1564{
1565 struct nic *nic = netdev_priv(netdev);
1566
fa05e1ad
JP		 1567 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1568 "mc_count=%d, flags=0x%04X\n",
1569 netdev_mc_count(netdev), netdev->flags);
1da177e4 1570
f26251eb 1571 if (netdev->flags & IFF_PROMISC)
1da177e4
LT		 1572 nic->flags |= promiscuous;
1573 else
1574 nic->flags &= ~promiscuous;
1575
f26251eb 1576 if (netdev->flags & IFF_ALLMULTI ||
4cd24eaf 1577 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1da177e4
LT		 1578 nic->flags |= multicast_all;
1579 else
1580 nic->flags &= ~multicast_all;
1581
1582 e100_exec_cb(nic, NULL, e100_configure);
1583 e100_exec_cb(nic, NULL, e100_multi);
1584}
1585
1586static void e100_update_stats(struct nic *nic)
1587{
09f75cd7
JG		 1588 struct net_device *dev = nic->netdev;
1589 struct net_device_stats *ns = &dev->stats;
1da177e4 1590 struct stats *s = &nic->mem->stats;
aaf918ba
AV		 1591 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1592 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1da177e4
LT		 1593 &s->complete;
1594
1595 /* Device's stats reporting may take several microseconds to
0a0863af 1596 * complete, so we're always waiting for results of the
1da177e4
LT		 1597 * previous command. */
1598
f26251eb 1599 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1da177e4
LT		 1600 *complete = 0;
1601 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1602 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1603 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1604 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1605 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1606 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1607 ns->collisions += nic->tx_collisions;
1608 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1609 le32_to_cpu(s->tx_lost_crs);
1da177e4
LT		 1610 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1611 nic->rx_over_length_errors;
1612 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1613 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1614 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1615 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
ecf7130b 1616 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1da177e4
LT		 1617 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1618 le32_to_cpu(s->rx_alignment_errors) +
1619 le32_to_cpu(s->rx_short_frame_errors) +
1620 le32_to_cpu(s->rx_cdt_errors);
1621 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1622 nic->tx_single_collisions +=
1623 le32_to_cpu(s->tx_single_collisions);
1624 nic->tx_multiple_collisions +=
1625 le32_to_cpu(s->tx_multiple_collisions);
f26251eb 1626 if (nic->mac >= mac_82558_D101_A4) {
1da177e4
LT		 1627 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1628 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1629 nic->rx_fc_unsupported +=
1630 le32_to_cpu(s->fc_rcv_unsupported);
f26251eb 1631 if (nic->mac >= mac_82559_D101M) {
1da177e4
LT		 1632 nic->tx_tco_frames +=
1633 le16_to_cpu(s->xmt_tco_frames);
1634 nic->rx_tco_frames +=
1635 le16_to_cpu(s->rcv_tco_frames);
1636 }
1637 }
1638 }
1639
05479938 1640
f26251eb 1641 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
fa05e1ad
JP		 1642 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1643 "exec cuc_dump_reset failed\n");
1da177e4
LT		 1644}
1645
1646static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1647{
1648 /* Adjust inter-frame-spacing (IFS) between two transmits if
1649 * we're getting collisions on a half-duplex connection. */
1650
f26251eb 1651 if (duplex == DUPLEX_HALF) {
1da177e4
LT		 1652 u32 prev = nic->adaptive_ifs;
1653 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1654
f26251eb 1655 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1da177e4 1656 (nic->tx_frames > min_frames)) {
f26251eb 1657 if (nic->adaptive_ifs < 60)
1da177e4
LT		 1658 nic->adaptive_ifs += 5;
1659 } else if (nic->tx_frames < min_frames) {
f26251eb 1660 if (nic->adaptive_ifs >= 5)
1da177e4
LT		 1661 nic->adaptive_ifs -= 5;
1662 }
f26251eb 1663 if (nic->adaptive_ifs != prev)
1da177e4
LT		 1664 e100_exec_cb(nic, NULL, e100_configure);
1665 }
1666}
1667
1668static void e100_watchdog(unsigned long data)
1669{
1670 struct nic *nic = (struct nic *)data;
1671 struct ethtool_cmd cmd;
1672
fa05e1ad
JP		 1673 netif_printk(nic, timer, KERN_DEBUG, nic->netdev,
1674 "right now = %ld\n", jiffies);
1da177e4
LT		 1675
1676 /* mii library handles link maintenance tasks */
1677
1678 mii_ethtool_gset(&nic->mii, &cmd);
1679
f26251eb 1680 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
fa05e1ad
JP		 1681 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n",
1682 cmd.speed == SPEED_100 ? 100 : 10,
1683 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
f26251eb 1684 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
fa05e1ad 1685 netdev_info(nic->netdev, "NIC Link is Down\n");
1da177e4
LT		 1686 }
1687
1688 mii_check_link(&nic->mii);
1689
1690 /* Software generated interrupt to recover from (rare) Rx
05479938
JB		 1691 * allocation failure.
1692 * Unfortunately have to use a spinlock to not re-enable interrupts
1693 * accidentally, due to hardware that shares a register between the
1694 * interrupt mask bit and the SW Interrupt generation bit */
1da177e4 1695 spin_lock_irq(&nic->cmd_lock);
27345bb6 1696 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1da177e4 1697 e100_write_flush(nic);
ad8c48ad 1698 spin_unlock_irq(&nic->cmd_lock);
1da177e4
LT		 1699
1700 e100_update_stats(nic);
1701 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1702
f26251eb 1703 if (nic->mac <= mac_82557_D100_C)
1da177e4
LT		 1704 /* Issue a multicast command to workaround a 557 lock up */
1705 e100_set_multicast_list(nic->netdev);
1706
f26251eb 1707 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1da177e4
LT		 1708 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1709 nic->flags |= ich_10h_workaround;
1710 else
1711 nic->flags &= ~ich_10h_workaround;
1712
34c6417b
SH		 1713 mod_timer(&nic->watchdog,
1714 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1da177e4
LT		 1715}
1716
858119e1 1717static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1da177e4
LT		 1718 struct sk_buff *skb)
1719{
1720 cb->command = nic->tx_command;
962082b6 1721 /* interrupt every 16 packets regardless of delay */
f26251eb 1722 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
996ec353 1723 cb->command |= cpu_to_le16(cb_i);
1da177e4
LT		 1724 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1725 cb->u.tcb.tcb_byte_count = 0;
1726 cb->u.tcb.threshold = nic->tx_threshold;
1727 cb->u.tcb.tbd_count = 1;
1728 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1729 skb->data, skb->len, PCI_DMA_TODEVICE));
611494dc 1730 /* check for mapping failure? */
1da177e4
LT		 1731 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1732}
1733
3b29a56d
SH		 1734static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1735 struct net_device *netdev)
1da177e4
LT		 1736{
1737 struct nic *nic = netdev_priv(netdev);
1738 int err;
1739
f26251eb 1740 if (nic->flags & ich_10h_workaround) {
1da177e4
LT		 1741 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1742 Issue a NOP command followed by a 1us delay before
1743 issuing the Tx command. */
f26251eb 1744 if (e100_exec_cmd(nic, cuc_nop, 0))
fa05e1ad
JP		 1745 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1746 "exec cuc_nop failed\n");
1da177e4
LT		 1747 udelay(1);
1748 }
1749
1750 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1751
f26251eb 1752 switch (err) {
1da177e4
LT		 1753 case -ENOSPC:
1754 /* We queued the skb, but now we're out of space. */
fa05e1ad
JP		 1755 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1756 "No space for CB\n");
1da177e4
LT		 1757 netif_stop_queue(netdev);
1758 break;
1759 case -ENOMEM:
1760 /* This is a hard error - log it. */
fa05e1ad
JP		 1761 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1762 "Out of Tx resources, returning skb\n");
1da177e4 1763 netif_stop_queue(netdev);
5b548140 1764 return NETDEV_TX_BUSY;
1da177e4
LT		 1765 }
1766
6ed10654 1767 return NETDEV_TX_OK;
1da177e4
LT		 1768}
1769
858119e1 1770static int e100_tx_clean(struct nic *nic)
1da177e4 1771{
09f75cd7 1772 struct net_device *dev = nic->netdev;
1da177e4
LT		 1773 struct cb *cb;
1774 int tx_cleaned = 0;
1775
1776 spin_lock(&nic->cb_lock);
1777
1da177e4 1778 /* Clean CBs marked complete */
f26251eb 1779 for (cb = nic->cb_to_clean;
1da177e4
LT		 1780 cb->status & cpu_to_le16(cb_complete);
1781 cb = nic->cb_to_clean = cb->next) {
fa05e1ad
JP		 1782 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev,
1783 "cb[%d]->status = 0x%04X\n",
1784 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1785 cb->status);
dc45010e 1786
f26251eb 1787 if (likely(cb->skb != NULL)) {
09f75cd7
JG		 1788 dev->stats.tx_packets++;
1789 dev->stats.tx_bytes += cb->skb->len;
1da177e4
LT		 1790
1791 pci_unmap_single(nic->pdev,
1792 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1793 le16_to_cpu(cb->u.tcb.tbd.size),
1794 PCI_DMA_TODEVICE);
1795 dev_kfree_skb_any(cb->skb);
1796 cb->skb = NULL;
1797 tx_cleaned = 1;
1798 }
1799 cb->status = 0;
1800 nic->cbs_avail++;
1801 }
1802
1803 spin_unlock(&nic->cb_lock);
1804
1805 /* Recover from running out of Tx resources in xmit_frame */
f26251eb 1806 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1da177e4
LT		 1807 netif_wake_queue(nic->netdev);
1808
1809 return tx_cleaned;
1810}
1811
1812static void e100_clean_cbs(struct nic *nic)
1813{
f26251eb
BA		 1814 if (nic->cbs) {
1815 while (nic->cbs_avail != nic->params.cbs.count) {
1da177e4 1816 struct cb *cb = nic->cb_to_clean;
f26251eb 1817 if (cb->skb) {
1da177e4
LT		 1818 pci_unmap_single(nic->pdev,
1819 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1820 le16_to_cpu(cb->u.tcb.tbd.size),
1821 PCI_DMA_TODEVICE);
1822 dev_kfree_skb(cb->skb);
1823 }
1824 nic->cb_to_clean = nic->cb_to_clean->next;
1825 nic->cbs_avail++;
1826 }
98468efd 1827 pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1da177e4
LT		 1828 nic->cbs = NULL;
1829 nic->cbs_avail = 0;
1830 }
1831 nic->cuc_cmd = cuc_start;
1832 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1833 nic->cbs;
1834}
1835
1836static int e100_alloc_cbs(struct nic *nic)
1837{
1838 struct cb *cb;
1839 unsigned int i, count = nic->params.cbs.count;
1840
1841 nic->cuc_cmd = cuc_start;
1842 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1843 nic->cbs_avail = 0;
1844
98468efd
RO		 1845 nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
1846 &nic->cbs_dma_addr);
f26251eb 1847 if (!nic->cbs)
1da177e4 1848 return -ENOMEM;
70abc8cb 1849 memset(nic->cbs, 0, count * sizeof(struct cb));
1da177e4 1850
f26251eb 1851 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1da177e4
LT		 1852 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1853 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1854
1855 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1856 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1857 ((i+1) % count) * sizeof(struct cb));
1da177e4
LT		 1858 }
1859
1860 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1861 nic->cbs_avail = count;
1862
1863 return 0;
1864}
1865
ca93ca42 1866static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1da177e4 1867{
f26251eb
BA		 1868 if (!nic->rxs) return;
1869 if (RU_SUSPENDED != nic->ru_running) return;
ca93ca42
JG		 1870
1871 /* handle init time starts */
f26251eb 1872 if (!rx) rx = nic->rxs;
ca93ca42
JG		 1873
1874 /* (Re)start RU if suspended or idle and RFA is non-NULL */
f26251eb 1875 if (rx->skb) {
ca93ca42
JG		 1876 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1877 nic->ru_running = RU_RUNNING;
1878 }
1da177e4
LT		 1879}
1880
1881#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
858119e1 1882static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1da177e4 1883{
89d71a66 1884 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1da177e4
LT		 1885 return -ENOMEM;
1886
89d71a66 1887 /* Init, and map the RFD. */
27d7ff46 1888 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1da177e4
LT		 1889 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1890 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1891
8d8bb39b 1892 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1f53367d 1893 dev_kfree_skb_any(rx->skb);
097688ef 1894 rx->skb = NULL;
1f53367d
MC		 1895 rx->dma_addr = 0;
1896 return -ENOMEM;
1897 }
1898
1da177e4 1899 /* Link the RFD to end of RFA by linking previous RFD to
7734f6e6
DA		 1900 * this one. We are safe to touch the previous RFD because
1901 * it is protected by the before last buffer's el bit being set */
aaf918ba 1902 if (rx->prev->skb) {
1da177e4 1903 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
6caf52a4 1904 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1923815d 1905 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
773c9c1f 1906 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 1907 }
1908
1909 return 0;
1910}
1911
858119e1 1912static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1da177e4
LT		 1913 unsigned int *work_done, unsigned int work_to_do)
1914{
09f75cd7 1915 struct net_device *dev = nic->netdev;
1da177e4
LT		 1916 struct sk_buff *skb = rx->skb;
1917 struct rfd *rfd = (struct rfd *)skb->data;
1918 u16 rfd_status, actual_size;
1919
f26251eb 1920 if (unlikely(work_done && *work_done >= work_to_do))
1da177e4
LT		 1921 return -EAGAIN;
1922
1923 /* Need to sync before taking a peek at cb_complete bit */
1924 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
773c9c1f 1925 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 1926 rfd_status = le16_to_cpu(rfd->status);
1927
fa05e1ad
JP		 1928 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev,
1929 "status=0x%04X\n", rfd_status);
1da177e4
LT		 1930
1931 /* If data isn't ready, nothing to indicate */
7734f6e6
DA		 1932 if (unlikely(!(rfd_status & cb_complete))) {
1933 /* If the next buffer has the el bit, but we think the receiver
1934 * is still running, check to see if it really stopped while
1935 * we had interrupts off.
1936 * This allows for a fast restart without re-enabling
1937 * interrupts */
1938 if ((le16_to_cpu(rfd->command) & cb_el) &&
1939 (RU_RUNNING == nic->ru_running))
1940
17393dd6 1941 if (ioread8(&nic->csr->scb.status) & rus_no_res)
7734f6e6 1942 nic->ru_running = RU_SUSPENDED;
303d67c2
KH		 1943 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1944 sizeof(struct rfd),
6ff9c2e7 1945 PCI_DMA_FROMDEVICE);
1f53367d 1946 return -ENODATA;
7734f6e6 1947 }
1da177e4
LT		 1948
1949 /* Get actual data size */
1950 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
f26251eb 1951 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1da177e4
LT		 1952 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1953
1954 /* Get data */
1955 pci_unmap_single(nic->pdev, rx->dma_addr,
773c9c1f 1956 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1da177e4 1957
7734f6e6
DA		 1958 /* If this buffer has the el bit, but we think the receiver
1959 * is still running, check to see if it really stopped while
1960 * we had interrupts off.
1961 * This allows for a fast restart without re-enabling interrupts.
1962 * This can happen when the RU sees the size change but also sees
1963 * the el bit set. */
1964 if ((le16_to_cpu(rfd->command) & cb_el) &&
1965 (RU_RUNNING == nic->ru_running)) {
1966
17393dd6 1967 if (ioread8(&nic->csr->scb.status) & rus_no_res)
ca93ca42 1968 nic->ru_running = RU_SUSPENDED;
7734f6e6 1969 }
ca93ca42 1970
1da177e4
LT		 1971 /* Pull off the RFD and put the actual data (minus eth hdr) */
1972 skb_reserve(skb, sizeof(struct rfd));
1973 skb_put(skb, actual_size);
1974 skb->protocol = eth_type_trans(skb, nic->netdev);
1975
f26251eb 1976 if (unlikely(!(rfd_status & cb_ok))) {
1da177e4 1977 /* Don't indicate if hardware indicates errors */
1da177e4 1978 dev_kfree_skb_any(skb);
f26251eb 1979 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1da177e4
LT		 1980 /* Don't indicate oversized frames */
1981 nic->rx_over_length_errors++;
1da177e4
LT		 1982 dev_kfree_skb_any(skb);
1983 } else {
09f75cd7
JG		 1984 dev->stats.rx_packets++;
1985 dev->stats.rx_bytes += actual_size;
1da177e4 1986 netif_receive_skb(skb);
f26251eb 1987 if (work_done)
1da177e4
LT		 1988 (*work_done)++;
1989 }
1990
1991 rx->skb = NULL;
1992
1993 return 0;
1994}
1995
858119e1 1996static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1da177e4
LT		 1997 unsigned int work_to_do)
1998{
1999 struct rx *rx;
7734f6e6
DA		 2000 int restart_required = 0, err = 0;
2001 struct rx *old_before_last_rx, *new_before_last_rx;
2002 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1da177e4
LT		 2003
2004 /* Indicate newly arrived packets */
f26251eb 2005 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
7734f6e6
DA		 2006 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
2007 /* Hit quota or no more to clean */
2008 if (-EAGAIN == err || -ENODATA == err)
ca93ca42 2009 break;
1da177e4
LT		 2010 }
2011
7734f6e6
DA		 2012
2013 /* On EAGAIN, hit quota so have more work to do, restart once
2014 * cleanup is complete.
2015 * Else, are we already rnr? then pay attention!!! this ensures that
2016 * the state machine progression never allows a start with a
2017 * partially cleaned list, avoiding a race between hardware
2018 * and rx_to_clean when in NAPI mode */
2019 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2020 restart_required = 1;
2021
2022 old_before_last_rx = nic->rx_to_use->prev->prev;
2023 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
ca93ca42 2024
1da177e4 2025 /* Alloc new skbs to refill list */
f26251eb
BA		 2026 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2027 if (unlikely(e100_rx_alloc_skb(nic, rx)))
1da177e4
LT		 2028 break; /* Better luck next time (see watchdog) */
2029 }
ca93ca42 2030
7734f6e6
DA		 2031 new_before_last_rx = nic->rx_to_use->prev->prev;
2032 if (new_before_last_rx != old_before_last_rx) {
2033 /* Set the el-bit on the buffer that is before the last buffer.
2034 * This lets us update the next pointer on the last buffer
2035 * without worrying about hardware touching it.
2036 * We set the size to 0 to prevent hardware from touching this
2037 * buffer.
2038 * When the hardware hits the before last buffer with el-bit
2039 * and size of 0, it will RNR interrupt, the RUS will go into
2040 * the No Resources state. It will not complete nor write to
2041 * this buffer. */
2042 new_before_last_rfd =
2043 (struct rfd *)new_before_last_rx->skb->data;
2044 new_before_last_rfd->size = 0;
2045 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2046 pci_dma_sync_single_for_device(nic->pdev,
2047 new_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2048 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2049
2050 /* Now that we have a new stopping point, we can clear the old
2051 * stopping point. We must sync twice to get the proper
2052 * ordering on the hardware side of things. */
2053 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2054 pci_dma_sync_single_for_device(nic->pdev,
2055 old_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2056 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2057 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2058 pci_dma_sync_single_for_device(nic->pdev,
2059 old_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2060 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2061 }
2062
f26251eb 2063 if (restart_required) {
ca93ca42 2064 // ack the rnr?
915e91d7 2065 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
7734f6e6 2066 e100_start_receiver(nic, nic->rx_to_clean);
f26251eb 2067 if (work_done)
ca93ca42
JG		 2068 (*work_done)++;
2069 }
1da177e4
LT		 2070}
2071
2072static void e100_rx_clean_list(struct nic *nic)
2073{
2074 struct rx *rx;
2075 unsigned int i, count = nic->params.rfds.count;
2076
ca93ca42
JG		 2077 nic->ru_running = RU_UNINITIALIZED;
2078
f26251eb
BA		 2079 if (nic->rxs) {
2080 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2081 if (rx->skb) {
1da177e4 2082 pci_unmap_single(nic->pdev, rx->dma_addr,
773c9c1f 2083 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 2084 dev_kfree_skb(rx->skb);
2085 }
2086 }
2087 kfree(nic->rxs);
2088 nic->rxs = NULL;
2089 }
2090
2091 nic->rx_to_use = nic->rx_to_clean = NULL;
1da177e4
LT		 2092}
2093
2094static int e100_rx_alloc_list(struct nic *nic)
2095{
2096 struct rx *rx;
2097 unsigned int i, count = nic->params.rfds.count;
7734f6e6 2098 struct rfd *before_last;
1da177e4
LT		 2099
2100 nic->rx_to_use = nic->rx_to_clean = NULL;
ca93ca42 2101 nic->ru_running = RU_UNINITIALIZED;
1da177e4 2102
f26251eb 2103 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
1da177e4 2104 return -ENOMEM;
1da177e4 2105
f26251eb 2106 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
1da177e4
LT		 2107 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2108 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
f26251eb 2109 if (e100_rx_alloc_skb(nic, rx)) {
1da177e4
LT		 2110 e100_rx_clean_list(nic);
2111 return -ENOMEM;
2112 }
2113 }
7734f6e6
DA		 2114 /* Set the el-bit on the buffer that is before the last buffer.
2115 * This lets us update the next pointer on the last buffer without
2116 * worrying about hardware touching it.
2117 * We set the size to 0 to prevent hardware from touching this buffer.
2118 * When the hardware hits the before last buffer with el-bit and size
2119 * of 0, it will RNR interrupt, the RU will go into the No Resources
2120 * state. It will not complete nor write to this buffer. */
2121 rx = nic->rxs->prev->prev;
2122 before_last = (struct rfd *)rx->skb->data;
2123 before_last->command |= cpu_to_le16(cb_el);
2124 before_last->size = 0;
2125 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
773c9c1f 2126 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 2127
2128 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
ca93ca42 2129 nic->ru_running = RU_SUSPENDED;
1da177e4
LT		 2130
2131 return 0;
2132}
2133
7d12e780 2134static irqreturn_t e100_intr(int irq, void *dev_id)
1da177e4
LT		 2135{
2136 struct net_device *netdev = dev_id;
2137 struct nic *nic = netdev_priv(netdev);
27345bb6 2138 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
1da177e4 2139
fa05e1ad
JP		 2140 netif_printk(nic, intr, KERN_DEBUG, nic->netdev,
2141 "stat_ack = 0x%02X\n", stat_ack);
1da177e4 2142
f26251eb 2143 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
1da177e4
LT		 2144 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2145 return IRQ_NONE;
2146
2147 /* Ack interrupt(s) */
27345bb6 2148 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
1da177e4 2149
ca93ca42 2150 /* We hit Receive No Resource (RNR); restart RU after cleaning */
f26251eb 2151 if (stat_ack & stat_ack_rnr)
ca93ca42
JG		 2152 nic->ru_running = RU_SUSPENDED;
2153
288379f0 2154 if (likely(napi_schedule_prep(&nic->napi))) {
0685c31b 2155 e100_disable_irq(nic);
288379f0 2156 __napi_schedule(&nic->napi);
0685c31b 2157 }
1da177e4
LT		 2158
2159 return IRQ_HANDLED;
2160}
2161
bea3348e 2162static int e100_poll(struct napi_struct *napi, int budget)
1da177e4 2163{
bea3348e 2164 struct nic *nic = container_of(napi, struct nic, napi);
ddfce6bb 2165 unsigned int work_done = 0;
1da177e4 2166
bea3348e 2167 e100_rx_clean(nic, &work_done, budget);
53e52c72 2168 e100_tx_clean(nic);
1da177e4 2169
53e52c72
DM		 2170 /* If budget not fully consumed, exit the polling mode */
2171 if (work_done < budget) {
288379f0 2172 napi_complete(napi);
1da177e4 2173 e100_enable_irq(nic);
1da177e4
LT		 2174 }
2175
bea3348e 2176 return work_done;
1da177e4
LT		 2177}
2178
2179#ifdef CONFIG_NET_POLL_CONTROLLER
2180static void e100_netpoll(struct net_device *netdev)
2181{
2182 struct nic *nic = netdev_priv(netdev);
611494dc 2183
1da177e4 2184 e100_disable_irq(nic);
7d12e780 2185 e100_intr(nic->pdev->irq, netdev);
1da177e4
LT		 2186 e100_tx_clean(nic);
2187 e100_enable_irq(nic);
2188}
2189#endif
2190
1da177e4
LT		 2191static int e100_set_mac_address(struct net_device *netdev, void *p)
2192{
2193 struct nic *nic = netdev_priv(netdev);
2194 struct sockaddr *addr = p;
2195
2196 if (!is_valid_ether_addr(addr->sa_data))
2197 return -EADDRNOTAVAIL;
2198
2199 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2200 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2201
2202 return 0;
2203}
2204
2205static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2206{
f26251eb 2207 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1da177e4
LT		 2208 return -EINVAL;
2209 netdev->mtu = new_mtu;
2210 return 0;
2211}
2212
2213static int e100_asf(struct nic *nic)
2214{
2215 /* ASF can be enabled from eeprom */
2216 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2217 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2218 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2219 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2220}
2221
2222static int e100_up(struct nic *nic)
2223{
2224 int err;
2225
f26251eb 2226 if ((err = e100_rx_alloc_list(nic)))
1da177e4 2227 return err;
f26251eb 2228 if ((err = e100_alloc_cbs(nic)))
1da177e4 2229 goto err_rx_clean_list;
f26251eb 2230 if ((err = e100_hw_init(nic)))
1da177e4
LT		 2231 goto err_clean_cbs;
2232 e100_set_multicast_list(nic->netdev);
ca93ca42 2233 e100_start_receiver(nic, NULL);
1da177e4 2234 mod_timer(&nic->watchdog, jiffies);
f26251eb 2235 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
1da177e4
LT		 2236 nic->netdev->name, nic->netdev)))
2237 goto err_no_irq;
1da177e4 2238 netif_wake_queue(nic->netdev);
bea3348e 2239 napi_enable(&nic->napi);
0236ebb7
MC		 2240 /* enable ints _after_ enabling poll, preventing a race between
2241 * disable ints+schedule */
2242 e100_enable_irq(nic);
1da177e4
LT		 2243 return 0;
2244
2245err_no_irq:
2246 del_timer_sync(&nic->watchdog);
2247err_clean_cbs:
2248 e100_clean_cbs(nic);
2249err_rx_clean_list:
2250 e100_rx_clean_list(nic);
2251 return err;
2252}
2253
2254static void e100_down(struct nic *nic)
2255{
0236ebb7 2256 /* wait here for poll to complete */
bea3348e 2257 napi_disable(&nic->napi);
0236ebb7 2258 netif_stop_queue(nic->netdev);
1da177e4
LT		 2259 e100_hw_reset(nic);
2260 free_irq(nic->pdev->irq, nic->netdev);
2261 del_timer_sync(&nic->watchdog);
2262 netif_carrier_off(nic->netdev);
1da177e4
LT		 2263 e100_clean_cbs(nic);
2264 e100_rx_clean_list(nic);
2265}
2266
2267static void e100_tx_timeout(struct net_device *netdev)
2268{
2269 struct nic *nic = netdev_priv(netdev);
2270
05479938 2271 /* Reset outside of interrupt context, to avoid request_irq
2acdb1e0
MC		 2272 * in interrupt context */
2273 schedule_work(&nic->tx_timeout_task);
2274}
2275
c4028958 2276static void e100_tx_timeout_task(struct work_struct *work)
2acdb1e0 2277{
c4028958
DH		 2278 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2279 struct net_device *netdev = nic->netdev;
2acdb1e0 2280
fa05e1ad
JP		 2281 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
2282 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));
401da6ae
AC		 2283
2284 rtnl_lock();
2285 if (netif_running(netdev)) {
2286 e100_down(netdev_priv(netdev));
2287 e100_up(netdev_priv(netdev));
2288 }
2289 rtnl_unlock();
1da177e4
LT		 2290}
2291
2292static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2293{
2294 int err;
2295 struct sk_buff *skb;
2296
2297 /* Use driver resources to perform internal MAC or PHY
2298 * loopback test. A single packet is prepared and transmitted
2299 * in loopback mode, and the test passes if the received
2300 * packet compares byte-for-byte to the transmitted packet. */
2301
f26251eb 2302 if ((err = e100_rx_alloc_list(nic)))
1da177e4 2303 return err;
f26251eb 2304 if ((err = e100_alloc_cbs(nic)))
1da177e4
LT		 2305 goto err_clean_rx;
2306
2307 /* ICH PHY loopback is broken so do MAC loopback instead */
f26251eb 2308 if (nic->flags & ich && loopback_mode == lb_phy)
1da177e4
LT		 2309 loopback_mode = lb_mac;
2310
2311 nic->loopback = loopback_mode;
f26251eb 2312 if ((err = e100_hw_init(nic)))
1da177e4
LT		 2313 goto err_loopback_none;
2314
f26251eb 2315 if (loopback_mode == lb_phy)
1da177e4
LT		 2316 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2317 BMCR_LOOPBACK);
2318
ca93ca42 2319 e100_start_receiver(nic, NULL);
1da177e4 2320
f26251eb 2321 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
1da177e4
LT		 2322 err = -ENOMEM;
2323 goto err_loopback_none;
2324 }
2325 skb_put(skb, ETH_DATA_LEN);
2326 memset(skb->data, 0xFF, ETH_DATA_LEN);
2327 e100_xmit_frame(skb, nic->netdev);
2328
2329 msleep(10);
2330
aa49cdd9 2331 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
773c9c1f 2332 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
aa49cdd9 2333
f26251eb 2334 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1da177e4
LT		 2335 skb->data, ETH_DATA_LEN))
2336 err = -EAGAIN;
2337
2338err_loopback_none:
2339 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2340 nic->loopback = lb_none;
1da177e4 2341 e100_clean_cbs(nic);
aa49cdd9 2342 e100_hw_reset(nic);
1da177e4
LT		 2343err_clean_rx:
2344 e100_rx_clean_list(nic);
2345 return err;
2346}
2347
2348#define MII_LED_CONTROL 0x1B
b55de80e
BA		 2349#define E100_82552_LED_OVERRIDE 0x19
2350#define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2351#define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
1da177e4
LT		 2352static void e100_blink_led(unsigned long data)
2353{
2354 struct nic *nic = (struct nic *)data;
2355 enum led_state {
2356 led_on = 0x01,
2357 led_off = 0x04,
2358 led_on_559 = 0x05,
2359 led_on_557 = 0x07,
2360 };
b55de80e
BA		 2361 u16 led_reg = MII_LED_CONTROL;
2362
2363 if (nic->phy == phy_82552_v) {
2364 led_reg = E100_82552_LED_OVERRIDE;
1da177e4 2365
b55de80e
BA		 2366 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2367 E100_82552_LED_OFF : E100_82552_LED_ON;
2368 } else {
2369 nic->leds = (nic->leds & led_on) ? led_off :
2370 (nic->mac < mac_82559_D101M) ? led_on_557 :
2371 led_on_559;
2372 }
2373 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
1da177e4
LT		 2374 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2375}
2376
2377static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2378{
2379 struct nic *nic = netdev_priv(netdev);
2380 return mii_ethtool_gset(&nic->mii, cmd);
2381}
2382
2383static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2384{
2385 struct nic *nic = netdev_priv(netdev);
2386 int err;
2387
2388 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2389 err = mii_ethtool_sset(&nic->mii, cmd);
2390 e100_exec_cb(nic, NULL, e100_configure);
2391
2392 return err;
2393}
2394
2395static void e100_get_drvinfo(struct net_device *netdev,
2396 struct ethtool_drvinfo *info)
2397{
2398 struct nic *nic = netdev_priv(netdev);
2399 strcpy(info->driver, DRV_NAME);
2400 strcpy(info->version, DRV_VERSION);
2401 strcpy(info->fw_version, "N/A");
2402 strcpy(info->bus_info, pci_name(nic->pdev));
2403}
2404
abf9b902 2405#define E100_PHY_REGS 0x1C
1da177e4
LT		 2406static int e100_get_regs_len(struct net_device *netdev)
2407{
2408 struct nic *nic = netdev_priv(netdev);
abf9b902 2409 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
1da177e4
LT		 2410}
2411
2412static void e100_get_regs(struct net_device *netdev,
2413 struct ethtool_regs *regs, void *p)
2414{
2415 struct nic *nic = netdev_priv(netdev);
2416 u32 *buff = p;
2417 int i;
2418
44c10138 2419 regs->version = (1 << 24) | nic->pdev->revision;
27345bb6
JB		 2420 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2421 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2422 ioread16(&nic->csr->scb.status);
f26251eb 2423 for (i = E100_PHY_REGS; i >= 0; i--)
1da177e4
LT		 2424 buff[1 + E100_PHY_REGS - i] =
2425 mdio_read(netdev, nic->mii.phy_id, i);
2426 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2427 e100_exec_cb(nic, NULL, e100_dump);
2428 msleep(10);
2429 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2430 sizeof(nic->mem->dump_buf));
2431}
2432
2433static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2434{
2435 struct nic *nic = netdev_priv(netdev);
2436 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2437 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2438}
2439
2440static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2441{
2442 struct nic *nic = netdev_priv(netdev);
2443
bc79fc84
RW		 2444 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2445 !device_can_wakeup(&nic->pdev->dev))
1da177e4
LT		 2446 return -EOPNOTSUPP;
2447
f26251eb 2448 if (wol->wolopts)
1da177e4
LT		 2449 nic->flags |= wol_magic;
2450 else
2451 nic->flags &= ~wol_magic;
2452
bc79fc84
RW		 2453 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2454
1da177e4
LT		 2455 e100_exec_cb(nic, NULL, e100_configure);
2456
2457 return 0;
2458}
2459
2460static u32 e100_get_msglevel(struct net_device *netdev)
2461{
2462 struct nic *nic = netdev_priv(netdev);
2463 return nic->msg_enable;
2464}
2465
2466static void e100_set_msglevel(struct net_device *netdev, u32 value)
2467{
2468 struct nic *nic = netdev_priv(netdev);
2469 nic->msg_enable = value;
2470}
2471
2472static int e100_nway_reset(struct net_device *netdev)
2473{
2474 struct nic *nic = netdev_priv(netdev);
2475 return mii_nway_restart(&nic->mii);
2476}
2477
2478static u32 e100_get_link(struct net_device *netdev)
2479{
2480 struct nic *nic = netdev_priv(netdev);
2481 return mii_link_ok(&nic->mii);
2482}
2483
2484static int e100_get_eeprom_len(struct net_device *netdev)
2485{
2486 struct nic *nic = netdev_priv(netdev);
2487 return nic->eeprom_wc << 1;
2488}
2489
2490#define E100_EEPROM_MAGIC 0x1234
2491static int e100_get_eeprom(struct net_device *netdev,
2492 struct ethtool_eeprom *eeprom, u8 *bytes)
2493{
2494 struct nic *nic = netdev_priv(netdev);
2495
2496 eeprom->magic = E100_EEPROM_MAGIC;
2497 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2498
2499 return 0;
2500}
2501
2502static int e100_set_eeprom(struct net_device *netdev,
2503 struct ethtool_eeprom *eeprom, u8 *bytes)
2504{
2505 struct nic *nic = netdev_priv(netdev);
2506
f26251eb 2507 if (eeprom->magic != E100_EEPROM_MAGIC)
1da177e4
LT		 2508 return -EINVAL;
2509
2510 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2511
2512 return e100_eeprom_save(nic, eeprom->offset >> 1,
2513 (eeprom->len >> 1) + 1);
2514}
2515
2516static void e100_get_ringparam(struct net_device *netdev,
2517 struct ethtool_ringparam *ring)
2518{
2519 struct nic *nic = netdev_priv(netdev);
2520 struct param_range *rfds = &nic->params.rfds;
2521 struct param_range *cbs = &nic->params.cbs;
2522
2523 ring->rx_max_pending = rfds->max;
2524 ring->tx_max_pending = cbs->max;
2525 ring->rx_mini_max_pending = 0;
2526 ring->rx_jumbo_max_pending = 0;
2527 ring->rx_pending = rfds->count;
2528 ring->tx_pending = cbs->count;
2529 ring->rx_mini_pending = 0;
2530 ring->rx_jumbo_pending = 0;
2531}
2532
2533static int e100_set_ringparam(struct net_device *netdev,
2534 struct ethtool_ringparam *ring)
2535{
2536 struct nic *nic = netdev_priv(netdev);
2537 struct param_range *rfds = &nic->params.rfds;
2538 struct param_range *cbs = &nic->params.cbs;
2539
05479938 2540 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1da177e4
LT		 2541 return -EINVAL;
2542
f26251eb 2543 if (netif_running(netdev))
1da177e4
LT		 2544 e100_down(nic);
2545 rfds->count = max(ring->rx_pending, rfds->min);
2546 rfds->count = min(rfds->count, rfds->max);
2547 cbs->count = max(ring->tx_pending, cbs->min);
2548 cbs->count = min(cbs->count, cbs->max);
fa05e1ad
JP		 2549 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n",
2550 rfds->count, cbs->count);
f26251eb 2551 if (netif_running(netdev))
1da177e4
LT		 2552 e100_up(nic);
2553
2554 return 0;
2555}
2556
2557static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2558 "Link test (on/offline)",
2559 "Eeprom test (on/offline)",
2560 "Self test (offline)",
2561 "Mac loopback (offline)",
2562 "Phy loopback (offline)",
2563};
4c3616cd 2564#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
1da177e4 2565
1da177e4
LT		 2566static void e100_diag_test(struct net_device *netdev,
2567 struct ethtool_test *test, u64 *data)
2568{
2569 struct ethtool_cmd cmd;
2570 struct nic *nic = netdev_priv(netdev);
2571 int i, err;
2572
2573 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2574 data[0] = !mii_link_ok(&nic->mii);
2575 data[1] = e100_eeprom_load(nic);
f26251eb 2576 if (test->flags & ETH_TEST_FL_OFFLINE) {
1da177e4
LT		 2577
2578 /* save speed, duplex & autoneg settings */
2579 err = mii_ethtool_gset(&nic->mii, &cmd);
2580
f26251eb 2581 if (netif_running(netdev))
1da177e4
LT		 2582 e100_down(nic);
2583 data[2] = e100_self_test(nic);
2584 data[3] = e100_loopback_test(nic, lb_mac);
2585 data[4] = e100_loopback_test(nic, lb_phy);
2586
2587 /* restore speed, duplex & autoneg settings */
2588 err = mii_ethtool_sset(&nic->mii, &cmd);
2589
f26251eb 2590 if (netif_running(netdev))
1da177e4
LT		 2591 e100_up(nic);
2592 }
f26251eb 2593 for (i = 0; i < E100_TEST_LEN; i++)
1da177e4 2594 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
a074fb86
MC		 2595
2596 msleep_interruptible(4 * 1000);
1da177e4
LT		 2597}
2598
2599static int e100_phys_id(struct net_device *netdev, u32 data)
2600{
2601 struct nic *nic = netdev_priv(netdev);
b55de80e
BA		 2602 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2603 MII_LED_CONTROL;
1da177e4 2604
f26251eb 2605 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1da177e4
LT		 2606 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2607 mod_timer(&nic->blink_timer, jiffies);
2608 msleep_interruptible(data * 1000);
2609 del_timer_sync(&nic->blink_timer);
b55de80e 2610 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
1da177e4
LT		 2611
2612 return 0;
2613}
2614
2615static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2616 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2617 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2618 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2619 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2620 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2621 "tx_heartbeat_errors", "tx_window_errors",
2622 /* device-specific stats */
2623 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2624 "tx_flow_control_pause", "rx_flow_control_pause",
2625 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2626};
2627#define E100_NET_STATS_LEN 21
4c3616cd 2628#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
1da177e4 2629
b9f2c044 2630static int e100_get_sset_count(struct net_device *netdev, int sset)
1da177e4 2631{
b9f2c044
JG		 2632 switch (sset) {
2633 case ETH_SS_TEST:
2634 return E100_TEST_LEN;
2635 case ETH_SS_STATS:
2636 return E100_STATS_LEN;
2637 default:
2638 return -EOPNOTSUPP;
2639 }
1da177e4
LT		 2640}
2641
2642static void e100_get_ethtool_stats(struct net_device *netdev,
2643 struct ethtool_stats *stats, u64 *data)
2644{
2645 struct nic *nic = netdev_priv(netdev);
2646 int i;
2647
f26251eb 2648 for (i = 0; i < E100_NET_STATS_LEN; i++)
09f75cd7 2649 data[i] = ((unsigned long *)&netdev->stats)[i];
1da177e4
LT		 2650
2651 data[i++] = nic->tx_deferred;
2652 data[i++] = nic->tx_single_collisions;
2653 data[i++] = nic->tx_multiple_collisions;
2654 data[i++] = nic->tx_fc_pause;
2655 data[i++] = nic->rx_fc_pause;
2656 data[i++] = nic->rx_fc_unsupported;
2657 data[i++] = nic->tx_tco_frames;
2658 data[i++] = nic->rx_tco_frames;
2659}
2660
2661static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2662{
f26251eb 2663 switch (stringset) {
1da177e4
LT		 2664 case ETH_SS_TEST:
2665 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2666 break;
2667 case ETH_SS_STATS:
2668 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2669 break;
2670 }
2671}
2672
7282d491 2673static const struct ethtool_ops e100_ethtool_ops = {
1da177e4
LT		 2674 .get_settings = e100_get_settings,
2675 .set_settings = e100_set_settings,
2676 .get_drvinfo = e100_get_drvinfo,
2677 .get_regs_len = e100_get_regs_len,
2678 .get_regs = e100_get_regs,
2679 .get_wol = e100_get_wol,
2680 .set_wol = e100_set_wol,
2681 .get_msglevel = e100_get_msglevel,
2682 .set_msglevel = e100_set_msglevel,
2683 .nway_reset = e100_nway_reset,
2684 .get_link = e100_get_link,
2685 .get_eeprom_len = e100_get_eeprom_len,
2686 .get_eeprom = e100_get_eeprom,
2687 .set_eeprom = e100_set_eeprom,
2688 .get_ringparam = e100_get_ringparam,
2689 .set_ringparam = e100_set_ringparam,
1da177e4
LT		 2690 .self_test = e100_diag_test,
2691 .get_strings = e100_get_strings,
2692 .phys_id = e100_phys_id,
1da177e4 2693 .get_ethtool_stats = e100_get_ethtool_stats,
b9f2c044 2694 .get_sset_count = e100_get_sset_count,
1da177e4
LT		 2695};
2696
2697static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2698{
2699 struct nic *nic = netdev_priv(netdev);
2700
2701 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2702}
2703
2704static int e100_alloc(struct nic *nic)
2705{
2706 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2707 &nic->dma_addr);
2708 return nic->mem ? 0 : -ENOMEM;
2709}
2710
2711static void e100_free(struct nic *nic)
2712{
f26251eb 2713 if (nic->mem) {
1da177e4
LT		 2714 pci_free_consistent(nic->pdev, sizeof(struct mem),
2715 nic->mem, nic->dma_addr);
2716 nic->mem = NULL;
2717 }
2718}
2719
2720static int e100_open(struct net_device *netdev)
2721{
2722 struct nic *nic = netdev_priv(netdev);
2723 int err = 0;
2724
2725 netif_carrier_off(netdev);
f26251eb 2726 if ((err = e100_up(nic)))
fa05e1ad 2727 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n");
1da177e4
LT		 2728 return err;
2729}
2730
2731static int e100_close(struct net_device *netdev)
2732{
2733 e100_down(netdev_priv(netdev));
2734 return 0;
2735}
2736
acc78426
SH		 2737static const struct net_device_ops e100_netdev_ops = {
2738 .ndo_open = e100_open,
2739 .ndo_stop = e100_close,
00829823 2740 .ndo_start_xmit = e100_xmit_frame,
acc78426
SH		 2741 .ndo_validate_addr = eth_validate_addr,
2742 .ndo_set_multicast_list = e100_set_multicast_list,
2743 .ndo_set_mac_address = e100_set_mac_address,
2744 .ndo_change_mtu = e100_change_mtu,
2745 .ndo_do_ioctl = e100_do_ioctl,
2746 .ndo_tx_timeout = e100_tx_timeout,
2747#ifdef CONFIG_NET_POLL_CONTROLLER
2748 .ndo_poll_controller = e100_netpoll,
2749#endif
2750};
2751
1da177e4
LT		 2752static int __devinit e100_probe(struct pci_dev *pdev,
2753 const struct pci_device_id *ent)
2754{
2755 struct net_device *netdev;
2756 struct nic *nic;
2757 int err;
2758
f26251eb
BA		 2759 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2760 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
fa05e1ad 2761 pr_err("Etherdev alloc failed, aborting\n");
1da177e4
LT		 2762 return -ENOMEM;
2763 }
2764
acc78426 2765 netdev->netdev_ops = &e100_netdev_ops;
1da177e4 2766 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
1da177e4 2767 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
0eb5a34c 2768 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4
LT		 2769
2770 nic = netdev_priv(netdev);
bea3348e 2771 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
1da177e4
LT		 2772 nic->netdev = netdev;
2773 nic->pdev = pdev;
2774 nic->msg_enable = (1 << debug) - 1;
72001762 2775 nic->mdio_ctrl = mdio_ctrl_hw;
1da177e4
LT		 2776 pci_set_drvdata(pdev, netdev);
2777
f26251eb 2778 if ((err = pci_enable_device(pdev))) {
fa05e1ad 2779 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 2780 goto err_out_free_dev;
2781 }
2782
f26251eb 2783 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
fa05e1ad 2784 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n");
1da177e4
LT		 2785 err = -ENODEV;
2786 goto err_out_disable_pdev;
2787 }
2788
f26251eb 2789 if ((err = pci_request_regions(pdev, DRV_NAME))) {
fa05e1ad 2790 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 2791 goto err_out_disable_pdev;
2792 }
2793
284901a9 2794 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
fa05e1ad 2795 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n");
1da177e4
LT		 2796 goto err_out_free_res;
2797 }
2798
1da177e4
LT		 2799 SET_NETDEV_DEV(netdev, &pdev->dev);
2800
27345bb6 2801 if (use_io)
fa05e1ad 2802 netif_info(nic, probe, nic->netdev, "using i/o access mode\n");
27345bb6
JB		 2803
2804 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
f26251eb 2805 if (!nic->csr) {
fa05e1ad 2806 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n");
1da177e4
LT		 2807 err = -ENOMEM;
2808 goto err_out_free_res;
2809 }
2810
f26251eb 2811 if (ent->driver_data)
1da177e4
LT		 2812 nic->flags |= ich;
2813 else
2814 nic->flags &= ~ich;
2815
2816 e100_get_defaults(nic);
2817
1f53367d 2818 /* locks must be initialized before calling hw_reset */
1da177e4
LT		 2819 spin_lock_init(&nic->cb_lock);
2820 spin_lock_init(&nic->cmd_lock);
ac7c6669 2821 spin_lock_init(&nic->mdio_lock);
1da177e4
LT		 2822
2823 /* Reset the device before pci_set_master() in case device is in some
2824 * funky state and has an interrupt pending - hint: we don't have the
2825 * interrupt handler registered yet. */
2826 e100_hw_reset(nic);
2827
2828 pci_set_master(pdev);
2829
2830 init_timer(&nic->watchdog);
2831 nic->watchdog.function = e100_watchdog;
2832 nic->watchdog.data = (unsigned long)nic;
2833 init_timer(&nic->blink_timer);
2834 nic->blink_timer.function = e100_blink_led;
2835 nic->blink_timer.data = (unsigned long)nic;
2836
c4028958 2837 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2acdb1e0 2838
f26251eb 2839 if ((err = e100_alloc(nic))) {
fa05e1ad 2840 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n");
1da177e4
LT		 2841 goto err_out_iounmap;
2842 }
2843
f26251eb 2844 if ((err = e100_eeprom_load(nic)))
1da177e4
LT		 2845 goto err_out_free;
2846
f92d8728
MC		 2847 e100_phy_init(nic);
2848
1da177e4 2849 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
a92dd923 2850 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
948cd43f
JB		 2851 if (!is_valid_ether_addr(netdev->perm_addr)) {
2852 if (!eeprom_bad_csum_allow) {
fa05e1ad 2853 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n");
948cd43f
JB		 2854 err = -EAGAIN;
2855 goto err_out_free;
2856 } else {
fa05e1ad 2857 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n");
948cd43f 2858 }
1da177e4
LT		 2859 }
2860
2861 /* Wol magic packet can be enabled from eeprom */
f26251eb 2862 if ((nic->mac >= mac_82558_D101_A4) &&
bc79fc84 2863 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
1da177e4 2864 nic->flags |= wol_magic;
bc79fc84
RW		 2865 device_set_wakeup_enable(&pdev->dev, true);
2866 }
1da177e4 2867
6bdacb1a 2868 /* ack any pending wake events, disable PME */
e7272403 2869 pci_pme_active(pdev, false);
1da177e4
LT		 2870
2871 strcpy(netdev->name, "eth%d");
f26251eb 2872 if ((err = register_netdev(netdev))) {
fa05e1ad 2873 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
1da177e4
LT		 2874 goto err_out_free;
2875 }
98468efd
RO		 2876 nic->cbs_pool = pci_pool_create(netdev->name,
2877 nic->pdev,
211a0d94 2878 nic->params.cbs.max * sizeof(struct cb),
98468efd
RO		 2879 sizeof(u32),
2880 0);
fa05e1ad
JP		 2881 netif_info(nic, probe, nic->netdev,
2882 "addr 0x%llx, irq %d, MAC addr %pM\n",
2883 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2884 pdev->irq, netdev->dev_addr);
1da177e4
LT		 2885
2886 return 0;
2887
2888err_out_free:
2889 e100_free(nic);
2890err_out_iounmap:
27345bb6 2891 pci_iounmap(pdev, nic->csr);
1da177e4
LT		 2892err_out_free_res:
2893 pci_release_regions(pdev);
2894err_out_disable_pdev:
2895 pci_disable_device(pdev);
2896err_out_free_dev:
2897 pci_set_drvdata(pdev, NULL);
2898 free_netdev(netdev);
2899 return err;
2900}
2901
2902static void __devexit e100_remove(struct pci_dev *pdev)
2903{
2904 struct net_device *netdev = pci_get_drvdata(pdev);
2905
f26251eb 2906 if (netdev) {
1da177e4
LT		 2907 struct nic *nic = netdev_priv(netdev);
2908 unregister_netdev(netdev);
2909 e100_free(nic);
915e91d7 2910 pci_iounmap(pdev, nic->csr);
98468efd 2911 pci_pool_destroy(nic->cbs_pool);
1da177e4
LT		 2912 free_netdev(netdev);
2913 pci_release_regions(pdev);
2914 pci_disable_device(pdev);
2915 pci_set_drvdata(pdev, NULL);
2916 }
2917}
2918
b55de80e
BA		 2919#define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2920#define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2921#define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
ac7c992c 2922static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
1da177e4
LT		 2923{
2924 struct net_device *netdev = pci_get_drvdata(pdev);
2925 struct nic *nic = netdev_priv(netdev);
2926
824545e7 2927 if (netif_running(netdev))
f902283b 2928 e100_down(nic);
518d8338 2929 netif_device_detach(netdev);
a53a33da 2930
1da177e4 2931 pci_save_state(pdev);
e8e82b76
AK		 2932
2933 if ((nic->flags & wol_magic) | e100_asf(nic)) {
b55de80e
BA		 2934 /* enable reverse auto-negotiation */
2935 if (nic->phy == phy_82552_v) {
2936 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2937 E100_82552_SMARTSPEED);
2938
2939 mdio_write(netdev, nic->mii.phy_id,
2940 E100_82552_SMARTSPEED, smartspeed |
2941 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2942 }
ac7c992c 2943 *enable_wake = true;
e8e82b76 2944 } else {
ac7c992c 2945 *enable_wake = false;
e8e82b76 2946 }
975b366a 2947
8543da66 2948 pci_disable_device(pdev);
ac7c992c 2949}
1da177e4 2950
ac7c992c
TLSC		 2951static int __e100_power_off(struct pci_dev *pdev, bool wake)
2952{
6905b1f1 2953 if (wake)
ac7c992c 2954 return pci_prepare_to_sleep(pdev);
6905b1f1
RW		 2955
2956 pci_wake_from_d3(pdev, false);
2957 pci_set_power_state(pdev, PCI_D3hot);
2958
2959 return 0;
1da177e4
LT		 2960}
2961
f902283b 2962#ifdef CONFIG_PM
ac7c992c
TLSC		 2963static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2964{
2965 bool wake;
2966 __e100_shutdown(pdev, &wake);
2967 return __e100_power_off(pdev, wake);
2968}
2969
1da177e4
LT		 2970static int e100_resume(struct pci_dev *pdev)
2971{
2972 struct net_device *netdev = pci_get_drvdata(pdev);
2973 struct nic *nic = netdev_priv(netdev);
2974
975b366a 2975 pci_set_power_state(pdev, PCI_D0);
1da177e4 2976 pci_restore_state(pdev);
6bdacb1a 2977 /* ack any pending wake events, disable PME */
975b366a 2978 pci_enable_wake(pdev, 0, 0);
1da177e4 2979
4b512d26 2980 /* disable reverse auto-negotiation */
b55de80e
BA		 2981 if (nic->phy == phy_82552_v) {
2982 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2983 E100_82552_SMARTSPEED);
2984
2985 mdio_write(netdev, nic->mii.phy_id,
2986 E100_82552_SMARTSPEED,
2987 smartspeed & ~(E100_82552_REV_ANEG));
2988 }
2989
1da177e4 2990 netif_device_attach(netdev);
975b366a 2991 if (netif_running(netdev))
1da177e4
LT		 2992 e100_up(nic);
2993
2994 return 0;
2995}
975b366a 2996#endif /* CONFIG_PM */
1da177e4 2997
d18c3db5 2998static void e100_shutdown(struct pci_dev *pdev)
6bdacb1a 2999{
ac7c992c
TLSC		 3000 bool wake;
3001 __e100_shutdown(pdev, &wake);
3002 if (system_state == SYSTEM_POWER_OFF)
3003 __e100_power_off(pdev, wake);
6bdacb1a
MC		 3004}
3005
2cc30492
AK		 3006/* ------------------ PCI Error Recovery infrastructure -------------- */
3007/**
3008 * e100_io_error_detected - called when PCI error is detected.
3009 * @pdev: Pointer to PCI device
0a0863af 3010 * @state: The current pci connection state
2cc30492
AK		 3011 */
3012static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3013{
3014 struct net_device *netdev = pci_get_drvdata(pdev);
bea3348e 3015 struct nic *nic = netdev_priv(netdev);
2cc30492 3016
2cc30492 3017 netif_device_detach(netdev);
ef681ce1
AD		 3018
3019 if (state == pci_channel_io_perm_failure)
3020 return PCI_ERS_RESULT_DISCONNECT;
3021
3022 if (netif_running(netdev))
3023 e100_down(nic);
b1d26f24 3024 pci_disable_device(pdev);
2cc30492
AK		 3025
3026 /* Request a slot reset. */
3027 return PCI_ERS_RESULT_NEED_RESET;
3028}
3029
3030/**
3031 * e100_io_slot_reset - called after the pci bus has been reset.
3032 * @pdev: Pointer to PCI device
3033 *
3034 * Restart the card from scratch.
3035 */
3036static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3037{
3038 struct net_device *netdev = pci_get_drvdata(pdev);
3039 struct nic *nic = netdev_priv(netdev);
3040
3041 if (pci_enable_device(pdev)) {
fa05e1ad 3042 pr_err("Cannot re-enable PCI device after reset\n");
2cc30492
AK		 3043 return PCI_ERS_RESULT_DISCONNECT;
3044 }
3045 pci_set_master(pdev);
3046
3047 /* Only one device per card can do a reset */
3048 if (0 != PCI_FUNC(pdev->devfn))
3049 return PCI_ERS_RESULT_RECOVERED;
3050 e100_hw_reset(nic);
3051 e100_phy_init(nic);
3052
3053 return PCI_ERS_RESULT_RECOVERED;
3054}
3055
3056/**
3057 * e100_io_resume - resume normal operations
3058 * @pdev: Pointer to PCI device
3059 *
3060 * Resume normal operations after an error recovery
3061 * sequence has been completed.
3062 */
3063static void e100_io_resume(struct pci_dev *pdev)
3064{
3065 struct net_device *netdev = pci_get_drvdata(pdev);
3066 struct nic *nic = netdev_priv(netdev);
3067
3068 /* ack any pending wake events, disable PME */
3069 pci_enable_wake(pdev, 0, 0);
3070
3071 netif_device_attach(netdev);
3072 if (netif_running(netdev)) {
3073 e100_open(netdev);
3074 mod_timer(&nic->watchdog, jiffies);
3075 }
3076}
3077
3078static struct pci_error_handlers e100_err_handler = {
3079 .error_detected = e100_io_error_detected,
3080 .slot_reset = e100_io_slot_reset,
3081 .resume = e100_io_resume,
3082};
6bdacb1a 3083
1da177e4
LT		 3084static struct pci_driver e100_driver = {
3085 .name = DRV_NAME,
3086 .id_table = e100_id_table,
3087 .probe = e100_probe,
3088 .remove = __devexit_p(e100_remove),
e8e82b76 3089#ifdef CONFIG_PM
975b366a 3090 /* Power Management hooks */
1da177e4
LT		 3091 .suspend = e100_suspend,
3092 .resume = e100_resume,
3093#endif
05479938 3094 .shutdown = e100_shutdown,
2cc30492 3095 .err_handler = &e100_err_handler,
1da177e4
LT		 3096};
3097
3098static int __init e100_init_module(void)
3099{
f26251eb 3100 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
fa05e1ad
JP		 3101 pr_info("%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3102 pr_info("%s\n", DRV_COPYRIGHT);
1da177e4 3103 }
29917620 3104 return pci_register_driver(&e100_driver);
1da177e4
LT		 3105}
3106
3107static void __exit e100_cleanup_module(void)
3108{
3109 pci_unregister_driver(&e100_driver);
3110}
3111
3112module_init(e100_init_module);
3113module_exit(e100_cleanup_module);
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