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a1365275 SH |
1 | /* |
2 | * dm9000.c: Version 1.2 03/18/2003 | |
3 | * | |
4 | * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. | |
5 | * Copyright (C) 1997 Sten Wang | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. | |
18 | * | |
19 | * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match | |
20 | * 06/22/2001 Support DM9801 progrmming | |
21 | * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 | |
22 | * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 | |
23 | * R17 = (R17 & 0xfff0) | NF + 3 | |
24 | * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 | |
25 | * R17 = (R17 & 0xfff0) | NF | |
26 | * | |
27 | * v1.00 modify by simon 2001.9.5 | |
28 | * change for kernel 2.4.x | |
29 | * | |
30 | * v1.1 11/09/2001 fix force mode bug | |
31 | * | |
32 | * v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: | |
33 | * Fixed phy reset. | |
34 | * Added tx/rx 32 bit mode. | |
35 | * Cleaned up for kernel merge. | |
36 | * | |
37 | * 03/03/2004 Sascha Hauer <s.hauer@pengutronix.de> | |
38 | * Port to 2.6 kernel | |
39 | * | |
40 | * 24-Sep-2004 Ben Dooks <ben@simtec.co.uk> | |
41 | * Cleanup of code to remove ifdefs | |
42 | * Allowed platform device data to influence access width | |
43 | * Reformatting areas of code | |
44 | * | |
45 | * 17-Mar-2005 Sascha Hauer <s.hauer@pengutronix.de> | |
46 | * * removed 2.4 style module parameters | |
47 | * * removed removed unused stat counter and fixed | |
48 | * net_device_stats | |
49 | * * introduced tx_timeout function | |
50 | * * reworked locking | |
9ef9ac51 BD |
51 | * |
52 | * 01-Jul-2005 Ben Dooks <ben@simtec.co.uk> | |
53 | * * fixed spinlock call without pointer | |
54 | * * ensure spinlock is initialised | |
a1365275 SH |
55 | */ |
56 | ||
57 | #include <linux/module.h> | |
58 | #include <linux/ioport.h> | |
59 | #include <linux/netdevice.h> | |
60 | #include <linux/etherdevice.h> | |
61 | #include <linux/init.h> | |
62 | #include <linux/skbuff.h> | |
a1365275 SH |
63 | #include <linux/spinlock.h> |
64 | #include <linux/crc32.h> | |
65 | #include <linux/mii.h> | |
66 | #include <linux/dm9000.h> | |
67 | #include <linux/delay.h> | |
d052d1be | 68 | #include <linux/platform_device.h> |
4e4fc05a | 69 | #include <linux/irq.h> |
a1365275 SH |
70 | |
71 | #include <asm/delay.h> | |
72 | #include <asm/irq.h> | |
73 | #include <asm/io.h> | |
74 | ||
75 | #include "dm9000.h" | |
76 | ||
77 | /* Board/System/Debug information/definition ---------------- */ | |
78 | ||
79 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
80 | ||
a1365275 SH |
81 | #define CARDNAME "dm9000" |
82 | #define PFX CARDNAME ": " | |
83 | ||
84 | #define DM9000_TIMER_WUT jiffies+(HZ*2) /* timer wakeup time : 2 second */ | |
85 | ||
f40d24d9 AL |
86 | #ifdef CONFIG_BLACKFIN |
87 | #define readsb insb | |
88 | #define readsw insw | |
89 | #define readsl insl | |
90 | #define writesb outsb | |
91 | #define writesw outsw | |
92 | #define writesl outsl | |
93 | #define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH) | |
94 | #else | |
4e4fc05a | 95 | #define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQT_RISING) |
f40d24d9 AL |
96 | #endif |
97 | ||
a1365275 SH |
98 | /* |
99 | * Transmit timeout, default 5 seconds. | |
100 | */ | |
101 | static int watchdog = 5000; | |
102 | module_param(watchdog, int, 0400); | |
103 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
104 | ||
105 | /* Structure/enum declaration ------------------------------- */ | |
106 | typedef struct board_info { | |
107 | ||
108 | void __iomem *io_addr; /* Register I/O base address */ | |
109 | void __iomem *io_data; /* Data I/O address */ | |
110 | u16 irq; /* IRQ */ | |
111 | ||
112 | u16 tx_pkt_cnt; | |
113 | u16 queue_pkt_len; | |
114 | u16 queue_start_addr; | |
115 | u16 dbug_cnt; | |
116 | u8 io_mode; /* 0:word, 2:byte */ | |
117 | u8 phy_addr; | |
33ba5091 | 118 | unsigned int flags; |
a1365275 | 119 | |
5b2b4ff0 BD |
120 | int debug_level; |
121 | ||
a1365275 SH |
122 | void (*inblk)(void __iomem *port, void *data, int length); |
123 | void (*outblk)(void __iomem *port, void *data, int length); | |
124 | void (*dumpblk)(void __iomem *port, int length); | |
125 | ||
a76836f9 BD |
126 | struct device *dev; /* parent device */ |
127 | ||
a1365275 SH |
128 | struct resource *addr_res; /* resources found */ |
129 | struct resource *data_res; | |
130 | struct resource *addr_req; /* resources requested */ | |
131 | struct resource *data_req; | |
132 | struct resource *irq_res; | |
133 | ||
134 | struct timer_list timer; | |
a1365275 SH |
135 | unsigned char srom[128]; |
136 | spinlock_t lock; | |
137 | ||
138 | struct mii_if_info mii; | |
139 | u32 msg_enable; | |
140 | } board_info_t; | |
141 | ||
5b2b4ff0 BD |
142 | /* debug code */ |
143 | ||
144 | #define dm9000_dbg(db, lev, msg...) do { \ | |
145 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
146 | (lev) < db->debug_level) { \ | |
147 | dev_dbg(db->dev, msg); \ | |
148 | } \ | |
149 | } while (0) | |
150 | ||
a1365275 | 151 | /* function declaration ------------------------------------- */ |
3ae5eaec | 152 | static int dm9000_probe(struct platform_device *); |
a1365275 SH |
153 | static int dm9000_open(struct net_device *); |
154 | static int dm9000_start_xmit(struct sk_buff *, struct net_device *); | |
155 | static int dm9000_stop(struct net_device *); | |
a1365275 SH |
156 | |
157 | ||
158 | static void dm9000_timer(unsigned long); | |
159 | static void dm9000_init_dm9000(struct net_device *); | |
160 | ||
7d12e780 | 161 | static irqreturn_t dm9000_interrupt(int, void *); |
a1365275 SH |
162 | |
163 | static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg); | |
164 | static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, | |
165 | int value); | |
166 | static u16 read_srom_word(board_info_t *, int); | |
167 | static void dm9000_rx(struct net_device *); | |
168 | static void dm9000_hash_table(struct net_device *); | |
169 | ||
170 | //#define DM9000_PROGRAM_EEPROM | |
171 | #ifdef DM9000_PROGRAM_EEPROM | |
172 | static void program_eeprom(board_info_t * db); | |
173 | #endif | |
174 | /* DM9000 network board routine ---------------------------- */ | |
175 | ||
176 | static void | |
177 | dm9000_reset(board_info_t * db) | |
178 | { | |
a76836f9 BD |
179 | dev_dbg(db->dev, "resetting device\n"); |
180 | ||
a1365275 SH |
181 | /* RESET device */ |
182 | writeb(DM9000_NCR, db->io_addr); | |
183 | udelay(200); | |
184 | writeb(NCR_RST, db->io_data); | |
185 | udelay(200); | |
186 | } | |
187 | ||
188 | /* | |
189 | * Read a byte from I/O port | |
190 | */ | |
191 | static u8 | |
192 | ior(board_info_t * db, int reg) | |
193 | { | |
194 | writeb(reg, db->io_addr); | |
195 | return readb(db->io_data); | |
196 | } | |
197 | ||
198 | /* | |
199 | * Write a byte to I/O port | |
200 | */ | |
201 | ||
202 | static void | |
203 | iow(board_info_t * db, int reg, int value) | |
204 | { | |
205 | writeb(reg, db->io_addr); | |
206 | writeb(value, db->io_data); | |
207 | } | |
208 | ||
209 | /* routines for sending block to chip */ | |
210 | ||
211 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
212 | { | |
213 | writesb(reg, data, count); | |
214 | } | |
215 | ||
216 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
217 | { | |
218 | writesw(reg, data, (count+1) >> 1); | |
219 | } | |
220 | ||
221 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
222 | { | |
223 | writesl(reg, data, (count+3) >> 2); | |
224 | } | |
225 | ||
226 | /* input block from chip to memory */ | |
227 | ||
228 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
229 | { | |
5f6b5517 | 230 | readsb(reg, data, count); |
a1365275 SH |
231 | } |
232 | ||
233 | ||
234 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
235 | { | |
236 | readsw(reg, data, (count+1) >> 1); | |
237 | } | |
238 | ||
239 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
240 | { | |
241 | readsl(reg, data, (count+3) >> 2); | |
242 | } | |
243 | ||
244 | /* dump block from chip to null */ | |
245 | ||
246 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
247 | { | |
248 | int i; | |
249 | int tmp; | |
250 | ||
251 | for (i = 0; i < count; i++) | |
252 | tmp = readb(reg); | |
253 | } | |
254 | ||
255 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
256 | { | |
257 | int i; | |
258 | int tmp; | |
259 | ||
260 | count = (count + 1) >> 1; | |
261 | ||
262 | for (i = 0; i < count; i++) | |
263 | tmp = readw(reg); | |
264 | } | |
265 | ||
266 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
267 | { | |
268 | int i; | |
269 | int tmp; | |
270 | ||
271 | count = (count + 3) >> 2; | |
272 | ||
273 | for (i = 0; i < count; i++) | |
274 | tmp = readl(reg); | |
275 | } | |
276 | ||
277 | /* dm9000_set_io | |
278 | * | |
279 | * select the specified set of io routines to use with the | |
280 | * device | |
281 | */ | |
282 | ||
283 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
284 | { | |
285 | /* use the size of the data resource to work out what IO | |
286 | * routines we want to use | |
287 | */ | |
288 | ||
289 | switch (byte_width) { | |
290 | case 1: | |
291 | db->dumpblk = dm9000_dumpblk_8bit; | |
292 | db->outblk = dm9000_outblk_8bit; | |
293 | db->inblk = dm9000_inblk_8bit; | |
294 | break; | |
295 | ||
a1365275 SH |
296 | |
297 | case 3: | |
a76836f9 BD |
298 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
299 | case 2: | |
a1365275 SH |
300 | db->dumpblk = dm9000_dumpblk_16bit; |
301 | db->outblk = dm9000_outblk_16bit; | |
302 | db->inblk = dm9000_inblk_16bit; | |
303 | break; | |
304 | ||
305 | case 4: | |
306 | default: | |
307 | db->dumpblk = dm9000_dumpblk_32bit; | |
308 | db->outblk = dm9000_outblk_32bit; | |
309 | db->inblk = dm9000_inblk_32bit; | |
310 | break; | |
311 | } | |
312 | } | |
313 | ||
314 | ||
315 | /* Our watchdog timed out. Called by the networking layer */ | |
316 | static void dm9000_timeout(struct net_device *dev) | |
317 | { | |
318 | board_info_t *db = (board_info_t *) dev->priv; | |
319 | u8 reg_save; | |
320 | unsigned long flags; | |
321 | ||
322 | /* Save previous register address */ | |
323 | reg_save = readb(db->io_addr); | |
9ef9ac51 | 324 | spin_lock_irqsave(&db->lock,flags); |
a1365275 SH |
325 | |
326 | netif_stop_queue(dev); | |
327 | dm9000_reset(db); | |
328 | dm9000_init_dm9000(dev); | |
329 | /* We can accept TX packets again */ | |
330 | dev->trans_start = jiffies; | |
331 | netif_wake_queue(dev); | |
332 | ||
333 | /* Restore previous register address */ | |
334 | writeb(reg_save, db->io_addr); | |
9ef9ac51 | 335 | spin_unlock_irqrestore(&db->lock,flags); |
a1365275 SH |
336 | } |
337 | ||
2fd0e33f KH |
338 | #ifdef CONFIG_NET_POLL_CONTROLLER |
339 | /* | |
340 | *Used by netconsole | |
341 | */ | |
342 | static void dm9000_poll_controller(struct net_device *dev) | |
343 | { | |
344 | disable_irq(dev->irq); | |
28431146 | 345 | dm9000_interrupt(dev->irq,dev); |
2fd0e33f KH |
346 | enable_irq(dev->irq); |
347 | } | |
348 | #endif | |
a1365275 SH |
349 | |
350 | /* dm9000_release_board | |
351 | * | |
352 | * release a board, and any mapped resources | |
353 | */ | |
354 | ||
355 | static void | |
356 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
357 | { | |
358 | if (db->data_res == NULL) { | |
359 | if (db->addr_res != NULL) | |
360 | release_mem_region((unsigned long)db->io_addr, 4); | |
361 | return; | |
362 | } | |
363 | ||
364 | /* unmap our resources */ | |
365 | ||
366 | iounmap(db->io_addr); | |
367 | iounmap(db->io_data); | |
368 | ||
369 | /* release the resources */ | |
370 | ||
371 | if (db->data_req != NULL) { | |
372 | release_resource(db->data_req); | |
373 | kfree(db->data_req); | |
374 | } | |
375 | ||
51985487 DO |
376 | if (db->addr_req != NULL) { |
377 | release_resource(db->addr_req); | |
a1365275 SH |
378 | kfree(db->addr_req); |
379 | } | |
380 | } | |
381 | ||
382 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) | |
383 | ||
384 | /* | |
385 | * Search DM9000 board, allocate space and register it | |
386 | */ | |
387 | static int | |
3ae5eaec | 388 | dm9000_probe(struct platform_device *pdev) |
a1365275 | 389 | { |
a1365275 SH |
390 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; |
391 | struct board_info *db; /* Point a board information structure */ | |
392 | struct net_device *ndev; | |
393 | unsigned long base; | |
394 | int ret = 0; | |
395 | int iosize; | |
396 | int i; | |
397 | u32 id_val; | |
398 | ||
a1365275 SH |
399 | /* Init network device */ |
400 | ndev = alloc_etherdev(sizeof (struct board_info)); | |
401 | if (!ndev) { | |
a76836f9 | 402 | dev_err(&pdev->dev, "could not allocate device.\n"); |
a1365275 SH |
403 | return -ENOMEM; |
404 | } | |
405 | ||
3ae5eaec | 406 | SET_NETDEV_DEV(ndev, &pdev->dev); |
a1365275 | 407 | |
a76836f9 | 408 | dev_dbg(&pdev->dev, "dm9000_probe()"); |
a1365275 SH |
409 | |
410 | /* setup board info structure */ | |
411 | db = (struct board_info *) ndev->priv; | |
412 | memset(db, 0, sizeof (*db)); | |
413 | ||
a76836f9 BD |
414 | db->dev = &pdev->dev; |
415 | ||
9ef9ac51 BD |
416 | spin_lock_init(&db->lock); |
417 | ||
a1365275 SH |
418 | if (pdev->num_resources < 2) { |
419 | ret = -ENODEV; | |
420 | goto out; | |
b4ed03ff | 421 | } else if (pdev->num_resources == 2) { |
a1365275 SH |
422 | base = pdev->resource[0].start; |
423 | ||
424 | if (!request_mem_region(base, 4, ndev->name)) { | |
425 | ret = -EBUSY; | |
426 | goto out; | |
427 | } | |
428 | ||
429 | ndev->base_addr = base; | |
430 | ndev->irq = pdev->resource[1].start; | |
b4ed03ff BD |
431 | db->io_addr = (void __iomem *)base; |
432 | db->io_data = (void __iomem *)(base + 4); | |
a1365275 | 433 | |
f40d24d9 AL |
434 | /* ensure at least we have a default set of IO routines */ |
435 | dm9000_set_io(db, 2); | |
436 | ||
b4ed03ff | 437 | } else { |
a1365275 SH |
438 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
439 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
440 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
441 | ||
b4ed03ff BD |
442 | if (db->addr_res == NULL || db->data_res == NULL || |
443 | db->irq_res == NULL) { | |
a76836f9 | 444 | dev_err(db->dev, "insufficient resources\n"); |
a1365275 SH |
445 | ret = -ENOENT; |
446 | goto out; | |
447 | } | |
448 | ||
449 | i = res_size(db->addr_res); | |
450 | db->addr_req = request_mem_region(db->addr_res->start, i, | |
451 | pdev->name); | |
452 | ||
453 | if (db->addr_req == NULL) { | |
a76836f9 | 454 | dev_err(db->dev, "cannot claim address reg area\n"); |
a1365275 SH |
455 | ret = -EIO; |
456 | goto out; | |
457 | } | |
458 | ||
459 | db->io_addr = ioremap(db->addr_res->start, i); | |
460 | ||
461 | if (db->io_addr == NULL) { | |
a76836f9 | 462 | dev_err(db->dev, "failed to ioremap address reg\n"); |
a1365275 SH |
463 | ret = -EINVAL; |
464 | goto out; | |
465 | } | |
466 | ||
467 | iosize = res_size(db->data_res); | |
468 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
469 | pdev->name); | |
470 | ||
471 | if (db->data_req == NULL) { | |
a76836f9 | 472 | dev_err(db->dev, "cannot claim data reg area\n"); |
a1365275 SH |
473 | ret = -EIO; |
474 | goto out; | |
475 | } | |
476 | ||
477 | db->io_data = ioremap(db->data_res->start, iosize); | |
478 | ||
479 | if (db->io_data == NULL) { | |
a76836f9 | 480 | dev_err(db->dev,"failed to ioremap data reg\n"); |
a1365275 SH |
481 | ret = -EINVAL; |
482 | goto out; | |
483 | } | |
484 | ||
485 | /* fill in parameters for net-dev structure */ | |
486 | ||
487 | ndev->base_addr = (unsigned long)db->io_addr; | |
488 | ndev->irq = db->irq_res->start; | |
489 | ||
490 | /* ensure at least we have a default set of IO routines */ | |
491 | dm9000_set_io(db, iosize); | |
a1365275 SH |
492 | } |
493 | ||
494 | /* check to see if anything is being over-ridden */ | |
495 | if (pdata != NULL) { | |
496 | /* check to see if the driver wants to over-ride the | |
497 | * default IO width */ | |
498 | ||
499 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
500 | dm9000_set_io(db, 1); | |
501 | ||
502 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
503 | dm9000_set_io(db, 2); | |
504 | ||
505 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
506 | dm9000_set_io(db, 4); | |
507 | ||
508 | /* check to see if there are any IO routine | |
509 | * over-rides */ | |
510 | ||
511 | if (pdata->inblk != NULL) | |
512 | db->inblk = pdata->inblk; | |
513 | ||
514 | if (pdata->outblk != NULL) | |
515 | db->outblk = pdata->outblk; | |
516 | ||
517 | if (pdata->dumpblk != NULL) | |
518 | db->dumpblk = pdata->dumpblk; | |
33ba5091 BD |
519 | |
520 | db->flags = pdata->flags; | |
a1365275 SH |
521 | } |
522 | ||
523 | dm9000_reset(db); | |
524 | ||
525 | /* try two times, DM9000 sometimes gets the first read wrong */ | |
526 | for (i = 0; i < 2; i++) { | |
527 | id_val = ior(db, DM9000_VIDL); | |
528 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
529 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
530 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
531 | ||
532 | if (id_val == DM9000_ID) | |
533 | break; | |
a76836f9 | 534 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); |
a1365275 SH |
535 | } |
536 | ||
537 | if (id_val != DM9000_ID) { | |
a76836f9 | 538 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); |
418d6f87 MR |
539 | ret = -ENODEV; |
540 | goto out; | |
a1365275 SH |
541 | } |
542 | ||
543 | /* from this point we assume that we have found a DM9000 */ | |
544 | ||
545 | /* driver system function */ | |
546 | ether_setup(ndev); | |
547 | ||
548 | ndev->open = &dm9000_open; | |
549 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
550 | ndev->tx_timeout = &dm9000_timeout; | |
551 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
552 | ndev->stop = &dm9000_stop; | |
a1365275 | 553 | ndev->set_multicast_list = &dm9000_hash_table; |
2fd0e33f KH |
554 | #ifdef CONFIG_NET_POLL_CONTROLLER |
555 | ndev->poll_controller = &dm9000_poll_controller; | |
556 | #endif | |
a1365275 SH |
557 | |
558 | #ifdef DM9000_PROGRAM_EEPROM | |
559 | program_eeprom(db); | |
560 | #endif | |
561 | db->msg_enable = NETIF_MSG_LINK; | |
562 | db->mii.phy_id_mask = 0x1f; | |
563 | db->mii.reg_num_mask = 0x1f; | |
564 | db->mii.force_media = 0; | |
565 | db->mii.full_duplex = 0; | |
566 | db->mii.dev = ndev; | |
567 | db->mii.mdio_read = dm9000_phy_read; | |
568 | db->mii.mdio_write = dm9000_phy_write; | |
569 | ||
570 | /* Read SROM content */ | |
571 | for (i = 0; i < 64; i++) | |
572 | ((u16 *) db->srom)[i] = read_srom_word(db, i); | |
573 | ||
574 | /* Set Node Address */ | |
575 | for (i = 0; i < 6; i++) | |
576 | ndev->dev_addr[i] = db->srom[i]; | |
577 | ||
5b55dda6 BD |
578 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
579 | /* try reading from mac */ | |
580 | ||
581 | for (i = 0; i < 6; i++) | |
582 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
583 | } | |
584 | ||
a1365275 | 585 | if (!is_valid_ether_addr(ndev->dev_addr)) |
a76836f9 BD |
586 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " |
587 | "set using ifconfig\n", ndev->name); | |
a1365275 | 588 | |
3ae5eaec | 589 | platform_set_drvdata(pdev, ndev); |
a1365275 SH |
590 | ret = register_netdev(ndev); |
591 | ||
592 | if (ret == 0) { | |
0795af57 JP |
593 | DECLARE_MAC_BUF(mac); |
594 | printk("%s: dm9000 at %p,%p IRQ %d MAC: %s\n", | |
595 | ndev->name, db->io_addr, db->io_data, ndev->irq, | |
596 | print_mac(mac, ndev->dev_addr)); | |
a1365275 SH |
597 | } |
598 | return 0; | |
599 | ||
418d6f87 | 600 | out: |
a76836f9 | 601 | dev_err(db->dev, "not found (%d).\n", ret); |
a1365275 SH |
602 | |
603 | dm9000_release_board(pdev, db); | |
9fd9f9b6 | 604 | free_netdev(ndev); |
a1365275 SH |
605 | |
606 | return ret; | |
607 | } | |
608 | ||
609 | /* | |
610 | * Open the interface. | |
611 | * The interface is opened whenever "ifconfig" actives it. | |
612 | */ | |
613 | static int | |
614 | dm9000_open(struct net_device *dev) | |
615 | { | |
616 | board_info_t *db = (board_info_t *) dev->priv; | |
617 | ||
a76836f9 | 618 | dev_dbg(db->dev, "entering %s\n", __func__); |
a1365275 | 619 | |
f40d24d9 | 620 | if (request_irq(dev->irq, &dm9000_interrupt, DM9000_IRQ_FLAGS, dev->name, dev)) |
a1365275 SH |
621 | return -EAGAIN; |
622 | ||
623 | /* Initialize DM9000 board */ | |
624 | dm9000_reset(db); | |
625 | dm9000_init_dm9000(dev); | |
626 | ||
627 | /* Init driver variable */ | |
628 | db->dbug_cnt = 0; | |
629 | ||
630 | /* set and active a timer process */ | |
631 | init_timer(&db->timer); | |
9ef9ac51 | 632 | db->timer.expires = DM9000_TIMER_WUT; |
a1365275 SH |
633 | db->timer.data = (unsigned long) dev; |
634 | db->timer.function = &dm9000_timer; | |
635 | add_timer(&db->timer); | |
636 | ||
637 | mii_check_media(&db->mii, netif_msg_link(db), 1); | |
638 | netif_start_queue(dev); | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | /* | |
644 | * Initilize dm9000 board | |
645 | */ | |
646 | static void | |
647 | dm9000_init_dm9000(struct net_device *dev) | |
648 | { | |
649 | board_info_t *db = (board_info_t *) dev->priv; | |
650 | ||
5b2b4ff0 | 651 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 SH |
652 | |
653 | /* I/O mode */ | |
654 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
655 | ||
656 | /* GPIO0 on pre-activate PHY */ | |
657 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
658 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
659 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
660 | ||
33ba5091 BD |
661 | if (db->flags & DM9000_PLATF_EXT_PHY) |
662 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
663 | ||
a1365275 SH |
664 | /* Program operating register */ |
665 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
666 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
667 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
668 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
669 | /* clear TX status */ | |
670 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
671 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
672 | ||
673 | /* Set address filter table */ | |
674 | dm9000_hash_table(dev); | |
675 | ||
676 | /* Activate DM9000 */ | |
677 | iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); | |
678 | /* Enable TX/RX interrupt mask */ | |
679 | iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); | |
680 | ||
681 | /* Init Driver variable */ | |
682 | db->tx_pkt_cnt = 0; | |
683 | db->queue_pkt_len = 0; | |
684 | dev->trans_start = 0; | |
a1365275 SH |
685 | } |
686 | ||
687 | /* | |
688 | * Hardware start transmission. | |
689 | * Send a packet to media from the upper layer. | |
690 | */ | |
691 | static int | |
692 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
693 | { | |
c46ac946 | 694 | unsigned long flags; |
a1365275 SH |
695 | board_info_t *db = (board_info_t *) dev->priv; |
696 | ||
5b2b4ff0 | 697 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
698 | |
699 | if (db->tx_pkt_cnt > 1) | |
700 | return 1; | |
701 | ||
c46ac946 | 702 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
703 | |
704 | /* Move data to DM9000 TX RAM */ | |
705 | writeb(DM9000_MWCMD, db->io_addr); | |
706 | ||
707 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 708 | dev->stats.tx_bytes += skb->len; |
a1365275 | 709 | |
c46ac946 | 710 | db->tx_pkt_cnt++; |
a1365275 | 711 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 712 | if (db->tx_pkt_cnt == 1) { |
a1365275 SH |
713 | /* Set TX length to DM9000 */ |
714 | iow(db, DM9000_TXPLL, skb->len & 0xff); | |
715 | iow(db, DM9000_TXPLH, (skb->len >> 8) & 0xff); | |
716 | ||
717 | /* Issue TX polling command */ | |
718 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
719 | ||
720 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
721 | } else { |
722 | /* Second packet */ | |
a1365275 | 723 | db->queue_pkt_len = skb->len; |
c46ac946 | 724 | netif_stop_queue(dev); |
a1365275 SH |
725 | } |
726 | ||
c46ac946 FW |
727 | spin_unlock_irqrestore(&db->lock, flags); |
728 | ||
a1365275 SH |
729 | /* free this SKB */ |
730 | dev_kfree_skb(skb); | |
731 | ||
a1365275 SH |
732 | return 0; |
733 | } | |
734 | ||
735 | static void | |
736 | dm9000_shutdown(struct net_device *dev) | |
737 | { | |
738 | board_info_t *db = (board_info_t *) dev->priv; | |
739 | ||
740 | /* RESET device */ | |
741 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
742 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
743 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
744 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
745 | } | |
746 | ||
747 | /* | |
748 | * Stop the interface. | |
749 | * The interface is stopped when it is brought. | |
750 | */ | |
751 | static int | |
752 | dm9000_stop(struct net_device *ndev) | |
753 | { | |
754 | board_info_t *db = (board_info_t *) ndev->priv; | |
755 | ||
5b2b4ff0 | 756 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 SH |
757 | |
758 | /* deleted timer */ | |
759 | del_timer(&db->timer); | |
760 | ||
761 | netif_stop_queue(ndev); | |
762 | netif_carrier_off(ndev); | |
763 | ||
764 | /* free interrupt */ | |
765 | free_irq(ndev->irq, ndev); | |
766 | ||
767 | dm9000_shutdown(ndev); | |
768 | ||
769 | return 0; | |
770 | } | |
771 | ||
772 | /* | |
773 | * DM9000 interrupt handler | |
774 | * receive the packet to upper layer, free the transmitted packet | |
775 | */ | |
776 | ||
5d22a312 | 777 | static void |
a1365275 SH |
778 | dm9000_tx_done(struct net_device *dev, board_info_t * db) |
779 | { | |
780 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ | |
781 | ||
782 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { | |
783 | /* One packet sent complete */ | |
784 | db->tx_pkt_cnt--; | |
09f75cd7 | 785 | dev->stats.tx_packets++; |
a1365275 SH |
786 | |
787 | /* Queue packet check & send */ | |
788 | if (db->tx_pkt_cnt > 0) { | |
789 | iow(db, DM9000_TXPLL, db->queue_pkt_len & 0xff); | |
790 | iow(db, DM9000_TXPLH, (db->queue_pkt_len >> 8) & 0xff); | |
791 | iow(db, DM9000_TCR, TCR_TXREQ); | |
792 | dev->trans_start = jiffies; | |
793 | } | |
794 | netif_wake_queue(dev); | |
795 | } | |
796 | } | |
797 | ||
798 | static irqreturn_t | |
7d12e780 | 799 | dm9000_interrupt(int irq, void *dev_id) |
a1365275 SH |
800 | { |
801 | struct net_device *dev = dev_id; | |
5b2b4ff0 | 802 | board_info_t *db = (board_info_t *) dev->priv; |
a1365275 SH |
803 | int int_status; |
804 | u8 reg_save; | |
805 | ||
5b2b4ff0 | 806 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
a1365275 SH |
807 | |
808 | /* A real interrupt coming */ | |
5b2b4ff0 | 809 | |
a1365275 SH |
810 | spin_lock(&db->lock); |
811 | ||
812 | /* Save previous register address */ | |
813 | reg_save = readb(db->io_addr); | |
814 | ||
815 | /* Disable all interrupts */ | |
816 | iow(db, DM9000_IMR, IMR_PAR); | |
817 | ||
818 | /* Got DM9000 interrupt status */ | |
819 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
820 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
821 | ||
822 | /* Received the coming packet */ | |
823 | if (int_status & ISR_PRS) | |
824 | dm9000_rx(dev); | |
825 | ||
826 | /* Trnasmit Interrupt check */ | |
827 | if (int_status & ISR_PTS) | |
828 | dm9000_tx_done(dev, db); | |
829 | ||
830 | /* Re-enable interrupt mask */ | |
831 | iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); | |
832 | ||
833 | /* Restore previous register address */ | |
834 | writeb(reg_save, db->io_addr); | |
835 | ||
836 | spin_unlock(&db->lock); | |
837 | ||
838 | return IRQ_HANDLED; | |
839 | } | |
840 | ||
a1365275 SH |
841 | /* |
842 | * A periodic timer routine | |
843 | * Dynamic media sense, allocated Rx buffer... | |
844 | */ | |
845 | static void | |
846 | dm9000_timer(unsigned long data) | |
847 | { | |
848 | struct net_device *dev = (struct net_device *) data; | |
849 | board_info_t *db = (board_info_t *) dev->priv; | |
a1365275 | 850 | |
5b2b4ff0 | 851 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
a1365275 | 852 | |
a1365275 SH |
853 | mii_check_media(&db->mii, netif_msg_link(db), 0); |
854 | ||
a1365275 SH |
855 | /* Set timer again */ |
856 | db->timer.expires = DM9000_TIMER_WUT; | |
857 | add_timer(&db->timer); | |
858 | } | |
859 | ||
860 | struct dm9000_rxhdr { | |
93116573 BD |
861 | u8 RxPktReady; |
862 | u8 RxStatus; | |
a1365275 SH |
863 | u16 RxLen; |
864 | } __attribute__((__packed__)); | |
865 | ||
866 | /* | |
867 | * Received a packet and pass to upper layer | |
868 | */ | |
869 | static void | |
870 | dm9000_rx(struct net_device *dev) | |
871 | { | |
872 | board_info_t *db = (board_info_t *) dev->priv; | |
873 | struct dm9000_rxhdr rxhdr; | |
874 | struct sk_buff *skb; | |
875 | u8 rxbyte, *rdptr; | |
6478fac6 | 876 | bool GoodPacket; |
a1365275 SH |
877 | int RxLen; |
878 | ||
879 | /* Check packet ready or not */ | |
880 | do { | |
881 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
882 | ||
883 | /* Get most updated data */ | |
884 | rxbyte = readb(db->io_data); | |
885 | ||
886 | /* Status check: this byte must be 0 or 1 */ | |
887 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 888 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
889 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
890 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
891 | return; | |
892 | } | |
893 | ||
894 | if (rxbyte != DM9000_PKT_RDY) | |
895 | return; | |
896 | ||
897 | /* A packet ready now & Get status/length */ | |
6478fac6 | 898 | GoodPacket = true; |
a1365275 SH |
899 | writeb(DM9000_MRCMD, db->io_addr); |
900 | ||
901 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
902 | ||
93116573 | 903 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 SH |
904 | |
905 | /* Packet Status check */ | |
906 | if (RxLen < 0x40) { | |
6478fac6 | 907 | GoodPacket = false; |
a76836f9 | 908 | dev_dbg(db->dev, "Bad Packet received (runt)\n"); |
a1365275 SH |
909 | } |
910 | ||
911 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 912 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
913 | } |
914 | ||
93116573 | 915 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 916 | GoodPacket = false; |
93116573 | 917 | if (rxhdr.RxStatus & 0x01) { |
a76836f9 | 918 | dev_dbg(db->dev, "fifo error\n"); |
09f75cd7 | 919 | dev->stats.rx_fifo_errors++; |
a1365275 | 920 | } |
93116573 | 921 | if (rxhdr.RxStatus & 0x02) { |
a76836f9 | 922 | dev_dbg(db->dev, "crc error\n"); |
09f75cd7 | 923 | dev->stats.rx_crc_errors++; |
a1365275 | 924 | } |
93116573 | 925 | if (rxhdr.RxStatus & 0x80) { |
a76836f9 | 926 | dev_dbg(db->dev, "length error\n"); |
09f75cd7 | 927 | dev->stats.rx_length_errors++; |
a1365275 SH |
928 | } |
929 | } | |
930 | ||
931 | /* Move data from DM9000 */ | |
932 | if (GoodPacket | |
933 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
934 | skb_reserve(skb, 2); |
935 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
936 | ||
937 | /* Read received packet from RX SRAM */ | |
938 | ||
939 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 940 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
941 | |
942 | /* Pass to upper layer */ | |
943 | skb->protocol = eth_type_trans(skb, dev); | |
944 | netif_rx(skb); | |
09f75cd7 | 945 | dev->stats.rx_packets++; |
a1365275 SH |
946 | |
947 | } else { | |
948 | /* need to dump the packet's data */ | |
949 | ||
950 | (db->dumpblk)(db->io_data, RxLen); | |
951 | } | |
952 | } while (rxbyte == DM9000_PKT_RDY); | |
953 | } | |
954 | ||
955 | /* | |
956 | * Read a word data from SROM | |
957 | */ | |
958 | static u16 | |
959 | read_srom_word(board_info_t * db, int offset) | |
960 | { | |
961 | iow(db, DM9000_EPAR, offset); | |
962 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
963 | mdelay(8); /* according to the datasheet 200us should be enough, | |
964 | but it doesn't work */ | |
965 | iow(db, DM9000_EPCR, 0x0); | |
966 | return (ior(db, DM9000_EPDRL) + (ior(db, DM9000_EPDRH) << 8)); | |
967 | } | |
968 | ||
969 | #ifdef DM9000_PROGRAM_EEPROM | |
970 | /* | |
971 | * Write a word data to SROM | |
972 | */ | |
973 | static void | |
974 | write_srom_word(board_info_t * db, int offset, u16 val) | |
975 | { | |
976 | iow(db, DM9000_EPAR, offset); | |
977 | iow(db, DM9000_EPDRH, ((val >> 8) & 0xff)); | |
978 | iow(db, DM9000_EPDRL, (val & 0xff)); | |
979 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); | |
980 | mdelay(8); /* same shit */ | |
981 | iow(db, DM9000_EPCR, 0); | |
982 | } | |
983 | ||
984 | /* | |
985 | * Only for development: | |
986 | * Here we write static data to the eeprom in case | |
987 | * we don't have valid content on a new board | |
988 | */ | |
989 | static void | |
990 | program_eeprom(board_info_t * db) | |
991 | { | |
992 | u16 eeprom[] = { 0x0c00, 0x007f, 0x1300, /* MAC Address */ | |
993 | 0x0000, /* Autoload: accept nothing */ | |
994 | 0x0a46, 0x9000, /* Vendor / Product ID */ | |
995 | 0x0000, /* pin control */ | |
996 | 0x0000, | |
997 | }; /* Wake-up mode control */ | |
998 | int i; | |
999 | for (i = 0; i < 8; i++) | |
1000 | write_srom_word(db, i, eeprom[i]); | |
1001 | } | |
1002 | #endif | |
1003 | ||
1004 | ||
1005 | /* | |
1006 | * Calculate the CRC valude of the Rx packet | |
1007 | * flag = 1 : return the reverse CRC (for the received packet CRC) | |
1008 | * 0 : return the normal CRC (for Hash Table index) | |
1009 | */ | |
1010 | ||
1011 | static unsigned long | |
1012 | cal_CRC(unsigned char *Data, unsigned int Len, u8 flag) | |
1013 | { | |
1014 | ||
1015 | u32 crc = ether_crc_le(Len, Data); | |
1016 | ||
1017 | if (flag) | |
1018 | return ~crc; | |
1019 | ||
1020 | return crc; | |
1021 | } | |
1022 | ||
1023 | /* | |
1024 | * Set DM9000 multicast address | |
1025 | */ | |
1026 | static void | |
1027 | dm9000_hash_table(struct net_device *dev) | |
1028 | { | |
1029 | board_info_t *db = (board_info_t *) dev->priv; | |
1030 | struct dev_mc_list *mcptr = dev->mc_list; | |
1031 | int mc_cnt = dev->mc_count; | |
1032 | u32 hash_val; | |
1033 | u16 i, oft, hash_table[4]; | |
1034 | unsigned long flags; | |
1035 | ||
5b2b4ff0 | 1036 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 SH |
1037 | |
1038 | spin_lock_irqsave(&db->lock,flags); | |
1039 | ||
1040 | for (i = 0, oft = 0x10; i < 6; i++, oft++) | |
1041 | iow(db, oft, dev->dev_addr[i]); | |
1042 | ||
1043 | /* Clear Hash Table */ | |
1044 | for (i = 0; i < 4; i++) | |
1045 | hash_table[i] = 0x0; | |
1046 | ||
1047 | /* broadcast address */ | |
1048 | hash_table[3] = 0x8000; | |
1049 | ||
1050 | /* the multicast address in Hash Table : 64 bits */ | |
1051 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
1052 | hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f; | |
1053 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); | |
1054 | } | |
1055 | ||
1056 | /* Write the hash table to MAC MD table */ | |
1057 | for (i = 0, oft = 0x16; i < 4; i++) { | |
1058 | iow(db, oft++, hash_table[i] & 0xff); | |
1059 | iow(db, oft++, (hash_table[i] >> 8) & 0xff); | |
1060 | } | |
1061 | ||
1062 | spin_unlock_irqrestore(&db->lock,flags); | |
1063 | } | |
1064 | ||
1065 | ||
1066 | /* | |
1067 | * Read a word from phyxcer | |
1068 | */ | |
1069 | static int | |
1070 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
1071 | { | |
1072 | board_info_t *db = (board_info_t *) dev->priv; | |
1073 | unsigned long flags; | |
9ef9ac51 | 1074 | unsigned int reg_save; |
a1365275 SH |
1075 | int ret; |
1076 | ||
1077 | spin_lock_irqsave(&db->lock,flags); | |
9ef9ac51 BD |
1078 | |
1079 | /* Save previous register address */ | |
1080 | reg_save = readb(db->io_addr); | |
1081 | ||
a1365275 SH |
1082 | /* Fill the phyxcer register into REG_0C */ |
1083 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1084 | ||
1085 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ | |
1086 | udelay(100); /* Wait read complete */ | |
1087 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ | |
1088 | ||
1089 | /* The read data keeps on REG_0D & REG_0E */ | |
1090 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1091 | ||
9ef9ac51 BD |
1092 | /* restore the previous address */ |
1093 | writeb(reg_save, db->io_addr); | |
1094 | ||
a1365275 SH |
1095 | spin_unlock_irqrestore(&db->lock,flags); |
1096 | ||
1097 | return ret; | |
1098 | } | |
1099 | ||
1100 | /* | |
1101 | * Write a word to phyxcer | |
1102 | */ | |
1103 | static void | |
1104 | dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value) | |
1105 | { | |
1106 | board_info_t *db = (board_info_t *) dev->priv; | |
1107 | unsigned long flags; | |
9ef9ac51 | 1108 | unsigned long reg_save; |
a1365275 SH |
1109 | |
1110 | spin_lock_irqsave(&db->lock,flags); | |
1111 | ||
9ef9ac51 BD |
1112 | /* Save previous register address */ |
1113 | reg_save = readb(db->io_addr); | |
1114 | ||
a1365275 SH |
1115 | /* Fill the phyxcer register into REG_0C */ |
1116 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1117 | ||
1118 | /* Fill the written data into REG_0D & REG_0E */ | |
1119 | iow(db, DM9000_EPDRL, (value & 0xff)); | |
1120 | iow(db, DM9000_EPDRH, ((value >> 8) & 0xff)); | |
1121 | ||
1122 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
1123 | udelay(500); /* Wait write complete */ | |
1124 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ | |
1125 | ||
9ef9ac51 BD |
1126 | /* restore the previous address */ |
1127 | writeb(reg_save, db->io_addr); | |
1128 | ||
a1365275 SH |
1129 | spin_unlock_irqrestore(&db->lock,flags); |
1130 | } | |
1131 | ||
1132 | static int | |
3ae5eaec | 1133 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1134 | { |
3ae5eaec | 1135 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 | 1136 | |
9480e307 | 1137 | if (ndev) { |
a1365275 SH |
1138 | if (netif_running(ndev)) { |
1139 | netif_device_detach(ndev); | |
1140 | dm9000_shutdown(ndev); | |
1141 | } | |
1142 | } | |
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | static int | |
3ae5eaec | 1147 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1148 | { |
3ae5eaec | 1149 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1150 | board_info_t *db = (board_info_t *) ndev->priv; |
1151 | ||
9480e307 | 1152 | if (ndev) { |
a1365275 SH |
1153 | |
1154 | if (netif_running(ndev)) { | |
1155 | dm9000_reset(db); | |
1156 | dm9000_init_dm9000(ndev); | |
1157 | ||
1158 | netif_device_attach(ndev); | |
1159 | } | |
1160 | } | |
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | static int | |
3ae5eaec | 1165 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1166 | { |
3ae5eaec | 1167 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1168 | |
3ae5eaec | 1169 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1170 | |
1171 | unregister_netdev(ndev); | |
1172 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1173 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1174 | |
a76836f9 | 1175 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1176 | return 0; |
1177 | } | |
1178 | ||
3ae5eaec | 1179 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1180 | .driver = { |
1181 | .name = "dm9000", | |
1182 | .owner = THIS_MODULE, | |
1183 | }, | |
a1365275 SH |
1184 | .probe = dm9000_probe, |
1185 | .remove = dm9000_drv_remove, | |
1186 | .suspend = dm9000_drv_suspend, | |
1187 | .resume = dm9000_drv_resume, | |
1188 | }; | |
1189 | ||
1190 | static int __init | |
1191 | dm9000_init(void) | |
1192 | { | |
2ae2d77c BD |
1193 | printk(KERN_INFO "%s Ethernet Driver\n", CARDNAME); |
1194 | ||
3ae5eaec | 1195 | return platform_driver_register(&dm9000_driver); /* search board and register */ |
a1365275 SH |
1196 | } |
1197 | ||
1198 | static void __exit | |
1199 | dm9000_cleanup(void) | |
1200 | { | |
3ae5eaec | 1201 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1202 | } |
1203 | ||
1204 | module_init(dm9000_init); | |
1205 | module_exit(dm9000_cleanup); | |
1206 | ||
1207 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1208 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1209 | MODULE_LICENSE("GPL"); |