[net-next-2.6.git] / drivers / net / depca.h

/*
    Written 1994 by David C. Davies.

    Copyright 1994 David C. Davies. This software may be used and distributed
    according to the terms of the GNU General Public License, incorporated herein by
    reference.
*/

/*
** I/O addresses. Note that the 2k buffer option is not supported in
** this driver.
*/
#define DEPCA_NICSR ioaddr+0x00   /* Network interface CSR */
#define DEPCA_RBI   ioaddr+0x02   /* RAM buffer index (2k buffer mode) */
#define DEPCA_DATA  ioaddr+0x04   /* LANCE registers' data port */
#define DEPCA_ADDR  ioaddr+0x06   /* LANCE registers' address port */
#define DEPCA_HBASE ioaddr+0x08   /* EISA high memory base address reg. */
#define DEPCA_PROM  ioaddr+0x0c   /* Ethernet address ROM data port */
#define DEPCA_CNFG  ioaddr+0x0c   /* EISA Configuration port */
#define DEPCA_RBSA  ioaddr+0x0e   /* RAM buffer starting address (2k buff.) */

/*
** These are LANCE registers addressable through DEPCA_ADDR
*/
#define CSR0       0
#define CSR1       1
#define CSR2       2
#define CSR3       3

/*
** NETWORK INTERFACE CSR (NI_CSR) bit definitions
*/

#define TO       	0x0100	/* Time Out for remote boot */
#define SHE      	0x0080  /* SHadow memory Enable */
#define BS       	0x0040  /* Bank Select */
#define BUF      	0x0020	/* BUFfer size (1->32k, 0->64k) */
#define RBE      	0x0010	/* Remote Boot Enable (1->net boot) */
#define AAC      	0x0008  /* Address ROM Address Counter (1->enable) */
#define _128KB      	0x0008  /* 128kB Network RAM (1->enable) */
#define IM       	0x0004	/* Interrupt Mask (1->mask) */
#define IEN      	0x0002	/* Interrupt tristate ENable (1->enable) */
#define LED      	0x0001	/* LED control */

/*
** Control and Status Register 0 (CSR0) bit definitions
*/

#define ERR     	0x8000 	/* Error summary */
#define BABL    	0x4000 	/* Babble transmitter timeout error  */
#define CERR    	0x2000 	/* Collision Error */
#define MISS    	0x1000 	/* Missed packet */
#define MERR    	0x0800 	/* Memory Error */
#define RINT    	0x0400 	/* Receiver Interrupt */
#define TINT    	0x0200 	/* Transmit Interrupt */
#define IDON    	0x0100 	/* Initialization Done */
#define INTR    	0x0080 	/* Interrupt Flag */
#define INEA    	0x0040 	/* Interrupt Enable */
#define RXON    	0x0020 	/* Receiver on */
#define TXON    	0x0010 	/* Transmitter on */
#define TDMD    	0x0008 	/* Transmit Demand */
#define STOP    	0x0004 	/* Stop */
#define STRT    	0x0002 	/* Start */
#define INIT    	0x0001 	/* Initialize */
#define INTM            0xff00  /* Interrupt Mask */
#define INTE            0xfff0  /* Interrupt Enable */

/*
** CONTROL AND STATUS REGISTER 3 (CSR3)
*/

#define BSWP    	0x0004	/* Byte SWaP */
#define ACON    	0x0002	/* ALE control */
#define BCON    	0x0001	/* Byte CONtrol */

/*
** Initialization Block Mode Register
*/

#define PROM       	0x8000 	/* Promiscuous Mode */
#define EMBA       	0x0080	/* Enable Modified Back-off Algorithm */
#define INTL       	0x0040 	/* Internal Loopback */
#define DRTY       	0x0020 	/* Disable Retry */
#define COLL       	0x0010 	/* Force Collision */
#define DTCR       	0x0008 	/* Disable Transmit CRC */
#define LOOP       	0x0004 	/* Loopback */
#define DTX        	0x0002 	/* Disable the Transmitter */
#define DRX        	0x0001 	/* Disable the Receiver */

/*
** Receive Message Descriptor 1 (RMD1) bit definitions.
*/

#define R_OWN       0x80000000 	/* Owner bit 0 = host, 1 = lance */
#define R_ERR     	0x4000 	/* Error Summary */
#define R_FRAM    	0x2000 	/* Framing Error */
#define R_OFLO    	0x1000 	/* Overflow Error */
#define R_CRC     	0x0800 	/* CRC Error */
#define R_BUFF    	0x0400 	/* Buffer Error */
#define R_STP     	0x0200 	/* Start of Packet */
#define R_ENP     	0x0100 	/* End of Packet */

/*
** Transmit Message Descriptor 1 (TMD1) bit definitions.
*/

#define T_OWN       0x80000000 	/* Owner bit 0 = host, 1 = lance */
#define T_ERR     	0x4000 	/* Error Summary */
#define T_ADD_FCS 	0x2000 	/* More the 1 retry needed to Xmit */
#define T_MORE    	0x1000	/* >1 retry to transmit packet */
#define T_ONE     	0x0800 	/* 1 try needed to transmit the packet */
#define T_DEF     	0x0400 	/* Deferred */
#define T_STP       0x02000000 	/* Start of Packet */
#define T_ENP       0x01000000	/* End of Packet */
#define T_FLAGS     0xff000000  /* TX Flags Field */

/*
** Transmit Message Descriptor 3 (TMD3) bit definitions.
*/

#define TMD3_BUFF    0x8000	/* BUFFer error */
#define TMD3_UFLO    0x4000	/* UnderFLOw error */
#define TMD3_RES     0x2000	/* REServed */
#define TMD3_LCOL    0x1000	/* Late COLlision */
#define TMD3_LCAR    0x0800	/* Loss of CARrier */
#define TMD3_RTRY    0x0400	/* ReTRY error */

/*
** EISA configuration Register (CNFG) bit definitions
*/

#define TIMEOUT       	0x0100	/* 0:2.5 mins, 1: 30 secs */
#define REMOTE      	0x0080  /* Remote Boot Enable -> 1 */
#define IRQ11       	0x0040  /* Enable -> 1 */
#define IRQ10    	0x0020	/* Enable -> 1 */
#define IRQ9    	0x0010	/* Enable -> 1 */
#define IRQ5      	0x0008  /* Enable -> 1 */
#define BUFF     	0x0004	/* 0: 64kB or 128kB, 1: 32kB */
#define PADR16   	0x0002	/* RAM on 64kB boundary */
#define PADR17    	0x0001	/* RAM on 128kB boundary */

/*
** Miscellaneous
*/
#define HASH_TABLE_LEN   64           /* Bits */
#define HASH_BITS        0x003f       /* 6 LS bits */

#define MASK_INTERRUPTS   1
#define UNMASK_INTERRUPTS 0

#define EISA_EN         0x0001        /* Enable EISA bus buffers */
#define EISA_ID         iobase+0x0080 /* ID long word for EISA card */
#define EISA_CTRL       iobase+0x0084 /* Control word for EISA card */

/*
** Include the IOCTL stuff
*/
#include <linux/sockios.h>

#define	DEPCAIOCTL	SIOCDEVPRIVATE

struct depca_ioctl {
	unsigned short cmd;                /* Command to run */
	unsigned short len;                /* Length of the data buffer */
	unsigned char  __user *data;       /* Pointer to the data buffer */
};

/*
** Recognised commands for the driver
*/
#define DEPCA_GET_HWADDR	0x01 /* Get the hardware address */
#define DEPCA_SET_HWADDR	0x02 /* Get the hardware address */
#define DEPCA_SET_PROM  	0x03 /* Set Promiscuous Mode */
#define DEPCA_CLR_PROM  	0x04 /* Clear Promiscuous Mode */
#define DEPCA_SAY_BOO	        0x05 /* Say "Boo!" to the kernel log file */
#define DEPCA_GET_MCA   	0x06 /* Get a multicast address */
#define DEPCA_SET_MCA   	0x07 /* Set a multicast address */
#define DEPCA_CLR_MCA    	0x08 /* Clear a multicast address */
#define DEPCA_MCA_EN    	0x09 /* Enable a multicast address group */
#define DEPCA_GET_STATS  	0x0a /* Get the driver statistics */
#define DEPCA_CLR_STATS 	0x0b /* Zero out the driver statistics */
#define DEPCA_GET_REG   	0x0c /* Get the Register contents */
#define DEPCA_SET_REG   	0x0d /* Set the Register contents */
#define DEPCA_DUMP              0x0f /* Dump the DEPCA Status */
Commit	Line	Data
1da177e4 LT	1	/*
	2	Written 1994 by David C. Davies.
	3
	4	Copyright 1994 David C. Davies. This software may be used and distributed
	5	according to the terms of the GNU General Public License, incorporated herein by
	6	reference.
	7	*/
	8
	9	/*
	10	** I/O addresses. Note that the 2k buffer option is not supported in
	11	** this driver.
	12	*/
	13	#define DEPCA_NICSR ioaddr+0x00 /* Network interface CSR */
	14	#define DEPCA_RBI ioaddr+0x02 /* RAM buffer index (2k buffer mode) */
	15	#define DEPCA_DATA ioaddr+0x04 /* LANCE registers' data port */
	16	#define DEPCA_ADDR ioaddr+0x06 /* LANCE registers' address port */
	17	#define DEPCA_HBASE ioaddr+0x08 /* EISA high memory base address reg. */
	18	#define DEPCA_PROM ioaddr+0x0c /* Ethernet address ROM data port */
	19	#define DEPCA_CNFG ioaddr+0x0c /* EISA Configuration port */
	20	#define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */
	21
	22	/*
6aa20a22	23	** These are LANCE registers addressable through DEPCA_ADDR
1da177e4 LT	24	*/
	25	#define CSR0 0
	26	#define CSR1 1
	27	#define CSR2 2
	28	#define CSR3 3
	29
6aa20a22 JG	30	/*
6aa20a22 JG	31	** NETWORK INTERFACE CSR (NI_CSR) bit definitions
1da177e4	32	*/
6aa20a22	33
1da177e4 LT	34	#define TO 0x0100 /* Time Out for remote boot */
	35	#define SHE 0x0080 /* SHadow memory Enable */
	36	#define BS 0x0040 /* Bank Select */
	37	#define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */
	38	#define RBE 0x0010 /* Remote Boot Enable (1->net boot) */
	39	#define AAC 0x0008 /* Address ROM Address Counter (1->enable) */
	40	#define _128KB 0x0008 /* 128kB Network RAM (1->enable) */
	41	#define IM 0x0004 /* Interrupt Mask (1->mask) */
	42	#define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */
	43	#define LED 0x0001 /* LED control */
	44
6aa20a22 JG	45	/*
6aa20a22 JG	46	** Control and Status Register 0 (CSR0) bit definitions
1da177e4 LT	47	*/
	48
	49	#define ERR 0x8000 /* Error summary */
	50	#define BABL 0x4000 /* Babble transmitter timeout error */
	51	#define CERR 0x2000 /* Collision Error */
	52	#define MISS 0x1000 /* Missed packet */
	53	#define MERR 0x0800 /* Memory Error */
	54	#define RINT 0x0400 /* Receiver Interrupt */
	55	#define TINT 0x0200 /* Transmit Interrupt */
	56	#define IDON 0x0100 /* Initialization Done */
	57	#define INTR 0x0080 /* Interrupt Flag */
	58	#define INEA 0x0040 /* Interrupt Enable */
	59	#define RXON 0x0020 /* Receiver on */
	60	#define TXON 0x0010 /* Transmitter on */
	61	#define TDMD 0x0008 /* Transmit Demand */
	62	#define STOP 0x0004 /* Stop */
	63	#define STRT 0x0002 /* Start */
	64	#define INIT 0x0001 /* Initialize */
	65	#define INTM 0xff00 /* Interrupt Mask */
	66	#define INTE 0xfff0 /* Interrupt Enable */
	67
	68	/*
	69	** CONTROL AND STATUS REGISTER 3 (CSR3)
	70	*/
	71
	72	#define BSWP 0x0004 /* Byte SWaP */
	73	#define ACON 0x0002 /* ALE control */
	74	#define BCON 0x0001 /* Byte CONtrol */
	75
	76	/*
6aa20a22	77	** Initialization Block Mode Register
1da177e4 LT	78	*/
	79
	80	#define PROM 0x8000 /* Promiscuous Mode */
	81	#define EMBA 0x0080 /* Enable Modified Back-off Algorithm */
	82	#define INTL 0x0040 /* Internal Loopback */
	83	#define DRTY 0x0020 /* Disable Retry */
	84	#define COLL 0x0010 /* Force Collision */
	85	#define DTCR 0x0008 /* Disable Transmit CRC */
	86	#define LOOP 0x0004 /* Loopback */
	87	#define DTX 0x0002 /* Disable the Transmitter */
	88	#define DRX 0x0001 /* Disable the Receiver */
	89
	90	/*
6aa20a22	91	** Receive Message Descriptor 1 (RMD1) bit definitions.
1da177e4 LT	92	*/
	93
	94	#define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
	95	#define R_ERR 0x4000 /* Error Summary */
	96	#define R_FRAM 0x2000 /* Framing Error */
	97	#define R_OFLO 0x1000 /* Overflow Error */
	98	#define R_CRC 0x0800 /* CRC Error */
	99	#define R_BUFF 0x0400 /* Buffer Error */
	100	#define R_STP 0x0200 /* Start of Packet */
	101	#define R_ENP 0x0100 /* End of Packet */
	102
	103	/*
6aa20a22	104	** Transmit Message Descriptor 1 (TMD1) bit definitions.
1da177e4 LT	105	*/
	106
	107	#define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
	108	#define T_ERR 0x4000 /* Error Summary */
	109	#define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */
	110	#define T_MORE 0x1000 /* >1 retry to transmit packet */
	111	#define T_ONE 0x0800 /* 1 try needed to transmit the packet */
	112	#define T_DEF 0x0400 /* Deferred */
	113	#define T_STP 0x02000000 /* Start of Packet */
	114	#define T_ENP 0x01000000 /* End of Packet */
	115	#define T_FLAGS 0xff000000 /* TX Flags Field */
	116
	117	/*
	118	** Transmit Message Descriptor 3 (TMD3) bit definitions.
	119	*/
	120
	121	#define TMD3_BUFF 0x8000 /* BUFFer error */
	122	#define TMD3_UFLO 0x4000 /* UnderFLOw error */
	123	#define TMD3_RES 0x2000 /* REServed */
	124	#define TMD3_LCOL 0x1000 /* Late COLlision */
	125	#define TMD3_LCAR 0x0800 /* Loss of CARrier */
	126	#define TMD3_RTRY 0x0400 /* ReTRY error */
	127
6aa20a22 JG	128	/*
6aa20a22 JG	129	** EISA configuration Register (CNFG) bit definitions
1da177e4	130	*/
6aa20a22	131
1da177e4 LT	132	#define TIMEOUT 0x0100 /* 0:2.5 mins, 1: 30 secs */
	133	#define REMOTE 0x0080 /* Remote Boot Enable -> 1 */
	134	#define IRQ11 0x0040 /* Enable -> 1 */
	135	#define IRQ10 0x0020 /* Enable -> 1 */
	136	#define IRQ9 0x0010 /* Enable -> 1 */
	137	#define IRQ5 0x0008 /* Enable -> 1 */
	138	#define BUFF 0x0004 /* 0: 64kB or 128kB, 1: 32kB */
	139	#define PADR16 0x0002 /* RAM on 64kB boundary */
	140	#define PADR17 0x0001 /* RAM on 128kB boundary */
	141
	142	/*
	143	** Miscellaneous
	144	*/
	145	#define HASH_TABLE_LEN 64 /* Bits */
	146	#define HASH_BITS 0x003f /* 6 LS bits */
	147
	148	#define MASK_INTERRUPTS 1
	149	#define UNMASK_INTERRUPTS 0
	150
	151	#define EISA_EN 0x0001 /* Enable EISA bus buffers */
	152	#define EISA_ID iobase+0x0080 /* ID long word for EISA card */
	153	#define EISA_CTRL iobase+0x0084 /* Control word for EISA card */
	154
	155	/*
	156	** Include the IOCTL stuff
	157	*/
	158	#include <linux/sockios.h>
	159
	160	#define DEPCAIOCTL SIOCDEVPRIVATE
	161
	162	struct depca_ioctl {
	163	unsigned short cmd; /* Command to run */
	164	unsigned short len; /* Length of the data buffer */
	165	unsigned char __user data; / Pointer to the data buffer */
	166	};
	167
6aa20a22 JG	168	/*
6aa20a22 JG	169	** Recognised commands for the driver
1da177e4 LT	170	*/
	171	#define DEPCA_GET_HWADDR 0x01 /* Get the hardware address */
	172	#define DEPCA_SET_HWADDR 0x02 /* Get the hardware address */
	173	#define DEPCA_SET_PROM 0x03 /* Set Promiscuous Mode */
	174	#define DEPCA_CLR_PROM 0x04 /* Clear Promiscuous Mode */
	175	#define DEPCA_SAY_BOO 0x05 /* Say "Boo!" to the kernel log file */
	176	#define DEPCA_GET_MCA 0x06 /* Get a multicast address */
	177	#define DEPCA_SET_MCA 0x07 /* Set a multicast address */
	178	#define DEPCA_CLR_MCA 0x08 /* Clear a multicast address */
	179	#define DEPCA_MCA_EN 0x09 /* Enable a multicast address group */
	180	#define DEPCA_GET_STATS 0x0a /* Get the driver statistics */
	181	#define DEPCA_CLR_STATS 0x0b /* Zero out the driver statistics */
	182	#define DEPCA_GET_REG 0x0c /* Get the Register contents */
	183	#define DEPCA_SET_REG 0x0d /* Set the Register contents */
	184	#define DEPCA_DUMP 0x0f /* Dump the DEPCA Status */
	185