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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / cxgb4 / t4fw_api.h
CommitLineData
bbc02c7e
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef _T4FW_INTERFACE_H_
36#define _T4FW_INTERFACE_H_
37
38#define FW_T4VF_SGE_BASE_ADDR 0x0000
39#define FW_T4VF_MPS_BASE_ADDR 0x0100
40#define FW_T4VF_PL_BASE_ADDR 0x0200
41#define FW_T4VF_MBDATA_BASE_ADDR 0x0240
42#define FW_T4VF_CIM_BASE_ADDR 0x0300
43
44enum fw_wr_opcodes {
45 FW_FILTER_WR = 0x02,
46 FW_ULPTX_WR = 0x04,
47 FW_TP_WR = 0x05,
48 FW_ETH_TX_PKT_WR = 0x08,
49 FW_FLOWC_WR = 0x0a,
50 FW_OFLD_TX_DATA_WR = 0x0b,
51 FW_CMD_WR = 0x10,
52 FW_ETH_TX_PKT_VM_WR = 0x11,
53 FW_RI_RES_WR = 0x0c,
54 FW_RI_INIT_WR = 0x0d,
55 FW_RI_RDMA_WRITE_WR = 0x14,
56 FW_RI_SEND_WR = 0x15,
57 FW_RI_RDMA_READ_WR = 0x16,
58 FW_RI_RECV_WR = 0x17,
59 FW_RI_BIND_MW_WR = 0x18,
60 FW_RI_FR_NSMR_WR = 0x19,
61 FW_RI_INV_LSTAG_WR = 0x1a,
62 FW_LASTC2E_WR = 0x40
63};
64
65struct fw_wr_hdr {
66 __be32 hi;
67 __be32 lo;
68};
69
70#define FW_WR_OP(x) ((x) << 24)
71#define FW_WR_ATOMIC(x) ((x) << 23)
72#define FW_WR_FLUSH(x) ((x) << 22)
73#define FW_WR_COMPL(x) ((x) << 21)
81323b74 74#define FW_WR_IMMDLEN_MASK 0xff
bbc02c7e
DM		 75#define FW_WR_IMMDLEN(x) ((x) << 0)
76
77#define FW_WR_EQUIQ (1U << 31)
78#define FW_WR_EQUEQ (1U << 30)
79#define FW_WR_FLOWID(x) ((x) << 8)
80#define FW_WR_LEN16(x) ((x) << 0)
81
82struct fw_ulptx_wr {
83 __be32 op_to_compl;
84 __be32 flowid_len16;
85 u64 cookie;
86};
87
88struct fw_tp_wr {
89 __be32 op_to_immdlen;
90 __be32 flowid_len16;
91 u64 cookie;
92};
93
94struct fw_eth_tx_pkt_wr {
95 __be32 op_immdlen;
96 __be32 equiq_to_len16;
97 __be64 r3;
98};
99
100enum fw_flowc_mnem {
101 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
102 FW_FLOWC_MNEM_CH,
103 FW_FLOWC_MNEM_PORT,
104 FW_FLOWC_MNEM_IQID,
105 FW_FLOWC_MNEM_SNDNXT,
106 FW_FLOWC_MNEM_RCVNXT,
107 FW_FLOWC_MNEM_SNDBUF,
108 FW_FLOWC_MNEM_MSS,
109};
110
111struct fw_flowc_mnemval {
112 u8 mnemonic;
113 u8 r4[3];
114 __be32 val;
115};
116
117struct fw_flowc_wr {
118 __be32 op_to_nparams;
119#define FW_FLOWC_WR_NPARAMS(x) ((x) << 0)
120 __be32 flowid_len16;
121 struct fw_flowc_mnemval mnemval[0];
122};
123
124struct fw_ofld_tx_data_wr {
125 __be32 op_to_immdlen;
126 __be32 flowid_len16;
127 __be32 plen;
128 __be32 tunnel_to_proxy;
129#define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19)
130#define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18)
131#define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17)
132#define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16)
133#define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15)
134#define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14)
135#define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10)
136#define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
137};
138
139struct fw_cmd_wr {
140 __be32 op_dma;
141#define FW_CMD_WR_DMA (1U << 17)
142 __be32 len16_pkd;
143 __be64 cookie_daddr;
144};
145
146struct fw_eth_tx_pkt_vm_wr {
147 __be32 op_immdlen;
148 __be32 equiq_to_len16;
149 __be32 r3[2];
150 u8 ethmacdst[6];
151 u8 ethmacsrc[6];
152 __be16 ethtype;
153 __be16 vlantci;
154};
155
156#define FW_CMD_MAX_TIMEOUT 3000
157
158enum fw_cmd_opcodes {
159 FW_LDST_CMD = 0x01,
160 FW_RESET_CMD = 0x03,
161 FW_HELLO_CMD = 0x04,
162 FW_BYE_CMD = 0x05,
163 FW_INITIALIZE_CMD = 0x06,
164 FW_CAPS_CONFIG_CMD = 0x07,
165 FW_PARAMS_CMD = 0x08,
166 FW_PFVF_CMD = 0x09,
167 FW_IQ_CMD = 0x10,
168 FW_EQ_MNGT_CMD = 0x11,
169 FW_EQ_ETH_CMD = 0x12,
170 FW_EQ_CTRL_CMD = 0x13,
171 FW_EQ_OFLD_CMD = 0x21,
172 FW_VI_CMD = 0x14,
173 FW_VI_MAC_CMD = 0x15,
174 FW_VI_RXMODE_CMD = 0x16,
175 FW_VI_ENABLE_CMD = 0x17,
176 FW_ACL_MAC_CMD = 0x18,
177 FW_ACL_VLAN_CMD = 0x19,
178 FW_VI_STATS_CMD = 0x1a,
179 FW_PORT_CMD = 0x1b,
180 FW_PORT_STATS_CMD = 0x1c,
181 FW_PORT_LB_STATS_CMD = 0x1d,
182 FW_PORT_TRACE_CMD = 0x1e,
183 FW_PORT_TRACE_MMAP_CMD = 0x1f,
184 FW_RSS_IND_TBL_CMD = 0x20,
185 FW_RSS_GLB_CONFIG_CMD = 0x22,
186 FW_RSS_VI_CONFIG_CMD = 0x23,
187 FW_LASTC2E_CMD = 0x40,
188 FW_ERROR_CMD = 0x80,
189 FW_DEBUG_CMD = 0x81,
190};
191
192enum fw_cmd_cap {
193 FW_CMD_CAP_PF = 0x01,
194 FW_CMD_CAP_DMAQ = 0x02,
195 FW_CMD_CAP_PORT = 0x04,
196 FW_CMD_CAP_PORTPROMISC = 0x08,
197 FW_CMD_CAP_PORTSTATS = 0x10,
198 FW_CMD_CAP_VF = 0x80,
199};
200
201/*
202 * Generic command header flit0
203 */
204struct fw_cmd_hdr {
205 __be32 hi;
206 __be32 lo;
207};
208
209#define FW_CMD_OP(x) ((x) << 24)
210#define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff)
211#define FW_CMD_REQUEST (1U << 23)
212#define FW_CMD_READ (1U << 22)
213#define FW_CMD_WRITE (1U << 21)
214#define FW_CMD_EXEC (1U << 20)
215#define FW_CMD_RAMASK(x) ((x) << 20)
216#define FW_CMD_RETVAL(x) ((x) << 8)
217#define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff)
218#define FW_CMD_LEN16(x) ((x) << 0)
219
220enum fw_ldst_addrspc {
221 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
222 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
223 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
224 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
225 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
226 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
227 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
228 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
229 FW_LDST_ADDRSPC_MDIO = 0x0018,
230 FW_LDST_ADDRSPC_MPS = 0x0020,
231 FW_LDST_ADDRSPC_FUNC = 0x0028
232};
233
234enum fw_ldst_mps_fid {
235 FW_LDST_MPS_ATRB,
236 FW_LDST_MPS_RPLC
237};
238
239enum fw_ldst_func_access_ctl {
240 FW_LDST_FUNC_ACC_CTL_VIID,
241 FW_LDST_FUNC_ACC_CTL_FID
242};
243
244enum fw_ldst_func_mod_index {
245 FW_LDST_FUNC_MPS
246};
247
248struct fw_ldst_cmd {
249 __be32 op_to_addrspace;
250#define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
251 __be32 cycles_to_len16;
252 union fw_ldst {
253 struct fw_ldst_addrval {
254 __be32 addr;
255 __be32 val;
256 } addrval;
257 struct fw_ldst_idctxt {
258 __be32 physid;
259 __be32 msg_pkd;
260 __be32 ctxt_data7;
261 __be32 ctxt_data6;
262 __be32 ctxt_data5;
263 __be32 ctxt_data4;
264 __be32 ctxt_data3;
265 __be32 ctxt_data2;
266 __be32 ctxt_data1;
267 __be32 ctxt_data0;
268 } idctxt;
269 struct fw_ldst_mdio {
270 __be16 paddr_mmd;
271 __be16 raddr;
272 __be16 vctl;
273 __be16 rval;
274 } mdio;
275 struct fw_ldst_mps {
276 __be16 fid_ctl;
277 __be16 rplcpf_pkd;
278 __be32 rplc127_96;
279 __be32 rplc95_64;
280 __be32 rplc63_32;
281 __be32 rplc31_0;
282 __be32 atrb;
283 __be16 vlan[16];
284 } mps;
285 struct fw_ldst_func {
286 u8 access_ctl;
287 u8 mod_index;
288 __be16 ctl_id;
289 __be32 offset;
290 __be64 data0;
291 __be64 data1;
292 } func;
293 } u;
294};
295
296#define FW_LDST_CMD_MSG(x) ((x) << 31)
297#define FW_LDST_CMD_PADDR(x) ((x) << 8)
298#define FW_LDST_CMD_MMD(x) ((x) << 0)
299#define FW_LDST_CMD_FID(x) ((x) << 15)
300#define FW_LDST_CMD_CTL(x) ((x) << 0)
301#define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
302
303struct fw_reset_cmd {
304 __be32 op_to_write;
305 __be32 retval_len16;
306 __be32 val;
307 __be32 r3;
308};
309
310struct fw_hello_cmd {
311 __be32 op_to_write;
312 __be32 retval_len16;
313 __be32 err_to_mbasyncnot;
314#define FW_HELLO_CMD_ERR (1U << 31)
315#define FW_HELLO_CMD_INIT (1U << 30)
316#define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
317#define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
318#define FW_HELLO_CMD_MBMASTER(x) ((x) << 24)
319#define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
320 __be32 fwrev;
321};
322
323struct fw_bye_cmd {
324 __be32 op_to_write;
325 __be32 retval_len16;
326 __be64 r3;
327};
328
329struct fw_initialize_cmd {
330 __be32 op_to_write;
331 __be32 retval_len16;
332 __be64 r3;
333};
334
335enum fw_caps_config_hm {
336 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
337 FW_CAPS_CONFIG_HM_PL = 0x00000002,
338 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
339 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
340 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
341 FW_CAPS_CONFIG_HM_TP = 0x00000020,
342 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
343 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
344 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
345 FW_CAPS_CONFIG_HM_MC = 0x00000200,
346 FW_CAPS_CONFIG_HM_LE = 0x00000400,
347 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
348 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
349 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
350 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
351 FW_CAPS_CONFIG_HM_MI = 0x00008000,
352 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
353 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
354 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
355 FW_CAPS_CONFIG_HM_MA = 0x00080000,
356 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
357 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
358 FW_CAPS_CONFIG_HM_UART = 0x00400000,
359 FW_CAPS_CONFIG_HM_SF = 0x00800000,
360};
361
362enum fw_caps_config_nbm {
363 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
364 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
365};
366
367enum fw_caps_config_link {
368 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
369 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
370 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
371};
372
373enum fw_caps_config_switch {
374 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
375 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
376};
377
378enum fw_caps_config_nic {
379 FW_CAPS_CONFIG_NIC = 0x00000001,
380 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
381};
382
383enum fw_caps_config_ofld {
384 FW_CAPS_CONFIG_OFLD = 0x00000001,
385};
386
387enum fw_caps_config_rdma {
388 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
389 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
390};
391
392enum fw_caps_config_iscsi {
393 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
394 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
395 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
396 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
397};
398
399enum fw_caps_config_fcoe {
400 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
401 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
402};
403
404struct fw_caps_config_cmd {
405 __be32 op_to_write;
406 __be32 retval_len16;
407 __be32 r2;
408 __be32 hwmbitmap;
409 __be16 nbmcaps;
410 __be16 linkcaps;
411 __be16 switchcaps;
412 __be16 r3;
413 __be16 niccaps;
414 __be16 ofldcaps;
415 __be16 rdmacaps;
416 __be16 r4;
417 __be16 iscsicaps;
418 __be16 fcoecaps;
419 __be32 r5;
420 __be64 r6;
421};
422
423/*
424 * params command mnemonics
425 */
426enum fw_params_mnem {
427 FW_PARAMS_MNEM_DEV = 1, /* device params */
428 FW_PARAMS_MNEM_PFVF = 2, /* function params */
429 FW_PARAMS_MNEM_REG = 3, /* limited register access */
430 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
431 FW_PARAMS_MNEM_LAST
432};
433
434/*
435 * device parameters
436 */
437enum fw_params_param_dev {
438 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
439 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
440 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
441 * allocated by the device's
442 * Lookup Engine
443 */
444 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
445 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
446 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
447 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
448 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
449 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
450 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
81323b74
CL		 451 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
452 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
453 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
bbc02c7e
DM		 454};
455
456/*
457 * physical and virtual function parameters
458 */
459enum fw_params_param_pfvf {
460 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
461 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
462 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
463 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
464 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
465 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
466 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
467 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
468 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
469 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
470 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
471 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
472 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
473 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
474 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
475 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
476 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
477 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
478 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
479 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
480 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
a0881cab
DM		 481 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
482 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
483 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
484 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
bbc02c7e 485 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
a0881cab
DM		 486 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
487 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
1ae970e0
DM		 488 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
489 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
e46dab4d
DM		 490 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
491 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
492 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
493 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
494 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
bbc02c7e
DM		 495};
496
497/*
498 * dma queue parameters
499 */
500enum fw_params_param_dmaq {
501 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
502 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
503 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
504 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
505 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
506};
507
508#define FW_PARAMS_MNEM(x) ((x) << 24)
509#define FW_PARAMS_PARAM_X(x) ((x) << 16)
510#define FW_PARAMS_PARAM_Y(x) ((x) << 8)
511#define FW_PARAMS_PARAM_Z(x) ((x) << 0)
512#define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
513#define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
514
515struct fw_params_cmd {
516 __be32 op_to_vfn;
517 __be32 retval_len16;
518 struct fw_params_param {
519 __be32 mnem;
520 __be32 val;
521 } param[7];
522};
523
524#define FW_PARAMS_CMD_PFN(x) ((x) << 8)
525#define FW_PARAMS_CMD_VFN(x) ((x) << 0)
526
527struct fw_pfvf_cmd {
528 __be32 op_to_vfn;
529 __be32 retval_len16;
530 __be32 niqflint_niq;
81323b74 531 __be32 type_to_neq;
bbc02c7e
DM		 532 __be32 tc_to_nexactf;
533 __be32 r_caps_to_nethctrl;
534 __be16 nricq;
535 __be16 nriqp;
536 __be32 r4;
537};
538
539#define FW_PFVF_CMD_PFN(x) ((x) << 8)
540#define FW_PFVF_CMD_VFN(x) ((x) << 0)
541
542#define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
543#define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
544
545#define FW_PFVF_CMD_NIQ(x) ((x) << 0)
546#define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
547
81323b74
CL		 548#define FW_PFVF_CMD_TYPE (1 << 31)
549#define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1)
550
bbc02c7e 551#define FW_PFVF_CMD_CMASK(x) ((x) << 24)
81323b74
CL		 552#define FW_PFVF_CMD_CMASK_MASK 0xf
553#define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK)
bbc02c7e
DM		 554
555#define FW_PFVF_CMD_PMASK(x) ((x) << 20)
81323b74
CL		 556#define FW_PFVF_CMD_PMASK_MASK 0xf
557#define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK)
bbc02c7e
DM		 558
559#define FW_PFVF_CMD_NEQ(x) ((x) << 0)
560#define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
561
562#define FW_PFVF_CMD_TC(x) ((x) << 24)
563#define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
564
565#define FW_PFVF_CMD_NVI(x) ((x) << 16)
566#define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
567
568#define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
569#define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
570
571#define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
572#define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
573
574#define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
575#define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
576
577#define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
578#define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
579
580enum fw_iq_type {
581 FW_IQ_TYPE_FL_INT_CAP,
582 FW_IQ_TYPE_NO_FL_INT_CAP
583};
584
585struct fw_iq_cmd {
586 __be32 op_to_vfn;
587 __be32 alloc_to_len16;
588 __be16 physiqid;
589 __be16 iqid;
590 __be16 fl0id;
591 __be16 fl1id;
592 __be32 type_to_iqandstindex;
593 __be16 iqdroprss_to_iqesize;
594 __be16 iqsize;
595 __be64 iqaddr;
596 __be32 iqns_to_fl0congen;
597 __be16 fl0dcaen_to_fl0cidxfthresh;
598 __be16 fl0size;
599 __be64 fl0addr;
600 __be32 fl1cngchmap_to_fl1congen;
601 __be16 fl1dcaen_to_fl1cidxfthresh;
602 __be16 fl1size;
603 __be64 fl1addr;
604};
605
606#define FW_IQ_CMD_PFN(x) ((x) << 8)
607#define FW_IQ_CMD_VFN(x) ((x) << 0)
608
609#define FW_IQ_CMD_ALLOC (1U << 31)
610#define FW_IQ_CMD_FREE (1U << 30)
611#define FW_IQ_CMD_MODIFY (1U << 29)
612#define FW_IQ_CMD_IQSTART(x) ((x) << 28)
613#define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
614
615#define FW_IQ_CMD_TYPE(x) ((x) << 29)
616#define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
617#define FW_IQ_CMD_VIID(x) ((x) << 16)
618#define FW_IQ_CMD_IQANDST(x) ((x) << 15)
619#define FW_IQ_CMD_IQANUS(x) ((x) << 14)
620#define FW_IQ_CMD_IQANUD(x) ((x) << 12)
621#define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
622
623#define FW_IQ_CMD_IQDROPRSS (1U << 15)
624#define FW_IQ_CMD_IQGTSMODE (1U << 14)
625#define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
626#define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
627#define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
628#define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
629#define FW_IQ_CMD_IQO (1U << 3)
630#define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
631#define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
632
633#define FW_IQ_CMD_IQNS(x) ((x) << 31)
634#define FW_IQ_CMD_IQRO(x) ((x) << 30)
635#define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
636#define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
637#define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
638#define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
639#define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
640#define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
641#define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
642#define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
643#define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
644#define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
645#define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
646#define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
647#define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
648#define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
649#define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
650#define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
651#define FW_IQ_CMD_FL0PADEN (1U << 2)
652#define FW_IQ_CMD_FL0PACKEN (1U << 1)
653#define FW_IQ_CMD_FL0CONGEN (1U << 0)
654
655#define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
656#define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
657#define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
658#define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
659#define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
660#define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
661
662#define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
663#define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
664#define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
665#define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
666#define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
667#define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
668#define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
669#define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
670#define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
671#define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
672#define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
673#define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
674#define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
675#define FW_IQ_CMD_FL1PADEN (1U << 2)
676#define FW_IQ_CMD_FL1PACKEN (1U << 1)
677#define FW_IQ_CMD_FL1CONGEN (1U << 0)
678
679#define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
680#define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
681#define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
682#define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
683#define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
684#define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
685
686struct fw_eq_eth_cmd {
687 __be32 op_to_vfn;
688 __be32 alloc_to_len16;
689 __be32 eqid_pkd;
690 __be32 physeqid_pkd;
691 __be32 fetchszm_to_iqid;
692 __be32 dcaen_to_eqsize;
693 __be64 eqaddr;
694 __be32 viid_pkd;
695 __be32 r8_lo;
696 __be64 r9;
697};
698
699#define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
700#define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
701#define FW_EQ_ETH_CMD_ALLOC (1U << 31)
702#define FW_EQ_ETH_CMD_FREE (1U << 30)
703#define FW_EQ_ETH_CMD_MODIFY (1U << 29)
704#define FW_EQ_ETH_CMD_EQSTART (1U << 28)
705#define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
706
707#define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
708#define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
709#define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
81323b74 710#define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
bbc02c7e
DM		 711
712#define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
713#define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
714#define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
715#define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
716#define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
717#define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
718#define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
719#define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
720#define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
721#define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
722
723#define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
724#define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
725#define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
726#define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
727#define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
728#define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
729#define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
730
731#define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
732
733struct fw_eq_ctrl_cmd {
734 __be32 op_to_vfn;
735 __be32 alloc_to_len16;
736 __be32 cmpliqid_eqid;
737 __be32 physeqid_pkd;
738 __be32 fetchszm_to_iqid;
739 __be32 dcaen_to_eqsize;
740 __be64 eqaddr;
741};
742
743#define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
744#define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
745
746#define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
747#define FW_EQ_CTRL_CMD_FREE (1U << 30)
748#define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
749#define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
750#define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
751
752#define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
753#define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
754#define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
755#define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
756
757#define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
758#define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
759#define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
760#define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
761#define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
762#define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
763#define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
764#define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
765#define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
766#define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
767
768#define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
769#define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
770#define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
771#define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
772#define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
773#define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
774#define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
775
776struct fw_eq_ofld_cmd {
777 __be32 op_to_vfn;
778 __be32 alloc_to_len16;
779 __be32 eqid_pkd;
780 __be32 physeqid_pkd;
781 __be32 fetchszm_to_iqid;
782 __be32 dcaen_to_eqsize;
783 __be64 eqaddr;
784};
785
786#define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
787#define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
788
789#define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
790#define FW_EQ_OFLD_CMD_FREE (1U << 30)
791#define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
792#define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
793#define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
794
795#define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
796#define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
797#define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
798
799#define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
800#define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
801#define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
802#define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
803#define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
804#define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
805#define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
806#define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
807#define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
808#define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
809
810#define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
811#define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
812#define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
813#define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
814#define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
815#define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
816#define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
817
818/*
819 * Macros for VIID parsing:
820 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
821 */
822#define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
823#define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
824#define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
825
826struct fw_vi_cmd {
827 __be32 op_to_vfn;
828 __be32 alloc_to_len16;
a0881cab 829 __be16 type_viid;
bbc02c7e
DM		 830 u8 mac[6];
831 u8 portid_pkd;
832 u8 nmac;
833 u8 nmac0[6];
834 __be16 rsssize_pkd;
835 u8 nmac1[6];
a0881cab 836 __be16 idsiiq_pkd;
bbc02c7e 837 u8 nmac2[6];
a0881cab 838 __be16 idseiq_pkd;
bbc02c7e
DM		 839 u8 nmac3[6];
840 __be64 r9;
841 __be64 r10;
842};
843
844#define FW_VI_CMD_PFN(x) ((x) << 8)
845#define FW_VI_CMD_VFN(x) ((x) << 0)
846#define FW_VI_CMD_ALLOC (1U << 31)
847#define FW_VI_CMD_FREE (1U << 30)
848#define FW_VI_CMD_VIID(x) ((x) << 0)
a0881cab 849#define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
bbc02c7e 850#define FW_VI_CMD_PORTID(x) ((x) << 4)
81323b74 851#define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
bbc02c7e
DM		 852#define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
853
854/* Special VI_MAC command index ids */
855#define FW_VI_MAC_ADD_MAC 0x3FF
856#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
857#define FW_VI_MAC_MAC_BASED_FREE 0x3FD
81323b74 858#define FW_CLS_TCAM_NUM_ENTRIES 336
bbc02c7e
DM		 859
860enum fw_vi_mac_smac {
861 FW_VI_MAC_MPS_TCAM_ENTRY,
862 FW_VI_MAC_MPS_TCAM_ONLY,
863 FW_VI_MAC_SMT_ONLY,
864 FW_VI_MAC_SMT_AND_MPSTCAM
865};
866
867enum fw_vi_mac_result {
868 FW_VI_MAC_R_SUCCESS,
869 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
870 FW_VI_MAC_R_SMAC_FAIL,
871 FW_VI_MAC_R_F_ACL_CHECK
872};
873
874struct fw_vi_mac_cmd {
875 __be32 op_to_viid;
876 __be32 freemacs_to_len16;
877 union fw_vi_mac {
878 struct fw_vi_mac_exact {
879 __be16 valid_to_idx;
880 u8 macaddr[6];
881 } exact[7];
882 struct fw_vi_mac_hash {
883 __be64 hashvec;
884 } hash;
885 } u;
886};
887
888#define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
889#define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
890#define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
891#define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
892#define FW_VI_MAC_CMD_VALID (1U << 15)
893#define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
894#define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
895#define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
896#define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
897#define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
898
899#define FW_RXMODE_MTU_NO_CHG 65535
900
901struct fw_vi_rxmode_cmd {
902 __be32 op_to_viid;
903 __be32 retval_len16;
f8f5aafa 904 __be32 mtu_to_vlanexen;
bbc02c7e
DM		 905 __be32 r4_lo;
906};
907
908#define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
81323b74 909#define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
bbc02c7e
DM		 910#define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
911#define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
912#define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
913#define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
914#define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
915#define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
916#define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
f8f5aafa
DM		 917#define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
918#define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
bbc02c7e
DM		 919
920struct fw_vi_enable_cmd {
921 __be32 op_to_viid;
922 __be32 ien_to_len16;
923 __be16 blinkdur;
924 __be16 r3;
925 __be32 r4;
926};
927
928#define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
929#define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
930#define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
931#define FW_VI_ENABLE_CMD_LED (1U << 29)
932
933/* VI VF stats offset definitions */
934#define VI_VF_NUM_STATS 16
935enum fw_vi_stats_vf_index {
936 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
937 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
938 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
939 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
940 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
941 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
942 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
943 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
944 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
945 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
946 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
947 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
948 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
949 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
950 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
951 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
952};
953
954/* VI PF stats offset definitions */
955#define VI_PF_NUM_STATS 17
956enum fw_vi_stats_pf_index {
957 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
958 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
959 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
960 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
961 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
962 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
963 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
964 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
965 FW_VI_PF_STAT_RX_BYTES_IX,
966 FW_VI_PF_STAT_RX_FRAMES_IX,
967 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
968 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
969 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
970 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
971 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
972 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
973 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
974};
975
976struct fw_vi_stats_cmd {
977 __be32 op_to_viid;
978 __be32 retval_len16;
979 union fw_vi_stats {
980 struct fw_vi_stats_ctl {
981 __be16 nstats_ix;
982 __be16 r6;
983 __be32 r7;
984 __be64 stat0;
985 __be64 stat1;
986 __be64 stat2;
987 __be64 stat3;
988 __be64 stat4;
989 __be64 stat5;
990 } ctl;
991 struct fw_vi_stats_pf {
992 __be64 tx_bcast_bytes;
993 __be64 tx_bcast_frames;
994 __be64 tx_mcast_bytes;
995 __be64 tx_mcast_frames;
996 __be64 tx_ucast_bytes;
997 __be64 tx_ucast_frames;
998 __be64 tx_offload_bytes;
999 __be64 tx_offload_frames;
1000 __be64 rx_pf_bytes;
1001 __be64 rx_pf_frames;
1002 __be64 rx_bcast_bytes;
1003 __be64 rx_bcast_frames;
1004 __be64 rx_mcast_bytes;
1005 __be64 rx_mcast_frames;
1006 __be64 rx_ucast_bytes;
1007 __be64 rx_ucast_frames;
1008 __be64 rx_err_frames;
1009 } pf;
1010 struct fw_vi_stats_vf {
1011 __be64 tx_bcast_bytes;
1012 __be64 tx_bcast_frames;
1013 __be64 tx_mcast_bytes;
1014 __be64 tx_mcast_frames;
1015 __be64 tx_ucast_bytes;
1016 __be64 tx_ucast_frames;
1017 __be64 tx_drop_frames;
1018 __be64 tx_offload_bytes;
1019 __be64 tx_offload_frames;
1020 __be64 rx_bcast_bytes;
1021 __be64 rx_bcast_frames;
1022 __be64 rx_mcast_bytes;
1023 __be64 rx_mcast_frames;
1024 __be64 rx_ucast_bytes;
1025 __be64 rx_ucast_frames;
1026 __be64 rx_err_frames;
1027 } vf;
1028 } u;
1029};
1030
1031#define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1032#define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1033#define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1034
1035struct fw_acl_mac_cmd {
1036 __be32 op_to_vfn;
1037 __be32 en_to_len16;
1038 u8 nmac;
1039 u8 r3[7];
1040 __be16 r4;
1041 u8 macaddr0[6];
1042 __be16 r5;
1043 u8 macaddr1[6];
1044 __be16 r6;
1045 u8 macaddr2[6];
1046 __be16 r7;
1047 u8 macaddr3[6];
1048};
1049
1050#define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1051#define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1052#define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1053
1054struct fw_acl_vlan_cmd {
1055 __be32 op_to_vfn;
1056 __be32 en_to_len16;
1057 u8 nvlan;
1058 u8 dropnovlan_fm;
1059 u8 r3_lo[6];
1060 __be16 vlanid[16];
1061};
1062
1063#define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1064#define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1065#define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1066#define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1067#define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1068
1069enum fw_port_cap {
1070 FW_PORT_CAP_SPEED_100M = 0x0001,
1071 FW_PORT_CAP_SPEED_1G = 0x0002,
1072 FW_PORT_CAP_SPEED_2_5G = 0x0004,
1073 FW_PORT_CAP_SPEED_10G = 0x0008,
1074 FW_PORT_CAP_SPEED_40G = 0x0010,
1075 FW_PORT_CAP_SPEED_100G = 0x0020,
1076 FW_PORT_CAP_FC_RX = 0x0040,
1077 FW_PORT_CAP_FC_TX = 0x0080,
1078 FW_PORT_CAP_ANEG = 0x0100,
1079 FW_PORT_CAP_MDI_0 = 0x0200,
1080 FW_PORT_CAP_MDI_1 = 0x0400,
1081 FW_PORT_CAP_BEAN = 0x0800,
1082 FW_PORT_CAP_PMA_LPBK = 0x1000,
1083 FW_PORT_CAP_PCS_LPBK = 0x2000,
1084 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
1085 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
1086};
1087
1088enum fw_port_mdi {
1089 FW_PORT_MDI_UNCHANGED,
1090 FW_PORT_MDI_AUTO,
1091 FW_PORT_MDI_F_STRAIGHT,
1092 FW_PORT_MDI_F_CROSSOVER
1093};
1094
1095#define FW_PORT_MDI(x) ((x) << 9)
1096
1097enum fw_port_action {
1098 FW_PORT_ACTION_L1_CFG = 0x0001,
1099 FW_PORT_ACTION_L2_CFG = 0x0002,
1100 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1101 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
1102 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
1103 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1104 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
1105 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
1106 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
1107 FW_PORT_ACTION_L1_LPBK = 0x0021,
1108 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
1109 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
1110 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1111 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1112 FW_PORT_ACTION_PHY_RESET = 0x0040,
1113 FW_PORT_ACTION_PMA_RESET = 0x0041,
1114 FW_PORT_ACTION_PCS_RESET = 0x0042,
1115 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
1116 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
1117 FW_PORT_ACTION_AN_RESET = 0x0045
1118};
1119
1120enum fw_port_l2cfg_ctlbf {
1121 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1122 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1123 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1124 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1125 FW_PORT_L2_CTLBF_IVLAN = 0x10,
1126 FW_PORT_L2_CTLBF_TXIPG = 0x20
1127};
1128
1129enum fw_port_dcb_cfg {
1130 FW_PORT_DCB_CFG_PG = 0x01,
1131 FW_PORT_DCB_CFG_PFC = 0x02,
1132 FW_PORT_DCB_CFG_APPL = 0x04
1133};
1134
1135enum fw_port_dcb_cfg_rc {
1136 FW_PORT_DCB_CFG_SUCCESS = 0x0,
1137 FW_PORT_DCB_CFG_ERROR = 0x1
1138};
1139
1140struct fw_port_cmd {
1141 __be32 op_to_portid;
1142 __be32 action_to_len16;
1143 union fw_port {
1144 struct fw_port_l1cfg {
1145 __be32 rcap;
1146 __be32 r;
1147 } l1cfg;
1148 struct fw_port_l2cfg {
1149 __be16 ctlbf_to_ivlan0;
1150 __be16 ivlantype;
1151 __be32 txipg_pkd;
1152 __be16 ovlan0mask;
1153 __be16 ovlan0type;
1154 __be16 ovlan1mask;
1155 __be16 ovlan1type;
1156 __be16 ovlan2mask;
1157 __be16 ovlan2type;
1158 __be16 ovlan3mask;
1159 __be16 ovlan3type;
1160 } l2cfg;
1161 struct fw_port_info {
1162 __be32 lstatus_to_modtype;
1163 __be16 pcap;
1164 __be16 acap;
a0881cab
DM		 1165 __be16 mtu;
1166 __u8 cbllen;
1167 __u8 r9;
1168 __be32 r10;
1169 __be64 r11;
bbc02c7e
DM		 1170 } info;
1171 struct fw_port_ppp {
1172 __be32 pppen_to_ncsich;
1173 __be32 r11;
1174 } ppp;
1175 struct fw_port_dcb {
1176 __be16 cfg;
1177 u8 up_map;
1178 u8 sf_cfgrc;
1179 __be16 prot_ix;
1180 u8 pe7_to_pe0;
1181 u8 numTCPFCs;
1182 __be32 pgid0_to_pgid7;
1183 __be32 numTCs_oui;
1184 u8 pgpc[8];
1185 } dcb;
1186 } u;
1187};
1188
1189#define FW_PORT_CMD_READ (1U << 22)
1190
1191#define FW_PORT_CMD_PORTID(x) ((x) << 0)
1192#define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1193
1194#define FW_PORT_CMD_ACTION(x) ((x) << 16)
81323b74 1195#define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
bbc02c7e
DM		 1196
1197#define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1198#define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1199#define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1200#define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1201#define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1202#define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1203
1204#define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1205
1206#define FW_PORT_CMD_LSTATUS (1U << 31)
1207#define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1208#define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1209#define FW_PORT_CMD_TXPAUSE (1U << 23)
1210#define FW_PORT_CMD_RXPAUSE (1U << 22)
1211#define FW_PORT_CMD_MDIOCAP (1U << 21)
1212#define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1213#define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1214#define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1215#define FW_PORT_CMD_PTYPE_MASK 0x1f
1216#define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1217#define FW_PORT_CMD_MODTYPE_MASK 0x1f
1218#define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1219
1220#define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1221#define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1222#define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1223
1224#define FW_PORT_CMD_CH0(x) ((x) << 20)
1225#define FW_PORT_CMD_CH1(x) ((x) << 16)
1226#define FW_PORT_CMD_CH2(x) ((x) << 12)
1227#define FW_PORT_CMD_CH3(x) ((x) << 8)
1228#define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1229
1230enum fw_port_type {
a0881cab
DM		 1231 FW_PORT_TYPE_FIBER_XFI,
1232 FW_PORT_TYPE_FIBER_XAUI,
bbc02c7e 1233 FW_PORT_TYPE_BT_SGMII,
a0881cab 1234 FW_PORT_TYPE_BT_XFI,
bbc02c7e 1235 FW_PORT_TYPE_BT_XAUI,
a0881cab 1236 FW_PORT_TYPE_KX4,
bbc02c7e 1237 FW_PORT_TYPE_CX4,
a0881cab
DM		 1238 FW_PORT_TYPE_KX,
1239 FW_PORT_TYPE_KR,
1240 FW_PORT_TYPE_SFP,
1241 FW_PORT_TYPE_BP_AP,
bbc02c7e
DM		 1242
1243 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1244};
1245
1246enum fw_port_module_type {
1247 FW_PORT_MOD_TYPE_NA,
1248 FW_PORT_MOD_TYPE_LR,
1249 FW_PORT_MOD_TYPE_SR,
1250 FW_PORT_MOD_TYPE_ER,
a0881cab
DM		 1251 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1252 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1253 FW_PORT_MOD_TYPE_LRM,
bbc02c7e
DM		 1254
1255 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1256};
1257
1258/* port stats */
1259#define FW_NUM_PORT_STATS 50
1260#define FW_NUM_PORT_TX_STATS 23
1261#define FW_NUM_PORT_RX_STATS 27
1262
1263enum fw_port_stats_tx_index {
1264 FW_STAT_TX_PORT_BYTES_IX,
1265 FW_STAT_TX_PORT_FRAMES_IX,
1266 FW_STAT_TX_PORT_BCAST_IX,
1267 FW_STAT_TX_PORT_MCAST_IX,
1268 FW_STAT_TX_PORT_UCAST_IX,
1269 FW_STAT_TX_PORT_ERROR_IX,
1270 FW_STAT_TX_PORT_64B_IX,
1271 FW_STAT_TX_PORT_65B_127B_IX,
1272 FW_STAT_TX_PORT_128B_255B_IX,
1273 FW_STAT_TX_PORT_256B_511B_IX,
1274 FW_STAT_TX_PORT_512B_1023B_IX,
1275 FW_STAT_TX_PORT_1024B_1518B_IX,
1276 FW_STAT_TX_PORT_1519B_MAX_IX,
1277 FW_STAT_TX_PORT_DROP_IX,
1278 FW_STAT_TX_PORT_PAUSE_IX,
1279 FW_STAT_TX_PORT_PPP0_IX,
1280 FW_STAT_TX_PORT_PPP1_IX,
1281 FW_STAT_TX_PORT_PPP2_IX,
1282 FW_STAT_TX_PORT_PPP3_IX,
1283 FW_STAT_TX_PORT_PPP4_IX,
1284 FW_STAT_TX_PORT_PPP5_IX,
1285 FW_STAT_TX_PORT_PPP6_IX,
1286 FW_STAT_TX_PORT_PPP7_IX
1287};
1288
1289enum fw_port_stat_rx_index {
1290 FW_STAT_RX_PORT_BYTES_IX,
1291 FW_STAT_RX_PORT_FRAMES_IX,
1292 FW_STAT_RX_PORT_BCAST_IX,
1293 FW_STAT_RX_PORT_MCAST_IX,
1294 FW_STAT_RX_PORT_UCAST_IX,
1295 FW_STAT_RX_PORT_MTU_ERROR_IX,
1296 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1297 FW_STAT_RX_PORT_CRC_ERROR_IX,
1298 FW_STAT_RX_PORT_LEN_ERROR_IX,
1299 FW_STAT_RX_PORT_SYM_ERROR_IX,
1300 FW_STAT_RX_PORT_64B_IX,
1301 FW_STAT_RX_PORT_65B_127B_IX,
1302 FW_STAT_RX_PORT_128B_255B_IX,
1303 FW_STAT_RX_PORT_256B_511B_IX,
1304 FW_STAT_RX_PORT_512B_1023B_IX,
1305 FW_STAT_RX_PORT_1024B_1518B_IX,
1306 FW_STAT_RX_PORT_1519B_MAX_IX,
1307 FW_STAT_RX_PORT_PAUSE_IX,
1308 FW_STAT_RX_PORT_PPP0_IX,
1309 FW_STAT_RX_PORT_PPP1_IX,
1310 FW_STAT_RX_PORT_PPP2_IX,
1311 FW_STAT_RX_PORT_PPP3_IX,
1312 FW_STAT_RX_PORT_PPP4_IX,
1313 FW_STAT_RX_PORT_PPP5_IX,
1314 FW_STAT_RX_PORT_PPP6_IX,
1315 FW_STAT_RX_PORT_PPP7_IX,
1316 FW_STAT_RX_PORT_LESS_64B_IX
1317};
1318
1319struct fw_port_stats_cmd {
1320 __be32 op_to_portid;
1321 __be32 retval_len16;
1322 union fw_port_stats {
1323 struct fw_port_stats_ctl {
1324 u8 nstats_bg_bm;
1325 u8 tx_ix;
1326 __be16 r6;
1327 __be32 r7;
1328 __be64 stat0;
1329 __be64 stat1;
1330 __be64 stat2;
1331 __be64 stat3;
1332 __be64 stat4;
1333 __be64 stat5;
1334 } ctl;
1335 struct fw_port_stats_all {
1336 __be64 tx_bytes;
1337 __be64 tx_frames;
1338 __be64 tx_bcast;
1339 __be64 tx_mcast;
1340 __be64 tx_ucast;
1341 __be64 tx_error;
1342 __be64 tx_64b;
1343 __be64 tx_65b_127b;
1344 __be64 tx_128b_255b;
1345 __be64 tx_256b_511b;
1346 __be64 tx_512b_1023b;
1347 __be64 tx_1024b_1518b;
1348 __be64 tx_1519b_max;
1349 __be64 tx_drop;
1350 __be64 tx_pause;
1351 __be64 tx_ppp0;
1352 __be64 tx_ppp1;
1353 __be64 tx_ppp2;
1354 __be64 tx_ppp3;
1355 __be64 tx_ppp4;
1356 __be64 tx_ppp5;
1357 __be64 tx_ppp6;
1358 __be64 tx_ppp7;
1359 __be64 rx_bytes;
1360 __be64 rx_frames;
1361 __be64 rx_bcast;
1362 __be64 rx_mcast;
1363 __be64 rx_ucast;
1364 __be64 rx_mtu_error;
1365 __be64 rx_mtu_crc_error;
1366 __be64 rx_crc_error;
1367 __be64 rx_len_error;
1368 __be64 rx_sym_error;
1369 __be64 rx_64b;
1370 __be64 rx_65b_127b;
1371 __be64 rx_128b_255b;
1372 __be64 rx_256b_511b;
1373 __be64 rx_512b_1023b;
1374 __be64 rx_1024b_1518b;
1375 __be64 rx_1519b_max;
1376 __be64 rx_pause;
1377 __be64 rx_ppp0;
1378 __be64 rx_ppp1;
1379 __be64 rx_ppp2;
1380 __be64 rx_ppp3;
1381 __be64 rx_ppp4;
1382 __be64 rx_ppp5;
1383 __be64 rx_ppp6;
1384 __be64 rx_ppp7;
1385 __be64 rx_less_64b;
1386 __be64 rx_bg_drop;
1387 __be64 rx_bg_trunc;
1388 } all;
1389 } u;
1390};
1391
1392#define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1393#define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1394#define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1395#define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1396
1397/* port loopback stats */
1398#define FW_NUM_LB_STATS 16
1399enum fw_port_lb_stats_index {
1400 FW_STAT_LB_PORT_BYTES_IX,
1401 FW_STAT_LB_PORT_FRAMES_IX,
1402 FW_STAT_LB_PORT_BCAST_IX,
1403 FW_STAT_LB_PORT_MCAST_IX,
1404 FW_STAT_LB_PORT_UCAST_IX,
1405 FW_STAT_LB_PORT_ERROR_IX,
1406 FW_STAT_LB_PORT_64B_IX,
1407 FW_STAT_LB_PORT_65B_127B_IX,
1408 FW_STAT_LB_PORT_128B_255B_IX,
1409 FW_STAT_LB_PORT_256B_511B_IX,
1410 FW_STAT_LB_PORT_512B_1023B_IX,
1411 FW_STAT_LB_PORT_1024B_1518B_IX,
1412 FW_STAT_LB_PORT_1519B_MAX_IX,
1413 FW_STAT_LB_PORT_DROP_FRAMES_IX
1414};
1415
1416struct fw_port_lb_stats_cmd {
1417 __be32 op_to_lbport;
1418 __be32 retval_len16;
1419 union fw_port_lb_stats {
1420 struct fw_port_lb_stats_ctl {
1421 u8 nstats_bg_bm;
1422 u8 ix_pkd;
1423 __be16 r6;
1424 __be32 r7;
1425 __be64 stat0;
1426 __be64 stat1;
1427 __be64 stat2;
1428 __be64 stat3;
1429 __be64 stat4;
1430 __be64 stat5;
1431 } ctl;
1432 struct fw_port_lb_stats_all {
1433 __be64 tx_bytes;
1434 __be64 tx_frames;
1435 __be64 tx_bcast;
1436 __be64 tx_mcast;
1437 __be64 tx_ucast;
1438 __be64 tx_error;
1439 __be64 tx_64b;
1440 __be64 tx_65b_127b;
1441 __be64 tx_128b_255b;
1442 __be64 tx_256b_511b;
1443 __be64 tx_512b_1023b;
1444 __be64 tx_1024b_1518b;
1445 __be64 tx_1519b_max;
1446 __be64 rx_lb_drop;
1447 __be64 rx_lb_trunc;
1448 } all;
1449 } u;
1450};
1451
1452#define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
1453#define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
1454#define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
1455#define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
1456
1457struct fw_rss_ind_tbl_cmd {
1458 __be32 op_to_viid;
1459#define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
1460 __be32 retval_len16;
1461 __be16 niqid;
1462 __be16 startidx;
1463 __be32 r3;
1464 __be32 iq0_to_iq2;
1465#define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
1466#define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
1467#define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
1468 __be32 iq3_to_iq5;
1469 __be32 iq6_to_iq8;
1470 __be32 iq9_to_iq11;
1471 __be32 iq12_to_iq14;
1472 __be32 iq15_to_iq17;
1473 __be32 iq18_to_iq20;
1474 __be32 iq21_to_iq23;
1475 __be32 iq24_to_iq26;
1476 __be32 iq27_to_iq29;
1477 __be32 iq30_iq31;
1478 __be32 r15_lo;
1479};
1480
1481struct fw_rss_glb_config_cmd {
1482 __be32 op_to_write;
1483 __be32 retval_len16;
1484 union fw_rss_glb_config {
1485 struct fw_rss_glb_config_manual {
1486 __be32 mode_pkd;
1487 __be32 r3;
1488 __be64 r4;
1489 __be64 r5;
1490 } manual;
1491 struct fw_rss_glb_config_basicvirtual {
1492 __be32 mode_pkd;
1493 __be32 synmapen_to_hashtoeplitz;
1494#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
1495#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
1496#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
1497#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
1498#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
1499#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
1500#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
1501#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
1502#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
1503 __be64 r8;
1504 __be64 r9;
1505 } basicvirtual;
1506 } u;
1507};
1508
1509#define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
81323b74 1510#define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
bbc02c7e
DM		 1511
1512#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
1513#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1514
1515struct fw_rss_vi_config_cmd {
1516 __be32 op_to_viid;
1517#define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
1518 __be32 retval_len16;
1519 union fw_rss_vi_config {
1520 struct fw_rss_vi_config_manual {
1521 __be64 r3;
1522 __be64 r4;
1523 __be64 r5;
1524 } manual;
1525 struct fw_rss_vi_config_basicvirtual {
1526 __be32 r6;
81323b74 1527 __be32 defaultq_to_udpen;
bbc02c7e 1528#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
81323b74 1529#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
bbc02c7e
DM		 1530#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
1531#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
1532#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
1533#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
81323b74 1534#define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0)
bbc02c7e
DM		 1535 __be64 r9;
1536 __be64 r10;
1537 } basicvirtual;
1538 } u;
1539};
1540
1541enum fw_error_type {
1542 FW_ERROR_TYPE_EXCEPTION = 0x0,
1543 FW_ERROR_TYPE_HWMODULE = 0x1,
1544 FW_ERROR_TYPE_WR = 0x2,
1545 FW_ERROR_TYPE_ACL = 0x3,
1546};
1547
1548struct fw_error_cmd {
1549 __be32 op_to_type;
1550 __be32 len16_pkd;
1551 union fw_error {
1552 struct fw_error_exception {
1553 __be32 info[6];
1554 } exception;
1555 struct fw_error_hwmodule {
1556 __be32 regaddr;
1557 __be32 regval;
1558 } hwmodule;
1559 struct fw_error_wr {
1560 __be16 cidx;
1561 __be16 pfn_vfn;
1562 __be32 eqid;
1563 u8 wrhdr[16];
1564 } wr;
1565 struct fw_error_acl {
1566 __be16 cidx;
1567 __be16 pfn_vfn;
1568 __be32 eqid;
1569 __be16 mv_pkd;
1570 u8 val[6];
1571 __be64 r4;
1572 } acl;
1573 } u;
1574};
1575
1576struct fw_debug_cmd {
1577 __be32 op_type;
1578#define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
1579 __be32 len16_pkd;
1580 union fw_debug {
1581 struct fw_debug_assert {
1582 __be32 fcid;
1583 __be32 line;
1584 __be32 x;
1585 __be32 y;
1586 u8 filename_0_7[8];
1587 u8 filename_8_15[8];
1588 __be64 r3;
1589 } assert;
1590 struct fw_debug_prt {
1591 __be16 dprtstridx;
1592 __be16 r3[3];
1593 __be32 dprtstrparam0;
1594 __be32 dprtstrparam1;
1595 __be32 dprtstrparam2;
1596 __be32 dprtstrparam3;
1597 } prt;
1598 } u;
1599};
1600
1601struct fw_hdr {
1602 u8 ver;
1603 u8 reserved1;
1604 __be16 len512; /* bin length in units of 512-bytes */
1605 __be32 fw_ver; /* firmware version */
1606 __be32 tp_microcode_ver;
1607 u8 intfver_nic;
1608 u8 intfver_vnic;
1609 u8 intfver_ofld;
1610 u8 intfver_ri;
1611 u8 intfver_iscsipdu;
1612 u8 intfver_iscsi;
1613 u8 intfver_fcoe;
1614 u8 reserved2;
1615 __be32 reserved3[27];
1616};
1617
1618#define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
1619#define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
1620#define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
1621#define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
1622#endif /* _T4FW_INTERFACE_H_ */
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