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cnic: Finetune iSCSI connection reset.
[net-next-2.6.git] / drivers / net / cnic.c
CommitLineData
a4636960
MC		 1/* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
ddf79b20
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
a4636960
MC		 15#include <linux/module.h>
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/list.h>
20#include <linux/slab.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/netdevice.h>
24#include <linux/uio_driver.h>
25#include <linux/in.h>
26#include <linux/dma-mapping.h>
27#include <linux/delay.h>
28#include <linux/ethtool.h>
29#include <linux/if_vlan.h>
30#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31#define BCM_VLAN 1
32#endif
33#include <net/ip.h>
34#include <net/tcp.h>
35#include <net/route.h>
36#include <net/ipv6.h>
37#include <net/ip6_route.h>
c05e85a0 38#include <net/ip6_checksum.h>
a4636960
MC		 39#include <scsi/iscsi_if.h>
40
41#include "cnic_if.h"
42#include "bnx2.h"
e2513065
MC		 43#include "bnx2x_reg.h"
44#include "bnx2x_fw_defs.h"
45#include "bnx2x_hsi.h"
46#include "../scsi/bnx2i/57xx_iscsi_constants.h"
47#include "../scsi/bnx2i/57xx_iscsi_hsi.h"
a4636960
MC		 48#include "cnic.h"
49#include "cnic_defs.h"
50
51#define DRV_MODULE_NAME "cnic"
a4636960
MC		 52
53static char version[] __devinitdata =
54 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
55
56MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
57 "Chen (zongxi@broadcom.com");
58MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
59MODULE_LICENSE("GPL");
60MODULE_VERSION(CNIC_MODULE_VERSION);
61
62static LIST_HEAD(cnic_dev_list);
63static DEFINE_RWLOCK(cnic_dev_lock);
64static DEFINE_MUTEX(cnic_lock);
65
66static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
67
68static int cnic_service_bnx2(void *, void *);
71034ba8 69static int cnic_service_bnx2x(void *, void *);
a4636960
MC		 70static int cnic_ctl(void *, struct cnic_ctl_info *);
71
72static struct cnic_ops cnic_bnx2_ops = {
73 .cnic_owner = THIS_MODULE,
74 .cnic_handler = cnic_service_bnx2,
75 .cnic_ctl = cnic_ctl,
76};
77
71034ba8
MC		 78static struct cnic_ops cnic_bnx2x_ops = {
79 .cnic_owner = THIS_MODULE,
80 .cnic_handler = cnic_service_bnx2x,
81 .cnic_ctl = cnic_ctl,
82};
83
86b53606
MC		 84static void cnic_shutdown_rings(struct cnic_dev *);
85static void cnic_init_rings(struct cnic_dev *);
a4636960
MC		 86static int cnic_cm_set_pg(struct cnic_sock *);
87
88static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
89{
90 struct cnic_dev *dev = uinfo->priv;
91 struct cnic_local *cp = dev->cnic_priv;
92
93 if (!capable(CAP_NET_ADMIN))
94 return -EPERM;
95
96 if (cp->uio_dev != -1)
97 return -EBUSY;
98
86b53606
MC		 99 rtnl_lock();
100 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
101 rtnl_unlock();
102 return -ENODEV;
103 }
104
a4636960
MC		 105 cp->uio_dev = iminor(inode);
106
86b53606
MC		 107 cnic_init_rings(dev);
108 rtnl_unlock();
a4636960
MC		 109
110 return 0;
111}
112
113static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
114{
115 struct cnic_dev *dev = uinfo->priv;
116 struct cnic_local *cp = dev->cnic_priv;
117
86b53606 118 cnic_shutdown_rings(dev);
6ef57a0e 119
a4636960
MC		 120 cp->uio_dev = -1;
121 return 0;
122}
123
124static inline void cnic_hold(struct cnic_dev *dev)
125{
126 atomic_inc(&dev->ref_count);
127}
128
129static inline void cnic_put(struct cnic_dev *dev)
130{
131 atomic_dec(&dev->ref_count);
132}
133
134static inline void csk_hold(struct cnic_sock *csk)
135{
136 atomic_inc(&csk->ref_count);
137}
138
139static inline void csk_put(struct cnic_sock *csk)
140{
141 atomic_dec(&csk->ref_count);
142}
143
144static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
145{
146 struct cnic_dev *cdev;
147
148 read_lock(&cnic_dev_lock);
149 list_for_each_entry(cdev, &cnic_dev_list, list) {
150 if (netdev == cdev->netdev) {
151 cnic_hold(cdev);
152 read_unlock(&cnic_dev_lock);
153 return cdev;
154 }
155 }
156 read_unlock(&cnic_dev_lock);
157 return NULL;
158}
159
7fc1ece4
MC		 160static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
161{
162 atomic_inc(&ulp_ops->ref_count);
163}
164
165static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
166{
167 atomic_dec(&ulp_ops->ref_count);
168}
169
a4636960
MC		 170static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
171{
172 struct cnic_local *cp = dev->cnic_priv;
173 struct cnic_eth_dev *ethdev = cp->ethdev;
174 struct drv_ctl_info info;
175 struct drv_ctl_io *io = &info.data.io;
176
177 info.cmd = DRV_CTL_CTX_WR_CMD;
178 io->cid_addr = cid_addr;
179 io->offset = off;
180 io->data = val;
181 ethdev->drv_ctl(dev->netdev, &info);
182}
183
71034ba8
MC		 184static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
185{
186 struct cnic_local *cp = dev->cnic_priv;
187 struct cnic_eth_dev *ethdev = cp->ethdev;
188 struct drv_ctl_info info;
189 struct drv_ctl_io *io = &info.data.io;
190
191 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
192 io->offset = off;
193 io->dma_addr = addr;
194 ethdev->drv_ctl(dev->netdev, &info);
195}
196
197static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
198{
199 struct cnic_local *cp = dev->cnic_priv;
200 struct cnic_eth_dev *ethdev = cp->ethdev;
201 struct drv_ctl_info info;
202 struct drv_ctl_l2_ring *ring = &info.data.ring;
203
204 if (start)
205 info.cmd = DRV_CTL_START_L2_CMD;
206 else
207 info.cmd = DRV_CTL_STOP_L2_CMD;
208
209 ring->cid = cid;
210 ring->client_id = cl_id;
211 ethdev->drv_ctl(dev->netdev, &info);
212}
213
a4636960
MC		 214static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
215{
216 struct cnic_local *cp = dev->cnic_priv;
217 struct cnic_eth_dev *ethdev = cp->ethdev;
218 struct drv_ctl_info info;
219 struct drv_ctl_io *io = &info.data.io;
220
221 info.cmd = DRV_CTL_IO_WR_CMD;
222 io->offset = off;
223 io->data = val;
224 ethdev->drv_ctl(dev->netdev, &info);
225}
226
227static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
228{
229 struct cnic_local *cp = dev->cnic_priv;
230 struct cnic_eth_dev *ethdev = cp->ethdev;
231 struct drv_ctl_info info;
232 struct drv_ctl_io *io = &info.data.io;
233
234 info.cmd = DRV_CTL_IO_RD_CMD;
235 io->offset = off;
236 ethdev->drv_ctl(dev->netdev, &info);
237 return io->data;
238}
239
240static int cnic_in_use(struct cnic_sock *csk)
241{
242 return test_bit(SK_F_INUSE, &csk->flags);
243}
244
245static void cnic_kwq_completion(struct cnic_dev *dev, u32 count)
246{
247 struct cnic_local *cp = dev->cnic_priv;
248 struct cnic_eth_dev *ethdev = cp->ethdev;
249 struct drv_ctl_info info;
250
251 info.cmd = DRV_CTL_COMPLETION_CMD;
252 info.data.comp.comp_count = count;
253 ethdev->drv_ctl(dev->netdev, &info);
254}
255
71034ba8
MC		 256static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
257{
258 u32 i;
259
260 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
261 if (cp->ctx_tbl[i].cid == cid) {
262 *l5_cid = i;
263 return 0;
264 }
265 }
266 return -EINVAL;
267}
268
a4636960
MC		 269static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
270 struct cnic_sock *csk)
271{
272 struct iscsi_path path_req;
273 char *buf = NULL;
274 u16 len = 0;
275 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
276 struct cnic_ulp_ops *ulp_ops;
277
278 if (cp->uio_dev == -1)
279 return -ENODEV;
280
281 if (csk) {
282 len = sizeof(path_req);
283 buf = (char *) &path_req;
284 memset(&path_req, 0, len);
285
286 msg_type = ISCSI_KEVENT_PATH_REQ;
287 path_req.handle = (u64) csk->l5_cid;
288 if (test_bit(SK_F_IPV6, &csk->flags)) {
289 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
290 sizeof(struct in6_addr));
291 path_req.ip_addr_len = 16;
292 } else {
293 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
294 sizeof(struct in_addr));
295 path_req.ip_addr_len = 4;
296 }
297 path_req.vlan_id = csk->vlan_id;
298 path_req.pmtu = csk->mtu;
299 }
300
301 rcu_read_lock();
6d7760a8 302 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
a4636960
MC		 303 if (ulp_ops)
304 ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
305 rcu_read_unlock();
306 return 0;
307}
308
309static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
310 char *buf, u16 len)
311{
312 int rc = -EINVAL;
313
314 switch (msg_type) {
315 case ISCSI_UEVENT_PATH_UPDATE: {
316 struct cnic_local *cp;
317 u32 l5_cid;
318 struct cnic_sock *csk;
319 struct iscsi_path *path_resp;
320
321 if (len < sizeof(*path_resp))
322 break;
323
324 path_resp = (struct iscsi_path *) buf;
325 cp = dev->cnic_priv;
326 l5_cid = (u32) path_resp->handle;
327 if (l5_cid >= MAX_CM_SK_TBL_SZ)
328 break;
329
330 csk = &cp->csk_tbl[l5_cid];
331 csk_hold(csk);
332 if (cnic_in_use(csk)) {
333 memcpy(csk->ha, path_resp->mac_addr, 6);
334 if (test_bit(SK_F_IPV6, &csk->flags))
335 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
336 sizeof(struct in6_addr));
337 else
338 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
339 sizeof(struct in_addr));
340 if (is_valid_ether_addr(csk->ha))
341 cnic_cm_set_pg(csk);
342 }
343 csk_put(csk);
344 rc = 0;
345 }
346 }
347
348 return rc;
349}
350
351static int cnic_offld_prep(struct cnic_sock *csk)
352{
353 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
354 return 0;
355
356 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
357 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
358 return 0;
359 }
360
361 return 1;
362}
363
364static int cnic_close_prep(struct cnic_sock *csk)
365{
366 clear_bit(SK_F_CONNECT_START, &csk->flags);
367 smp_mb__after_clear_bit();
368
369 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
370 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
371 msleep(1);
372
373 return 1;
374 }
375 return 0;
376}
377
378static int cnic_abort_prep(struct cnic_sock *csk)
379{
380 clear_bit(SK_F_CONNECT_START, &csk->flags);
381 smp_mb__after_clear_bit();
382
383 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
384 msleep(1);
385
386 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
387 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
388 return 1;
389 }
390
391 return 0;
392}
393
6d7760a8
MC		 394static void cnic_uio_stop(void)
395{
396 struct cnic_dev *dev;
397
398 read_lock(&cnic_dev_lock);
399 list_for_each_entry(dev, &cnic_dev_list, list) {
400 struct cnic_local *cp = dev->cnic_priv;
401
402 if (cp->cnic_uinfo)
403 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
404 }
405 read_unlock(&cnic_dev_lock);
406}
407
a4636960
MC		 408int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
409{
410 struct cnic_dev *dev;
411
0d37f36f 412 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
ddf79b20 413 pr_err("%s: Bad type %d\n", __func__, ulp_type);
a4636960
MC		 414 return -EINVAL;
415 }
416 mutex_lock(&cnic_lock);
417 if (cnic_ulp_tbl[ulp_type]) {
ddf79b20
JP		 418 pr_err("%s: Type %d has already been registered\n",
419 __func__, ulp_type);
a4636960
MC		 420 mutex_unlock(&cnic_lock);
421 return -EBUSY;
422 }
423
424 read_lock(&cnic_dev_lock);
425 list_for_each_entry(dev, &cnic_dev_list, list) {
426 struct cnic_local *cp = dev->cnic_priv;
427
428 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
429 }
430 read_unlock(&cnic_dev_lock);
431
7fc1ece4 432 atomic_set(&ulp_ops->ref_count, 0);
a4636960
MC		 433 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
434 mutex_unlock(&cnic_lock);
435
436 /* Prevent race conditions with netdev_event */
437 rtnl_lock();
438 read_lock(&cnic_dev_lock);
439 list_for_each_entry(dev, &cnic_dev_list, list) {
440 struct cnic_local *cp = dev->cnic_priv;
441
442 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
443 ulp_ops->cnic_init(dev);
444 }
445 read_unlock(&cnic_dev_lock);
446 rtnl_unlock();
447
448 return 0;
449}
450
451int cnic_unregister_driver(int ulp_type)
452{
453 struct cnic_dev *dev;
7fc1ece4
MC		 454 struct cnic_ulp_ops *ulp_ops;
455 int i = 0;
a4636960 456
0d37f36f 457 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
ddf79b20 458 pr_err("%s: Bad type %d\n", __func__, ulp_type);
a4636960
MC		 459 return -EINVAL;
460 }
461 mutex_lock(&cnic_lock);
7fc1ece4
MC		 462 ulp_ops = cnic_ulp_tbl[ulp_type];
463 if (!ulp_ops) {
ddf79b20
JP		 464 pr_err("%s: Type %d has not been registered\n",
465 __func__, ulp_type);
a4636960
MC		 466 goto out_unlock;
467 }
468 read_lock(&cnic_dev_lock);
469 list_for_each_entry(dev, &cnic_dev_list, list) {
470 struct cnic_local *cp = dev->cnic_priv;
471
472 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
ddf79b20
JP		 473 pr_err("%s: Type %d still has devices registered\n",
474 __func__, ulp_type);
a4636960
MC		 475 read_unlock(&cnic_dev_lock);
476 goto out_unlock;
477 }
478 }
479 read_unlock(&cnic_dev_lock);
480
6d7760a8
MC		 481 if (ulp_type == CNIC_ULP_ISCSI)
482 cnic_uio_stop();
483
a4636960
MC		 484 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
485
486 mutex_unlock(&cnic_lock);
487 synchronize_rcu();
7fc1ece4
MC		 488 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
489 msleep(100);
490 i++;
491 }
492
493 if (atomic_read(&ulp_ops->ref_count) != 0)
ddf79b20 494 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
a4636960
MC		 495 return 0;
496
497out_unlock:
498 mutex_unlock(&cnic_lock);
499 return -EINVAL;
500}
501
502static int cnic_start_hw(struct cnic_dev *);
503static void cnic_stop_hw(struct cnic_dev *);
504
505static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
506 void *ulp_ctx)
507{
508 struct cnic_local *cp = dev->cnic_priv;
509 struct cnic_ulp_ops *ulp_ops;
510
0d37f36f 511 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
ddf79b20 512 pr_err("%s: Bad type %d\n", __func__, ulp_type);
a4636960
MC		 513 return -EINVAL;
514 }
515 mutex_lock(&cnic_lock);
516 if (cnic_ulp_tbl[ulp_type] == NULL) {
ddf79b20
JP		 517 pr_err("%s: Driver with type %d has not been registered\n",
518 __func__, ulp_type);
a4636960
MC		 519 mutex_unlock(&cnic_lock);
520 return -EAGAIN;
521 }
522 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
ddf79b20
JP		 523 pr_err("%s: Type %d has already been registered to this device\n",
524 __func__, ulp_type);
a4636960
MC		 525 mutex_unlock(&cnic_lock);
526 return -EBUSY;
527 }
528
529 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
530 cp->ulp_handle[ulp_type] = ulp_ctx;
531 ulp_ops = cnic_ulp_tbl[ulp_type];
532 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
533 cnic_hold(dev);
534
535 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
536 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
537 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
538
539 mutex_unlock(&cnic_lock);
540
541 return 0;
542
543}
544EXPORT_SYMBOL(cnic_register_driver);
545
546static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
547{
548 struct cnic_local *cp = dev->cnic_priv;
681dbd71 549 int i = 0;
a4636960 550
0d37f36f 551 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
ddf79b20 552 pr_err("%s: Bad type %d\n", __func__, ulp_type);
a4636960
MC		 553 return -EINVAL;
554 }
555 mutex_lock(&cnic_lock);
556 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
557 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
558 cnic_put(dev);
559 } else {
ddf79b20
JP		 560 pr_err("%s: device not registered to this ulp type %d\n",
561 __func__, ulp_type);
a4636960
MC		 562 mutex_unlock(&cnic_lock);
563 return -EINVAL;
564 }
565 mutex_unlock(&cnic_lock);
566
567 synchronize_rcu();
568
681dbd71
MC		 569 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
570 i < 20) {
571 msleep(100);
572 i++;
573 }
574 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
ddf79b20 575 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
681dbd71 576
a4636960
MC		 577 return 0;
578}
579EXPORT_SYMBOL(cnic_unregister_driver);
580
581static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
582{
583 id_tbl->start = start_id;
584 id_tbl->max = size;
585 id_tbl->next = 0;
586 spin_lock_init(&id_tbl->lock);
587 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
588 if (!id_tbl->table)
589 return -ENOMEM;
590
591 return 0;
592}
593
594static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
595{
596 kfree(id_tbl->table);
597 id_tbl->table = NULL;
598}
599
600static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
601{
602 int ret = -1;
603
604 id -= id_tbl->start;
605 if (id >= id_tbl->max)
606 return ret;
607
608 spin_lock(&id_tbl->lock);
609 if (!test_bit(id, id_tbl->table)) {
610 set_bit(id, id_tbl->table);
611 ret = 0;
612 }
613 spin_unlock(&id_tbl->lock);
614 return ret;
615}
616
617/* Returns -1 if not successful */
618static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
619{
620 u32 id;
621
622 spin_lock(&id_tbl->lock);
623 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
624 if (id >= id_tbl->max) {
625 id = -1;
626 if (id_tbl->next != 0) {
627 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
628 if (id >= id_tbl->next)
629 id = -1;
630 }
631 }
632
633 if (id < id_tbl->max) {
634 set_bit(id, id_tbl->table);
635 id_tbl->next = (id + 1) & (id_tbl->max - 1);
636 id += id_tbl->start;
637 }
638
639 spin_unlock(&id_tbl->lock);
640
641 return id;
642}
643
644static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
645{
646 if (id == -1)
647 return;
648
649 id -= id_tbl->start;
650 if (id >= id_tbl->max)
651 return;
652
653 clear_bit(id, id_tbl->table);
654}
655
656static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
657{
658 int i;
659
660 if (!dma->pg_arr)
661 return;
662
663 for (i = 0; i < dma->num_pages; i++) {
664 if (dma->pg_arr[i]) {
3248e168
MC		 665 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
666 dma->pg_arr[i], dma->pg_map_arr[i]);
a4636960
MC		 667 dma->pg_arr[i] = NULL;
668 }
669 }
670 if (dma->pgtbl) {
3248e168
MC		 671 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
672 dma->pgtbl, dma->pgtbl_map);
a4636960
MC		 673 dma->pgtbl = NULL;
674 }
675 kfree(dma->pg_arr);
676 dma->pg_arr = NULL;
677 dma->num_pages = 0;
678}
679
680static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
681{
682 int i;
683 u32 *page_table = dma->pgtbl;
684
685 for (i = 0; i < dma->num_pages; i++) {
686 /* Each entry needs to be in big endian format. */
687 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
688 page_table++;
689 *page_table = (u32) dma->pg_map_arr[i];
690 page_table++;
691 }
692}
693
71034ba8
MC		 694static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
695{
696 int i;
697 u32 *page_table = dma->pgtbl;
698
699 for (i = 0; i < dma->num_pages; i++) {
700 /* Each entry needs to be in little endian format. */
701 *page_table = dma->pg_map_arr[i] & 0xffffffff;
702 page_table++;
703 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
704 page_table++;
705 }
706}
707
a4636960
MC		 708static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
709 int pages, int use_pg_tbl)
710{
711 int i, size;
712 struct cnic_local *cp = dev->cnic_priv;
713
714 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
715 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
716 if (dma->pg_arr == NULL)
717 return -ENOMEM;
718
719 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
720 dma->num_pages = pages;
721
722 for (i = 0; i < pages; i++) {
3248e168
MC		 723 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
724 BCM_PAGE_SIZE,
725 &dma->pg_map_arr[i],
726 GFP_ATOMIC);
a4636960
MC		 727 if (dma->pg_arr[i] == NULL)
728 goto error;
729 }
730 if (!use_pg_tbl)
731 return 0;
732
733 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
734 ~(BCM_PAGE_SIZE - 1);
3248e168
MC		 735 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
736 &dma->pgtbl_map, GFP_ATOMIC);
a4636960
MC		 737 if (dma->pgtbl == NULL)
738 goto error;
739
740 cp->setup_pgtbl(dev, dma);
741
742 return 0;
743
744error:
745 cnic_free_dma(dev, dma);
746 return -ENOMEM;
747}
748
86b53606
MC		 749static void cnic_free_context(struct cnic_dev *dev)
750{
751 struct cnic_local *cp = dev->cnic_priv;
752 int i;
753
754 for (i = 0; i < cp->ctx_blks; i++) {
755 if (cp->ctx_arr[i].ctx) {
3248e168
MC		 756 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
757 cp->ctx_arr[i].ctx,
758 cp->ctx_arr[i].mapping);
86b53606
MC		 759 cp->ctx_arr[i].ctx = NULL;
760 }
761 }
762}
763
a4636960
MC		 764static void cnic_free_resc(struct cnic_dev *dev)
765{
766 struct cnic_local *cp = dev->cnic_priv;
767 int i = 0;
768
769 if (cp->cnic_uinfo) {
a4636960
MC		 770 while (cp->uio_dev != -1 && i < 15) {
771 msleep(100);
772 i++;
773 }
774 uio_unregister_device(cp->cnic_uinfo);
775 kfree(cp->cnic_uinfo);
776 cp->cnic_uinfo = NULL;
777 }
778
779 if (cp->l2_buf) {
3248e168
MC		 780 dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
781 cp->l2_buf, cp->l2_buf_map);
a4636960
MC		 782 cp->l2_buf = NULL;
783 }
784
785 if (cp->l2_ring) {
3248e168
MC		 786 dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
787 cp->l2_ring, cp->l2_ring_map);
a4636960
MC		 788 cp->l2_ring = NULL;
789 }
790
86b53606 791 cnic_free_context(dev);
a4636960
MC		 792 kfree(cp->ctx_arr);
793 cp->ctx_arr = NULL;
794 cp->ctx_blks = 0;
795
796 cnic_free_dma(dev, &cp->gbl_buf_info);
797 cnic_free_dma(dev, &cp->conn_buf_info);
798 cnic_free_dma(dev, &cp->kwq_info);
71034ba8 799 cnic_free_dma(dev, &cp->kwq_16_data_info);
a4636960
MC		 800 cnic_free_dma(dev, &cp->kcq_info);
801 kfree(cp->iscsi_tbl);
802 cp->iscsi_tbl = NULL;
803 kfree(cp->ctx_tbl);
804 cp->ctx_tbl = NULL;
805
806 cnic_free_id_tbl(&cp->cid_tbl);
807}
808
809static int cnic_alloc_context(struct cnic_dev *dev)
810{
811 struct cnic_local *cp = dev->cnic_priv;
812
813 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
814 int i, k, arr_size;
815
816 cp->ctx_blk_size = BCM_PAGE_SIZE;
817 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
818 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
819 sizeof(struct cnic_ctx);
820 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
821 if (cp->ctx_arr == NULL)
822 return -ENOMEM;
823
824 k = 0;
825 for (i = 0; i < 2; i++) {
826 u32 j, reg, off, lo, hi;
827
828 if (i == 0)
829 off = BNX2_PG_CTX_MAP;
830 else
831 off = BNX2_ISCSI_CTX_MAP;
832
833 reg = cnic_reg_rd_ind(dev, off);
834 lo = reg >> 16;
835 hi = reg & 0xffff;
836 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
837 cp->ctx_arr[k].cid = j;
838 }
839
840 cp->ctx_blks = k;
841 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
842 cp->ctx_blks = 0;
843 return -ENOMEM;
844 }
845
846 for (i = 0; i < cp->ctx_blks; i++) {
847 cp->ctx_arr[i].ctx =
3248e168
MC		 848 dma_alloc_coherent(&dev->pcidev->dev,
849 BCM_PAGE_SIZE,
850 &cp->ctx_arr[i].mapping,
851 GFP_KERNEL);
a4636960
MC		 852 if (cp->ctx_arr[i].ctx == NULL)
853 return -ENOMEM;
854 }
855 }
856 return 0;
857}
858
ec0248ea
MC		 859static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
860{
861 struct cnic_local *cp = dev->cnic_priv;
862
863 cp->l2_ring_size = pages * BCM_PAGE_SIZE;
3248e168
MC		 864 cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
865 &cp->l2_ring_map,
866 GFP_KERNEL | __GFP_COMP);
ec0248ea
MC		 867 if (!cp->l2_ring)
868 return -ENOMEM;
869
870 cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
871 cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
3248e168
MC		 872 cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
873 &cp->l2_buf_map,
874 GFP_KERNEL | __GFP_COMP);
ec0248ea
MC		 875 if (!cp->l2_buf)
876 return -ENOMEM;
877
878 return 0;
879}
880
5e9b2dbf 881static int cnic_alloc_uio(struct cnic_dev *dev) {
a4636960
MC		 882 struct cnic_local *cp = dev->cnic_priv;
883 struct uio_info *uinfo;
884 int ret;
885
a4636960
MC		 886 uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
887 if (!uinfo)
5e9b2dbf 888 return -ENOMEM;
a4636960
MC		 889
890 uinfo->mem[0].addr = dev->netdev->base_addr;
891 uinfo->mem[0].internal_addr = dev->regview;
892 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
893 uinfo->mem[0].memtype = UIO_MEM_PHYS;
894
5e9b2dbf 895 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
86b53606 896 uinfo->mem[1].addr = (unsigned long) cp->status_blk & PAGE_MASK;
5e9b2dbf
MC		 897 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
898 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
899 else
900 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
901
902 uinfo->name = "bnx2_cnic";
71034ba8
MC		 903 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
904 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
905 PAGE_MASK;
906 uinfo->mem[1].size = sizeof(struct host_def_status_block);
907
908 uinfo->name = "bnx2x_cnic";
5e9b2dbf
MC		 909 }
910
a4636960
MC		 911 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
912
913 uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
914 uinfo->mem[2].size = cp->l2_ring_size;
915 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
916
917 uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
918 uinfo->mem[3].size = cp->l2_buf_size;
919 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
920
a4636960
MC		 921 uinfo->version = CNIC_MODULE_VERSION;
922 uinfo->irq = UIO_IRQ_CUSTOM;
923
924 uinfo->open = cnic_uio_open;
925 uinfo->release = cnic_uio_close;
926
927 uinfo->priv = dev;
928
929 ret = uio_register_device(&dev->pcidev->dev, uinfo);
930 if (ret) {
931 kfree(uinfo);
5e9b2dbf 932 return ret;
a4636960
MC		 933 }
934
935 cp->cnic_uinfo = uinfo;
5e9b2dbf
MC		 936 return 0;
937}
938
939static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
940{
941 struct cnic_local *cp = dev->cnic_priv;
942 int ret;
943
944 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
945 if (ret)
946 goto error;
947 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
948
949 ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 1);
950 if (ret)
951 goto error;
952 cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
953
954 ret = cnic_alloc_context(dev);
955 if (ret)
956 goto error;
957
958 ret = cnic_alloc_l2_rings(dev, 2);
959 if (ret)
960 goto error;
961
962 ret = cnic_alloc_uio(dev);
963 if (ret)
964 goto error;
a4636960
MC		 965
966 return 0;
967
968error:
969 cnic_free_resc(dev);
970 return ret;
971}
972
71034ba8
MC		 973static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
974{
975 struct cnic_local *cp = dev->cnic_priv;
976 struct cnic_eth_dev *ethdev = cp->ethdev;
977 int ctx_blk_size = cp->ethdev->ctx_blk_size;
978 int total_mem, blks, i, cid_space;
979
980 if (BNX2X_ISCSI_START_CID < ethdev->starting_cid)
981 return -EINVAL;
982
983 cid_space = MAX_ISCSI_TBL_SZ +
984 (BNX2X_ISCSI_START_CID - ethdev->starting_cid);
985
986 total_mem = BNX2X_CONTEXT_MEM_SIZE * cid_space;
987 blks = total_mem / ctx_blk_size;
988 if (total_mem % ctx_blk_size)
989 blks++;
990
991 if (blks > cp->ethdev->ctx_tbl_len)
992 return -ENOMEM;
993
994 cp->ctx_arr = kzalloc(blks * sizeof(struct cnic_ctx), GFP_KERNEL);
995 if (cp->ctx_arr == NULL)
996 return -ENOMEM;
997
998 cp->ctx_blks = blks;
999 cp->ctx_blk_size = ctx_blk_size;
1000 if (BNX2X_CHIP_IS_E1H(cp->chip_id))
1001 cp->ctx_align = 0;
1002 else
1003 cp->ctx_align = ctx_blk_size;
1004
1005 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1006
1007 for (i = 0; i < blks; i++) {
1008 cp->ctx_arr[i].ctx =
3248e168
MC		 1009 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1010 &cp->ctx_arr[i].mapping,
1011 GFP_KERNEL);
71034ba8
MC		 1012 if (cp->ctx_arr[i].ctx == NULL)
1013 return -ENOMEM;
1014
1015 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1016 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1017 cnic_free_context(dev);
1018 cp->ctx_blk_size += cp->ctx_align;
1019 i = -1;
1020 continue;
1021 }
1022 }
1023 }
1024 return 0;
1025}
1026
1027static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1028{
1029 struct cnic_local *cp = dev->cnic_priv;
1030 int i, j, n, ret, pages;
1031 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1032
1033 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1034 GFP_KERNEL);
1035 if (!cp->iscsi_tbl)
1036 goto error;
1037
1038 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1039 MAX_CNIC_L5_CONTEXT, GFP_KERNEL);
1040 if (!cp->ctx_tbl)
1041 goto error;
1042
1043 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1044 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1045 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1046 }
1047
1048 pages = PAGE_ALIGN(MAX_CNIC_L5_CONTEXT * CNIC_KWQ16_DATA_SIZE) /
1049 PAGE_SIZE;
1050
1051 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1052 if (ret)
1053 return -ENOMEM;
1054
1055 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1056 for (i = 0, j = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1057 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1058
1059 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1060 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1061 off;
1062
1063 if ((i % n) == (n - 1))
1064 j++;
1065 }
1066
1067 ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 0);
1068 if (ret)
1069 goto error;
1070 cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
1071
1072 for (i = 0; i < KCQ_PAGE_CNT; i++) {
1073 struct bnx2x_bd_chain_next *next =
1074 (struct bnx2x_bd_chain_next *)
1075 &cp->kcq[i][MAX_KCQE_CNT];
1076 int j = i + 1;
1077
1078 if (j >= KCQ_PAGE_CNT)
1079 j = 0;
1080 next->addr_hi = (u64) cp->kcq_info.pg_map_arr[j] >> 32;
1081 next->addr_lo = cp->kcq_info.pg_map_arr[j] & 0xffffffff;
1082 }
1083
1084 pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
1085 BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
1086 ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
1087 if (ret)
1088 goto error;
1089
1090 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1091 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1092 if (ret)
1093 goto error;
1094
1095 ret = cnic_alloc_bnx2x_context(dev);
1096 if (ret)
1097 goto error;
1098
1099 cp->bnx2x_status_blk = cp->status_blk;
1100 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1101
4e9c4fd3
MC		 1102 memset(cp->bnx2x_status_blk, 0, sizeof(struct host_status_block));
1103
71034ba8
MC		 1104 cp->l2_rx_ring_size = 15;
1105
1106 ret = cnic_alloc_l2_rings(dev, 4);
1107 if (ret)
1108 goto error;
1109
1110 ret = cnic_alloc_uio(dev);
1111 if (ret)
1112 goto error;
1113
1114 return 0;
1115
1116error:
1117 cnic_free_resc(dev);
1118 return -ENOMEM;
1119}
1120
a4636960
MC		 1121static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1122{
1123 return cp->max_kwq_idx -
1124 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1125}
1126
1127static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1128 u32 num_wqes)
1129{
1130 struct cnic_local *cp = dev->cnic_priv;
1131 struct kwqe *prod_qe;
1132 u16 prod, sw_prod, i;
1133
1134 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1135 return -EAGAIN; /* bnx2 is down */
1136
1137 spin_lock_bh(&cp->cnic_ulp_lock);
1138 if (num_wqes > cnic_kwq_avail(cp) &&
1139 !(cp->cnic_local_flags & CNIC_LCL_FL_KWQ_INIT)) {
1140 spin_unlock_bh(&cp->cnic_ulp_lock);
1141 return -EAGAIN;
1142 }
1143
1144 cp->cnic_local_flags &= ~CNIC_LCL_FL_KWQ_INIT;
1145
1146 prod = cp->kwq_prod_idx;
1147 sw_prod = prod & MAX_KWQ_IDX;
1148 for (i = 0; i < num_wqes; i++) {
1149 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1150 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1151 prod++;
1152 sw_prod = prod & MAX_KWQ_IDX;
1153 }
1154 cp->kwq_prod_idx = prod;
1155
1156 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1157
1158 spin_unlock_bh(&cp->cnic_ulp_lock);
1159 return 0;
1160}
1161
71034ba8
MC		 1162static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1163 union l5cm_specific_data *l5_data)
1164{
1165 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1166 dma_addr_t map;
1167
1168 map = ctx->kwqe_data_mapping;
1169 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1170 l5_data->phy_address.hi = (u64) map >> 32;
1171 return ctx->kwqe_data;
1172}
1173
1174static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1175 u32 type, union l5cm_specific_data *l5_data)
1176{
1177 struct cnic_local *cp = dev->cnic_priv;
1178 struct l5cm_spe kwqe;
1179 struct kwqe_16 *kwq[1];
1180 int ret;
1181
1182 kwqe.hdr.conn_and_cmd_data =
1183 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1184 BNX2X_HW_CID(cid, cp->func)));
1185 kwqe.hdr.type = cpu_to_le16(type);
1186 kwqe.hdr.reserved = 0;
1187 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1188 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1189
1190 kwq[0] = (struct kwqe_16 *) &kwqe;
1191
1192 spin_lock_bh(&cp->cnic_ulp_lock);
1193 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1194 spin_unlock_bh(&cp->cnic_ulp_lock);
1195
1196 if (ret == 1)
1197 return 0;
1198
1199 return -EBUSY;
1200}
1201
1202static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1203 struct kcqe *cqes[], u32 num_cqes)
1204{
1205 struct cnic_local *cp = dev->cnic_priv;
1206 struct cnic_ulp_ops *ulp_ops;
1207
1208 rcu_read_lock();
1209 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1210 if (likely(ulp_ops)) {
1211 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1212 cqes, num_cqes);
1213 }
1214 rcu_read_unlock();
1215}
1216
1217static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1218{
1219 struct cnic_local *cp = dev->cnic_priv;
1220 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1221 int func = cp->func, pages;
1222 int hq_bds;
1223
1224 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1225 cp->num_ccells = req1->num_ccells_per_conn;
1226 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1227 cp->num_iscsi_tasks;
1228 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1229 BNX2X_ISCSI_R2TQE_SIZE;
1230 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1231 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1232 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1233 cp->num_cqs = req1->num_cqs;
1234
1235 if (!dev->max_iscsi_conn)
1236 return 0;
1237
1238 /* init Tstorm RAM */
1239 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(func),
1240 req1->rq_num_wqes);
1241 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
1242 PAGE_SIZE);
1243 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1244 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
1245 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1246 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
1247 req1->num_tasks_per_conn);
1248
1249 /* init Ustorm RAM */
1250 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1251 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(func),
1252 req1->rq_buffer_size);
1253 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(func),
1254 PAGE_SIZE);
1255 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1256 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
1257 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1258 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
1259 req1->num_tasks_per_conn);
1260 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(func),
1261 req1->rq_num_wqes);
1262 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(func),
1263 req1->cq_num_wqes);
1264 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
1265 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1266
1267 /* init Xstorm RAM */
1268 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
1269 PAGE_SIZE);
1270 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1271 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
1272 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1273 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
1274 req1->num_tasks_per_conn);
1275 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(func),
1276 hq_bds);
1277 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(func),
1278 req1->num_tasks_per_conn);
1279 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
1280 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1281
1282 /* init Cstorm RAM */
1283 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
1284 PAGE_SIZE);
1285 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1286 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
1287 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1288 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
1289 req1->num_tasks_per_conn);
1290 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(func),
1291 req1->cq_num_wqes);
1292 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(func),
1293 hq_bds);
1294
1295 return 0;
1296}
1297
1298static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1299{
1300 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1301 struct cnic_local *cp = dev->cnic_priv;
1302 int func = cp->func;
1303 struct iscsi_kcqe kcqe;
1304 struct kcqe *cqes[1];
1305
1306 memset(&kcqe, 0, sizeof(kcqe));
1307 if (!dev->max_iscsi_conn) {
1308 kcqe.completion_status =
1309 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1310 goto done;
1311 }
1312
1313 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1314 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
1315 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1316 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
1317 req2->error_bit_map[1]);
1318
1319 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1320 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
1321 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1322 USTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
1323 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1324 USTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
1325 req2->error_bit_map[1]);
1326
1327 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1328 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
1329
1330 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1331
1332done:
1333 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1334 cqes[0] = (struct kcqe *) &kcqe;
1335 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1336
1337 return 0;
1338}
1339
1340static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1341{
1342 struct cnic_local *cp = dev->cnic_priv;
1343 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1344
1345 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1346 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1347
1348 cnic_free_dma(dev, &iscsi->hq_info);
1349 cnic_free_dma(dev, &iscsi->r2tq_info);
1350 cnic_free_dma(dev, &iscsi->task_array_info);
1351 }
1352 cnic_free_id(&cp->cid_tbl, ctx->cid);
1353 ctx->cid = 0;
1354}
1355
1356static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1357{
1358 u32 cid;
1359 int ret, pages;
1360 struct cnic_local *cp = dev->cnic_priv;
1361 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1362 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1363
1364 cid = cnic_alloc_new_id(&cp->cid_tbl);
1365 if (cid == -1) {
1366 ret = -ENOMEM;
1367 goto error;
1368 }
1369
1370 ctx->cid = cid;
1371 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1372
1373 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1374 if (ret)
1375 goto error;
1376
1377 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1378 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1379 if (ret)
1380 goto error;
1381
1382 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1383 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1384 if (ret)
1385 goto error;
1386
1387 return 0;
1388
1389error:
1390 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1391 return ret;
1392}
1393
1394static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1395 struct regpair *ctx_addr)
1396{
1397 struct cnic_local *cp = dev->cnic_priv;
1398 struct cnic_eth_dev *ethdev = cp->ethdev;
1399 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1400 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1401 unsigned long align_off = 0;
1402 dma_addr_t ctx_map;
1403 void *ctx;
1404
1405 if (cp->ctx_align) {
1406 unsigned long mask = cp->ctx_align - 1;
1407
1408 if (cp->ctx_arr[blk].mapping & mask)
1409 align_off = cp->ctx_align -
1410 (cp->ctx_arr[blk].mapping & mask);
1411 }
1412 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1413 (off * BNX2X_CONTEXT_MEM_SIZE);
1414 ctx = cp->ctx_arr[blk].ctx + align_off +
1415 (off * BNX2X_CONTEXT_MEM_SIZE);
1416 if (init)
1417 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1418
1419 ctx_addr->lo = ctx_map & 0xffffffff;
1420 ctx_addr->hi = (u64) ctx_map >> 32;
1421 return ctx;
1422}
1423
1424static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1425 u32 num)
1426{
1427 struct cnic_local *cp = dev->cnic_priv;
1428 struct iscsi_kwqe_conn_offload1 *req1 =
1429 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1430 struct iscsi_kwqe_conn_offload2 *req2 =
1431 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1432 struct iscsi_kwqe_conn_offload3 *req3;
1433 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1434 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1435 u32 cid = ctx->cid;
1436 u32 hw_cid = BNX2X_HW_CID(cid, cp->func);
1437 struct iscsi_context *ictx;
1438 struct regpair context_addr;
1439 int i, j, n = 2, n_max;
1440
1441 ctx->ctx_flags = 0;
1442 if (!req2->num_additional_wqes)
1443 return -EINVAL;
1444
1445 n_max = req2->num_additional_wqes + 2;
1446
1447 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1448 if (ictx == NULL)
1449 return -ENOMEM;
1450
1451 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1452
1453 ictx->xstorm_ag_context.hq_prod = 1;
1454
1455 ictx->xstorm_st_context.iscsi.first_burst_length =
1456 ISCSI_DEF_FIRST_BURST_LEN;
1457 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1458 ISCSI_DEF_MAX_RECV_SEG_LEN;
1459 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1460 req1->sq_page_table_addr_lo;
1461 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1462 req1->sq_page_table_addr_hi;
1463 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1464 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1465 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1466 iscsi->hq_info.pgtbl_map & 0xffffffff;
1467 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1468 (u64) iscsi->hq_info.pgtbl_map >> 32;
1469 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1470 iscsi->hq_info.pgtbl[0];
1471 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1472 iscsi->hq_info.pgtbl[1];
1473 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1474 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1475 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1476 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1477 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1478 iscsi->r2tq_info.pgtbl[0];
1479 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1480 iscsi->r2tq_info.pgtbl[1];
1481 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1482 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1483 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1484 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1485 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1486 BNX2X_ISCSI_PBL_NOT_CACHED;
1487 ictx->xstorm_st_context.iscsi.flags.flags |=
1488 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1489 ictx->xstorm_st_context.iscsi.flags.flags |=
1490 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1491
1492 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1493 /* TSTORM requires the base address of RQ DB & not PTE */
1494 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1495 req2->rq_page_table_addr_lo & PAGE_MASK;
1496 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1497 req2->rq_page_table_addr_hi;
1498 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1499 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1500 ictx->tstorm_st_context.tcp.flags2 |=
1501 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1502
1503 ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1504
1505 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
15971c3c 1506 req2->rq_page_table_addr_lo;
71034ba8 1507 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
15971c3c 1508 req2->rq_page_table_addr_hi;
71034ba8
MC		 1509 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1510 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1511 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1512 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1513 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1514 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1515 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1516 iscsi->r2tq_info.pgtbl[0];
1517 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1518 iscsi->r2tq_info.pgtbl[1];
1519 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1520 req1->cq_page_table_addr_lo;
1521 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1522 req1->cq_page_table_addr_hi;
1523 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1524 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1525 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1526 ictx->ustorm_st_context.task_pbe_cache_index =
1527 BNX2X_ISCSI_PBL_NOT_CACHED;
1528 ictx->ustorm_st_context.task_pdu_cache_index =
1529 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1530
1531 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1532 if (j == 3) {
1533 if (n >= n_max)
1534 break;
1535 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1536 j = 0;
1537 }
1538 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1539 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1540 req3->qp_first_pte[j].hi;
1541 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1542 req3->qp_first_pte[j].lo;
1543 }
1544
1545 ictx->ustorm_st_context.task_pbl_base.lo =
1546 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1547 ictx->ustorm_st_context.task_pbl_base.hi =
1548 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1549 ictx->ustorm_st_context.tce_phy_addr.lo =
1550 iscsi->task_array_info.pgtbl[0];
1551 ictx->ustorm_st_context.tce_phy_addr.hi =
1552 iscsi->task_array_info.pgtbl[1];
1553 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1554 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1555 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1556 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1557 ISCSI_DEF_MAX_BURST_LEN;
1558 ictx->ustorm_st_context.negotiated_rx |=
1559 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1560 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1561
1562 ictx->cstorm_st_context.hq_pbl_base.lo =
1563 iscsi->hq_info.pgtbl_map & 0xffffffff;
1564 ictx->cstorm_st_context.hq_pbl_base.hi =
1565 (u64) iscsi->hq_info.pgtbl_map >> 32;
1566 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1567 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1568 ictx->cstorm_st_context.task_pbl_base.lo =
1569 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1570 ictx->cstorm_st_context.task_pbl_base.hi =
1571 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1572 /* CSTORM and USTORM initialization is different, CSTORM requires
1573 * CQ DB base & not PTE addr */
1574 ictx->cstorm_st_context.cq_db_base.lo =
1575 req1->cq_page_table_addr_lo & PAGE_MASK;
1576 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1577 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1578 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1579 for (i = 0; i < cp->num_cqs; i++) {
1580 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1581 ISCSI_INITIAL_SN;
1582 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1583 ISCSI_INITIAL_SN;
1584 }
1585
1586 ictx->xstorm_ag_context.cdu_reserved =
1587 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1588 ISCSI_CONNECTION_TYPE);
1589 ictx->ustorm_ag_context.cdu_usage =
1590 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1591 ISCSI_CONNECTION_TYPE);
1592 return 0;
1593
1594}
1595
1596static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1597 u32 num, int *work)
1598{
1599 struct iscsi_kwqe_conn_offload1 *req1;
1600 struct iscsi_kwqe_conn_offload2 *req2;
1601 struct cnic_local *cp = dev->cnic_priv;
1602 struct iscsi_kcqe kcqe;
1603 struct kcqe *cqes[1];
1604 u32 l5_cid;
1605 int ret;
1606
1607 if (num < 2) {
1608 *work = num;
1609 return -EINVAL;
1610 }
1611
1612 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1613 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1614 if ((num - 2) < req2->num_additional_wqes) {
1615 *work = num;
1616 return -EINVAL;
1617 }
1618 *work = 2 + req2->num_additional_wqes;;
1619
1620 l5_cid = req1->iscsi_conn_id;
1621 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1622 return -EINVAL;
1623
1624 memset(&kcqe, 0, sizeof(kcqe));
1625 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1626 kcqe.iscsi_conn_id = l5_cid;
1627 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1628
1629 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1630 atomic_dec(&cp->iscsi_conn);
1631 ret = 0;
1632 goto done;
1633 }
1634 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1635 if (ret) {
1636 atomic_dec(&cp->iscsi_conn);
1637 ret = 0;
1638 goto done;
1639 }
1640 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1641 if (ret < 0) {
1642 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1643 atomic_dec(&cp->iscsi_conn);
1644 goto done;
1645 }
1646
1647 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1648 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp->ctx_tbl[l5_cid].cid,
1649 cp->func);
1650
1651done:
1652 cqes[0] = (struct kcqe *) &kcqe;
1653 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1654 return ret;
1655}
1656
1657
1658static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1659{
1660 struct cnic_local *cp = dev->cnic_priv;
1661 struct iscsi_kwqe_conn_update *req =
1662 (struct iscsi_kwqe_conn_update *) kwqe;
1663 void *data;
1664 union l5cm_specific_data l5_data;
1665 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1666 int ret;
1667
1668 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1669 return -EINVAL;
1670
1671 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1672 if (!data)
1673 return -ENOMEM;
1674
1675 memcpy(data, kwqe, sizeof(struct kwqe));
1676
1677 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1678 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1679 return ret;
1680}
1681
1682static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1683{
1684 struct cnic_local *cp = dev->cnic_priv;
1685 struct iscsi_kwqe_conn_destroy *req =
1686 (struct iscsi_kwqe_conn_destroy *) kwqe;
1687 union l5cm_specific_data l5_data;
1688 u32 l5_cid = req->reserved0;
1689 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1690 int ret = 0;
1691 struct iscsi_kcqe kcqe;
1692 struct kcqe *cqes[1];
1693
1694 if (!(ctx->ctx_flags & CTX_FL_OFFLD_START))
1695 goto skip_cfc_delete;
1696
1697 while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
1698 msleep(250);
1699
1700 init_waitqueue_head(&ctx->waitq);
1701 ctx->wait_cond = 0;
1702 memset(&l5_data, 0, sizeof(l5_data));
1703 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
1704 req->context_id,
1705 ETH_CONNECTION_TYPE |
1706 (1 << SPE_HDR_COMMON_RAMROD_SHIFT),
1707 &l5_data);
1708 if (ret == 0)
1709 wait_event(ctx->waitq, ctx->wait_cond);
1710
1711skip_cfc_delete:
1712 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1713
1714 atomic_dec(&cp->iscsi_conn);
1715
1716 memset(&kcqe, 0, sizeof(kcqe));
1717 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1718 kcqe.iscsi_conn_id = l5_cid;
1719 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1720 kcqe.iscsi_conn_context_id = req->context_id;
1721
1722 cqes[0] = (struct kcqe *) &kcqe;
1723 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1724
1725 return ret;
1726}
1727
1728static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1729 struct l4_kwq_connect_req1 *kwqe1,
1730 struct l4_kwq_connect_req3 *kwqe3,
1731 struct l5cm_active_conn_buffer *conn_buf)
1732{
1733 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1734 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1735 &conn_buf->xstorm_conn_buffer;
1736 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1737 &conn_buf->tstorm_conn_buffer;
1738 struct regpair context_addr;
1739 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1740 struct in6_addr src_ip, dst_ip;
1741 int i;
1742 u32 *addrp;
1743
1744 addrp = (u32 *) &conn_addr->local_ip_addr;
1745 for (i = 0; i < 4; i++, addrp++)
1746 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1747
1748 addrp = (u32 *) &conn_addr->remote_ip_addr;
1749 for (i = 0; i < 4; i++, addrp++)
1750 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1751
1752 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1753
1754 xstorm_buf->context_addr.hi = context_addr.hi;
1755 xstorm_buf->context_addr.lo = context_addr.lo;
1756 xstorm_buf->mss = 0xffff;
1757 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1758 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1759 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1760 xstorm_buf->pseudo_header_checksum =
1761 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1762
1763 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1764 tstorm_buf->params |=
1765 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1766 if (kwqe3->ka_timeout) {
1767 tstorm_buf->ka_enable = 1;
1768 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1769 tstorm_buf->ka_interval = kwqe3->ka_interval;
1770 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1771 }
1772 tstorm_buf->rcv_buf = kwqe3->rcv_buf;
1773 tstorm_buf->snd_buf = kwqe3->snd_buf;
1774 tstorm_buf->max_rt_time = 0xffffffff;
1775}
1776
1777static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1778{
1779 struct cnic_local *cp = dev->cnic_priv;
1780 int func = CNIC_FUNC(cp);
1781 u8 *mac = dev->mac_addr;
1782
1783 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1784 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(func), mac[0]);
1785 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1786 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(func), mac[1]);
1787 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1788 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(func), mac[2]);
1789 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1790 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(func), mac[3]);
1791 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1792 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(func), mac[4]);
1793 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1794 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(func), mac[5]);
1795
1796 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1797 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func), mac[5]);
1798 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1799 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
1800 mac[4]);
1801 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1802 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func), mac[3]);
1803 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1804 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
1805 mac[2]);
1806 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1807 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 2,
1808 mac[1]);
1809 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1810 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 3,
1811 mac[0]);
1812}
1813
1814static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
1815{
1816 struct cnic_local *cp = dev->cnic_priv;
1817 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1818 u16 tstorm_flags = 0;
1819
1820 if (tcp_ts) {
1821 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1822 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1823 }
1824
1825 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1826 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), xstorm_flags);
1827
1828 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1829 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), tstorm_flags);
1830}
1831
1832static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
1833 u32 num, int *work)
1834{
1835 struct cnic_local *cp = dev->cnic_priv;
1836 struct l4_kwq_connect_req1 *kwqe1 =
1837 (struct l4_kwq_connect_req1 *) wqes[0];
1838 struct l4_kwq_connect_req3 *kwqe3;
1839 struct l5cm_active_conn_buffer *conn_buf;
1840 struct l5cm_conn_addr_params *conn_addr;
1841 union l5cm_specific_data l5_data;
1842 u32 l5_cid = kwqe1->pg_cid;
1843 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
1844 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1845 int ret;
1846
1847 if (num < 2) {
1848 *work = num;
1849 return -EINVAL;
1850 }
1851
1852 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
1853 *work = 3;
1854 else
1855 *work = 2;
1856
1857 if (num < *work) {
1858 *work = num;
1859 return -EINVAL;
1860 }
1861
1862 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
ddf79b20 1863 netdev_err(dev->netdev, "conn_buf size too big\n");
71034ba8
MC		 1864 return -ENOMEM;
1865 }
1866 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1867 if (!conn_buf)
1868 return -ENOMEM;
1869
1870 memset(conn_buf, 0, sizeof(*conn_buf));
1871
1872 conn_addr = &conn_buf->conn_addr_buf;
1873 conn_addr->remote_addr_0 = csk->ha[0];
1874 conn_addr->remote_addr_1 = csk->ha[1];
1875 conn_addr->remote_addr_2 = csk->ha[2];
1876 conn_addr->remote_addr_3 = csk->ha[3];
1877 conn_addr->remote_addr_4 = csk->ha[4];
1878 conn_addr->remote_addr_5 = csk->ha[5];
1879
1880 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
1881 struct l4_kwq_connect_req2 *kwqe2 =
1882 (struct l4_kwq_connect_req2 *) wqes[1];
1883
1884 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
1885 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
1886 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
1887
1888 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
1889 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
1890 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
1891 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
1892 }
1893 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
1894
1895 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
1896 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
1897 conn_addr->local_tcp_port = kwqe1->src_port;
1898 conn_addr->remote_tcp_port = kwqe1->dst_port;
1899
1900 conn_addr->pmtu = kwqe3->pmtu;
1901 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
1902
1903 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1904 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->func), csk->vlan_id);
1905
1906 cnic_bnx2x_set_tcp_timestamp(dev,
1907 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
1908
1909 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
1910 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1911 if (!ret)
1912 ctx->ctx_flags |= CTX_FL_OFFLD_START;
1913
1914 return ret;
1915}
1916
1917static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
1918{
1919 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
1920 union l5cm_specific_data l5_data;
1921 int ret;
1922
1923 memset(&l5_data, 0, sizeof(l5_data));
1924 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
1925 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1926 return ret;
1927}
1928
1929static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
1930{
1931 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
1932 union l5cm_specific_data l5_data;
1933 int ret;
1934
1935 memset(&l5_data, 0, sizeof(l5_data));
1936 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
1937 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1938 return ret;
1939}
1940static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
1941{
1942 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
1943 struct l4_kcq kcqe;
1944 struct kcqe *cqes[1];
1945
1946 memset(&kcqe, 0, sizeof(kcqe));
1947 kcqe.pg_host_opaque = req->host_opaque;
1948 kcqe.pg_cid = req->host_opaque;
1949 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
1950 cqes[0] = (struct kcqe *) &kcqe;
1951 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
1952 return 0;
1953}
1954
1955static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
1956{
1957 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
1958 struct l4_kcq kcqe;
1959 struct kcqe *cqes[1];
1960
1961 memset(&kcqe, 0, sizeof(kcqe));
1962 kcqe.pg_host_opaque = req->pg_host_opaque;
1963 kcqe.pg_cid = req->pg_cid;
1964 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
1965 cqes[0] = (struct kcqe *) &kcqe;
1966 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
1967 return 0;
1968}
1969
1970static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1971 u32 num_wqes)
1972{
1973 int i, work, ret;
1974 u32 opcode;
1975 struct kwqe *kwqe;
1976
1977 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1978 return -EAGAIN; /* bnx2 is down */
1979
1980 for (i = 0; i < num_wqes; ) {
1981 kwqe = wqes[i];
1982 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
1983 work = 1;
1984
1985 switch (opcode) {
1986 case ISCSI_KWQE_OPCODE_INIT1:
1987 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
1988 break;
1989 case ISCSI_KWQE_OPCODE_INIT2:
1990 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
1991 break;
1992 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
1993 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
1994 num_wqes - i, &work);
1995 break;
1996 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
1997 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
1998 break;
1999 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2000 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2001 break;
2002 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2003 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2004 &work);
2005 break;
2006 case L4_KWQE_OPCODE_VALUE_CLOSE:
2007 ret = cnic_bnx2x_close(dev, kwqe);
2008 break;
2009 case L4_KWQE_OPCODE_VALUE_RESET:
2010 ret = cnic_bnx2x_reset(dev, kwqe);
2011 break;
2012 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2013 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2014 break;
2015 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2016 ret = cnic_bnx2x_update_pg(dev, kwqe);
2017 break;
2018 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2019 ret = 0;
2020 break;
2021 default:
2022 ret = 0;
ddf79b20
JP		 2023 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2024 opcode);
71034ba8
MC		 2025 break;
2026 }
2027 if (ret < 0)
ddf79b20
JP		 2028 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2029 opcode);
71034ba8
MC		 2030 i += work;
2031 }
2032 return 0;
2033}
2034
a4636960
MC		 2035static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2036{
2037 struct cnic_local *cp = dev->cnic_priv;
2038 int i, j;
2039
2040 i = 0;
2041 j = 1;
2042 while (num_cqes) {
2043 struct cnic_ulp_ops *ulp_ops;
2044 int ulp_type;
2045 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2046 u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
2047
2048 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2049 cnic_kwq_completion(dev, 1);
2050
2051 while (j < num_cqes) {
2052 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2053
2054 if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
2055 break;
2056
2057 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2058 cnic_kwq_completion(dev, 1);
2059 j++;
2060 }
2061
2062 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2063 ulp_type = CNIC_ULP_RDMA;
2064 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2065 ulp_type = CNIC_ULP_ISCSI;
2066 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2067 ulp_type = CNIC_ULP_L4;
2068 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2069 goto end;
2070 else {
ddf79b20
JP		 2071 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2072 kcqe_op_flag);
a4636960
MC		 2073 goto end;
2074 }
2075
2076 rcu_read_lock();
2077 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2078 if (likely(ulp_ops)) {
2079 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2080 cp->completed_kcq + i, j);
2081 }
2082 rcu_read_unlock();
2083end:
2084 num_cqes -= j;
2085 i += j;
2086 j = 1;
2087 }
2088 return;
2089}
2090
71034ba8
MC		 2091static u16 cnic_bnx2_next_idx(u16 idx)
2092{
2093 return idx + 1;
2094}
2095
2096static u16 cnic_bnx2_hw_idx(u16 idx)
2097{
2098 return idx;
2099}
2100
2101static u16 cnic_bnx2x_next_idx(u16 idx)
a4636960 2102{
71034ba8
MC		 2103 idx++;
2104 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2105 idx++;
2106
2107 return idx;
a4636960
MC		 2108}
2109
71034ba8 2110static u16 cnic_bnx2x_hw_idx(u16 idx)
a4636960 2111{
71034ba8
MC		 2112 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2113 idx++;
a4636960
MC		 2114 return idx;
2115}
2116
2117static int cnic_get_kcqes(struct cnic_dev *dev, u16 hw_prod, u16 *sw_prod)
2118{
2119 struct cnic_local *cp = dev->cnic_priv;
2120 u16 i, ri, last;
2121 struct kcqe *kcqe;
2122 int kcqe_cnt = 0, last_cnt = 0;
2123
2124 i = ri = last = *sw_prod;
2125 ri &= MAX_KCQ_IDX;
2126
2127 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2128 kcqe = &cp->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2129 cp->completed_kcq[kcqe_cnt++] = kcqe;
2130 i = cp->next_idx(i);
2131 ri = i & MAX_KCQ_IDX;
2132 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2133 last_cnt = kcqe_cnt;
2134 last = i;
2135 }
2136 }
2137
2138 *sw_prod = last;
2139 return last_cnt;
2140}
2141
86b53606 2142static void cnic_chk_pkt_rings(struct cnic_local *cp)
a4636960
MC		 2143{
2144 u16 rx_cons = *cp->rx_cons_ptr;
2145 u16 tx_cons = *cp->tx_cons_ptr;
2146
2147 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2148 cp->tx_cons = tx_cons;
2149 cp->rx_cons = rx_cons;
71034ba8 2150
a4636960
MC		 2151 uio_event_notify(cp->cnic_uinfo);
2152 }
2153}
2154
2155static int cnic_service_bnx2(void *data, void *status_blk)
2156{
2157 struct cnic_dev *dev = data;
2158 struct status_block *sblk = status_blk;
2159 struct cnic_local *cp = dev->cnic_priv;
2160 u32 status_idx = sblk->status_idx;
2161 u16 hw_prod, sw_prod;
2162 int kcqe_cnt;
2163
2164 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2165 return status_idx;
2166
2167 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2168
2169 hw_prod = sblk->status_completion_producer_index;
2170 sw_prod = cp->kcq_prod_idx;
2171 while (sw_prod != hw_prod) {
2172 kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
2173 if (kcqe_cnt == 0)
2174 goto done;
2175
2176 service_kcqes(dev, kcqe_cnt);
2177
2178 /* Tell compiler that status_blk fields can change. */
2179 barrier();
2180 if (status_idx != sblk->status_idx) {
2181 status_idx = sblk->status_idx;
2182 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2183 hw_prod = sblk->status_completion_producer_index;
2184 } else
2185 break;
2186 }
2187
2188done:
2189 CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
2190
2191 cp->kcq_prod_idx = sw_prod;
2192
86b53606 2193 cnic_chk_pkt_rings(cp);
a4636960
MC		 2194 return status_idx;
2195}
2196
2197static void cnic_service_bnx2_msix(unsigned long data)
2198{
2199 struct cnic_dev *dev = (struct cnic_dev *) data;
2200 struct cnic_local *cp = dev->cnic_priv;
2201 struct status_block_msix *status_blk = cp->bnx2_status_blk;
2202 u32 status_idx = status_blk->status_idx;
2203 u16 hw_prod, sw_prod;
2204 int kcqe_cnt;
2205
2206 cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
2207
2208 hw_prod = status_blk->status_completion_producer_index;
2209 sw_prod = cp->kcq_prod_idx;
2210 while (sw_prod != hw_prod) {
2211 kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
2212 if (kcqe_cnt == 0)
2213 goto done;
2214
2215 service_kcqes(dev, kcqe_cnt);
2216
2217 /* Tell compiler that status_blk fields can change. */
2218 barrier();
2219 if (status_idx != status_blk->status_idx) {
2220 status_idx = status_blk->status_idx;
2221 cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
2222 hw_prod = status_blk->status_completion_producer_index;
2223 } else
2224 break;
2225 }
2226
2227done:
2228 CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
2229 cp->kcq_prod_idx = sw_prod;
2230
86b53606 2231 cnic_chk_pkt_rings(cp);
a4636960
MC		 2232
2233 cp->last_status_idx = status_idx;
2234 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2235 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2236}
2237
2238static irqreturn_t cnic_irq(int irq, void *dev_instance)
2239{
2240 struct cnic_dev *dev = dev_instance;
2241 struct cnic_local *cp = dev->cnic_priv;
2242 u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
2243
2244 if (cp->ack_int)
2245 cp->ack_int(dev);
2246
2247 prefetch(cp->status_blk);
2248 prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2249
2250 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2251 tasklet_schedule(&cp->cnic_irq_task);
2252
2253 return IRQ_HANDLED;
2254}
2255
71034ba8
MC		 2256static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2257 u16 index, u8 op, u8 update)
2258{
2259 struct cnic_local *cp = dev->cnic_priv;
2260 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2261 COMMAND_REG_INT_ACK);
2262 struct igu_ack_register igu_ack;
2263
2264 igu_ack.status_block_index = index;
2265 igu_ack.sb_id_and_flags =
2266 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2267 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2268 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2269 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2270
2271 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2272}
2273
2274static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2275{
2276 struct cnic_local *cp = dev->cnic_priv;
2277
2278 cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, 0,
2279 IGU_INT_DISABLE, 0);
2280}
2281
2282static void cnic_service_bnx2x_bh(unsigned long data)
2283{
2284 struct cnic_dev *dev = (struct cnic_dev *) data;
2285 struct cnic_local *cp = dev->cnic_priv;
2286 u16 hw_prod, sw_prod;
2287 struct cstorm_status_block_c *sblk =
2288 &cp->bnx2x_status_blk->c_status_block;
2289 u32 status_idx = sblk->status_block_index;
2290 int kcqe_cnt;
2291
2292 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2293 return;
2294
2295 hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
2296 hw_prod = cp->hw_idx(hw_prod);
2297 sw_prod = cp->kcq_prod_idx;
2298 while (sw_prod != hw_prod) {
2299 kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
2300 if (kcqe_cnt == 0)
2301 goto done;
2302
2303 service_kcqes(dev, kcqe_cnt);
2304
2305 /* Tell compiler that sblk fields can change. */
2306 barrier();
2307 if (status_idx == sblk->status_block_index)
2308 break;
2309
2310 status_idx = sblk->status_block_index;
2311 hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
2312 hw_prod = cp->hw_idx(hw_prod);
2313 }
2314
2315done:
2316 CNIC_WR16(dev, cp->kcq_io_addr, sw_prod + MAX_KCQ_IDX);
2317 cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID,
2318 status_idx, IGU_INT_ENABLE, 1);
2319
2320 cp->kcq_prod_idx = sw_prod;
2321 return;
2322}
2323
2324static int cnic_service_bnx2x(void *data, void *status_blk)
2325{
2326 struct cnic_dev *dev = data;
2327 struct cnic_local *cp = dev->cnic_priv;
2328 u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
2329
2330 prefetch(cp->status_blk);
2331 prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2332
2333 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2334 tasklet_schedule(&cp->cnic_irq_task);
2335
2336 cnic_chk_pkt_rings(cp);
2337
2338 return 0;
2339}
2340
a4636960
MC		 2341static void cnic_ulp_stop(struct cnic_dev *dev)
2342{
2343 struct cnic_local *cp = dev->cnic_priv;
2344 int if_type;
2345
6d7760a8
MC		 2346 if (cp->cnic_uinfo)
2347 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2348
a4636960
MC		 2349 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2350 struct cnic_ulp_ops *ulp_ops;
2351
681dbd71
MC		 2352 mutex_lock(&cnic_lock);
2353 ulp_ops = cp->ulp_ops[if_type];
2354 if (!ulp_ops) {
2355 mutex_unlock(&cnic_lock);
a4636960 2356 continue;
681dbd71
MC		 2357 }
2358 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2359 mutex_unlock(&cnic_lock);
a4636960
MC		 2360
2361 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2362 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
681dbd71
MC		 2363
2364 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
a4636960 2365 }
a4636960
MC		 2366}
2367
2368static void cnic_ulp_start(struct cnic_dev *dev)
2369{
2370 struct cnic_local *cp = dev->cnic_priv;
2371 int if_type;
2372
a4636960
MC		 2373 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2374 struct cnic_ulp_ops *ulp_ops;
2375
681dbd71
MC		 2376 mutex_lock(&cnic_lock);
2377 ulp_ops = cp->ulp_ops[if_type];
2378 if (!ulp_ops || !ulp_ops->cnic_start) {
2379 mutex_unlock(&cnic_lock);
a4636960 2380 continue;
681dbd71
MC		 2381 }
2382 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2383 mutex_unlock(&cnic_lock);
a4636960
MC		 2384
2385 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2386 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
681dbd71
MC		 2387
2388 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
a4636960 2389 }
a4636960
MC		 2390}
2391
2392static int cnic_ctl(void *data, struct cnic_ctl_info *info)
2393{
2394 struct cnic_dev *dev = data;
2395
2396 switch (info->cmd) {
2397 case CNIC_CTL_STOP_CMD:
2398 cnic_hold(dev);
a4636960
MC		 2399
2400 cnic_ulp_stop(dev);
2401 cnic_stop_hw(dev);
2402
a4636960
MC		 2403 cnic_put(dev);
2404 break;
2405 case CNIC_CTL_START_CMD:
2406 cnic_hold(dev);
a4636960
MC		 2407
2408 if (!cnic_start_hw(dev))
2409 cnic_ulp_start(dev);
2410
a4636960
MC		 2411 cnic_put(dev);
2412 break;
71034ba8
MC		 2413 case CNIC_CTL_COMPLETION_CMD: {
2414 u32 cid = BNX2X_SW_CID(info->data.comp.cid);
2415 u32 l5_cid;
2416 struct cnic_local *cp = dev->cnic_priv;
2417
2418 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
2419 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2420
2421 ctx->wait_cond = 1;
2422 wake_up(&ctx->waitq);
2423 }
2424 break;
2425 }
a4636960
MC		 2426 default:
2427 return -EINVAL;
2428 }
2429 return 0;
2430}
2431
2432static void cnic_ulp_init(struct cnic_dev *dev)
2433{
2434 int i;
2435 struct cnic_local *cp = dev->cnic_priv;
2436
a4636960
MC		 2437 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2438 struct cnic_ulp_ops *ulp_ops;
2439
7fc1ece4
MC		 2440 mutex_lock(&cnic_lock);
2441 ulp_ops = cnic_ulp_tbl[i];
2442 if (!ulp_ops || !ulp_ops->cnic_init) {
2443 mutex_unlock(&cnic_lock);
a4636960 2444 continue;
7fc1ece4
MC		 2445 }
2446 ulp_get(ulp_ops);
2447 mutex_unlock(&cnic_lock);
a4636960
MC		 2448
2449 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2450 ulp_ops->cnic_init(dev);
2451
7fc1ece4 2452 ulp_put(ulp_ops);
a4636960 2453 }
a4636960
MC		 2454}
2455
2456static void cnic_ulp_exit(struct cnic_dev *dev)
2457{
2458 int i;
2459 struct cnic_local *cp = dev->cnic_priv;
2460
a4636960
MC		 2461 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2462 struct cnic_ulp_ops *ulp_ops;
2463
7fc1ece4
MC		 2464 mutex_lock(&cnic_lock);
2465 ulp_ops = cnic_ulp_tbl[i];
2466 if (!ulp_ops || !ulp_ops->cnic_exit) {
2467 mutex_unlock(&cnic_lock);
a4636960 2468 continue;
7fc1ece4
MC		 2469 }
2470 ulp_get(ulp_ops);
2471 mutex_unlock(&cnic_lock);
a4636960
MC		 2472
2473 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2474 ulp_ops->cnic_exit(dev);
2475
7fc1ece4 2476 ulp_put(ulp_ops);
a4636960 2477 }
a4636960
MC		 2478}
2479
2480static int cnic_cm_offload_pg(struct cnic_sock *csk)
2481{
2482 struct cnic_dev *dev = csk->dev;
2483 struct l4_kwq_offload_pg *l4kwqe;
2484 struct kwqe *wqes[1];
2485
2486 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
2487 memset(l4kwqe, 0, sizeof(*l4kwqe));
2488 wqes[0] = (struct kwqe *) l4kwqe;
2489
2490 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
2491 l4kwqe->flags =
2492 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
2493 l4kwqe->l2hdr_nbytes = ETH_HLEN;
2494
2495 l4kwqe->da0 = csk->ha[0];
2496 l4kwqe->da1 = csk->ha[1];
2497 l4kwqe->da2 = csk->ha[2];
2498 l4kwqe->da3 = csk->ha[3];
2499 l4kwqe->da4 = csk->ha[4];
2500 l4kwqe->da5 = csk->ha[5];
2501
2502 l4kwqe->sa0 = dev->mac_addr[0];
2503 l4kwqe->sa1 = dev->mac_addr[1];
2504 l4kwqe->sa2 = dev->mac_addr[2];
2505 l4kwqe->sa3 = dev->mac_addr[3];
2506 l4kwqe->sa4 = dev->mac_addr[4];
2507 l4kwqe->sa5 = dev->mac_addr[5];
2508
2509 l4kwqe->etype = ETH_P_IP;
a9736c08 2510 l4kwqe->ipid_start = DEF_IPID_START;
a4636960
MC		 2511 l4kwqe->host_opaque = csk->l5_cid;
2512
2513 if (csk->vlan_id) {
2514 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
2515 l4kwqe->vlan_tag = csk->vlan_id;
2516 l4kwqe->l2hdr_nbytes += 4;
2517 }
2518
2519 return dev->submit_kwqes(dev, wqes, 1);
2520}
2521
2522static int cnic_cm_update_pg(struct cnic_sock *csk)
2523{
2524 struct cnic_dev *dev = csk->dev;
2525 struct l4_kwq_update_pg *l4kwqe;
2526 struct kwqe *wqes[1];
2527
2528 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
2529 memset(l4kwqe, 0, sizeof(*l4kwqe));
2530 wqes[0] = (struct kwqe *) l4kwqe;
2531
2532 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
2533 l4kwqe->flags =
2534 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
2535 l4kwqe->pg_cid = csk->pg_cid;
2536
2537 l4kwqe->da0 = csk->ha[0];
2538 l4kwqe->da1 = csk->ha[1];
2539 l4kwqe->da2 = csk->ha[2];
2540 l4kwqe->da3 = csk->ha[3];
2541 l4kwqe->da4 = csk->ha[4];
2542 l4kwqe->da5 = csk->ha[5];
2543
2544 l4kwqe->pg_host_opaque = csk->l5_cid;
2545 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
2546
2547 return dev->submit_kwqes(dev, wqes, 1);
2548}
2549
2550static int cnic_cm_upload_pg(struct cnic_sock *csk)
2551{
2552 struct cnic_dev *dev = csk->dev;
2553 struct l4_kwq_upload *l4kwqe;
2554 struct kwqe *wqes[1];
2555
2556 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
2557 memset(l4kwqe, 0, sizeof(*l4kwqe));
2558 wqes[0] = (struct kwqe *) l4kwqe;
2559
2560 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
2561 l4kwqe->flags =
2562 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
2563 l4kwqe->cid = csk->pg_cid;
2564
2565 return dev->submit_kwqes(dev, wqes, 1);
2566}
2567
2568static int cnic_cm_conn_req(struct cnic_sock *csk)
2569{
2570 struct cnic_dev *dev = csk->dev;
2571 struct l4_kwq_connect_req1 *l4kwqe1;
2572 struct l4_kwq_connect_req2 *l4kwqe2;
2573 struct l4_kwq_connect_req3 *l4kwqe3;
2574 struct kwqe *wqes[3];
2575 u8 tcp_flags = 0;
2576 int num_wqes = 2;
2577
2578 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
2579 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
2580 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
2581 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
2582 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
2583 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
2584
2585 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
2586 l4kwqe3->flags =
2587 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
2588 l4kwqe3->ka_timeout = csk->ka_timeout;
2589 l4kwqe3->ka_interval = csk->ka_interval;
2590 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
2591 l4kwqe3->tos = csk->tos;
2592 l4kwqe3->ttl = csk->ttl;
2593 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
2594 l4kwqe3->pmtu = csk->mtu;
2595 l4kwqe3->rcv_buf = csk->rcv_buf;
2596 l4kwqe3->snd_buf = csk->snd_buf;
2597 l4kwqe3->seed = csk->seed;
2598
2599 wqes[0] = (struct kwqe *) l4kwqe1;
2600 if (test_bit(SK_F_IPV6, &csk->flags)) {
2601 wqes[1] = (struct kwqe *) l4kwqe2;
2602 wqes[2] = (struct kwqe *) l4kwqe3;
2603 num_wqes = 3;
2604
2605 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
2606 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
2607 l4kwqe2->flags =
2608 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
2609 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
2610 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
2611 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
2612 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
2613 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
2614 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
2615 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
2616 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
2617 sizeof(struct tcphdr);
2618 } else {
2619 wqes[1] = (struct kwqe *) l4kwqe3;
2620 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
2621 sizeof(struct tcphdr);
2622 }
2623
2624 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
2625 l4kwqe1->flags =
2626 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
2627 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
2628 l4kwqe1->cid = csk->cid;
2629 l4kwqe1->pg_cid = csk->pg_cid;
2630 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
2631 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
2632 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
2633 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
2634 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
2635 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
2636 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
2637 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
2638 if (csk->tcp_flags & SK_TCP_NAGLE)
2639 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
2640 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
2641 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
2642 if (csk->tcp_flags & SK_TCP_SACK)
2643 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
2644 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
2645 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
2646
2647 l4kwqe1->tcp_flags = tcp_flags;
2648
2649 return dev->submit_kwqes(dev, wqes, num_wqes);
2650}
2651
2652static int cnic_cm_close_req(struct cnic_sock *csk)
2653{
2654 struct cnic_dev *dev = csk->dev;
2655 struct l4_kwq_close_req *l4kwqe;
2656 struct kwqe *wqes[1];
2657
2658 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
2659 memset(l4kwqe, 0, sizeof(*l4kwqe));
2660 wqes[0] = (struct kwqe *) l4kwqe;
2661
2662 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
2663 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
2664 l4kwqe->cid = csk->cid;
2665
2666 return dev->submit_kwqes(dev, wqes, 1);
2667}
2668
2669static int cnic_cm_abort_req(struct cnic_sock *csk)
2670{
2671 struct cnic_dev *dev = csk->dev;
2672 struct l4_kwq_reset_req *l4kwqe;
2673 struct kwqe *wqes[1];
2674
2675 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
2676 memset(l4kwqe, 0, sizeof(*l4kwqe));
2677 wqes[0] = (struct kwqe *) l4kwqe;
2678
2679 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
2680 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
2681 l4kwqe->cid = csk->cid;
2682
2683 return dev->submit_kwqes(dev, wqes, 1);
2684}
2685
2686static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
2687 u32 l5_cid, struct cnic_sock **csk, void *context)
2688{
2689 struct cnic_local *cp = dev->cnic_priv;
2690 struct cnic_sock *csk1;
2691
2692 if (l5_cid >= MAX_CM_SK_TBL_SZ)
2693 return -EINVAL;
2694
2695 csk1 = &cp->csk_tbl[l5_cid];
2696 if (atomic_read(&csk1->ref_count))
2697 return -EAGAIN;
2698
2699 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
2700 return -EBUSY;
2701
2702 csk1->dev = dev;
2703 csk1->cid = cid;
2704 csk1->l5_cid = l5_cid;
2705 csk1->ulp_type = ulp_type;
2706 csk1->context = context;
2707
2708 csk1->ka_timeout = DEF_KA_TIMEOUT;
2709 csk1->ka_interval = DEF_KA_INTERVAL;
2710 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
2711 csk1->tos = DEF_TOS;
2712 csk1->ttl = DEF_TTL;
2713 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
2714 csk1->rcv_buf = DEF_RCV_BUF;
2715 csk1->snd_buf = DEF_SND_BUF;
2716 csk1->seed = DEF_SEED;
2717
2718 *csk = csk1;
2719 return 0;
2720}
2721
2722static void cnic_cm_cleanup(struct cnic_sock *csk)
2723{
2724 if (csk->src_port) {
2725 struct cnic_dev *dev = csk->dev;
2726 struct cnic_local *cp = dev->cnic_priv;
2727
2728 cnic_free_id(&cp->csk_port_tbl, csk->src_port);
2729 csk->src_port = 0;
2730 }
2731}
2732
2733static void cnic_close_conn(struct cnic_sock *csk)
2734{
2735 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
2736 cnic_cm_upload_pg(csk);
2737 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
2738 }
2739 cnic_cm_cleanup(csk);
2740}
2741
2742static int cnic_cm_destroy(struct cnic_sock *csk)
2743{
2744 if (!cnic_in_use(csk))
2745 return -EINVAL;
2746
2747 csk_hold(csk);
2748 clear_bit(SK_F_INUSE, &csk->flags);
2749 smp_mb__after_clear_bit();
2750 while (atomic_read(&csk->ref_count) != 1)
2751 msleep(1);
2752 cnic_cm_cleanup(csk);
2753
2754 csk->flags = 0;
2755 csk_put(csk);
2756 return 0;
2757}
2758
2759static inline u16 cnic_get_vlan(struct net_device *dev,
2760 struct net_device **vlan_dev)
2761{
2762 if (dev->priv_flags & IFF_802_1Q_VLAN) {
2763 *vlan_dev = vlan_dev_real_dev(dev);
2764 return vlan_dev_vlan_id(dev);
2765 }
2766 *vlan_dev = dev;
2767 return 0;
2768}
2769
2770static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
2771 struct dst_entry **dst)
2772{
faea56c9 2773#if defined(CONFIG_INET)
a4636960
MC		 2774 struct flowi fl;
2775 int err;
2776 struct rtable *rt;
2777
2778 memset(&fl, 0, sizeof(fl));
2779 fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
2780
2781 err = ip_route_output_key(&init_net, &rt, &fl);
2782 if (!err)
2783 *dst = &rt->u.dst;
2784 return err;
faea56c9
RD		 2785#else
2786 return -ENETUNREACH;
2787#endif
a4636960
MC		 2788}
2789
2790static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
2791 struct dst_entry **dst)
2792{
faea56c9 2793#if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
a4636960
MC		 2794 struct flowi fl;
2795
2796 memset(&fl, 0, sizeof(fl));
2797 ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
2798 if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
2799 fl.oif = dst_addr->sin6_scope_id;
2800
2801 *dst = ip6_route_output(&init_net, NULL, &fl);
2802 if (*dst)
2803 return 0;
2804#endif
2805
2806 return -ENETUNREACH;
2807}
2808
2809static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
2810 int ulp_type)
2811{
2812 struct cnic_dev *dev = NULL;
2813 struct dst_entry *dst;
2814 struct net_device *netdev = NULL;
2815 int err = -ENETUNREACH;
2816
2817 if (dst_addr->sin_family == AF_INET)
2818 err = cnic_get_v4_route(dst_addr, &dst);
2819 else if (dst_addr->sin_family == AF_INET6) {
2820 struct sockaddr_in6 *dst_addr6 =
2821 (struct sockaddr_in6 *) dst_addr;
2822
2823 err = cnic_get_v6_route(dst_addr6, &dst);
2824 } else
2825 return NULL;
2826
2827 if (err)
2828 return NULL;
2829
2830 if (!dst->dev)
2831 goto done;
2832
2833 cnic_get_vlan(dst->dev, &netdev);
2834
2835 dev = cnic_from_netdev(netdev);
2836
2837done:
2838 dst_release(dst);
2839 if (dev)
2840 cnic_put(dev);
2841 return dev;
2842}
2843
2844static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2845{
2846 struct cnic_dev *dev = csk->dev;
2847 struct cnic_local *cp = dev->cnic_priv;
2848
2849 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
2850}
2851
2852static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2853{
2854 struct cnic_dev *dev = csk->dev;
2855 struct cnic_local *cp = dev->cnic_priv;
2856 int is_v6, err, rc = -ENETUNREACH;
2857 struct dst_entry *dst;
2858 struct net_device *realdev;
2859 u32 local_port;
2860
2861 if (saddr->local.v6.sin6_family == AF_INET6 &&
2862 saddr->remote.v6.sin6_family == AF_INET6)
2863 is_v6 = 1;
2864 else if (saddr->local.v4.sin_family == AF_INET &&
2865 saddr->remote.v4.sin_family == AF_INET)
2866 is_v6 = 0;
2867 else
2868 return -EINVAL;
2869
2870 clear_bit(SK_F_IPV6, &csk->flags);
2871
2872 if (is_v6) {
faea56c9 2873#if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
a4636960
MC		 2874 set_bit(SK_F_IPV6, &csk->flags);
2875 err = cnic_get_v6_route(&saddr->remote.v6, &dst);
2876 if (err)
2877 return err;
2878
2879 if (!dst || dst->error || !dst->dev)
2880 goto err_out;
2881
2882 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
2883 sizeof(struct in6_addr));
2884 csk->dst_port = saddr->remote.v6.sin6_port;
2885 local_port = saddr->local.v6.sin6_port;
2886#else
2887 return rc;
2888#endif
2889
2890 } else {
2891 err = cnic_get_v4_route(&saddr->remote.v4, &dst);
2892 if (err)
2893 return err;
2894
2895 if (!dst || dst->error || !dst->dev)
2896 goto err_out;
2897
2898 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
2899 csk->dst_port = saddr->remote.v4.sin_port;
2900 local_port = saddr->local.v4.sin_port;
2901 }
2902
2903 csk->vlan_id = cnic_get_vlan(dst->dev, &realdev);
2904 if (realdev != dev->netdev)
2905 goto err_out;
2906
2907 if (local_port >= CNIC_LOCAL_PORT_MIN &&
2908 local_port < CNIC_LOCAL_PORT_MAX) {
2909 if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
2910 local_port = 0;
2911 } else
2912 local_port = 0;
2913
2914 if (!local_port) {
2915 local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
2916 if (local_port == -1) {
2917 rc = -ENOMEM;
2918 goto err_out;
2919 }
2920 }
2921 csk->src_port = local_port;
2922
2923 csk->mtu = dst_mtu(dst);
2924 rc = 0;
2925
2926err_out:
2927 dst_release(dst);
2928 return rc;
2929}
2930
2931static void cnic_init_csk_state(struct cnic_sock *csk)
2932{
2933 csk->state = 0;
2934 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
2935 clear_bit(SK_F_CLOSING, &csk->flags);
2936}
2937
2938static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2939{
2940 int err = 0;
2941
2942 if (!cnic_in_use(csk))
2943 return -EINVAL;
2944
2945 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
2946 return -EINVAL;
2947
2948 cnic_init_csk_state(csk);
2949
2950 err = cnic_get_route(csk, saddr);
2951 if (err)
2952 goto err_out;
2953
2954 err = cnic_resolve_addr(csk, saddr);
2955 if (!err)
2956 return 0;
2957
2958err_out:
2959 clear_bit(SK_F_CONNECT_START, &csk->flags);
2960 return err;
2961}
2962
2963static int cnic_cm_abort(struct cnic_sock *csk)
2964{
2965 struct cnic_local *cp = csk->dev->cnic_priv;
2966 u32 opcode;
2967
2968 if (!cnic_in_use(csk))
2969 return -EINVAL;
2970
2971 if (cnic_abort_prep(csk))
2972 return cnic_cm_abort_req(csk);
2973
2974 /* Getting here means that we haven't started connect, or
2975 * connect was not successful.
2976 */
2977
2978 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
2979 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
2980 opcode = csk->state;
2981 else
2982 opcode = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
2983 cp->close_conn(csk, opcode);
2984
2985 return 0;
2986}
2987
2988static int cnic_cm_close(struct cnic_sock *csk)
2989{
2990 if (!cnic_in_use(csk))
2991 return -EINVAL;
2992
2993 if (cnic_close_prep(csk)) {
2994 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
2995 return cnic_cm_close_req(csk);
2996 }
2997 return 0;
2998}
2999
3000static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3001 u8 opcode)
3002{
3003 struct cnic_ulp_ops *ulp_ops;
3004 int ulp_type = csk->ulp_type;
3005
3006 rcu_read_lock();
3007 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3008 if (ulp_ops) {
3009 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3010 ulp_ops->cm_connect_complete(csk);
3011 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3012 ulp_ops->cm_close_complete(csk);
3013 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3014 ulp_ops->cm_remote_abort(csk);
3015 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3016 ulp_ops->cm_abort_complete(csk);
3017 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3018 ulp_ops->cm_remote_close(csk);
3019 }
3020 rcu_read_unlock();
3021}
3022
3023static int cnic_cm_set_pg(struct cnic_sock *csk)
3024{
3025 if (cnic_offld_prep(csk)) {
3026 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3027 cnic_cm_update_pg(csk);
3028 else
3029 cnic_cm_offload_pg(csk);
3030 }
3031 return 0;
3032}
3033
3034static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3035{
3036 struct cnic_local *cp = dev->cnic_priv;
3037 u32 l5_cid = kcqe->pg_host_opaque;
3038 u8 opcode = kcqe->op_code;
3039 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3040
3041 csk_hold(csk);
3042 if (!cnic_in_use(csk))
3043 goto done;
3044
3045 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3046 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3047 goto done;
3048 }
a9736c08
EW		 3049 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3050 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3051 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3052 cnic_cm_upcall(cp, csk,
3053 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3054 goto done;
3055 }
3056
a4636960
MC		 3057 csk->pg_cid = kcqe->pg_cid;
3058 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3059 cnic_cm_conn_req(csk);
3060
3061done:
3062 csk_put(csk);
3063}
3064
3065static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3066{
3067 struct cnic_local *cp = dev->cnic_priv;
3068 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3069 u8 opcode = l4kcqe->op_code;
3070 u32 l5_cid;
3071 struct cnic_sock *csk;
3072
3073 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3074 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3075 cnic_cm_process_offld_pg(dev, l4kcqe);
3076 return;
3077 }
3078
3079 l5_cid = l4kcqe->conn_id;
3080 if (opcode & 0x80)
3081 l5_cid = l4kcqe->cid;
3082 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3083 return;
3084
3085 csk = &cp->csk_tbl[l5_cid];
3086 csk_hold(csk);
3087
3088 if (!cnic_in_use(csk)) {
3089 csk_put(csk);
3090 return;
3091 }
3092
3093 switch (opcode) {
a9736c08
EW		 3094 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3095 if (l4kcqe->status != 0) {
3096 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3097 cnic_cm_upcall(cp, csk,
3098 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3099 }
3100 break;
a4636960
MC		 3101 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3102 if (l4kcqe->status == 0)
3103 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3104
3105 smp_mb__before_clear_bit();
3106 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3107 cnic_cm_upcall(cp, csk, opcode);
3108 break;
3109
3110 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
66883e90
EW		 3111 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
3112 cnic_cm_upcall(cp, csk, opcode);
3113 break;
3114 } else if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags))
a4636960
MC		 3115 csk->state = opcode;
3116 /* fall through */
3117 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3118 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
71034ba8
MC		 3119 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3120 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
a4636960
MC		 3121 cp->close_conn(csk, opcode);
3122 break;
3123
3124 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3125 cnic_cm_upcall(cp, csk, opcode);
3126 break;
3127 }
3128 csk_put(csk);
3129}
3130
3131static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3132{
3133 struct cnic_dev *dev = data;
3134 int i;
3135
3136 for (i = 0; i < num; i++)
3137 cnic_cm_process_kcqe(dev, kcqe[i]);
3138}
3139
3140static struct cnic_ulp_ops cm_ulp_ops = {
3141 .indicate_kcqes = cnic_cm_indicate_kcqe,
3142};
3143
3144static void cnic_cm_free_mem(struct cnic_dev *dev)
3145{
3146 struct cnic_local *cp = dev->cnic_priv;
3147
3148 kfree(cp->csk_tbl);
3149 cp->csk_tbl = NULL;
3150 cnic_free_id_tbl(&cp->csk_port_tbl);
3151}
3152
3153static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3154{
3155 struct cnic_local *cp = dev->cnic_priv;
3156
3157 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3158 GFP_KERNEL);
3159 if (!cp->csk_tbl)
3160 return -ENOMEM;
3161
3162 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3163 CNIC_LOCAL_PORT_MIN)) {
3164 cnic_cm_free_mem(dev);
3165 return -ENOMEM;
3166 }
3167 return 0;
3168}
3169
3170static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3171{
3172 if ((opcode == csk->state) ||
3173 (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED &&
3174 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)) {
3175 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags))
3176 return 1;
3177 }
66883e90
EW		 3178 /* 57710+ only workaround to handle unsolicited RESET_COMP
3179 * which will be treated like a RESET RCVD notification
3180 * which triggers the clean up procedure
3181 */
3182 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
3183 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3184 csk->state = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3185 return 1;
3186 }
3187 }
a4636960
MC		 3188 return 0;
3189}
3190
3191static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3192{
3193 struct cnic_dev *dev = csk->dev;
3194 struct cnic_local *cp = dev->cnic_priv;
3195
3196 clear_bit(SK_F_CONNECT_START, &csk->flags);
66883e90
EW		 3197 cnic_close_conn(csk);
3198 cnic_cm_upcall(cp, csk, opcode);
a4636960
MC		 3199}
3200
3201static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3202{
3203}
3204
3205static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3206{
3207 u32 seed;
3208
3209 get_random_bytes(&seed, 4);
3210 cnic_ctx_wr(dev, 45, 0, seed);
3211 return 0;
3212}
3213
71034ba8
MC		 3214static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3215{
3216 struct cnic_dev *dev = csk->dev;
3217 struct cnic_local *cp = dev->cnic_priv;
3218 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3219 union l5cm_specific_data l5_data;
3220 u32 cmd = 0;
3221 int close_complete = 0;
3222
3223 switch (opcode) {
3224 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3225 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3226 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3227 if (cnic_ready_to_close(csk, opcode))
3228 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3229 break;
3230 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3231 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3232 break;
3233 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3234 close_complete = 1;
3235 break;
3236 }
3237 if (cmd) {
3238 memset(&l5_data, 0, sizeof(l5_data));
3239
3240 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3241 &l5_data);
3242 } else if (close_complete) {
3243 ctx->timestamp = jiffies;
3244 cnic_close_conn(csk);
3245 cnic_cm_upcall(cp, csk, csk->state);
3246 }
3247}
3248
3249static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3250{
3251}
3252
3253static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3254{
3255 struct cnic_local *cp = dev->cnic_priv;
3256 int func = CNIC_FUNC(cp);
3257
3258 cnic_init_bnx2x_mac(dev);
3259 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3260
3261 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
3262 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(func), 0);
3263
3264 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3265 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(func), 1);
3266 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3267 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(func),
3268 DEF_MAX_DA_COUNT);
3269
3270 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3271 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(func), DEF_TTL);
3272 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3273 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(func), DEF_TOS);
3274 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3275 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(func), 2);
3276 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3277 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(func), DEF_SWS_TIMER);
3278
3279 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(func),
3280 DEF_MAX_CWND);
3281 return 0;
3282}
3283
a4636960
MC		 3284static int cnic_cm_open(struct cnic_dev *dev)
3285{
3286 struct cnic_local *cp = dev->cnic_priv;
3287 int err;
3288
3289 err = cnic_cm_alloc_mem(dev);
3290 if (err)
3291 return err;
3292
3293 err = cp->start_cm(dev);
3294
3295 if (err)
3296 goto err_out;
3297
3298 dev->cm_create = cnic_cm_create;
3299 dev->cm_destroy = cnic_cm_destroy;
3300 dev->cm_connect = cnic_cm_connect;
3301 dev->cm_abort = cnic_cm_abort;
3302 dev->cm_close = cnic_cm_close;
3303 dev->cm_select_dev = cnic_cm_select_dev;
3304
3305 cp->ulp_handle[CNIC_ULP_L4] = dev;
3306 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
3307 return 0;
3308
3309err_out:
3310 cnic_cm_free_mem(dev);
3311 return err;
3312}
3313
3314static int cnic_cm_shutdown(struct cnic_dev *dev)
3315{
3316 struct cnic_local *cp = dev->cnic_priv;
3317 int i;
3318
3319 cp->stop_cm(dev);
3320
3321 if (!cp->csk_tbl)
3322 return 0;
3323
3324 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
3325 struct cnic_sock *csk = &cp->csk_tbl[i];
3326
3327 clear_bit(SK_F_INUSE, &csk->flags);
3328 cnic_cm_cleanup(csk);
3329 }
3330 cnic_cm_free_mem(dev);
3331
3332 return 0;
3333}
3334
3335static void cnic_init_context(struct cnic_dev *dev, u32 cid)
3336{
3337 struct cnic_local *cp = dev->cnic_priv;
3338 u32 cid_addr;
3339 int i;
3340
3341 if (CHIP_NUM(cp) == CHIP_NUM_5709)
3342 return;
3343
3344 cid_addr = GET_CID_ADDR(cid);
3345
3346 for (i = 0; i < CTX_SIZE; i += 4)
3347 cnic_ctx_wr(dev, cid_addr, i, 0);
3348}
3349
3350static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
3351{
3352 struct cnic_local *cp = dev->cnic_priv;
3353 int ret = 0, i;
3354 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
3355
3356 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3357 return 0;
3358
3359 for (i = 0; i < cp->ctx_blks; i++) {
3360 int j;
3361 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
3362 u32 val;
3363
3364 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
3365
3366 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
3367 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
3368 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
3369 (u64) cp->ctx_arr[i].mapping >> 32);
3370 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
3371 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3372 for (j = 0; j < 10; j++) {
3373
3374 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
3375 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
3376 break;
3377 udelay(5);
3378 }
3379 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
3380 ret = -EBUSY;
3381 break;
3382 }
3383 }
3384 return ret;
3385}
3386
3387static void cnic_free_irq(struct cnic_dev *dev)
3388{
3389 struct cnic_local *cp = dev->cnic_priv;
3390 struct cnic_eth_dev *ethdev = cp->ethdev;
3391
3392 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3393 cp->disable_int_sync(dev);
3394 tasklet_disable(&cp->cnic_irq_task);
3395 free_irq(ethdev->irq_arr[0].vector, dev);
3396 }
3397}
3398
3399static int cnic_init_bnx2_irq(struct cnic_dev *dev)
3400{
3401 struct cnic_local *cp = dev->cnic_priv;
3402 struct cnic_eth_dev *ethdev = cp->ethdev;
3403
3404 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3405 int err, i = 0;
3406 int sblk_num = cp->status_blk_num;
3407 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
3408 BNX2_HC_SB_CONFIG_1;
3409
3410 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
3411
3412 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
3413 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
3414 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
3415
3416 cp->bnx2_status_blk = cp->status_blk;
3417 cp->last_status_idx = cp->bnx2_status_blk->status_idx;
164165da 3418 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
a4636960
MC		 3419 (unsigned long) dev);
3420 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
3421 "cnic", dev);
3422 if (err) {
3423 tasklet_disable(&cp->cnic_irq_task);
3424 return err;
3425 }
3426 while (cp->bnx2_status_blk->status_completion_producer_index &&
3427 i < 10) {
3428 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
3429 1 << (11 + sblk_num));
3430 udelay(10);
3431 i++;
3432 barrier();
3433 }
3434 if (cp->bnx2_status_blk->status_completion_producer_index) {
3435 cnic_free_irq(dev);
3436 goto failed;
3437 }
3438
3439 } else {
3440 struct status_block *sblk = cp->status_blk;
3441 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
3442 int i = 0;
3443
3444 while (sblk->status_completion_producer_index && i < 10) {
3445 CNIC_WR(dev, BNX2_HC_COMMAND,
3446 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3447 udelay(10);
3448 i++;
3449 barrier();
3450 }
3451 if (sblk->status_completion_producer_index)
3452 goto failed;
3453
3454 }
3455 return 0;
3456
3457failed:
ddf79b20 3458 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
a4636960
MC		 3459 return -EBUSY;
3460}
3461
3462static void cnic_enable_bnx2_int(struct cnic_dev *dev)
3463{
3464 struct cnic_local *cp = dev->cnic_priv;
3465 struct cnic_eth_dev *ethdev = cp->ethdev;
3466
3467 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3468 return;
3469
3470 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3471 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
3472}
3473
3474static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
3475{
3476 struct cnic_local *cp = dev->cnic_priv;
3477 struct cnic_eth_dev *ethdev = cp->ethdev;
3478
3479 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3480 return;
3481
3482 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3483 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3484 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
3485 synchronize_irq(ethdev->irq_arr[0].vector);
3486}
3487
3488static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
3489{
3490 struct cnic_local *cp = dev->cnic_priv;
3491 struct cnic_eth_dev *ethdev = cp->ethdev;
3492 u32 cid_addr, tx_cid, sb_id;
3493 u32 val, offset0, offset1, offset2, offset3;
3494 int i;
3495 struct tx_bd *txbd;
3496 dma_addr_t buf_map;
3497 struct status_block *s_blk = cp->status_blk;
3498
3499 sb_id = cp->status_blk_num;
3500 tx_cid = 20;
3501 cnic_init_context(dev, tx_cid);
3502 cnic_init_context(dev, tx_cid + 1);
3503 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
3504 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3505 struct status_block_msix *sblk = cp->status_blk;
3506
3507 tx_cid = TX_TSS_CID + sb_id - 1;
3508 cnic_init_context(dev, tx_cid);
3509 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
3510 (TX_TSS_CID << 7));
3511 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
3512 }
3513 cp->tx_cons = *cp->tx_cons_ptr;
3514
3515 cid_addr = GET_CID_ADDR(tx_cid);
3516 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
3517 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
3518
3519 for (i = 0; i < PHY_CTX_SIZE; i += 4)
3520 cnic_ctx_wr(dev, cid_addr2, i, 0);
3521
3522 offset0 = BNX2_L2CTX_TYPE_XI;
3523 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
3524 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
3525 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
3526 } else {
3527 offset0 = BNX2_L2CTX_TYPE;
3528 offset1 = BNX2_L2CTX_CMD_TYPE;
3529 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
3530 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
3531 }
3532 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
3533 cnic_ctx_wr(dev, cid_addr, offset0, val);
3534
3535 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3536 cnic_ctx_wr(dev, cid_addr, offset1, val);
3537
3538 txbd = (struct tx_bd *) cp->l2_ring;
3539
3540 buf_map = cp->l2_buf_map;
3541 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
3542 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
3543 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3544 }
3545 val = (u64) cp->l2_ring_map >> 32;
3546 cnic_ctx_wr(dev, cid_addr, offset2, val);
3547 txbd->tx_bd_haddr_hi = val;
3548
3549 val = (u64) cp->l2_ring_map & 0xffffffff;
3550 cnic_ctx_wr(dev, cid_addr, offset3, val);
3551 txbd->tx_bd_haddr_lo = val;
3552}
3553
3554static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
3555{
3556 struct cnic_local *cp = dev->cnic_priv;
3557 struct cnic_eth_dev *ethdev = cp->ethdev;
3558 u32 cid_addr, sb_id, val, coal_reg, coal_val;
3559 int i;
3560 struct rx_bd *rxbd;
3561 struct status_block *s_blk = cp->status_blk;
3562
3563 sb_id = cp->status_blk_num;
3564 cnic_init_context(dev, 2);
3565 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
3566 coal_reg = BNX2_HC_COMMAND;
3567 coal_val = CNIC_RD(dev, coal_reg);
3568 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3569 struct status_block_msix *sblk = cp->status_blk;
3570
3571 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
3572 coal_reg = BNX2_HC_COALESCE_NOW;
3573 coal_val = 1 << (11 + sb_id);
3574 }
3575 i = 0;
3576 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
3577 CNIC_WR(dev, coal_reg, coal_val);
3578 udelay(10);
3579 i++;
3580 barrier();
3581 }
3582 cp->rx_cons = *cp->rx_cons_ptr;
3583
3584 cid_addr = GET_CID_ADDR(2);
3585 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3586 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3587 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
3588
3589 if (sb_id == 0)
d0549382 3590 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
a4636960 3591 else
d0549382 3592 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
a4636960
MC		 3593 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
3594
3595 rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
3596 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3597 dma_addr_t buf_map;
3598 int n = (i % cp->l2_rx_ring_size) + 1;
3599
3600 buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
3601 rxbd->rx_bd_len = cp->l2_single_buf_size;
3602 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3603 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
3604 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3605 }
3606 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
3607 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
3608 rxbd->rx_bd_haddr_hi = val;
3609
3610 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
3611 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
3612 rxbd->rx_bd_haddr_lo = val;
3613
3614 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
3615 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
3616}
3617
3618static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
3619{
3620 struct kwqe *wqes[1], l2kwqe;
3621
3622 memset(&l2kwqe, 0, sizeof(l2kwqe));
3623 wqes[0] = &l2kwqe;
3624 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
3625 (L2_KWQE_OPCODE_VALUE_FLUSH <<
3626 KWQE_OPCODE_SHIFT) | 2;
3627 dev->submit_kwqes(dev, wqes, 1);
3628}
3629
3630static void cnic_set_bnx2_mac(struct cnic_dev *dev)
3631{
3632 struct cnic_local *cp = dev->cnic_priv;
3633 u32 val;
3634
3635 val = cp->func << 2;
3636
3637 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
3638
3639 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3640 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
3641 dev->mac_addr[0] = (u8) (val >> 8);
3642 dev->mac_addr[1] = (u8) val;
3643
3644 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
3645
3646 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3647 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
3648 dev->mac_addr[2] = (u8) (val >> 24);
3649 dev->mac_addr[3] = (u8) (val >> 16);
3650 dev->mac_addr[4] = (u8) (val >> 8);
3651 dev->mac_addr[5] = (u8) val;
3652
3653 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
3654
3655 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
3656 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3657 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
3658
3659 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
3660 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
3661 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
3662}
3663
3664static int cnic_start_bnx2_hw(struct cnic_dev *dev)
3665{
3666 struct cnic_local *cp = dev->cnic_priv;
3667 struct cnic_eth_dev *ethdev = cp->ethdev;
3668 struct status_block *sblk = cp->status_blk;
3669 u32 val;
3670 int err;
3671
3672 cnic_set_bnx2_mac(dev);
3673
3674 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
3675 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3676 if (BCM_PAGE_BITS > 12)
3677 val |= (12 - 8) << 4;
3678 else
3679 val |= (BCM_PAGE_BITS - 8) << 4;
3680
3681 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
3682
3683 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
3684 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
3685 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
3686
3687 err = cnic_setup_5709_context(dev, 1);
3688 if (err)
3689 return err;
3690
3691 cnic_init_context(dev, KWQ_CID);
3692 cnic_init_context(dev, KCQ_CID);
3693
3694 cp->kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
3695 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
3696
3697 cp->max_kwq_idx = MAX_KWQ_IDX;
3698 cp->kwq_prod_idx = 0;
3699 cp->kwq_con_idx = 0;
3700 cp->cnic_local_flags |= CNIC_LCL_FL_KWQ_INIT;
3701
3702 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
3703 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
3704 else
3705 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
3706
3707 /* Initialize the kernel work queue context. */
3708 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3709 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
3710 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_TYPE, val);
3711
3712 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
3713 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
3714
3715 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
3716 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
3717
3718 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
3719 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
3720
3721 val = (u32) cp->kwq_info.pgtbl_map;
3722 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
3723
3724 cp->kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
3725 cp->kcq_io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
3726
3727 cp->kcq_prod_idx = 0;
3728
3729 /* Initialize the kernel complete queue context. */
3730 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3731 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
3732 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_TYPE, val);
3733
3734 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
3735 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
3736
3737 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
3738 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
3739
3740 val = (u32) ((u64) cp->kcq_info.pgtbl_map >> 32);
3741 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
3742
3743 val = (u32) cp->kcq_info.pgtbl_map;
3744 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
3745
3746 cp->int_num = 0;
3747 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3748 u32 sb_id = cp->status_blk_num;
d0549382 3749 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
a4636960
MC		 3750
3751 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
3752 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
3753 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
3754 }
3755
3756 /* Enable Commnad Scheduler notification when we write to the
3757 * host producer index of the kernel contexts. */
3758 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
3759
3760 /* Enable Command Scheduler notification when we write to either
3761 * the Send Queue or Receive Queue producer indexes of the kernel
3762 * bypass contexts. */
3763 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
3764 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
3765
3766 /* Notify COM when the driver post an application buffer. */
3767 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
3768
3769 /* Set the CP and COM doorbells. These two processors polls the
3770 * doorbell for a non zero value before running. This must be done
3771 * after setting up the kernel queue contexts. */
3772 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
3773 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
3774
3775 cnic_init_bnx2_tx_ring(dev);
3776 cnic_init_bnx2_rx_ring(dev);
3777
3778 err = cnic_init_bnx2_irq(dev);
3779 if (err) {
ddf79b20 3780 netdev_err(dev->netdev, "cnic_init_irq failed\n");
a4636960
MC		 3781 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
3782 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
3783 return err;
3784 }
3785
3786 return 0;
3787}
3788
71034ba8
MC		 3789static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
3790{
3791 struct cnic_local *cp = dev->cnic_priv;
3792 struct cnic_eth_dev *ethdev = cp->ethdev;
3793 u32 start_offset = ethdev->ctx_tbl_offset;
3794 int i;
3795
3796 for (i = 0; i < cp->ctx_blks; i++) {
3797 struct cnic_ctx *ctx = &cp->ctx_arr[i];
3798 dma_addr_t map = ctx->mapping;
3799
3800 if (cp->ctx_align) {
3801 unsigned long mask = cp->ctx_align - 1;
3802
3803 map = (map + mask) & ~mask;
3804 }
3805
3806 cnic_ctx_tbl_wr(dev, start_offset + i, map);
3807 }
3808}
3809
3810static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
3811{
3812 struct cnic_local *cp = dev->cnic_priv;
3813 struct cnic_eth_dev *ethdev = cp->ethdev;
3814 int err = 0;
3815
164165da 3816 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
71034ba8
MC		 3817 (unsigned long) dev);
3818 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3819 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
3820 "cnic", dev);
3821 if (err)
3822 tasklet_disable(&cp->cnic_irq_task);
3823 }
3824 return err;
3825}
3826
3827static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
3828{
3829 struct cnic_local *cp = dev->cnic_priv;
3830 u8 sb_id = cp->status_blk_num;
3831 int port = CNIC_PORT(cp);
3832
3833 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
3834 CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
3835 HC_INDEX_C_ISCSI_EQ_CONS),
3836 64 / 12);
3837 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
3838 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
3839 HC_INDEX_C_ISCSI_EQ_CONS), 0);
3840}
3841
3842static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
3843{
3844}
3845
3846static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev)
3847{
3848 struct cnic_local *cp = dev->cnic_priv;
3849 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
3850 struct eth_context *context;
3851 struct regpair context_addr;
3852 dma_addr_t buf_map;
3853 int func = CNIC_FUNC(cp);
3854 int port = CNIC_PORT(cp);
3855 int i;
3856 int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
3857 u32 val;
3858
3859 memset(txbd, 0, BCM_PAGE_SIZE);
3860
3861 buf_map = cp->l2_buf_map;
3862 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
3863 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
3864 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
3865
3866 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
3867 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
3868 reg_bd->addr_hi = start_bd->addr_hi;
3869 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
3870 start_bd->nbytes = cpu_to_le16(0x10);
3871 start_bd->nbd = cpu_to_le16(3);
3872 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
3873 start_bd->general_data = (UNICAST_ADDRESS <<
3874 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
3875 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
3876
3877 }
3878 context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 1, &context_addr);
3879
3880 val = (u64) cp->l2_ring_map >> 32;
3881 txbd->next_bd.addr_hi = cpu_to_le32(val);
3882
3883 context->xstorm_st_context.tx_bd_page_base_hi = val;
3884
3885 val = (u64) cp->l2_ring_map & 0xffffffff;
3886 txbd->next_bd.addr_lo = cpu_to_le32(val);
3887
3888 context->xstorm_st_context.tx_bd_page_base_lo = val;
3889
3890 context->cstorm_st_context.sb_index_number =
3891 HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS;
3892 context->cstorm_st_context.status_block_id = BNX2X_DEF_SB_ID;
3893
3894 context->xstorm_st_context.statistics_data = (cli |
3895 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
3896
3897 context->xstorm_ag_context.cdu_reserved =
3898 CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
3899 CDU_REGION_NUMBER_XCM_AG,
3900 ETH_CONNECTION_TYPE);
3901
3902 /* reset xstorm per client statistics */
3903 val = BAR_XSTRORM_INTMEM +
3904 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
3905 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
3906 CNIC_WR(dev, val + i * 4, 0);
3907
3908 cp->tx_cons_ptr =
3909 &cp->bnx2x_def_status_blk->c_def_status_block.index_values[
3910 HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS];
3911}
3912
3913static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev)
3914{
3915 struct cnic_local *cp = dev->cnic_priv;
3916 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
3917 BCM_PAGE_SIZE);
3918 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
3919 (cp->l2_ring + (2 * BCM_PAGE_SIZE));
3920 struct eth_context *context;
3921 struct regpair context_addr;
3922 int i;
3923 int port = CNIC_PORT(cp);
3924 int func = CNIC_FUNC(cp);
3925 int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
3926 u32 val;
3927 struct tstorm_eth_client_config tstorm_client = {0};
3928
3929 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
3930 dma_addr_t buf_map;
3931 int n = (i % cp->l2_rx_ring_size) + 1;
3932
3933 buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
3934 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
3935 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
3936 }
3937 context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 0, &context_addr);
3938
3939 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
3940 rxbd->addr_hi = cpu_to_le32(val);
3941
3942 context->ustorm_st_context.common.bd_page_base_hi = val;
3943
3944 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
3945 rxbd->addr_lo = cpu_to_le32(val);
3946
3947 context->ustorm_st_context.common.bd_page_base_lo = val;
3948
3949 context->ustorm_st_context.common.sb_index_numbers =
3950 BNX2X_ISCSI_RX_SB_INDEX_NUM;
3951 context->ustorm_st_context.common.clientId = cli;
3952 context->ustorm_st_context.common.status_block_id = BNX2X_DEF_SB_ID;
3953 context->ustorm_st_context.common.flags =
3954 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
3955 context->ustorm_st_context.common.statistics_counter_id = cli;
3956 context->ustorm_st_context.common.mc_alignment_log_size = 0;
3957 context->ustorm_st_context.common.bd_buff_size =
3958 cp->l2_single_buf_size;
3959
3960 context->ustorm_ag_context.cdu_usage =
3961 CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
3962 CDU_REGION_NUMBER_UCM_AG,
3963 ETH_CONNECTION_TYPE);
3964
3965 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
3966 val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
3967 rxcqe->addr_hi = cpu_to_le32(val);
3968
3969 CNIC_WR(dev, BAR_USTRORM_INTMEM +
3970 USTORM_CQE_PAGE_BASE_OFFSET(port, cli) + 4, val);
3971
3972 CNIC_WR(dev, BAR_USTRORM_INTMEM +
3973 USTORM_CQE_PAGE_NEXT_OFFSET(port, cli) + 4, val);
3974
3975 val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
3976 rxcqe->addr_lo = cpu_to_le32(val);
3977
3978 CNIC_WR(dev, BAR_USTRORM_INTMEM +
3979 USTORM_CQE_PAGE_BASE_OFFSET(port, cli), val);
3980
3981 CNIC_WR(dev, BAR_USTRORM_INTMEM +
3982 USTORM_CQE_PAGE_NEXT_OFFSET(port, cli), val);
3983
3984 /* client tstorm info */
3985 tstorm_client.mtu = cp->l2_single_buf_size - 14;
3986 tstorm_client.config_flags =
3987 (TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE |
3988 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE);
3989 tstorm_client.statistics_counter_id = cli;
3990
3991 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
3992 TSTORM_CLIENT_CONFIG_OFFSET(port, cli),
3993 ((u32 *)&tstorm_client)[0]);
3994 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
3995 TSTORM_CLIENT_CONFIG_OFFSET(port, cli) + 4,
3996 ((u32 *)&tstorm_client)[1]);
3997
3998 /* reset tstorm per client statistics */
3999 val = BAR_TSTRORM_INTMEM +
4000 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4001 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
4002 CNIC_WR(dev, val + i * 4, 0);
4003
4004 /* reset ustorm per client statistics */
4005 val = BAR_USTRORM_INTMEM +
4006 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4007 for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
4008 CNIC_WR(dev, val + i * 4, 0);
4009
4010 cp->rx_cons_ptr =
4011 &cp->bnx2x_def_status_blk->u_def_status_block.index_values[
4012 HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS];
4013}
4014
4015static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4016{
4017 struct cnic_local *cp = dev->cnic_priv;
4018 u32 base, addr, val;
4019 int port = CNIC_PORT(cp);
4020
4021 dev->max_iscsi_conn = 0;
4022 base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
4023 if (base < 0xa0000 || base >= 0xc0000)
4024 return;
4025
dd2e4dbc 4026 addr = BNX2X_SHMEM_ADDR(base,
71034ba8
MC		 4027 dev_info.port_hw_config[port].iscsi_mac_upper);
4028
dd2e4dbc
MC		 4029 val = CNIC_RD(dev, addr);
4030
71034ba8
MC		 4031 dev->mac_addr[0] = (u8) (val >> 8);
4032 dev->mac_addr[1] = (u8) val;
4033
dd2e4dbc 4034 addr = BNX2X_SHMEM_ADDR(base,
71034ba8
MC		 4035 dev_info.port_hw_config[port].iscsi_mac_lower);
4036
dd2e4dbc
MC		 4037 val = CNIC_RD(dev, addr);
4038
71034ba8
MC		 4039 dev->mac_addr[2] = (u8) (val >> 24);
4040 dev->mac_addr[3] = (u8) (val >> 16);
4041 dev->mac_addr[4] = (u8) (val >> 8);
4042 dev->mac_addr[5] = (u8) val;
4043
4044 addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
4045 val = CNIC_RD(dev, addr);
4046
4047 if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
4048 u16 val16;
4049
4050 addr = BNX2X_SHMEM_ADDR(base,
4051 drv_lic_key[port].max_iscsi_init_conn);
4052 val16 = CNIC_RD16(dev, addr);
4053
4054 if (val16)
4055 val16 ^= 0x1e1e;
4056 dev->max_iscsi_conn = val16;
4057 }
4058 if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
4059 int func = CNIC_FUNC(cp);
4060
4061 addr = BNX2X_SHMEM_ADDR(base,
4062 mf_cfg.func_mf_config[func].e1hov_tag);
4063 val = CNIC_RD(dev, addr);
4064 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
4065 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
4066 addr = BNX2X_SHMEM_ADDR(base,
4067 mf_cfg.func_mf_config[func].config);
4068 val = CNIC_RD(dev, addr);
4069 val &= FUNC_MF_CFG_PROTOCOL_MASK;
4070 if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
4071 dev->max_iscsi_conn = 0;
4072 }
4073 }
4074}
4075
4076static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4077{
4078 struct cnic_local *cp = dev->cnic_priv;
4079 int func = CNIC_FUNC(cp), ret, i;
4080 int port = CNIC_PORT(cp);
4081 u16 eq_idx;
4082 u8 sb_id = cp->status_blk_num;
4083
4084 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4085 BNX2X_ISCSI_START_CID);
4086
4087 if (ret)
4088 return -ENOMEM;
4089
4090 cp->kcq_io_addr = BAR_CSTRORM_INTMEM +
4091 CSTORM_ISCSI_EQ_PROD_OFFSET(func, 0);
4092 cp->kcq_prod_idx = 0;
4093
4094 cnic_get_bnx2x_iscsi_info(dev);
4095
4096 /* Only 1 EQ */
4097 CNIC_WR16(dev, cp->kcq_io_addr, MAX_KCQ_IDX);
4098 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4099 CSTORM_ISCSI_EQ_CONS_OFFSET(func, 0), 0);
4100 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4101 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0),
4102 cp->kcq_info.pg_map_arr[1] & 0xffffffff);
4103 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4104 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0) + 4,
4105 (u64) cp->kcq_info.pg_map_arr[1] >> 32);
4106 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4107 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0),
4108 cp->kcq_info.pg_map_arr[0] & 0xffffffff);
4109 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4110 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0) + 4,
4111 (u64) cp->kcq_info.pg_map_arr[0] >> 32);
4112 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4113 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(func, 0), 1);
4114 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4115 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(func, 0), cp->status_blk_num);
4116 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4117 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(func, 0),
4118 HC_INDEX_C_ISCSI_EQ_CONS);
4119
4120 for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
4121 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4122 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i),
4123 cp->conn_buf_info.pgtbl[2 * i]);
4124 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4125 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i) + 4,
4126 cp->conn_buf_info.pgtbl[(2 * i) + 1]);
4127 }
4128
4129 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4130 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func),
4131 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4132 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4133 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func) + 4,
4134 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4135
4136 cnic_setup_bnx2x_context(dev);
4137
4138 eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM +
4139 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
4140 offsetof(struct cstorm_status_block_c,
4141 index_values[HC_INDEX_C_ISCSI_EQ_CONS]));
4142 if (eq_idx != 0) {
ddf79b20 4143 netdev_err(dev->netdev, "EQ cons index %x != 0\n", eq_idx);
71034ba8
MC		 4144 return -EBUSY;
4145 }
4146 ret = cnic_init_bnx2x_irq(dev);
4147 if (ret)
4148 return ret;
4149
4150 cnic_init_bnx2x_tx_ring(dev);
4151 cnic_init_bnx2x_rx_ring(dev);
4152
4153 return 0;
4154}
4155
86b53606
MC		 4156static void cnic_init_rings(struct cnic_dev *dev)
4157{
4158 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4159 cnic_init_bnx2_tx_ring(dev);
4160 cnic_init_bnx2_rx_ring(dev);
71034ba8
MC		 4161 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4162 struct cnic_local *cp = dev->cnic_priv;
71034ba8
MC		 4163 u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
4164 union l5cm_specific_data l5_data;
4165 struct ustorm_eth_rx_producers rx_prods = {0};
c7596b79 4166 u32 off, i;
71034ba8
MC		 4167
4168 rx_prods.bd_prod = 0;
4169 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4170 barrier();
4171
c7596b79 4172 off = BAR_USTRORM_INTMEM +
71034ba8
MC		 4173 USTORM_RX_PRODS_OFFSET(CNIC_PORT(cp), cli);
4174
4175 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
c7596b79 4176 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
71034ba8
MC		 4177
4178 cnic_init_bnx2x_tx_ring(dev);
4179 cnic_init_bnx2x_rx_ring(dev);
4180
4181 l5_data.phy_address.lo = cli;
4182 l5_data.phy_address.hi = 0;
4183 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4184 BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
4185 cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
86b53606
MC		 4186 }
4187}
4188
4189static void cnic_shutdown_rings(struct cnic_dev *dev)
4190{
4191 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4192 cnic_shutdown_bnx2_rx_ring(dev);
71034ba8
MC		 4193 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4194 struct cnic_local *cp = dev->cnic_priv;
4195 u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
8b065b67 4196 union l5cm_specific_data l5_data;
71034ba8
MC		 4197
4198 cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
8b065b67
MC		 4199
4200 l5_data.phy_address.lo = cli;
4201 l5_data.phy_address.hi = 0;
4202 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
4203 BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
4204 msleep(10);
1bcdc32c
MC		 4205
4206 memset(&l5_data, 0, sizeof(l5_data));
4207 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
4208 BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE |
4209 (1 << SPE_HDR_COMMON_RAMROD_SHIFT), &l5_data);
4210 msleep(10);
86b53606
MC		 4211 }
4212}
4213
a3059b12 4214static int cnic_register_netdev(struct cnic_dev *dev)
a4636960
MC		 4215{
4216 struct cnic_local *cp = dev->cnic_priv;
4217 struct cnic_eth_dev *ethdev = cp->ethdev;
4218 int err;
4219
a3059b12
MC		 4220 if (!ethdev)
4221 return -ENODEV;
4222
4223 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
4224 return 0;
a4636960
MC		 4225
4226 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
a3059b12 4227 if (err)
ddf79b20 4228 netdev_err(dev->netdev, "register_cnic failed\n");
a3059b12
MC		 4229
4230 return err;
4231}
4232
4233static void cnic_unregister_netdev(struct cnic_dev *dev)
4234{
4235 struct cnic_local *cp = dev->cnic_priv;
4236 struct cnic_eth_dev *ethdev = cp->ethdev;
4237
4238 if (!ethdev)
4239 return;
4240
4241 ethdev->drv_unregister_cnic(dev->netdev);
4242}
4243
4244static int cnic_start_hw(struct cnic_dev *dev)
4245{
4246 struct cnic_local *cp = dev->cnic_priv;
4247 struct cnic_eth_dev *ethdev = cp->ethdev;
4248 int err;
4249
4250 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
4251 return -EALREADY;
a4636960
MC		 4252
4253 dev->regview = ethdev->io_base;
4254 cp->chip_id = ethdev->chip_id;
4255 pci_dev_get(dev->pcidev);
4256 cp->func = PCI_FUNC(dev->pcidev->devfn);
4257 cp->status_blk = ethdev->irq_arr[0].status_blk;
4258 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
4259
4260 err = cp->alloc_resc(dev);
4261 if (err) {
ddf79b20 4262 netdev_err(dev->netdev, "allocate resource failure\n");
a4636960
MC		 4263 goto err1;
4264 }
4265
4266 err = cp->start_hw(dev);
4267 if (err)
4268 goto err1;
4269
4270 err = cnic_cm_open(dev);
4271 if (err)
4272 goto err1;
4273
4274 set_bit(CNIC_F_CNIC_UP, &dev->flags);
4275
4276 cp->enable_int(dev);
4277
4278 return 0;
4279
4280err1:
a4636960
MC		 4281 cp->free_resc(dev);
4282 pci_dev_put(dev->pcidev);
a4636960
MC		 4283 return err;
4284}
4285
4286static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
4287{
a4636960
MC		 4288 cnic_disable_bnx2_int_sync(dev);
4289
4290 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4291 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4292
4293 cnic_init_context(dev, KWQ_CID);
4294 cnic_init_context(dev, KCQ_CID);
4295
4296 cnic_setup_5709_context(dev, 0);
4297 cnic_free_irq(dev);
4298
a4636960
MC		 4299 cnic_free_resc(dev);
4300}
4301
71034ba8
MC		 4302
4303static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
4304{
4305 struct cnic_local *cp = dev->cnic_priv;
4306 u8 sb_id = cp->status_blk_num;
4307 int port = CNIC_PORT(cp);
4308
4309 cnic_free_irq(dev);
4310 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4311 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
4312 offsetof(struct cstorm_status_block_c,
4313 index_values[HC_INDEX_C_ISCSI_EQ_CONS]),
4314 0);
4e9c4fd3
MC		 4315 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4316 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->func, 0), 0);
4317 CNIC_WR16(dev, cp->kcq_io_addr, 0);
71034ba8
MC		 4318 cnic_free_resc(dev);
4319}
4320
a4636960
MC		 4321static void cnic_stop_hw(struct cnic_dev *dev)
4322{
4323 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4324 struct cnic_local *cp = dev->cnic_priv;
4325
4326 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
4327 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
4328 synchronize_rcu();
4329 cnic_cm_shutdown(dev);
4330 cp->stop_hw(dev);
4331 pci_dev_put(dev->pcidev);
4332 }
4333}
4334
4335static void cnic_free_dev(struct cnic_dev *dev)
4336{
4337 int i = 0;
4338
4339 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
4340 msleep(100);
4341 i++;
4342 }
4343 if (atomic_read(&dev->ref_count) != 0)
ddf79b20 4344 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
a4636960 4345
ddf79b20 4346 netdev_info(dev->netdev, "Removed CNIC device\n");
a4636960
MC		 4347 dev_put(dev->netdev);
4348 kfree(dev);
4349}
4350
4351static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
4352 struct pci_dev *pdev)
4353{
4354 struct cnic_dev *cdev;
4355 struct cnic_local *cp;
4356 int alloc_size;
4357
4358 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
4359
4360 cdev = kzalloc(alloc_size , GFP_KERNEL);
4361 if (cdev == NULL) {
ddf79b20 4362 netdev_err(dev, "allocate dev struct failure\n");
a4636960
MC		 4363 return NULL;
4364 }
4365
4366 cdev->netdev = dev;
4367 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
4368 cdev->register_device = cnic_register_device;
4369 cdev->unregister_device = cnic_unregister_device;
4370 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
4371
4372 cp = cdev->cnic_priv;
4373 cp->dev = cdev;
4374 cp->uio_dev = -1;
4375 cp->l2_single_buf_size = 0x400;
4376 cp->l2_rx_ring_size = 3;
4377
4378 spin_lock_init(&cp->cnic_ulp_lock);
4379
ddf79b20 4380 netdev_info(dev, "Added CNIC device\n");
a4636960
MC		 4381
4382 return cdev;
4383}
4384
4385static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
4386{
4387 struct pci_dev *pdev;
4388 struct cnic_dev *cdev;
4389 struct cnic_local *cp;
4390 struct cnic_eth_dev *ethdev = NULL;
e2ee3616 4391 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
a4636960 4392
e2ee3616 4393 probe = symbol_get(bnx2_cnic_probe);
a4636960
MC		 4394 if (probe) {
4395 ethdev = (*probe)(dev);
64c64608 4396 symbol_put(bnx2_cnic_probe);
a4636960
MC		 4397 }
4398 if (!ethdev)
4399 return NULL;
4400
4401 pdev = ethdev->pdev;
4402 if (!pdev)
4403 return NULL;
4404
4405 dev_hold(dev);
4406 pci_dev_get(pdev);
4407 if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
4408 pdev->device == PCI_DEVICE_ID_NX2_5709S) {
4409 u8 rev;
4410
4411 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
4412 if (rev < 0x10) {
4413 pci_dev_put(pdev);
4414 goto cnic_err;
4415 }
4416 }
4417 pci_dev_put(pdev);
4418
4419 cdev = cnic_alloc_dev(dev, pdev);
4420 if (cdev == NULL)
4421 goto cnic_err;
4422
4423 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
4424 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
4425
4426 cp = cdev->cnic_priv;
4427 cp->ethdev = ethdev;
4428 cdev->pcidev = pdev;
4429
4430 cp->cnic_ops = &cnic_bnx2_ops;
4431 cp->start_hw = cnic_start_bnx2_hw;
4432 cp->stop_hw = cnic_stop_bnx2_hw;
4433 cp->setup_pgtbl = cnic_setup_page_tbl;
4434 cp->alloc_resc = cnic_alloc_bnx2_resc;
4435 cp->free_resc = cnic_free_resc;
4436 cp->start_cm = cnic_cm_init_bnx2_hw;
4437 cp->stop_cm = cnic_cm_stop_bnx2_hw;
4438 cp->enable_int = cnic_enable_bnx2_int;
4439 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
4440 cp->close_conn = cnic_close_bnx2_conn;
4441 cp->next_idx = cnic_bnx2_next_idx;
4442 cp->hw_idx = cnic_bnx2_hw_idx;
4443 return cdev;
4444
4445cnic_err:
4446 dev_put(dev);
4447 return NULL;
4448}
4449
71034ba8
MC		 4450static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
4451{
4452 struct pci_dev *pdev;
4453 struct cnic_dev *cdev;
4454 struct cnic_local *cp;
4455 struct cnic_eth_dev *ethdev = NULL;
4456 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
4457
4458 probe = symbol_get(bnx2x_cnic_probe);
4459 if (probe) {
4460 ethdev = (*probe)(dev);
4461 symbol_put(bnx2x_cnic_probe);
4462 }
4463 if (!ethdev)
4464 return NULL;
4465
4466 pdev = ethdev->pdev;
4467 if (!pdev)
4468 return NULL;
4469
4470 dev_hold(dev);
4471 cdev = cnic_alloc_dev(dev, pdev);
4472 if (cdev == NULL) {
4473 dev_put(dev);
4474 return NULL;
4475 }
4476
4477 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
4478 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
4479
4480 cp = cdev->cnic_priv;
4481 cp->ethdev = ethdev;
4482 cdev->pcidev = pdev;
4483
4484 cp->cnic_ops = &cnic_bnx2x_ops;
4485 cp->start_hw = cnic_start_bnx2x_hw;
4486 cp->stop_hw = cnic_stop_bnx2x_hw;
4487 cp->setup_pgtbl = cnic_setup_page_tbl_le;
4488 cp->alloc_resc = cnic_alloc_bnx2x_resc;
4489 cp->free_resc = cnic_free_resc;
4490 cp->start_cm = cnic_cm_init_bnx2x_hw;
4491 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
4492 cp->enable_int = cnic_enable_bnx2x_int;
4493 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
4494 cp->ack_int = cnic_ack_bnx2x_msix;
4495 cp->close_conn = cnic_close_bnx2x_conn;
4496 cp->next_idx = cnic_bnx2x_next_idx;
4497 cp->hw_idx = cnic_bnx2x_hw_idx;
4498 return cdev;
4499}
4500
a4636960
MC		 4501static struct cnic_dev *is_cnic_dev(struct net_device *dev)
4502{
4503 struct ethtool_drvinfo drvinfo;
4504 struct cnic_dev *cdev = NULL;
4505
4506 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
4507 memset(&drvinfo, 0, sizeof(drvinfo));
4508 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
4509
4510 if (!strcmp(drvinfo.driver, "bnx2"))
4511 cdev = init_bnx2_cnic(dev);
71034ba8
MC		 4512 if (!strcmp(drvinfo.driver, "bnx2x"))
4513 cdev = init_bnx2x_cnic(dev);
a4636960
MC		 4514 if (cdev) {
4515 write_lock(&cnic_dev_lock);
4516 list_add(&cdev->list, &cnic_dev_list);
4517 write_unlock(&cnic_dev_lock);
4518 }
4519 }
4520 return cdev;
4521}
4522
4523/**
4524 * netdev event handler
4525 */
4526static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
4527 void *ptr)
4528{
4529 struct net_device *netdev = ptr;
4530 struct cnic_dev *dev;
4531 int if_type;
4532 int new_dev = 0;
4533
4534 dev = cnic_from_netdev(netdev);
4535
4536 if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
4537 /* Check for the hot-plug device */
4538 dev = is_cnic_dev(netdev);
4539 if (dev) {
4540 new_dev = 1;
4541 cnic_hold(dev);
4542 }
4543 }
4544 if (dev) {
4545 struct cnic_local *cp = dev->cnic_priv;
4546
4547 if (new_dev)
4548 cnic_ulp_init(dev);
4549 else if (event == NETDEV_UNREGISTER)
4550 cnic_ulp_exit(dev);
6053bbf7
MC		 4551
4552 if (event == NETDEV_UP) {
a3059b12
MC		 4553 if (cnic_register_netdev(dev) != 0) {
4554 cnic_put(dev);
4555 goto done;
4556 }
a4636960
MC		 4557 if (!cnic_start_hw(dev))
4558 cnic_ulp_start(dev);
a4636960
MC		 4559 }
4560
4561 rcu_read_lock();
4562 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
4563 struct cnic_ulp_ops *ulp_ops;
4564 void *ctx;
4565
4566 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
4567 if (!ulp_ops || !ulp_ops->indicate_netevent)
4568 continue;
4569
4570 ctx = cp->ulp_handle[if_type];
4571
4572 ulp_ops->indicate_netevent(ctx, event);
4573 }
4574 rcu_read_unlock();
4575
4576 if (event == NETDEV_GOING_DOWN) {
a4636960
MC		 4577 cnic_ulp_stop(dev);
4578 cnic_stop_hw(dev);
a3059b12 4579 cnic_unregister_netdev(dev);
a4636960
MC		 4580 } else if (event == NETDEV_UNREGISTER) {
4581 write_lock(&cnic_dev_lock);
4582 list_del_init(&dev->list);
4583 write_unlock(&cnic_dev_lock);
4584
4585 cnic_put(dev);
4586 cnic_free_dev(dev);
4587 goto done;
4588 }
4589 cnic_put(dev);
4590 }
4591done:
4592 return NOTIFY_DONE;
4593}
4594
4595static struct notifier_block cnic_netdev_notifier = {
4596 .notifier_call = cnic_netdev_event
4597};
4598
4599static void cnic_release(void)
4600{
4601 struct cnic_dev *dev;
4602
4603 while (!list_empty(&cnic_dev_list)) {
4604 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
4605 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4606 cnic_ulp_stop(dev);
4607 cnic_stop_hw(dev);
4608 }
4609
4610 cnic_ulp_exit(dev);
a3059b12 4611 cnic_unregister_netdev(dev);
a4636960
MC		 4612 list_del_init(&dev->list);
4613 cnic_free_dev(dev);
4614 }
4615}
4616
4617static int __init cnic_init(void)
4618{
4619 int rc = 0;
4620
ddf79b20 4621 pr_info("%s", version);
a4636960
MC		 4622
4623 rc = register_netdevice_notifier(&cnic_netdev_notifier);
4624 if (rc) {
4625 cnic_release();
4626 return rc;
4627 }
4628
4629 return 0;
4630}
4631
4632static void __exit cnic_exit(void)
4633{
4634 unregister_netdevice_notifier(&cnic_netdev_notifier);
4635 cnic_release();
4636 return;
4637}
4638
4639module_init(cnic_init);
4640module_exit(cnic_exit);
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