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[net-next-2.6.git] / drivers / net / chelsio / subr.c
CommitLineData
8199d3a7
CL		 1/*****************************************************************************
2 * *
3 * File: subr.c *
559fb51b
SB		 4 * $Revision: 1.27 $ *
5 * $Date: 2005/06/22 01:08:36 $ *
8199d3a7
CL		 6 * Description: *
7 * Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40#include "common.h"
41#include "elmer0.h"
42#include "regs.h"
8199d3a7
CL		 43#include "gmac.h"
44#include "cphy.h"
45#include "sge.h"
f1d3d38a 46#include "tp.h"
8199d3a7
CL		 47#include "espi.h"
48
49/**
50 * t1_wait_op_done - wait until an operation is completed
51 * @adapter: the adapter performing the operation
52 * @reg: the register to check for completion
53 * @mask: a single-bit field within @reg that indicates completion
54 * @polarity: the value of the field when the operation is completed
55 * @attempts: number of check iterations
56 * @delay: delay in usecs between iterations
57 *
58 * Wait until an operation is completed by checking a bit in a register
59 * up to @attempts times. Returns %0 if the operation completes and %1
60 * otherwise.
61 */
62static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
f1d3d38a 63 int attempts, int delay)
8199d3a7
CL		 64{
65 while (1) {
559fb51b 66 u32 val = readl(adapter->regs + reg) & mask;
8199d3a7
CL		 67
68 if (!!val == polarity)
69 return 0;
70 if (--attempts == 0)
71 return 1;
72 if (delay)
73 udelay(delay);
74 }
75}
76
77#define TPI_ATTEMPTS 50
78
79/*
80 * Write a register over the TPI interface (unlocked and locked versions).
81 */
f1d3d38a 82int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
8199d3a7
CL		 83{
84 int tpi_busy;
85
559fb51b
SB		 86 writel(addr, adapter->regs + A_TPI_ADDR);
87 writel(value, adapter->regs + A_TPI_WR_DATA);
88 writel(F_TPIWR, adapter->regs + A_TPI_CSR);
8199d3a7
CL		 89
90 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
91 TPI_ATTEMPTS, 3);
92 if (tpi_busy)
93 CH_ALERT("%s: TPI write to 0x%x failed\n",
94 adapter->name, addr);
95 return tpi_busy;
96}
97
98int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
99{
100 int ret;
101
f1d3d38a 102 spin_lock(&adapter->tpi_lock);
8199d3a7 103 ret = __t1_tpi_write(adapter, addr, value);
f1d3d38a 104 spin_unlock(&adapter->tpi_lock);
8199d3a7
CL		 105 return ret;
106}
107
108/*
109 * Read a register over the TPI interface (unlocked and locked versions).
110 */
f1d3d38a 111int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
8199d3a7
CL		 112{
113 int tpi_busy;
114
559fb51b
SB		 115 writel(addr, adapter->regs + A_TPI_ADDR);
116 writel(0, adapter->regs + A_TPI_CSR);
8199d3a7
CL		 117
118 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
119 TPI_ATTEMPTS, 3);
120 if (tpi_busy)
121 CH_ALERT("%s: TPI read from 0x%x failed\n",
122 adapter->name, addr);
123 else
559fb51b 124 *valp = readl(adapter->regs + A_TPI_RD_DATA);
8199d3a7
CL		 125 return tpi_busy;
126}
127
128int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
129{
130 int ret;
131
f1d3d38a 132 spin_lock(&adapter->tpi_lock);
8199d3a7 133 ret = __t1_tpi_read(adapter, addr, valp);
f1d3d38a 134 spin_unlock(&adapter->tpi_lock);
8199d3a7
CL		 135 return ret;
136}
137
f1d3d38a
SH		 138/*
139 * Set a TPI parameter.
140 */
141static void t1_tpi_par(adapter_t *adapter, u32 value)
142{
143 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
144}
145
8199d3a7
CL		 146/*
147 * Called when a port's link settings change to propagate the new values to the
148 * associated PHY and MAC. After performing the common tasks it invokes an
149 * OS-specific handler.
150 */
f1d3d38a 151void t1_link_changed(adapter_t *adapter, int port_id)
8199d3a7
CL		 152{
153 int link_ok, speed, duplex, fc;
154 struct cphy *phy = adapter->port[port_id].phy;
155 struct link_config *lc = &adapter->port[port_id].link_config;
156
157 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
158
159 lc->speed = speed < 0 ? SPEED_INVALID : speed;
160 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
161 if (!(lc->requested_fc & PAUSE_AUTONEG))
162 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
163
164 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
165 /* Set MAC speed, duplex, and flow control to match PHY. */
166 struct cmac *mac = adapter->port[port_id].mac;
167
168 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
169 lc->fc = (unsigned char)fc;
170 }
f1d3d38a 171 t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
8199d3a7
CL		 172}
173
174static int t1_pci_intr_handler(adapter_t *adapter)
175{
176 u32 pcix_cause;
177
11e5a202 178 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
8199d3a7
CL		 179
180 if (pcix_cause) {
181 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
11e5a202 182 pcix_cause);
8199d3a7
CL		 183 t1_fatal_err(adapter); /* PCI errors are fatal */
184 }
185 return 0;
186}
187
352c417d
SH		 188#ifdef CONFIG_CHELSIO_T1_COUGAR
189#include "cspi.h"
190#endif
191#ifdef CONFIG_CHELSIO_T1_1G
192#include "fpga_defs.h"
193
194/*
195 * PHY interrupt handler for FPGA boards.
196 */
197static int fpga_phy_intr_handler(adapter_t *adapter)
198{
199 int p;
200 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
201
202 for_each_port(adapter, p)
203 if (cause & (1 << p)) {
204 struct cphy *phy = adapter->port[p].phy;
205 int phy_cause = phy->ops->interrupt_handler(phy);
206
207 if (phy_cause & cphy_cause_link_change)
208 t1_link_changed(adapter, p);
209 }
210 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
211 return 0;
212}
213
214/*
215 * Slow path interrupt handler for FPGAs.
216 */
217static int fpga_slow_intr(adapter_t *adapter)
218{
219 u32 cause = readl(adapter->regs + A_PL_CAUSE);
220
221 cause &= ~F_PL_INTR_SGE_DATA;
222 if (cause & F_PL_INTR_SGE_ERR)
223 t1_sge_intr_error_handler(adapter->sge);
224
225 if (cause & FPGA_PCIX_INTERRUPT_GMAC)
356bd146 226 fpga_phy_intr_handler(adapter);
352c417d
SH		 227
228 if (cause & FPGA_PCIX_INTERRUPT_TP) {
356bd146 229 /*
352c417d
SH		 230 * FPGA doesn't support MC4 interrupts and it requires
231 * this odd layer of indirection for MC5.
356bd146 232 */
352c417d
SH		 233 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
234
235 /* Clear TP interrupt */
236 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
237 }
238 if (cause & FPGA_PCIX_INTERRUPT_PCIX)
239 t1_pci_intr_handler(adapter);
240
241 /* Clear the interrupts just processed. */
242 if (cause)
243 writel(cause, adapter->regs + A_PL_CAUSE);
244
245 return cause != 0;
246}
247#endif
8199d3a7
CL		 248
249/*
250 * Wait until Elmer's MI1 interface is ready for new operations.
251 */
252static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
253{
254 int attempts = 100, busy;
255
256 do {
257 u32 val;
258
259 __t1_tpi_read(adapter, mi1_reg, &val);
260 busy = val & F_MI1_OP_BUSY;
261 if (busy)
262 udelay(10);
263 } while (busy && --attempts);
264 if (busy)
356bd146 265 CH_ALERT("%s: MDIO operation timed out\n", adapter->name);
8199d3a7
CL		 266 return busy;
267}
268
269/*
270 * MI1 MDIO initialization.
271 */
272static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
273{
274 u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
275 u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
276 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
277
278 if (!(bi->caps & SUPPORTED_10000baseT_Full))
279 val |= V_MI1_SOF(1);
280 t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
281}
282
352c417d
SH		 283#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
284/*
285 * Elmer MI1 MDIO read/write operations.
286 */
287static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
288 int reg_addr, unsigned int *valp)
289{
290 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
291
292 if (mmd_addr)
293 return -EINVAL;
294
295 spin_lock(&adapter->tpi_lock);
296 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
297 __t1_tpi_write(adapter,
298 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
299 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
300 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
301 spin_unlock(&adapter->tpi_lock);
302 return 0;
303}
304
305static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
306 int reg_addr, unsigned int val)
307{
308 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
309
310 if (mmd_addr)
311 return -EINVAL;
312
313 spin_lock(&adapter->tpi_lock);
314 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
315 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
316 __t1_tpi_write(adapter,
317 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
318 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
319 spin_unlock(&adapter->tpi_lock);
320 return 0;
321}
322
323#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
459e536b 324static const struct mdio_ops mi1_mdio_ops = {
4c247db1
SH		 325 .init = mi1_mdio_init,
326 .read = mi1_mdio_read,
327 .write = mi1_mdio_write
352c417d
SH		 328};
329#endif
330
331#endif
332
8199d3a7
CL		 333static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
334 int reg_addr, unsigned int *valp)
335{
336 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
337
f1d3d38a 338 spin_lock(&adapter->tpi_lock);
8199d3a7
CL		 339
340 /* Write the address we want. */
341 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
342 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
343 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
344 MI1_OP_INDIRECT_ADDRESS);
345 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
346
347 /* Write the operation we want. */
f1d3d38a
SH		 348 __t1_tpi_write(adapter,
349 A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
8199d3a7
CL		 350 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
351
352 /* Read the data. */
353 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
f1d3d38a 354 spin_unlock(&adapter->tpi_lock);
8199d3a7
CL		 355 return 0;
356}
357
358static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
359 int reg_addr, unsigned int val)
360{
361 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
362
f1d3d38a 363 spin_lock(&adapter->tpi_lock);
8199d3a7
CL		 364
365 /* Write the address we want. */
366 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
367 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
368 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
369 MI1_OP_INDIRECT_ADDRESS);
370 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
371
372 /* Write the data. */
373 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
374 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
375 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
f1d3d38a 376 spin_unlock(&adapter->tpi_lock);
8199d3a7
CL		 377 return 0;
378}
379
459e536b 380static const struct mdio_ops mi1_mdio_ext_ops = {
4c247db1
SH		 381 .init = mi1_mdio_init,
382 .read = mi1_mdio_ext_read,
383 .write = mi1_mdio_ext_write
8199d3a7
CL		 384};
385
386enum {
f1d3d38a 387 CH_BRD_T110_1CU,
8199d3a7
CL		 388 CH_BRD_N110_1F,
389 CH_BRD_N210_1F,
f1d3d38a
SH		 390 CH_BRD_T210_1F,
391 CH_BRD_T210_1CU,
392 CH_BRD_N204_4CU,
8199d3a7
CL		 393};
394
4c247db1
SH		 395static const struct board_info t1_board[] = {
396 {
397 .board = CHBT_BOARD_CHT110,
398 .port_number = 1,
399 .caps = SUPPORTED_10000baseT_Full,
400 .chip_term = CHBT_TERM_T1,
401 .chip_mac = CHBT_MAC_PM3393,
402 .chip_phy = CHBT_PHY_MY3126,
403 .clock_core = 125000000,
404 .clock_mc3 = 150000000,
405 .clock_mc4 = 125000000,
406 .espi_nports = 1,
407 .clock_elmer0 = 44,
408 .mdio_mdien = 1,
409 .mdio_mdiinv = 1,
410 .mdio_mdc = 1,
411 .mdio_phybaseaddr = 1,
412 .gmac = &t1_pm3393_ops,
413 .gphy = &t1_my3126_ops,
414 .mdio_ops = &mi1_mdio_ext_ops,
415 .desc = "Chelsio T110 1x10GBase-CX4 TOE",
416 },
417
418 {
419 .board = CHBT_BOARD_N110,
420 .port_number = 1,
421 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
422 .chip_term = CHBT_TERM_T1,
423 .chip_mac = CHBT_MAC_PM3393,
424 .chip_phy = CHBT_PHY_88X2010,
425 .clock_core = 125000000,
426 .espi_nports = 1,
427 .clock_elmer0 = 44,
428 .mdio_mdien = 0,
429 .mdio_mdiinv = 0,
430 .mdio_mdc = 1,
431 .mdio_phybaseaddr = 0,
432 .gmac = &t1_pm3393_ops,
433 .gphy = &t1_mv88x201x_ops,
434 .mdio_ops = &mi1_mdio_ext_ops,
435 .desc = "Chelsio N110 1x10GBaseX NIC",
436 },
437
438 {
439 .board = CHBT_BOARD_N210,
440 .port_number = 1,
441 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
442 .chip_term = CHBT_TERM_T2,
443 .chip_mac = CHBT_MAC_PM3393,
444 .chip_phy = CHBT_PHY_88X2010,
445 .clock_core = 125000000,
446 .espi_nports = 1,
447 .clock_elmer0 = 44,
448 .mdio_mdien = 0,
449 .mdio_mdiinv = 0,
450 .mdio_mdc = 1,
451 .mdio_phybaseaddr = 0,
452 .gmac = &t1_pm3393_ops,
453 .gphy = &t1_mv88x201x_ops,
454 .mdio_ops = &mi1_mdio_ext_ops,
455 .desc = "Chelsio N210 1x10GBaseX NIC",
456 },
457
458 {
459 .board = CHBT_BOARD_CHT210,
460 .port_number = 1,
461 .caps = SUPPORTED_10000baseT_Full,
462 .chip_term = CHBT_TERM_T2,
463 .chip_mac = CHBT_MAC_PM3393,
464 .chip_phy = CHBT_PHY_88X2010,
465 .clock_core = 125000000,
466 .clock_mc3 = 133000000,
467 .clock_mc4 = 125000000,
468 .espi_nports = 1,
469 .clock_elmer0 = 44,
470 .mdio_mdien = 0,
471 .mdio_mdiinv = 0,
472 .mdio_mdc = 1,
473 .mdio_phybaseaddr = 0,
474 .gmac = &t1_pm3393_ops,
475 .gphy = &t1_mv88x201x_ops,
476 .mdio_ops = &mi1_mdio_ext_ops,
477 .desc = "Chelsio T210 1x10GBaseX TOE",
478 },
479
480 {
481 .board = CHBT_BOARD_CHT210,
482 .port_number = 1,
483 .caps = SUPPORTED_10000baseT_Full,
484 .chip_term = CHBT_TERM_T2,
485 .chip_mac = CHBT_MAC_PM3393,
486 .chip_phy = CHBT_PHY_MY3126,
487 .clock_core = 125000000,
488 .clock_mc3 = 133000000,
489 .clock_mc4 = 125000000,
490 .espi_nports = 1,
491 .clock_elmer0 = 44,
492 .mdio_mdien = 1,
493 .mdio_mdiinv = 1,
494 .mdio_mdc = 1,
495 .mdio_phybaseaddr = 1,
496 .gmac = &t1_pm3393_ops,
497 .gphy = &t1_my3126_ops,
498 .mdio_ops = &mi1_mdio_ext_ops,
499 .desc = "Chelsio T210 1x10GBase-CX4 TOE",
500 },
f1d3d38a 501
352c417d 502#ifdef CONFIG_CHELSIO_T1_1G
4c247db1
SH		 503 {
504 .board = CHBT_BOARD_CHN204,
505 .port_number = 4,
506 .caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
507 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
508 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
509 SUPPORTED_PAUSE | SUPPORTED_TP,
510 .chip_term = CHBT_TERM_T2,
511 .chip_mac = CHBT_MAC_VSC7321,
512 .chip_phy = CHBT_PHY_88E1111,
513 .clock_core = 100000000,
514 .espi_nports = 4,
515 .clock_elmer0 = 44,
516 .mdio_mdien = 0,
517 .mdio_mdiinv = 0,
518 .mdio_mdc = 0,
519 .mdio_phybaseaddr = 4,
520 .gmac = &t1_vsc7326_ops,
521 .gphy = &t1_mv88e1xxx_ops,
522 .mdio_ops = &mi1_mdio_ops,
523 .desc = "Chelsio N204 4x100/1000BaseT NIC",
524 },
352c417d 525#endif
f1d3d38a 526
8199d3a7
CL		 527};
528
529struct pci_device_id t1_pci_tbl[] = {
f1d3d38a
SH		 530 CH_DEVICE(8, 0, CH_BRD_T110_1CU),
531 CH_DEVICE(8, 1, CH_BRD_T110_1CU),
8199d3a7
CL		 532 CH_DEVICE(7, 0, CH_BRD_N110_1F),
533 CH_DEVICE(10, 1, CH_BRD_N210_1F),
f1d3d38a
SH		 534 CH_DEVICE(11, 1, CH_BRD_T210_1F),
535 CH_DEVICE(14, 1, CH_BRD_T210_1CU),
536 CH_DEVICE(16, 1, CH_BRD_N204_4CU),
537 { 0 }
8199d3a7
CL		 538};
539
559fb51b
SB		 540MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
541
8199d3a7
CL		 542/*
543 * Return the board_info structure with a given index. Out-of-range indices
544 * return NULL.
545 */
546const struct board_info *t1_get_board_info(unsigned int board_id)
547{
559fb51b 548 return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
8199d3a7
CL		 549}
550
551struct chelsio_vpd_t {
552 u32 format_version;
553 u8 serial_number[16];
554 u8 mac_base_address[6];
555 u8 pad[2]; /* make multiple-of-4 size requirement explicit */
556};
557
558#define EEPROMSIZE (8 * 1024)
559#define EEPROM_MAX_POLL 4
560
561/*
562 * Read SEEPROM. A zero is written to the flag register when the addres is
563 * written to the Control register. The hardware device will set the flag to a
564 * one when 4B have been transferred to the Data register.
565 */
566int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data)
567{
568 int i = EEPROM_MAX_POLL;
569 u16 val;
570
571 if (addr >= EEPROMSIZE || (addr & 3))
572 return -EINVAL;
573
574 pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
575 do {
576 udelay(50);
577 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
578 } while (!(val & F_VPD_OP_FLAG) && --i);
579
580 if (!(val & F_VPD_OP_FLAG)) {
581 CH_ERR("%s: reading EEPROM address 0x%x failed\n",
582 adapter->name, addr);
583 return -EIO;
584 }
585 pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, data);
586 *data = le32_to_cpu(*data);
587 return 0;
588}
589
590static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
591{
592 int addr, ret = 0;
593
594 for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
595 ret = t1_seeprom_read(adapter, addr,
596 (u32 *)((u8 *)vpd + addr));
597
598 return ret;
599}
600
601/*
602 * Read a port's MAC address from the VPD ROM.
603 */
604static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
605{
606 struct chelsio_vpd_t vpd;
607
608 if (t1_eeprom_vpd_get(adapter, &vpd))
609 return 1;
610 memcpy(mac_addr, vpd.mac_base_address, 5);
611 mac_addr[5] = vpd.mac_base_address[5] + index;
612 return 0;
613}
614
615/*
616 * Set up the MAC/PHY according to the requested link settings.
617 *
618 * If the PHY can auto-negotiate first decide what to advertise, then
619 * enable/disable auto-negotiation as desired and reset.
620 *
621 * If the PHY does not auto-negotiate we just reset it.
622 *
623 * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
624 * otherwise do it later based on the outcome of auto-negotiation.
625 */
626int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
627{
628 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
629
630 if (lc->supported & SUPPORTED_Autoneg) {
631 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
632 if (fc) {
f1d3d38a
SH		 633 if (fc == ((PAUSE_RX | PAUSE_TX) &
634 (mac->adapter->params.nports < 2)))
8199d3a7 635 lc->advertising |= ADVERTISED_PAUSE;
f1d3d38a
SH		 636 else {
637 lc->advertising |= ADVERTISED_ASYM_PAUSE;
638 if (fc == PAUSE_RX)
639 lc->advertising |= ADVERTISED_PAUSE;
640 }
8199d3a7
CL		 641 }
642 phy->ops->advertise(phy, lc->advertising);
643
644 if (lc->autoneg == AUTONEG_DISABLE) {
645 lc->speed = lc->requested_speed;
646 lc->duplex = lc->requested_duplex;
647 lc->fc = (unsigned char)fc;
648 mac->ops->set_speed_duplex_fc(mac, lc->speed,
649 lc->duplex, fc);
650 /* Also disables autoneg */
f1d3d38a 651 phy->state = PHY_AUTONEG_RDY;
8199d3a7
CL		 652 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
653 phy->ops->reset(phy, 0);
f1d3d38a
SH		 654 } else {
655 phy->state = PHY_AUTONEG_EN;
8199d3a7 656 phy->ops->autoneg_enable(phy); /* also resets PHY */
f1d3d38a 657 }
8199d3a7 658 } else {
f1d3d38a 659 phy->state = PHY_AUTONEG_RDY;
8199d3a7
CL		 660 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
661 lc->fc = (unsigned char)fc;
662 phy->ops->reset(phy, 0);
663 }
664 return 0;
665}
666
667/*
668 * External interrupt handler for boards using elmer0.
669 */
f1d3d38a 670int t1_elmer0_ext_intr_handler(adapter_t *adapter)
8199d3a7 671{
11e5a202 672 struct cphy *phy;
8199d3a7 673 int phy_cause;
11e5a202 674 u32 cause;
8199d3a7
CL		 675
676 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
677
678 switch (board_info(adapter)->board) {
352c417d 679#ifdef CONFIG_CHELSIO_T1_1G
356bd146
FR		 680 case CHBT_BOARD_CHT204:
681 case CHBT_BOARD_CHT204E:
682 case CHBT_BOARD_CHN204:
683 case CHBT_BOARD_CHT204V: {
684 int i, port_bit;
352c417d
SH		 685 for_each_port(adapter, i) {
686 port_bit = i + 1;
c697f83e
FR		 687 if (!(cause & (1 << port_bit)))
688 continue;
352c417d 689
356bd146 690 phy = adapter->port[i].phy;
352c417d
SH		 691 phy_cause = phy->ops->interrupt_handler(phy);
692 if (phy_cause & cphy_cause_link_change)
693 t1_link_changed(adapter, i);
694 }
356bd146
FR		 695 break;
696 }
352c417d
SH		 697 case CHBT_BOARD_CHT101:
698 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
699 phy = adapter->port[0].phy;
700 phy_cause = phy->ops->interrupt_handler(phy);
701 if (phy_cause & cphy_cause_link_change)
702 t1_link_changed(adapter, 0);
703 }
704 break;
705 case CHBT_BOARD_7500: {
706 int p;
356bd146 707 /*
352c417d
SH		 708 * Elmer0's interrupt cause isn't useful here because there is
709 * only one bit that can be set for all 4 ports. This means
710 * we are forced to check every PHY's interrupt status
711 * register to see who initiated the interrupt.
356bd146
FR		 712 */
713 for_each_port(adapter, p) {
352c417d
SH		 714 phy = adapter->port[p].phy;
715 phy_cause = phy->ops->interrupt_handler(phy);
716 if (phy_cause & cphy_cause_link_change)
717 t1_link_changed(adapter, p);
718 }
719 break;
720 }
721#endif
f1d3d38a 722 case CHBT_BOARD_CHT210:
8199d3a7
CL		 723 case CHBT_BOARD_N210:
724 case CHBT_BOARD_N110:
725 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
726 phy = adapter->port[0].phy;
727 phy_cause = phy->ops->interrupt_handler(phy);
728 if (phy_cause & cphy_cause_link_change)
f1d3d38a
SH		 729 t1_link_changed(adapter, 0);
730 }
731 break;
732 case CHBT_BOARD_8000:
733 case CHBT_BOARD_CHT110:
356bd146 734 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
f1d3d38a
SH		 735 cause);
736 if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
737 struct cmac *mac = adapter->port[0].mac;
738
739 mac->ops->interrupt_handler(mac);
8199d3a7 740 }
f1d3d38a
SH		 741 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
742 u32 mod_detect;
743
744 t1_tpi_read(adapter,
745 A_ELMER0_GPI_STAT, &mod_detect);
356bd146 746 CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
f1d3d38a 747 mod_detect ? "removed" : "inserted");
356bd146 748 }
8199d3a7 749 break;
352c417d
SH		 750#ifdef CONFIG_CHELSIO_T1_COUGAR
751 case CHBT_BOARD_COUGAR:
752 if (adapter->params.nports == 1) {
753 if (cause & ELMER0_GP_BIT1) { /* Vitesse MAC */
754 struct cmac *mac = adapter->port[0].mac;
755 mac->ops->interrupt_handler(mac);
756 }
757 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
758 }
759 } else {
760 int i, port_bit;
761
762 for_each_port(adapter, i) {
763 port_bit = i ? i + 1 : 0;
c697f83e
FR		 764 if (!(cause & (1 << port_bit)))
765 continue;
352c417d
SH		 766
767 phy = adapter->port[i].phy;
768 phy_cause = phy->ops->interrupt_handler(phy);
769 if (phy_cause & cphy_cause_link_change)
770 t1_link_changed(adapter, i);
771 }
772 }
773 break;
774#endif
8199d3a7
CL		 775 }
776 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
777 return 0;
778}
779
780/* Enables all interrupts. */
781void t1_interrupts_enable(adapter_t *adapter)
782{
783 unsigned int i;
784
f1d3d38a 785 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
8199d3a7
CL		 786
787 t1_sge_intr_enable(adapter->sge);
f1d3d38a 788 t1_tp_intr_enable(adapter->tp);
8199d3a7
CL		 789 if (adapter->espi) {
790 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
791 t1_espi_intr_enable(adapter->espi);
792 }
793
794 /* Enable MAC/PHY interrupts for each port. */
795 for_each_port(adapter, i) {
796 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
797 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
798 }
799
800 /* Enable PCIX & external chip interrupts on ASIC boards. */
f1d3d38a
SH		 801 if (t1_is_asic(adapter)) {
802 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
8199d3a7 803
f1d3d38a
SH		 804 /* PCI-X interrupts */
805 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
806 0xffffffff);
8199d3a7 807
f1d3d38a
SH		 808 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
809 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
810 writel(pl_intr, adapter->regs + A_PL_ENABLE);
811 }
8199d3a7
CL		 812}
813
814/* Disables all interrupts. */
815void t1_interrupts_disable(adapter_t* adapter)
816{
817 unsigned int i;
818
819 t1_sge_intr_disable(adapter->sge);
f1d3d38a 820 t1_tp_intr_disable(adapter->tp);
8199d3a7
CL		 821 if (adapter->espi)
822 t1_espi_intr_disable(adapter->espi);
823
824 /* Disable MAC/PHY interrupts for each port. */
825 for_each_port(adapter, i) {
826 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
827 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
828 }
829
830 /* Disable PCIX & external chip interrupts. */
f1d3d38a 831 if (t1_is_asic(adapter))
356bd146 832 writel(0, adapter->regs + A_PL_ENABLE);
8199d3a7
CL		 833
834 /* PCI-X interrupts */
835 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
836
837 adapter->slow_intr_mask = 0;
838}
839
840/* Clears all interrupts */
841void t1_interrupts_clear(adapter_t* adapter)
842{
843 unsigned int i;
844
845 t1_sge_intr_clear(adapter->sge);
f1d3d38a 846 t1_tp_intr_clear(adapter->tp);
8199d3a7
CL		 847 if (adapter->espi)
848 t1_espi_intr_clear(adapter->espi);
849
850 /* Clear MAC/PHY interrupts for each port. */
851 for_each_port(adapter, i) {
852 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
853 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
854 }
855
856 /* Enable interrupts for external devices. */
f1d3d38a
SH		 857 if (t1_is_asic(adapter)) {
858 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
8199d3a7 859
f1d3d38a
SH		 860 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
861 adapter->regs + A_PL_CAUSE);
862 }
8199d3a7
CL		 863
864 /* PCI-X interrupts */
865 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
866}
867
868/*
869 * Slow path interrupt handler for ASICs.
870 */
f1d3d38a 871static int asic_slow_intr(adapter_t *adapter)
8199d3a7 872{
559fb51b 873 u32 cause = readl(adapter->regs + A_PL_CAUSE);
8199d3a7
CL		 874
875 cause &= adapter->slow_intr_mask;
876 if (!cause)
877 return 0;
878 if (cause & F_PL_INTR_SGE_ERR)
879 t1_sge_intr_error_handler(adapter->sge);
f1d3d38a
SH		 880 if (cause & F_PL_INTR_TP)
881 t1_tp_intr_handler(adapter->tp);
8199d3a7
CL		 882 if (cause & F_PL_INTR_ESPI)
883 t1_espi_intr_handler(adapter->espi);
884 if (cause & F_PL_INTR_PCIX)
885 t1_pci_intr_handler(adapter);
886 if (cause & F_PL_INTR_EXT)
33a85aa1 887 t1_elmer0_ext_intr(adapter);
8199d3a7
CL		 888
889 /* Clear the interrupts just processed. */
559fb51b 890 writel(cause, adapter->regs + A_PL_CAUSE);
f1d3d38a 891 readl(adapter->regs + A_PL_CAUSE); /* flush writes */
8199d3a7
CL		 892 return 1;
893}
894
f1d3d38a 895int t1_slow_intr_handler(adapter_t *adapter)
8199d3a7 896{
352c417d
SH		 897#ifdef CONFIG_CHELSIO_T1_1G
898 if (!t1_is_asic(adapter))
899 return fpga_slow_intr(adapter);
900#endif
f1d3d38a 901 return asic_slow_intr(adapter);
559fb51b 902}
8199d3a7 903
f1d3d38a
SH		 904/* Power sequencing is a work-around for Intel's XPAKs. */
905static void power_sequence_xpak(adapter_t* adapter)
559fb51b 906{
356bd146
FR		 907 u32 mod_detect;
908 u32 gpo;
559fb51b 909
356bd146
FR		 910 /* Check for XPAK */
911 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
f1d3d38a
SH		 912 if (!(ELMER0_GP_BIT5 & mod_detect)) {
913 /* XPAK is present */
914 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
915 gpo |= ELMER0_GP_BIT18;
916 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
8199d3a7
CL		 917 }
918}
919
920int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
921 struct adapter_params *p)
922{
923 p->chip_version = bi->chip_term;
f1d3d38a 924 p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
8199d3a7 925 if (p->chip_version == CHBT_TERM_T1 ||
f1d3d38a
SH		 926 p->chip_version == CHBT_TERM_T2 ||
927 p->chip_version == CHBT_TERM_FPGA) {
559fb51b 928 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
8199d3a7
CL		 929
930 val = G_TP_PC_REV(val);
931 if (val == 2)
932 p->chip_revision = TERM_T1B;
933 else if (val == 3)
934 p->chip_revision = TERM_T2;
935 else
936 return -1;
937 } else
938 return -1;
939 return 0;
940}
941
942/*
943 * Enable board components other than the Chelsio chip, such as external MAC
944 * and PHY.
945 */
946static int board_init(adapter_t *adapter, const struct board_info *bi)
947{
948 switch (bi->board) {
f1d3d38a 949 case CHBT_BOARD_8000:
8199d3a7
CL		 950 case CHBT_BOARD_N110:
951 case CHBT_BOARD_N210:
f1d3d38a
SH		 952 case CHBT_BOARD_CHT210:
953 case CHBT_BOARD_COUGAR:
356bd146
FR		 954 t1_tpi_par(adapter, 0xf);
955 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
f1d3d38a
SH		 956 break;
957 case CHBT_BOARD_CHT110:
356bd146
FR		 958 t1_tpi_par(adapter, 0xf);
959 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
f1d3d38a 960
356bd146
FR		 961 /* TBD XXX Might not need. This fixes a problem
962 * described in the Intel SR XPAK errata.
963 */
964 power_sequence_xpak(adapter);
8199d3a7 965 break;
352c417d 966#ifdef CONFIG_CHELSIO_T1_1G
356bd146
FR		 967 case CHBT_BOARD_CHT204E:
968 /* add config space write here */
352c417d
SH		 969 case CHBT_BOARD_CHT204:
970 case CHBT_BOARD_CHT204V:
971 case CHBT_BOARD_CHN204:
356bd146
FR		 972 t1_tpi_par(adapter, 0xf);
973 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
974 break;
352c417d
SH		 975 case CHBT_BOARD_CHT101:
976 case CHBT_BOARD_7500:
356bd146
FR		 977 t1_tpi_par(adapter, 0xf);
978 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
352c417d
SH		 979 break;
980#endif
8199d3a7
CL		 981 }
982 return 0;
983}
984
985/*
986 * Initialize and configure the Terminator HW modules. Note that external
987 * MAC and PHYs are initialized separately.
988 */
989int t1_init_hw_modules(adapter_t *adapter)
990{
991 int err = -EIO;
992 const struct board_info *bi = board_info(adapter);
993
559fb51b
SB		 994 if (!bi->clock_mc4) {
995 u32 val = readl(adapter->regs + A_MC4_CFG);
8199d3a7 996
559fb51b
SB		 997 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
998 writel(F_M_BUS_ENABLE | F_TCAM_RESET,
999 adapter->regs + A_MC5_CONFIG);
8199d3a7
CL		 1000 }
1001
352c417d
SH		 1002#ifdef CONFIG_CHELSIO_T1_COUGAR
1003 if (adapter->cspi && t1_cspi_init(adapter->cspi))
1004 goto out_err;
1005#endif
8199d3a7
CL		 1006 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
1007 bi->espi_nports))
1008 goto out_err;
1009
f1d3d38a
SH		 1010 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
1011 goto out_err;
8199d3a7
CL		 1012
1013 err = t1_sge_configure(adapter->sge, &adapter->params.sge);
1014 if (err)
1015 goto out_err;
1016
1017 err = 0;
356bd146 1018out_err:
8199d3a7
CL		 1019 return err;
1020}
1021
1022/*
1023 * Determine a card's PCI mode.
1024 */
559fb51b 1025static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
8199d3a7 1026{
f71e1309 1027 static const unsigned short speed_map[] = { 33, 66, 100, 133 };
8199d3a7
CL		 1028 u32 pci_mode;
1029
1030 pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
1031 p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
1032 p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
1033 p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
1034}
1035
1036/*
1037 * Release the structures holding the SW per-Terminator-HW-module state.
1038 */
1039void t1_free_sw_modules(adapter_t *adapter)
1040{
1041 unsigned int i;
1042
1043 for_each_port(adapter, i) {
1044 struct cmac *mac = adapter->port[i].mac;
1045 struct cphy *phy = adapter->port[i].phy;
1046
1047 if (mac)
1048 mac->ops->destroy(mac);
1049 if (phy)
1050 phy->ops->destroy(phy);
1051 }
1052
1053 if (adapter->sge)
1054 t1_sge_destroy(adapter->sge);
f1d3d38a
SH		 1055 if (adapter->tp)
1056 t1_tp_destroy(adapter->tp);
8199d3a7
CL		 1057 if (adapter->espi)
1058 t1_espi_destroy(adapter->espi);
352c417d 1059#ifdef CONFIG_CHELSIO_T1_COUGAR
356bd146 1060 if (adapter->cspi)
352c417d
SH		 1061 t1_cspi_destroy(adapter->cspi);
1062#endif
8199d3a7
CL		 1063}
1064
1065static void __devinit init_link_config(struct link_config *lc,
1066 const struct board_info *bi)
1067{
1068 lc->supported = bi->caps;
1069 lc->requested_speed = lc->speed = SPEED_INVALID;
1070 lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
1071 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
1072 if (lc->supported & SUPPORTED_Autoneg) {
1073 lc->advertising = lc->supported;
1074 lc->autoneg = AUTONEG_ENABLE;
1075 lc->requested_fc |= PAUSE_AUTONEG;
1076 } else {
1077 lc->advertising = 0;
1078 lc->autoneg = AUTONEG_DISABLE;
1079 }
1080}
1081
352c417d
SH		 1082#ifdef CONFIG_CHELSIO_T1_COUGAR
1083 if (bi->clock_cspi && !(adapter->cspi = t1_cspi_create(adapter))) {
1084 CH_ERR("%s: CSPI initialization failed\n",
1085 adapter->name);
1086 goto error;
356bd146 1087 }
352c417d 1088#endif
8199d3a7
CL		 1089
1090/*
1091 * Allocate and initialize the data structures that hold the SW state of
1092 * the Terminator HW modules.
1093 */
1094int __devinit t1_init_sw_modules(adapter_t *adapter,
1095 const struct board_info *bi)
1096{
1097 unsigned int i;
1098
1099 adapter->params.brd_info = bi;
1100 adapter->params.nports = bi->port_number;
1101 adapter->params.stats_update_period = bi->gmac->stats_update_period;
1102
1103 adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1104 if (!adapter->sge) {
1105 CH_ERR("%s: SGE initialization failed\n",
1106 adapter->name);
1107 goto error;
1108 }
1109
8199d3a7
CL		 1110 if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1111 CH_ERR("%s: ESPI initialization failed\n",
1112 adapter->name);
1113 goto error;
1114 }
1115
f1d3d38a
SH		 1116 adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1117 if (!adapter->tp) {
1118 CH_ERR("%s: TP initialization failed\n",
1119 adapter->name);
1120 goto error;
1121 }
1122
8199d3a7
CL		 1123 board_init(adapter, bi);
1124 bi->mdio_ops->init(adapter, bi);
1125 if (bi->gphy->reset)
1126 bi->gphy->reset(adapter);
1127 if (bi->gmac->reset)
1128 bi->gmac->reset(adapter);
1129
1130 for_each_port(adapter, i) {
1131 u8 hw_addr[6];
1132 struct cmac *mac;
1133 int phy_addr = bi->mdio_phybaseaddr + i;
1134
1135 adapter->port[i].phy = bi->gphy->create(adapter, phy_addr,
1136 bi->mdio_ops);
1137 if (!adapter->port[i].phy) {
1138 CH_ERR("%s: PHY %d initialization failed\n",
1139 adapter->name, i);
1140 goto error;
1141 }
1142
1143 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1144 if (!mac) {
1145 CH_ERR("%s: MAC %d initialization failed\n",
1146 adapter->name, i);
1147 goto error;
1148 }
1149
1150 /*
1151 * Get the port's MAC addresses either from the EEPROM if one
1152 * exists or the one hardcoded in the MAC.
1153 */
f1d3d38a
SH		 1154 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1155 mac->ops->macaddress_get(mac, hw_addr);
1156 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
8199d3a7 1157 CH_ERR("%s: could not read MAC address from VPD ROM\n",
559fb51b 1158 adapter->port[i].dev->name);
8199d3a7
CL		 1159 goto error;
1160 }
559fb51b 1161 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
8199d3a7
CL		 1162 init_link_config(&adapter->port[i].link_config, bi);
1163 }
1164
1165 get_pci_mode(adapter, &adapter->params.pci);
1166 t1_interrupts_clear(adapter);
1167 return 0;
1168
f1d3d38a 1169error:
8199d3a7
CL		 1170 t1_free_sw_modules(adapter);
1171 return -1;
1172}
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