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bnx2x: New link code
[net-next-2.6.git] / drivers / net / bnx2x.h
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a2fbb9ea
ET		 1/* bnx2x.h: Broadcom Everest network driver.
2 *
49d66772 3 * Copyright (c) 2007-2008 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
17/* error/debug prints */
18
19#define DRV_MODULE_NAME "bnx2x"
20#define PFX DRV_MODULE_NAME ": "
21
22/* for messages that are currently off */
23#define BNX2X_MSG_OFF 0
24#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */
25#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */
26#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */
27#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */
f1410647
ET		 28#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
29#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
a2fbb9ea
ET		 30
31#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
32
33/* regular debug print */
34#define DP(__mask, __fmt, __args...) do { \
35 if (bp->msglevel & (__mask)) \
36 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
37 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
38 } while (0)
39
40/* for errors (never masked) */
41#define BNX2X_ERR(__fmt, __args...) do { \
42 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
43 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
44 } while (0)
45
f1410647
ET		 46/* for logging (never masked) */
47#define BNX2X_LOG(__fmt, __args...) do { \
48 printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
49 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
50 } while (0)
51
a2fbb9ea
ET		 52/* before we have a dev->name use dev_info() */
53#define BNX2X_DEV_INFO(__fmt, __args...) do { \
54 if (bp->msglevel & NETIF_MSG_PROBE) \
55 dev_info(&bp->pdev->dev, __fmt, ##__args); \
56 } while (0)
57
58
59#ifdef BNX2X_STOP_ON_ERROR
60#define bnx2x_panic() do { \
61 bp->panic = 1; \
62 BNX2X_ERR("driver assert\n"); \
63 bnx2x_disable_int(bp); \
64 bnx2x_panic_dump(bp); \
65 } while (0)
66#else
67#define bnx2x_panic() do { \
68 BNX2X_ERR("driver assert\n"); \
69 bnx2x_panic_dump(bp); \
70 } while (0)
71#endif
72
73
74#define U64_LO(x) (((u64)x) & 0xffffffff)
75#define U64_HI(x) (((u64)x) >> 32)
76#define HILO_U64(hi, lo) (((u64)hi << 32) + lo)
77
78
79#define REG_ADDR(bp, offset) (bp->regview + offset)
80
81#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
82#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
83#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
84
85#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
86#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
87#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
88#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
89
90#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
91#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
92
c18487ee
YR		 93#define REG_RD_DMAE(bp, offset, valp, len32) \
94 do { \
95 bnx2x_read_dmae(bp, offset, len32);\
96 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
97 } while (0)
98
a2fbb9ea
ET		 99#define REG_WR_DMAE(bp, offset, val, len32) \
100 do { \
101 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
102 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
103 offset, len32); \
104 } while (0)
105
106#define SHMEM_RD(bp, type) \
107 REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
108#define SHMEM_WR(bp, type, val) \
109 REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
110
111#define NIG_WR(reg, val) REG_WR(bp, reg, val)
112#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
113#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
114
115
116#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
117
118#define for_each_nondefault_queue(bp, var) \
119 for (var = 1; var < bp->num_queues; var++)
120#define is_multi(bp) (bp->num_queues > 1)
121
122
123struct regp {
124 u32 lo;
125 u32 hi;
126};
127
128struct bmac_stats {
129 struct regp tx_gtpkt;
130 struct regp tx_gtxpf;
131 struct regp tx_gtfcs;
132 struct regp tx_gtmca;
133 struct regp tx_gtgca;
134 struct regp tx_gtfrg;
135 struct regp tx_gtovr;
136 struct regp tx_gt64;
137 struct regp tx_gt127;
138 struct regp tx_gt255; /* 10 */
139 struct regp tx_gt511;
140 struct regp tx_gt1023;
141 struct regp tx_gt1518;
142 struct regp tx_gt2047;
143 struct regp tx_gt4095;
144 struct regp tx_gt9216;
145 struct regp tx_gt16383;
146 struct regp tx_gtmax;
147 struct regp tx_gtufl;
148 struct regp tx_gterr; /* 20 */
149 struct regp tx_gtbyt;
150
151 struct regp rx_gr64;
152 struct regp rx_gr127;
153 struct regp rx_gr255;
154 struct regp rx_gr511;
155 struct regp rx_gr1023;
156 struct regp rx_gr1518;
157 struct regp rx_gr2047;
158 struct regp rx_gr4095;
159 struct regp rx_gr9216; /* 30 */
160 struct regp rx_gr16383;
161 struct regp rx_grmax;
162 struct regp rx_grpkt;
163 struct regp rx_grfcs;
164 struct regp rx_grmca;
165 struct regp rx_grbca;
166 struct regp rx_grxcf;
167 struct regp rx_grxpf;
168 struct regp rx_grxuo;
169 struct regp rx_grjbr; /* 40 */
170 struct regp rx_grovr;
171 struct regp rx_grflr;
172 struct regp rx_grmeg;
173 struct regp rx_grmeb;
174 struct regp rx_grbyt;
175 struct regp rx_grund;
176 struct regp rx_grfrg;
177 struct regp rx_grerb;
178 struct regp rx_grfre;
179 struct regp rx_gripj; /* 50 */
180};
181
182struct emac_stats {
183 u32 rx_ifhcinoctets ;
184 u32 rx_ifhcinbadoctets ;
185 u32 rx_etherstatsfragments ;
186 u32 rx_ifhcinucastpkts ;
187 u32 rx_ifhcinmulticastpkts ;
188 u32 rx_ifhcinbroadcastpkts ;
189 u32 rx_dot3statsfcserrors ;
190 u32 rx_dot3statsalignmenterrors ;
191 u32 rx_dot3statscarriersenseerrors ;
192 u32 rx_xonpauseframesreceived ; /* 10 */
193 u32 rx_xoffpauseframesreceived ;
194 u32 rx_maccontrolframesreceived ;
195 u32 rx_xoffstateentered ;
196 u32 rx_dot3statsframestoolong ;
197 u32 rx_etherstatsjabbers ;
198 u32 rx_etherstatsundersizepkts ;
199 u32 rx_etherstatspkts64octets ;
200 u32 rx_etherstatspkts65octetsto127octets ;
201 u32 rx_etherstatspkts128octetsto255octets ;
202 u32 rx_etherstatspkts256octetsto511octets ; /* 20 */
203 u32 rx_etherstatspkts512octetsto1023octets ;
204 u32 rx_etherstatspkts1024octetsto1522octets;
205 u32 rx_etherstatspktsover1522octets ;
206
207 u32 rx_falsecarriererrors ;
208
209 u32 tx_ifhcoutoctets ;
210 u32 tx_ifhcoutbadoctets ;
211 u32 tx_etherstatscollisions ;
212 u32 tx_outxonsent ;
213 u32 tx_outxoffsent ;
214 u32 tx_flowcontroldone ; /* 30 */
215 u32 tx_dot3statssinglecollisionframes ;
216 u32 tx_dot3statsmultiplecollisionframes ;
217 u32 tx_dot3statsdeferredtransmissions ;
218 u32 tx_dot3statsexcessivecollisions ;
219 u32 tx_dot3statslatecollisions ;
220 u32 tx_ifhcoutucastpkts ;
221 u32 tx_ifhcoutmulticastpkts ;
222 u32 tx_ifhcoutbroadcastpkts ;
223 u32 tx_etherstatspkts64octets ;
224 u32 tx_etherstatspkts65octetsto127octets ; /* 40 */
225 u32 tx_etherstatspkts128octetsto255octets ;
226 u32 tx_etherstatspkts256octetsto511octets ;
227 u32 tx_etherstatspkts512octetsto1023octets ;
228 u32 tx_etherstatspkts1024octetsto1522octet ;
229 u32 tx_etherstatspktsover1522octets ;
230 u32 tx_dot3statsinternalmactransmiterrors ; /* 46 */
231};
232
233union mac_stats {
234 struct emac_stats emac;
235 struct bmac_stats bmac;
236};
237
238struct nig_stats {
239 u32 brb_discard;
240 u32 brb_packet;
241 u32 brb_truncate;
242 u32 flow_ctrl_discard;
243 u32 flow_ctrl_octets;
244 u32 flow_ctrl_packet;
245 u32 mng_discard;
246 u32 mng_octet_inp;
247 u32 mng_octet_out;
248 u32 mng_packet_inp;
249 u32 mng_packet_out;
250 u32 pbf_octets;
251 u32 pbf_packet;
252 u32 safc_inp;
253 u32 done;
254 u32 pad;
255};
256
257struct bnx2x_eth_stats {
258 u32 pad; /* to make long counters u64 aligned */
259 u32 mac_stx_start;
260 u32 total_bytes_received_hi;
261 u32 total_bytes_received_lo;
262 u32 total_bytes_transmitted_hi;
263 u32 total_bytes_transmitted_lo;
264 u32 total_unicast_packets_received_hi;
265 u32 total_unicast_packets_received_lo;
266 u32 total_multicast_packets_received_hi;
267 u32 total_multicast_packets_received_lo;
268 u32 total_broadcast_packets_received_hi;
269 u32 total_broadcast_packets_received_lo;
270 u32 total_unicast_packets_transmitted_hi;
271 u32 total_unicast_packets_transmitted_lo;
272 u32 total_multicast_packets_transmitted_hi;
273 u32 total_multicast_packets_transmitted_lo;
274 u32 total_broadcast_packets_transmitted_hi;
275 u32 total_broadcast_packets_transmitted_lo;
276 u32 crc_receive_errors;
277 u32 alignment_errors;
278 u32 false_carrier_detections;
279 u32 runt_packets_received;
280 u32 jabber_packets_received;
281 u32 pause_xon_frames_received;
282 u32 pause_xoff_frames_received;
283 u32 pause_xon_frames_transmitted;
284 u32 pause_xoff_frames_transmitted;
285 u32 single_collision_transmit_frames;
286 u32 multiple_collision_transmit_frames;
287 u32 late_collision_frames;
288 u32 excessive_collision_frames;
289 u32 control_frames_received;
290 u32 frames_received_64_bytes;
291 u32 frames_received_65_127_bytes;
292 u32 frames_received_128_255_bytes;
293 u32 frames_received_256_511_bytes;
294 u32 frames_received_512_1023_bytes;
295 u32 frames_received_1024_1522_bytes;
296 u32 frames_received_1523_9022_bytes;
297 u32 frames_transmitted_64_bytes;
298 u32 frames_transmitted_65_127_bytes;
299 u32 frames_transmitted_128_255_bytes;
300 u32 frames_transmitted_256_511_bytes;
301 u32 frames_transmitted_512_1023_bytes;
302 u32 frames_transmitted_1024_1522_bytes;
303 u32 frames_transmitted_1523_9022_bytes;
304 u32 valid_bytes_received_hi;
305 u32 valid_bytes_received_lo;
306 u32 error_runt_packets_received;
307 u32 error_jabber_packets_received;
308 u32 mac_stx_end;
309
310 u32 pad2;
311 u32 stat_IfHCInBadOctets_hi;
312 u32 stat_IfHCInBadOctets_lo;
313 u32 stat_IfHCOutBadOctets_hi;
314 u32 stat_IfHCOutBadOctets_lo;
315 u32 stat_Dot3statsFramesTooLong;
316 u32 stat_Dot3statsInternalMacTransmitErrors;
317 u32 stat_Dot3StatsCarrierSenseErrors;
318 u32 stat_Dot3StatsDeferredTransmissions;
319 u32 stat_FlowControlDone;
320 u32 stat_XoffStateEntered;
321
322 u32 x_total_sent_bytes_hi;
323 u32 x_total_sent_bytes_lo;
324 u32 x_total_sent_pkts;
325
326 u32 t_rcv_unicast_bytes_hi;
327 u32 t_rcv_unicast_bytes_lo;
328 u32 t_rcv_broadcast_bytes_hi;
329 u32 t_rcv_broadcast_bytes_lo;
330 u32 t_rcv_multicast_bytes_hi;
331 u32 t_rcv_multicast_bytes_lo;
332 u32 t_total_rcv_pkt;
333
334 u32 checksum_discard;
335 u32 packets_too_big_discard;
336 u32 no_buff_discard;
337 u32 ttl0_discard;
338 u32 mac_discard;
339 u32 mac_filter_discard;
340 u32 xxoverflow_discard;
341 u32 brb_truncate_discard;
342
343 u32 brb_discard;
344 u32 brb_packet;
345 u32 brb_truncate;
346 u32 flow_ctrl_discard;
347 u32 flow_ctrl_octets;
348 u32 flow_ctrl_packet;
349 u32 mng_discard;
350 u32 mng_octet_inp;
351 u32 mng_octet_out;
352 u32 mng_packet_inp;
353 u32 mng_packet_out;
354 u32 pbf_octets;
355 u32 pbf_packet;
356 u32 safc_inp;
357 u32 driver_xoff;
358 u32 number_of_bugs_found_in_stats_spec; /* just kidding */
359};
360
361#define MAC_STX_NA 0xffffffff
362
363#ifdef BNX2X_MULTI
364#define MAX_CONTEXT 16
365#else
366#define MAX_CONTEXT 1
367#endif
368
369union cdu_context {
370 struct eth_context eth;
371 char pad[1024];
372};
373
374#define MAX_DMAE_C 5
375
376/* DMA memory not used in fastpath */
377struct bnx2x_slowpath {
378 union cdu_context context[MAX_CONTEXT];
379 struct eth_stats_query fw_stats;
380 struct mac_configuration_cmd mac_config;
381 struct mac_configuration_cmd mcast_config;
382
383 /* used by dmae command executer */
384 struct dmae_command dmae[MAX_DMAE_C];
385
386 union mac_stats mac_stats;
387 struct nig_stats nig;
388 struct bnx2x_eth_stats eth_stats;
389
390 u32 wb_comp;
391#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
392 u32 wb_data[4];
393};
394
395#define bnx2x_sp(bp, var) (&bp->slowpath->var)
396#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
397#define bnx2x_sp_mapping(bp, var) \
398 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
399
400
401struct sw_rx_bd {
402 struct sk_buff *skb;
403 DECLARE_PCI_UNMAP_ADDR(mapping)
404};
405
406struct sw_tx_bd {
407 struct sk_buff *skb;
408 u16 first_bd;
409};
410
411struct bnx2x_fastpath {
412
413 struct napi_struct napi;
414
415 struct host_status_block *status_blk;
416 dma_addr_t status_blk_mapping;
417
418 struct eth_tx_db_data *hw_tx_prods;
419 dma_addr_t tx_prods_mapping;
420
421 struct sw_tx_bd *tx_buf_ring;
422
423 struct eth_tx_bd *tx_desc_ring;
424 dma_addr_t tx_desc_mapping;
425
426 struct sw_rx_bd *rx_buf_ring;
427
428 struct eth_rx_bd *rx_desc_ring;
429 dma_addr_t rx_desc_mapping;
430
431 union eth_rx_cqe *rx_comp_ring;
432 dma_addr_t rx_comp_mapping;
433
434 int state;
435#define BNX2X_FP_STATE_CLOSED 0
436#define BNX2X_FP_STATE_IRQ 0x80000
437#define BNX2X_FP_STATE_OPENING 0x90000
438#define BNX2X_FP_STATE_OPEN 0xa0000
439#define BNX2X_FP_STATE_HALTING 0xb0000
440#define BNX2X_FP_STATE_HALTED 0xc0000
a2fbb9ea
ET		 441
442 int index;
443
444 u16 tx_pkt_prod;
445 u16 tx_pkt_cons;
446 u16 tx_bd_prod;
447 u16 tx_bd_cons;
448 u16 *tx_cons_sb;
449
450 u16 fp_c_idx;
451 u16 fp_u_idx;
452
453 u16 rx_bd_prod;
454 u16 rx_bd_cons;
455 u16 rx_comp_prod;
456 u16 rx_comp_cons;
457 u16 *rx_cons_sb;
458
459 unsigned long tx_pkt,
460 rx_pkt,
461 rx_calls;
462
463 struct bnx2x *bp; /* parent */
464};
465
466#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
467
468
469/* attn group wiring */
470#define MAX_DYNAMIC_ATTN_GRPS 8
471
472struct attn_route {
473 u32 sig[4];
474};
475
476struct bnx2x {
477 /* Fields used in the tx and intr/napi performance paths
478 * are grouped together in the beginning of the structure
479 */
480 struct bnx2x_fastpath *fp;
481 void __iomem *regview;
482 void __iomem *doorbells;
483
484 struct net_device *dev;
485 struct pci_dev *pdev;
486
487 atomic_t intr_sem;
488 struct msix_entry msix_table[MAX_CONTEXT+1];
489
490 int tx_ring_size;
491
492#ifdef BCM_VLAN
493 struct vlan_group *vlgrp;
494#endif
495
496 u32 rx_csum;
497 u32 rx_offset;
498 u32 rx_buf_use_size; /* useable size */
499 u32 rx_buf_size; /* with alignment */
500#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
501#define ETH_MIN_PACKET_SIZE 60
502#define ETH_MAX_PACKET_SIZE 1500
503#define ETH_MAX_JUMBO_PACKET_SIZE 9600
504
505 struct host_def_status_block *def_status_blk;
506#define DEF_SB_ID 16
507 u16 def_c_idx;
508 u16 def_u_idx;
509 u16 def_t_idx;
510 u16 def_x_idx;
511 u16 def_att_idx;
512 u32 attn_state;
513 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
514 u32 aeu_mask;
515 u32 nig_mask;
516
517 /* slow path ring */
518 struct eth_spe *spq;
519 dma_addr_t spq_mapping;
520 u16 spq_prod_idx;
a2fbb9ea
ET		 521 struct eth_spe *spq_prod_bd;
522 struct eth_spe *spq_last_bd;
523 u16 *dsb_sp_prod;
524 u16 spq_left; /* serialize spq */
525 spinlock_t spq_lock;
526
527 /* Flag for marking that there is either
528 * STAT_QUERY or CFC DELETE ramrod pending
529 */
530 u8 stat_pending;
531
c14423fe 532 /* End of fields used in the performance code paths */
a2fbb9ea
ET		 533
534 int panic;
535 int msglevel;
536
537 u32 flags;
538#define PCIX_FLAG 1
539#define PCI_32BIT_FLAG 2
540#define ONE_TDMA_FLAG 4 /* no longer used */
541#define NO_WOL_FLAG 8
542#define USING_DAC_FLAG 0x10
543#define USING_MSIX_FLAG 0x20
544#define ASF_ENABLE_FLAG 0x40
545
546 int port;
547
548 int pm_cap;
549 int pcie_cap;
550
c18487ee
YR		 551 struct work_struct sp_task;
552 struct work_struct reset_task;
a2fbb9ea
ET		 553
554 struct timer_list timer;
555 int timer_interval;
556 int current_interval;
557
558 u32 shmem_base;
559
560 u32 chip_id;
561/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
562#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
563
564#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
a2fbb9ea
ET		 565
566#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
567#define CHIP_REV_Ax 0x00000000
568#define CHIP_REV_Bx 0x00001000
569#define CHIP_REV_Cx 0x00002000
570#define CHIP_REV_EMUL 0x0000e000
571#define CHIP_REV_FPGA 0x0000f000
572#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
573 (CHIP_REV(bp) == CHIP_REV_FPGA))
c18487ee
YR		 574#define CHIP_REV_IS_EMUL(bp) (CHIP_REV(bp) == CHIP_REV_EMUL)
575#define CHIP_REV_IS_FPGA(bp) (CHIP_REV(bp) == CHIP_REV_FPGA)
a2fbb9ea
ET		 576
577#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
578#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f)
579
580 u16 fw_seq;
581 u16 fw_drv_pulse_wr_seq;
582 u32 fw_mb;
583
584 u32 hw_config;
f1410647 585 u32 board;
c18487ee
YR		 586
587 struct link_params link_params;
588
589 struct link_vars link_vars;
590
591 u32 link_config;
a2fbb9ea
ET		 592
593 u32 supported;
594/* link settings - missing defines */
595#define SUPPORTED_2500baseT_Full (1 << 15)
a2fbb9ea 596
a2fbb9ea 597 u32 phy_addr;
c18487ee
YR		 598
599 /* used to synchronize phy accesses */
600 struct mutex phy_mutex;
601
a2fbb9ea
ET		 602 u32 phy_id;
603
a2fbb9ea 604
a2fbb9ea
ET		 605 u32 advertising;
606/* link settings - missing defines */
607#define ADVERTISED_2500baseT_Full (1 << 15)
a2fbb9ea 608
a2fbb9ea
ET		 609
610 u32 bc_ver;
611
612 int flash_size;
613#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
614#define NVRAM_TIMEOUT_COUNT 30000
615#define NVRAM_PAGE_SIZE 256
616
f1410647
ET		 617 u8 wol;
618
a2fbb9ea
ET		 619 int rx_ring_size;
620
621 u16 tx_quick_cons_trip_int;
622 u16 tx_quick_cons_trip;
623 u16 tx_ticks_int;
624 u16 tx_ticks;
625
626 u16 rx_quick_cons_trip_int;
627 u16 rx_quick_cons_trip;
628 u16 rx_ticks_int;
629 u16 rx_ticks;
630
631 u32 stats_ticks;
632
633 int state;
634#define BNX2X_STATE_CLOSED 0x0
635#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
636#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
637#define BNX2X_STATE_OPEN 0x3000
638#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
639#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
640#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
641#define BNX2X_STATE_ERROR 0xF000
642
643 int num_queues;
644
645 u32 rx_mode;
646#define BNX2X_RX_MODE_NONE 0
647#define BNX2X_RX_MODE_NORMAL 1
648#define BNX2X_RX_MODE_ALLMULTI 2
649#define BNX2X_RX_MODE_PROMISC 3
650#define BNX2X_MAX_MULTICAST 64
651#define BNX2X_MAX_EMUL_MULTI 16
652
653 dma_addr_t def_status_blk_mapping;
654
655 struct bnx2x_slowpath *slowpath;
656 dma_addr_t slowpath_mapping;
657
658#ifdef BCM_ISCSI
659 void *t1;
660 dma_addr_t t1_mapping;
661 void *t2;
662 dma_addr_t t2_mapping;
663 void *timers;
664 dma_addr_t timers_mapping;
665 void *qm;
666 dma_addr_t qm_mapping;
667#endif
668
669 char *name;
a2fbb9ea
ET		 670
671 /* used to synchronize stats collecting */
672 int stats_state;
673#define STATS_STATE_DISABLE 0
674#define STATS_STATE_ENABLE 1
675#define STATS_STATE_STOP 2 /* stop stats on next iteration */
676
677 /* used by dmae command loader */
678 struct dmae_command dmae;
679 int executer_idx;
680
681 u32 old_brb_discard;
682 struct bmac_stats old_bmac;
683 struct tstorm_per_client_stats old_tclient;
684 struct z_stream_s *strm;
685 void *gunzip_buf;
686 dma_addr_t gunzip_mapping;
687 int gunzip_outlen;
688#define FW_BUF_SIZE 0x8000
689
690};
691
692
693/* DMAE command defines */
694#define DMAE_CMD_SRC_PCI 0
695#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
696
697#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
698#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
699
700#define DMAE_CMD_C_DST_PCI 0
701#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
702
703#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
704
705#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
706#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
707#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
708#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
709
710#define DMAE_CMD_PORT_0 0
711#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
712
713#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
714#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
715
716#define DMAE_LEN32_MAX 0x400
717
c18487ee
YR		 718void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
719void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
720 u32 len32);
721int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
722
a2fbb9ea
ET		 723
724/* MC hsi */
725#define RX_COPY_THRESH 92
726#define BCM_PAGE_BITS 12
727#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
728
729#define NUM_TX_RINGS 16
730#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
731#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
732#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
733#define MAX_TX_BD (NUM_TX_BD - 1)
734#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
735#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
736 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
737#define TX_BD(x) ((x) & MAX_TX_BD)
738#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
739
740/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
741#define NUM_RX_RINGS 8
742#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
743#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
744#define RX_DESC_MASK (RX_DESC_CNT - 1)
745#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
746#define MAX_RX_BD (NUM_RX_BD - 1)
747#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
748#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
749 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
750#define RX_BD(x) ((x) & MAX_RX_BD)
751
752#define NUM_RCQ_RINGS (NUM_RX_RINGS * 2)
753#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
754#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
755#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
756#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
757#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
758#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
759 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
760#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
761
762
763/* used on a CID received from the HW */
764#define SW_CID(x) (le32_to_cpu(x) & \
765 (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
766#define CQE_CMD(x) (le32_to_cpu(x) >> \
767 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
768
769#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
770 le32_to_cpu((bd)->addr_lo))
771#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
772
773
774#define STROM_ASSERT_ARRAY_SIZE 50
775
776
777#define MDIO_INDIRECT_REG_ADDR 0x1f
778#define MDIO_SET_REG_BANK(bp, reg_bank) \
779 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
780
781#define MDIO_ACCESS_TIMEOUT 1000
782
783
784/* must be used on a CID before placing it on a HW ring */
785#define HW_CID(bp, x) (x | (bp->port << 23))
786
787#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
788#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
789
790#define ATTN_NIG_FOR_FUNC (1L << 8)
791#define ATTN_SW_TIMER_4_FUNC (1L << 9)
792#define GPIO_2_FUNC (1L << 10)
793#define GPIO_3_FUNC (1L << 11)
794#define GPIO_4_FUNC (1L << 12)
795#define ATTN_GENERAL_ATTN_1 (1L << 13)
796#define ATTN_GENERAL_ATTN_2 (1L << 14)
797#define ATTN_GENERAL_ATTN_3 (1L << 15)
798#define ATTN_GENERAL_ATTN_4 (1L << 13)
799#define ATTN_GENERAL_ATTN_5 (1L << 14)
800#define ATTN_GENERAL_ATTN_6 (1L << 15)
801
802#define ATTN_HARD_WIRED_MASK 0xff00
803#define ATTENTION_ID 4
804
805
806#define BNX2X_BTR 3
807#define MAX_SPQ_PENDING 8
808
809
0e39e645
ET		 810#define BNX2X_NUM_STATS 34
811#define BNX2X_NUM_TESTS 1
a2fbb9ea
ET		 812
813
814#define DPM_TRIGER_TYPE 0x40
815#define DOORBELL(bp, cid, val) \
816 do { \
817 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
818 DPM_TRIGER_TYPE); \
819 } while (0)
820
25047950
ET		 821/* PCIE link and speed */
822#define PCICFG_LINK_WIDTH 0x1f00000
823#define PCICFG_LINK_WIDTH_SHIFT 20
824#define PCICFG_LINK_SPEED 0xf0000
825#define PCICFG_LINK_SPEED_SHIFT 16
a2fbb9ea 826
f1410647 827#define BMAC_CONTROL_RX_ENABLE 2
96fc1784
ET		 828
829#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
830
a2fbb9ea
ET		 831/* stuff added to make the code fit 80Col */
832
833#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
834#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
835#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \
836 (TPA_TYPE_START | TPA_TYPE_END))
837#define BNX2X_RX_SUM_OK(cqe) \
838 (!(cqe->fast_path_cqe.status_flags & \
839 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
840 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
841
842#define BNX2X_RX_SUM_FIX(cqe) \
843 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
844 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
845 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
846
847
a2fbb9ea
ET		 848#define BNX2X_MC_ASSERT_BITS \
849 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
850 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
851 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
852 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
853
854#define BNX2X_MCP_ASSERT \
855 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
856
857#define BNX2X_DOORQ_ASSERT \
858 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
859
860#define HW_INTERRUT_ASSERT_SET_0 \
861 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
862 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
863 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
864 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
865#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
866 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
867 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
868 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
869 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
870#define HW_INTERRUT_ASSERT_SET_1 \
871 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
872 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
873 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
874 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
875 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
876 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
877 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
878 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
879 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
880 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
881 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
882#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
883 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
884 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
885 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
886 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
887 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
888 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
889 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
890 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
891 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
892 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
893#define HW_INTERRUT_ASSERT_SET_2 \
894 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
895 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
896 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
897 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
898 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
899#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
900 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
901 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
902 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
903 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
904 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
905 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
906
907
908#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
909 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
910 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
911
912
913#define MULTI_FLAGS \
914 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
915 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
916 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
917 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
918 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
919
920#define MULTI_MASK 0x7f
921
922
923#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
924#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
925#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
926
927#define BNX2X_RX_SB_INDEX \
928 &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
929
930#define BNX2X_TX_SB_INDEX \
931 &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
932
933#define BNX2X_SP_DSB_INDEX \
934&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
935
936
937#define CAM_IS_INVALID(x) \
938(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
939
940#define CAM_INVALIDATE(x) \
941x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE
942
943
944/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
945
946#endif /* bnx2x.h */
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