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e10bc84d | 1 | /* Copyright 2008-2010 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef BNX2X_LINK_H | |
18 | #define BNX2X_LINK_H | |
19 | ||
20 | ||
21 | ||
22 | /***********************************************************/ | |
23 | /* Defines */ | |
24 | /***********************************************************/ | |
25 | #define DEFAULT_PHY_DEV_ADDR 3 | |
26 | ||
27 | ||
28 | ||
c0700f90 DM |
29 | #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO |
30 | #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX | |
31 | #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX | |
32 | #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH | |
33 | #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE | |
ea4e040a YR |
34 | |
35 | #define SPEED_AUTO_NEG 0 | |
36 | #define SPEED_12000 12000 | |
37 | #define SPEED_12500 12500 | |
38 | #define SPEED_13000 13000 | |
39 | #define SPEED_15000 15000 | |
40 | #define SPEED_16000 16000 | |
41 | ||
4d295db0 EG |
42 | #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14 |
43 | #define SFP_EEPROM_VENDOR_NAME_SIZE 16 | |
44 | #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25 | |
45 | #define SFP_EEPROM_VENDOR_OUI_SIZE 3 | |
46 | #define SFP_EEPROM_PART_NO_ADDR 0x28 | |
47 | #define SFP_EEPROM_PART_NO_SIZE 16 | |
48 | #define PWR_FLT_ERR_MSG_LEN 250 | |
b7737c9b YR |
49 | |
50 | #define XGXS_EXT_PHY_TYPE(ext_phy_config) \ | |
51 | ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) | |
52 | #define XGXS_EXT_PHY_ADDR(ext_phy_config) \ | |
53 | (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ | |
54 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) | |
55 | #define SERDES_EXT_PHY_TYPE(ext_phy_config) \ | |
56 | ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) | |
57 | ||
e10bc84d YR |
58 | /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ |
59 | #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) | |
60 | /* Single Media board contains single external phy */ | |
61 | #define SINGLE_MEDIA(params) (params->num_phys == 2) | |
a22f0788 YR |
62 | /* Dual Media board contains two external phy with different media */ |
63 | #define DUAL_MEDIA(params) (params->num_phys == 3) | |
64 | #define FW_PARAM_MDIO_CTRL_OFFSET 16 | |
65 | #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ | |
66 | (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET) | |
ea4e040a YR |
67 | /***********************************************************/ |
68 | /* Structs */ | |
69 | /***********************************************************/ | |
e10bc84d YR |
70 | #define INT_PHY 0 |
71 | #define EXT_PHY1 1 | |
a22f0788 YR |
72 | #define EXT_PHY2 2 |
73 | #define MAX_PHYS 3 | |
e10bc84d | 74 | |
b7737c9b YR |
75 | /* Same configuration is shared between the XGXS and the first external phy */ |
76 | #define LINK_CONFIG_SIZE (MAX_PHYS - 1) | |
77 | #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \ | |
78 | 0 : (_phy_idx - 1)) | |
e10bc84d YR |
79 | /***********************************************************/ |
80 | /* bnx2x_phy struct */ | |
81 | /* Defines the required arguments and function per phy */ | |
82 | /***********************************************************/ | |
83 | struct link_vars; | |
84 | struct link_params; | |
85 | struct bnx2x_phy; | |
86 | ||
b7737c9b YR |
87 | typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params, |
88 | struct link_vars *vars); | |
89 | typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params, | |
90 | struct link_vars *vars); | |
91 | typedef void (*link_reset_t)(struct bnx2x_phy *phy, | |
92 | struct link_params *params); | |
93 | typedef void (*config_loopback_t)(struct bnx2x_phy *phy, | |
94 | struct link_params *params); | |
95 | typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len); | |
96 | typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params); | |
97 | typedef void (*set_link_led_t)(struct bnx2x_phy *phy, | |
98 | struct link_params *params, u8 mode); | |
a22f0788 YR |
99 | typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy, |
100 | struct link_params *params, u32 action); | |
b7737c9b | 101 | |
e10bc84d YR |
102 | struct bnx2x_phy { |
103 | u32 type; | |
104 | ||
105 | /* Loaded during init */ | |
106 | u8 addr; | |
107 | ||
b7737c9b YR |
108 | u8 flags; |
109 | /* Require HW lock */ | |
110 | #define FLAGS_HW_LOCK_REQUIRED (1<<0) | |
111 | /* No Over-Current detection */ | |
112 | #define FLAGS_NOC (1<<1) | |
113 | /* Fan failure detection required */ | |
114 | #define FLAGS_FAN_FAILURE_DET_REQ (1<<2) | |
115 | /* Initialize first the XGXS and only then the phy itself */ | |
a22f0788 YR |
116 | #define FLAGS_INIT_XGXS_FIRST (1<<3) |
117 | #define FLAGS_REARM_LATCH_SIGNAL (1<<6) | |
118 | #define FLAGS_SFP_NOT_APPROVED (1<<7) | |
b7737c9b YR |
119 | |
120 | u8 def_md_devad; | |
121 | u8 reserved; | |
122 | /* preemphasis values for the rx side */ | |
123 | u16 rx_preemphasis[4]; | |
124 | ||
125 | /* preemphasis values for the tx side */ | |
126 | u16 tx_preemphasis[4]; | |
127 | ||
128 | /* EMAC address for access MDIO */ | |
e10bc84d | 129 | u32 mdio_ctrl; |
b7737c9b YR |
130 | |
131 | u32 supported; | |
132 | ||
133 | u32 media_type; | |
134 | #define ETH_PHY_UNSPECIFIED 0x0 | |
135 | #define ETH_PHY_SFP_FIBER 0x1 | |
136 | #define ETH_PHY_XFP_FIBER 0x2 | |
137 | #define ETH_PHY_DA_TWINAX 0x3 | |
138 | #define ETH_PHY_BASE_T 0x4 | |
139 | #define ETH_PHY_NOT_PRESENT 0xff | |
140 | ||
141 | /* The address in which version is located*/ | |
142 | u32 ver_addr; | |
143 | ||
144 | u16 req_flow_ctrl; | |
145 | ||
146 | u16 req_line_speed; | |
147 | ||
148 | u32 speed_cap_mask; | |
149 | ||
150 | u16 req_duplex; | |
151 | u16 rsrv; | |
152 | /* Called per phy/port init, and it configures LASI, speed, autoneg, | |
153 | duplex, flow control negotiation, etc. */ | |
154 | config_init_t config_init; | |
155 | ||
156 | /* Called due to interrupt. It determines the link, speed */ | |
157 | read_status_t read_status; | |
158 | ||
159 | /* Called when driver is unloading. Should reset the phy */ | |
160 | link_reset_t link_reset; | |
161 | ||
162 | /* Set the loopback configuration for the phy */ | |
163 | config_loopback_t config_loopback; | |
164 | ||
165 | /* Format the given raw number into str up to len */ | |
166 | format_fw_ver_t format_fw_ver; | |
167 | ||
168 | /* Reset the phy (both ports) */ | |
169 | hw_reset_t hw_reset; | |
170 | ||
171 | /* Set link led mode (on/off/oper)*/ | |
172 | set_link_led_t set_link_led; | |
a22f0788 YR |
173 | |
174 | /* PHY Specific tasks */ | |
175 | phy_specific_func_t phy_specific_func; | |
176 | #define DISABLE_TX 1 | |
177 | #define ENABLE_TX 2 | |
e10bc84d YR |
178 | }; |
179 | ||
ea4e040a YR |
180 | /* Inputs parameters to the CLC */ |
181 | struct link_params { | |
182 | ||
183 | u8 port; | |
184 | ||
185 | /* Default / User Configuration */ | |
186 | u8 loopback_mode; | |
187 | #define LOOPBACK_NONE 0 | |
188 | #define LOOPBACK_EMAC 1 | |
189 | #define LOOPBACK_BMAC 2 | |
de6eae1f | 190 | #define LOOPBACK_XGXS 3 |
ea4e040a | 191 | #define LOOPBACK_EXT_PHY 4 |
6bbca910 | 192 | #define LOOPBACK_EXT 5 |
ea4e040a | 193 | |
ea4e040a YR |
194 | /* Device parameters */ |
195 | u8 mac_addr[6]; | |
8c99e7b0 | 196 | |
a22f0788 YR |
197 | u16 req_duplex[LINK_CONFIG_SIZE]; |
198 | u16 req_flow_ctrl[LINK_CONFIG_SIZE]; | |
199 | ||
200 | u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ | |
201 | ||
ea4e040a YR |
202 | /* shmem parameters */ |
203 | u32 shmem_base; | |
a22f0788 YR |
204 | u32 shmem2_base; |
205 | u32 speed_cap_mask[LINK_CONFIG_SIZE]; | |
ea4e040a YR |
206 | u32 switch_cfg; |
207 | #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH | |
208 | #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH | |
209 | #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT | |
210 | ||
ea4e040a | 211 | u32 lane_config; |
659bc5c4 | 212 | |
ea4e040a YR |
213 | /* Phy register parameter */ |
214 | u32 chip_id; | |
215 | ||
589abe3a EG |
216 | u32 feature_config_flags; |
217 | #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) | |
4d295db0 | 218 | #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) |
a22f0788 | 219 | #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) |
e10bc84d YR |
220 | /* Will be populated during common init */ |
221 | struct bnx2x_phy phy[MAX_PHYS]; | |
222 | ||
223 | /* Will be populated during common init */ | |
224 | u8 num_phys; | |
1ef70b9c | 225 | |
b7737c9b YR |
226 | u8 rsrv; |
227 | u16 hw_led_mode; /* part of the hw_config read from the shmem */ | |
a22f0788 | 228 | u32 multi_phy_config; |
b7737c9b | 229 | |
ea4e040a YR |
230 | /* Device pointer passed to all callback functions */ |
231 | struct bnx2x *bp; | |
a22f0788 YR |
232 | u16 req_fc_auto_adv; /* Should be set to TX / BOTH when |
233 | req_flow_ctrl is set to AUTO */ | |
ea4e040a YR |
234 | }; |
235 | ||
236 | /* Output parameters */ | |
237 | struct link_vars { | |
1ef70b9c EG |
238 | u8 phy_flags; |
239 | ||
240 | u8 mac_type; | |
241 | #define MAC_TYPE_NONE 0 | |
242 | #define MAC_TYPE_EMAC 1 | |
243 | #define MAC_TYPE_BMAC 2 | |
244 | ||
ea4e040a YR |
245 | u8 phy_link_up; /* internal phy link indication */ |
246 | u8 link_up; | |
1ef70b9c EG |
247 | |
248 | u16 line_speed; | |
ea4e040a | 249 | u16 duplex; |
1ef70b9c | 250 | |
ea4e040a | 251 | u16 flow_ctrl; |
1ef70b9c | 252 | u16 ieee_fc; |
ea4e040a | 253 | |
ea4e040a YR |
254 | /* The same definitions as the shmem parameter */ |
255 | u32 link_status; | |
256 | }; | |
257 | ||
258 | /***********************************************************/ | |
259 | /* Functions */ | |
260 | /***********************************************************/ | |
ea4e040a YR |
261 | u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output); |
262 | ||
589abe3a EG |
263 | /* Reset the link. Should be called when driver or interface goes down |
264 | Before calling phy firmware upgrade, the reset_ext_phy should be set | |
265 | to 0 */ | |
266 | u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |
267 | u8 reset_ext_phy); | |
ea4e040a YR |
268 | |
269 | /* bnx2x_link_update should be called upon link interrupt */ | |
270 | u8 bnx2x_link_update(struct link_params *input, struct link_vars *output); | |
271 | ||
e10bc84d | 272 | /* use the following phy functions to read/write from external_phy |
ea4e040a YR |
273 | In order to use it to read/write internal phy registers, use |
274 | DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as | |
ea4e040a | 275 | the register */ |
e10bc84d YR |
276 | u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
277 | u8 devad, u16 reg, u16 *ret_val); | |
ea4e040a | 278 | |
e10bc84d YR |
279 | u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr, |
280 | u8 devad, u16 reg, u16 val); | |
c18aa15d | 281 | |
e10bc84d YR |
282 | u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
283 | u8 devad, u16 reg, u16 *ret_val); | |
ea4e040a | 284 | |
e10bc84d YR |
285 | u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
286 | u8 devad, u16 reg, u16 val); | |
ea4e040a | 287 | /* Reads the link_status from the shmem, |
33471629 | 288 | and update the link vars accordingly */ |
ea4e040a YR |
289 | void bnx2x_link_status_update(struct link_params *input, |
290 | struct link_vars *output); | |
291 | /* returns string representing the fw_version of the external phy */ | |
292 | u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, | |
293 | u8 *version, u16 len); | |
294 | ||
295 | /* Set/Unset the led | |
296 | Basically, the CLC takes care of the led for the link, but in case one needs | |
33471629 | 297 | to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to |
ea4e040a | 298 | blink the led, and LED_MODE_OFF to set the led off.*/ |
7f02c4ad YR |
299 | u8 bnx2x_set_led(struct link_params *params, struct link_vars *vars, |
300 | u8 mode, u32 speed); | |
301 | #define LED_MODE_OFF 0 | |
302 | #define LED_MODE_ON 1 | |
303 | #define LED_MODE_OPER 2 | |
304 | #define LED_MODE_FRONT_PANEL_OFF 3 | |
ea4e040a YR |
305 | |
306 | u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value); | |
307 | ||
589abe3a EG |
308 | /* bnx2x_handle_module_detect_int should be called upon module detection |
309 | interrupt */ | |
310 | void bnx2x_handle_module_detect_int(struct link_params *params); | |
311 | ||
ea4e040a YR |
312 | /* Get the actual link status. In case it returns 0, link is up, |
313 | otherwise link is down*/ | |
a22f0788 YR |
314 | u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars, |
315 | u8 is_serdes); | |
ea4e040a | 316 | |
6bbca910 | 317 | /* One-time initialization for external phy after power up */ |
a22f0788 | 318 | u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base); |
ea4e040a | 319 | |
f57a6025 EG |
320 | /* Reset the external PHY using GPIO */ |
321 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); | |
322 | ||
e10bc84d YR |
323 | /* Reset the external of SFX7101 */ |
324 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy); | |
356e2385 | 325 | |
e10bc84d YR |
326 | u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
327 | struct link_params *params, u16 addr, | |
4d295db0 | 328 | u8 byte_cnt, u8 *o_buf); |
d90d96ba YR |
329 | |
330 | void bnx2x_hw_reset_phy(struct link_params *params); | |
331 | ||
332 | /* Checks if HW lock is required for this phy/board type */ | |
a22f0788 YR |
333 | u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, |
334 | u32 shmem2_base); | |
335 | ||
e10bc84d YR |
336 | /* Returns the aggregative supported attributes of the phys on board */ |
337 | u32 bnx2x_supported_attr(struct link_params *params, u8 phy_idx); | |
a22f0788 YR |
338 | |
339 | /* Check swap bit and adjust PHY order */ | |
340 | u32 bnx2x_phy_selection(struct link_params *params); | |
341 | ||
e10bc84d YR |
342 | /* Probe the phys on board, and populate them in "params" */ |
343 | u8 bnx2x_phy_probe(struct link_params *params); | |
d90d96ba | 344 | /* Checks if fan failure detection is required on one of the phys on board */ |
a22f0788 YR |
345 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base, |
346 | u32 shmem2_base, u8 port); | |
d90d96ba | 347 | |
ea4e040a | 348 | #endif /* BNX2X_LINK_H */ |