[net-next-2.6.git] / drivers / net / bnx2x / bnx2x_link.h

/* Copyright 2008-2010 Broadcom Corporation
 *
 * Unless you and Broadcom execute a separate written software license
 * agreement governing use of this software, this software is licensed to you
 * under the terms of the GNU General Public License version 2, available
 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
 *
 * Notwithstanding the above, under no circumstances may you combine this
 * software in any way with any other Broadcom software provided under a
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *
 * Written by Yaniv Rosner
 *
 */

#ifndef BNX2X_LINK_H
#define BNX2X_LINK_H


/***********************************************************/
/*                         Defines                         */
/***********************************************************/
#define DEFAULT_PHY_DEV_ADDR	3
#define E2_DEFAULT_PHY_DEV_ADDR	5


#define BNX2X_FLOW_CTRL_AUTO		PORT_FEATURE_FLOW_CONTROL_AUTO
#define BNX2X_FLOW_CTRL_TX		PORT_FEATURE_FLOW_CONTROL_TX
#define BNX2X_FLOW_CTRL_RX		PORT_FEATURE_FLOW_CONTROL_RX
#define BNX2X_FLOW_CTRL_BOTH		PORT_FEATURE_FLOW_CONTROL_BOTH
#define BNX2X_FLOW_CTRL_NONE		PORT_FEATURE_FLOW_CONTROL_NONE

#define SPEED_AUTO_NEG	    0
#define SPEED_12000		12000
#define SPEED_12500		12500
#define SPEED_13000		13000
#define SPEED_15000		15000
#define SPEED_16000		16000

#define SFP_EEPROM_VENDOR_NAME_ADDR		0x14
#define SFP_EEPROM_VENDOR_NAME_SIZE		16
#define SFP_EEPROM_VENDOR_OUI_ADDR		0x25
#define SFP_EEPROM_VENDOR_OUI_SIZE		3
#define SFP_EEPROM_PART_NO_ADDR 		0x28
#define SFP_EEPROM_PART_NO_SIZE		16
#define PWR_FLT_ERR_MSG_LEN			250

#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
		 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)

/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
#define SINGLE_MEDIA_DIRECT(params)	(params->num_phys == 1)
/* Single Media board contains single external phy */
#define SINGLE_MEDIA(params)		(params->num_phys == 2)
/* Dual Media board contains two external phy with different media */
#define DUAL_MEDIA(params)		(params->num_phys == 3)
#define FW_PARAM_MDIO_CTRL_OFFSET 16
#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
	(phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
/***********************************************************/
/*                         Structs                         */
/***********************************************************/
#define INT_PHY		0
#define EXT_PHY1	1
#define EXT_PHY2	2
#define MAX_PHYS	3

/* Same configuration is shared between the XGXS and the first external phy */
#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
					 0 : (_phy_idx - 1))
/***********************************************************/
/*                      bnx2x_phy struct                     */
/*  Defines the required arguments and function per phy    */
/***********************************************************/
struct link_vars;
struct link_params;
struct bnx2x_phy;

typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
			    struct link_vars *vars);
typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
			    struct link_vars *vars);
typedef void (*link_reset_t)(struct bnx2x_phy *phy,
			     struct link_params *params);
typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
				  struct link_params *params);
typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
			       struct link_params *params, u8 mode);
typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
				    struct link_params *params, u32 action);

struct bnx2x_phy {
	u32 type;

	/* Loaded during init */
	u8 addr;

	u8 flags;
	/* Require HW lock */
#define FLAGS_HW_LOCK_REQUIRED		(1<<0)
	/* No Over-Current detection */
#define FLAGS_NOC			(1<<1)
	/* Fan failure detection required */
#define FLAGS_FAN_FAILURE_DET_REQ	(1<<2)
	/* Initialize first the XGXS and only then the phy itself */
#define FLAGS_INIT_XGXS_FIRST		(1<<3)
#define FLAGS_REARM_LATCH_SIGNAL	(1<<6)
#define FLAGS_SFP_NOT_APPROVED		(1<<7)

	u8 def_md_devad;
	u8 reserved;
	/* preemphasis values for the rx side */
	u16 rx_preemphasis[4];

	/* preemphasis values for the tx side */
	u16 tx_preemphasis[4];

	/* EMAC address for access MDIO */
	u32 mdio_ctrl;

	u32 supported;

	u32 media_type;
#define	ETH_PHY_UNSPECIFIED 0x0
#define	ETH_PHY_SFP_FIBER   0x1
#define	ETH_PHY_XFP_FIBER   0x2
#define	ETH_PHY_DA_TWINAX   0x3
#define	ETH_PHY_BASE_T      0x4
#define	ETH_PHY_NOT_PRESENT 0xff

	/* The address in which version is located*/
	u32 ver_addr;

	u16 req_flow_ctrl;

	u16 req_line_speed;

	u32 speed_cap_mask;

	u16 req_duplex;
	u16 rsrv;
	/* Called per phy/port init, and it configures LASI, speed, autoneg,
	 duplex, flow control negotiation, etc. */
	config_init_t config_init;

	/* Called due to interrupt. It determines the link, speed */
	read_status_t read_status;

	/* Called when driver is unloading. Should reset the phy */
	link_reset_t link_reset;

	/* Set the loopback configuration for the phy */
	config_loopback_t config_loopback;

	/* Format the given raw number into str up to len */
	format_fw_ver_t format_fw_ver;

	/* Reset the phy (both ports) */
	hw_reset_t hw_reset;

	/* Set link led mode (on/off/oper)*/
	set_link_led_t set_link_led;

	/* PHY Specific tasks */
	phy_specific_func_t phy_specific_func;
#define DISABLE_TX	1
#define ENABLE_TX	2
};

/* Inputs parameters to the CLC */
struct link_params {

	u8 port;

	/* Default / User Configuration */
	u8 loopback_mode;
#define LOOPBACK_NONE	0
#define LOOPBACK_EMAC	1
#define LOOPBACK_BMAC	2
#define LOOPBACK_XGXS		3
#define LOOPBACK_EXT_PHY	4
#define LOOPBACK_EXT 	5

	/* Device parameters */
	u8 mac_addr[6];

	u16 req_duplex[LINK_CONFIG_SIZE];
	u16 req_flow_ctrl[LINK_CONFIG_SIZE];

	u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */

	/* shmem parameters */
	u32 shmem_base;
	u32 shmem2_base;
	u32 speed_cap_mask[LINK_CONFIG_SIZE];
	u32 switch_cfg;
#define SWITCH_CFG_1G		PORT_FEATURE_CON_SWITCH_1G_SWITCH
#define SWITCH_CFG_10G		PORT_FEATURE_CON_SWITCH_10G_SWITCH
#define SWITCH_CFG_AUTO_DETECT	PORT_FEATURE_CON_SWITCH_AUTO_DETECT

	u32 lane_config;

	/* Phy register parameter */
	u32 chip_id;

	u32 feature_config_flags;
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY	(1<<2)
#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY	(1<<3)
	/* Will be populated during common init */
	struct bnx2x_phy phy[MAX_PHYS];

	/* Will be populated during common init */
	u8 num_phys;

	u8 rsrv;
	u16 hw_led_mode; /* part of the hw_config read from the shmem */
	u32 multi_phy_config;

	/* Device pointer passed to all callback functions */
	struct bnx2x *bp;
	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
				req_flow_ctrl is set to AUTO */
};

/* Output parameters */
struct link_vars {
	u8 phy_flags;

	u8 mac_type;
#define MAC_TYPE_NONE		0
#define MAC_TYPE_EMAC		1
#define MAC_TYPE_BMAC		2

	u8 phy_link_up; /* internal phy link indication */
	u8 link_up;

	u16 line_speed;
	u16 duplex;

	u16 flow_ctrl;
	u16 ieee_fc;

	/* The same definitions as the shmem parameter */
	u32 link_status;
};

/***********************************************************/
/*                         Functions                       */
/***********************************************************/
u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);

/* Reset the link. Should be called when driver or interface goes down
   Before calling phy firmware upgrade, the reset_ext_phy should be set
   to 0 */
u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
		  u8 reset_ext_phy);

/* bnx2x_link_update should be called upon link interrupt */
u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);

/* use the following phy functions to read/write from external_phy
  In order to use it to read/write internal phy registers, use
  DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
  the register */
u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
		  u8 devad, u16 reg, u16 *ret_val);

u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
		   u8 devad, u16 reg, u16 val);
/* Reads the link_status from the shmem,
   and update the link vars accordingly */
void bnx2x_link_status_update(struct link_params *input,
			    struct link_vars *output);
/* returns string representing the fw_version of the external phy */
u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
			      u8 *version, u16 len);

/* Set/Unset the led
   Basically, the CLC takes care of the led for the link, but in case one needs
   to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
   blink the led, and LED_MODE_OFF to set the led off.*/
u8 bnx2x_set_led(struct link_params *params, struct link_vars *vars,
		 u8 mode, u32 speed);
#define LED_MODE_OFF			0
#define LED_MODE_ON			1
#define LED_MODE_OPER			2
#define LED_MODE_FRONT_PANEL_OFF	3

/* bnx2x_handle_module_detect_int should be called upon module detection
   interrupt */
void bnx2x_handle_module_detect_int(struct link_params *params);

/* Get the actual link status. In case it returns 0, link is up,
	otherwise link is down*/
u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars,
		   u8 is_serdes);

/* One-time initialization for external phy after power up */
u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
			 u32 shmem2_base_path[], u32 chip_id);

/* Reset the external PHY using GPIO */
void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);

/* Reset the external of SFX7101 */
void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);

void bnx2x_hw_reset_phy(struct link_params *params);

/* Checks if HW lock is required for this phy/board type */
u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
			  u32 shmem2_base);

/* Check swap bit and adjust PHY order */
u32 bnx2x_phy_selection(struct link_params *params);

/* Probe the phys on board, and populate them in "params" */
u8 bnx2x_phy_probe(struct link_params *params);
/* Checks if fan failure detection is required on one of the phys on board */
u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
			     u32 shmem2_base, u8 port);

#endif /* BNX2X_LINK_H */
Commit	Line	Data
e10bc84d	1	/* Copyright 2008-2010 Broadcom Corporation
ea4e040a YR	2	*
	3	* Unless you and Broadcom execute a separate written software license
	4	* agreement governing use of this software, this software is licensed to you
	5	* under the terms of the GNU General Public License version 2, available
	6	* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
	7	*
	8	* Notwithstanding the above, under no circumstances may you combine this
	9	* software in any way with any other Broadcom software provided under a
	10	* license other than the GPL, without Broadcom's express prior written
	11	* consent.
	12	*
	13	* Written by Yaniv Rosner
	14	*
	15	*/
	16
	17	#ifndef BNX2X_LINK_H
	18	#define BNX2X_LINK_H
	19
	20
	21
	22	/***********************************************************/
	23	/* Defines */
	24	/***********************************************************/
f2e0899f DK	25	#define DEFAULT_PHY_DEV_ADDR 3
f2e0899f DK	26	#define E2_DEFAULT_PHY_DEV_ADDR 5
ea4e040a YR	27
	28
	29
c0700f90 DM	30	#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
	31	#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
	32	#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
	33	#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
	34	#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
ea4e040a YR	35
	36	#define SPEED_AUTO_NEG 0
	37	#define SPEED_12000 12000
	38	#define SPEED_12500 12500
	39	#define SPEED_13000 13000
	40	#define SPEED_15000 15000
	41	#define SPEED_16000 16000
	42
4d295db0 EG	43	#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
	44	#define SFP_EEPROM_VENDOR_NAME_SIZE 16
	45	#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
	46	#define SFP_EEPROM_VENDOR_OUI_SIZE 3
	47	#define SFP_EEPROM_PART_NO_ADDR 0x28
	48	#define SFP_EEPROM_PART_NO_SIZE 16
	49	#define PWR_FLT_ERR_MSG_LEN 250
b7737c9b YR	50
	51	#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
	52	((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
	53	#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
	54	(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
	55	PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
	56	#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
	57	((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
	58
e10bc84d YR	59	/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
	60	#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
	61	/* Single Media board contains single external phy */
	62	#define SINGLE_MEDIA(params) (params->num_phys == 2)
a22f0788 YR	63	/* Dual Media board contains two external phy with different media */
	64	#define DUAL_MEDIA(params) (params->num_phys == 3)
	65	#define FW_PARAM_MDIO_CTRL_OFFSET 16
	66	#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
	67	(phy_addr \| phy_type \| mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
ea4e040a YR	68	/***********************************************************/
	69	/* Structs */
	70	/***********************************************************/
e10bc84d YR	71	#define INT_PHY 0
e10bc84d YR	72	#define EXT_PHY1 1
a22f0788 YR	73	#define EXT_PHY2 2
a22f0788 YR	74	#define MAX_PHYS 3
e10bc84d	75
b7737c9b YR	76	/* Same configuration is shared between the XGXS and the first external phy */
	77	#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
	78	#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
	79	0 : (_phy_idx - 1))
e10bc84d YR	80	/***********************************************************/
	81	/* bnx2x_phy struct */
	82	/* Defines the required arguments and function per phy */
	83	/***********************************************************/
	84	struct link_vars;
	85	struct link_params;
	86	struct bnx2x_phy;
	87
b7737c9b YR	88	typedef u8 (config_init_t)(struct bnx2x_phy phy, struct link_params *params,
	89	struct link_vars *vars);
	90	typedef u8 (read_status_t)(struct bnx2x_phy phy, struct link_params *params,
	91	struct link_vars *vars);
	92	typedef void (link_reset_t)(struct bnx2x_phy phy,
	93	struct link_params *params);
	94	typedef void (config_loopback_t)(struct bnx2x_phy phy,
	95	struct link_params *params);
	96	typedef u8 (format_fw_ver_t)(u32 raw, u8 str, u16 *len);
	97	typedef void (hw_reset_t)(struct bnx2x_phy phy, struct link_params *params);
	98	typedef void (set_link_led_t)(struct bnx2x_phy phy,
	99	struct link_params *params, u8 mode);
a22f0788 YR	100	typedef void (phy_specific_func_t)(struct bnx2x_phy phy,
a22f0788 YR	101	struct link_params *params, u32 action);
b7737c9b	102
e10bc84d YR	103	struct bnx2x_phy {
	104	u32 type;
	105
	106	/* Loaded during init */
	107	u8 addr;
	108
b7737c9b YR	109	u8 flags;
	110	/* Require HW lock */
	111	#define FLAGS_HW_LOCK_REQUIRED (1<<0)
	112	/* No Over-Current detection */
	113	#define FLAGS_NOC (1<<1)
	114	/* Fan failure detection required */
	115	#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
	116	/* Initialize first the XGXS and only then the phy itself */
a22f0788 YR	117	#define FLAGS_INIT_XGXS_FIRST (1<<3)
	118	#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
	119	#define FLAGS_SFP_NOT_APPROVED (1<<7)
b7737c9b YR	120
	121	u8 def_md_devad;
	122	u8 reserved;
	123	/* preemphasis values for the rx side */
	124	u16 rx_preemphasis[4];
	125
	126	/* preemphasis values for the tx side */
	127	u16 tx_preemphasis[4];
	128
	129	/* EMAC address for access MDIO */
e10bc84d	130	u32 mdio_ctrl;
b7737c9b YR	131
	132	u32 supported;
	133
	134	u32 media_type;
	135	#define ETH_PHY_UNSPECIFIED 0x0
	136	#define ETH_PHY_SFP_FIBER 0x1
	137	#define ETH_PHY_XFP_FIBER 0x2
	138	#define ETH_PHY_DA_TWINAX 0x3
	139	#define ETH_PHY_BASE_T 0x4
	140	#define ETH_PHY_NOT_PRESENT 0xff
	141
	142	/* The address in which version is located*/
	143	u32 ver_addr;
	144
	145	u16 req_flow_ctrl;
	146
	147	u16 req_line_speed;
	148
	149	u32 speed_cap_mask;
	150
	151	u16 req_duplex;
	152	u16 rsrv;
	153	/* Called per phy/port init, and it configures LASI, speed, autoneg,
	154	duplex, flow control negotiation, etc. */
	155	config_init_t config_init;
	156
	157	/* Called due to interrupt. It determines the link, speed */
	158	read_status_t read_status;
	159
	160	/* Called when driver is unloading. Should reset the phy */
	161	link_reset_t link_reset;
	162
	163	/* Set the loopback configuration for the phy */
	164	config_loopback_t config_loopback;
	165
	166	/* Format the given raw number into str up to len */
	167	format_fw_ver_t format_fw_ver;
	168
	169	/* Reset the phy (both ports) */
	170	hw_reset_t hw_reset;
	171
	172	/* Set link led mode (on/off/oper)*/
	173	set_link_led_t set_link_led;
a22f0788 YR	174
	175	/* PHY Specific tasks */
	176	phy_specific_func_t phy_specific_func;
	177	#define DISABLE_TX 1
	178	#define ENABLE_TX 2
e10bc84d YR	179	};
e10bc84d YR	180
ea4e040a YR	181	/* Inputs parameters to the CLC */
	182	struct link_params {
	183
	184	u8 port;
	185
	186	/* Default / User Configuration */
	187	u8 loopback_mode;
	188	#define LOOPBACK_NONE 0
	189	#define LOOPBACK_EMAC 1
	190	#define LOOPBACK_BMAC 2
de6eae1f	191	#define LOOPBACK_XGXS 3
ea4e040a	192	#define LOOPBACK_EXT_PHY 4
6bbca910	193	#define LOOPBACK_EXT 5
ea4e040a	194
ea4e040a YR	195	/* Device parameters */
ea4e040a YR	196	u8 mac_addr[6];
8c99e7b0	197
a22f0788 YR	198	u16 req_duplex[LINK_CONFIG_SIZE];
	199	u16 req_flow_ctrl[LINK_CONFIG_SIZE];
	200
	201	u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
	202
ea4e040a YR	203	/* shmem parameters */
ea4e040a YR	204	u32 shmem_base;
a22f0788 YR	205	u32 shmem2_base;
a22f0788 YR	206	u32 speed_cap_mask[LINK_CONFIG_SIZE];
ea4e040a YR	207	u32 switch_cfg;
	208	#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
	209	#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
	210	#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
	211
ea4e040a	212	u32 lane_config;
659bc5c4	213
ea4e040a YR	214	/* Phy register parameter */
	215	u32 chip_id;
	216
589abe3a EG	217	u32 feature_config_flags;
589abe3a EG	218	#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
4d295db0	219	#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
a22f0788	220	#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
e10bc84d YR	221	/* Will be populated during common init */
	222	struct bnx2x_phy phy[MAX_PHYS];
	223
	224	/* Will be populated during common init */
	225	u8 num_phys;
1ef70b9c	226
b7737c9b YR	227	u8 rsrv;
b7737c9b YR	228	u16 hw_led_mode; /* part of the hw_config read from the shmem */
a22f0788	229	u32 multi_phy_config;
b7737c9b	230
ea4e040a YR	231	/* Device pointer passed to all callback functions */
ea4e040a YR	232	struct bnx2x *bp;
a22f0788 YR	233	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
a22f0788 YR	234	req_flow_ctrl is set to AUTO */
ea4e040a YR	235	};
	236
	237	/* Output parameters */
	238	struct link_vars {
1ef70b9c EG	239	u8 phy_flags;
	240
	241	u8 mac_type;
	242	#define MAC_TYPE_NONE 0
	243	#define MAC_TYPE_EMAC 1
	244	#define MAC_TYPE_BMAC 2
	245
ea4e040a YR	246	u8 phy_link_up; /* internal phy link indication */
ea4e040a YR	247	u8 link_up;
1ef70b9c EG	248
1ef70b9c EG	249	u16 line_speed;
ea4e040a	250	u16 duplex;
1ef70b9c	251
ea4e040a	252	u16 flow_ctrl;
1ef70b9c	253	u16 ieee_fc;
ea4e040a	254
ea4e040a YR	255	/* The same definitions as the shmem parameter */
	256	u32 link_status;
	257	};
	258
	259	/***********************************************************/
	260	/* Functions */
	261	/***********************************************************/
ea4e040a YR	262	u8 bnx2x_phy_init(struct link_params input, struct link_vars output);
ea4e040a YR	263
589abe3a EG	264	/* Reset the link. Should be called when driver or interface goes down
	265	Before calling phy firmware upgrade, the reset_ext_phy should be set
	266	to 0 */
	267	u8 bnx2x_link_reset(struct link_params params, struct link_vars vars,
	268	u8 reset_ext_phy);
ea4e040a YR	269
	270	/* bnx2x_link_update should be called upon link interrupt */
	271	u8 bnx2x_link_update(struct link_params input, struct link_vars output);
	272
e10bc84d	273	/* use the following phy functions to read/write from external_phy
ea4e040a YR	274	In order to use it to read/write internal phy registers, use
ea4e040a YR	275	DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
ea4e040a	276	the register */
e10bc84d YR	277	u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
e10bc84d YR	278	u8 devad, u16 reg, u16 *ret_val);
ea4e040a	279
e10bc84d YR	280	u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
e10bc84d YR	281	u8 devad, u16 reg, u16 val);
ea4e040a	282	/* Reads the link_status from the shmem,
33471629	283	and update the link vars accordingly */
ea4e040a YR	284	void bnx2x_link_status_update(struct link_params *input,
	285	struct link_vars *output);
	286	/* returns string representing the fw_version of the external phy */
	287	u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
	288	u8 *version, u16 len);
	289
	290	/* Set/Unset the led
	291	Basically, the CLC takes care of the led for the link, but in case one needs
33471629	292	to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
ea4e040a	293	blink the led, and LED_MODE_OFF to set the led off.*/
7f02c4ad YR	294	u8 bnx2x_set_led(struct link_params params, struct link_vars vars,
	295	u8 mode, u32 speed);
	296	#define LED_MODE_OFF 0
	297	#define LED_MODE_ON 1
	298	#define LED_MODE_OPER 2
	299	#define LED_MODE_FRONT_PANEL_OFF 3
ea4e040a	300
589abe3a EG	301	/* bnx2x_handle_module_detect_int should be called upon module detection
	302	interrupt */
	303	void bnx2x_handle_module_detect_int(struct link_params *params);
	304
ea4e040a YR	305	/* Get the actual link status. In case it returns 0, link is up,
ea4e040a YR	306	otherwise link is down*/
a22f0788 YR	307	u8 bnx2x_test_link(struct link_params input, struct link_vars vars,
a22f0788 YR	308	u8 is_serdes);
ea4e040a	309
6bbca910	310	/* One-time initialization for external phy after power up */
f2e0899f DK	311	u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
f2e0899f DK	312	u32 shmem2_base_path[], u32 chip_id);
ea4e040a	313
f57a6025 EG	314	/* Reset the external PHY using GPIO */
	315	void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
	316
e10bc84d YR	317	/* Reset the external of SFX7101 */
e10bc84d YR	318	void bnx2x_sfx7101_sp_sw_reset(struct bnx2x bp, struct bnx2x_phy phy);
356e2385	319
d90d96ba YR	320	void bnx2x_hw_reset_phy(struct link_params *params);
	321
	322	/* Checks if HW lock is required for this phy/board type */
a22f0788 YR	323	u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
	324	u32 shmem2_base);
	325
a22f0788 YR	326	/* Check swap bit and adjust PHY order */
	327	u32 bnx2x_phy_selection(struct link_params *params);
	328
e10bc84d YR	329	/* Probe the phys on board, and populate them in "params" */
e10bc84d YR	330	u8 bnx2x_phy_probe(struct link_params *params);
d90d96ba	331	/* Checks if fan failure detection is required on one of the phys on board */
a22f0788 YR	332	u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
a22f0788 YR	333	u32 shmem2_base, u8 port);
d90d96ba	334
ea4e040a	335	#endif /* BNX2X_LINK_H */