]>
Commit | Line | Data |
---|---|---|
9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
3 | * Copyright (c) 2007-2010 Broadcom Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
21 | #include <linux/netdevice.h> | |
22 | ||
23 | ||
24 | #include "bnx2x.h" | |
25 | ||
d6214d7a | 26 | extern int num_queues; |
9f6c9258 DK |
27 | |
28 | /*********************** Interfaces **************************** | |
29 | * Functions that need to be implemented by each driver version | |
30 | */ | |
31 | ||
32 | /** | |
33 | * Initialize link parameters structure variables. | |
34 | * | |
35 | * @param bp | |
36 | * @param load_mode | |
37 | * | |
38 | * @return u8 | |
39 | */ | |
40 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); | |
41 | ||
42 | /** | |
43 | * Configure hw according to link parameters structure. | |
44 | * | |
45 | * @param bp | |
46 | */ | |
47 | void bnx2x_link_set(struct bnx2x *bp); | |
48 | ||
49 | /** | |
50 | * Query link status | |
51 | * | |
52 | * @param bp | |
a22f0788 | 53 | * @param is_serdes |
9f6c9258 DK |
54 | * |
55 | * @return 0 - link is UP | |
56 | */ | |
a22f0788 | 57 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 DK |
58 | |
59 | /** | |
60 | * Handles link status change | |
61 | * | |
62 | * @param bp | |
63 | */ | |
64 | void bnx2x__link_status_update(struct bnx2x *bp); | |
65 | ||
f85582f8 DK |
66 | /** |
67 | * Report link status to upper layer | |
68 | * | |
69 | * @param bp | |
70 | * | |
71 | * @return int | |
72 | */ | |
73 | void bnx2x_link_report(struct bnx2x *bp); | |
74 | ||
9f6c9258 DK |
75 | /** |
76 | * MSI-X slowpath interrupt handler | |
77 | * | |
78 | * @param irq | |
79 | * @param dev_instance | |
80 | * | |
81 | * @return irqreturn_t | |
82 | */ | |
83 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
84 | ||
85 | /** | |
86 | * non MSI-X interrupt handler | |
87 | * | |
88 | * @param irq | |
89 | * @param dev_instance | |
90 | * | |
91 | * @return irqreturn_t | |
92 | */ | |
93 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
94 | #ifdef BCM_CNIC | |
95 | ||
96 | /** | |
97 | * Send command to cnic driver | |
98 | * | |
99 | * @param bp | |
100 | * @param cmd | |
101 | */ | |
102 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
103 | ||
104 | /** | |
105 | * Provides cnic information for proper interrupt handling | |
106 | * | |
107 | * @param bp | |
108 | */ | |
109 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
110 | #endif | |
111 | ||
112 | /** | |
113 | * Enable HW interrupts. | |
114 | * | |
115 | * @param bp | |
116 | */ | |
117 | void bnx2x_int_enable(struct bnx2x *bp); | |
118 | ||
119 | /** | |
120 | * Disable interrupts. This function ensures that there are no | |
121 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
122 | * | |
123 | * @param bp | |
124 | * @param disable_hw if true, disable HW interrupts. | |
125 | */ | |
126 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
127 | ||
6891dd25 DK |
128 | /** |
129 | * Loads device firmware | |
130 | * | |
131 | * @param bp | |
132 | * | |
133 | * @return int | |
134 | */ | |
135 | int bnx2x_init_firmware(struct bnx2x *bp); | |
136 | ||
9f6c9258 DK |
137 | /** |
138 | * Init HW blocks according to current initialization stage: | |
139 | * COMMON, PORT or FUNCTION. | |
140 | * | |
141 | * @param bp | |
142 | * @param load_code: COMMON, PORT or FUNCTION | |
143 | * | |
144 | * @return int | |
145 | */ | |
146 | int bnx2x_init_hw(struct bnx2x *bp, u32 load_code); | |
147 | ||
148 | /** | |
149 | * Init driver internals: | |
150 | * - rings | |
151 | * - status blocks | |
152 | * - etc. | |
153 | * | |
154 | * @param bp | |
155 | * @param load_code COMMON, PORT or FUNCTION | |
156 | */ | |
157 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); | |
158 | ||
159 | /** | |
160 | * Allocate driver's memory. | |
161 | * | |
162 | * @param bp | |
163 | * | |
164 | * @return int | |
165 | */ | |
166 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
167 | ||
168 | /** | |
169 | * Release driver's memory. | |
170 | * | |
171 | * @param bp | |
172 | */ | |
173 | void bnx2x_free_mem(struct bnx2x *bp); | |
174 | ||
175 | /** | |
523224a3 | 176 | * Setup eth Client. |
9f6c9258 DK |
177 | * |
178 | * @param bp | |
523224a3 DK |
179 | * @param fp |
180 | * @param is_leading | |
9f6c9258 DK |
181 | * |
182 | * @return int | |
183 | */ | |
523224a3 DK |
184 | int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
185 | int is_leading); | |
9f6c9258 | 186 | |
9f6c9258 | 187 | /** |
d6214d7a | 188 | * Set number of queues according to mode |
9f6c9258 DK |
189 | * |
190 | * @param bp | |
191 | * | |
192 | */ | |
d6214d7a | 193 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
194 | |
195 | /** | |
196 | * Cleanup chip internals: | |
197 | * - Cleanup MAC configuration. | |
198 | * - Close clients. | |
199 | * - etc. | |
200 | * | |
201 | * @param bp | |
202 | * @param unload_mode | |
203 | */ | |
204 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); | |
205 | ||
206 | /** | |
207 | * Acquire HW lock. | |
208 | * | |
209 | * @param bp | |
210 | * @param resource Resource bit which was locked | |
211 | * | |
212 | * @return int | |
213 | */ | |
214 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
215 | ||
216 | /** | |
217 | * Release HW lock. | |
218 | * | |
219 | * @param bp driver handle | |
220 | * @param resource Resource bit which was locked | |
221 | * | |
222 | * @return int | |
223 | */ | |
224 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
225 | ||
226 | /** | |
227 | * Configure eth MAC address in the HW according to the value in | |
f85582f8 | 228 | * netdev->dev_addr. |
9f6c9258 DK |
229 | * |
230 | * @param bp driver handle | |
231 | * @param set | |
232 | */ | |
523224a3 | 233 | void bnx2x_set_eth_mac(struct bnx2x *bp, int set); |
9f6c9258 | 234 | |
9f6c9258 | 235 | /** |
f85582f8 | 236 | * Set MAC filtering configurations. |
9f6c9258 | 237 | * |
f85582f8 | 238 | * @remarks called with netif_tx_lock from dev_mcast.c |
9f6c9258 | 239 | * |
f85582f8 | 240 | * @param dev net_device |
9f6c9258 DK |
241 | */ |
242 | void bnx2x_set_rx_mode(struct net_device *dev); | |
243 | ||
244 | /** | |
245 | * Configure MAC filtering rules in a FW. | |
246 | * | |
247 | * @param bp driver handle | |
248 | */ | |
249 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp); | |
250 | ||
251 | /* Parity errors related */ | |
252 | void bnx2x_inc_load_cnt(struct bnx2x *bp); | |
253 | u32 bnx2x_dec_load_cnt(struct bnx2x *bp); | |
254 | bool bnx2x_chk_parity_attn(struct bnx2x *bp); | |
255 | bool bnx2x_reset_is_done(struct bnx2x *bp); | |
256 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); | |
257 | ||
258 | /** | |
259 | * Perform statistics handling according to event | |
260 | * | |
261 | * @param bp driver handle | |
f85582f8 | 262 | * @param event bnx2x_stats_event |
9f6c9258 DK |
263 | */ |
264 | void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event); | |
265 | ||
9f6c9258 | 266 | /** |
f85582f8 | 267 | * Handle ramrods completion |
9f6c9258 DK |
268 | * |
269 | * @param fp fastpath handle for the event | |
270 | * @param rr_cqe eth_rx_cqe | |
271 | */ | |
f85582f8 | 272 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 273 | |
523224a3 DK |
274 | /** |
275 | * Init/halt function before/after sending | |
276 | * CLIENT_SETUP/CFC_DEL for the first/last client. | |
277 | * | |
278 | * @param bp | |
279 | * | |
280 | * @return int | |
281 | */ | |
282 | int bnx2x_func_start(struct bnx2x *bp); | |
523224a3 DK |
283 | |
284 | /** | |
285 | * Prepare ILT configurations according to current driver | |
286 | * parameters. | |
287 | * | |
288 | * @param bp | |
289 | */ | |
290 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 291 | |
f85582f8 DK |
292 | /** |
293 | * Set power state to the requested value. Currently only D0 and | |
294 | * D3hot are supported. | |
295 | * | |
296 | * @param bp | |
297 | * @param state D0 or D3hot | |
298 | * | |
299 | * @return int | |
300 | */ | |
301 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
302 | ||
303 | /* dev_close main block */ | |
304 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); | |
305 | ||
306 | /* dev_open main block */ | |
307 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
308 | ||
309 | /* hard_xmit callback */ | |
310 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
311 | ||
312 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); | |
313 | ||
314 | /* NAPI poll Rx part */ | |
315 | int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); | |
316 | ||
317 | /* NAPI poll Tx part */ | |
318 | int bnx2x_tx_int(struct bnx2x_fastpath *fp); | |
319 | ||
320 | /* suspend/resume callbacks */ | |
321 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
322 | int bnx2x_resume(struct pci_dev *pdev); | |
323 | ||
324 | /* Release IRQ vectors */ | |
325 | void bnx2x_free_irq(struct bnx2x *bp); | |
326 | ||
327 | void bnx2x_init_rx_rings(struct bnx2x *bp); | |
328 | void bnx2x_free_skbs(struct bnx2x *bp); | |
329 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
330 | void bnx2x_netif_start(struct bnx2x *bp); | |
331 | ||
d6214d7a DK |
332 | /** |
333 | * Fill msix_table, request vectors, update num_queues according | |
334 | * to number of available vectors | |
335 | * | |
336 | * @param bp | |
337 | * | |
338 | * @return int | |
339 | */ | |
340 | int bnx2x_enable_msix(struct bnx2x *bp); | |
341 | ||
342 | /** | |
343 | * Request msi mode from OS, updated internals accordingly | |
344 | * | |
345 | * @param bp | |
346 | * | |
347 | * @return int | |
348 | */ | |
349 | int bnx2x_enable_msi(struct bnx2x *bp); | |
350 | ||
d6214d7a DK |
351 | /** |
352 | * NAPI callback | |
353 | * | |
354 | * @param napi | |
355 | * @param budget | |
356 | * | |
357 | * @return int | |
358 | */ | |
359 | int bnx2x_poll(struct napi_struct *napi, int budget); | |
f85582f8 DK |
360 | |
361 | /** | |
362 | * Allocate/release memories outsize main driver structure | |
363 | * | |
364 | * @param bp | |
365 | * | |
366 | * @return int | |
367 | */ | |
368 | int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); | |
369 | void bnx2x_free_mem_bp(struct bnx2x *bp); | |
370 | ||
371 | /** | |
372 | * Change mtu netdev callback | |
373 | * | |
374 | * @param dev | |
375 | * @param new_mtu | |
376 | * | |
377 | * @return int | |
378 | */ | |
379 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
380 | ||
381 | /** | |
382 | * tx timeout netdev callback | |
383 | * | |
384 | * @param dev | |
385 | * @param new_mtu | |
386 | * | |
387 | * @return int | |
388 | */ | |
389 | void bnx2x_tx_timeout(struct net_device *dev); | |
390 | ||
391 | #ifdef BCM_VLAN | |
392 | /** | |
393 | * vlan rx register netdev callback | |
394 | * | |
395 | * @param dev | |
396 | * @param new_mtu | |
397 | * | |
398 | * @return int | |
399 | */ | |
400 | void bnx2x_vlan_rx_register(struct net_device *dev, | |
401 | struct vlan_group *vlgrp); | |
402 | ||
403 | #endif | |
404 | ||
9f6c9258 DK |
405 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
406 | { | |
9f6c9258 | 407 | barrier(); /* status block is written to by the chip */ |
523224a3 | 408 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
409 | } |
410 | ||
411 | static inline void bnx2x_update_rx_prod(struct bnx2x *bp, | |
412 | struct bnx2x_fastpath *fp, | |
413 | u16 bd_prod, u16 rx_comp_prod, | |
414 | u16 rx_sge_prod) | |
415 | { | |
416 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
417 | int i; | |
418 | ||
419 | /* Update producers */ | |
420 | rx_prods.bd_prod = bd_prod; | |
421 | rx_prods.cqe_prod = rx_comp_prod; | |
422 | rx_prods.sge_prod = rx_sge_prod; | |
423 | ||
424 | /* | |
425 | * Make sure that the BD and SGE data is updated before updating the | |
426 | * producers since FW might read the BD/SGE right after the producer | |
427 | * is updated. | |
428 | * This is only applicable for weak-ordered memory model archs such | |
429 | * as IA-64. The following barrier is also mandatory since FW will | |
430 | * assumes BDs must have buffers. | |
431 | */ | |
432 | wmb(); | |
433 | ||
434 | for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++) | |
523224a3 DK |
435 | REG_WR(bp, |
436 | BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4, | |
9f6c9258 DK |
437 | ((u32 *)&rx_prods)[i]); |
438 | ||
439 | mmiowb(); /* keep prod updates ordered */ | |
440 | ||
441 | DP(NETIF_MSG_RX_STATUS, | |
442 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
443 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
444 | } | |
445 | ||
f2e0899f DK |
446 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
447 | u8 segment, u16 index, u8 op, | |
448 | u8 update, u32 igu_addr) | |
449 | { | |
450 | struct igu_regular cmd_data = {0}; | |
451 | ||
452 | cmd_data.sb_id_and_flags = | |
453 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
454 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
455 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
456 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
457 | ||
458 | DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n", | |
459 | cmd_data.sb_id_and_flags, igu_addr); | |
460 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
461 | ||
462 | /* Make sure that ACK is written */ | |
463 | mmiowb(); | |
464 | barrier(); | |
465 | } | |
466 | ||
467 | static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, | |
468 | u8 idu_sb_id, bool is_Pf) | |
469 | { | |
470 | u32 data, ctl, cnt = 100; | |
471 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
472 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
473 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
474 | u32 sb_bit = 1 << (idu_sb_id%32); | |
475 | u32 func_encode = BP_FUNC(bp) | | |
476 | ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT); | |
477 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; | |
478 | ||
479 | /* Not supported in BC mode */ | |
480 | if (CHIP_INT_MODE_IS_BC(bp)) | |
481 | return; | |
482 | ||
483 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
484 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
485 | IGU_REGULAR_CLEANUP_SET | | |
486 | IGU_REGULAR_BCLEANUP; | |
487 | ||
488 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
489 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
490 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
9f6c9258 | 491 | |
f2e0899f DK |
492 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", |
493 | data, igu_addr_data); | |
494 | REG_WR(bp, igu_addr_data, data); | |
495 | mmiowb(); | |
496 | barrier(); | |
497 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
498 | ctl, igu_addr_ctl); | |
499 | REG_WR(bp, igu_addr_ctl, ctl); | |
500 | mmiowb(); | |
501 | barrier(); | |
9f6c9258 | 502 | |
f2e0899f DK |
503 | /* wait for clean up to finish */ |
504 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
505 | msleep(20); | |
506 | ||
507 | ||
508 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { | |
509 | DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: " | |
510 | "idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
511 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
512 | } | |
513 | } | |
514 | ||
515 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, | |
516 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
517 | { |
518 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
519 | COMMAND_REG_INT_ACK); | |
520 | struct igu_ack_register igu_ack; | |
521 | ||
522 | igu_ack.status_block_index = index; | |
523 | igu_ack.sb_id_and_flags = | |
524 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
525 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
526 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
527 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
528 | ||
529 | DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", | |
530 | (*(u32 *)&igu_ack), hc_addr); | |
531 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); | |
532 | ||
533 | /* Make sure that ACK is written */ | |
534 | mmiowb(); | |
535 | barrier(); | |
536 | } | |
f2e0899f DK |
537 | |
538 | static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
539 | u16 index, u8 op, u8 update) | |
540 | { | |
541 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
542 | ||
543 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
544 | igu_addr); | |
545 | } | |
546 | ||
547 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, | |
548 | u16 index, u8 op, u8 update) | |
549 | { | |
550 | if (bp->common.int_block == INT_BLOCK_HC) | |
551 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
552 | else { | |
553 | u8 segment; | |
554 | ||
555 | if (CHIP_INT_MODE_IS_BC(bp)) | |
556 | segment = storm; | |
557 | else if (igu_sb_id != bp->igu_dsb_id) | |
558 | segment = IGU_SEG_ACCESS_DEF; | |
559 | else if (storm == ATTENTION_ID) | |
560 | segment = IGU_SEG_ACCESS_ATTN; | |
561 | else | |
562 | segment = IGU_SEG_ACCESS_DEF; | |
563 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
564 | } | |
565 | } | |
566 | ||
567 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
568 | { |
569 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
570 | COMMAND_REG_SIMD_MASK); | |
571 | u32 result = REG_RD(bp, hc_addr); | |
572 | ||
573 | DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n", | |
574 | result, hc_addr); | |
575 | ||
f2e0899f | 576 | barrier(); |
9f6c9258 DK |
577 | return result; |
578 | } | |
579 | ||
f2e0899f DK |
580 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
581 | { | |
582 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
583 | u32 result = REG_RD(bp, igu_addr); | |
584 | ||
585 | DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n", | |
586 | result, igu_addr); | |
587 | ||
588 | barrier(); | |
589 | return result; | |
590 | } | |
591 | ||
592 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
593 | { | |
594 | barrier(); | |
595 | if (bp->common.int_block == INT_BLOCK_HC) | |
596 | return bnx2x_hc_ack_int(bp); | |
597 | else | |
598 | return bnx2x_igu_ack_int(bp); | |
599 | } | |
600 | ||
9f6c9258 DK |
601 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp) |
602 | { | |
603 | /* Tell compiler that consumer and producer can change */ | |
604 | barrier(); | |
807540ba | 605 | return fp->tx_pkt_prod != fp->tx_pkt_cons; |
9f6c9258 DK |
606 | } |
607 | ||
608 | static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp) | |
609 | { | |
610 | s16 used; | |
611 | u16 prod; | |
612 | u16 cons; | |
613 | ||
614 | prod = fp->tx_bd_prod; | |
615 | cons = fp->tx_bd_cons; | |
616 | ||
617 | /* NUM_TX_RINGS = number of "next-page" entries | |
618 | It will be used as a threshold */ | |
619 | used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; | |
620 | ||
621 | #ifdef BNX2X_STOP_ON_ERROR | |
622 | WARN_ON(used < 0); | |
623 | WARN_ON(used > fp->bp->tx_ring_size); | |
624 | WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL); | |
625 | #endif | |
626 | ||
627 | return (s16)(fp->bp->tx_ring_size) - used; | |
628 | } | |
629 | ||
630 | static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
631 | { | |
632 | u16 hw_cons; | |
633 | ||
634 | /* Tell compiler that status block fields can change */ | |
635 | barrier(); | |
636 | hw_cons = le16_to_cpu(*fp->tx_cons_sb); | |
637 | return hw_cons != fp->tx_pkt_cons; | |
638 | } | |
639 | ||
523224a3 DK |
640 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
641 | { | |
642 | u16 rx_cons_sb; | |
643 | ||
644 | /* Tell compiler that status block fields can change */ | |
645 | barrier(); | |
646 | rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); | |
647 | if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) | |
648 | rx_cons_sb++; | |
649 | return (fp->rx_comp_cons != rx_cons_sb); | |
650 | } | |
f85582f8 | 651 | |
f2e0899f DK |
652 | /** |
653 | * disables tx from stack point of view | |
654 | * | |
655 | * @param bp | |
656 | */ | |
657 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
658 | { | |
659 | netif_tx_disable(bp->dev); | |
660 | netif_carrier_off(bp->dev); | |
661 | } | |
662 | ||
9f6c9258 DK |
663 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
664 | struct bnx2x_fastpath *fp, u16 index) | |
665 | { | |
666 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
667 | struct page *page = sw_buf->page; | |
668 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
669 | ||
670 | /* Skip "next page" elements */ | |
671 | if (!page) | |
672 | return; | |
673 | ||
674 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
4bca60f4 | 675 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); |
9f6c9258 DK |
676 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
677 | ||
678 | sw_buf->page = NULL; | |
679 | sge->addr_hi = 0; | |
680 | sge->addr_lo = 0; | |
681 | } | |
682 | ||
d6214d7a DK |
683 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) |
684 | { | |
685 | int i; | |
523224a3 | 686 | |
d6214d7a DK |
687 | /* Add NAPI objects */ |
688 | for_each_queue(bp, i) | |
689 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), | |
690 | bnx2x_poll, BNX2X_NAPI_WEIGHT); | |
691 | } | |
523224a3 | 692 | |
d6214d7a DK |
693 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
694 | { | |
695 | int i; | |
696 | ||
697 | for_each_queue(bp, i) | |
698 | netif_napi_del(&bnx2x_fp(bp, i, napi)); | |
699 | } | |
523224a3 | 700 | |
d6214d7a DK |
701 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
702 | { | |
703 | if (bp->flags & USING_MSIX_FLAG) { | |
704 | pci_disable_msix(bp->pdev); | |
705 | bp->flags &= ~USING_MSIX_FLAG; | |
706 | } else if (bp->flags & USING_MSI_FLAG) { | |
707 | pci_disable_msi(bp->pdev); | |
708 | bp->flags &= ~USING_MSI_FLAG; | |
709 | } | |
710 | } | |
711 | ||
712 | static inline int bnx2x_calc_num_queues(struct bnx2x *bp) | |
713 | { | |
714 | return num_queues ? | |
715 | min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : | |
716 | min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp)); | |
717 | } | |
523224a3 DK |
718 | |
719 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) | |
9f6c9258 | 720 | { |
523224a3 | 721 | int i, j; |
9f6c9258 | 722 | |
523224a3 DK |
723 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
724 | int idx = RX_SGE_CNT * i - 1; | |
725 | ||
726 | for (j = 0; j < 2; j++) { | |
727 | SGE_MASK_CLEAR_BIT(fp, idx); | |
728 | idx--; | |
729 | } | |
730 | } | |
731 | } | |
732 | ||
733 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
734 | { | |
735 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
736 | memset(fp->sge_mask, 0xff, | |
737 | (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64)); | |
738 | ||
739 | /* Clear the two last indices in the page to 1: | |
740 | these are the indices that correspond to the "next" element, | |
741 | hence will never be indicated and should be removed from | |
742 | the calculations. */ | |
743 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
744 | } |
745 | ||
746 | static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp, | |
747 | struct bnx2x_fastpath *fp, u16 index) | |
748 | { | |
749 | struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT); | |
750 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
751 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
752 | dma_addr_t mapping; | |
753 | ||
754 | if (unlikely(page == NULL)) | |
755 | return -ENOMEM; | |
756 | ||
757 | mapping = dma_map_page(&bp->pdev->dev, page, 0, | |
758 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); | |
759 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
760 | __free_pages(page, PAGES_PER_SGE_SHIFT); | |
761 | return -ENOMEM; | |
762 | } | |
763 | ||
764 | sw_buf->page = page; | |
765 | dma_unmap_addr_set(sw_buf, mapping, mapping); | |
766 | ||
767 | sge->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
768 | sge->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
769 | ||
770 | return 0; | |
771 | } | |
f85582f8 | 772 | |
9f6c9258 DK |
773 | static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp, |
774 | struct bnx2x_fastpath *fp, u16 index) | |
775 | { | |
776 | struct sk_buff *skb; | |
777 | struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index]; | |
778 | struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; | |
779 | dma_addr_t mapping; | |
780 | ||
781 | skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); | |
782 | if (unlikely(skb == NULL)) | |
783 | return -ENOMEM; | |
784 | ||
785 | mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size, | |
786 | DMA_FROM_DEVICE); | |
787 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
788 | dev_kfree_skb(skb); | |
789 | return -ENOMEM; | |
790 | } | |
791 | ||
792 | rx_buf->skb = skb; | |
793 | dma_unmap_addr_set(rx_buf, mapping, mapping); | |
794 | ||
795 | rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
796 | rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
801 | /* note that we are not allocating a new skb, | |
802 | * we are just moving one from cons to prod | |
803 | * we are not creating a new mapping, | |
804 | * so there is no need to check for dma_mapping_error(). | |
805 | */ | |
806 | static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp, | |
749a8503 | 807 | u16 cons, u16 prod) |
9f6c9258 DK |
808 | { |
809 | struct bnx2x *bp = fp->bp; | |
810 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; | |
811 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
812 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
813 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
814 | ||
815 | dma_sync_single_for_device(&bp->pdev->dev, | |
816 | dma_unmap_addr(cons_rx_buf, mapping), | |
817 | RX_COPY_THRESH, DMA_FROM_DEVICE); | |
818 | ||
819 | prod_rx_buf->skb = cons_rx_buf->skb; | |
820 | dma_unmap_addr_set(prod_rx_buf, mapping, | |
821 | dma_unmap_addr(cons_rx_buf, mapping)); | |
822 | *prod_bd = *cons_bd; | |
823 | } | |
f85582f8 | 824 | |
523224a3 DK |
825 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
826 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 827 | { |
523224a3 | 828 | int i; |
9f6c9258 | 829 | |
523224a3 DK |
830 | for (i = 0; i < last; i++) |
831 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
832 | } |
833 | ||
9f6c9258 DK |
834 | static inline void bnx2x_free_tpa_pool(struct bnx2x *bp, |
835 | struct bnx2x_fastpath *fp, int last) | |
836 | { | |
837 | int i; | |
838 | ||
839 | for (i = 0; i < last; i++) { | |
840 | struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]); | |
841 | struct sk_buff *skb = rx_buf->skb; | |
842 | ||
843 | if (skb == NULL) { | |
844 | DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i); | |
845 | continue; | |
846 | } | |
847 | ||
848 | if (fp->tpa_state[i] == BNX2X_TPA_START) | |
849 | dma_unmap_single(&bp->pdev->dev, | |
850 | dma_unmap_addr(rx_buf, mapping), | |
851 | bp->rx_buf_size, DMA_FROM_DEVICE); | |
852 | ||
853 | dev_kfree_skb(skb); | |
854 | rx_buf->skb = NULL; | |
855 | } | |
856 | } | |
857 | ||
858 | ||
523224a3 | 859 | static inline void bnx2x_init_tx_rings(struct bnx2x *bp) |
9f6c9258 DK |
860 | { |
861 | int i, j; | |
862 | ||
863 | for_each_queue(bp, j) { | |
864 | struct bnx2x_fastpath *fp = &bp->fp[j]; | |
865 | ||
866 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
867 | struct eth_tx_next_bd *tx_next_bd = | |
868 | &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
869 | ||
870 | tx_next_bd->addr_hi = | |
871 | cpu_to_le32(U64_HI(fp->tx_desc_mapping + | |
872 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
873 | tx_next_bd->addr_lo = | |
874 | cpu_to_le32(U64_LO(fp->tx_desc_mapping + | |
875 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
876 | } | |
877 | ||
523224a3 | 878 | SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
9f6c9258 DK |
879 | fp->tx_db.data.zero_fill1 = 0; |
880 | fp->tx_db.data.prod = 0; | |
881 | ||
882 | fp->tx_pkt_prod = 0; | |
883 | fp->tx_pkt_cons = 0; | |
884 | fp->tx_bd_prod = 0; | |
885 | fp->tx_bd_cons = 0; | |
9f6c9258 DK |
886 | fp->tx_pkt = 0; |
887 | } | |
888 | } | |
f85582f8 | 889 | |
523224a3 | 890 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 891 | { |
523224a3 | 892 | int i; |
9f6c9258 | 893 | |
523224a3 DK |
894 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
895 | struct eth_rx_bd *rx_bd; | |
896 | ||
897 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
898 | rx_bd->addr_hi = | |
899 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
900 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
901 | rx_bd->addr_lo = | |
902 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
903 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
904 | } | |
9f6c9258 DK |
905 | } |
906 | ||
523224a3 DK |
907 | static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp) |
908 | { | |
909 | int i; | |
910 | ||
911 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { | |
912 | struct eth_rx_sge *sge; | |
913 | ||
914 | sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2]; | |
915 | sge->addr_hi = | |
916 | cpu_to_le32(U64_HI(fp->rx_sge_mapping + | |
917 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
918 | ||
919 | sge->addr_lo = | |
920 | cpu_to_le32(U64_LO(fp->rx_sge_mapping + | |
921 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
922 | } | |
923 | } | |
924 | ||
925 | static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp) | |
926 | { | |
927 | int i; | |
928 | for (i = 1; i <= NUM_RCQ_RINGS; i++) { | |
929 | struct eth_rx_cqe_next_page *nextpg; | |
930 | ||
931 | nextpg = (struct eth_rx_cqe_next_page *) | |
932 | &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1]; | |
933 | nextpg->addr_hi = | |
934 | cpu_to_le32(U64_HI(fp->rx_comp_mapping + | |
935 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
936 | nextpg->addr_lo = | |
937 | cpu_to_le32(U64_LO(fp->rx_comp_mapping + | |
938 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
939 | } | |
940 | } | |
941 | ||
942 | ||
943 | ||
944 | static inline void __storm_memset_struct(struct bnx2x *bp, | |
945 | u32 addr, size_t size, u32 *data) | |
946 | { | |
947 | int i; | |
948 | for (i = 0; i < size/4; i++) | |
949 | REG_WR(bp, addr + (i * 4), data[i]); | |
950 | } | |
951 | ||
952 | static inline void storm_memset_mac_filters(struct bnx2x *bp, | |
953 | struct tstorm_eth_mac_filter_config *mac_filters, | |
954 | u16 abs_fid) | |
955 | { | |
956 | size_t size = sizeof(struct tstorm_eth_mac_filter_config); | |
957 | ||
958 | u32 addr = BAR_TSTRORM_INTMEM + | |
959 | TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid); | |
960 | ||
961 | __storm_memset_struct(bp, addr, size, (u32 *)mac_filters); | |
962 | } | |
963 | ||
964 | static inline void storm_memset_cmng(struct bnx2x *bp, | |
965 | struct cmng_struct_per_port *cmng, | |
966 | u8 port) | |
967 | { | |
968 | size_t size = sizeof(struct cmng_struct_per_port); | |
969 | ||
970 | u32 addr = BAR_XSTRORM_INTMEM + | |
971 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
972 | ||
973 | __storm_memset_struct(bp, addr, size, (u32 *)cmng); | |
974 | } | |
f85582f8 | 975 | |
9f6c9258 DK |
976 | /* HW Lock for shared dual port PHYs */ |
977 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); | |
978 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
979 | ||
9f6c9258 | 980 | #endif /* BNX2X_CMN_H */ |