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b6016b76 MC |
1 | /* bnx2.c: Broadcom NX2 network driver. |
2 | * | |
3 | * Copyright (c) 2004, 2005 Broadcom Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Written by: Michael Chan (mchan@broadcom.com) | |
10 | */ | |
11 | ||
12 | #include "bnx2.h" | |
13 | #include "bnx2_fw.h" | |
14 | ||
15 | #define DRV_MODULE_NAME "bnx2" | |
16 | #define PFX DRV_MODULE_NAME ": " | |
17 | #define DRV_MODULE_VERSION "1.2.19" | |
18 | #define DRV_MODULE_RELDATE "May 23, 2005" | |
19 | ||
20 | #define RUN_AT(x) (jiffies + (x)) | |
21 | ||
22 | /* Time in jiffies before concluding the transmitter is hung. */ | |
23 | #define TX_TIMEOUT (5*HZ) | |
24 | ||
25 | static char version[] __devinitdata = | |
26 | "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | |
27 | ||
28 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); | |
29 | MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver"); | |
30 | MODULE_LICENSE("GPL"); | |
31 | MODULE_VERSION(DRV_MODULE_VERSION); | |
32 | ||
33 | static int disable_msi = 0; | |
34 | ||
35 | module_param(disable_msi, int, 0); | |
36 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
37 | ||
38 | typedef enum { | |
39 | BCM5706 = 0, | |
40 | NC370T, | |
41 | NC370I, | |
42 | BCM5706S, | |
43 | NC370F, | |
44 | } board_t; | |
45 | ||
46 | /* indexed by board_t, above */ | |
47 | static struct { | |
48 | char *name; | |
49 | } board_info[] __devinitdata = { | |
50 | { "Broadcom NetXtreme II BCM5706 1000Base-T" }, | |
51 | { "HP NC370T Multifunction Gigabit Server Adapter" }, | |
52 | { "HP NC370i Multifunction Gigabit Server Adapter" }, | |
53 | { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, | |
54 | { "HP NC370F Multifunction Gigabit Server Adapter" }, | |
b6016b76 MC |
55 | }; |
56 | ||
57 | static struct pci_device_id bnx2_pci_tbl[] = { | |
58 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
59 | PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, | |
60 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
61 | PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, | |
62 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
63 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, | |
64 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, | |
65 | PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, | |
66 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, | |
67 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, | |
68 | { 0, } | |
69 | }; | |
70 | ||
71 | static struct flash_spec flash_table[] = | |
72 | { | |
73 | /* Slow EEPROM */ | |
74 | {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400, | |
75 | 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, | |
76 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, | |
77 | "EEPROM - slow"}, | |
78 | /* Fast EEPROM */ | |
79 | {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400, | |
80 | 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, | |
81 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, | |
82 | "EEPROM - fast"}, | |
83 | /* ATMEL AT45DB011B (buffered flash) */ | |
84 | {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400, | |
85 | 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, | |
86 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, | |
87 | "Buffered flash"}, | |
88 | /* Saifun SA25F005 (non-buffered flash) */ | |
89 | /* strap, cfg1, & write1 need updates */ | |
90 | {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406, | |
91 | 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, | |
92 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, | |
93 | "Non-buffered flash (64kB)"}, | |
94 | /* Saifun SA25F010 (non-buffered flash) */ | |
95 | /* strap, cfg1, & write1 need updates */ | |
96 | {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406, | |
97 | 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, | |
98 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, | |
99 | "Non-buffered flash (128kB)"}, | |
100 | /* Saifun SA25F020 (non-buffered flash) */ | |
101 | /* strap, cfg1, & write1 need updates */ | |
102 | {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406, | |
103 | 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, | |
104 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, | |
105 | "Non-buffered flash (256kB)"}, | |
106 | }; | |
107 | ||
108 | MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); | |
109 | ||
110 | static u32 | |
111 | bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) | |
112 | { | |
113 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); | |
114 | return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW)); | |
115 | } | |
116 | ||
117 | static void | |
118 | bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) | |
119 | { | |
120 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); | |
121 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); | |
122 | } | |
123 | ||
124 | static void | |
125 | bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) | |
126 | { | |
127 | offset += cid_addr; | |
128 | REG_WR(bp, BNX2_CTX_DATA_ADR, offset); | |
129 | REG_WR(bp, BNX2_CTX_DATA, val); | |
130 | } | |
131 | ||
132 | static int | |
133 | bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) | |
134 | { | |
135 | u32 val1; | |
136 | int i, ret; | |
137 | ||
138 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | |
139 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
140 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
141 | ||
142 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
143 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
144 | ||
145 | udelay(40); | |
146 | } | |
147 | ||
148 | val1 = (bp->phy_addr << 21) | (reg << 16) | | |
149 | BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | | |
150 | BNX2_EMAC_MDIO_COMM_START_BUSY; | |
151 | REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); | |
152 | ||
153 | for (i = 0; i < 50; i++) { | |
154 | udelay(10); | |
155 | ||
156 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
157 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { | |
158 | udelay(5); | |
159 | ||
160 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
161 | val1 &= BNX2_EMAC_MDIO_COMM_DATA; | |
162 | ||
163 | break; | |
164 | } | |
165 | } | |
166 | ||
167 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { | |
168 | *val = 0x0; | |
169 | ret = -EBUSY; | |
170 | } | |
171 | else { | |
172 | *val = val1; | |
173 | ret = 0; | |
174 | } | |
175 | ||
176 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | |
177 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
178 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
179 | ||
180 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
181 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
182 | ||
183 | udelay(40); | |
184 | } | |
185 | ||
186 | return ret; | |
187 | } | |
188 | ||
189 | static int | |
190 | bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) | |
191 | { | |
192 | u32 val1; | |
193 | int i, ret; | |
194 | ||
195 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | |
196 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
197 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
198 | ||
199 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
200 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
201 | ||
202 | udelay(40); | |
203 | } | |
204 | ||
205 | val1 = (bp->phy_addr << 21) | (reg << 16) | val | | |
206 | BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | | |
207 | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; | |
208 | REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); | |
209 | ||
210 | for (i = 0; i < 50; i++) { | |
211 | udelay(10); | |
212 | ||
213 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | |
214 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { | |
215 | udelay(5); | |
216 | break; | |
217 | } | |
218 | } | |
219 | ||
220 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) | |
221 | ret = -EBUSY; | |
222 | else | |
223 | ret = 0; | |
224 | ||
225 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | |
226 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
227 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | |
228 | ||
229 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | |
230 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | |
231 | ||
232 | udelay(40); | |
233 | } | |
234 | ||
235 | return ret; | |
236 | } | |
237 | ||
238 | static void | |
239 | bnx2_disable_int(struct bnx2 *bp) | |
240 | { | |
241 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
242 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
243 | REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); | |
244 | } | |
245 | ||
246 | static void | |
247 | bnx2_enable_int(struct bnx2 *bp) | |
248 | { | |
249 | u32 val; | |
250 | ||
251 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
252 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx); | |
253 | ||
254 | val = REG_RD(bp, BNX2_HC_COMMAND); | |
255 | REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW); | |
256 | } | |
257 | ||
258 | static void | |
259 | bnx2_disable_int_sync(struct bnx2 *bp) | |
260 | { | |
261 | atomic_inc(&bp->intr_sem); | |
262 | bnx2_disable_int(bp); | |
263 | synchronize_irq(bp->pdev->irq); | |
264 | } | |
265 | ||
266 | static void | |
267 | bnx2_netif_stop(struct bnx2 *bp) | |
268 | { | |
269 | bnx2_disable_int_sync(bp); | |
270 | if (netif_running(bp->dev)) { | |
271 | netif_poll_disable(bp->dev); | |
272 | netif_tx_disable(bp->dev); | |
273 | bp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
274 | } | |
275 | } | |
276 | ||
277 | static void | |
278 | bnx2_netif_start(struct bnx2 *bp) | |
279 | { | |
280 | if (atomic_dec_and_test(&bp->intr_sem)) { | |
281 | if (netif_running(bp->dev)) { | |
282 | netif_wake_queue(bp->dev); | |
283 | netif_poll_enable(bp->dev); | |
284 | bnx2_enable_int(bp); | |
285 | } | |
286 | } | |
287 | } | |
288 | ||
289 | static void | |
290 | bnx2_free_mem(struct bnx2 *bp) | |
291 | { | |
292 | if (bp->stats_blk) { | |
293 | pci_free_consistent(bp->pdev, sizeof(struct statistics_block), | |
294 | bp->stats_blk, bp->stats_blk_mapping); | |
295 | bp->stats_blk = NULL; | |
296 | } | |
297 | if (bp->status_blk) { | |
298 | pci_free_consistent(bp->pdev, sizeof(struct status_block), | |
299 | bp->status_blk, bp->status_blk_mapping); | |
300 | bp->status_blk = NULL; | |
301 | } | |
302 | if (bp->tx_desc_ring) { | |
303 | pci_free_consistent(bp->pdev, | |
304 | sizeof(struct tx_bd) * TX_DESC_CNT, | |
305 | bp->tx_desc_ring, bp->tx_desc_mapping); | |
306 | bp->tx_desc_ring = NULL; | |
307 | } | |
308 | if (bp->tx_buf_ring) { | |
309 | kfree(bp->tx_buf_ring); | |
310 | bp->tx_buf_ring = NULL; | |
311 | } | |
312 | if (bp->rx_desc_ring) { | |
313 | pci_free_consistent(bp->pdev, | |
314 | sizeof(struct rx_bd) * RX_DESC_CNT, | |
315 | bp->rx_desc_ring, bp->rx_desc_mapping); | |
316 | bp->rx_desc_ring = NULL; | |
317 | } | |
318 | if (bp->rx_buf_ring) { | |
319 | kfree(bp->rx_buf_ring); | |
320 | bp->rx_buf_ring = NULL; | |
321 | } | |
322 | } | |
323 | ||
324 | static int | |
325 | bnx2_alloc_mem(struct bnx2 *bp) | |
326 | { | |
327 | bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT, | |
328 | GFP_KERNEL); | |
329 | if (bp->tx_buf_ring == NULL) | |
330 | return -ENOMEM; | |
331 | ||
332 | memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT); | |
333 | bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, | |
334 | sizeof(struct tx_bd) * | |
335 | TX_DESC_CNT, | |
336 | &bp->tx_desc_mapping); | |
337 | if (bp->tx_desc_ring == NULL) | |
338 | goto alloc_mem_err; | |
339 | ||
340 | bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT, | |
341 | GFP_KERNEL); | |
342 | if (bp->rx_buf_ring == NULL) | |
343 | goto alloc_mem_err; | |
344 | ||
345 | memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT); | |
346 | bp->rx_desc_ring = pci_alloc_consistent(bp->pdev, | |
347 | sizeof(struct rx_bd) * | |
348 | RX_DESC_CNT, | |
349 | &bp->rx_desc_mapping); | |
350 | if (bp->rx_desc_ring == NULL) | |
351 | goto alloc_mem_err; | |
352 | ||
353 | bp->status_blk = pci_alloc_consistent(bp->pdev, | |
354 | sizeof(struct status_block), | |
355 | &bp->status_blk_mapping); | |
356 | if (bp->status_blk == NULL) | |
357 | goto alloc_mem_err; | |
358 | ||
359 | memset(bp->status_blk, 0, sizeof(struct status_block)); | |
360 | ||
361 | bp->stats_blk = pci_alloc_consistent(bp->pdev, | |
362 | sizeof(struct statistics_block), | |
363 | &bp->stats_blk_mapping); | |
364 | if (bp->stats_blk == NULL) | |
365 | goto alloc_mem_err; | |
366 | ||
367 | memset(bp->stats_blk, 0, sizeof(struct statistics_block)); | |
368 | ||
369 | return 0; | |
370 | ||
371 | alloc_mem_err: | |
372 | bnx2_free_mem(bp); | |
373 | return -ENOMEM; | |
374 | } | |
375 | ||
376 | static void | |
377 | bnx2_report_link(struct bnx2 *bp) | |
378 | { | |
379 | if (bp->link_up) { | |
380 | netif_carrier_on(bp->dev); | |
381 | printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name); | |
382 | ||
383 | printk("%d Mbps ", bp->line_speed); | |
384 | ||
385 | if (bp->duplex == DUPLEX_FULL) | |
386 | printk("full duplex"); | |
387 | else | |
388 | printk("half duplex"); | |
389 | ||
390 | if (bp->flow_ctrl) { | |
391 | if (bp->flow_ctrl & FLOW_CTRL_RX) { | |
392 | printk(", receive "); | |
393 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
394 | printk("& transmit "); | |
395 | } | |
396 | else { | |
397 | printk(", transmit "); | |
398 | } | |
399 | printk("flow control ON"); | |
400 | } | |
401 | printk("\n"); | |
402 | } | |
403 | else { | |
404 | netif_carrier_off(bp->dev); | |
405 | printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name); | |
406 | } | |
407 | } | |
408 | ||
409 | static void | |
410 | bnx2_resolve_flow_ctrl(struct bnx2 *bp) | |
411 | { | |
412 | u32 local_adv, remote_adv; | |
413 | ||
414 | bp->flow_ctrl = 0; | |
415 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != | |
416 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { | |
417 | ||
418 | if (bp->duplex == DUPLEX_FULL) { | |
419 | bp->flow_ctrl = bp->req_flow_ctrl; | |
420 | } | |
421 | return; | |
422 | } | |
423 | ||
424 | if (bp->duplex != DUPLEX_FULL) { | |
425 | return; | |
426 | } | |
427 | ||
428 | bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); | |
429 | bnx2_read_phy(bp, MII_LPA, &remote_adv); | |
430 | ||
431 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
432 | u32 new_local_adv = 0; | |
433 | u32 new_remote_adv = 0; | |
434 | ||
435 | if (local_adv & ADVERTISE_1000XPAUSE) | |
436 | new_local_adv |= ADVERTISE_PAUSE_CAP; | |
437 | if (local_adv & ADVERTISE_1000XPSE_ASYM) | |
438 | new_local_adv |= ADVERTISE_PAUSE_ASYM; | |
439 | if (remote_adv & ADVERTISE_1000XPAUSE) | |
440 | new_remote_adv |= ADVERTISE_PAUSE_CAP; | |
441 | if (remote_adv & ADVERTISE_1000XPSE_ASYM) | |
442 | new_remote_adv |= ADVERTISE_PAUSE_ASYM; | |
443 | ||
444 | local_adv = new_local_adv; | |
445 | remote_adv = new_remote_adv; | |
446 | } | |
447 | ||
448 | /* See Table 28B-3 of 802.3ab-1999 spec. */ | |
449 | if (local_adv & ADVERTISE_PAUSE_CAP) { | |
450 | if(local_adv & ADVERTISE_PAUSE_ASYM) { | |
451 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
452 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
453 | } | |
454 | else if (remote_adv & ADVERTISE_PAUSE_ASYM) { | |
455 | bp->flow_ctrl = FLOW_CTRL_RX; | |
456 | } | |
457 | } | |
458 | else { | |
459 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
460 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
461 | } | |
462 | } | |
463 | } | |
464 | else if (local_adv & ADVERTISE_PAUSE_ASYM) { | |
465 | if ((remote_adv & ADVERTISE_PAUSE_CAP) && | |
466 | (remote_adv & ADVERTISE_PAUSE_ASYM)) { | |
467 | ||
468 | bp->flow_ctrl = FLOW_CTRL_TX; | |
469 | } | |
470 | } | |
471 | } | |
472 | ||
473 | static int | |
474 | bnx2_serdes_linkup(struct bnx2 *bp) | |
475 | { | |
476 | u32 bmcr, local_adv, remote_adv, common; | |
477 | ||
478 | bp->link_up = 1; | |
479 | bp->line_speed = SPEED_1000; | |
480 | ||
481 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
482 | if (bmcr & BMCR_FULLDPLX) { | |
483 | bp->duplex = DUPLEX_FULL; | |
484 | } | |
485 | else { | |
486 | bp->duplex = DUPLEX_HALF; | |
487 | } | |
488 | ||
489 | if (!(bmcr & BMCR_ANENABLE)) { | |
490 | return 0; | |
491 | } | |
492 | ||
493 | bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); | |
494 | bnx2_read_phy(bp, MII_LPA, &remote_adv); | |
495 | ||
496 | common = local_adv & remote_adv; | |
497 | if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { | |
498 | ||
499 | if (common & ADVERTISE_1000XFULL) { | |
500 | bp->duplex = DUPLEX_FULL; | |
501 | } | |
502 | else { | |
503 | bp->duplex = DUPLEX_HALF; | |
504 | } | |
505 | } | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static int | |
511 | bnx2_copper_linkup(struct bnx2 *bp) | |
512 | { | |
513 | u32 bmcr; | |
514 | ||
515 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
516 | if (bmcr & BMCR_ANENABLE) { | |
517 | u32 local_adv, remote_adv, common; | |
518 | ||
519 | bnx2_read_phy(bp, MII_CTRL1000, &local_adv); | |
520 | bnx2_read_phy(bp, MII_STAT1000, &remote_adv); | |
521 | ||
522 | common = local_adv & (remote_adv >> 2); | |
523 | if (common & ADVERTISE_1000FULL) { | |
524 | bp->line_speed = SPEED_1000; | |
525 | bp->duplex = DUPLEX_FULL; | |
526 | } | |
527 | else if (common & ADVERTISE_1000HALF) { | |
528 | bp->line_speed = SPEED_1000; | |
529 | bp->duplex = DUPLEX_HALF; | |
530 | } | |
531 | else { | |
532 | bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); | |
533 | bnx2_read_phy(bp, MII_LPA, &remote_adv); | |
534 | ||
535 | common = local_adv & remote_adv; | |
536 | if (common & ADVERTISE_100FULL) { | |
537 | bp->line_speed = SPEED_100; | |
538 | bp->duplex = DUPLEX_FULL; | |
539 | } | |
540 | else if (common & ADVERTISE_100HALF) { | |
541 | bp->line_speed = SPEED_100; | |
542 | bp->duplex = DUPLEX_HALF; | |
543 | } | |
544 | else if (common & ADVERTISE_10FULL) { | |
545 | bp->line_speed = SPEED_10; | |
546 | bp->duplex = DUPLEX_FULL; | |
547 | } | |
548 | else if (common & ADVERTISE_10HALF) { | |
549 | bp->line_speed = SPEED_10; | |
550 | bp->duplex = DUPLEX_HALF; | |
551 | } | |
552 | else { | |
553 | bp->line_speed = 0; | |
554 | bp->link_up = 0; | |
555 | } | |
556 | } | |
557 | } | |
558 | else { | |
559 | if (bmcr & BMCR_SPEED100) { | |
560 | bp->line_speed = SPEED_100; | |
561 | } | |
562 | else { | |
563 | bp->line_speed = SPEED_10; | |
564 | } | |
565 | if (bmcr & BMCR_FULLDPLX) { | |
566 | bp->duplex = DUPLEX_FULL; | |
567 | } | |
568 | else { | |
569 | bp->duplex = DUPLEX_HALF; | |
570 | } | |
571 | } | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
576 | static int | |
577 | bnx2_set_mac_link(struct bnx2 *bp) | |
578 | { | |
579 | u32 val; | |
580 | ||
581 | REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); | |
582 | if (bp->link_up && (bp->line_speed == SPEED_1000) && | |
583 | (bp->duplex == DUPLEX_HALF)) { | |
584 | REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); | |
585 | } | |
586 | ||
587 | /* Configure the EMAC mode register. */ | |
588 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
589 | ||
590 | val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | | |
591 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK); | |
592 | ||
593 | if (bp->link_up) { | |
594 | if (bp->line_speed != SPEED_1000) | |
595 | val |= BNX2_EMAC_MODE_PORT_MII; | |
596 | else | |
597 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
598 | } | |
599 | else { | |
600 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
601 | } | |
602 | ||
603 | /* Set the MAC to operate in the appropriate duplex mode. */ | |
604 | if (bp->duplex == DUPLEX_HALF) | |
605 | val |= BNX2_EMAC_MODE_HALF_DUPLEX; | |
606 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
607 | ||
608 | /* Enable/disable rx PAUSE. */ | |
609 | bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; | |
610 | ||
611 | if (bp->flow_ctrl & FLOW_CTRL_RX) | |
612 | bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; | |
613 | REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); | |
614 | ||
615 | /* Enable/disable tx PAUSE. */ | |
616 | val = REG_RD(bp, BNX2_EMAC_TX_MODE); | |
617 | val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; | |
618 | ||
619 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
620 | val |= BNX2_EMAC_TX_MODE_FLOW_EN; | |
621 | REG_WR(bp, BNX2_EMAC_TX_MODE, val); | |
622 | ||
623 | /* Acknowledge the interrupt. */ | |
624 | REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static int | |
630 | bnx2_set_link(struct bnx2 *bp) | |
631 | { | |
632 | u32 bmsr; | |
633 | u8 link_up; | |
634 | ||
635 | if (bp->loopback == MAC_LOOPBACK) { | |
636 | bp->link_up = 1; | |
637 | return 0; | |
638 | } | |
639 | ||
640 | link_up = bp->link_up; | |
641 | ||
642 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | |
643 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | |
644 | ||
645 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | |
646 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { | |
647 | u32 val; | |
648 | ||
649 | val = REG_RD(bp, BNX2_EMAC_STATUS); | |
650 | if (val & BNX2_EMAC_STATUS_LINK) | |
651 | bmsr |= BMSR_LSTATUS; | |
652 | else | |
653 | bmsr &= ~BMSR_LSTATUS; | |
654 | } | |
655 | ||
656 | if (bmsr & BMSR_LSTATUS) { | |
657 | bp->link_up = 1; | |
658 | ||
659 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
660 | bnx2_serdes_linkup(bp); | |
661 | } | |
662 | else { | |
663 | bnx2_copper_linkup(bp); | |
664 | } | |
665 | bnx2_resolve_flow_ctrl(bp); | |
666 | } | |
667 | else { | |
668 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | |
669 | (bp->autoneg & AUTONEG_SPEED)) { | |
670 | ||
671 | u32 bmcr; | |
672 | ||
673 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
674 | if (!(bmcr & BMCR_ANENABLE)) { | |
675 | bnx2_write_phy(bp, MII_BMCR, bmcr | | |
676 | BMCR_ANENABLE); | |
677 | } | |
678 | } | |
679 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | |
680 | bp->link_up = 0; | |
681 | } | |
682 | ||
683 | if (bp->link_up != link_up) { | |
684 | bnx2_report_link(bp); | |
685 | } | |
686 | ||
687 | bnx2_set_mac_link(bp); | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | static int | |
693 | bnx2_reset_phy(struct bnx2 *bp) | |
694 | { | |
695 | int i; | |
696 | u32 reg; | |
697 | ||
698 | bnx2_write_phy(bp, MII_BMCR, BMCR_RESET); | |
699 | ||
700 | #define PHY_RESET_MAX_WAIT 100 | |
701 | for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { | |
702 | udelay(10); | |
703 | ||
704 | bnx2_read_phy(bp, MII_BMCR, ®); | |
705 | if (!(reg & BMCR_RESET)) { | |
706 | udelay(20); | |
707 | break; | |
708 | } | |
709 | } | |
710 | if (i == PHY_RESET_MAX_WAIT) { | |
711 | return -EBUSY; | |
712 | } | |
713 | return 0; | |
714 | } | |
715 | ||
716 | static u32 | |
717 | bnx2_phy_get_pause_adv(struct bnx2 *bp) | |
718 | { | |
719 | u32 adv = 0; | |
720 | ||
721 | if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == | |
722 | (FLOW_CTRL_RX | FLOW_CTRL_TX)) { | |
723 | ||
724 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
725 | adv = ADVERTISE_1000XPAUSE; | |
726 | } | |
727 | else { | |
728 | adv = ADVERTISE_PAUSE_CAP; | |
729 | } | |
730 | } | |
731 | else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { | |
732 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
733 | adv = ADVERTISE_1000XPSE_ASYM; | |
734 | } | |
735 | else { | |
736 | adv = ADVERTISE_PAUSE_ASYM; | |
737 | } | |
738 | } | |
739 | else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { | |
740 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
741 | adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; | |
742 | } | |
743 | else { | |
744 | adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
745 | } | |
746 | } | |
747 | return adv; | |
748 | } | |
749 | ||
750 | static int | |
751 | bnx2_setup_serdes_phy(struct bnx2 *bp) | |
752 | { | |
753 | u32 adv, bmcr; | |
754 | u32 new_adv = 0; | |
755 | ||
756 | if (!(bp->autoneg & AUTONEG_SPEED)) { | |
757 | u32 new_bmcr; | |
758 | ||
759 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
760 | new_bmcr = bmcr & ~BMCR_ANENABLE; | |
761 | new_bmcr |= BMCR_SPEED1000; | |
762 | if (bp->req_duplex == DUPLEX_FULL) { | |
763 | new_bmcr |= BMCR_FULLDPLX; | |
764 | } | |
765 | else { | |
766 | new_bmcr &= ~BMCR_FULLDPLX; | |
767 | } | |
768 | if (new_bmcr != bmcr) { | |
769 | /* Force a link down visible on the other side */ | |
770 | if (bp->link_up) { | |
771 | bnx2_read_phy(bp, MII_ADVERTISE, &adv); | |
772 | adv &= ~(ADVERTISE_1000XFULL | | |
773 | ADVERTISE_1000XHALF); | |
774 | bnx2_write_phy(bp, MII_ADVERTISE, adv); | |
775 | bnx2_write_phy(bp, MII_BMCR, bmcr | | |
776 | BMCR_ANRESTART | BMCR_ANENABLE); | |
777 | ||
778 | bp->link_up = 0; | |
779 | netif_carrier_off(bp->dev); | |
780 | } | |
781 | bnx2_write_phy(bp, MII_BMCR, new_bmcr); | |
782 | } | |
783 | return 0; | |
784 | } | |
785 | ||
786 | if (bp->advertising & ADVERTISED_1000baseT_Full) | |
787 | new_adv |= ADVERTISE_1000XFULL; | |
788 | ||
789 | new_adv |= bnx2_phy_get_pause_adv(bp); | |
790 | ||
791 | bnx2_read_phy(bp, MII_ADVERTISE, &adv); | |
792 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
793 | ||
794 | bp->serdes_an_pending = 0; | |
795 | if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { | |
796 | /* Force a link down visible on the other side */ | |
797 | if (bp->link_up) { | |
798 | int i; | |
799 | ||
800 | bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); | |
801 | for (i = 0; i < 110; i++) { | |
802 | udelay(100); | |
803 | } | |
804 | } | |
805 | ||
806 | bnx2_write_phy(bp, MII_ADVERTISE, new_adv); | |
807 | bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | | |
808 | BMCR_ANENABLE); | |
809 | bp->serdes_an_pending = SERDES_AN_TIMEOUT / bp->timer_interval; | |
810 | } | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
815 | #define ETHTOOL_ALL_FIBRE_SPEED \ | |
816 | (ADVERTISED_1000baseT_Full) | |
817 | ||
818 | #define ETHTOOL_ALL_COPPER_SPEED \ | |
819 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ | |
820 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ | |
821 | ADVERTISED_1000baseT_Full) | |
822 | ||
823 | #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ | |
824 | ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) | |
825 | ||
826 | #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) | |
827 | ||
828 | static int | |
829 | bnx2_setup_copper_phy(struct bnx2 *bp) | |
830 | { | |
831 | u32 bmcr; | |
832 | u32 new_bmcr; | |
833 | ||
834 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
835 | ||
836 | if (bp->autoneg & AUTONEG_SPEED) { | |
837 | u32 adv_reg, adv1000_reg; | |
838 | u32 new_adv_reg = 0; | |
839 | u32 new_adv1000_reg = 0; | |
840 | ||
841 | bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg); | |
842 | adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | | |
843 | ADVERTISE_PAUSE_ASYM); | |
844 | ||
845 | bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); | |
846 | adv1000_reg &= PHY_ALL_1000_SPEED; | |
847 | ||
848 | if (bp->advertising & ADVERTISED_10baseT_Half) | |
849 | new_adv_reg |= ADVERTISE_10HALF; | |
850 | if (bp->advertising & ADVERTISED_10baseT_Full) | |
851 | new_adv_reg |= ADVERTISE_10FULL; | |
852 | if (bp->advertising & ADVERTISED_100baseT_Half) | |
853 | new_adv_reg |= ADVERTISE_100HALF; | |
854 | if (bp->advertising & ADVERTISED_100baseT_Full) | |
855 | new_adv_reg |= ADVERTISE_100FULL; | |
856 | if (bp->advertising & ADVERTISED_1000baseT_Full) | |
857 | new_adv1000_reg |= ADVERTISE_1000FULL; | |
858 | ||
859 | new_adv_reg |= ADVERTISE_CSMA; | |
860 | ||
861 | new_adv_reg |= bnx2_phy_get_pause_adv(bp); | |
862 | ||
863 | if ((adv1000_reg != new_adv1000_reg) || | |
864 | (adv_reg != new_adv_reg) || | |
865 | ((bmcr & BMCR_ANENABLE) == 0)) { | |
866 | ||
867 | bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg); | |
868 | bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg); | |
869 | bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART | | |
870 | BMCR_ANENABLE); | |
871 | } | |
872 | else if (bp->link_up) { | |
873 | /* Flow ctrl may have changed from auto to forced */ | |
874 | /* or vice-versa. */ | |
875 | ||
876 | bnx2_resolve_flow_ctrl(bp); | |
877 | bnx2_set_mac_link(bp); | |
878 | } | |
879 | return 0; | |
880 | } | |
881 | ||
882 | new_bmcr = 0; | |
883 | if (bp->req_line_speed == SPEED_100) { | |
884 | new_bmcr |= BMCR_SPEED100; | |
885 | } | |
886 | if (bp->req_duplex == DUPLEX_FULL) { | |
887 | new_bmcr |= BMCR_FULLDPLX; | |
888 | } | |
889 | if (new_bmcr != bmcr) { | |
890 | u32 bmsr; | |
891 | int i = 0; | |
892 | ||
893 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | |
894 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | |
895 | ||
896 | if (bmsr & BMSR_LSTATUS) { | |
897 | /* Force link down */ | |
898 | bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); | |
899 | do { | |
900 | udelay(100); | |
901 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | |
902 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | |
903 | i++; | |
904 | } while ((bmsr & BMSR_LSTATUS) && (i < 620)); | |
905 | } | |
906 | ||
907 | bnx2_write_phy(bp, MII_BMCR, new_bmcr); | |
908 | ||
909 | /* Normally, the new speed is setup after the link has | |
910 | * gone down and up again. In some cases, link will not go | |
911 | * down so we need to set up the new speed here. | |
912 | */ | |
913 | if (bmsr & BMSR_LSTATUS) { | |
914 | bp->line_speed = bp->req_line_speed; | |
915 | bp->duplex = bp->req_duplex; | |
916 | bnx2_resolve_flow_ctrl(bp); | |
917 | bnx2_set_mac_link(bp); | |
918 | } | |
919 | } | |
920 | return 0; | |
921 | } | |
922 | ||
923 | static int | |
924 | bnx2_setup_phy(struct bnx2 *bp) | |
925 | { | |
926 | if (bp->loopback == MAC_LOOPBACK) | |
927 | return 0; | |
928 | ||
929 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
930 | return (bnx2_setup_serdes_phy(bp)); | |
931 | } | |
932 | else { | |
933 | return (bnx2_setup_copper_phy(bp)); | |
934 | } | |
935 | } | |
936 | ||
937 | static int | |
938 | bnx2_init_serdes_phy(struct bnx2 *bp) | |
939 | { | |
940 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | |
941 | ||
942 | if (CHIP_NUM(bp) == CHIP_NUM_5706) { | |
943 | REG_WR(bp, BNX2_MISC_UNUSED0, 0x300); | |
944 | } | |
945 | ||
946 | if (bp->dev->mtu > 1500) { | |
947 | u32 val; | |
948 | ||
949 | /* Set extended packet length bit */ | |
950 | bnx2_write_phy(bp, 0x18, 0x7); | |
951 | bnx2_read_phy(bp, 0x18, &val); | |
952 | bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); | |
953 | ||
954 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
955 | bnx2_read_phy(bp, 0x1c, &val); | |
956 | bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); | |
957 | } | |
958 | else { | |
959 | u32 val; | |
960 | ||
961 | bnx2_write_phy(bp, 0x18, 0x7); | |
962 | bnx2_read_phy(bp, 0x18, &val); | |
963 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
964 | ||
965 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
966 | bnx2_read_phy(bp, 0x1c, &val); | |
967 | bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); | |
968 | } | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
973 | static int | |
974 | bnx2_init_copper_phy(struct bnx2 *bp) | |
975 | { | |
976 | bp->phy_flags |= PHY_CRC_FIX_FLAG; | |
977 | ||
978 | if (bp->phy_flags & PHY_CRC_FIX_FLAG) { | |
979 | bnx2_write_phy(bp, 0x18, 0x0c00); | |
980 | bnx2_write_phy(bp, 0x17, 0x000a); | |
981 | bnx2_write_phy(bp, 0x15, 0x310b); | |
982 | bnx2_write_phy(bp, 0x17, 0x201f); | |
983 | bnx2_write_phy(bp, 0x15, 0x9506); | |
984 | bnx2_write_phy(bp, 0x17, 0x401f); | |
985 | bnx2_write_phy(bp, 0x15, 0x14e2); | |
986 | bnx2_write_phy(bp, 0x18, 0x0400); | |
987 | } | |
988 | ||
989 | if (bp->dev->mtu > 1500) { | |
990 | u32 val; | |
991 | ||
992 | /* Set extended packet length bit */ | |
993 | bnx2_write_phy(bp, 0x18, 0x7); | |
994 | bnx2_read_phy(bp, 0x18, &val); | |
995 | bnx2_write_phy(bp, 0x18, val | 0x4000); | |
996 | ||
997 | bnx2_read_phy(bp, 0x10, &val); | |
998 | bnx2_write_phy(bp, 0x10, val | 0x1); | |
999 | } | |
1000 | else { | |
1001 | u32 val; | |
1002 | ||
1003 | bnx2_write_phy(bp, 0x18, 0x7); | |
1004 | bnx2_read_phy(bp, 0x18, &val); | |
1005 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
1006 | ||
1007 | bnx2_read_phy(bp, 0x10, &val); | |
1008 | bnx2_write_phy(bp, 0x10, val & ~0x1); | |
1009 | } | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | ||
1015 | static int | |
1016 | bnx2_init_phy(struct bnx2 *bp) | |
1017 | { | |
1018 | u32 val; | |
1019 | int rc = 0; | |
1020 | ||
1021 | bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG; | |
1022 | bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG; | |
1023 | ||
1024 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); | |
1025 | ||
1026 | bnx2_reset_phy(bp); | |
1027 | ||
1028 | bnx2_read_phy(bp, MII_PHYSID1, &val); | |
1029 | bp->phy_id = val << 16; | |
1030 | bnx2_read_phy(bp, MII_PHYSID2, &val); | |
1031 | bp->phy_id |= val & 0xffff; | |
1032 | ||
1033 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
1034 | rc = bnx2_init_serdes_phy(bp); | |
1035 | } | |
1036 | else { | |
1037 | rc = bnx2_init_copper_phy(bp); | |
1038 | } | |
1039 | ||
1040 | bnx2_setup_phy(bp); | |
1041 | ||
1042 | return rc; | |
1043 | } | |
1044 | ||
1045 | static int | |
1046 | bnx2_set_mac_loopback(struct bnx2 *bp) | |
1047 | { | |
1048 | u32 mac_mode; | |
1049 | ||
1050 | mac_mode = REG_RD(bp, BNX2_EMAC_MODE); | |
1051 | mac_mode &= ~BNX2_EMAC_MODE_PORT; | |
1052 | mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; | |
1053 | REG_WR(bp, BNX2_EMAC_MODE, mac_mode); | |
1054 | bp->link_up = 1; | |
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | static int | |
1059 | bnx2_fw_sync(struct bnx2 *bp, u32 msg_data) | |
1060 | { | |
1061 | int i; | |
1062 | u32 val; | |
1063 | ||
1064 | if (bp->fw_timed_out) | |
1065 | return -EBUSY; | |
1066 | ||
1067 | bp->fw_wr_seq++; | |
1068 | msg_data |= bp->fw_wr_seq; | |
1069 | ||
1070 | REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data); | |
1071 | ||
1072 | /* wait for an acknowledgement. */ | |
1073 | for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) { | |
1074 | udelay(5); | |
1075 | ||
1076 | val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB); | |
1077 | ||
1078 | if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) | |
1079 | break; | |
1080 | } | |
1081 | ||
1082 | /* If we timed out, inform the firmware that this is the case. */ | |
1083 | if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) && | |
1084 | ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) { | |
1085 | ||
1086 | msg_data &= ~BNX2_DRV_MSG_CODE; | |
1087 | msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; | |
1088 | ||
1089 | REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data); | |
1090 | ||
1091 | bp->fw_timed_out = 1; | |
1092 | ||
1093 | return -EBUSY; | |
1094 | } | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | static void | |
1100 | bnx2_init_context(struct bnx2 *bp) | |
1101 | { | |
1102 | u32 vcid; | |
1103 | ||
1104 | vcid = 96; | |
1105 | while (vcid) { | |
1106 | u32 vcid_addr, pcid_addr, offset; | |
1107 | ||
1108 | vcid--; | |
1109 | ||
1110 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
1111 | u32 new_vcid; | |
1112 | ||
1113 | vcid_addr = GET_PCID_ADDR(vcid); | |
1114 | if (vcid & 0x8) { | |
1115 | new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); | |
1116 | } | |
1117 | else { | |
1118 | new_vcid = vcid; | |
1119 | } | |
1120 | pcid_addr = GET_PCID_ADDR(new_vcid); | |
1121 | } | |
1122 | else { | |
1123 | vcid_addr = GET_CID_ADDR(vcid); | |
1124 | pcid_addr = vcid_addr; | |
1125 | } | |
1126 | ||
1127 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00); | |
1128 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | |
1129 | ||
1130 | /* Zero out the context. */ | |
1131 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { | |
1132 | CTX_WR(bp, 0x00, offset, 0); | |
1133 | } | |
1134 | ||
1135 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); | |
1136 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | |
1137 | } | |
1138 | } | |
1139 | ||
1140 | static int | |
1141 | bnx2_alloc_bad_rbuf(struct bnx2 *bp) | |
1142 | { | |
1143 | u16 *good_mbuf; | |
1144 | u32 good_mbuf_cnt; | |
1145 | u32 val; | |
1146 | ||
1147 | good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL); | |
1148 | if (good_mbuf == NULL) { | |
1149 | printk(KERN_ERR PFX "Failed to allocate memory in " | |
1150 | "bnx2_alloc_bad_rbuf\n"); | |
1151 | return -ENOMEM; | |
1152 | } | |
1153 | ||
1154 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
1155 | BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); | |
1156 | ||
1157 | good_mbuf_cnt = 0; | |
1158 | ||
1159 | /* Allocate a bunch of mbufs and save the good ones in an array. */ | |
1160 | val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); | |
1161 | while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { | |
1162 | REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ); | |
1163 | ||
1164 | val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC); | |
1165 | ||
1166 | val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; | |
1167 | ||
1168 | /* The addresses with Bit 9 set are bad memory blocks. */ | |
1169 | if (!(val & (1 << 9))) { | |
1170 | good_mbuf[good_mbuf_cnt] = (u16) val; | |
1171 | good_mbuf_cnt++; | |
1172 | } | |
1173 | ||
1174 | val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); | |
1175 | } | |
1176 | ||
1177 | /* Free the good ones back to the mbuf pool thus discarding | |
1178 | * all the bad ones. */ | |
1179 | while (good_mbuf_cnt) { | |
1180 | good_mbuf_cnt--; | |
1181 | ||
1182 | val = good_mbuf[good_mbuf_cnt]; | |
1183 | val = (val << 9) | val | 1; | |
1184 | ||
1185 | REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val); | |
1186 | } | |
1187 | kfree(good_mbuf); | |
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | static void | |
1192 | bnx2_set_mac_addr(struct bnx2 *bp) | |
1193 | { | |
1194 | u32 val; | |
1195 | u8 *mac_addr = bp->dev->dev_addr; | |
1196 | ||
1197 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
1198 | ||
1199 | REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val); | |
1200 | ||
1201 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
1202 | (mac_addr[4] << 8) | mac_addr[5]; | |
1203 | ||
1204 | REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val); | |
1205 | } | |
1206 | ||
1207 | static inline int | |
1208 | bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index) | |
1209 | { | |
1210 | struct sk_buff *skb; | |
1211 | struct sw_bd *rx_buf = &bp->rx_buf_ring[index]; | |
1212 | dma_addr_t mapping; | |
1213 | struct rx_bd *rxbd = &bp->rx_desc_ring[index]; | |
1214 | unsigned long align; | |
1215 | ||
1216 | skb = dev_alloc_skb(bp->rx_buf_size); | |
1217 | if (skb == NULL) { | |
1218 | return -ENOMEM; | |
1219 | } | |
1220 | ||
1221 | if (unlikely((align = (unsigned long) skb->data & 0x7))) { | |
1222 | skb_reserve(skb, 8 - align); | |
1223 | } | |
1224 | ||
1225 | skb->dev = bp->dev; | |
1226 | mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size, | |
1227 | PCI_DMA_FROMDEVICE); | |
1228 | ||
1229 | rx_buf->skb = skb; | |
1230 | pci_unmap_addr_set(rx_buf, mapping, mapping); | |
1231 | ||
1232 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; | |
1233 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
1234 | ||
1235 | bp->rx_prod_bseq += bp->rx_buf_use_size; | |
1236 | ||
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | static void | |
1241 | bnx2_phy_int(struct bnx2 *bp) | |
1242 | { | |
1243 | u32 new_link_state, old_link_state; | |
1244 | ||
1245 | new_link_state = bp->status_blk->status_attn_bits & | |
1246 | STATUS_ATTN_BITS_LINK_STATE; | |
1247 | old_link_state = bp->status_blk->status_attn_bits_ack & | |
1248 | STATUS_ATTN_BITS_LINK_STATE; | |
1249 | if (new_link_state != old_link_state) { | |
1250 | if (new_link_state) { | |
1251 | REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, | |
1252 | STATUS_ATTN_BITS_LINK_STATE); | |
1253 | } | |
1254 | else { | |
1255 | REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, | |
1256 | STATUS_ATTN_BITS_LINK_STATE); | |
1257 | } | |
1258 | bnx2_set_link(bp); | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | static void | |
1263 | bnx2_tx_int(struct bnx2 *bp) | |
1264 | { | |
1265 | u16 hw_cons, sw_cons, sw_ring_cons; | |
1266 | int tx_free_bd = 0; | |
1267 | ||
1268 | hw_cons = bp->status_blk->status_tx_quick_consumer_index0; | |
1269 | if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) { | |
1270 | hw_cons++; | |
1271 | } | |
1272 | sw_cons = bp->tx_cons; | |
1273 | ||
1274 | while (sw_cons != hw_cons) { | |
1275 | struct sw_bd *tx_buf; | |
1276 | struct sk_buff *skb; | |
1277 | int i, last; | |
1278 | ||
1279 | sw_ring_cons = TX_RING_IDX(sw_cons); | |
1280 | ||
1281 | tx_buf = &bp->tx_buf_ring[sw_ring_cons]; | |
1282 | skb = tx_buf->skb; | |
1283 | #ifdef BCM_TSO | |
1284 | /* partial BD completions possible with TSO packets */ | |
1285 | if (skb_shinfo(skb)->tso_size) { | |
1286 | u16 last_idx, last_ring_idx; | |
1287 | ||
1288 | last_idx = sw_cons + | |
1289 | skb_shinfo(skb)->nr_frags + 1; | |
1290 | last_ring_idx = sw_ring_cons + | |
1291 | skb_shinfo(skb)->nr_frags + 1; | |
1292 | if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) { | |
1293 | last_idx++; | |
1294 | } | |
1295 | if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { | |
1296 | break; | |
1297 | } | |
1298 | } | |
1299 | #endif | |
1300 | pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), | |
1301 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
1302 | ||
1303 | tx_buf->skb = NULL; | |
1304 | last = skb_shinfo(skb)->nr_frags; | |
1305 | ||
1306 | for (i = 0; i < last; i++) { | |
1307 | sw_cons = NEXT_TX_BD(sw_cons); | |
1308 | ||
1309 | pci_unmap_page(bp->pdev, | |
1310 | pci_unmap_addr( | |
1311 | &bp->tx_buf_ring[TX_RING_IDX(sw_cons)], | |
1312 | mapping), | |
1313 | skb_shinfo(skb)->frags[i].size, | |
1314 | PCI_DMA_TODEVICE); | |
1315 | } | |
1316 | ||
1317 | sw_cons = NEXT_TX_BD(sw_cons); | |
1318 | ||
1319 | tx_free_bd += last + 1; | |
1320 | ||
1321 | dev_kfree_skb_irq(skb); | |
1322 | ||
1323 | hw_cons = bp->status_blk->status_tx_quick_consumer_index0; | |
1324 | if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) { | |
1325 | hw_cons++; | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | atomic_add(tx_free_bd, &bp->tx_avail_bd); | |
1330 | ||
1331 | if (unlikely(netif_queue_stopped(bp->dev))) { | |
1332 | unsigned long flags; | |
1333 | ||
1334 | spin_lock_irqsave(&bp->tx_lock, flags); | |
1335 | if ((netif_queue_stopped(bp->dev)) && | |
1336 | (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)) { | |
1337 | ||
1338 | netif_wake_queue(bp->dev); | |
1339 | } | |
1340 | spin_unlock_irqrestore(&bp->tx_lock, flags); | |
1341 | } | |
1342 | ||
1343 | bp->tx_cons = sw_cons; | |
1344 | ||
1345 | } | |
1346 | ||
1347 | static inline void | |
1348 | bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb, | |
1349 | u16 cons, u16 prod) | |
1350 | { | |
1351 | struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons]; | |
1352 | struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod]; | |
1353 | struct rx_bd *cons_bd = &bp->rx_desc_ring[cons]; | |
1354 | struct rx_bd *prod_bd = &bp->rx_desc_ring[prod]; | |
1355 | ||
1356 | pci_dma_sync_single_for_device(bp->pdev, | |
1357 | pci_unmap_addr(cons_rx_buf, mapping), | |
1358 | bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); | |
1359 | ||
1360 | prod_rx_buf->skb = cons_rx_buf->skb; | |
1361 | pci_unmap_addr_set(prod_rx_buf, mapping, | |
1362 | pci_unmap_addr(cons_rx_buf, mapping)); | |
1363 | ||
1364 | memcpy(prod_bd, cons_bd, 8); | |
1365 | ||
1366 | bp->rx_prod_bseq += bp->rx_buf_use_size; | |
1367 | ||
1368 | } | |
1369 | ||
1370 | static int | |
1371 | bnx2_rx_int(struct bnx2 *bp, int budget) | |
1372 | { | |
1373 | u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; | |
1374 | struct l2_fhdr *rx_hdr; | |
1375 | int rx_pkt = 0; | |
1376 | ||
1377 | hw_cons = bp->status_blk->status_rx_quick_consumer_index0; | |
1378 | if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) { | |
1379 | hw_cons++; | |
1380 | } | |
1381 | sw_cons = bp->rx_cons; | |
1382 | sw_prod = bp->rx_prod; | |
1383 | ||
1384 | /* Memory barrier necessary as speculative reads of the rx | |
1385 | * buffer can be ahead of the index in the status block | |
1386 | */ | |
1387 | rmb(); | |
1388 | while (sw_cons != hw_cons) { | |
1389 | unsigned int len; | |
1390 | u16 status; | |
1391 | struct sw_bd *rx_buf; | |
1392 | struct sk_buff *skb; | |
1393 | ||
1394 | sw_ring_cons = RX_RING_IDX(sw_cons); | |
1395 | sw_ring_prod = RX_RING_IDX(sw_prod); | |
1396 | ||
1397 | rx_buf = &bp->rx_buf_ring[sw_ring_cons]; | |
1398 | skb = rx_buf->skb; | |
1399 | pci_dma_sync_single_for_cpu(bp->pdev, | |
1400 | pci_unmap_addr(rx_buf, mapping), | |
1401 | bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); | |
1402 | ||
1403 | rx_hdr = (struct l2_fhdr *) skb->data; | |
1404 | len = rx_hdr->l2_fhdr_pkt_len - 4; | |
1405 | ||
1406 | if (rx_hdr->l2_fhdr_errors & | |
1407 | (L2_FHDR_ERRORS_BAD_CRC | | |
1408 | L2_FHDR_ERRORS_PHY_DECODE | | |
1409 | L2_FHDR_ERRORS_ALIGNMENT | | |
1410 | L2_FHDR_ERRORS_TOO_SHORT | | |
1411 | L2_FHDR_ERRORS_GIANT_FRAME)) { | |
1412 | ||
1413 | goto reuse_rx; | |
1414 | } | |
1415 | ||
1416 | /* Since we don't have a jumbo ring, copy small packets | |
1417 | * if mtu > 1500 | |
1418 | */ | |
1419 | if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) { | |
1420 | struct sk_buff *new_skb; | |
1421 | ||
1422 | new_skb = dev_alloc_skb(len + 2); | |
1423 | if (new_skb == NULL) | |
1424 | goto reuse_rx; | |
1425 | ||
1426 | /* aligned copy */ | |
1427 | memcpy(new_skb->data, | |
1428 | skb->data + bp->rx_offset - 2, | |
1429 | len + 2); | |
1430 | ||
1431 | skb_reserve(new_skb, 2); | |
1432 | skb_put(new_skb, len); | |
1433 | new_skb->dev = bp->dev; | |
1434 | ||
1435 | bnx2_reuse_rx_skb(bp, skb, | |
1436 | sw_ring_cons, sw_ring_prod); | |
1437 | ||
1438 | skb = new_skb; | |
1439 | } | |
1440 | else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) { | |
1441 | pci_unmap_single(bp->pdev, | |
1442 | pci_unmap_addr(rx_buf, mapping), | |
1443 | bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); | |
1444 | ||
1445 | skb_reserve(skb, bp->rx_offset); | |
1446 | skb_put(skb, len); | |
1447 | } | |
1448 | else { | |
1449 | reuse_rx: | |
1450 | bnx2_reuse_rx_skb(bp, skb, | |
1451 | sw_ring_cons, sw_ring_prod); | |
1452 | goto next_rx; | |
1453 | } | |
1454 | ||
1455 | skb->protocol = eth_type_trans(skb, bp->dev); | |
1456 | ||
1457 | if ((len > (bp->dev->mtu + ETH_HLEN)) && | |
1458 | (htons(skb->protocol) != 0x8100)) { | |
1459 | ||
1460 | dev_kfree_skb_irq(skb); | |
1461 | goto next_rx; | |
1462 | ||
1463 | } | |
1464 | ||
1465 | status = rx_hdr->l2_fhdr_status; | |
1466 | skb->ip_summed = CHECKSUM_NONE; | |
1467 | if (bp->rx_csum && | |
1468 | (status & (L2_FHDR_STATUS_TCP_SEGMENT | | |
1469 | L2_FHDR_STATUS_UDP_DATAGRAM))) { | |
1470 | ||
1471 | u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum; | |
1472 | ||
1473 | if (cksum == 0xffff) | |
1474 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1475 | } | |
1476 | ||
1477 | #ifdef BCM_VLAN | |
1478 | if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) { | |
1479 | vlan_hwaccel_receive_skb(skb, bp->vlgrp, | |
1480 | rx_hdr->l2_fhdr_vlan_tag); | |
1481 | } | |
1482 | else | |
1483 | #endif | |
1484 | netif_receive_skb(skb); | |
1485 | ||
1486 | bp->dev->last_rx = jiffies; | |
1487 | rx_pkt++; | |
1488 | ||
1489 | next_rx: | |
1490 | rx_buf->skb = NULL; | |
1491 | ||
1492 | sw_cons = NEXT_RX_BD(sw_cons); | |
1493 | sw_prod = NEXT_RX_BD(sw_prod); | |
1494 | ||
1495 | if ((rx_pkt == budget)) | |
1496 | break; | |
1497 | } | |
1498 | bp->rx_cons = sw_cons; | |
1499 | bp->rx_prod = sw_prod; | |
1500 | ||
1501 | REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod); | |
1502 | ||
1503 | REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq); | |
1504 | ||
1505 | mmiowb(); | |
1506 | ||
1507 | return rx_pkt; | |
1508 | ||
1509 | } | |
1510 | ||
1511 | /* MSI ISR - The only difference between this and the INTx ISR | |
1512 | * is that the MSI interrupt is always serviced. | |
1513 | */ | |
1514 | static irqreturn_t | |
1515 | bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs) | |
1516 | { | |
1517 | struct net_device *dev = dev_instance; | |
1518 | struct bnx2 *bp = dev->priv; | |
1519 | ||
1520 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
1521 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | | |
1522 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
1523 | ||
1524 | /* Return here if interrupt is disabled. */ | |
1525 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) { | |
1526 | return IRQ_RETVAL(1); | |
1527 | } | |
1528 | ||
1529 | if (netif_rx_schedule_prep(dev)) { | |
1530 | __netif_rx_schedule(dev); | |
1531 | } | |
1532 | ||
1533 | return IRQ_RETVAL(1); | |
1534 | } | |
1535 | ||
1536 | static irqreturn_t | |
1537 | bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | |
1538 | { | |
1539 | struct net_device *dev = dev_instance; | |
1540 | struct bnx2 *bp = dev->priv; | |
1541 | ||
1542 | /* When using INTx, it is possible for the interrupt to arrive | |
1543 | * at the CPU before the status block posted prior to the | |
1544 | * interrupt. Reading a register will flush the status block. | |
1545 | * When using MSI, the MSI message will always complete after | |
1546 | * the status block write. | |
1547 | */ | |
1548 | if ((bp->status_blk->status_idx == bp->last_status_idx) || | |
1549 | (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) & | |
1550 | BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) | |
1551 | return IRQ_RETVAL(0); | |
1552 | ||
1553 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
1554 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | | |
1555 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
1556 | ||
1557 | /* Return here if interrupt is shared and is disabled. */ | |
1558 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) { | |
1559 | return IRQ_RETVAL(1); | |
1560 | } | |
1561 | ||
1562 | if (netif_rx_schedule_prep(dev)) { | |
1563 | __netif_rx_schedule(dev); | |
1564 | } | |
1565 | ||
1566 | return IRQ_RETVAL(1); | |
1567 | } | |
1568 | ||
1569 | static int | |
1570 | bnx2_poll(struct net_device *dev, int *budget) | |
1571 | { | |
1572 | struct bnx2 *bp = dev->priv; | |
1573 | int rx_done = 1; | |
1574 | ||
1575 | bp->last_status_idx = bp->status_blk->status_idx; | |
1576 | ||
1577 | rmb(); | |
1578 | if ((bp->status_blk->status_attn_bits & | |
1579 | STATUS_ATTN_BITS_LINK_STATE) != | |
1580 | (bp->status_blk->status_attn_bits_ack & | |
1581 | STATUS_ATTN_BITS_LINK_STATE)) { | |
1582 | ||
1583 | unsigned long flags; | |
1584 | ||
1585 | spin_lock_irqsave(&bp->phy_lock, flags); | |
1586 | bnx2_phy_int(bp); | |
1587 | spin_unlock_irqrestore(&bp->phy_lock, flags); | |
1588 | } | |
1589 | ||
1590 | if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) { | |
1591 | bnx2_tx_int(bp); | |
1592 | } | |
1593 | ||
1594 | if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) { | |
1595 | int orig_budget = *budget; | |
1596 | int work_done; | |
1597 | ||
1598 | if (orig_budget > dev->quota) | |
1599 | orig_budget = dev->quota; | |
1600 | ||
1601 | work_done = bnx2_rx_int(bp, orig_budget); | |
1602 | *budget -= work_done; | |
1603 | dev->quota -= work_done; | |
1604 | ||
1605 | if (work_done >= orig_budget) { | |
1606 | rx_done = 0; | |
1607 | } | |
1608 | } | |
1609 | ||
1610 | if (rx_done) { | |
1611 | netif_rx_complete(dev); | |
1612 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
1613 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
1614 | bp->last_status_idx); | |
1615 | return 0; | |
1616 | } | |
1617 | ||
1618 | return 1; | |
1619 | } | |
1620 | ||
1621 | /* Called with rtnl_lock from vlan functions and also dev->xmit_lock | |
1622 | * from set_multicast. | |
1623 | */ | |
1624 | static void | |
1625 | bnx2_set_rx_mode(struct net_device *dev) | |
1626 | { | |
1627 | struct bnx2 *bp = dev->priv; | |
1628 | u32 rx_mode, sort_mode; | |
1629 | int i; | |
1630 | unsigned long flags; | |
1631 | ||
1632 | spin_lock_irqsave(&bp->phy_lock, flags); | |
1633 | ||
1634 | rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | | |
1635 | BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); | |
1636 | sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; | |
1637 | #ifdef BCM_VLAN | |
1638 | if (!bp->vlgrp) { | |
1639 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; | |
1640 | } | |
1641 | #else | |
1642 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; | |
1643 | #endif | |
1644 | if (dev->flags & IFF_PROMISC) { | |
1645 | /* Promiscuous mode. */ | |
1646 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; | |
1647 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN; | |
1648 | } | |
1649 | else if (dev->flags & IFF_ALLMULTI) { | |
1650 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
1651 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
1652 | 0xffffffff); | |
1653 | } | |
1654 | sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; | |
1655 | } | |
1656 | else { | |
1657 | /* Accept one or more multicast(s). */ | |
1658 | struct dev_mc_list *mclist; | |
1659 | u32 mc_filter[NUM_MC_HASH_REGISTERS]; | |
1660 | u32 regidx; | |
1661 | u32 bit; | |
1662 | u32 crc; | |
1663 | ||
1664 | memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); | |
1665 | ||
1666 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1667 | i++, mclist = mclist->next) { | |
1668 | ||
1669 | crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr); | |
1670 | bit = crc & 0xff; | |
1671 | regidx = (bit & 0xe0) >> 5; | |
1672 | bit &= 0x1f; | |
1673 | mc_filter[regidx] |= (1 << bit); | |
1674 | } | |
1675 | ||
1676 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
1677 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
1678 | mc_filter[i]); | |
1679 | } | |
1680 | ||
1681 | sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; | |
1682 | } | |
1683 | ||
1684 | if (rx_mode != bp->rx_mode) { | |
1685 | bp->rx_mode = rx_mode; | |
1686 | REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); | |
1687 | } | |
1688 | ||
1689 | REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | |
1690 | REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); | |
1691 | REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); | |
1692 | ||
1693 | spin_unlock_irqrestore(&bp->phy_lock, flags); | |
1694 | } | |
1695 | ||
1696 | static void | |
1697 | load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, | |
1698 | u32 rv2p_proc) | |
1699 | { | |
1700 | int i; | |
1701 | u32 val; | |
1702 | ||
1703 | ||
1704 | for (i = 0; i < rv2p_code_len; i += 8) { | |
1705 | REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code); | |
1706 | rv2p_code++; | |
1707 | REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code); | |
1708 | rv2p_code++; | |
1709 | ||
1710 | if (rv2p_proc == RV2P_PROC1) { | |
1711 | val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR; | |
1712 | REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val); | |
1713 | } | |
1714 | else { | |
1715 | val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR; | |
1716 | REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val); | |
1717 | } | |
1718 | } | |
1719 | ||
1720 | /* Reset the processor, un-stall is done later. */ | |
1721 | if (rv2p_proc == RV2P_PROC1) { | |
1722 | REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); | |
1723 | } | |
1724 | else { | |
1725 | REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); | |
1726 | } | |
1727 | } | |
1728 | ||
1729 | static void | |
1730 | load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |
1731 | { | |
1732 | u32 offset; | |
1733 | u32 val; | |
1734 | ||
1735 | /* Halt the CPU. */ | |
1736 | val = REG_RD_IND(bp, cpu_reg->mode); | |
1737 | val |= cpu_reg->mode_value_halt; | |
1738 | REG_WR_IND(bp, cpu_reg->mode, val); | |
1739 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | |
1740 | ||
1741 | /* Load the Text area. */ | |
1742 | offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); | |
1743 | if (fw->text) { | |
1744 | int j; | |
1745 | ||
1746 | for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { | |
1747 | REG_WR_IND(bp, offset, fw->text[j]); | |
1748 | } | |
1749 | } | |
1750 | ||
1751 | /* Load the Data area. */ | |
1752 | offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); | |
1753 | if (fw->data) { | |
1754 | int j; | |
1755 | ||
1756 | for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { | |
1757 | REG_WR_IND(bp, offset, fw->data[j]); | |
1758 | } | |
1759 | } | |
1760 | ||
1761 | /* Load the SBSS area. */ | |
1762 | offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); | |
1763 | if (fw->sbss) { | |
1764 | int j; | |
1765 | ||
1766 | for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { | |
1767 | REG_WR_IND(bp, offset, fw->sbss[j]); | |
1768 | } | |
1769 | } | |
1770 | ||
1771 | /* Load the BSS area. */ | |
1772 | offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); | |
1773 | if (fw->bss) { | |
1774 | int j; | |
1775 | ||
1776 | for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { | |
1777 | REG_WR_IND(bp, offset, fw->bss[j]); | |
1778 | } | |
1779 | } | |
1780 | ||
1781 | /* Load the Read-Only area. */ | |
1782 | offset = cpu_reg->spad_base + | |
1783 | (fw->rodata_addr - cpu_reg->mips_view_base); | |
1784 | if (fw->rodata) { | |
1785 | int j; | |
1786 | ||
1787 | for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { | |
1788 | REG_WR_IND(bp, offset, fw->rodata[j]); | |
1789 | } | |
1790 | } | |
1791 | ||
1792 | /* Clear the pre-fetch instruction. */ | |
1793 | REG_WR_IND(bp, cpu_reg->inst, 0); | |
1794 | REG_WR_IND(bp, cpu_reg->pc, fw->start_addr); | |
1795 | ||
1796 | /* Start the CPU. */ | |
1797 | val = REG_RD_IND(bp, cpu_reg->mode); | |
1798 | val &= ~cpu_reg->mode_value_halt; | |
1799 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | |
1800 | REG_WR_IND(bp, cpu_reg->mode, val); | |
1801 | } | |
1802 | ||
1803 | static void | |
1804 | bnx2_init_cpus(struct bnx2 *bp) | |
1805 | { | |
1806 | struct cpu_reg cpu_reg; | |
1807 | struct fw_info fw; | |
1808 | ||
1809 | /* Initialize the RV2P processor. */ | |
1810 | load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1); | |
1811 | load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2); | |
1812 | ||
1813 | /* Initialize the RX Processor. */ | |
1814 | cpu_reg.mode = BNX2_RXP_CPU_MODE; | |
1815 | cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT; | |
1816 | cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA; | |
1817 | cpu_reg.state = BNX2_RXP_CPU_STATE; | |
1818 | cpu_reg.state_value_clear = 0xffffff; | |
1819 | cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE; | |
1820 | cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK; | |
1821 | cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER; | |
1822 | cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION; | |
1823 | cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT; | |
1824 | cpu_reg.spad_base = BNX2_RXP_SCRATCH; | |
1825 | cpu_reg.mips_view_base = 0x8000000; | |
1826 | ||
1827 | fw.ver_major = bnx2_RXP_b06FwReleaseMajor; | |
1828 | fw.ver_minor = bnx2_RXP_b06FwReleaseMinor; | |
1829 | fw.ver_fix = bnx2_RXP_b06FwReleaseFix; | |
1830 | fw.start_addr = bnx2_RXP_b06FwStartAddr; | |
1831 | ||
1832 | fw.text_addr = bnx2_RXP_b06FwTextAddr; | |
1833 | fw.text_len = bnx2_RXP_b06FwTextLen; | |
1834 | fw.text_index = 0; | |
1835 | fw.text = bnx2_RXP_b06FwText; | |
1836 | ||
1837 | fw.data_addr = bnx2_RXP_b06FwDataAddr; | |
1838 | fw.data_len = bnx2_RXP_b06FwDataLen; | |
1839 | fw.data_index = 0; | |
1840 | fw.data = bnx2_RXP_b06FwData; | |
1841 | ||
1842 | fw.sbss_addr = bnx2_RXP_b06FwSbssAddr; | |
1843 | fw.sbss_len = bnx2_RXP_b06FwSbssLen; | |
1844 | fw.sbss_index = 0; | |
1845 | fw.sbss = bnx2_RXP_b06FwSbss; | |
1846 | ||
1847 | fw.bss_addr = bnx2_RXP_b06FwBssAddr; | |
1848 | fw.bss_len = bnx2_RXP_b06FwBssLen; | |
1849 | fw.bss_index = 0; | |
1850 | fw.bss = bnx2_RXP_b06FwBss; | |
1851 | ||
1852 | fw.rodata_addr = bnx2_RXP_b06FwRodataAddr; | |
1853 | fw.rodata_len = bnx2_RXP_b06FwRodataLen; | |
1854 | fw.rodata_index = 0; | |
1855 | fw.rodata = bnx2_RXP_b06FwRodata; | |
1856 | ||
1857 | load_cpu_fw(bp, &cpu_reg, &fw); | |
1858 | ||
1859 | /* Initialize the TX Processor. */ | |
1860 | cpu_reg.mode = BNX2_TXP_CPU_MODE; | |
1861 | cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT; | |
1862 | cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA; | |
1863 | cpu_reg.state = BNX2_TXP_CPU_STATE; | |
1864 | cpu_reg.state_value_clear = 0xffffff; | |
1865 | cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE; | |
1866 | cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK; | |
1867 | cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER; | |
1868 | cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION; | |
1869 | cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT; | |
1870 | cpu_reg.spad_base = BNX2_TXP_SCRATCH; | |
1871 | cpu_reg.mips_view_base = 0x8000000; | |
1872 | ||
1873 | fw.ver_major = bnx2_TXP_b06FwReleaseMajor; | |
1874 | fw.ver_minor = bnx2_TXP_b06FwReleaseMinor; | |
1875 | fw.ver_fix = bnx2_TXP_b06FwReleaseFix; | |
1876 | fw.start_addr = bnx2_TXP_b06FwStartAddr; | |
1877 | ||
1878 | fw.text_addr = bnx2_TXP_b06FwTextAddr; | |
1879 | fw.text_len = bnx2_TXP_b06FwTextLen; | |
1880 | fw.text_index = 0; | |
1881 | fw.text = bnx2_TXP_b06FwText; | |
1882 | ||
1883 | fw.data_addr = bnx2_TXP_b06FwDataAddr; | |
1884 | fw.data_len = bnx2_TXP_b06FwDataLen; | |
1885 | fw.data_index = 0; | |
1886 | fw.data = bnx2_TXP_b06FwData; | |
1887 | ||
1888 | fw.sbss_addr = bnx2_TXP_b06FwSbssAddr; | |
1889 | fw.sbss_len = bnx2_TXP_b06FwSbssLen; | |
1890 | fw.sbss_index = 0; | |
1891 | fw.sbss = bnx2_TXP_b06FwSbss; | |
1892 | ||
1893 | fw.bss_addr = bnx2_TXP_b06FwBssAddr; | |
1894 | fw.bss_len = bnx2_TXP_b06FwBssLen; | |
1895 | fw.bss_index = 0; | |
1896 | fw.bss = bnx2_TXP_b06FwBss; | |
1897 | ||
1898 | fw.rodata_addr = bnx2_TXP_b06FwRodataAddr; | |
1899 | fw.rodata_len = bnx2_TXP_b06FwRodataLen; | |
1900 | fw.rodata_index = 0; | |
1901 | fw.rodata = bnx2_TXP_b06FwRodata; | |
1902 | ||
1903 | load_cpu_fw(bp, &cpu_reg, &fw); | |
1904 | ||
1905 | /* Initialize the TX Patch-up Processor. */ | |
1906 | cpu_reg.mode = BNX2_TPAT_CPU_MODE; | |
1907 | cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT; | |
1908 | cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA; | |
1909 | cpu_reg.state = BNX2_TPAT_CPU_STATE; | |
1910 | cpu_reg.state_value_clear = 0xffffff; | |
1911 | cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE; | |
1912 | cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK; | |
1913 | cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER; | |
1914 | cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION; | |
1915 | cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT; | |
1916 | cpu_reg.spad_base = BNX2_TPAT_SCRATCH; | |
1917 | cpu_reg.mips_view_base = 0x8000000; | |
1918 | ||
1919 | fw.ver_major = bnx2_TPAT_b06FwReleaseMajor; | |
1920 | fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor; | |
1921 | fw.ver_fix = bnx2_TPAT_b06FwReleaseFix; | |
1922 | fw.start_addr = bnx2_TPAT_b06FwStartAddr; | |
1923 | ||
1924 | fw.text_addr = bnx2_TPAT_b06FwTextAddr; | |
1925 | fw.text_len = bnx2_TPAT_b06FwTextLen; | |
1926 | fw.text_index = 0; | |
1927 | fw.text = bnx2_TPAT_b06FwText; | |
1928 | ||
1929 | fw.data_addr = bnx2_TPAT_b06FwDataAddr; | |
1930 | fw.data_len = bnx2_TPAT_b06FwDataLen; | |
1931 | fw.data_index = 0; | |
1932 | fw.data = bnx2_TPAT_b06FwData; | |
1933 | ||
1934 | fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr; | |
1935 | fw.sbss_len = bnx2_TPAT_b06FwSbssLen; | |
1936 | fw.sbss_index = 0; | |
1937 | fw.sbss = bnx2_TPAT_b06FwSbss; | |
1938 | ||
1939 | fw.bss_addr = bnx2_TPAT_b06FwBssAddr; | |
1940 | fw.bss_len = bnx2_TPAT_b06FwBssLen; | |
1941 | fw.bss_index = 0; | |
1942 | fw.bss = bnx2_TPAT_b06FwBss; | |
1943 | ||
1944 | fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr; | |
1945 | fw.rodata_len = bnx2_TPAT_b06FwRodataLen; | |
1946 | fw.rodata_index = 0; | |
1947 | fw.rodata = bnx2_TPAT_b06FwRodata; | |
1948 | ||
1949 | load_cpu_fw(bp, &cpu_reg, &fw); | |
1950 | ||
1951 | /* Initialize the Completion Processor. */ | |
1952 | cpu_reg.mode = BNX2_COM_CPU_MODE; | |
1953 | cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT; | |
1954 | cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA; | |
1955 | cpu_reg.state = BNX2_COM_CPU_STATE; | |
1956 | cpu_reg.state_value_clear = 0xffffff; | |
1957 | cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE; | |
1958 | cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK; | |
1959 | cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER; | |
1960 | cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION; | |
1961 | cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT; | |
1962 | cpu_reg.spad_base = BNX2_COM_SCRATCH; | |
1963 | cpu_reg.mips_view_base = 0x8000000; | |
1964 | ||
1965 | fw.ver_major = bnx2_COM_b06FwReleaseMajor; | |
1966 | fw.ver_minor = bnx2_COM_b06FwReleaseMinor; | |
1967 | fw.ver_fix = bnx2_COM_b06FwReleaseFix; | |
1968 | fw.start_addr = bnx2_COM_b06FwStartAddr; | |
1969 | ||
1970 | fw.text_addr = bnx2_COM_b06FwTextAddr; | |
1971 | fw.text_len = bnx2_COM_b06FwTextLen; | |
1972 | fw.text_index = 0; | |
1973 | fw.text = bnx2_COM_b06FwText; | |
1974 | ||
1975 | fw.data_addr = bnx2_COM_b06FwDataAddr; | |
1976 | fw.data_len = bnx2_COM_b06FwDataLen; | |
1977 | fw.data_index = 0; | |
1978 | fw.data = bnx2_COM_b06FwData; | |
1979 | ||
1980 | fw.sbss_addr = bnx2_COM_b06FwSbssAddr; | |
1981 | fw.sbss_len = bnx2_COM_b06FwSbssLen; | |
1982 | fw.sbss_index = 0; | |
1983 | fw.sbss = bnx2_COM_b06FwSbss; | |
1984 | ||
1985 | fw.bss_addr = bnx2_COM_b06FwBssAddr; | |
1986 | fw.bss_len = bnx2_COM_b06FwBssLen; | |
1987 | fw.bss_index = 0; | |
1988 | fw.bss = bnx2_COM_b06FwBss; | |
1989 | ||
1990 | fw.rodata_addr = bnx2_COM_b06FwRodataAddr; | |
1991 | fw.rodata_len = bnx2_COM_b06FwRodataLen; | |
1992 | fw.rodata_index = 0; | |
1993 | fw.rodata = bnx2_COM_b06FwRodata; | |
1994 | ||
1995 | load_cpu_fw(bp, &cpu_reg, &fw); | |
1996 | ||
1997 | } | |
1998 | ||
1999 | static int | |
2000 | bnx2_set_power_state(struct bnx2 *bp, int state) | |
2001 | { | |
2002 | u16 pmcsr; | |
2003 | ||
2004 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
2005 | ||
2006 | switch (state) { | |
2007 | case 0: { | |
2008 | u32 val; | |
2009 | ||
2010 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, | |
2011 | (pmcsr & ~PCI_PM_CTRL_STATE_MASK) | | |
2012 | PCI_PM_CTRL_PME_STATUS); | |
2013 | ||
2014 | if (pmcsr & PCI_PM_CTRL_STATE_MASK) | |
2015 | /* delay required during transition out of D3hot */ | |
2016 | msleep(20); | |
2017 | ||
2018 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
2019 | val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; | |
2020 | val &= ~BNX2_EMAC_MODE_MPKT; | |
2021 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
2022 | ||
2023 | val = REG_RD(bp, BNX2_RPM_CONFIG); | |
2024 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | |
2025 | REG_WR(bp, BNX2_RPM_CONFIG, val); | |
2026 | break; | |
2027 | } | |
2028 | case 3: { | |
2029 | int i; | |
2030 | u32 val, wol_msg; | |
2031 | ||
2032 | if (bp->wol) { | |
2033 | u32 advertising; | |
2034 | u8 autoneg; | |
2035 | ||
2036 | autoneg = bp->autoneg; | |
2037 | advertising = bp->advertising; | |
2038 | ||
2039 | bp->autoneg = AUTONEG_SPEED; | |
2040 | bp->advertising = ADVERTISED_10baseT_Half | | |
2041 | ADVERTISED_10baseT_Full | | |
2042 | ADVERTISED_100baseT_Half | | |
2043 | ADVERTISED_100baseT_Full | | |
2044 | ADVERTISED_Autoneg; | |
2045 | ||
2046 | bnx2_setup_copper_phy(bp); | |
2047 | ||
2048 | bp->autoneg = autoneg; | |
2049 | bp->advertising = advertising; | |
2050 | ||
2051 | bnx2_set_mac_addr(bp); | |
2052 | ||
2053 | val = REG_RD(bp, BNX2_EMAC_MODE); | |
2054 | ||
2055 | /* Enable port mode. */ | |
2056 | val &= ~BNX2_EMAC_MODE_PORT; | |
2057 | val |= BNX2_EMAC_MODE_PORT_MII | | |
2058 | BNX2_EMAC_MODE_MPKT_RCVD | | |
2059 | BNX2_EMAC_MODE_ACPI_RCVD | | |
2060 | BNX2_EMAC_MODE_FORCE_LINK | | |
2061 | BNX2_EMAC_MODE_MPKT; | |
2062 | ||
2063 | REG_WR(bp, BNX2_EMAC_MODE, val); | |
2064 | ||
2065 | /* receive all multicast */ | |
2066 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
2067 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
2068 | 0xffffffff); | |
2069 | } | |
2070 | REG_WR(bp, BNX2_EMAC_RX_MODE, | |
2071 | BNX2_EMAC_RX_MODE_SORT_MODE); | |
2072 | ||
2073 | val = 1 | BNX2_RPM_SORT_USER0_BC_EN | | |
2074 | BNX2_RPM_SORT_USER0_MC_EN; | |
2075 | REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | |
2076 | REG_WR(bp, BNX2_RPM_SORT_USER0, val); | |
2077 | REG_WR(bp, BNX2_RPM_SORT_USER0, val | | |
2078 | BNX2_RPM_SORT_USER0_ENA); | |
2079 | ||
2080 | /* Need to enable EMAC and RPM for WOL. */ | |
2081 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
2082 | BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | | |
2083 | BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | | |
2084 | BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); | |
2085 | ||
2086 | val = REG_RD(bp, BNX2_RPM_CONFIG); | |
2087 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | |
2088 | REG_WR(bp, BNX2_RPM_CONFIG, val); | |
2089 | ||
2090 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
2091 | } | |
2092 | else { | |
2093 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
2094 | } | |
2095 | ||
2096 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg); | |
2097 | ||
2098 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
2099 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || | |
2100 | (CHIP_ID(bp) == CHIP_ID_5706_A1)) { | |
2101 | ||
2102 | if (bp->wol) | |
2103 | pmcsr |= 3; | |
2104 | } | |
2105 | else { | |
2106 | pmcsr |= 3; | |
2107 | } | |
2108 | if (bp->wol) { | |
2109 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
2110 | } | |
2111 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, | |
2112 | pmcsr); | |
2113 | ||
2114 | /* No more memory access after this point until | |
2115 | * device is brought back to D0. | |
2116 | */ | |
2117 | udelay(50); | |
2118 | break; | |
2119 | } | |
2120 | default: | |
2121 | return -EINVAL; | |
2122 | } | |
2123 | return 0; | |
2124 | } | |
2125 | ||
2126 | static int | |
2127 | bnx2_acquire_nvram_lock(struct bnx2 *bp) | |
2128 | { | |
2129 | u32 val; | |
2130 | int j; | |
2131 | ||
2132 | /* Request access to the flash interface. */ | |
2133 | REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); | |
2134 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
2135 | val = REG_RD(bp, BNX2_NVM_SW_ARB); | |
2136 | if (val & BNX2_NVM_SW_ARB_ARB_ARB2) | |
2137 | break; | |
2138 | ||
2139 | udelay(5); | |
2140 | } | |
2141 | ||
2142 | if (j >= NVRAM_TIMEOUT_COUNT) | |
2143 | return -EBUSY; | |
2144 | ||
2145 | return 0; | |
2146 | } | |
2147 | ||
2148 | static int | |
2149 | bnx2_release_nvram_lock(struct bnx2 *bp) | |
2150 | { | |
2151 | int j; | |
2152 | u32 val; | |
2153 | ||
2154 | /* Relinquish nvram interface. */ | |
2155 | REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); | |
2156 | ||
2157 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
2158 | val = REG_RD(bp, BNX2_NVM_SW_ARB); | |
2159 | if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) | |
2160 | break; | |
2161 | ||
2162 | udelay(5); | |
2163 | } | |
2164 | ||
2165 | if (j >= NVRAM_TIMEOUT_COUNT) | |
2166 | return -EBUSY; | |
2167 | ||
2168 | return 0; | |
2169 | } | |
2170 | ||
2171 | ||
2172 | static int | |
2173 | bnx2_enable_nvram_write(struct bnx2 *bp) | |
2174 | { | |
2175 | u32 val; | |
2176 | ||
2177 | val = REG_RD(bp, BNX2_MISC_CFG); | |
2178 | REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); | |
2179 | ||
2180 | if (!bp->flash_info->buffered) { | |
2181 | int j; | |
2182 | ||
2183 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
2184 | REG_WR(bp, BNX2_NVM_COMMAND, | |
2185 | BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); | |
2186 | ||
2187 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
2188 | udelay(5); | |
2189 | ||
2190 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
2191 | if (val & BNX2_NVM_COMMAND_DONE) | |
2192 | break; | |
2193 | } | |
2194 | ||
2195 | if (j >= NVRAM_TIMEOUT_COUNT) | |
2196 | return -EBUSY; | |
2197 | } | |
2198 | return 0; | |
2199 | } | |
2200 | ||
2201 | static void | |
2202 | bnx2_disable_nvram_write(struct bnx2 *bp) | |
2203 | { | |
2204 | u32 val; | |
2205 | ||
2206 | val = REG_RD(bp, BNX2_MISC_CFG); | |
2207 | REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); | |
2208 | } | |
2209 | ||
2210 | ||
2211 | static void | |
2212 | bnx2_enable_nvram_access(struct bnx2 *bp) | |
2213 | { | |
2214 | u32 val; | |
2215 | ||
2216 | val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); | |
2217 | /* Enable both bits, even on read. */ | |
2218 | REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, | |
2219 | val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); | |
2220 | } | |
2221 | ||
2222 | static void | |
2223 | bnx2_disable_nvram_access(struct bnx2 *bp) | |
2224 | { | |
2225 | u32 val; | |
2226 | ||
2227 | val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); | |
2228 | /* Disable both bits, even after read. */ | |
2229 | REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, | |
2230 | val & ~(BNX2_NVM_ACCESS_ENABLE_EN | | |
2231 | BNX2_NVM_ACCESS_ENABLE_WR_EN)); | |
2232 | } | |
2233 | ||
2234 | static int | |
2235 | bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) | |
2236 | { | |
2237 | u32 cmd; | |
2238 | int j; | |
2239 | ||
2240 | if (bp->flash_info->buffered) | |
2241 | /* Buffered flash, no erase needed */ | |
2242 | return 0; | |
2243 | ||
2244 | /* Build an erase command */ | |
2245 | cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | | |
2246 | BNX2_NVM_COMMAND_DOIT; | |
2247 | ||
2248 | /* Need to clear DONE bit separately. */ | |
2249 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
2250 | ||
2251 | /* Address of the NVRAM to read from. */ | |
2252 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
2253 | ||
2254 | /* Issue an erase command. */ | |
2255 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
2256 | ||
2257 | /* Wait for completion. */ | |
2258 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
2259 | u32 val; | |
2260 | ||
2261 | udelay(5); | |
2262 | ||
2263 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
2264 | if (val & BNX2_NVM_COMMAND_DONE) | |
2265 | break; | |
2266 | } | |
2267 | ||
2268 | if (j >= NVRAM_TIMEOUT_COUNT) | |
2269 | return -EBUSY; | |
2270 | ||
2271 | return 0; | |
2272 | } | |
2273 | ||
2274 | static int | |
2275 | bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) | |
2276 | { | |
2277 | u32 cmd; | |
2278 | int j; | |
2279 | ||
2280 | /* Build the command word. */ | |
2281 | cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; | |
2282 | ||
2283 | /* Calculate an offset of a buffered flash. */ | |
2284 | if (bp->flash_info->buffered) { | |
2285 | offset = ((offset / bp->flash_info->page_size) << | |
2286 | bp->flash_info->page_bits) + | |
2287 | (offset % bp->flash_info->page_size); | |
2288 | } | |
2289 | ||
2290 | /* Need to clear DONE bit separately. */ | |
2291 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
2292 | ||
2293 | /* Address of the NVRAM to read from. */ | |
2294 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
2295 | ||
2296 | /* Issue a read command. */ | |
2297 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
2298 | ||
2299 | /* Wait for completion. */ | |
2300 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
2301 | u32 val; | |
2302 | ||
2303 | udelay(5); | |
2304 | ||
2305 | val = REG_RD(bp, BNX2_NVM_COMMAND); | |
2306 | if (val & BNX2_NVM_COMMAND_DONE) { | |
2307 | val = REG_RD(bp, BNX2_NVM_READ); | |
2308 | ||
2309 | val = be32_to_cpu(val); | |
2310 | memcpy(ret_val, &val, 4); | |
2311 | break; | |
2312 | } | |
2313 | } | |
2314 | if (j >= NVRAM_TIMEOUT_COUNT) | |
2315 | return -EBUSY; | |
2316 | ||
2317 | return 0; | |
2318 | } | |
2319 | ||
2320 | ||
2321 | static int | |
2322 | bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) | |
2323 | { | |
2324 | u32 cmd, val32; | |
2325 | int j; | |
2326 | ||
2327 | /* Build the command word. */ | |
2328 | cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; | |
2329 | ||
2330 | /* Calculate an offset of a buffered flash. */ | |
2331 | if (bp->flash_info->buffered) { | |
2332 | offset = ((offset / bp->flash_info->page_size) << | |
2333 | bp->flash_info->page_bits) + | |
2334 | (offset % bp->flash_info->page_size); | |
2335 | } | |
2336 | ||
2337 | /* Need to clear DONE bit separately. */ | |
2338 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | |
2339 | ||
2340 | memcpy(&val32, val, 4); | |
2341 | val32 = cpu_to_be32(val32); | |
2342 | ||
2343 | /* Write the data. */ | |
2344 | REG_WR(bp, BNX2_NVM_WRITE, val32); | |
2345 | ||
2346 | /* Address of the NVRAM to write to. */ | |
2347 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | |
2348 | ||
2349 | /* Issue the write command. */ | |
2350 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | |
2351 | ||
2352 | /* Wait for completion. */ | |
2353 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
2354 | udelay(5); | |
2355 | ||
2356 | if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) | |
2357 | break; | |
2358 | } | |
2359 | if (j >= NVRAM_TIMEOUT_COUNT) | |
2360 | return -EBUSY; | |
2361 | ||
2362 | return 0; | |
2363 | } | |
2364 | ||
2365 | static int | |
2366 | bnx2_init_nvram(struct bnx2 *bp) | |
2367 | { | |
2368 | u32 val; | |
2369 | int j, entry_count, rc; | |
2370 | struct flash_spec *flash; | |
2371 | ||
2372 | /* Determine the selected interface. */ | |
2373 | val = REG_RD(bp, BNX2_NVM_CFG1); | |
2374 | ||
2375 | entry_count = sizeof(flash_table) / sizeof(struct flash_spec); | |
2376 | ||
2377 | rc = 0; | |
2378 | if (val & 0x40000000) { | |
2379 | ||
2380 | /* Flash interface has been reconfigured */ | |
2381 | for (j = 0, flash = &flash_table[0]; j < entry_count; | |
2382 | j++, flash++) { | |
2383 | ||
2384 | if (val == flash->config1) { | |
2385 | bp->flash_info = flash; | |
2386 | break; | |
2387 | } | |
2388 | } | |
2389 | } | |
2390 | else { | |
2391 | /* Not yet been reconfigured */ | |
2392 | ||
2393 | for (j = 0, flash = &flash_table[0]; j < entry_count; | |
2394 | j++, flash++) { | |
2395 | ||
2396 | if ((val & FLASH_STRAP_MASK) == flash->strapping) { | |
2397 | bp->flash_info = flash; | |
2398 | ||
2399 | /* Request access to the flash interface. */ | |
2400 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
2401 | return rc; | |
2402 | ||
2403 | /* Enable access to flash interface */ | |
2404 | bnx2_enable_nvram_access(bp); | |
2405 | ||
2406 | /* Reconfigure the flash interface */ | |
2407 | REG_WR(bp, BNX2_NVM_CFG1, flash->config1); | |
2408 | REG_WR(bp, BNX2_NVM_CFG2, flash->config2); | |
2409 | REG_WR(bp, BNX2_NVM_CFG3, flash->config3); | |
2410 | REG_WR(bp, BNX2_NVM_WRITE1, flash->write1); | |
2411 | ||
2412 | /* Disable access to flash interface */ | |
2413 | bnx2_disable_nvram_access(bp); | |
2414 | bnx2_release_nvram_lock(bp); | |
2415 | ||
2416 | break; | |
2417 | } | |
2418 | } | |
2419 | } /* if (val & 0x40000000) */ | |
2420 | ||
2421 | if (j == entry_count) { | |
2422 | bp->flash_info = NULL; | |
2423 | printk(KERN_ALERT "Unknown flash/EEPROM type.\n"); | |
2424 | rc = -ENODEV; | |
2425 | } | |
2426 | ||
2427 | return rc; | |
2428 | } | |
2429 | ||
2430 | static int | |
2431 | bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, | |
2432 | int buf_size) | |
2433 | { | |
2434 | int rc = 0; | |
2435 | u32 cmd_flags, offset32, len32, extra; | |
2436 | ||
2437 | if (buf_size == 0) | |
2438 | return 0; | |
2439 | ||
2440 | /* Request access to the flash interface. */ | |
2441 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
2442 | return rc; | |
2443 | ||
2444 | /* Enable access to flash interface */ | |
2445 | bnx2_enable_nvram_access(bp); | |
2446 | ||
2447 | len32 = buf_size; | |
2448 | offset32 = offset; | |
2449 | extra = 0; | |
2450 | ||
2451 | cmd_flags = 0; | |
2452 | ||
2453 | if (offset32 & 3) { | |
2454 | u8 buf[4]; | |
2455 | u32 pre_len; | |
2456 | ||
2457 | offset32 &= ~3; | |
2458 | pre_len = 4 - (offset & 3); | |
2459 | ||
2460 | if (pre_len >= len32) { | |
2461 | pre_len = len32; | |
2462 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
2463 | BNX2_NVM_COMMAND_LAST; | |
2464 | } | |
2465 | else { | |
2466 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
2467 | } | |
2468 | ||
2469 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
2470 | ||
2471 | if (rc) | |
2472 | return rc; | |
2473 | ||
2474 | memcpy(ret_buf, buf + (offset & 3), pre_len); | |
2475 | ||
2476 | offset32 += 4; | |
2477 | ret_buf += pre_len; | |
2478 | len32 -= pre_len; | |
2479 | } | |
2480 | if (len32 & 3) { | |
2481 | extra = 4 - (len32 & 3); | |
2482 | len32 = (len32 + 4) & ~3; | |
2483 | } | |
2484 | ||
2485 | if (len32 == 4) { | |
2486 | u8 buf[4]; | |
2487 | ||
2488 | if (cmd_flags) | |
2489 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
2490 | else | |
2491 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
2492 | BNX2_NVM_COMMAND_LAST; | |
2493 | ||
2494 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
2495 | ||
2496 | memcpy(ret_buf, buf, 4 - extra); | |
2497 | } | |
2498 | else if (len32 > 0) { | |
2499 | u8 buf[4]; | |
2500 | ||
2501 | /* Read the first word. */ | |
2502 | if (cmd_flags) | |
2503 | cmd_flags = 0; | |
2504 | else | |
2505 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
2506 | ||
2507 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); | |
2508 | ||
2509 | /* Advance to the next dword. */ | |
2510 | offset32 += 4; | |
2511 | ret_buf += 4; | |
2512 | len32 -= 4; | |
2513 | ||
2514 | while (len32 > 4 && rc == 0) { | |
2515 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); | |
2516 | ||
2517 | /* Advance to the next dword. */ | |
2518 | offset32 += 4; | |
2519 | ret_buf += 4; | |
2520 | len32 -= 4; | |
2521 | } | |
2522 | ||
2523 | if (rc) | |
2524 | return rc; | |
2525 | ||
2526 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
2527 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
2528 | ||
2529 | memcpy(ret_buf, buf, 4 - extra); | |
2530 | } | |
2531 | ||
2532 | /* Disable access to flash interface */ | |
2533 | bnx2_disable_nvram_access(bp); | |
2534 | ||
2535 | bnx2_release_nvram_lock(bp); | |
2536 | ||
2537 | return rc; | |
2538 | } | |
2539 | ||
2540 | static int | |
2541 | bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, | |
2542 | int buf_size) | |
2543 | { | |
2544 | u32 written, offset32, len32; | |
2545 | u8 *buf, start[4], end[4]; | |
2546 | int rc = 0; | |
2547 | int align_start, align_end; | |
2548 | ||
2549 | buf = data_buf; | |
2550 | offset32 = offset; | |
2551 | len32 = buf_size; | |
2552 | align_start = align_end = 0; | |
2553 | ||
2554 | if ((align_start = (offset32 & 3))) { | |
2555 | offset32 &= ~3; | |
2556 | len32 += align_start; | |
2557 | if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) | |
2558 | return rc; | |
2559 | } | |
2560 | ||
2561 | if (len32 & 3) { | |
2562 | if ((len32 > 4) || !align_start) { | |
2563 | align_end = 4 - (len32 & 3); | |
2564 | len32 += align_end; | |
2565 | if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, | |
2566 | end, 4))) { | |
2567 | return rc; | |
2568 | } | |
2569 | } | |
2570 | } | |
2571 | ||
2572 | if (align_start || align_end) { | |
2573 | buf = kmalloc(len32, GFP_KERNEL); | |
2574 | if (buf == 0) | |
2575 | return -ENOMEM; | |
2576 | if (align_start) { | |
2577 | memcpy(buf, start, 4); | |
2578 | } | |
2579 | if (align_end) { | |
2580 | memcpy(buf + len32 - 4, end, 4); | |
2581 | } | |
2582 | memcpy(buf + align_start, data_buf, buf_size); | |
2583 | } | |
2584 | ||
2585 | written = 0; | |
2586 | while ((written < len32) && (rc == 0)) { | |
2587 | u32 page_start, page_end, data_start, data_end; | |
2588 | u32 addr, cmd_flags; | |
2589 | int i; | |
2590 | u8 flash_buffer[264]; | |
2591 | ||
2592 | /* Find the page_start addr */ | |
2593 | page_start = offset32 + written; | |
2594 | page_start -= (page_start % bp->flash_info->page_size); | |
2595 | /* Find the page_end addr */ | |
2596 | page_end = page_start + bp->flash_info->page_size; | |
2597 | /* Find the data_start addr */ | |
2598 | data_start = (written == 0) ? offset32 : page_start; | |
2599 | /* Find the data_end addr */ | |
2600 | data_end = (page_end > offset32 + len32) ? | |
2601 | (offset32 + len32) : page_end; | |
2602 | ||
2603 | /* Request access to the flash interface. */ | |
2604 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
2605 | goto nvram_write_end; | |
2606 | ||
2607 | /* Enable access to flash interface */ | |
2608 | bnx2_enable_nvram_access(bp); | |
2609 | ||
2610 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
2611 | if (bp->flash_info->buffered == 0) { | |
2612 | int j; | |
2613 | ||
2614 | /* Read the whole page into the buffer | |
2615 | * (non-buffer flash only) */ | |
2616 | for (j = 0; j < bp->flash_info->page_size; j += 4) { | |
2617 | if (j == (bp->flash_info->page_size - 4)) { | |
2618 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
2619 | } | |
2620 | rc = bnx2_nvram_read_dword(bp, | |
2621 | page_start + j, | |
2622 | &flash_buffer[j], | |
2623 | cmd_flags); | |
2624 | ||
2625 | if (rc) | |
2626 | goto nvram_write_end; | |
2627 | ||
2628 | cmd_flags = 0; | |
2629 | } | |
2630 | } | |
2631 | ||
2632 | /* Enable writes to flash interface (unlock write-protect) */ | |
2633 | if ((rc = bnx2_enable_nvram_write(bp)) != 0) | |
2634 | goto nvram_write_end; | |
2635 | ||
2636 | /* Erase the page */ | |
2637 | if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) | |
2638 | goto nvram_write_end; | |
2639 | ||
2640 | /* Re-enable the write again for the actual write */ | |
2641 | bnx2_enable_nvram_write(bp); | |
2642 | ||
2643 | /* Loop to write back the buffer data from page_start to | |
2644 | * data_start */ | |
2645 | i = 0; | |
2646 | if (bp->flash_info->buffered == 0) { | |
2647 | for (addr = page_start; addr < data_start; | |
2648 | addr += 4, i += 4) { | |
2649 | ||
2650 | rc = bnx2_nvram_write_dword(bp, addr, | |
2651 | &flash_buffer[i], cmd_flags); | |
2652 | ||
2653 | if (rc != 0) | |
2654 | goto nvram_write_end; | |
2655 | ||
2656 | cmd_flags = 0; | |
2657 | } | |
2658 | } | |
2659 | ||
2660 | /* Loop to write the new data from data_start to data_end */ | |
2661 | for (addr = data_start; addr < data_end; addr += 4, i++) { | |
2662 | if ((addr == page_end - 4) || | |
2663 | ((bp->flash_info->buffered) && | |
2664 | (addr == data_end - 4))) { | |
2665 | ||
2666 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
2667 | } | |
2668 | rc = bnx2_nvram_write_dword(bp, addr, buf, | |
2669 | cmd_flags); | |
2670 | ||
2671 | if (rc != 0) | |
2672 | goto nvram_write_end; | |
2673 | ||
2674 | cmd_flags = 0; | |
2675 | buf += 4; | |
2676 | } | |
2677 | ||
2678 | /* Loop to write back the buffer data from data_end | |
2679 | * to page_end */ | |
2680 | if (bp->flash_info->buffered == 0) { | |
2681 | for (addr = data_end; addr < page_end; | |
2682 | addr += 4, i += 4) { | |
2683 | ||
2684 | if (addr == page_end-4) { | |
2685 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
2686 | } | |
2687 | rc = bnx2_nvram_write_dword(bp, addr, | |
2688 | &flash_buffer[i], cmd_flags); | |
2689 | ||
2690 | if (rc != 0) | |
2691 | goto nvram_write_end; | |
2692 | ||
2693 | cmd_flags = 0; | |
2694 | } | |
2695 | } | |
2696 | ||
2697 | /* Disable writes to flash interface (lock write-protect) */ | |
2698 | bnx2_disable_nvram_write(bp); | |
2699 | ||
2700 | /* Disable access to flash interface */ | |
2701 | bnx2_disable_nvram_access(bp); | |
2702 | bnx2_release_nvram_lock(bp); | |
2703 | ||
2704 | /* Increment written */ | |
2705 | written += data_end - data_start; | |
2706 | } | |
2707 | ||
2708 | nvram_write_end: | |
2709 | if (align_start || align_end) | |
2710 | kfree(buf); | |
2711 | return rc; | |
2712 | } | |
2713 | ||
2714 | static int | |
2715 | bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | |
2716 | { | |
2717 | u32 val; | |
2718 | int i, rc = 0; | |
2719 | ||
2720 | /* Wait for the current PCI transaction to complete before | |
2721 | * issuing a reset. */ | |
2722 | REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, | |
2723 | BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | | |
2724 | BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | | |
2725 | BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | | |
2726 | BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); | |
2727 | val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); | |
2728 | udelay(5); | |
2729 | ||
2730 | /* Deposit a driver reset signature so the firmware knows that | |
2731 | * this is a soft reset. */ | |
2732 | REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE, | |
2733 | BNX2_DRV_RESET_SIGNATURE_MAGIC); | |
2734 | ||
2735 | bp->fw_timed_out = 0; | |
2736 | ||
2737 | /* Wait for the firmware to tell us it is ok to issue a reset. */ | |
2738 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code); | |
2739 | ||
2740 | /* Do a dummy read to force the chip to complete all current transaction | |
2741 | * before we issue a reset. */ | |
2742 | val = REG_RD(bp, BNX2_MISC_ID); | |
2743 | ||
2744 | val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
2745 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
2746 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
2747 | ||
2748 | /* Chip reset. */ | |
2749 | REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); | |
2750 | ||
2751 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || | |
2752 | (CHIP_ID(bp) == CHIP_ID_5706_A1)) | |
2753 | msleep(15); | |
2754 | ||
2755 | /* Reset takes approximate 30 usec */ | |
2756 | for (i = 0; i < 10; i++) { | |
2757 | val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); | |
2758 | if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
2759 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { | |
2760 | break; | |
2761 | } | |
2762 | udelay(10); | |
2763 | } | |
2764 | ||
2765 | if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
2766 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { | |
2767 | printk(KERN_ERR PFX "Chip reset did not complete\n"); | |
2768 | return -EBUSY; | |
2769 | } | |
2770 | ||
2771 | /* Make sure byte swapping is properly configured. */ | |
2772 | val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); | |
2773 | if (val != 0x01020304) { | |
2774 | printk(KERN_ERR PFX "Chip not in correct endian mode\n"); | |
2775 | return -ENODEV; | |
2776 | } | |
2777 | ||
2778 | bp->fw_timed_out = 0; | |
2779 | ||
2780 | /* Wait for the firmware to finish its initialization. */ | |
2781 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code); | |
2782 | ||
2783 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
2784 | /* Adjust the voltage regular to two steps lower. The default | |
2785 | * of this register is 0x0000000e. */ | |
2786 | REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); | |
2787 | ||
2788 | /* Remove bad rbuf memory from the free pool. */ | |
2789 | rc = bnx2_alloc_bad_rbuf(bp); | |
2790 | } | |
2791 | ||
2792 | return rc; | |
2793 | } | |
2794 | ||
2795 | static int | |
2796 | bnx2_init_chip(struct bnx2 *bp) | |
2797 | { | |
2798 | u32 val; | |
2799 | ||
2800 | /* Make sure the interrupt is not active. */ | |
2801 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
2802 | ||
2803 | val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | | |
2804 | BNX2_DMA_CONFIG_DATA_WORD_SWAP | | |
2805 | #ifdef __BIG_ENDIAN | |
2806 | BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | | |
2807 | #endif | |
2808 | BNX2_DMA_CONFIG_CNTL_WORD_SWAP | | |
2809 | DMA_READ_CHANS << 12 | | |
2810 | DMA_WRITE_CHANS << 16; | |
2811 | ||
2812 | val |= (0x2 << 20) | (1 << 11); | |
2813 | ||
2814 | if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133)) | |
2815 | val |= (1 << 23); | |
2816 | ||
2817 | if ((CHIP_NUM(bp) == CHIP_NUM_5706) && | |
2818 | (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG)) | |
2819 | val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; | |
2820 | ||
2821 | REG_WR(bp, BNX2_DMA_CONFIG, val); | |
2822 | ||
2823 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
2824 | val = REG_RD(bp, BNX2_TDMA_CONFIG); | |
2825 | val |= BNX2_TDMA_CONFIG_ONE_DMA; | |
2826 | REG_WR(bp, BNX2_TDMA_CONFIG, val); | |
2827 | } | |
2828 | ||
2829 | if (bp->flags & PCIX_FLAG) { | |
2830 | u16 val16; | |
2831 | ||
2832 | pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
2833 | &val16); | |
2834 | pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
2835 | val16 & ~PCI_X_CMD_ERO); | |
2836 | } | |
2837 | ||
2838 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
2839 | BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | | |
2840 | BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | | |
2841 | BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); | |
2842 | ||
2843 | /* Initialize context mapping and zero out the quick contexts. The | |
2844 | * context block must have already been enabled. */ | |
2845 | bnx2_init_context(bp); | |
2846 | ||
2847 | bnx2_init_cpus(bp); | |
2848 | bnx2_init_nvram(bp); | |
2849 | ||
2850 | bnx2_set_mac_addr(bp); | |
2851 | ||
2852 | val = REG_RD(bp, BNX2_MQ_CONFIG); | |
2853 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; | |
2854 | val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; | |
2855 | REG_WR(bp, BNX2_MQ_CONFIG, val); | |
2856 | ||
2857 | val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); | |
2858 | REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); | |
2859 | REG_WR(bp, BNX2_MQ_KNL_WIND_END, val); | |
2860 | ||
2861 | val = (BCM_PAGE_BITS - 8) << 24; | |
2862 | REG_WR(bp, BNX2_RV2P_CONFIG, val); | |
2863 | ||
2864 | /* Configure page size. */ | |
2865 | val = REG_RD(bp, BNX2_TBDR_CONFIG); | |
2866 | val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; | |
2867 | val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; | |
2868 | REG_WR(bp, BNX2_TBDR_CONFIG, val); | |
2869 | ||
2870 | val = bp->mac_addr[0] + | |
2871 | (bp->mac_addr[1] << 8) + | |
2872 | (bp->mac_addr[2] << 16) + | |
2873 | bp->mac_addr[3] + | |
2874 | (bp->mac_addr[4] << 8) + | |
2875 | (bp->mac_addr[5] << 16); | |
2876 | REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); | |
2877 | ||
2878 | /* Program the MTU. Also include 4 bytes for CRC32. */ | |
2879 | val = bp->dev->mtu + ETH_HLEN + 4; | |
2880 | if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) | |
2881 | val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; | |
2882 | REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); | |
2883 | ||
2884 | bp->last_status_idx = 0; | |
2885 | bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; | |
2886 | ||
2887 | /* Set up how to generate a link change interrupt. */ | |
2888 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); | |
2889 | ||
2890 | REG_WR(bp, BNX2_HC_STATUS_ADDR_L, | |
2891 | (u64) bp->status_blk_mapping & 0xffffffff); | |
2892 | REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); | |
2893 | ||
2894 | REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L, | |
2895 | (u64) bp->stats_blk_mapping & 0xffffffff); | |
2896 | REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, | |
2897 | (u64) bp->stats_blk_mapping >> 32); | |
2898 | ||
2899 | REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, | |
2900 | (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); | |
2901 | ||
2902 | REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, | |
2903 | (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); | |
2904 | ||
2905 | REG_WR(bp, BNX2_HC_COMP_PROD_TRIP, | |
2906 | (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); | |
2907 | ||
2908 | REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); | |
2909 | ||
2910 | REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); | |
2911 | ||
2912 | REG_WR(bp, BNX2_HC_COM_TICKS, | |
2913 | (bp->com_ticks_int << 16) | bp->com_ticks); | |
2914 | ||
2915 | REG_WR(bp, BNX2_HC_CMD_TICKS, | |
2916 | (bp->cmd_ticks_int << 16) | bp->cmd_ticks); | |
2917 | ||
2918 | REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00); | |
2919 | REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ | |
2920 | ||
2921 | if (CHIP_ID(bp) == CHIP_ID_5706_A1) | |
2922 | REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS); | |
2923 | else { | |
2924 | REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE | | |
2925 | BNX2_HC_CONFIG_TX_TMR_MODE | | |
2926 | BNX2_HC_CONFIG_COLLECT_STATS); | |
2927 | } | |
2928 | ||
2929 | /* Clear internal stats counters. */ | |
2930 | REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); | |
2931 | ||
2932 | REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); | |
2933 | ||
2934 | /* Initialize the receive filter. */ | |
2935 | bnx2_set_rx_mode(bp->dev); | |
2936 | ||
2937 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET); | |
2938 | ||
2939 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff); | |
2940 | REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); | |
2941 | ||
2942 | udelay(20); | |
2943 | ||
2944 | return 0; | |
2945 | } | |
2946 | ||
2947 | ||
2948 | static void | |
2949 | bnx2_init_tx_ring(struct bnx2 *bp) | |
2950 | { | |
2951 | struct tx_bd *txbd; | |
2952 | u32 val; | |
2953 | ||
2954 | txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT]; | |
2955 | ||
2956 | txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32; | |
2957 | txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff; | |
2958 | ||
2959 | bp->tx_prod = 0; | |
2960 | bp->tx_cons = 0; | |
2961 | bp->tx_prod_bseq = 0; | |
2962 | atomic_set(&bp->tx_avail_bd, bp->tx_ring_size); | |
2963 | ||
2964 | val = BNX2_L2CTX_TYPE_TYPE_L2; | |
2965 | val |= BNX2_L2CTX_TYPE_SIZE_L2; | |
2966 | CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val); | |
2967 | ||
2968 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2; | |
2969 | val |= 8 << 16; | |
2970 | CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val); | |
2971 | ||
2972 | val = (u64) bp->tx_desc_mapping >> 32; | |
2973 | CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val); | |
2974 | ||
2975 | val = (u64) bp->tx_desc_mapping & 0xffffffff; | |
2976 | CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val); | |
2977 | } | |
2978 | ||
2979 | static void | |
2980 | bnx2_init_rx_ring(struct bnx2 *bp) | |
2981 | { | |
2982 | struct rx_bd *rxbd; | |
2983 | int i; | |
2984 | u16 prod, ring_prod; | |
2985 | u32 val; | |
2986 | ||
2987 | /* 8 for CRC and VLAN */ | |
2988 | bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8; | |
2989 | /* 8 for alignment */ | |
2990 | bp->rx_buf_size = bp->rx_buf_use_size + 8; | |
2991 | ||
2992 | ring_prod = prod = bp->rx_prod = 0; | |
2993 | bp->rx_cons = 0; | |
2994 | bp->rx_prod_bseq = 0; | |
2995 | ||
2996 | rxbd = &bp->rx_desc_ring[0]; | |
2997 | for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) { | |
2998 | rxbd->rx_bd_len = bp->rx_buf_use_size; | |
2999 | rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; | |
3000 | } | |
3001 | ||
3002 | rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32; | |
3003 | rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff; | |
3004 | ||
3005 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; | |
3006 | val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; | |
3007 | val |= 0x02 << 8; | |
3008 | CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val); | |
3009 | ||
3010 | val = (u64) bp->rx_desc_mapping >> 32; | |
3011 | CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val); | |
3012 | ||
3013 | val = (u64) bp->rx_desc_mapping & 0xffffffff; | |
3014 | CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val); | |
3015 | ||
3016 | for ( ;ring_prod < bp->rx_ring_size; ) { | |
3017 | if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) { | |
3018 | break; | |
3019 | } | |
3020 | prod = NEXT_RX_BD(prod); | |
3021 | ring_prod = RX_RING_IDX(prod); | |
3022 | } | |
3023 | bp->rx_prod = prod; | |
3024 | ||
3025 | REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod); | |
3026 | ||
3027 | REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq); | |
3028 | } | |
3029 | ||
3030 | static void | |
3031 | bnx2_free_tx_skbs(struct bnx2 *bp) | |
3032 | { | |
3033 | int i; | |
3034 | ||
3035 | if (bp->tx_buf_ring == NULL) | |
3036 | return; | |
3037 | ||
3038 | for (i = 0; i < TX_DESC_CNT; ) { | |
3039 | struct sw_bd *tx_buf = &bp->tx_buf_ring[i]; | |
3040 | struct sk_buff *skb = tx_buf->skb; | |
3041 | int j, last; | |
3042 | ||
3043 | if (skb == NULL) { | |
3044 | i++; | |
3045 | continue; | |
3046 | } | |
3047 | ||
3048 | pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), | |
3049 | skb_headlen(skb), PCI_DMA_TODEVICE); | |
3050 | ||
3051 | tx_buf->skb = NULL; | |
3052 | ||
3053 | last = skb_shinfo(skb)->nr_frags; | |
3054 | for (j = 0; j < last; j++) { | |
3055 | tx_buf = &bp->tx_buf_ring[i + j + 1]; | |
3056 | pci_unmap_page(bp->pdev, | |
3057 | pci_unmap_addr(tx_buf, mapping), | |
3058 | skb_shinfo(skb)->frags[j].size, | |
3059 | PCI_DMA_TODEVICE); | |
3060 | } | |
3061 | dev_kfree_skb_any(skb); | |
3062 | i += j + 1; | |
3063 | } | |
3064 | ||
3065 | } | |
3066 | ||
3067 | static void | |
3068 | bnx2_free_rx_skbs(struct bnx2 *bp) | |
3069 | { | |
3070 | int i; | |
3071 | ||
3072 | if (bp->rx_buf_ring == NULL) | |
3073 | return; | |
3074 | ||
3075 | for (i = 0; i < RX_DESC_CNT; i++) { | |
3076 | struct sw_bd *rx_buf = &bp->rx_buf_ring[i]; | |
3077 | struct sk_buff *skb = rx_buf->skb; | |
3078 | ||
3079 | if (skb == 0) | |
3080 | continue; | |
3081 | ||
3082 | pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping), | |
3083 | bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); | |
3084 | ||
3085 | rx_buf->skb = NULL; | |
3086 | ||
3087 | dev_kfree_skb_any(skb); | |
3088 | } | |
3089 | } | |
3090 | ||
3091 | static void | |
3092 | bnx2_free_skbs(struct bnx2 *bp) | |
3093 | { | |
3094 | bnx2_free_tx_skbs(bp); | |
3095 | bnx2_free_rx_skbs(bp); | |
3096 | } | |
3097 | ||
3098 | static int | |
3099 | bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) | |
3100 | { | |
3101 | int rc; | |
3102 | ||
3103 | rc = bnx2_reset_chip(bp, reset_code); | |
3104 | bnx2_free_skbs(bp); | |
3105 | if (rc) | |
3106 | return rc; | |
3107 | ||
3108 | bnx2_init_chip(bp); | |
3109 | bnx2_init_tx_ring(bp); | |
3110 | bnx2_init_rx_ring(bp); | |
3111 | return 0; | |
3112 | } | |
3113 | ||
3114 | static int | |
3115 | bnx2_init_nic(struct bnx2 *bp) | |
3116 | { | |
3117 | int rc; | |
3118 | ||
3119 | if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) | |
3120 | return rc; | |
3121 | ||
3122 | bnx2_init_phy(bp); | |
3123 | bnx2_set_link(bp); | |
3124 | return 0; | |
3125 | } | |
3126 | ||
3127 | static int | |
3128 | bnx2_test_registers(struct bnx2 *bp) | |
3129 | { | |
3130 | int ret; | |
3131 | int i; | |
3132 | static struct { | |
3133 | u16 offset; | |
3134 | u16 flags; | |
3135 | u32 rw_mask; | |
3136 | u32 ro_mask; | |
3137 | } reg_tbl[] = { | |
3138 | { 0x006c, 0, 0x00000000, 0x0000003f }, | |
3139 | { 0x0090, 0, 0xffffffff, 0x00000000 }, | |
3140 | { 0x0094, 0, 0x00000000, 0x00000000 }, | |
3141 | ||
3142 | { 0x0404, 0, 0x00003f00, 0x00000000 }, | |
3143 | { 0x0418, 0, 0x00000000, 0xffffffff }, | |
3144 | { 0x041c, 0, 0x00000000, 0xffffffff }, | |
3145 | { 0x0420, 0, 0x00000000, 0x80ffffff }, | |
3146 | { 0x0424, 0, 0x00000000, 0x00000000 }, | |
3147 | { 0x0428, 0, 0x00000000, 0x00000001 }, | |
3148 | { 0x0450, 0, 0x00000000, 0x0000ffff }, | |
3149 | { 0x0454, 0, 0x00000000, 0xffffffff }, | |
3150 | { 0x0458, 0, 0x00000000, 0xffffffff }, | |
3151 | ||
3152 | { 0x0808, 0, 0x00000000, 0xffffffff }, | |
3153 | { 0x0854, 0, 0x00000000, 0xffffffff }, | |
3154 | { 0x0868, 0, 0x00000000, 0x77777777 }, | |
3155 | { 0x086c, 0, 0x00000000, 0x77777777 }, | |
3156 | { 0x0870, 0, 0x00000000, 0x77777777 }, | |
3157 | { 0x0874, 0, 0x00000000, 0x77777777 }, | |
3158 | ||
3159 | { 0x0c00, 0, 0x00000000, 0x00000001 }, | |
3160 | { 0x0c04, 0, 0x00000000, 0x03ff0001 }, | |
3161 | { 0x0c08, 0, 0x0f0ff073, 0x00000000 }, | |
3162 | { 0x0c0c, 0, 0x00ffffff, 0x00000000 }, | |
3163 | { 0x0c30, 0, 0x00000000, 0xffffffff }, | |
3164 | { 0x0c34, 0, 0x00000000, 0xffffffff }, | |
3165 | { 0x0c38, 0, 0x00000000, 0xffffffff }, | |
3166 | { 0x0c3c, 0, 0x00000000, 0xffffffff }, | |
3167 | { 0x0c40, 0, 0x00000000, 0xffffffff }, | |
3168 | { 0x0c44, 0, 0x00000000, 0xffffffff }, | |
3169 | { 0x0c48, 0, 0x00000000, 0x0007ffff }, | |
3170 | { 0x0c4c, 0, 0x00000000, 0xffffffff }, | |
3171 | { 0x0c50, 0, 0x00000000, 0xffffffff }, | |
3172 | { 0x0c54, 0, 0x00000000, 0xffffffff }, | |
3173 | { 0x0c58, 0, 0x00000000, 0xffffffff }, | |
3174 | { 0x0c5c, 0, 0x00000000, 0xffffffff }, | |
3175 | { 0x0c60, 0, 0x00000000, 0xffffffff }, | |
3176 | { 0x0c64, 0, 0x00000000, 0xffffffff }, | |
3177 | { 0x0c68, 0, 0x00000000, 0xffffffff }, | |
3178 | { 0x0c6c, 0, 0x00000000, 0xffffffff }, | |
3179 | { 0x0c70, 0, 0x00000000, 0xffffffff }, | |
3180 | { 0x0c74, 0, 0x00000000, 0xffffffff }, | |
3181 | { 0x0c78, 0, 0x00000000, 0xffffffff }, | |
3182 | { 0x0c7c, 0, 0x00000000, 0xffffffff }, | |
3183 | { 0x0c80, 0, 0x00000000, 0xffffffff }, | |
3184 | { 0x0c84, 0, 0x00000000, 0xffffffff }, | |
3185 | { 0x0c88, 0, 0x00000000, 0xffffffff }, | |
3186 | { 0x0c8c, 0, 0x00000000, 0xffffffff }, | |
3187 | { 0x0c90, 0, 0x00000000, 0xffffffff }, | |
3188 | { 0x0c94, 0, 0x00000000, 0xffffffff }, | |
3189 | { 0x0c98, 0, 0x00000000, 0xffffffff }, | |
3190 | { 0x0c9c, 0, 0x00000000, 0xffffffff }, | |
3191 | { 0x0ca0, 0, 0x00000000, 0xffffffff }, | |
3192 | { 0x0ca4, 0, 0x00000000, 0xffffffff }, | |
3193 | { 0x0ca8, 0, 0x00000000, 0x0007ffff }, | |
3194 | { 0x0cac, 0, 0x00000000, 0xffffffff }, | |
3195 | { 0x0cb0, 0, 0x00000000, 0xffffffff }, | |
3196 | { 0x0cb4, 0, 0x00000000, 0xffffffff }, | |
3197 | { 0x0cb8, 0, 0x00000000, 0xffffffff }, | |
3198 | { 0x0cbc, 0, 0x00000000, 0xffffffff }, | |
3199 | { 0x0cc0, 0, 0x00000000, 0xffffffff }, | |
3200 | { 0x0cc4, 0, 0x00000000, 0xffffffff }, | |
3201 | { 0x0cc8, 0, 0x00000000, 0xffffffff }, | |
3202 | { 0x0ccc, 0, 0x00000000, 0xffffffff }, | |
3203 | { 0x0cd0, 0, 0x00000000, 0xffffffff }, | |
3204 | { 0x0cd4, 0, 0x00000000, 0xffffffff }, | |
3205 | { 0x0cd8, 0, 0x00000000, 0xffffffff }, | |
3206 | { 0x0cdc, 0, 0x00000000, 0xffffffff }, | |
3207 | { 0x0ce0, 0, 0x00000000, 0xffffffff }, | |
3208 | { 0x0ce4, 0, 0x00000000, 0xffffffff }, | |
3209 | { 0x0ce8, 0, 0x00000000, 0xffffffff }, | |
3210 | { 0x0cec, 0, 0x00000000, 0xffffffff }, | |
3211 | { 0x0cf0, 0, 0x00000000, 0xffffffff }, | |
3212 | { 0x0cf4, 0, 0x00000000, 0xffffffff }, | |
3213 | { 0x0cf8, 0, 0x00000000, 0xffffffff }, | |
3214 | { 0x0cfc, 0, 0x00000000, 0xffffffff }, | |
3215 | { 0x0d00, 0, 0x00000000, 0xffffffff }, | |
3216 | { 0x0d04, 0, 0x00000000, 0xffffffff }, | |
3217 | ||
3218 | { 0x1000, 0, 0x00000000, 0x00000001 }, | |
3219 | { 0x1004, 0, 0x00000000, 0x000f0001 }, | |
3220 | { 0x1044, 0, 0x00000000, 0xffc003ff }, | |
3221 | { 0x1080, 0, 0x00000000, 0x0001ffff }, | |
3222 | { 0x1084, 0, 0x00000000, 0xffffffff }, | |
3223 | { 0x1088, 0, 0x00000000, 0xffffffff }, | |
3224 | { 0x108c, 0, 0x00000000, 0xffffffff }, | |
3225 | { 0x1090, 0, 0x00000000, 0xffffffff }, | |
3226 | { 0x1094, 0, 0x00000000, 0xffffffff }, | |
3227 | { 0x1098, 0, 0x00000000, 0xffffffff }, | |
3228 | { 0x109c, 0, 0x00000000, 0xffffffff }, | |
3229 | { 0x10a0, 0, 0x00000000, 0xffffffff }, | |
3230 | ||
3231 | { 0x1408, 0, 0x01c00800, 0x00000000 }, | |
3232 | { 0x149c, 0, 0x8000ffff, 0x00000000 }, | |
3233 | { 0x14a8, 0, 0x00000000, 0x000001ff }, | |
3234 | { 0x14ac, 0, 0x4fffffff, 0x10000000 }, | |
3235 | { 0x14b0, 0, 0x00000002, 0x00000001 }, | |
3236 | { 0x14b8, 0, 0x00000000, 0x00000000 }, | |
3237 | { 0x14c0, 0, 0x00000000, 0x00000009 }, | |
3238 | { 0x14c4, 0, 0x00003fff, 0x00000000 }, | |
3239 | { 0x14cc, 0, 0x00000000, 0x00000001 }, | |
3240 | { 0x14d0, 0, 0xffffffff, 0x00000000 }, | |
3241 | { 0x1500, 0, 0x00000000, 0xffffffff }, | |
3242 | { 0x1504, 0, 0x00000000, 0xffffffff }, | |
3243 | { 0x1508, 0, 0x00000000, 0xffffffff }, | |
3244 | { 0x150c, 0, 0x00000000, 0xffffffff }, | |
3245 | { 0x1510, 0, 0x00000000, 0xffffffff }, | |
3246 | { 0x1514, 0, 0x00000000, 0xffffffff }, | |
3247 | { 0x1518, 0, 0x00000000, 0xffffffff }, | |
3248 | { 0x151c, 0, 0x00000000, 0xffffffff }, | |
3249 | { 0x1520, 0, 0x00000000, 0xffffffff }, | |
3250 | { 0x1524, 0, 0x00000000, 0xffffffff }, | |
3251 | { 0x1528, 0, 0x00000000, 0xffffffff }, | |
3252 | { 0x152c, 0, 0x00000000, 0xffffffff }, | |
3253 | { 0x1530, 0, 0x00000000, 0xffffffff }, | |
3254 | { 0x1534, 0, 0x00000000, 0xffffffff }, | |
3255 | { 0x1538, 0, 0x00000000, 0xffffffff }, | |
3256 | { 0x153c, 0, 0x00000000, 0xffffffff }, | |
3257 | { 0x1540, 0, 0x00000000, 0xffffffff }, | |
3258 | { 0x1544, 0, 0x00000000, 0xffffffff }, | |
3259 | { 0x1548, 0, 0x00000000, 0xffffffff }, | |
3260 | { 0x154c, 0, 0x00000000, 0xffffffff }, | |
3261 | { 0x1550, 0, 0x00000000, 0xffffffff }, | |
3262 | { 0x1554, 0, 0x00000000, 0xffffffff }, | |
3263 | { 0x1558, 0, 0x00000000, 0xffffffff }, | |
3264 | { 0x1600, 0, 0x00000000, 0xffffffff }, | |
3265 | { 0x1604, 0, 0x00000000, 0xffffffff }, | |
3266 | { 0x1608, 0, 0x00000000, 0xffffffff }, | |
3267 | { 0x160c, 0, 0x00000000, 0xffffffff }, | |
3268 | { 0x1610, 0, 0x00000000, 0xffffffff }, | |
3269 | { 0x1614, 0, 0x00000000, 0xffffffff }, | |
3270 | { 0x1618, 0, 0x00000000, 0xffffffff }, | |
3271 | { 0x161c, 0, 0x00000000, 0xffffffff }, | |
3272 | { 0x1620, 0, 0x00000000, 0xffffffff }, | |
3273 | { 0x1624, 0, 0x00000000, 0xffffffff }, | |
3274 | { 0x1628, 0, 0x00000000, 0xffffffff }, | |
3275 | { 0x162c, 0, 0x00000000, 0xffffffff }, | |
3276 | { 0x1630, 0, 0x00000000, 0xffffffff }, | |
3277 | { 0x1634, 0, 0x00000000, 0xffffffff }, | |
3278 | { 0x1638, 0, 0x00000000, 0xffffffff }, | |
3279 | { 0x163c, 0, 0x00000000, 0xffffffff }, | |
3280 | { 0x1640, 0, 0x00000000, 0xffffffff }, | |
3281 | { 0x1644, 0, 0x00000000, 0xffffffff }, | |
3282 | { 0x1648, 0, 0x00000000, 0xffffffff }, | |
3283 | { 0x164c, 0, 0x00000000, 0xffffffff }, | |
3284 | { 0x1650, 0, 0x00000000, 0xffffffff }, | |
3285 | { 0x1654, 0, 0x00000000, 0xffffffff }, | |
3286 | ||
3287 | { 0x1800, 0, 0x00000000, 0x00000001 }, | |
3288 | { 0x1804, 0, 0x00000000, 0x00000003 }, | |
3289 | { 0x1840, 0, 0x00000000, 0xffffffff }, | |
3290 | { 0x1844, 0, 0x00000000, 0xffffffff }, | |
3291 | { 0x1848, 0, 0x00000000, 0xffffffff }, | |
3292 | { 0x184c, 0, 0x00000000, 0xffffffff }, | |
3293 | { 0x1850, 0, 0x00000000, 0xffffffff }, | |
3294 | { 0x1900, 0, 0x7ffbffff, 0x00000000 }, | |
3295 | { 0x1904, 0, 0xffffffff, 0x00000000 }, | |
3296 | { 0x190c, 0, 0xffffffff, 0x00000000 }, | |
3297 | { 0x1914, 0, 0xffffffff, 0x00000000 }, | |
3298 | { 0x191c, 0, 0xffffffff, 0x00000000 }, | |
3299 | { 0x1924, 0, 0xffffffff, 0x00000000 }, | |
3300 | { 0x192c, 0, 0xffffffff, 0x00000000 }, | |
3301 | { 0x1934, 0, 0xffffffff, 0x00000000 }, | |
3302 | { 0x193c, 0, 0xffffffff, 0x00000000 }, | |
3303 | { 0x1944, 0, 0xffffffff, 0x00000000 }, | |
3304 | { 0x194c, 0, 0xffffffff, 0x00000000 }, | |
3305 | { 0x1954, 0, 0xffffffff, 0x00000000 }, | |
3306 | { 0x195c, 0, 0xffffffff, 0x00000000 }, | |
3307 | { 0x1964, 0, 0xffffffff, 0x00000000 }, | |
3308 | { 0x196c, 0, 0xffffffff, 0x00000000 }, | |
3309 | { 0x1974, 0, 0xffffffff, 0x00000000 }, | |
3310 | { 0x197c, 0, 0xffffffff, 0x00000000 }, | |
3311 | { 0x1980, 0, 0x0700ffff, 0x00000000 }, | |
3312 | ||
3313 | { 0x1c00, 0, 0x00000000, 0x00000001 }, | |
3314 | { 0x1c04, 0, 0x00000000, 0x00000003 }, | |
3315 | { 0x1c08, 0, 0x0000000f, 0x00000000 }, | |
3316 | { 0x1c40, 0, 0x00000000, 0xffffffff }, | |
3317 | { 0x1c44, 0, 0x00000000, 0xffffffff }, | |
3318 | { 0x1c48, 0, 0x00000000, 0xffffffff }, | |
3319 | { 0x1c4c, 0, 0x00000000, 0xffffffff }, | |
3320 | { 0x1c50, 0, 0x00000000, 0xffffffff }, | |
3321 | { 0x1d00, 0, 0x7ffbffff, 0x00000000 }, | |
3322 | { 0x1d04, 0, 0xffffffff, 0x00000000 }, | |
3323 | { 0x1d0c, 0, 0xffffffff, 0x00000000 }, | |
3324 | { 0x1d14, 0, 0xffffffff, 0x00000000 }, | |
3325 | { 0x1d1c, 0, 0xffffffff, 0x00000000 }, | |
3326 | { 0x1d24, 0, 0xffffffff, 0x00000000 }, | |
3327 | { 0x1d2c, 0, 0xffffffff, 0x00000000 }, | |
3328 | { 0x1d34, 0, 0xffffffff, 0x00000000 }, | |
3329 | { 0x1d3c, 0, 0xffffffff, 0x00000000 }, | |
3330 | { 0x1d44, 0, 0xffffffff, 0x00000000 }, | |
3331 | { 0x1d4c, 0, 0xffffffff, 0x00000000 }, | |
3332 | { 0x1d54, 0, 0xffffffff, 0x00000000 }, | |
3333 | { 0x1d5c, 0, 0xffffffff, 0x00000000 }, | |
3334 | { 0x1d64, 0, 0xffffffff, 0x00000000 }, | |
3335 | { 0x1d6c, 0, 0xffffffff, 0x00000000 }, | |
3336 | { 0x1d74, 0, 0xffffffff, 0x00000000 }, | |
3337 | { 0x1d7c, 0, 0xffffffff, 0x00000000 }, | |
3338 | { 0x1d80, 0, 0x0700ffff, 0x00000000 }, | |
3339 | ||
3340 | { 0x2004, 0, 0x00000000, 0x0337000f }, | |
3341 | { 0x2008, 0, 0xffffffff, 0x00000000 }, | |
3342 | { 0x200c, 0, 0xffffffff, 0x00000000 }, | |
3343 | { 0x2010, 0, 0xffffffff, 0x00000000 }, | |
3344 | { 0x2014, 0, 0x801fff80, 0x00000000 }, | |
3345 | { 0x2018, 0, 0x000003ff, 0x00000000 }, | |
3346 | ||
3347 | { 0x2800, 0, 0x00000000, 0x00000001 }, | |
3348 | { 0x2804, 0, 0x00000000, 0x00003f01 }, | |
3349 | { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, | |
3350 | { 0x2810, 0, 0xffff0000, 0x00000000 }, | |
3351 | { 0x2814, 0, 0xffff0000, 0x00000000 }, | |
3352 | { 0x2818, 0, 0xffff0000, 0x00000000 }, | |
3353 | { 0x281c, 0, 0xffff0000, 0x00000000 }, | |
3354 | { 0x2834, 0, 0xffffffff, 0x00000000 }, | |
3355 | { 0x2840, 0, 0x00000000, 0xffffffff }, | |
3356 | { 0x2844, 0, 0x00000000, 0xffffffff }, | |
3357 | { 0x2848, 0, 0xffffffff, 0x00000000 }, | |
3358 | { 0x284c, 0, 0xf800f800, 0x07ff07ff }, | |
3359 | ||
3360 | { 0x2c00, 0, 0x00000000, 0x00000011 }, | |
3361 | { 0x2c04, 0, 0x00000000, 0x00030007 }, | |
3362 | ||
3363 | { 0x3000, 0, 0x00000000, 0x00000001 }, | |
3364 | { 0x3004, 0, 0x00000000, 0x007007ff }, | |
3365 | { 0x3008, 0, 0x00000003, 0x00000000 }, | |
3366 | { 0x300c, 0, 0xffffffff, 0x00000000 }, | |
3367 | { 0x3010, 0, 0xffffffff, 0x00000000 }, | |
3368 | { 0x3014, 0, 0xffffffff, 0x00000000 }, | |
3369 | { 0x3034, 0, 0xffffffff, 0x00000000 }, | |
3370 | { 0x3038, 0, 0xffffffff, 0x00000000 }, | |
3371 | { 0x3050, 0, 0x00000001, 0x00000000 }, | |
3372 | ||
3373 | { 0x3c00, 0, 0x00000000, 0x00000001 }, | |
3374 | { 0x3c04, 0, 0x00000000, 0x00070000 }, | |
3375 | { 0x3c08, 0, 0x00007f71, 0x07f00000 }, | |
3376 | { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, | |
3377 | { 0x3c10, 0, 0xffffffff, 0x00000000 }, | |
3378 | { 0x3c14, 0, 0x00000000, 0xffffffff }, | |
3379 | { 0x3c18, 0, 0x00000000, 0xffffffff }, | |
3380 | { 0x3c1c, 0, 0xfffff000, 0x00000000 }, | |
3381 | { 0x3c20, 0, 0xffffff00, 0x00000000 }, | |
3382 | { 0x3c24, 0, 0xffffffff, 0x00000000 }, | |
3383 | { 0x3c28, 0, 0xffffffff, 0x00000000 }, | |
3384 | { 0x3c2c, 0, 0xffffffff, 0x00000000 }, | |
3385 | { 0x3c30, 0, 0xffffffff, 0x00000000 }, | |
3386 | { 0x3c34, 0, 0xffffffff, 0x00000000 }, | |
3387 | { 0x3c38, 0, 0xffffffff, 0x00000000 }, | |
3388 | { 0x3c3c, 0, 0xffffffff, 0x00000000 }, | |
3389 | { 0x3c40, 0, 0xffffffff, 0x00000000 }, | |
3390 | { 0x3c44, 0, 0xffffffff, 0x00000000 }, | |
3391 | { 0x3c48, 0, 0xffffffff, 0x00000000 }, | |
3392 | { 0x3c4c, 0, 0xffffffff, 0x00000000 }, | |
3393 | { 0x3c50, 0, 0xffffffff, 0x00000000 }, | |
3394 | { 0x3c54, 0, 0xffffffff, 0x00000000 }, | |
3395 | { 0x3c58, 0, 0xffffffff, 0x00000000 }, | |
3396 | { 0x3c5c, 0, 0xffffffff, 0x00000000 }, | |
3397 | { 0x3c60, 0, 0xffffffff, 0x00000000 }, | |
3398 | { 0x3c64, 0, 0xffffffff, 0x00000000 }, | |
3399 | { 0x3c68, 0, 0xffffffff, 0x00000000 }, | |
3400 | { 0x3c6c, 0, 0xffffffff, 0x00000000 }, | |
3401 | { 0x3c70, 0, 0xffffffff, 0x00000000 }, | |
3402 | { 0x3c74, 0, 0x0000003f, 0x00000000 }, | |
3403 | { 0x3c78, 0, 0x00000000, 0x00000000 }, | |
3404 | { 0x3c7c, 0, 0x00000000, 0x00000000 }, | |
3405 | { 0x3c80, 0, 0x3fffffff, 0x00000000 }, | |
3406 | { 0x3c84, 0, 0x0000003f, 0x00000000 }, | |
3407 | { 0x3c88, 0, 0x00000000, 0xffffffff }, | |
3408 | { 0x3c8c, 0, 0x00000000, 0xffffffff }, | |
3409 | ||
3410 | { 0x4000, 0, 0x00000000, 0x00000001 }, | |
3411 | { 0x4004, 0, 0x00000000, 0x00030000 }, | |
3412 | { 0x4008, 0, 0x00000ff0, 0x00000000 }, | |
3413 | { 0x400c, 0, 0xffffffff, 0x00000000 }, | |
3414 | { 0x4088, 0, 0x00000000, 0x00070303 }, | |
3415 | ||
3416 | { 0x4400, 0, 0x00000000, 0x00000001 }, | |
3417 | { 0x4404, 0, 0x00000000, 0x00003f01 }, | |
3418 | { 0x4408, 0, 0x7fff00ff, 0x00000000 }, | |
3419 | { 0x440c, 0, 0xffffffff, 0x00000000 }, | |
3420 | { 0x4410, 0, 0xffff, 0x0000 }, | |
3421 | { 0x4414, 0, 0xffff, 0x0000 }, | |
3422 | { 0x4418, 0, 0xffff, 0x0000 }, | |
3423 | { 0x441c, 0, 0xffff, 0x0000 }, | |
3424 | { 0x4428, 0, 0xffffffff, 0x00000000 }, | |
3425 | { 0x442c, 0, 0xffffffff, 0x00000000 }, | |
3426 | { 0x4430, 0, 0xffffffff, 0x00000000 }, | |
3427 | { 0x4434, 0, 0xffffffff, 0x00000000 }, | |
3428 | { 0x4438, 0, 0xffffffff, 0x00000000 }, | |
3429 | { 0x443c, 0, 0xffffffff, 0x00000000 }, | |
3430 | { 0x4440, 0, 0xffffffff, 0x00000000 }, | |
3431 | { 0x4444, 0, 0xffffffff, 0x00000000 }, | |
3432 | ||
3433 | { 0x4c00, 0, 0x00000000, 0x00000001 }, | |
3434 | { 0x4c04, 0, 0x00000000, 0x0000003f }, | |
3435 | { 0x4c08, 0, 0xffffffff, 0x00000000 }, | |
3436 | { 0x4c0c, 0, 0x0007fc00, 0x00000000 }, | |
3437 | { 0x4c10, 0, 0x80003fe0, 0x00000000 }, | |
3438 | { 0x4c14, 0, 0xffffffff, 0x00000000 }, | |
3439 | { 0x4c44, 0, 0x00000000, 0x9fff9fff }, | |
3440 | { 0x4c48, 0, 0x00000000, 0xb3009fff }, | |
3441 | { 0x4c4c, 0, 0x00000000, 0x77f33b30 }, | |
3442 | { 0x4c50, 0, 0x00000000, 0xffffffff }, | |
3443 | ||
3444 | { 0x5004, 0, 0x00000000, 0x0000007f }, | |
3445 | { 0x5008, 0, 0x0f0007ff, 0x00000000 }, | |
3446 | { 0x500c, 0, 0xf800f800, 0x07ff07ff }, | |
3447 | ||
3448 | { 0x5400, 0, 0x00000008, 0x00000001 }, | |
3449 | { 0x5404, 0, 0x00000000, 0x0000003f }, | |
3450 | { 0x5408, 0, 0x0000001f, 0x00000000 }, | |
3451 | { 0x540c, 0, 0xffffffff, 0x00000000 }, | |
3452 | { 0x5410, 0, 0xffffffff, 0x00000000 }, | |
3453 | { 0x5414, 0, 0x0000ffff, 0x00000000 }, | |
3454 | { 0x5418, 0, 0x0000ffff, 0x00000000 }, | |
3455 | { 0x541c, 0, 0x0000ffff, 0x00000000 }, | |
3456 | { 0x5420, 0, 0x0000ffff, 0x00000000 }, | |
3457 | { 0x5428, 0, 0x000000ff, 0x00000000 }, | |
3458 | { 0x542c, 0, 0xff00ffff, 0x00000000 }, | |
3459 | { 0x5430, 0, 0x001fff80, 0x00000000 }, | |
3460 | { 0x5438, 0, 0xffffffff, 0x00000000 }, | |
3461 | { 0x543c, 0, 0xffffffff, 0x00000000 }, | |
3462 | { 0x5440, 0, 0xf800f800, 0x07ff07ff }, | |
3463 | ||
3464 | { 0x5c00, 0, 0x00000000, 0x00000001 }, | |
3465 | { 0x5c04, 0, 0x00000000, 0x0003000f }, | |
3466 | { 0x5c08, 0, 0x00000003, 0x00000000 }, | |
3467 | { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, | |
3468 | { 0x5c10, 0, 0x00000000, 0xffffffff }, | |
3469 | { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, | |
3470 | { 0x5c84, 0, 0x00000000, 0x0000f333 }, | |
3471 | { 0x5c88, 0, 0x00000000, 0x00077373 }, | |
3472 | { 0x5c8c, 0, 0x00000000, 0x0007f737 }, | |
3473 | ||
3474 | { 0x6808, 0, 0x0000ff7f, 0x00000000 }, | |
3475 | { 0x680c, 0, 0xffffffff, 0x00000000 }, | |
3476 | { 0x6810, 0, 0xffffffff, 0x00000000 }, | |
3477 | { 0x6814, 0, 0xffffffff, 0x00000000 }, | |
3478 | { 0x6818, 0, 0xffffffff, 0x00000000 }, | |
3479 | { 0x681c, 0, 0xffffffff, 0x00000000 }, | |
3480 | { 0x6820, 0, 0x00ff00ff, 0x00000000 }, | |
3481 | { 0x6824, 0, 0x00ff00ff, 0x00000000 }, | |
3482 | { 0x6828, 0, 0x00ff00ff, 0x00000000 }, | |
3483 | { 0x682c, 0, 0x03ff03ff, 0x00000000 }, | |
3484 | { 0x6830, 0, 0x03ff03ff, 0x00000000 }, | |
3485 | { 0x6834, 0, 0x03ff03ff, 0x00000000 }, | |
3486 | { 0x6838, 0, 0x03ff03ff, 0x00000000 }, | |
3487 | { 0x683c, 0, 0x0000ffff, 0x00000000 }, | |
3488 | { 0x6840, 0, 0x00000ff0, 0x00000000 }, | |
3489 | { 0x6844, 0, 0x00ffff00, 0x00000000 }, | |
3490 | { 0x684c, 0, 0xffffffff, 0x00000000 }, | |
3491 | { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, | |
3492 | { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, | |
3493 | { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, | |
3494 | { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, | |
3495 | { 0x6908, 0, 0x00000000, 0x0001ff0f }, | |
3496 | { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, | |
3497 | ||
3498 | { 0xffff, 0, 0x00000000, 0x00000000 }, | |
3499 | }; | |
3500 | ||
3501 | ret = 0; | |
3502 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
3503 | u32 offset, rw_mask, ro_mask, save_val, val; | |
3504 | ||
3505 | offset = (u32) reg_tbl[i].offset; | |
3506 | rw_mask = reg_tbl[i].rw_mask; | |
3507 | ro_mask = reg_tbl[i].ro_mask; | |
3508 | ||
14ab9b86 | 3509 | save_val = readl(bp->regview + offset); |
b6016b76 | 3510 | |
14ab9b86 | 3511 | writel(0, bp->regview + offset); |
b6016b76 | 3512 | |
14ab9b86 | 3513 | val = readl(bp->regview + offset); |
b6016b76 MC |
3514 | if ((val & rw_mask) != 0) { |
3515 | goto reg_test_err; | |
3516 | } | |
3517 | ||
3518 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
3519 | goto reg_test_err; | |
3520 | } | |
3521 | ||
14ab9b86 | 3522 | writel(0xffffffff, bp->regview + offset); |
b6016b76 | 3523 | |
14ab9b86 | 3524 | val = readl(bp->regview + offset); |
b6016b76 MC |
3525 | if ((val & rw_mask) != rw_mask) { |
3526 | goto reg_test_err; | |
3527 | } | |
3528 | ||
3529 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
3530 | goto reg_test_err; | |
3531 | } | |
3532 | ||
14ab9b86 | 3533 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
3534 | continue; |
3535 | ||
3536 | reg_test_err: | |
14ab9b86 | 3537 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
3538 | ret = -ENODEV; |
3539 | break; | |
3540 | } | |
3541 | return ret; | |
3542 | } | |
3543 | ||
3544 | static int | |
3545 | bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) | |
3546 | { | |
3547 | static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, | |
3548 | 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; | |
3549 | int i; | |
3550 | ||
3551 | for (i = 0; i < sizeof(test_pattern) / 4; i++) { | |
3552 | u32 offset; | |
3553 | ||
3554 | for (offset = 0; offset < size; offset += 4) { | |
3555 | ||
3556 | REG_WR_IND(bp, start + offset, test_pattern[i]); | |
3557 | ||
3558 | if (REG_RD_IND(bp, start + offset) != | |
3559 | test_pattern[i]) { | |
3560 | return -ENODEV; | |
3561 | } | |
3562 | } | |
3563 | } | |
3564 | return 0; | |
3565 | } | |
3566 | ||
3567 | static int | |
3568 | bnx2_test_memory(struct bnx2 *bp) | |
3569 | { | |
3570 | int ret = 0; | |
3571 | int i; | |
3572 | static struct { | |
3573 | u32 offset; | |
3574 | u32 len; | |
3575 | } mem_tbl[] = { | |
3576 | { 0x60000, 0x4000 }, | |
3577 | { 0xa0000, 0x4000 }, | |
3578 | { 0xe0000, 0x4000 }, | |
3579 | { 0x120000, 0x4000 }, | |
3580 | { 0x1a0000, 0x4000 }, | |
3581 | { 0x160000, 0x4000 }, | |
3582 | { 0xffffffff, 0 }, | |
3583 | }; | |
3584 | ||
3585 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
3586 | if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, | |
3587 | mem_tbl[i].len)) != 0) { | |
3588 | return ret; | |
3589 | } | |
3590 | } | |
3591 | ||
3592 | return ret; | |
3593 | } | |
3594 | ||
3595 | static int | |
3596 | bnx2_test_loopback(struct bnx2 *bp) | |
3597 | { | |
3598 | unsigned int pkt_size, num_pkts, i; | |
3599 | struct sk_buff *skb, *rx_skb; | |
3600 | unsigned char *packet; | |
3601 | u16 rx_start_idx, rx_idx, send_idx; | |
3602 | u32 send_bseq, val; | |
3603 | dma_addr_t map; | |
3604 | struct tx_bd *txbd; | |
3605 | struct sw_bd *rx_buf; | |
3606 | struct l2_fhdr *rx_hdr; | |
3607 | int ret = -ENODEV; | |
3608 | ||
3609 | if (!netif_running(bp->dev)) | |
3610 | return -ENODEV; | |
3611 | ||
3612 | bp->loopback = MAC_LOOPBACK; | |
3613 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG); | |
3614 | bnx2_set_mac_loopback(bp); | |
3615 | ||
3616 | pkt_size = 1514; | |
3617 | skb = dev_alloc_skb(pkt_size); | |
3618 | packet = skb_put(skb, pkt_size); | |
3619 | memcpy(packet, bp->mac_addr, 6); | |
3620 | memset(packet + 6, 0x0, 8); | |
3621 | for (i = 14; i < pkt_size; i++) | |
3622 | packet[i] = (unsigned char) (i & 0xff); | |
3623 | ||
3624 | map = pci_map_single(bp->pdev, skb->data, pkt_size, | |
3625 | PCI_DMA_TODEVICE); | |
3626 | ||
3627 | val = REG_RD(bp, BNX2_HC_COMMAND); | |
3628 | REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
3629 | REG_RD(bp, BNX2_HC_COMMAND); | |
3630 | ||
3631 | udelay(5); | |
3632 | rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0; | |
3633 | ||
3634 | send_idx = 0; | |
3635 | send_bseq = 0; | |
3636 | num_pkts = 0; | |
3637 | ||
3638 | txbd = &bp->tx_desc_ring[send_idx]; | |
3639 | ||
3640 | txbd->tx_bd_haddr_hi = (u64) map >> 32; | |
3641 | txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; | |
3642 | txbd->tx_bd_mss_nbytes = pkt_size; | |
3643 | txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; | |
3644 | ||
3645 | num_pkts++; | |
3646 | send_idx = NEXT_TX_BD(send_idx); | |
3647 | ||
3648 | send_bseq += pkt_size; | |
3649 | ||
3650 | REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx); | |
3651 | REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq); | |
3652 | ||
3653 | ||
3654 | udelay(100); | |
3655 | ||
3656 | val = REG_RD(bp, BNX2_HC_COMMAND); | |
3657 | REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
3658 | REG_RD(bp, BNX2_HC_COMMAND); | |
3659 | ||
3660 | udelay(5); | |
3661 | ||
3662 | pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); | |
3663 | dev_kfree_skb_irq(skb); | |
3664 | ||
3665 | if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) { | |
3666 | goto loopback_test_done; | |
3667 | } | |
3668 | ||
3669 | rx_idx = bp->status_blk->status_rx_quick_consumer_index0; | |
3670 | if (rx_idx != rx_start_idx + num_pkts) { | |
3671 | goto loopback_test_done; | |
3672 | } | |
3673 | ||
3674 | rx_buf = &bp->rx_buf_ring[rx_start_idx]; | |
3675 | rx_skb = rx_buf->skb; | |
3676 | ||
3677 | rx_hdr = (struct l2_fhdr *) rx_skb->data; | |
3678 | skb_reserve(rx_skb, bp->rx_offset); | |
3679 | ||
3680 | pci_dma_sync_single_for_cpu(bp->pdev, | |
3681 | pci_unmap_addr(rx_buf, mapping), | |
3682 | bp->rx_buf_size, PCI_DMA_FROMDEVICE); | |
3683 | ||
3684 | if (rx_hdr->l2_fhdr_errors & | |
3685 | (L2_FHDR_ERRORS_BAD_CRC | | |
3686 | L2_FHDR_ERRORS_PHY_DECODE | | |
3687 | L2_FHDR_ERRORS_ALIGNMENT | | |
3688 | L2_FHDR_ERRORS_TOO_SHORT | | |
3689 | L2_FHDR_ERRORS_GIANT_FRAME)) { | |
3690 | ||
3691 | goto loopback_test_done; | |
3692 | } | |
3693 | ||
3694 | if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { | |
3695 | goto loopback_test_done; | |
3696 | } | |
3697 | ||
3698 | for (i = 14; i < pkt_size; i++) { | |
3699 | if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) { | |
3700 | goto loopback_test_done; | |
3701 | } | |
3702 | } | |
3703 | ||
3704 | ret = 0; | |
3705 | ||
3706 | loopback_test_done: | |
3707 | bp->loopback = 0; | |
3708 | return ret; | |
3709 | } | |
3710 | ||
3711 | #define NVRAM_SIZE 0x200 | |
3712 | #define CRC32_RESIDUAL 0xdebb20e3 | |
3713 | ||
3714 | static int | |
3715 | bnx2_test_nvram(struct bnx2 *bp) | |
3716 | { | |
3717 | u32 buf[NVRAM_SIZE / 4]; | |
3718 | u8 *data = (u8 *) buf; | |
3719 | int rc = 0; | |
3720 | u32 magic, csum; | |
3721 | ||
3722 | if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) | |
3723 | goto test_nvram_done; | |
3724 | ||
3725 | magic = be32_to_cpu(buf[0]); | |
3726 | if (magic != 0x669955aa) { | |
3727 | rc = -ENODEV; | |
3728 | goto test_nvram_done; | |
3729 | } | |
3730 | ||
3731 | if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) | |
3732 | goto test_nvram_done; | |
3733 | ||
3734 | csum = ether_crc_le(0x100, data); | |
3735 | if (csum != CRC32_RESIDUAL) { | |
3736 | rc = -ENODEV; | |
3737 | goto test_nvram_done; | |
3738 | } | |
3739 | ||
3740 | csum = ether_crc_le(0x100, data + 0x100); | |
3741 | if (csum != CRC32_RESIDUAL) { | |
3742 | rc = -ENODEV; | |
3743 | } | |
3744 | ||
3745 | test_nvram_done: | |
3746 | return rc; | |
3747 | } | |
3748 | ||
3749 | static int | |
3750 | bnx2_test_link(struct bnx2 *bp) | |
3751 | { | |
3752 | u32 bmsr; | |
3753 | ||
3754 | spin_lock_irq(&bp->phy_lock); | |
3755 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | |
3756 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | |
3757 | spin_unlock_irq(&bp->phy_lock); | |
3758 | ||
3759 | if (bmsr & BMSR_LSTATUS) { | |
3760 | return 0; | |
3761 | } | |
3762 | return -ENODEV; | |
3763 | } | |
3764 | ||
3765 | static int | |
3766 | bnx2_test_intr(struct bnx2 *bp) | |
3767 | { | |
3768 | int i; | |
3769 | u32 val; | |
3770 | u16 status_idx; | |
3771 | ||
3772 | if (!netif_running(bp->dev)) | |
3773 | return -ENODEV; | |
3774 | ||
3775 | status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; | |
3776 | ||
3777 | /* This register is not touched during run-time. */ | |
3778 | val = REG_RD(bp, BNX2_HC_COMMAND); | |
3779 | REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW); | |
3780 | REG_RD(bp, BNX2_HC_COMMAND); | |
3781 | ||
3782 | for (i = 0; i < 10; i++) { | |
3783 | if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != | |
3784 | status_idx) { | |
3785 | ||
3786 | break; | |
3787 | } | |
3788 | ||
3789 | msleep_interruptible(10); | |
3790 | } | |
3791 | if (i < 10) | |
3792 | return 0; | |
3793 | ||
3794 | return -ENODEV; | |
3795 | } | |
3796 | ||
3797 | static void | |
3798 | bnx2_timer(unsigned long data) | |
3799 | { | |
3800 | struct bnx2 *bp = (struct bnx2 *) data; | |
3801 | u32 msg; | |
3802 | ||
3803 | if (atomic_read(&bp->intr_sem) != 0) | |
3804 | goto bnx2_restart_timer; | |
3805 | ||
3806 | msg = (u32) ++bp->fw_drv_pulse_wr_seq; | |
3807 | REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg); | |
3808 | ||
3809 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | |
3810 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { | |
3811 | unsigned long flags; | |
3812 | ||
3813 | spin_lock_irqsave(&bp->phy_lock, flags); | |
3814 | if (bp->serdes_an_pending) { | |
3815 | bp->serdes_an_pending--; | |
3816 | } | |
3817 | else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
3818 | u32 bmcr; | |
3819 | ||
3820 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
3821 | ||
3822 | if (bmcr & BMCR_ANENABLE) { | |
3823 | u32 phy1, phy2; | |
3824 | ||
3825 | bnx2_write_phy(bp, 0x1c, 0x7c00); | |
3826 | bnx2_read_phy(bp, 0x1c, &phy1); | |
3827 | ||
3828 | bnx2_write_phy(bp, 0x17, 0x0f01); | |
3829 | bnx2_read_phy(bp, 0x15, &phy2); | |
3830 | bnx2_write_phy(bp, 0x17, 0x0f01); | |
3831 | bnx2_read_phy(bp, 0x15, &phy2); | |
3832 | ||
3833 | if ((phy1 & 0x10) && /* SIGNAL DETECT */ | |
3834 | !(phy2 & 0x20)) { /* no CONFIG */ | |
3835 | ||
3836 | bmcr &= ~BMCR_ANENABLE; | |
3837 | bmcr |= BMCR_SPEED1000 | | |
3838 | BMCR_FULLDPLX; | |
3839 | bnx2_write_phy(bp, MII_BMCR, bmcr); | |
3840 | bp->phy_flags |= | |
3841 | PHY_PARALLEL_DETECT_FLAG; | |
3842 | } | |
3843 | } | |
3844 | } | |
3845 | else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && | |
3846 | (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) { | |
3847 | u32 phy2; | |
3848 | ||
3849 | bnx2_write_phy(bp, 0x17, 0x0f01); | |
3850 | bnx2_read_phy(bp, 0x15, &phy2); | |
3851 | if (phy2 & 0x20) { | |
3852 | u32 bmcr; | |
3853 | ||
3854 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
3855 | bmcr |= BMCR_ANENABLE; | |
3856 | bnx2_write_phy(bp, MII_BMCR, bmcr); | |
3857 | ||
3858 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | |
3859 | ||
3860 | } | |
3861 | } | |
3862 | ||
3863 | spin_unlock_irqrestore(&bp->phy_lock, flags); | |
3864 | } | |
3865 | ||
3866 | bnx2_restart_timer: | |
3867 | bp->timer.expires = RUN_AT(bp->timer_interval); | |
3868 | ||
3869 | add_timer(&bp->timer); | |
3870 | } | |
3871 | ||
3872 | /* Called with rtnl_lock */ | |
3873 | static int | |
3874 | bnx2_open(struct net_device *dev) | |
3875 | { | |
3876 | struct bnx2 *bp = dev->priv; | |
3877 | int rc; | |
3878 | ||
3879 | bnx2_set_power_state(bp, 0); | |
3880 | bnx2_disable_int(bp); | |
3881 | ||
3882 | rc = bnx2_alloc_mem(bp); | |
3883 | if (rc) | |
3884 | return rc; | |
3885 | ||
3886 | if ((CHIP_ID(bp) != CHIP_ID_5706_A0) && | |
3887 | (CHIP_ID(bp) != CHIP_ID_5706_A1) && | |
3888 | !disable_msi) { | |
3889 | ||
3890 | if (pci_enable_msi(bp->pdev) == 0) { | |
3891 | bp->flags |= USING_MSI_FLAG; | |
3892 | rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name, | |
3893 | dev); | |
3894 | } | |
3895 | else { | |
3896 | rc = request_irq(bp->pdev->irq, bnx2_interrupt, | |
3897 | SA_SHIRQ, dev->name, dev); | |
3898 | } | |
3899 | } | |
3900 | else { | |
3901 | rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ, | |
3902 | dev->name, dev); | |
3903 | } | |
3904 | if (rc) { | |
3905 | bnx2_free_mem(bp); | |
3906 | return rc; | |
3907 | } | |
3908 | ||
3909 | rc = bnx2_init_nic(bp); | |
3910 | ||
3911 | if (rc) { | |
3912 | free_irq(bp->pdev->irq, dev); | |
3913 | if (bp->flags & USING_MSI_FLAG) { | |
3914 | pci_disable_msi(bp->pdev); | |
3915 | bp->flags &= ~USING_MSI_FLAG; | |
3916 | } | |
3917 | bnx2_free_skbs(bp); | |
3918 | bnx2_free_mem(bp); | |
3919 | return rc; | |
3920 | } | |
3921 | ||
3922 | init_timer(&bp->timer); | |
3923 | ||
3924 | bp->timer.expires = RUN_AT(bp->timer_interval); | |
3925 | bp->timer.data = (unsigned long) bp; | |
3926 | bp->timer.function = bnx2_timer; | |
3927 | add_timer(&bp->timer); | |
3928 | ||
3929 | atomic_set(&bp->intr_sem, 0); | |
3930 | ||
3931 | bnx2_enable_int(bp); | |
3932 | ||
3933 | if (bp->flags & USING_MSI_FLAG) { | |
3934 | /* Test MSI to make sure it is working | |
3935 | * If MSI test fails, go back to INTx mode | |
3936 | */ | |
3937 | if (bnx2_test_intr(bp) != 0) { | |
3938 | printk(KERN_WARNING PFX "%s: No interrupt was generated" | |
3939 | " using MSI, switching to INTx mode. Please" | |
3940 | " report this failure to the PCI maintainer" | |
3941 | " and include system chipset information.\n", | |
3942 | bp->dev->name); | |
3943 | ||
3944 | bnx2_disable_int(bp); | |
3945 | free_irq(bp->pdev->irq, dev); | |
3946 | pci_disable_msi(bp->pdev); | |
3947 | bp->flags &= ~USING_MSI_FLAG; | |
3948 | ||
3949 | rc = bnx2_init_nic(bp); | |
3950 | ||
3951 | if (!rc) { | |
3952 | rc = request_irq(bp->pdev->irq, bnx2_interrupt, | |
3953 | SA_SHIRQ, dev->name, dev); | |
3954 | } | |
3955 | if (rc) { | |
3956 | bnx2_free_skbs(bp); | |
3957 | bnx2_free_mem(bp); | |
3958 | del_timer_sync(&bp->timer); | |
3959 | return rc; | |
3960 | } | |
3961 | bnx2_enable_int(bp); | |
3962 | } | |
3963 | } | |
3964 | if (bp->flags & USING_MSI_FLAG) { | |
3965 | printk(KERN_INFO PFX "%s: using MSI\n", dev->name); | |
3966 | } | |
3967 | ||
3968 | netif_start_queue(dev); | |
3969 | ||
3970 | return 0; | |
3971 | } | |
3972 | ||
3973 | static void | |
3974 | bnx2_reset_task(void *data) | |
3975 | { | |
3976 | struct bnx2 *bp = data; | |
3977 | ||
afdc08b9 MC |
3978 | if (!netif_running(bp->dev)) |
3979 | return; | |
3980 | ||
3981 | bp->in_reset_task = 1; | |
b6016b76 MC |
3982 | bnx2_netif_stop(bp); |
3983 | ||
3984 | bnx2_init_nic(bp); | |
3985 | ||
3986 | atomic_set(&bp->intr_sem, 1); | |
3987 | bnx2_netif_start(bp); | |
afdc08b9 | 3988 | bp->in_reset_task = 0; |
b6016b76 MC |
3989 | } |
3990 | ||
3991 | static void | |
3992 | bnx2_tx_timeout(struct net_device *dev) | |
3993 | { | |
3994 | struct bnx2 *bp = dev->priv; | |
3995 | ||
3996 | /* This allows the netif to be shutdown gracefully before resetting */ | |
3997 | schedule_work(&bp->reset_task); | |
3998 | } | |
3999 | ||
4000 | #ifdef BCM_VLAN | |
4001 | /* Called with rtnl_lock */ | |
4002 | static void | |
4003 | bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp) | |
4004 | { | |
4005 | struct bnx2 *bp = dev->priv; | |
4006 | ||
4007 | bnx2_netif_stop(bp); | |
4008 | ||
4009 | bp->vlgrp = vlgrp; | |
4010 | bnx2_set_rx_mode(dev); | |
4011 | ||
4012 | bnx2_netif_start(bp); | |
4013 | } | |
4014 | ||
4015 | /* Called with rtnl_lock */ | |
4016 | static void | |
4017 | bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid) | |
4018 | { | |
4019 | struct bnx2 *bp = dev->priv; | |
4020 | ||
4021 | bnx2_netif_stop(bp); | |
4022 | ||
4023 | if (bp->vlgrp) | |
4024 | bp->vlgrp->vlan_devices[vid] = NULL; | |
4025 | bnx2_set_rx_mode(dev); | |
4026 | ||
4027 | bnx2_netif_start(bp); | |
4028 | } | |
4029 | #endif | |
4030 | ||
4031 | /* Called with dev->xmit_lock. | |
4032 | * hard_start_xmit is pseudo-lockless - a lock is only required when | |
4033 | * the tx queue is full. This way, we get the benefit of lockless | |
4034 | * operations most of the time without the complexities to handle | |
4035 | * netif_stop_queue/wake_queue race conditions. | |
4036 | */ | |
4037 | static int | |
4038 | bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
4039 | { | |
4040 | struct bnx2 *bp = dev->priv; | |
4041 | dma_addr_t mapping; | |
4042 | struct tx_bd *txbd; | |
4043 | struct sw_bd *tx_buf; | |
4044 | u32 len, vlan_tag_flags, last_frag, mss; | |
4045 | u16 prod, ring_prod; | |
4046 | int i; | |
4047 | ||
4048 | if (unlikely(atomic_read(&bp->tx_avail_bd) < | |
4049 | (skb_shinfo(skb)->nr_frags + 1))) { | |
4050 | ||
4051 | netif_stop_queue(dev); | |
4052 | printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n", | |
4053 | dev->name); | |
4054 | ||
4055 | return NETDEV_TX_BUSY; | |
4056 | } | |
4057 | len = skb_headlen(skb); | |
4058 | prod = bp->tx_prod; | |
4059 | ring_prod = TX_RING_IDX(prod); | |
4060 | ||
4061 | vlan_tag_flags = 0; | |
4062 | if (skb->ip_summed == CHECKSUM_HW) { | |
4063 | vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; | |
4064 | } | |
4065 | ||
4066 | if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) { | |
4067 | vlan_tag_flags |= | |
4068 | (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); | |
4069 | } | |
4070 | #ifdef BCM_TSO | |
4071 | if ((mss = skb_shinfo(skb)->tso_size) && | |
4072 | (skb->len > (bp->dev->mtu + ETH_HLEN))) { | |
4073 | u32 tcp_opt_len, ip_tcp_len; | |
4074 | ||
4075 | if (skb_header_cloned(skb) && | |
4076 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
4077 | dev_kfree_skb(skb); | |
4078 | return NETDEV_TX_OK; | |
4079 | } | |
4080 | ||
4081 | tcp_opt_len = ((skb->h.th->doff - 5) * 4); | |
4082 | vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; | |
4083 | ||
4084 | tcp_opt_len = 0; | |
4085 | if (skb->h.th->doff > 5) { | |
4086 | tcp_opt_len = (skb->h.th->doff - 5) << 2; | |
4087 | } | |
4088 | ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr); | |
4089 | ||
4090 | skb->nh.iph->check = 0; | |
4091 | skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len); | |
4092 | skb->h.th->check = | |
4093 | ~csum_tcpudp_magic(skb->nh.iph->saddr, | |
4094 | skb->nh.iph->daddr, | |
4095 | 0, IPPROTO_TCP, 0); | |
4096 | ||
4097 | if (tcp_opt_len || (skb->nh.iph->ihl > 5)) { | |
4098 | vlan_tag_flags |= ((skb->nh.iph->ihl - 5) + | |
4099 | (tcp_opt_len >> 2)) << 8; | |
4100 | } | |
4101 | } | |
4102 | else | |
4103 | #endif | |
4104 | { | |
4105 | mss = 0; | |
4106 | } | |
4107 | ||
4108 | mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
4109 | ||
4110 | tx_buf = &bp->tx_buf_ring[ring_prod]; | |
4111 | tx_buf->skb = skb; | |
4112 | pci_unmap_addr_set(tx_buf, mapping, mapping); | |
4113 | ||
4114 | txbd = &bp->tx_desc_ring[ring_prod]; | |
4115 | ||
4116 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
4117 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
4118 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
4119 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; | |
4120 | ||
4121 | last_frag = skb_shinfo(skb)->nr_frags; | |
4122 | ||
4123 | for (i = 0; i < last_frag; i++) { | |
4124 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
4125 | ||
4126 | prod = NEXT_TX_BD(prod); | |
4127 | ring_prod = TX_RING_IDX(prod); | |
4128 | txbd = &bp->tx_desc_ring[ring_prod]; | |
4129 | ||
4130 | len = frag->size; | |
4131 | mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset, | |
4132 | len, PCI_DMA_TODEVICE); | |
4133 | pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod], | |
4134 | mapping, mapping); | |
4135 | ||
4136 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
4137 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
4138 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
4139 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; | |
4140 | ||
4141 | } | |
4142 | txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; | |
4143 | ||
4144 | prod = NEXT_TX_BD(prod); | |
4145 | bp->tx_prod_bseq += skb->len; | |
4146 | ||
4147 | atomic_sub(last_frag + 1, &bp->tx_avail_bd); | |
4148 | ||
4149 | REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); | |
4150 | REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); | |
4151 | ||
4152 | mmiowb(); | |
4153 | ||
4154 | bp->tx_prod = prod; | |
4155 | dev->trans_start = jiffies; | |
4156 | ||
4157 | if (unlikely(atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS)) { | |
4158 | unsigned long flags; | |
4159 | ||
4160 | spin_lock_irqsave(&bp->tx_lock, flags); | |
4161 | if (atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS) { | |
4162 | netif_stop_queue(dev); | |
4163 | ||
4164 | if (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS) | |
4165 | netif_wake_queue(dev); | |
4166 | } | |
4167 | spin_unlock_irqrestore(&bp->tx_lock, flags); | |
4168 | } | |
4169 | ||
4170 | return NETDEV_TX_OK; | |
4171 | } | |
4172 | ||
4173 | /* Called with rtnl_lock */ | |
4174 | static int | |
4175 | bnx2_close(struct net_device *dev) | |
4176 | { | |
4177 | struct bnx2 *bp = dev->priv; | |
4178 | u32 reset_code; | |
4179 | ||
afdc08b9 MC |
4180 | /* Calling flush_scheduled_work() may deadlock because |
4181 | * linkwatch_event() may be on the workqueue and it will try to get | |
4182 | * the rtnl_lock which we are holding. | |
4183 | */ | |
4184 | while (bp->in_reset_task) | |
4185 | msleep(1); | |
4186 | ||
b6016b76 MC |
4187 | bnx2_netif_stop(bp); |
4188 | del_timer_sync(&bp->timer); | |
4189 | if (bp->wol) | |
4190 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
4191 | else | |
4192 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
4193 | bnx2_reset_chip(bp, reset_code); | |
4194 | free_irq(bp->pdev->irq, dev); | |
4195 | if (bp->flags & USING_MSI_FLAG) { | |
4196 | pci_disable_msi(bp->pdev); | |
4197 | bp->flags &= ~USING_MSI_FLAG; | |
4198 | } | |
4199 | bnx2_free_skbs(bp); | |
4200 | bnx2_free_mem(bp); | |
4201 | bp->link_up = 0; | |
4202 | netif_carrier_off(bp->dev); | |
4203 | bnx2_set_power_state(bp, 3); | |
4204 | return 0; | |
4205 | } | |
4206 | ||
4207 | #define GET_NET_STATS64(ctr) \ | |
4208 | (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \ | |
4209 | (unsigned long) (ctr##_lo) | |
4210 | ||
4211 | #define GET_NET_STATS32(ctr) \ | |
4212 | (ctr##_lo) | |
4213 | ||
4214 | #if (BITS_PER_LONG == 64) | |
4215 | #define GET_NET_STATS GET_NET_STATS64 | |
4216 | #else | |
4217 | #define GET_NET_STATS GET_NET_STATS32 | |
4218 | #endif | |
4219 | ||
4220 | static struct net_device_stats * | |
4221 | bnx2_get_stats(struct net_device *dev) | |
4222 | { | |
4223 | struct bnx2 *bp = dev->priv; | |
4224 | struct statistics_block *stats_blk = bp->stats_blk; | |
4225 | struct net_device_stats *net_stats = &bp->net_stats; | |
4226 | ||
4227 | if (bp->stats_blk == NULL) { | |
4228 | return net_stats; | |
4229 | } | |
4230 | net_stats->rx_packets = | |
4231 | GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) + | |
4232 | GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) + | |
4233 | GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts); | |
4234 | ||
4235 | net_stats->tx_packets = | |
4236 | GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) + | |
4237 | GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) + | |
4238 | GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts); | |
4239 | ||
4240 | net_stats->rx_bytes = | |
4241 | GET_NET_STATS(stats_blk->stat_IfHCInOctets); | |
4242 | ||
4243 | net_stats->tx_bytes = | |
4244 | GET_NET_STATS(stats_blk->stat_IfHCOutOctets); | |
4245 | ||
4246 | net_stats->multicast = | |
4247 | GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts); | |
4248 | ||
4249 | net_stats->collisions = | |
4250 | (unsigned long) stats_blk->stat_EtherStatsCollisions; | |
4251 | ||
4252 | net_stats->rx_length_errors = | |
4253 | (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts + | |
4254 | stats_blk->stat_EtherStatsOverrsizePkts); | |
4255 | ||
4256 | net_stats->rx_over_errors = | |
4257 | (unsigned long) stats_blk->stat_IfInMBUFDiscards; | |
4258 | ||
4259 | net_stats->rx_frame_errors = | |
4260 | (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors; | |
4261 | ||
4262 | net_stats->rx_crc_errors = | |
4263 | (unsigned long) stats_blk->stat_Dot3StatsFCSErrors; | |
4264 | ||
4265 | net_stats->rx_errors = net_stats->rx_length_errors + | |
4266 | net_stats->rx_over_errors + net_stats->rx_frame_errors + | |
4267 | net_stats->rx_crc_errors; | |
4268 | ||
4269 | net_stats->tx_aborted_errors = | |
4270 | (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions + | |
4271 | stats_blk->stat_Dot3StatsLateCollisions); | |
4272 | ||
4273 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | |
4274 | net_stats->tx_carrier_errors = 0; | |
4275 | else { | |
4276 | net_stats->tx_carrier_errors = | |
4277 | (unsigned long) | |
4278 | stats_blk->stat_Dot3StatsCarrierSenseErrors; | |
4279 | } | |
4280 | ||
4281 | net_stats->tx_errors = | |
4282 | (unsigned long) | |
4283 | stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors | |
4284 | + | |
4285 | net_stats->tx_aborted_errors + | |
4286 | net_stats->tx_carrier_errors; | |
4287 | ||
4288 | return net_stats; | |
4289 | } | |
4290 | ||
4291 | /* All ethtool functions called with rtnl_lock */ | |
4292 | ||
4293 | static int | |
4294 | bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
4295 | { | |
4296 | struct bnx2 *bp = dev->priv; | |
4297 | ||
4298 | cmd->supported = SUPPORTED_Autoneg; | |
4299 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
4300 | cmd->supported |= SUPPORTED_1000baseT_Full | | |
4301 | SUPPORTED_FIBRE; | |
4302 | ||
4303 | cmd->port = PORT_FIBRE; | |
4304 | } | |
4305 | else { | |
4306 | cmd->supported |= SUPPORTED_10baseT_Half | | |
4307 | SUPPORTED_10baseT_Full | | |
4308 | SUPPORTED_100baseT_Half | | |
4309 | SUPPORTED_100baseT_Full | | |
4310 | SUPPORTED_1000baseT_Full | | |
4311 | SUPPORTED_TP; | |
4312 | ||
4313 | cmd->port = PORT_TP; | |
4314 | } | |
4315 | ||
4316 | cmd->advertising = bp->advertising; | |
4317 | ||
4318 | if (bp->autoneg & AUTONEG_SPEED) { | |
4319 | cmd->autoneg = AUTONEG_ENABLE; | |
4320 | } | |
4321 | else { | |
4322 | cmd->autoneg = AUTONEG_DISABLE; | |
4323 | } | |
4324 | ||
4325 | if (netif_carrier_ok(dev)) { | |
4326 | cmd->speed = bp->line_speed; | |
4327 | cmd->duplex = bp->duplex; | |
4328 | } | |
4329 | else { | |
4330 | cmd->speed = -1; | |
4331 | cmd->duplex = -1; | |
4332 | } | |
4333 | ||
4334 | cmd->transceiver = XCVR_INTERNAL; | |
4335 | cmd->phy_address = bp->phy_addr; | |
4336 | ||
4337 | return 0; | |
4338 | } | |
4339 | ||
4340 | static int | |
4341 | bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
4342 | { | |
4343 | struct bnx2 *bp = dev->priv; | |
4344 | u8 autoneg = bp->autoneg; | |
4345 | u8 req_duplex = bp->req_duplex; | |
4346 | u16 req_line_speed = bp->req_line_speed; | |
4347 | u32 advertising = bp->advertising; | |
4348 | ||
4349 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
4350 | autoneg |= AUTONEG_SPEED; | |
4351 | ||
4352 | cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; | |
4353 | ||
4354 | /* allow advertising 1 speed */ | |
4355 | if ((cmd->advertising == ADVERTISED_10baseT_Half) || | |
4356 | (cmd->advertising == ADVERTISED_10baseT_Full) || | |
4357 | (cmd->advertising == ADVERTISED_100baseT_Half) || | |
4358 | (cmd->advertising == ADVERTISED_100baseT_Full)) { | |
4359 | ||
4360 | if (bp->phy_flags & PHY_SERDES_FLAG) | |
4361 | return -EINVAL; | |
4362 | ||
4363 | advertising = cmd->advertising; | |
4364 | ||
4365 | } | |
4366 | else if (cmd->advertising == ADVERTISED_1000baseT_Full) { | |
4367 | advertising = cmd->advertising; | |
4368 | } | |
4369 | else if (cmd->advertising == ADVERTISED_1000baseT_Half) { | |
4370 | return -EINVAL; | |
4371 | } | |
4372 | else { | |
4373 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
4374 | advertising = ETHTOOL_ALL_FIBRE_SPEED; | |
4375 | } | |
4376 | else { | |
4377 | advertising = ETHTOOL_ALL_COPPER_SPEED; | |
4378 | } | |
4379 | } | |
4380 | advertising |= ADVERTISED_Autoneg; | |
4381 | } | |
4382 | else { | |
4383 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
4384 | if ((cmd->speed != SPEED_1000) || | |
4385 | (cmd->duplex != DUPLEX_FULL)) { | |
4386 | return -EINVAL; | |
4387 | } | |
4388 | } | |
4389 | else if (cmd->speed == SPEED_1000) { | |
4390 | return -EINVAL; | |
4391 | } | |
4392 | autoneg &= ~AUTONEG_SPEED; | |
4393 | req_line_speed = cmd->speed; | |
4394 | req_duplex = cmd->duplex; | |
4395 | advertising = 0; | |
4396 | } | |
4397 | ||
4398 | bp->autoneg = autoneg; | |
4399 | bp->advertising = advertising; | |
4400 | bp->req_line_speed = req_line_speed; | |
4401 | bp->req_duplex = req_duplex; | |
4402 | ||
4403 | spin_lock_irq(&bp->phy_lock); | |
4404 | ||
4405 | bnx2_setup_phy(bp); | |
4406 | ||
4407 | spin_unlock_irq(&bp->phy_lock); | |
4408 | ||
4409 | return 0; | |
4410 | } | |
4411 | ||
4412 | static void | |
4413 | bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
4414 | { | |
4415 | struct bnx2 *bp = dev->priv; | |
4416 | ||
4417 | strcpy(info->driver, DRV_MODULE_NAME); | |
4418 | strcpy(info->version, DRV_MODULE_VERSION); | |
4419 | strcpy(info->bus_info, pci_name(bp->pdev)); | |
4420 | info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0'; | |
4421 | info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0'; | |
4422 | info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0'; | |
4423 | info->fw_version[6] = (bp->fw_ver & 0xff) + '0'; | |
4424 | info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.'; | |
4425 | info->fw_version[7] = 0; | |
4426 | } | |
4427 | ||
4428 | static void | |
4429 | bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
4430 | { | |
4431 | struct bnx2 *bp = dev->priv; | |
4432 | ||
4433 | if (bp->flags & NO_WOL_FLAG) { | |
4434 | wol->supported = 0; | |
4435 | wol->wolopts = 0; | |
4436 | } | |
4437 | else { | |
4438 | wol->supported = WAKE_MAGIC; | |
4439 | if (bp->wol) | |
4440 | wol->wolopts = WAKE_MAGIC; | |
4441 | else | |
4442 | wol->wolopts = 0; | |
4443 | } | |
4444 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
4445 | } | |
4446 | ||
4447 | static int | |
4448 | bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
4449 | { | |
4450 | struct bnx2 *bp = dev->priv; | |
4451 | ||
4452 | if (wol->wolopts & ~WAKE_MAGIC) | |
4453 | return -EINVAL; | |
4454 | ||
4455 | if (wol->wolopts & WAKE_MAGIC) { | |
4456 | if (bp->flags & NO_WOL_FLAG) | |
4457 | return -EINVAL; | |
4458 | ||
4459 | bp->wol = 1; | |
4460 | } | |
4461 | else { | |
4462 | bp->wol = 0; | |
4463 | } | |
4464 | return 0; | |
4465 | } | |
4466 | ||
4467 | static int | |
4468 | bnx2_nway_reset(struct net_device *dev) | |
4469 | { | |
4470 | struct bnx2 *bp = dev->priv; | |
4471 | u32 bmcr; | |
4472 | ||
4473 | if (!(bp->autoneg & AUTONEG_SPEED)) { | |
4474 | return -EINVAL; | |
4475 | } | |
4476 | ||
4477 | spin_lock_irq(&bp->phy_lock); | |
4478 | ||
4479 | /* Force a link down visible on the other side */ | |
4480 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
4481 | bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); | |
4482 | spin_unlock_irq(&bp->phy_lock); | |
4483 | ||
4484 | msleep(20); | |
4485 | ||
4486 | spin_lock_irq(&bp->phy_lock); | |
4487 | if (CHIP_NUM(bp) == CHIP_NUM_5706) { | |
4488 | bp->serdes_an_pending = SERDES_AN_TIMEOUT / | |
4489 | bp->timer_interval; | |
4490 | } | |
4491 | } | |
4492 | ||
4493 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | |
4494 | bmcr &= ~BMCR_LOOPBACK; | |
4495 | bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); | |
4496 | ||
4497 | spin_unlock_irq(&bp->phy_lock); | |
4498 | ||
4499 | return 0; | |
4500 | } | |
4501 | ||
4502 | static int | |
4503 | bnx2_get_eeprom_len(struct net_device *dev) | |
4504 | { | |
4505 | struct bnx2 *bp = dev->priv; | |
4506 | ||
4507 | if (bp->flash_info == 0) | |
4508 | return 0; | |
4509 | ||
4510 | return (int) bp->flash_info->total_size; | |
4511 | } | |
4512 | ||
4513 | static int | |
4514 | bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
4515 | u8 *eebuf) | |
4516 | { | |
4517 | struct bnx2 *bp = dev->priv; | |
4518 | int rc; | |
4519 | ||
4520 | if (eeprom->offset > bp->flash_info->total_size) | |
4521 | return -EINVAL; | |
4522 | ||
4523 | if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size) | |
4524 | eeprom->len = bp->flash_info->total_size - eeprom->offset; | |
4525 | ||
4526 | rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | |
4527 | ||
4528 | return rc; | |
4529 | } | |
4530 | ||
4531 | static int | |
4532 | bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
4533 | u8 *eebuf) | |
4534 | { | |
4535 | struct bnx2 *bp = dev->priv; | |
4536 | int rc; | |
4537 | ||
4538 | if (eeprom->offset > bp->flash_info->total_size) | |
4539 | return -EINVAL; | |
4540 | ||
4541 | if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size) | |
4542 | eeprom->len = bp->flash_info->total_size - eeprom->offset; | |
4543 | ||
4544 | rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | |
4545 | ||
4546 | return rc; | |
4547 | } | |
4548 | ||
4549 | static int | |
4550 | bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
4551 | { | |
4552 | struct bnx2 *bp = dev->priv; | |
4553 | ||
4554 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | |
4555 | ||
4556 | coal->rx_coalesce_usecs = bp->rx_ticks; | |
4557 | coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; | |
4558 | coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; | |
4559 | coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; | |
4560 | ||
4561 | coal->tx_coalesce_usecs = bp->tx_ticks; | |
4562 | coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; | |
4563 | coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; | |
4564 | coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; | |
4565 | ||
4566 | coal->stats_block_coalesce_usecs = bp->stats_ticks; | |
4567 | ||
4568 | return 0; | |
4569 | } | |
4570 | ||
4571 | static int | |
4572 | bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
4573 | { | |
4574 | struct bnx2 *bp = dev->priv; | |
4575 | ||
4576 | bp->rx_ticks = (u16) coal->rx_coalesce_usecs; | |
4577 | if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; | |
4578 | ||
4579 | bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; | |
4580 | if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; | |
4581 | ||
4582 | bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; | |
4583 | if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; | |
4584 | ||
4585 | bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; | |
4586 | if (bp->rx_quick_cons_trip_int > 0xff) | |
4587 | bp->rx_quick_cons_trip_int = 0xff; | |
4588 | ||
4589 | bp->tx_ticks = (u16) coal->tx_coalesce_usecs; | |
4590 | if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; | |
4591 | ||
4592 | bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; | |
4593 | if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; | |
4594 | ||
4595 | bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; | |
4596 | if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; | |
4597 | ||
4598 | bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; | |
4599 | if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = | |
4600 | 0xff; | |
4601 | ||
4602 | bp->stats_ticks = coal->stats_block_coalesce_usecs; | |
4603 | if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00; | |
4604 | bp->stats_ticks &= 0xffff00; | |
4605 | ||
4606 | if (netif_running(bp->dev)) { | |
4607 | bnx2_netif_stop(bp); | |
4608 | bnx2_init_nic(bp); | |
4609 | bnx2_netif_start(bp); | |
4610 | } | |
4611 | ||
4612 | return 0; | |
4613 | } | |
4614 | ||
4615 | static void | |
4616 | bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
4617 | { | |
4618 | struct bnx2 *bp = dev->priv; | |
4619 | ||
4620 | ering->rx_max_pending = MAX_RX_DESC_CNT; | |
4621 | ering->rx_mini_max_pending = 0; | |
4622 | ering->rx_jumbo_max_pending = 0; | |
4623 | ||
4624 | ering->rx_pending = bp->rx_ring_size; | |
4625 | ering->rx_mini_pending = 0; | |
4626 | ering->rx_jumbo_pending = 0; | |
4627 | ||
4628 | ering->tx_max_pending = MAX_TX_DESC_CNT; | |
4629 | ering->tx_pending = bp->tx_ring_size; | |
4630 | } | |
4631 | ||
4632 | static int | |
4633 | bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
4634 | { | |
4635 | struct bnx2 *bp = dev->priv; | |
4636 | ||
4637 | if ((ering->rx_pending > MAX_RX_DESC_CNT) || | |
4638 | (ering->tx_pending > MAX_TX_DESC_CNT) || | |
4639 | (ering->tx_pending <= MAX_SKB_FRAGS)) { | |
4640 | ||
4641 | return -EINVAL; | |
4642 | } | |
4643 | bp->rx_ring_size = ering->rx_pending; | |
4644 | bp->tx_ring_size = ering->tx_pending; | |
4645 | ||
4646 | if (netif_running(bp->dev)) { | |
4647 | bnx2_netif_stop(bp); | |
4648 | bnx2_init_nic(bp); | |
4649 | bnx2_netif_start(bp); | |
4650 | } | |
4651 | ||
4652 | return 0; | |
4653 | } | |
4654 | ||
4655 | static void | |
4656 | bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
4657 | { | |
4658 | struct bnx2 *bp = dev->priv; | |
4659 | ||
4660 | epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); | |
4661 | epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); | |
4662 | epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); | |
4663 | } | |
4664 | ||
4665 | static int | |
4666 | bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
4667 | { | |
4668 | struct bnx2 *bp = dev->priv; | |
4669 | ||
4670 | bp->req_flow_ctrl = 0; | |
4671 | if (epause->rx_pause) | |
4672 | bp->req_flow_ctrl |= FLOW_CTRL_RX; | |
4673 | if (epause->tx_pause) | |
4674 | bp->req_flow_ctrl |= FLOW_CTRL_TX; | |
4675 | ||
4676 | if (epause->autoneg) { | |
4677 | bp->autoneg |= AUTONEG_FLOW_CTRL; | |
4678 | } | |
4679 | else { | |
4680 | bp->autoneg &= ~AUTONEG_FLOW_CTRL; | |
4681 | } | |
4682 | ||
4683 | spin_lock_irq(&bp->phy_lock); | |
4684 | ||
4685 | bnx2_setup_phy(bp); | |
4686 | ||
4687 | spin_unlock_irq(&bp->phy_lock); | |
4688 | ||
4689 | return 0; | |
4690 | } | |
4691 | ||
4692 | static u32 | |
4693 | bnx2_get_rx_csum(struct net_device *dev) | |
4694 | { | |
4695 | struct bnx2 *bp = dev->priv; | |
4696 | ||
4697 | return bp->rx_csum; | |
4698 | } | |
4699 | ||
4700 | static int | |
4701 | bnx2_set_rx_csum(struct net_device *dev, u32 data) | |
4702 | { | |
4703 | struct bnx2 *bp = dev->priv; | |
4704 | ||
4705 | bp->rx_csum = data; | |
4706 | return 0; | |
4707 | } | |
4708 | ||
4709 | #define BNX2_NUM_STATS 45 | |
4710 | ||
14ab9b86 | 4711 | static struct { |
b6016b76 MC |
4712 | char string[ETH_GSTRING_LEN]; |
4713 | } bnx2_stats_str_arr[BNX2_NUM_STATS] = { | |
4714 | { "rx_bytes" }, | |
4715 | { "rx_error_bytes" }, | |
4716 | { "tx_bytes" }, | |
4717 | { "tx_error_bytes" }, | |
4718 | { "rx_ucast_packets" }, | |
4719 | { "rx_mcast_packets" }, | |
4720 | { "rx_bcast_packets" }, | |
4721 | { "tx_ucast_packets" }, | |
4722 | { "tx_mcast_packets" }, | |
4723 | { "tx_bcast_packets" }, | |
4724 | { "tx_mac_errors" }, | |
4725 | { "tx_carrier_errors" }, | |
4726 | { "rx_crc_errors" }, | |
4727 | { "rx_align_errors" }, | |
4728 | { "tx_single_collisions" }, | |
4729 | { "tx_multi_collisions" }, | |
4730 | { "tx_deferred" }, | |
4731 | { "tx_excess_collisions" }, | |
4732 | { "tx_late_collisions" }, | |
4733 | { "tx_total_collisions" }, | |
4734 | { "rx_fragments" }, | |
4735 | { "rx_jabbers" }, | |
4736 | { "rx_undersize_packets" }, | |
4737 | { "rx_oversize_packets" }, | |
4738 | { "rx_64_byte_packets" }, | |
4739 | { "rx_65_to_127_byte_packets" }, | |
4740 | { "rx_128_to_255_byte_packets" }, | |
4741 | { "rx_256_to_511_byte_packets" }, | |
4742 | { "rx_512_to_1023_byte_packets" }, | |
4743 | { "rx_1024_to_1522_byte_packets" }, | |
4744 | { "rx_1523_to_9022_byte_packets" }, | |
4745 | { "tx_64_byte_packets" }, | |
4746 | { "tx_65_to_127_byte_packets" }, | |
4747 | { "tx_128_to_255_byte_packets" }, | |
4748 | { "tx_256_to_511_byte_packets" }, | |
4749 | { "tx_512_to_1023_byte_packets" }, | |
4750 | { "tx_1024_to_1522_byte_packets" }, | |
4751 | { "tx_1523_to_9022_byte_packets" }, | |
4752 | { "rx_xon_frames" }, | |
4753 | { "rx_xoff_frames" }, | |
4754 | { "tx_xon_frames" }, | |
4755 | { "tx_xoff_frames" }, | |
4756 | { "rx_mac_ctrl_frames" }, | |
4757 | { "rx_filtered_packets" }, | |
4758 | { "rx_discards" }, | |
4759 | }; | |
4760 | ||
4761 | #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) | |
4762 | ||
14ab9b86 | 4763 | static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
4764 | STATS_OFFSET32(stat_IfHCInOctets_hi), |
4765 | STATS_OFFSET32(stat_IfHCInBadOctets_hi), | |
4766 | STATS_OFFSET32(stat_IfHCOutOctets_hi), | |
4767 | STATS_OFFSET32(stat_IfHCOutBadOctets_hi), | |
4768 | STATS_OFFSET32(stat_IfHCInUcastPkts_hi), | |
4769 | STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), | |
4770 | STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), | |
4771 | STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), | |
4772 | STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), | |
4773 | STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), | |
4774 | STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), | |
4775 | STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), | |
4776 | STATS_OFFSET32(stat_Dot3StatsFCSErrors), | |
4777 | STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), | |
4778 | STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), | |
4779 | STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), | |
4780 | STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), | |
4781 | STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), | |
4782 | STATS_OFFSET32(stat_Dot3StatsLateCollisions), | |
4783 | STATS_OFFSET32(stat_EtherStatsCollisions), | |
4784 | STATS_OFFSET32(stat_EtherStatsFragments), | |
4785 | STATS_OFFSET32(stat_EtherStatsJabbers), | |
4786 | STATS_OFFSET32(stat_EtherStatsUndersizePkts), | |
4787 | STATS_OFFSET32(stat_EtherStatsOverrsizePkts), | |
4788 | STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), | |
4789 | STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), | |
4790 | STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), | |
4791 | STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), | |
4792 | STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), | |
4793 | STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), | |
4794 | STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), | |
4795 | STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), | |
4796 | STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), | |
4797 | STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), | |
4798 | STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), | |
4799 | STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), | |
4800 | STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), | |
4801 | STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), | |
4802 | STATS_OFFSET32(stat_XonPauseFramesReceived), | |
4803 | STATS_OFFSET32(stat_XoffPauseFramesReceived), | |
4804 | STATS_OFFSET32(stat_OutXonSent), | |
4805 | STATS_OFFSET32(stat_OutXoffSent), | |
4806 | STATS_OFFSET32(stat_MacControlFramesReceived), | |
4807 | STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), | |
4808 | STATS_OFFSET32(stat_IfInMBUFDiscards), | |
4809 | }; | |
4810 | ||
4811 | /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are | |
4812 | * skipped because of errata. | |
4813 | */ | |
14ab9b86 | 4814 | static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
4815 | 8,0,8,8,8,8,8,8,8,8, |
4816 | 4,0,4,4,4,4,4,4,4,4, | |
4817 | 4,4,4,4,4,4,4,4,4,4, | |
4818 | 4,4,4,4,4,4,4,4,4,4, | |
4819 | 4,4,4,4,4, | |
4820 | }; | |
4821 | ||
4822 | #define BNX2_NUM_TESTS 6 | |
4823 | ||
14ab9b86 | 4824 | static struct { |
b6016b76 MC |
4825 | char string[ETH_GSTRING_LEN]; |
4826 | } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { | |
4827 | { "register_test (offline)" }, | |
4828 | { "memory_test (offline)" }, | |
4829 | { "loopback_test (offline)" }, | |
4830 | { "nvram_test (online)" }, | |
4831 | { "interrupt_test (online)" }, | |
4832 | { "link_test (online)" }, | |
4833 | }; | |
4834 | ||
4835 | static int | |
4836 | bnx2_self_test_count(struct net_device *dev) | |
4837 | { | |
4838 | return BNX2_NUM_TESTS; | |
4839 | } | |
4840 | ||
4841 | static void | |
4842 | bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) | |
4843 | { | |
4844 | struct bnx2 *bp = dev->priv; | |
4845 | ||
4846 | memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); | |
4847 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
4848 | bnx2_netif_stop(bp); | |
4849 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); | |
4850 | bnx2_free_skbs(bp); | |
4851 | ||
4852 | if (bnx2_test_registers(bp) != 0) { | |
4853 | buf[0] = 1; | |
4854 | etest->flags |= ETH_TEST_FL_FAILED; | |
4855 | } | |
4856 | if (bnx2_test_memory(bp) != 0) { | |
4857 | buf[1] = 1; | |
4858 | etest->flags |= ETH_TEST_FL_FAILED; | |
4859 | } | |
4860 | if (bnx2_test_loopback(bp) != 0) { | |
4861 | buf[2] = 1; | |
4862 | etest->flags |= ETH_TEST_FL_FAILED; | |
4863 | } | |
4864 | ||
4865 | if (!netif_running(bp->dev)) { | |
4866 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); | |
4867 | } | |
4868 | else { | |
4869 | bnx2_init_nic(bp); | |
4870 | bnx2_netif_start(bp); | |
4871 | } | |
4872 | ||
4873 | /* wait for link up */ | |
4874 | msleep_interruptible(3000); | |
4875 | if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG)) | |
4876 | msleep_interruptible(4000); | |
4877 | } | |
4878 | ||
4879 | if (bnx2_test_nvram(bp) != 0) { | |
4880 | buf[3] = 1; | |
4881 | etest->flags |= ETH_TEST_FL_FAILED; | |
4882 | } | |
4883 | if (bnx2_test_intr(bp) != 0) { | |
4884 | buf[4] = 1; | |
4885 | etest->flags |= ETH_TEST_FL_FAILED; | |
4886 | } | |
4887 | ||
4888 | if (bnx2_test_link(bp) != 0) { | |
4889 | buf[5] = 1; | |
4890 | etest->flags |= ETH_TEST_FL_FAILED; | |
4891 | ||
4892 | } | |
4893 | } | |
4894 | ||
4895 | static void | |
4896 | bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
4897 | { | |
4898 | switch (stringset) { | |
4899 | case ETH_SS_STATS: | |
4900 | memcpy(buf, bnx2_stats_str_arr, | |
4901 | sizeof(bnx2_stats_str_arr)); | |
4902 | break; | |
4903 | case ETH_SS_TEST: | |
4904 | memcpy(buf, bnx2_tests_str_arr, | |
4905 | sizeof(bnx2_tests_str_arr)); | |
4906 | break; | |
4907 | } | |
4908 | } | |
4909 | ||
4910 | static int | |
4911 | bnx2_get_stats_count(struct net_device *dev) | |
4912 | { | |
4913 | return BNX2_NUM_STATS; | |
4914 | } | |
4915 | ||
4916 | static void | |
4917 | bnx2_get_ethtool_stats(struct net_device *dev, | |
4918 | struct ethtool_stats *stats, u64 *buf) | |
4919 | { | |
4920 | struct bnx2 *bp = dev->priv; | |
4921 | int i; | |
4922 | u32 *hw_stats = (u32 *) bp->stats_blk; | |
14ab9b86 | 4923 | u8 *stats_len_arr = NULL; |
b6016b76 MC |
4924 | |
4925 | if (hw_stats == NULL) { | |
4926 | memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); | |
4927 | return; | |
4928 | } | |
4929 | ||
4930 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | |
4931 | stats_len_arr = bnx2_5706_stats_len_arr; | |
4932 | ||
4933 | for (i = 0; i < BNX2_NUM_STATS; i++) { | |
4934 | if (stats_len_arr[i] == 0) { | |
4935 | /* skip this counter */ | |
4936 | buf[i] = 0; | |
4937 | continue; | |
4938 | } | |
4939 | if (stats_len_arr[i] == 4) { | |
4940 | /* 4-byte counter */ | |
4941 | buf[i] = (u64) | |
4942 | *(hw_stats + bnx2_stats_offset_arr[i]); | |
4943 | continue; | |
4944 | } | |
4945 | /* 8-byte counter */ | |
4946 | buf[i] = (((u64) *(hw_stats + | |
4947 | bnx2_stats_offset_arr[i])) << 32) + | |
4948 | *(hw_stats + bnx2_stats_offset_arr[i] + 1); | |
4949 | } | |
4950 | } | |
4951 | ||
4952 | static int | |
4953 | bnx2_phys_id(struct net_device *dev, u32 data) | |
4954 | { | |
4955 | struct bnx2 *bp = dev->priv; | |
4956 | int i; | |
4957 | u32 save; | |
4958 | ||
4959 | if (data == 0) | |
4960 | data = 2; | |
4961 | ||
4962 | save = REG_RD(bp, BNX2_MISC_CFG); | |
4963 | REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); | |
4964 | ||
4965 | for (i = 0; i < (data * 2); i++) { | |
4966 | if ((i % 2) == 0) { | |
4967 | REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); | |
4968 | } | |
4969 | else { | |
4970 | REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | | |
4971 | BNX2_EMAC_LED_1000MB_OVERRIDE | | |
4972 | BNX2_EMAC_LED_100MB_OVERRIDE | | |
4973 | BNX2_EMAC_LED_10MB_OVERRIDE | | |
4974 | BNX2_EMAC_LED_TRAFFIC_OVERRIDE | | |
4975 | BNX2_EMAC_LED_TRAFFIC); | |
4976 | } | |
4977 | msleep_interruptible(500); | |
4978 | if (signal_pending(current)) | |
4979 | break; | |
4980 | } | |
4981 | REG_WR(bp, BNX2_EMAC_LED, 0); | |
4982 | REG_WR(bp, BNX2_MISC_CFG, save); | |
4983 | return 0; | |
4984 | } | |
4985 | ||
4986 | static struct ethtool_ops bnx2_ethtool_ops = { | |
4987 | .get_settings = bnx2_get_settings, | |
4988 | .set_settings = bnx2_set_settings, | |
4989 | .get_drvinfo = bnx2_get_drvinfo, | |
4990 | .get_wol = bnx2_get_wol, | |
4991 | .set_wol = bnx2_set_wol, | |
4992 | .nway_reset = bnx2_nway_reset, | |
4993 | .get_link = ethtool_op_get_link, | |
4994 | .get_eeprom_len = bnx2_get_eeprom_len, | |
4995 | .get_eeprom = bnx2_get_eeprom, | |
4996 | .set_eeprom = bnx2_set_eeprom, | |
4997 | .get_coalesce = bnx2_get_coalesce, | |
4998 | .set_coalesce = bnx2_set_coalesce, | |
4999 | .get_ringparam = bnx2_get_ringparam, | |
5000 | .set_ringparam = bnx2_set_ringparam, | |
5001 | .get_pauseparam = bnx2_get_pauseparam, | |
5002 | .set_pauseparam = bnx2_set_pauseparam, | |
5003 | .get_rx_csum = bnx2_get_rx_csum, | |
5004 | .set_rx_csum = bnx2_set_rx_csum, | |
5005 | .get_tx_csum = ethtool_op_get_tx_csum, | |
5006 | .set_tx_csum = ethtool_op_set_tx_csum, | |
5007 | .get_sg = ethtool_op_get_sg, | |
5008 | .set_sg = ethtool_op_set_sg, | |
5009 | #ifdef BCM_TSO | |
5010 | .get_tso = ethtool_op_get_tso, | |
5011 | .set_tso = ethtool_op_set_tso, | |
5012 | #endif | |
5013 | .self_test_count = bnx2_self_test_count, | |
5014 | .self_test = bnx2_self_test, | |
5015 | .get_strings = bnx2_get_strings, | |
5016 | .phys_id = bnx2_phys_id, | |
5017 | .get_stats_count = bnx2_get_stats_count, | |
5018 | .get_ethtool_stats = bnx2_get_ethtool_stats, | |
5019 | }; | |
5020 | ||
5021 | /* Called with rtnl_lock */ | |
5022 | static int | |
5023 | bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
5024 | { | |
14ab9b86 | 5025 | struct mii_ioctl_data *data = if_mii(ifr); |
b6016b76 MC |
5026 | struct bnx2 *bp = dev->priv; |
5027 | int err; | |
5028 | ||
5029 | switch(cmd) { | |
5030 | case SIOCGMIIPHY: | |
5031 | data->phy_id = bp->phy_addr; | |
5032 | ||
5033 | /* fallthru */ | |
5034 | case SIOCGMIIREG: { | |
5035 | u32 mii_regval; | |
5036 | ||
5037 | spin_lock_irq(&bp->phy_lock); | |
5038 | err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); | |
5039 | spin_unlock_irq(&bp->phy_lock); | |
5040 | ||
5041 | data->val_out = mii_regval; | |
5042 | ||
5043 | return err; | |
5044 | } | |
5045 | ||
5046 | case SIOCSMIIREG: | |
5047 | if (!capable(CAP_NET_ADMIN)) | |
5048 | return -EPERM; | |
5049 | ||
5050 | spin_lock_irq(&bp->phy_lock); | |
5051 | err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); | |
5052 | spin_unlock_irq(&bp->phy_lock); | |
5053 | ||
5054 | return err; | |
5055 | ||
5056 | default: | |
5057 | /* do nothing */ | |
5058 | break; | |
5059 | } | |
5060 | return -EOPNOTSUPP; | |
5061 | } | |
5062 | ||
5063 | /* Called with rtnl_lock */ | |
5064 | static int | |
5065 | bnx2_change_mac_addr(struct net_device *dev, void *p) | |
5066 | { | |
5067 | struct sockaddr *addr = p; | |
5068 | struct bnx2 *bp = dev->priv; | |
5069 | ||
5070 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
5071 | if (netif_running(dev)) | |
5072 | bnx2_set_mac_addr(bp); | |
5073 | ||
5074 | return 0; | |
5075 | } | |
5076 | ||
5077 | /* Called with rtnl_lock */ | |
5078 | static int | |
5079 | bnx2_change_mtu(struct net_device *dev, int new_mtu) | |
5080 | { | |
5081 | struct bnx2 *bp = dev->priv; | |
5082 | ||
5083 | if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || | |
5084 | ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) | |
5085 | return -EINVAL; | |
5086 | ||
5087 | dev->mtu = new_mtu; | |
5088 | if (netif_running(dev)) { | |
5089 | bnx2_netif_stop(bp); | |
5090 | ||
5091 | bnx2_init_nic(bp); | |
5092 | ||
5093 | bnx2_netif_start(bp); | |
5094 | } | |
5095 | return 0; | |
5096 | } | |
5097 | ||
5098 | #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) | |
5099 | static void | |
5100 | poll_bnx2(struct net_device *dev) | |
5101 | { | |
5102 | struct bnx2 *bp = dev->priv; | |
5103 | ||
5104 | disable_irq(bp->pdev->irq); | |
5105 | bnx2_interrupt(bp->pdev->irq, dev, NULL); | |
5106 | enable_irq(bp->pdev->irq); | |
5107 | } | |
5108 | #endif | |
5109 | ||
5110 | static int __devinit | |
5111 | bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |
5112 | { | |
5113 | struct bnx2 *bp; | |
5114 | unsigned long mem_len; | |
5115 | int rc; | |
5116 | u32 reg; | |
5117 | ||
5118 | SET_MODULE_OWNER(dev); | |
5119 | SET_NETDEV_DEV(dev, &pdev->dev); | |
5120 | bp = dev->priv; | |
5121 | ||
5122 | bp->flags = 0; | |
5123 | bp->phy_flags = 0; | |
5124 | ||
5125 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ | |
5126 | rc = pci_enable_device(pdev); | |
5127 | if (rc) { | |
5128 | printk(KERN_ERR PFX "Cannot enable PCI device, aborting."); | |
5129 | goto err_out; | |
5130 | } | |
5131 | ||
5132 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
5133 | printk(KERN_ERR PFX "Cannot find PCI device base address, " | |
5134 | "aborting.\n"); | |
5135 | rc = -ENODEV; | |
5136 | goto err_out_disable; | |
5137 | } | |
5138 | ||
5139 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
5140 | if (rc) { | |
5141 | printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n"); | |
5142 | goto err_out_disable; | |
5143 | } | |
5144 | ||
5145 | pci_set_master(pdev); | |
5146 | ||
5147 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
5148 | if (bp->pm_cap == 0) { | |
5149 | printk(KERN_ERR PFX "Cannot find power management capability, " | |
5150 | "aborting.\n"); | |
5151 | rc = -EIO; | |
5152 | goto err_out_release; | |
5153 | } | |
5154 | ||
5155 | bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); | |
5156 | if (bp->pcix_cap == 0) { | |
5157 | printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n"); | |
5158 | rc = -EIO; | |
5159 | goto err_out_release; | |
5160 | } | |
5161 | ||
5162 | if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) { | |
5163 | bp->flags |= USING_DAC_FLAG; | |
5164 | if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) { | |
5165 | printk(KERN_ERR PFX "pci_set_consistent_dma_mask " | |
5166 | "failed, aborting.\n"); | |
5167 | rc = -EIO; | |
5168 | goto err_out_release; | |
5169 | } | |
5170 | } | |
5171 | else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) { | |
5172 | printk(KERN_ERR PFX "System does not support DMA, aborting.\n"); | |
5173 | rc = -EIO; | |
5174 | goto err_out_release; | |
5175 | } | |
5176 | ||
5177 | bp->dev = dev; | |
5178 | bp->pdev = pdev; | |
5179 | ||
5180 | spin_lock_init(&bp->phy_lock); | |
5181 | spin_lock_init(&bp->tx_lock); | |
5182 | INIT_WORK(&bp->reset_task, bnx2_reset_task, bp); | |
5183 | ||
5184 | dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); | |
5185 | mem_len = MB_GET_CID_ADDR(17); | |
5186 | dev->mem_end = dev->mem_start + mem_len; | |
5187 | dev->irq = pdev->irq; | |
5188 | ||
5189 | bp->regview = ioremap_nocache(dev->base_addr, mem_len); | |
5190 | ||
5191 | if (!bp->regview) { | |
5192 | printk(KERN_ERR PFX "Cannot map register space, aborting.\n"); | |
5193 | rc = -ENOMEM; | |
5194 | goto err_out_release; | |
5195 | } | |
5196 | ||
5197 | /* Configure byte swap and enable write to the reg_window registers. | |
5198 | * Rely on CPU to do target byte swapping on big endian systems | |
5199 | * The chip's target access swapping will not swap all accesses | |
5200 | */ | |
5201 | pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, | |
5202 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
5203 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); | |
5204 | ||
5205 | bnx2_set_power_state(bp, 0); | |
5206 | ||
5207 | bp->chip_id = REG_RD(bp, BNX2_MISC_ID); | |
5208 | ||
5209 | bp->phy_addr = 1; | |
5210 | ||
5211 | /* Get bus information. */ | |
5212 | reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); | |
5213 | if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { | |
5214 | u32 clkreg; | |
5215 | ||
5216 | bp->flags |= PCIX_FLAG; | |
5217 | ||
5218 | clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); | |
5219 | ||
5220 | clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; | |
5221 | switch (clkreg) { | |
5222 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: | |
5223 | bp->bus_speed_mhz = 133; | |
5224 | break; | |
5225 | ||
5226 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: | |
5227 | bp->bus_speed_mhz = 100; | |
5228 | break; | |
5229 | ||
5230 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: | |
5231 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: | |
5232 | bp->bus_speed_mhz = 66; | |
5233 | break; | |
5234 | ||
5235 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: | |
5236 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: | |
5237 | bp->bus_speed_mhz = 50; | |
5238 | break; | |
5239 | ||
5240 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: | |
5241 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: | |
5242 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: | |
5243 | bp->bus_speed_mhz = 33; | |
5244 | break; | |
5245 | } | |
5246 | } | |
5247 | else { | |
5248 | if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) | |
5249 | bp->bus_speed_mhz = 66; | |
5250 | else | |
5251 | bp->bus_speed_mhz = 33; | |
5252 | } | |
5253 | ||
5254 | if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) | |
5255 | bp->flags |= PCI_32BIT_FLAG; | |
5256 | ||
5257 | /* 5706A0 may falsely detect SERR and PERR. */ | |
5258 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
5259 | reg = REG_RD(bp, PCI_COMMAND); | |
5260 | reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); | |
5261 | REG_WR(bp, PCI_COMMAND, reg); | |
5262 | } | |
5263 | else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && | |
5264 | !(bp->flags & PCIX_FLAG)) { | |
5265 | ||
5266 | printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, " | |
5267 | "aborting.\n"); | |
5268 | goto err_out_unmap; | |
5269 | } | |
5270 | ||
5271 | bnx2_init_nvram(bp); | |
5272 | ||
5273 | /* Get the permanent MAC address. First we need to make sure the | |
5274 | * firmware is actually running. | |
5275 | */ | |
5276 | reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE); | |
5277 | ||
5278 | if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != | |
5279 | BNX2_DEV_INFO_SIGNATURE_MAGIC) { | |
5280 | printk(KERN_ERR PFX "Firmware not running, aborting.\n"); | |
5281 | rc = -ENODEV; | |
5282 | goto err_out_unmap; | |
5283 | } | |
5284 | ||
5285 | bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + | |
5286 | BNX2_DEV_INFO_BC_REV); | |
5287 | ||
5288 | reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER); | |
5289 | bp->mac_addr[0] = (u8) (reg >> 8); | |
5290 | bp->mac_addr[1] = (u8) reg; | |
5291 | ||
5292 | reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER); | |
5293 | bp->mac_addr[2] = (u8) (reg >> 24); | |
5294 | bp->mac_addr[3] = (u8) (reg >> 16); | |
5295 | bp->mac_addr[4] = (u8) (reg >> 8); | |
5296 | bp->mac_addr[5] = (u8) reg; | |
5297 | ||
5298 | bp->tx_ring_size = MAX_TX_DESC_CNT; | |
5299 | bp->rx_ring_size = 100; | |
5300 | ||
5301 | bp->rx_csum = 1; | |
5302 | ||
5303 | bp->rx_offset = sizeof(struct l2_fhdr) + 2; | |
5304 | ||
5305 | bp->tx_quick_cons_trip_int = 20; | |
5306 | bp->tx_quick_cons_trip = 20; | |
5307 | bp->tx_ticks_int = 80; | |
5308 | bp->tx_ticks = 80; | |
5309 | ||
5310 | bp->rx_quick_cons_trip_int = 6; | |
5311 | bp->rx_quick_cons_trip = 6; | |
5312 | bp->rx_ticks_int = 18; | |
5313 | bp->rx_ticks = 18; | |
5314 | ||
5315 | bp->stats_ticks = 1000000 & 0xffff00; | |
5316 | ||
5317 | bp->timer_interval = HZ; | |
5318 | ||
5319 | /* Disable WOL support if we are running on a SERDES chip. */ | |
5320 | if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) { | |
5321 | bp->phy_flags |= PHY_SERDES_FLAG; | |
5322 | bp->flags |= NO_WOL_FLAG; | |
5323 | } | |
5324 | ||
5325 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | |
5326 | bp->tx_quick_cons_trip_int = | |
5327 | bp->tx_quick_cons_trip; | |
5328 | bp->tx_ticks_int = bp->tx_ticks; | |
5329 | bp->rx_quick_cons_trip_int = | |
5330 | bp->rx_quick_cons_trip; | |
5331 | bp->rx_ticks_int = bp->rx_ticks; | |
5332 | bp->comp_prod_trip_int = bp->comp_prod_trip; | |
5333 | bp->com_ticks_int = bp->com_ticks; | |
5334 | bp->cmd_ticks_int = bp->cmd_ticks; | |
5335 | } | |
5336 | ||
5337 | bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; | |
5338 | bp->req_line_speed = 0; | |
5339 | if (bp->phy_flags & PHY_SERDES_FLAG) { | |
5340 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; | |
5341 | } | |
5342 | else { | |
5343 | bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; | |
5344 | } | |
5345 | ||
5346 | bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; | |
5347 | ||
5348 | return 0; | |
5349 | ||
5350 | err_out_unmap: | |
5351 | if (bp->regview) { | |
5352 | iounmap(bp->regview); | |
5353 | } | |
5354 | ||
5355 | err_out_release: | |
5356 | pci_release_regions(pdev); | |
5357 | ||
5358 | err_out_disable: | |
5359 | pci_disable_device(pdev); | |
5360 | pci_set_drvdata(pdev, NULL); | |
5361 | ||
5362 | err_out: | |
5363 | return rc; | |
5364 | } | |
5365 | ||
5366 | static int __devinit | |
5367 | bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
5368 | { | |
5369 | static int version_printed = 0; | |
5370 | struct net_device *dev = NULL; | |
5371 | struct bnx2 *bp; | |
5372 | int rc, i; | |
5373 | ||
5374 | if (version_printed++ == 0) | |
5375 | printk(KERN_INFO "%s", version); | |
5376 | ||
5377 | /* dev zeroed in init_etherdev */ | |
5378 | dev = alloc_etherdev(sizeof(*bp)); | |
5379 | ||
5380 | if (!dev) | |
5381 | return -ENOMEM; | |
5382 | ||
5383 | rc = bnx2_init_board(pdev, dev); | |
5384 | if (rc < 0) { | |
5385 | free_netdev(dev); | |
5386 | return rc; | |
5387 | } | |
5388 | ||
5389 | dev->open = bnx2_open; | |
5390 | dev->hard_start_xmit = bnx2_start_xmit; | |
5391 | dev->stop = bnx2_close; | |
5392 | dev->get_stats = bnx2_get_stats; | |
5393 | dev->set_multicast_list = bnx2_set_rx_mode; | |
5394 | dev->do_ioctl = bnx2_ioctl; | |
5395 | dev->set_mac_address = bnx2_change_mac_addr; | |
5396 | dev->change_mtu = bnx2_change_mtu; | |
5397 | dev->tx_timeout = bnx2_tx_timeout; | |
5398 | dev->watchdog_timeo = TX_TIMEOUT; | |
5399 | #ifdef BCM_VLAN | |
5400 | dev->vlan_rx_register = bnx2_vlan_rx_register; | |
5401 | dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid; | |
5402 | #endif | |
5403 | dev->poll = bnx2_poll; | |
5404 | dev->ethtool_ops = &bnx2_ethtool_ops; | |
5405 | dev->weight = 64; | |
5406 | ||
5407 | bp = dev->priv; | |
5408 | ||
5409 | #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) | |
5410 | dev->poll_controller = poll_bnx2; | |
5411 | #endif | |
5412 | ||
5413 | if ((rc = register_netdev(dev))) { | |
5414 | printk(KERN_ERR PFX "Cannot register net device\n"); | |
5415 | if (bp->regview) | |
5416 | iounmap(bp->regview); | |
5417 | pci_release_regions(pdev); | |
5418 | pci_disable_device(pdev); | |
5419 | pci_set_drvdata(pdev, NULL); | |
5420 | free_netdev(dev); | |
5421 | return rc; | |
5422 | } | |
5423 | ||
5424 | pci_set_drvdata(pdev, dev); | |
5425 | ||
5426 | memcpy(dev->dev_addr, bp->mac_addr, 6); | |
5427 | bp->name = board_info[ent->driver_data].name, | |
5428 | printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, " | |
5429 | "IRQ %d, ", | |
5430 | dev->name, | |
5431 | bp->name, | |
5432 | ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', | |
5433 | ((CHIP_ID(bp) & 0x0ff0) >> 4), | |
5434 | ((bp->flags & PCIX_FLAG) ? "-X" : ""), | |
5435 | ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), | |
5436 | bp->bus_speed_mhz, | |
5437 | dev->base_addr, | |
5438 | bp->pdev->irq); | |
5439 | ||
5440 | printk("node addr "); | |
5441 | for (i = 0; i < 6; i++) | |
5442 | printk("%2.2x", dev->dev_addr[i]); | |
5443 | printk("\n"); | |
5444 | ||
5445 | dev->features |= NETIF_F_SG; | |
5446 | if (bp->flags & USING_DAC_FLAG) | |
5447 | dev->features |= NETIF_F_HIGHDMA; | |
5448 | dev->features |= NETIF_F_IP_CSUM; | |
5449 | #ifdef BCM_VLAN | |
5450 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
5451 | #endif | |
5452 | #ifdef BCM_TSO | |
5453 | dev->features |= NETIF_F_TSO; | |
5454 | #endif | |
5455 | ||
5456 | netif_carrier_off(bp->dev); | |
5457 | ||
5458 | return 0; | |
5459 | } | |
5460 | ||
5461 | static void __devexit | |
5462 | bnx2_remove_one(struct pci_dev *pdev) | |
5463 | { | |
5464 | struct net_device *dev = pci_get_drvdata(pdev); | |
5465 | struct bnx2 *bp = dev->priv; | |
5466 | ||
afdc08b9 MC |
5467 | flush_scheduled_work(); |
5468 | ||
b6016b76 MC |
5469 | unregister_netdev(dev); |
5470 | ||
5471 | if (bp->regview) | |
5472 | iounmap(bp->regview); | |
5473 | ||
5474 | free_netdev(dev); | |
5475 | pci_release_regions(pdev); | |
5476 | pci_disable_device(pdev); | |
5477 | pci_set_drvdata(pdev, NULL); | |
5478 | } | |
5479 | ||
5480 | static int | |
5481 | bnx2_suspend(struct pci_dev *pdev, u32 state) | |
5482 | { | |
5483 | struct net_device *dev = pci_get_drvdata(pdev); | |
5484 | struct bnx2 *bp = dev->priv; | |
5485 | u32 reset_code; | |
5486 | ||
5487 | if (!netif_running(dev)) | |
5488 | return 0; | |
5489 | ||
5490 | bnx2_netif_stop(bp); | |
5491 | netif_device_detach(dev); | |
5492 | del_timer_sync(&bp->timer); | |
5493 | if (bp->wol) | |
5494 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
5495 | else | |
5496 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
5497 | bnx2_reset_chip(bp, reset_code); | |
5498 | bnx2_free_skbs(bp); | |
5499 | bnx2_set_power_state(bp, state); | |
5500 | return 0; | |
5501 | } | |
5502 | ||
5503 | static int | |
5504 | bnx2_resume(struct pci_dev *pdev) | |
5505 | { | |
5506 | struct net_device *dev = pci_get_drvdata(pdev); | |
5507 | struct bnx2 *bp = dev->priv; | |
5508 | ||
5509 | if (!netif_running(dev)) | |
5510 | return 0; | |
5511 | ||
5512 | bnx2_set_power_state(bp, 0); | |
5513 | netif_device_attach(dev); | |
5514 | bnx2_init_nic(bp); | |
5515 | bnx2_netif_start(bp); | |
5516 | return 0; | |
5517 | } | |
5518 | ||
5519 | static struct pci_driver bnx2_pci_driver = { | |
14ab9b86 PH |
5520 | .name = DRV_MODULE_NAME, |
5521 | .id_table = bnx2_pci_tbl, | |
5522 | .probe = bnx2_init_one, | |
5523 | .remove = __devexit_p(bnx2_remove_one), | |
5524 | .suspend = bnx2_suspend, | |
5525 | .resume = bnx2_resume, | |
b6016b76 MC |
5526 | }; |
5527 | ||
5528 | static int __init bnx2_init(void) | |
5529 | { | |
5530 | return pci_module_init(&bnx2_pci_driver); | |
5531 | } | |
5532 | ||
5533 | static void __exit bnx2_cleanup(void) | |
5534 | { | |
5535 | pci_unregister_driver(&bnx2_pci_driver); | |
5536 | } | |
5537 | ||
5538 | module_init(bnx2_init); | |
5539 | module_exit(bnx2_cleanup); | |
5540 | ||
5541 | ||
5542 |