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be2net: Patch to flash redboot section while firmware update.
[net-next-2.6.git] / drivers / net / benet / be_cmds.h
CommitLineData
6b7c5b94
SP		 1/*
2 * Copyright (C) 2005 - 2009 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
b31c50a7 64 MCC_STATUS_DMA_FAILED = 0x5,
49643848 65 MCC_STATUS_NOT_SUPPORTED = 66
6b7c5b94
SP		 66};
67
68#define CQE_STATUS_COMPL_MASK 0xFFFF
69#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70#define CQE_STATUS_EXTD_MASK 0xFFFF
f5209b44 71#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
6b7c5b94 72
efd2e40a 73struct be_mcc_compl {
6b7c5b94
SP		 74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78};
79
a8f447bd
SP		 80/* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85#define ASYNC_EVENT_CODE_LINK_STATE 0x1
86struct be_async_event_trailer {
87 u32 code;
88};
89
90enum {
91 ASYNC_EVENT_LINK_DOWN = 0x0,
92 ASYNC_EVENT_LINK_UP = 0x1
93};
94
95/* When the event code of an async trailer is link-state, the mcc_compl
96 * must be interpreted as follows
97 */
98struct be_async_event_link_state {
99 u8 physical_port;
100 u8 port_link_status;
101 u8 port_duplex;
102 u8 port_speed;
103 u8 port_fault;
104 u8 rsvd0[7];
105 struct be_async_event_trailer trailer;
106} __packed;
107
6b7c5b94
SP		 108struct be_mcc_mailbox {
109 struct be_mcc_wrb wrb;
efd2e40a 110 struct be_mcc_compl compl;
6b7c5b94
SP		 111};
112
113#define CMD_SUBSYSTEM_COMMON 0x1
114#define CMD_SUBSYSTEM_ETH 0x3
115
116#define OPCODE_COMMON_NTWK_MAC_QUERY 1
117#define OPCODE_COMMON_NTWK_MAC_SET 2
118#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
119#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
120#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 121#define OPCODE_COMMON_READ_FLASHROM 6
84517482 122#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 123#define OPCODE_COMMON_CQ_CREATE 12
124#define OPCODE_COMMON_EQ_CREATE 13
125#define OPCODE_COMMON_MCC_CREATE 21
126#define OPCODE_COMMON_NTWK_RX_FILTER 34
127#define OPCODE_COMMON_GET_FW_VERSION 35
128#define OPCODE_COMMON_SET_FLOW_CONTROL 36
129#define OPCODE_COMMON_GET_FLOW_CONTROL 37
130#define OPCODE_COMMON_SET_FRAME_SIZE 39
131#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
132#define OPCODE_COMMON_FIRMWARE_CONFIG 42
133#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
134#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 135#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 136#define OPCODE_COMMON_CQ_DESTROY 54
137#define OPCODE_COMMON_EQ_DESTROY 55
138#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
139#define OPCODE_COMMON_NTWK_PMAC_ADD 59
140#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 141#define OPCODE_COMMON_FUNCTION_RESET 61
fad9ab2c
SB		 142#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
143#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 144#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
6b7c5b94
SP		 145
146#define OPCODE_ETH_ACPI_CONFIG 2
147#define OPCODE_ETH_PROMISCUOUS 3
148#define OPCODE_ETH_GET_STATISTICS 4
149#define OPCODE_ETH_TX_CREATE 7
150#define OPCODE_ETH_RX_CREATE 8
151#define OPCODE_ETH_TX_DESTROY 9
152#define OPCODE_ETH_RX_DESTROY 10
153
154struct be_cmd_req_hdr {
155 u8 opcode; /* dword 0 */
156 u8 subsystem; /* dword 0 */
157 u8 port_number; /* dword 0 */
158 u8 domain; /* dword 0 */
159 u32 timeout; /* dword 1 */
160 u32 request_length; /* dword 2 */
161 u32 rsvd; /* dword 3 */
162};
163
164#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
165#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
166struct be_cmd_resp_hdr {
167 u32 info; /* dword 0 */
168 u32 status; /* dword 1 */
169 u32 response_length; /* dword 2 */
170 u32 actual_resp_len; /* dword 3 */
171};
172
173struct phys_addr {
174 u32 lo;
175 u32 hi;
176};
177
178/**************************
179 * BE Command definitions *
180 **************************/
181
182/* Pseudo amap definition in which each bit of the actual structure is defined
183 * as a byte: used to calculate offset/shift/mask of each field */
184struct amap_eq_context {
185 u8 cidx[13]; /* dword 0*/
186 u8 rsvd0[3]; /* dword 0*/
187 u8 epidx[13]; /* dword 0*/
188 u8 valid; /* dword 0*/
189 u8 rsvd1; /* dword 0*/
190 u8 size; /* dword 0*/
191 u8 pidx[13]; /* dword 1*/
192 u8 rsvd2[3]; /* dword 1*/
193 u8 pd[10]; /* dword 1*/
194 u8 count[3]; /* dword 1*/
195 u8 solevent; /* dword 1*/
196 u8 stalled; /* dword 1*/
197 u8 armed; /* dword 1*/
198 u8 rsvd3[4]; /* dword 2*/
199 u8 func[8]; /* dword 2*/
200 u8 rsvd4; /* dword 2*/
201 u8 delaymult[10]; /* dword 2*/
202 u8 rsvd5[2]; /* dword 2*/
203 u8 phase[2]; /* dword 2*/
204 u8 nodelay; /* dword 2*/
205 u8 rsvd6[4]; /* dword 2*/
206 u8 rsvd7[32]; /* dword 3*/
207} __packed;
208
209struct be_cmd_req_eq_create {
210 struct be_cmd_req_hdr hdr;
211 u16 num_pages; /* sword */
212 u16 rsvd0; /* sword */
213 u8 context[sizeof(struct amap_eq_context) / 8];
214 struct phys_addr pages[8];
215} __packed;
216
217struct be_cmd_resp_eq_create {
218 struct be_cmd_resp_hdr resp_hdr;
219 u16 eq_id; /* sword */
220 u16 rsvd0; /* sword */
221} __packed;
222
223/******************** Mac query ***************************/
224enum {
225 MAC_ADDRESS_TYPE_STORAGE = 0x0,
226 MAC_ADDRESS_TYPE_NETWORK = 0x1,
227 MAC_ADDRESS_TYPE_PD = 0x2,
228 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
229};
230
231struct mac_addr {
232 u16 size_of_struct;
233 u8 addr[ETH_ALEN];
234} __packed;
235
236struct be_cmd_req_mac_query {
237 struct be_cmd_req_hdr hdr;
238 u8 type;
239 u8 permanent;
240 u16 if_id;
241} __packed;
242
243struct be_cmd_resp_mac_query {
244 struct be_cmd_resp_hdr hdr;
245 struct mac_addr mac;
246};
247
248/******************** PMac Add ***************************/
249struct be_cmd_req_pmac_add {
250 struct be_cmd_req_hdr hdr;
251 u32 if_id;
252 u8 mac_address[ETH_ALEN];
253 u8 rsvd0[2];
254} __packed;
255
256struct be_cmd_resp_pmac_add {
257 struct be_cmd_resp_hdr hdr;
258 u32 pmac_id;
259};
260
261/******************** PMac Del ***************************/
262struct be_cmd_req_pmac_del {
263 struct be_cmd_req_hdr hdr;
264 u32 if_id;
265 u32 pmac_id;
266};
267
268/******************** Create CQ ***************************/
269/* Pseudo amap definition in which each bit of the actual structure is defined
270 * as a byte: used to calculate offset/shift/mask of each field */
271struct amap_cq_context {
272 u8 cidx[11]; /* dword 0*/
273 u8 rsvd0; /* dword 0*/
274 u8 coalescwm[2]; /* dword 0*/
275 u8 nodelay; /* dword 0*/
276 u8 epidx[11]; /* dword 0*/
277 u8 rsvd1; /* dword 0*/
278 u8 count[2]; /* dword 0*/
279 u8 valid; /* dword 0*/
280 u8 solevent; /* dword 0*/
281 u8 eventable; /* dword 0*/
282 u8 pidx[11]; /* dword 1*/
283 u8 rsvd2; /* dword 1*/
284 u8 pd[10]; /* dword 1*/
285 u8 eqid[8]; /* dword 1*/
286 u8 stalled; /* dword 1*/
287 u8 armed; /* dword 1*/
288 u8 rsvd3[4]; /* dword 2*/
289 u8 func[8]; /* dword 2*/
290 u8 rsvd4[20]; /* dword 2*/
291 u8 rsvd5[32]; /* dword 3*/
292} __packed;
293
294struct be_cmd_req_cq_create {
295 struct be_cmd_req_hdr hdr;
296 u16 num_pages;
297 u16 rsvd0;
298 u8 context[sizeof(struct amap_cq_context) / 8];
299 struct phys_addr pages[8];
300} __packed;
301
302struct be_cmd_resp_cq_create {
303 struct be_cmd_resp_hdr hdr;
304 u16 cq_id;
305 u16 rsvd0;
306} __packed;
307
5fb379ee
SP		 308/******************** Create MCCQ ***************************/
309/* Pseudo amap definition in which each bit of the actual structure is defined
310 * as a byte: used to calculate offset/shift/mask of each field */
311struct amap_mcc_context {
312 u8 con_index[14];
313 u8 rsvd0[2];
314 u8 ring_size[4];
315 u8 fetch_wrb;
316 u8 fetch_r2t;
317 u8 cq_id[10];
318 u8 prod_index[14];
319 u8 fid[8];
320 u8 pdid[9];
321 u8 valid;
322 u8 rsvd1[32];
323 u8 rsvd2[32];
324} __packed;
325
326struct be_cmd_req_mcc_create {
327 struct be_cmd_req_hdr hdr;
328 u16 num_pages;
329 u16 rsvd0;
330 u8 context[sizeof(struct amap_mcc_context) / 8];
331 struct phys_addr pages[8];
332} __packed;
333
334struct be_cmd_resp_mcc_create {
335 struct be_cmd_resp_hdr hdr;
336 u16 id;
337 u16 rsvd0;
338} __packed;
339
6b7c5b94
SP		 340/******************** Create TxQ ***************************/
341#define BE_ETH_TX_RING_TYPE_STANDARD 2
342#define BE_ULP1_NUM 1
343
344/* Pseudo amap definition in which each bit of the actual structure is defined
345 * as a byte: used to calculate offset/shift/mask of each field */
346struct amap_tx_context {
347 u8 rsvd0[16]; /* dword 0 */
348 u8 tx_ring_size[4]; /* dword 0 */
349 u8 rsvd1[26]; /* dword 0 */
350 u8 pci_func_id[8]; /* dword 1 */
351 u8 rsvd2[9]; /* dword 1 */
352 u8 ctx_valid; /* dword 1 */
353 u8 cq_id_send[16]; /* dword 2 */
354 u8 rsvd3[16]; /* dword 2 */
355 u8 rsvd4[32]; /* dword 3 */
356 u8 rsvd5[32]; /* dword 4 */
357 u8 rsvd6[32]; /* dword 5 */
358 u8 rsvd7[32]; /* dword 6 */
359 u8 rsvd8[32]; /* dword 7 */
360 u8 rsvd9[32]; /* dword 8 */
361 u8 rsvd10[32]; /* dword 9 */
362 u8 rsvd11[32]; /* dword 10 */
363 u8 rsvd12[32]; /* dword 11 */
364 u8 rsvd13[32]; /* dword 12 */
365 u8 rsvd14[32]; /* dword 13 */
366 u8 rsvd15[32]; /* dword 14 */
367 u8 rsvd16[32]; /* dword 15 */
368} __packed;
369
370struct be_cmd_req_eth_tx_create {
371 struct be_cmd_req_hdr hdr;
372 u8 num_pages;
373 u8 ulp_num;
374 u8 type;
375 u8 bound_port;
376 u8 context[sizeof(struct amap_tx_context) / 8];
377 struct phys_addr pages[8];
378} __packed;
379
380struct be_cmd_resp_eth_tx_create {
381 struct be_cmd_resp_hdr hdr;
382 u16 cid;
383 u16 rsvd0;
384} __packed;
385
386/******************** Create RxQ ***************************/
387struct be_cmd_req_eth_rx_create {
388 struct be_cmd_req_hdr hdr;
389 u16 cq_id;
390 u8 frag_size;
391 u8 num_pages;
392 struct phys_addr pages[2];
393 u32 interface_id;
394 u16 max_frame_size;
395 u16 rsvd0;
396 u32 rss_queue;
397} __packed;
398
399struct be_cmd_resp_eth_rx_create {
400 struct be_cmd_resp_hdr hdr;
401 u16 id;
402 u8 cpu_id;
403 u8 rsvd0;
404} __packed;
405
406/******************** Q Destroy ***************************/
407/* Type of Queue to be destroyed */
408enum {
409 QTYPE_EQ = 1,
410 QTYPE_CQ,
411 QTYPE_TXQ,
5fb379ee
SP		 412 QTYPE_RXQ,
413 QTYPE_MCCQ
6b7c5b94
SP		 414};
415
416struct be_cmd_req_q_destroy {
417 struct be_cmd_req_hdr hdr;
418 u16 id;
419 u16 bypass_flush; /* valid only for rx q destroy */
420} __packed;
421
422/************ I/f Create (it's actually I/f Config Create)**********/
423
424/* Capability flags for the i/f */
425enum be_if_flags {
426 BE_IF_FLAGS_RSS = 0x4,
427 BE_IF_FLAGS_PROMISCUOUS = 0x8,
428 BE_IF_FLAGS_BROADCAST = 0x10,
429 BE_IF_FLAGS_UNTAGGED = 0x20,
430 BE_IF_FLAGS_ULP = 0x40,
431 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
432 BE_IF_FLAGS_VLAN = 0x100,
433 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
434 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
435 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
436};
437
438/* An RX interface is an object with one or more MAC addresses and
439 * filtering capabilities. */
440struct be_cmd_req_if_create {
441 struct be_cmd_req_hdr hdr;
442 u32 version; /* ignore currntly */
443 u32 capability_flags;
444 u32 enable_flags;
445 u8 mac_addr[ETH_ALEN];
446 u8 rsvd0;
447 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
448 u32 vlan_tag; /* not used currently */
449} __packed;
450
451struct be_cmd_resp_if_create {
452 struct be_cmd_resp_hdr hdr;
453 u32 interface_id;
454 u32 pmac_id;
455};
456
457/****** I/f Destroy(it's actually I/f Config Destroy )**********/
458struct be_cmd_req_if_destroy {
459 struct be_cmd_req_hdr hdr;
460 u32 interface_id;
461};
462
463/*************** HW Stats Get **********************************/
464struct be_port_rxf_stats {
465 u32 rx_bytes_lsd; /* dword 0*/
466 u32 rx_bytes_msd; /* dword 1*/
467 u32 rx_total_frames; /* dword 2*/
468 u32 rx_unicast_frames; /* dword 3*/
469 u32 rx_multicast_frames; /* dword 4*/
470 u32 rx_broadcast_frames; /* dword 5*/
471 u32 rx_crc_errors; /* dword 6*/
472 u32 rx_alignment_symbol_errors; /* dword 7*/
473 u32 rx_pause_frames; /* dword 8*/
474 u32 rx_control_frames; /* dword 9*/
475 u32 rx_in_range_errors; /* dword 10*/
476 u32 rx_out_range_errors; /* dword 11*/
477 u32 rx_frame_too_long; /* dword 12*/
478 u32 rx_address_match_errors; /* dword 13*/
479 u32 rx_vlan_mismatch; /* dword 14*/
480 u32 rx_dropped_too_small; /* dword 15*/
481 u32 rx_dropped_too_short; /* dword 16*/
482 u32 rx_dropped_header_too_small; /* dword 17*/
483 u32 rx_dropped_tcp_length; /* dword 18*/
484 u32 rx_dropped_runt; /* dword 19*/
485 u32 rx_64_byte_packets; /* dword 20*/
486 u32 rx_65_127_byte_packets; /* dword 21*/
487 u32 rx_128_256_byte_packets; /* dword 22*/
488 u32 rx_256_511_byte_packets; /* dword 23*/
489 u32 rx_512_1023_byte_packets; /* dword 24*/
490 u32 rx_1024_1518_byte_packets; /* dword 25*/
491 u32 rx_1519_2047_byte_packets; /* dword 26*/
492 u32 rx_2048_4095_byte_packets; /* dword 27*/
493 u32 rx_4096_8191_byte_packets; /* dword 28*/
494 u32 rx_8192_9216_byte_packets; /* dword 29*/
495 u32 rx_ip_checksum_errs; /* dword 30*/
496 u32 rx_tcp_checksum_errs; /* dword 31*/
497 u32 rx_udp_checksum_errs; /* dword 32*/
498 u32 rx_non_rss_packets; /* dword 33*/
499 u32 rx_ipv4_packets; /* dword 34*/
500 u32 rx_ipv6_packets; /* dword 35*/
501 u32 rx_ipv4_bytes_lsd; /* dword 36*/
502 u32 rx_ipv4_bytes_msd; /* dword 37*/
503 u32 rx_ipv6_bytes_lsd; /* dword 38*/
504 u32 rx_ipv6_bytes_msd; /* dword 39*/
505 u32 rx_chute1_packets; /* dword 40*/
506 u32 rx_chute2_packets; /* dword 41*/
507 u32 rx_chute3_packets; /* dword 42*/
508 u32 rx_management_packets; /* dword 43*/
509 u32 rx_switched_unicast_packets; /* dword 44*/
510 u32 rx_switched_multicast_packets; /* dword 45*/
511 u32 rx_switched_broadcast_packets; /* dword 46*/
512 u32 tx_bytes_lsd; /* dword 47*/
513 u32 tx_bytes_msd; /* dword 48*/
514 u32 tx_unicastframes; /* dword 49*/
515 u32 tx_multicastframes; /* dword 50*/
516 u32 tx_broadcastframes; /* dword 51*/
517 u32 tx_pauseframes; /* dword 52*/
518 u32 tx_controlframes; /* dword 53*/
519 u32 tx_64_byte_packets; /* dword 54*/
520 u32 tx_65_127_byte_packets; /* dword 55*/
521 u32 tx_128_256_byte_packets; /* dword 56*/
522 u32 tx_256_511_byte_packets; /* dword 57*/
523 u32 tx_512_1023_byte_packets; /* dword 58*/
524 u32 tx_1024_1518_byte_packets; /* dword 59*/
525 u32 tx_1519_2047_byte_packets; /* dword 60*/
526 u32 tx_2048_4095_byte_packets; /* dword 61*/
527 u32 tx_4096_8191_byte_packets; /* dword 62*/
528 u32 tx_8192_9216_byte_packets; /* dword 63*/
529 u32 rx_fifo_overflow; /* dword 64*/
530 u32 rx_input_fifo_overflow; /* dword 65*/
531};
532
533struct be_rxf_stats {
534 struct be_port_rxf_stats port[2];
535 u32 rx_drops_no_pbuf; /* dword 132*/
536 u32 rx_drops_no_txpb; /* dword 133*/
537 u32 rx_drops_no_erx_descr; /* dword 134*/
538 u32 rx_drops_no_tpre_descr; /* dword 135*/
539 u32 management_rx_port_packets; /* dword 136*/
540 u32 management_rx_port_bytes; /* dword 137*/
541 u32 management_rx_port_pause_frames; /* dword 138*/
542 u32 management_rx_port_errors; /* dword 139*/
543 u32 management_tx_port_packets; /* dword 140*/
544 u32 management_tx_port_bytes; /* dword 141*/
545 u32 management_tx_port_pause; /* dword 142*/
546 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
547 u32 rx_drops_too_many_frags; /* dword 144*/
548 u32 rx_drops_invalid_ring; /* dword 145*/
549 u32 forwarded_packets; /* dword 146*/
550 u32 rx_drops_mtu; /* dword 147*/
551 u32 rsvd0[15];
552};
553
554struct be_erx_stats {
555 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
556 u32 debug_wdma_sent_hold; /* dword 44*/
557 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
558 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
559 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
560};
561
562struct be_hw_stats {
563 struct be_rxf_stats rxf;
564 u32 rsvd[48];
565 struct be_erx_stats erx;
566};
567
568struct be_cmd_req_get_stats {
569 struct be_cmd_req_hdr hdr;
570 u8 rsvd[sizeof(struct be_hw_stats)];
571};
572
573struct be_cmd_resp_get_stats {
574 struct be_cmd_resp_hdr hdr;
575 struct be_hw_stats hw_stats;
576};
577
578struct be_cmd_req_vlan_config {
579 struct be_cmd_req_hdr hdr;
580 u8 interface_id;
581 u8 promiscuous;
582 u8 untagged;
583 u8 num_vlan;
584 u16 normal_vlan[64];
585} __packed;
586
587struct be_cmd_req_promiscuous_config {
588 struct be_cmd_req_hdr hdr;
589 u8 port0_promiscuous;
590 u8 port1_promiscuous;
591 u16 rsvd0;
592} __packed;
593
594struct macaddr {
595 u8 byte[ETH_ALEN];
596};
597
598struct be_cmd_req_mcast_mac_config {
599 struct be_cmd_req_hdr hdr;
600 u16 num_mac;
601 u8 promiscuous;
602 u8 interface_id;
603 struct macaddr mac[32];
604} __packed;
605
606static inline struct be_hw_stats *
607hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
608{
609 return &cmd->hw_stats;
610}
611
612/******************** Link Status Query *******************/
613struct be_cmd_req_link_status {
614 struct be_cmd_req_hdr hdr;
615 u32 rsvd;
616};
617
6b7c5b94
SP		 618enum {
619 PHY_LINK_DUPLEX_NONE = 0x0,
620 PHY_LINK_DUPLEX_HALF = 0x1,
621 PHY_LINK_DUPLEX_FULL = 0x2
622};
623
624enum {
625 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
626 PHY_LINK_SPEED_10MBPS = 0x1,
627 PHY_LINK_SPEED_100MBPS = 0x2,
628 PHY_LINK_SPEED_1GBPS = 0x3,
629 PHY_LINK_SPEED_10GBPS = 0x4
630};
631
632struct be_cmd_resp_link_status {
633 struct be_cmd_resp_hdr hdr;
634 u8 physical_port;
635 u8 mac_duplex;
636 u8 mac_speed;
637 u8 mac_fault;
638 u8 mgmt_mac_duplex;
639 u8 mgmt_mac_speed;
0388f251
SB		 640 u16 link_speed;
641 u32 rsvd0;
6b7c5b94
SP		 642} __packed;
643
0388f251
SB		 644/******************** Port Identification ***************************/
645/* Identifies the type of port attached to NIC */
646struct be_cmd_req_port_type {
647 struct be_cmd_req_hdr hdr;
648 u32 page_num;
649 u32 port;
650};
651
652enum {
653 TR_PAGE_A0 = 0xa0,
654 TR_PAGE_A2 = 0xa2
655};
656
657struct be_cmd_resp_port_type {
658 struct be_cmd_resp_hdr hdr;
659 u32 page_num;
660 u32 port;
661 struct data {
662 u8 identifier;
663 u8 identifier_ext;
664 u8 connector;
665 u8 transceiver[8];
666 u8 rsvd0[3];
667 u8 length_km;
668 u8 length_hm;
669 u8 length_om1;
670 u8 length_om2;
671 u8 length_cu;
672 u8 length_cu_m;
673 u8 vendor_name[16];
674 u8 rsvd;
675 u8 vendor_oui[3];
676 u8 vendor_pn[16];
677 u8 vendor_rev[4];
678 } data;
679};
680
6b7c5b94 681/******************** Get FW Version *******************/
6b7c5b94
SP		 682struct be_cmd_req_get_fw_version {
683 struct be_cmd_req_hdr hdr;
684 u8 rsvd0[FW_VER_LEN];
685 u8 rsvd1[FW_VER_LEN];
686} __packed;
687
688struct be_cmd_resp_get_fw_version {
689 struct be_cmd_resp_hdr hdr;
690 u8 firmware_version_string[FW_VER_LEN];
691 u8 fw_on_flash_version_string[FW_VER_LEN];
692} __packed;
693
694/******************** Set Flow Contrl *******************/
695struct be_cmd_req_set_flow_control {
696 struct be_cmd_req_hdr hdr;
697 u16 tx_flow_control;
698 u16 rx_flow_control;
699} __packed;
700
701/******************** Get Flow Contrl *******************/
702struct be_cmd_req_get_flow_control {
703 struct be_cmd_req_hdr hdr;
704 u32 rsvd;
705};
706
707struct be_cmd_resp_get_flow_control {
708 struct be_cmd_resp_hdr hdr;
709 u16 tx_flow_control;
710 u16 rx_flow_control;
711} __packed;
712
713/******************** Modify EQ Delay *******************/
714struct be_cmd_req_modify_eq_delay {
715 struct be_cmd_req_hdr hdr;
716 u32 num_eq;
717 struct {
718 u32 eq_id;
719 u32 phase;
720 u32 delay_multiplier;
721 } delay[8];
722} __packed;
723
724struct be_cmd_resp_modify_eq_delay {
725 struct be_cmd_resp_hdr hdr;
726 u32 rsvd0;
727} __packed;
728
729/******************** Get FW Config *******************/
730struct be_cmd_req_query_fw_cfg {
731 struct be_cmd_req_hdr hdr;
732 u32 rsvd[30];
733};
734
735struct be_cmd_resp_query_fw_cfg {
736 struct be_cmd_resp_hdr hdr;
737 u32 be_config_number;
738 u32 asic_revision;
739 u32 phys_port;
84517482 740 u32 function_cap;
6b7c5b94
SP		 741 u32 rsvd[26];
742};
743
fad9ab2c
SB		 744/******************** Port Beacon ***************************/
745
746#define BEACON_STATE_ENABLED 0x1
747#define BEACON_STATE_DISABLED 0x0
748
749struct be_cmd_req_enable_disable_beacon {
750 struct be_cmd_req_hdr hdr;
751 u8 port_num;
752 u8 beacon_state;
753 u8 beacon_duration;
754 u8 status_duration;
755} __packed;
756
757struct be_cmd_resp_enable_disable_beacon {
758 struct be_cmd_resp_hdr resp_hdr;
759 u32 rsvd0;
760} __packed;
761
762struct be_cmd_req_get_beacon_state {
763 struct be_cmd_req_hdr hdr;
764 u8 port_num;
765 u8 rsvd0;
766 u16 rsvd1;
767} __packed;
768
769struct be_cmd_resp_get_beacon_state {
770 struct be_cmd_resp_hdr resp_hdr;
771 u8 beacon_state;
772 u8 rsvd0[3];
773} __packed;
774
84517482
AK		 775/****************** Firmware Flash ******************/
776struct flashrom_params {
777 u32 op_code;
778 u32 op_type;
779 u32 data_buf_size;
780 u32 offset;
781 u8 data_buf[4];
782};
783
784struct be_cmd_write_flashrom {
785 struct be_cmd_req_hdr hdr;
786 struct flashrom_params params;
787};
788
8788fdc2
SP		 789extern int be_pci_fnum_get(struct be_adapter *adapter);
790extern int be_cmd_POST(struct be_adapter *adapter);
791extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 792 u8 type, bool permanent, u32 if_handle);
8788fdc2 793extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 794 u32 if_id, u32 *pmac_id);
8788fdc2 795extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
73d540f2
SP		 796extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
797 u32 en_flags, u8 *mac, bool pmac_invalid,
798 u32 *if_handle, u32 *pmac_id);
8788fdc2
SP		 799extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
800extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 801 struct be_queue_info *eq, int eq_delay);
8788fdc2 802extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 803 struct be_queue_info *cq, struct be_queue_info *eq,
804 bool sol_evts, bool no_delay,
805 int num_cqe_dma_coalesce);
8788fdc2 806extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 807 struct be_queue_info *mccq,
808 struct be_queue_info *cq);
8788fdc2 809extern int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 810 struct be_queue_info *txq,
811 struct be_queue_info *cq);
8788fdc2 812extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94
SP		 813 struct be_queue_info *rxq, u16 cq_id,
814 u16 frag_size, u16 max_frame_size, u32 if_id,
815 u32 rss);
8788fdc2 816extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 817 int type);
8788fdc2 818extern int be_cmd_link_status_query(struct be_adapter *adapter,
0388f251 819 bool *link_up, u8 *mac_speed, u16 *link_speed);
8788fdc2
SP		 820extern int be_cmd_reset(struct be_adapter *adapter);
821extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 822 struct be_dma_mem *nonemb_cmd);
8788fdc2 823extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
6b7c5b94 824
8788fdc2
SP		 825extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
826extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 827 u16 *vtag_array, u32 num, bool untagged,
828 bool promiscuous);
8788fdc2 829extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
6b7c5b94 830 u8 port_num, bool en);
8788fdc2 831extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
24307eef 832 struct dev_mc_list *mc_list, u32 mc_count);
8788fdc2 833extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 834 u32 tx_fc, u32 rx_fc);
8788fdc2 835extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 836 u32 *tx_fc, u32 *rx_fc);
dcb9b564
AK		 837extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
838 u32 *port_num, u32 *cap);
14074eab 839extern int be_cmd_reset_function(struct be_adapter *adapter);
b31c50a7 840extern int be_process_mcc(struct be_adapter *adapter);
fad9ab2c
SB		 841extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
842 u8 port_num, u8 beacon, u8 status, u8 state);
843extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
844 u8 port_num, u32 *state);
0388f251
SB		 845extern int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
846 u8 *connector);
84517482
AK		 847extern int be_cmd_write_flashrom(struct be_adapter *adapter,
848 struct be_dma_mem *cmd, u32 flash_oper,
849 u32 flash_opcode, u32 buf_size);
fa9a6fed 850extern int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc);
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