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6b7c5b94 SP |
1 | /* |
2 | * Copyright (C) 2005 - 2009 ServerEngines | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | ||
18 | /* | |
19 | * The driver sends configuration and managements command requests to the | |
20 | * firmware in the BE. These requests are communicated to the processor | |
21 | * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one | |
22 | * WRB inside a MAILBOX. | |
23 | * The commands are serviced by the ARM processor in the BladeEngine's MPU. | |
24 | */ | |
25 | ||
26 | struct be_sge { | |
27 | u32 pa_lo; | |
28 | u32 pa_hi; | |
29 | u32 len; | |
30 | }; | |
31 | ||
32 | #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ | |
33 | #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ | |
34 | #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ | |
35 | struct be_mcc_wrb { | |
36 | u32 embedded; /* dword 0 */ | |
37 | u32 payload_length; /* dword 1 */ | |
38 | u32 tag0; /* dword 2 */ | |
39 | u32 tag1; /* dword 3 */ | |
40 | u32 rsvd; /* dword 4 */ | |
41 | union { | |
42 | u8 embedded_payload[236]; /* used by embedded cmds */ | |
43 | struct be_sge sgl[19]; /* used by non-embedded cmds */ | |
44 | } payload; | |
45 | }; | |
46 | ||
47 | #define CQE_FLAGS_VALID_MASK (1 << 31) | |
48 | #define CQE_FLAGS_ASYNC_MASK (1 << 30) | |
49 | #define CQE_FLAGS_COMPLETED_MASK (1 << 28) | |
50 | #define CQE_FLAGS_CONSUMED_MASK (1 << 27) | |
51 | ||
52 | /* Completion Status */ | |
53 | enum { | |
54 | MCC_STATUS_SUCCESS = 0x0, | |
55 | /* The client does not have sufficient privileges to execute the command */ | |
56 | MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1, | |
57 | /* A parameter in the command was invalid. */ | |
58 | MCC_STATUS_INVALID_PARAMETER = 0x2, | |
59 | /* There are insufficient chip resources to execute the command */ | |
60 | MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3, | |
61 | /* The command is completing because the queue was getting flushed */ | |
62 | MCC_STATUS_QUEUE_FLUSHING = 0x4, | |
63 | /* The command is completing with a DMA error */ | |
b31c50a7 | 64 | MCC_STATUS_DMA_FAILED = 0x5, |
49643848 | 65 | MCC_STATUS_NOT_SUPPORTED = 66 |
6b7c5b94 SP |
66 | }; |
67 | ||
68 | #define CQE_STATUS_COMPL_MASK 0xFFFF | |
69 | #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ | |
70 | #define CQE_STATUS_EXTD_MASK 0xFFFF | |
f5209b44 | 71 | #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */ |
6b7c5b94 | 72 | |
efd2e40a | 73 | struct be_mcc_compl { |
6b7c5b94 SP |
74 | u32 status; /* dword 0 */ |
75 | u32 tag0; /* dword 1 */ | |
76 | u32 tag1; /* dword 2 */ | |
77 | u32 flags; /* dword 3 */ | |
78 | }; | |
79 | ||
a8f447bd SP |
80 | /* When the async bit of mcc_compl is set, the last 4 bytes of |
81 | * mcc_compl is interpreted as follows: | |
82 | */ | |
83 | #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ | |
84 | #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF | |
85 | #define ASYNC_EVENT_CODE_LINK_STATE 0x1 | |
86 | struct be_async_event_trailer { | |
87 | u32 code; | |
88 | }; | |
89 | ||
90 | enum { | |
91 | ASYNC_EVENT_LINK_DOWN = 0x0, | |
92 | ASYNC_EVENT_LINK_UP = 0x1 | |
93 | }; | |
94 | ||
95 | /* When the event code of an async trailer is link-state, the mcc_compl | |
96 | * must be interpreted as follows | |
97 | */ | |
98 | struct be_async_event_link_state { | |
99 | u8 physical_port; | |
100 | u8 port_link_status; | |
101 | u8 port_duplex; | |
102 | u8 port_speed; | |
103 | u8 port_fault; | |
104 | u8 rsvd0[7]; | |
105 | struct be_async_event_trailer trailer; | |
106 | } __packed; | |
107 | ||
6b7c5b94 SP |
108 | struct be_mcc_mailbox { |
109 | struct be_mcc_wrb wrb; | |
efd2e40a | 110 | struct be_mcc_compl compl; |
6b7c5b94 SP |
111 | }; |
112 | ||
113 | #define CMD_SUBSYSTEM_COMMON 0x1 | |
114 | #define CMD_SUBSYSTEM_ETH 0x3 | |
115 | ||
116 | #define OPCODE_COMMON_NTWK_MAC_QUERY 1 | |
117 | #define OPCODE_COMMON_NTWK_MAC_SET 2 | |
118 | #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 | |
119 | #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 | |
120 | #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 | |
fa9a6fed | 121 | #define OPCODE_COMMON_READ_FLASHROM 6 |
84517482 | 122 | #define OPCODE_COMMON_WRITE_FLASHROM 7 |
6b7c5b94 SP |
123 | #define OPCODE_COMMON_CQ_CREATE 12 |
124 | #define OPCODE_COMMON_EQ_CREATE 13 | |
125 | #define OPCODE_COMMON_MCC_CREATE 21 | |
126 | #define OPCODE_COMMON_NTWK_RX_FILTER 34 | |
127 | #define OPCODE_COMMON_GET_FW_VERSION 35 | |
128 | #define OPCODE_COMMON_SET_FLOW_CONTROL 36 | |
129 | #define OPCODE_COMMON_GET_FLOW_CONTROL 37 | |
130 | #define OPCODE_COMMON_SET_FRAME_SIZE 39 | |
131 | #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 | |
132 | #define OPCODE_COMMON_FIRMWARE_CONFIG 42 | |
133 | #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 | |
134 | #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 | |
5fb379ee | 135 | #define OPCODE_COMMON_MCC_DESTROY 53 |
6b7c5b94 SP |
136 | #define OPCODE_COMMON_CQ_DESTROY 54 |
137 | #define OPCODE_COMMON_EQ_DESTROY 55 | |
138 | #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 | |
139 | #define OPCODE_COMMON_NTWK_PMAC_ADD 59 | |
140 | #define OPCODE_COMMON_NTWK_PMAC_DEL 60 | |
14074eab | 141 | #define OPCODE_COMMON_FUNCTION_RESET 61 |
fad9ab2c SB |
142 | #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 |
143 | #define OPCODE_COMMON_GET_BEACON_STATE 70 | |
0388f251 | 144 | #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 |
6b7c5b94 SP |
145 | |
146 | #define OPCODE_ETH_ACPI_CONFIG 2 | |
147 | #define OPCODE_ETH_PROMISCUOUS 3 | |
148 | #define OPCODE_ETH_GET_STATISTICS 4 | |
149 | #define OPCODE_ETH_TX_CREATE 7 | |
150 | #define OPCODE_ETH_RX_CREATE 8 | |
151 | #define OPCODE_ETH_TX_DESTROY 9 | |
152 | #define OPCODE_ETH_RX_DESTROY 10 | |
71d8d1b5 | 153 | #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 |
6b7c5b94 SP |
154 | |
155 | struct be_cmd_req_hdr { | |
156 | u8 opcode; /* dword 0 */ | |
157 | u8 subsystem; /* dword 0 */ | |
158 | u8 port_number; /* dword 0 */ | |
159 | u8 domain; /* dword 0 */ | |
160 | u32 timeout; /* dword 1 */ | |
161 | u32 request_length; /* dword 2 */ | |
162 | u32 rsvd; /* dword 3 */ | |
163 | }; | |
164 | ||
165 | #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ | |
166 | #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ | |
167 | struct be_cmd_resp_hdr { | |
168 | u32 info; /* dword 0 */ | |
169 | u32 status; /* dword 1 */ | |
170 | u32 response_length; /* dword 2 */ | |
171 | u32 actual_resp_len; /* dword 3 */ | |
172 | }; | |
173 | ||
174 | struct phys_addr { | |
175 | u32 lo; | |
176 | u32 hi; | |
177 | }; | |
178 | ||
179 | /************************** | |
180 | * BE Command definitions * | |
181 | **************************/ | |
182 | ||
183 | /* Pseudo amap definition in which each bit of the actual structure is defined | |
184 | * as a byte: used to calculate offset/shift/mask of each field */ | |
185 | struct amap_eq_context { | |
186 | u8 cidx[13]; /* dword 0*/ | |
187 | u8 rsvd0[3]; /* dword 0*/ | |
188 | u8 epidx[13]; /* dword 0*/ | |
189 | u8 valid; /* dword 0*/ | |
190 | u8 rsvd1; /* dword 0*/ | |
191 | u8 size; /* dword 0*/ | |
192 | u8 pidx[13]; /* dword 1*/ | |
193 | u8 rsvd2[3]; /* dword 1*/ | |
194 | u8 pd[10]; /* dword 1*/ | |
195 | u8 count[3]; /* dword 1*/ | |
196 | u8 solevent; /* dword 1*/ | |
197 | u8 stalled; /* dword 1*/ | |
198 | u8 armed; /* dword 1*/ | |
199 | u8 rsvd3[4]; /* dword 2*/ | |
200 | u8 func[8]; /* dword 2*/ | |
201 | u8 rsvd4; /* dword 2*/ | |
202 | u8 delaymult[10]; /* dword 2*/ | |
203 | u8 rsvd5[2]; /* dword 2*/ | |
204 | u8 phase[2]; /* dword 2*/ | |
205 | u8 nodelay; /* dword 2*/ | |
206 | u8 rsvd6[4]; /* dword 2*/ | |
207 | u8 rsvd7[32]; /* dword 3*/ | |
208 | } __packed; | |
209 | ||
210 | struct be_cmd_req_eq_create { | |
211 | struct be_cmd_req_hdr hdr; | |
212 | u16 num_pages; /* sword */ | |
213 | u16 rsvd0; /* sword */ | |
214 | u8 context[sizeof(struct amap_eq_context) / 8]; | |
215 | struct phys_addr pages[8]; | |
216 | } __packed; | |
217 | ||
218 | struct be_cmd_resp_eq_create { | |
219 | struct be_cmd_resp_hdr resp_hdr; | |
220 | u16 eq_id; /* sword */ | |
221 | u16 rsvd0; /* sword */ | |
222 | } __packed; | |
223 | ||
224 | /******************** Mac query ***************************/ | |
225 | enum { | |
226 | MAC_ADDRESS_TYPE_STORAGE = 0x0, | |
227 | MAC_ADDRESS_TYPE_NETWORK = 0x1, | |
228 | MAC_ADDRESS_TYPE_PD = 0x2, | |
229 | MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 | |
230 | }; | |
231 | ||
232 | struct mac_addr { | |
233 | u16 size_of_struct; | |
234 | u8 addr[ETH_ALEN]; | |
235 | } __packed; | |
236 | ||
237 | struct be_cmd_req_mac_query { | |
238 | struct be_cmd_req_hdr hdr; | |
239 | u8 type; | |
240 | u8 permanent; | |
241 | u16 if_id; | |
242 | } __packed; | |
243 | ||
244 | struct be_cmd_resp_mac_query { | |
245 | struct be_cmd_resp_hdr hdr; | |
246 | struct mac_addr mac; | |
247 | }; | |
248 | ||
249 | /******************** PMac Add ***************************/ | |
250 | struct be_cmd_req_pmac_add { | |
251 | struct be_cmd_req_hdr hdr; | |
252 | u32 if_id; | |
253 | u8 mac_address[ETH_ALEN]; | |
254 | u8 rsvd0[2]; | |
255 | } __packed; | |
256 | ||
257 | struct be_cmd_resp_pmac_add { | |
258 | struct be_cmd_resp_hdr hdr; | |
259 | u32 pmac_id; | |
260 | }; | |
261 | ||
262 | /******************** PMac Del ***************************/ | |
263 | struct be_cmd_req_pmac_del { | |
264 | struct be_cmd_req_hdr hdr; | |
265 | u32 if_id; | |
266 | u32 pmac_id; | |
267 | }; | |
268 | ||
269 | /******************** Create CQ ***************************/ | |
270 | /* Pseudo amap definition in which each bit of the actual structure is defined | |
271 | * as a byte: used to calculate offset/shift/mask of each field */ | |
272 | struct amap_cq_context { | |
273 | u8 cidx[11]; /* dword 0*/ | |
274 | u8 rsvd0; /* dword 0*/ | |
275 | u8 coalescwm[2]; /* dword 0*/ | |
276 | u8 nodelay; /* dword 0*/ | |
277 | u8 epidx[11]; /* dword 0*/ | |
278 | u8 rsvd1; /* dword 0*/ | |
279 | u8 count[2]; /* dword 0*/ | |
280 | u8 valid; /* dword 0*/ | |
281 | u8 solevent; /* dword 0*/ | |
282 | u8 eventable; /* dword 0*/ | |
283 | u8 pidx[11]; /* dword 1*/ | |
284 | u8 rsvd2; /* dword 1*/ | |
285 | u8 pd[10]; /* dword 1*/ | |
286 | u8 eqid[8]; /* dword 1*/ | |
287 | u8 stalled; /* dword 1*/ | |
288 | u8 armed; /* dword 1*/ | |
289 | u8 rsvd3[4]; /* dword 2*/ | |
290 | u8 func[8]; /* dword 2*/ | |
291 | u8 rsvd4[20]; /* dword 2*/ | |
292 | u8 rsvd5[32]; /* dword 3*/ | |
293 | } __packed; | |
294 | ||
295 | struct be_cmd_req_cq_create { | |
296 | struct be_cmd_req_hdr hdr; | |
297 | u16 num_pages; | |
298 | u16 rsvd0; | |
299 | u8 context[sizeof(struct amap_cq_context) / 8]; | |
300 | struct phys_addr pages[8]; | |
301 | } __packed; | |
302 | ||
303 | struct be_cmd_resp_cq_create { | |
304 | struct be_cmd_resp_hdr hdr; | |
305 | u16 cq_id; | |
306 | u16 rsvd0; | |
307 | } __packed; | |
308 | ||
5fb379ee SP |
309 | /******************** Create MCCQ ***************************/ |
310 | /* Pseudo amap definition in which each bit of the actual structure is defined | |
311 | * as a byte: used to calculate offset/shift/mask of each field */ | |
312 | struct amap_mcc_context { | |
313 | u8 con_index[14]; | |
314 | u8 rsvd0[2]; | |
315 | u8 ring_size[4]; | |
316 | u8 fetch_wrb; | |
317 | u8 fetch_r2t; | |
318 | u8 cq_id[10]; | |
319 | u8 prod_index[14]; | |
320 | u8 fid[8]; | |
321 | u8 pdid[9]; | |
322 | u8 valid; | |
323 | u8 rsvd1[32]; | |
324 | u8 rsvd2[32]; | |
325 | } __packed; | |
326 | ||
327 | struct be_cmd_req_mcc_create { | |
328 | struct be_cmd_req_hdr hdr; | |
329 | u16 num_pages; | |
330 | u16 rsvd0; | |
331 | u8 context[sizeof(struct amap_mcc_context) / 8]; | |
332 | struct phys_addr pages[8]; | |
333 | } __packed; | |
334 | ||
335 | struct be_cmd_resp_mcc_create { | |
336 | struct be_cmd_resp_hdr hdr; | |
337 | u16 id; | |
338 | u16 rsvd0; | |
339 | } __packed; | |
340 | ||
6b7c5b94 SP |
341 | /******************** Create TxQ ***************************/ |
342 | #define BE_ETH_TX_RING_TYPE_STANDARD 2 | |
343 | #define BE_ULP1_NUM 1 | |
344 | ||
345 | /* Pseudo amap definition in which each bit of the actual structure is defined | |
346 | * as a byte: used to calculate offset/shift/mask of each field */ | |
347 | struct amap_tx_context { | |
348 | u8 rsvd0[16]; /* dword 0 */ | |
349 | u8 tx_ring_size[4]; /* dword 0 */ | |
350 | u8 rsvd1[26]; /* dword 0 */ | |
351 | u8 pci_func_id[8]; /* dword 1 */ | |
352 | u8 rsvd2[9]; /* dword 1 */ | |
353 | u8 ctx_valid; /* dword 1 */ | |
354 | u8 cq_id_send[16]; /* dword 2 */ | |
355 | u8 rsvd3[16]; /* dword 2 */ | |
356 | u8 rsvd4[32]; /* dword 3 */ | |
357 | u8 rsvd5[32]; /* dword 4 */ | |
358 | u8 rsvd6[32]; /* dword 5 */ | |
359 | u8 rsvd7[32]; /* dword 6 */ | |
360 | u8 rsvd8[32]; /* dword 7 */ | |
361 | u8 rsvd9[32]; /* dword 8 */ | |
362 | u8 rsvd10[32]; /* dword 9 */ | |
363 | u8 rsvd11[32]; /* dword 10 */ | |
364 | u8 rsvd12[32]; /* dword 11 */ | |
365 | u8 rsvd13[32]; /* dword 12 */ | |
366 | u8 rsvd14[32]; /* dword 13 */ | |
367 | u8 rsvd15[32]; /* dword 14 */ | |
368 | u8 rsvd16[32]; /* dword 15 */ | |
369 | } __packed; | |
370 | ||
371 | struct be_cmd_req_eth_tx_create { | |
372 | struct be_cmd_req_hdr hdr; | |
373 | u8 num_pages; | |
374 | u8 ulp_num; | |
375 | u8 type; | |
376 | u8 bound_port; | |
377 | u8 context[sizeof(struct amap_tx_context) / 8]; | |
378 | struct phys_addr pages[8]; | |
379 | } __packed; | |
380 | ||
381 | struct be_cmd_resp_eth_tx_create { | |
382 | struct be_cmd_resp_hdr hdr; | |
383 | u16 cid; | |
384 | u16 rsvd0; | |
385 | } __packed; | |
386 | ||
387 | /******************** Create RxQ ***************************/ | |
388 | struct be_cmd_req_eth_rx_create { | |
389 | struct be_cmd_req_hdr hdr; | |
390 | u16 cq_id; | |
391 | u8 frag_size; | |
392 | u8 num_pages; | |
393 | struct phys_addr pages[2]; | |
394 | u32 interface_id; | |
395 | u16 max_frame_size; | |
396 | u16 rsvd0; | |
397 | u32 rss_queue; | |
398 | } __packed; | |
399 | ||
400 | struct be_cmd_resp_eth_rx_create { | |
401 | struct be_cmd_resp_hdr hdr; | |
402 | u16 id; | |
403 | u8 cpu_id; | |
404 | u8 rsvd0; | |
405 | } __packed; | |
406 | ||
407 | /******************** Q Destroy ***************************/ | |
408 | /* Type of Queue to be destroyed */ | |
409 | enum { | |
410 | QTYPE_EQ = 1, | |
411 | QTYPE_CQ, | |
412 | QTYPE_TXQ, | |
5fb379ee SP |
413 | QTYPE_RXQ, |
414 | QTYPE_MCCQ | |
6b7c5b94 SP |
415 | }; |
416 | ||
417 | struct be_cmd_req_q_destroy { | |
418 | struct be_cmd_req_hdr hdr; | |
419 | u16 id; | |
420 | u16 bypass_flush; /* valid only for rx q destroy */ | |
421 | } __packed; | |
422 | ||
423 | /************ I/f Create (it's actually I/f Config Create)**********/ | |
424 | ||
425 | /* Capability flags for the i/f */ | |
426 | enum be_if_flags { | |
427 | BE_IF_FLAGS_RSS = 0x4, | |
428 | BE_IF_FLAGS_PROMISCUOUS = 0x8, | |
429 | BE_IF_FLAGS_BROADCAST = 0x10, | |
430 | BE_IF_FLAGS_UNTAGGED = 0x20, | |
431 | BE_IF_FLAGS_ULP = 0x40, | |
432 | BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, | |
433 | BE_IF_FLAGS_VLAN = 0x100, | |
434 | BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, | |
435 | BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, | |
436 | BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800 | |
437 | }; | |
438 | ||
439 | /* An RX interface is an object with one or more MAC addresses and | |
440 | * filtering capabilities. */ | |
441 | struct be_cmd_req_if_create { | |
442 | struct be_cmd_req_hdr hdr; | |
443 | u32 version; /* ignore currntly */ | |
444 | u32 capability_flags; | |
445 | u32 enable_flags; | |
446 | u8 mac_addr[ETH_ALEN]; | |
447 | u8 rsvd0; | |
448 | u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ | |
449 | u32 vlan_tag; /* not used currently */ | |
450 | } __packed; | |
451 | ||
452 | struct be_cmd_resp_if_create { | |
453 | struct be_cmd_resp_hdr hdr; | |
454 | u32 interface_id; | |
455 | u32 pmac_id; | |
456 | }; | |
457 | ||
458 | /****** I/f Destroy(it's actually I/f Config Destroy )**********/ | |
459 | struct be_cmd_req_if_destroy { | |
460 | struct be_cmd_req_hdr hdr; | |
461 | u32 interface_id; | |
462 | }; | |
463 | ||
464 | /*************** HW Stats Get **********************************/ | |
465 | struct be_port_rxf_stats { | |
466 | u32 rx_bytes_lsd; /* dword 0*/ | |
467 | u32 rx_bytes_msd; /* dword 1*/ | |
468 | u32 rx_total_frames; /* dword 2*/ | |
469 | u32 rx_unicast_frames; /* dword 3*/ | |
470 | u32 rx_multicast_frames; /* dword 4*/ | |
471 | u32 rx_broadcast_frames; /* dword 5*/ | |
472 | u32 rx_crc_errors; /* dword 6*/ | |
473 | u32 rx_alignment_symbol_errors; /* dword 7*/ | |
474 | u32 rx_pause_frames; /* dword 8*/ | |
475 | u32 rx_control_frames; /* dword 9*/ | |
476 | u32 rx_in_range_errors; /* dword 10*/ | |
477 | u32 rx_out_range_errors; /* dword 11*/ | |
478 | u32 rx_frame_too_long; /* dword 12*/ | |
479 | u32 rx_address_match_errors; /* dword 13*/ | |
480 | u32 rx_vlan_mismatch; /* dword 14*/ | |
481 | u32 rx_dropped_too_small; /* dword 15*/ | |
482 | u32 rx_dropped_too_short; /* dword 16*/ | |
483 | u32 rx_dropped_header_too_small; /* dword 17*/ | |
484 | u32 rx_dropped_tcp_length; /* dword 18*/ | |
485 | u32 rx_dropped_runt; /* dword 19*/ | |
486 | u32 rx_64_byte_packets; /* dword 20*/ | |
487 | u32 rx_65_127_byte_packets; /* dword 21*/ | |
488 | u32 rx_128_256_byte_packets; /* dword 22*/ | |
489 | u32 rx_256_511_byte_packets; /* dword 23*/ | |
490 | u32 rx_512_1023_byte_packets; /* dword 24*/ | |
491 | u32 rx_1024_1518_byte_packets; /* dword 25*/ | |
492 | u32 rx_1519_2047_byte_packets; /* dword 26*/ | |
493 | u32 rx_2048_4095_byte_packets; /* dword 27*/ | |
494 | u32 rx_4096_8191_byte_packets; /* dword 28*/ | |
495 | u32 rx_8192_9216_byte_packets; /* dword 29*/ | |
496 | u32 rx_ip_checksum_errs; /* dword 30*/ | |
497 | u32 rx_tcp_checksum_errs; /* dword 31*/ | |
498 | u32 rx_udp_checksum_errs; /* dword 32*/ | |
499 | u32 rx_non_rss_packets; /* dword 33*/ | |
500 | u32 rx_ipv4_packets; /* dword 34*/ | |
501 | u32 rx_ipv6_packets; /* dword 35*/ | |
502 | u32 rx_ipv4_bytes_lsd; /* dword 36*/ | |
503 | u32 rx_ipv4_bytes_msd; /* dword 37*/ | |
504 | u32 rx_ipv6_bytes_lsd; /* dword 38*/ | |
505 | u32 rx_ipv6_bytes_msd; /* dword 39*/ | |
506 | u32 rx_chute1_packets; /* dword 40*/ | |
507 | u32 rx_chute2_packets; /* dword 41*/ | |
508 | u32 rx_chute3_packets; /* dword 42*/ | |
509 | u32 rx_management_packets; /* dword 43*/ | |
510 | u32 rx_switched_unicast_packets; /* dword 44*/ | |
511 | u32 rx_switched_multicast_packets; /* dword 45*/ | |
512 | u32 rx_switched_broadcast_packets; /* dword 46*/ | |
513 | u32 tx_bytes_lsd; /* dword 47*/ | |
514 | u32 tx_bytes_msd; /* dword 48*/ | |
515 | u32 tx_unicastframes; /* dword 49*/ | |
516 | u32 tx_multicastframes; /* dword 50*/ | |
517 | u32 tx_broadcastframes; /* dword 51*/ | |
518 | u32 tx_pauseframes; /* dword 52*/ | |
519 | u32 tx_controlframes; /* dword 53*/ | |
520 | u32 tx_64_byte_packets; /* dword 54*/ | |
521 | u32 tx_65_127_byte_packets; /* dword 55*/ | |
522 | u32 tx_128_256_byte_packets; /* dword 56*/ | |
523 | u32 tx_256_511_byte_packets; /* dword 57*/ | |
524 | u32 tx_512_1023_byte_packets; /* dword 58*/ | |
525 | u32 tx_1024_1518_byte_packets; /* dword 59*/ | |
526 | u32 tx_1519_2047_byte_packets; /* dword 60*/ | |
527 | u32 tx_2048_4095_byte_packets; /* dword 61*/ | |
528 | u32 tx_4096_8191_byte_packets; /* dword 62*/ | |
529 | u32 tx_8192_9216_byte_packets; /* dword 63*/ | |
530 | u32 rx_fifo_overflow; /* dword 64*/ | |
531 | u32 rx_input_fifo_overflow; /* dword 65*/ | |
532 | }; | |
533 | ||
534 | struct be_rxf_stats { | |
535 | struct be_port_rxf_stats port[2]; | |
536 | u32 rx_drops_no_pbuf; /* dword 132*/ | |
537 | u32 rx_drops_no_txpb; /* dword 133*/ | |
538 | u32 rx_drops_no_erx_descr; /* dword 134*/ | |
539 | u32 rx_drops_no_tpre_descr; /* dword 135*/ | |
540 | u32 management_rx_port_packets; /* dword 136*/ | |
541 | u32 management_rx_port_bytes; /* dword 137*/ | |
542 | u32 management_rx_port_pause_frames; /* dword 138*/ | |
543 | u32 management_rx_port_errors; /* dword 139*/ | |
544 | u32 management_tx_port_packets; /* dword 140*/ | |
545 | u32 management_tx_port_bytes; /* dword 141*/ | |
546 | u32 management_tx_port_pause; /* dword 142*/ | |
547 | u32 management_rx_port_rxfifo_overflow; /* dword 143*/ | |
548 | u32 rx_drops_too_many_frags; /* dword 144*/ | |
549 | u32 rx_drops_invalid_ring; /* dword 145*/ | |
550 | u32 forwarded_packets; /* dword 146*/ | |
551 | u32 rx_drops_mtu; /* dword 147*/ | |
552 | u32 rsvd0[15]; | |
553 | }; | |
554 | ||
555 | struct be_erx_stats { | |
556 | u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ | |
557 | u32 debug_wdma_sent_hold; /* dword 44*/ | |
558 | u32 debug_wdma_pbfree_sent_hold; /* dword 45*/ | |
559 | u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/ | |
560 | u32 debug_pmem_pbuf_dealloc; /* dword 47*/ | |
561 | }; | |
562 | ||
563 | struct be_hw_stats { | |
564 | struct be_rxf_stats rxf; | |
565 | u32 rsvd[48]; | |
566 | struct be_erx_stats erx; | |
567 | }; | |
568 | ||
569 | struct be_cmd_req_get_stats { | |
570 | struct be_cmd_req_hdr hdr; | |
571 | u8 rsvd[sizeof(struct be_hw_stats)]; | |
572 | }; | |
573 | ||
574 | struct be_cmd_resp_get_stats { | |
575 | struct be_cmd_resp_hdr hdr; | |
576 | struct be_hw_stats hw_stats; | |
577 | }; | |
578 | ||
579 | struct be_cmd_req_vlan_config { | |
580 | struct be_cmd_req_hdr hdr; | |
581 | u8 interface_id; | |
582 | u8 promiscuous; | |
583 | u8 untagged; | |
584 | u8 num_vlan; | |
585 | u16 normal_vlan[64]; | |
586 | } __packed; | |
587 | ||
588 | struct be_cmd_req_promiscuous_config { | |
589 | struct be_cmd_req_hdr hdr; | |
590 | u8 port0_promiscuous; | |
591 | u8 port1_promiscuous; | |
592 | u16 rsvd0; | |
593 | } __packed; | |
594 | ||
e7b909a6 SP |
595 | /******************** Multicast MAC Config *******************/ |
596 | #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ | |
6b7c5b94 SP |
597 | struct macaddr { |
598 | u8 byte[ETH_ALEN]; | |
599 | }; | |
600 | ||
601 | struct be_cmd_req_mcast_mac_config { | |
602 | struct be_cmd_req_hdr hdr; | |
603 | u16 num_mac; | |
604 | u8 promiscuous; | |
605 | u8 interface_id; | |
e7b909a6 | 606 | struct macaddr mac[BE_MAX_MC]; |
6b7c5b94 SP |
607 | } __packed; |
608 | ||
609 | static inline struct be_hw_stats * | |
610 | hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd) | |
611 | { | |
612 | return &cmd->hw_stats; | |
613 | } | |
614 | ||
615 | /******************** Link Status Query *******************/ | |
616 | struct be_cmd_req_link_status { | |
617 | struct be_cmd_req_hdr hdr; | |
618 | u32 rsvd; | |
619 | }; | |
620 | ||
6b7c5b94 SP |
621 | enum { |
622 | PHY_LINK_DUPLEX_NONE = 0x0, | |
623 | PHY_LINK_DUPLEX_HALF = 0x1, | |
624 | PHY_LINK_DUPLEX_FULL = 0x2 | |
625 | }; | |
626 | ||
627 | enum { | |
628 | PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ | |
629 | PHY_LINK_SPEED_10MBPS = 0x1, | |
630 | PHY_LINK_SPEED_100MBPS = 0x2, | |
631 | PHY_LINK_SPEED_1GBPS = 0x3, | |
632 | PHY_LINK_SPEED_10GBPS = 0x4 | |
633 | }; | |
634 | ||
635 | struct be_cmd_resp_link_status { | |
636 | struct be_cmd_resp_hdr hdr; | |
637 | u8 physical_port; | |
638 | u8 mac_duplex; | |
639 | u8 mac_speed; | |
640 | u8 mac_fault; | |
641 | u8 mgmt_mac_duplex; | |
642 | u8 mgmt_mac_speed; | |
0388f251 SB |
643 | u16 link_speed; |
644 | u32 rsvd0; | |
6b7c5b94 SP |
645 | } __packed; |
646 | ||
0388f251 SB |
647 | /******************** Port Identification ***************************/ |
648 | /* Identifies the type of port attached to NIC */ | |
649 | struct be_cmd_req_port_type { | |
650 | struct be_cmd_req_hdr hdr; | |
651 | u32 page_num; | |
652 | u32 port; | |
653 | }; | |
654 | ||
655 | enum { | |
656 | TR_PAGE_A0 = 0xa0, | |
657 | TR_PAGE_A2 = 0xa2 | |
658 | }; | |
659 | ||
660 | struct be_cmd_resp_port_type { | |
661 | struct be_cmd_resp_hdr hdr; | |
662 | u32 page_num; | |
663 | u32 port; | |
664 | struct data { | |
665 | u8 identifier; | |
666 | u8 identifier_ext; | |
667 | u8 connector; | |
668 | u8 transceiver[8]; | |
669 | u8 rsvd0[3]; | |
670 | u8 length_km; | |
671 | u8 length_hm; | |
672 | u8 length_om1; | |
673 | u8 length_om2; | |
674 | u8 length_cu; | |
675 | u8 length_cu_m; | |
676 | u8 vendor_name[16]; | |
677 | u8 rsvd; | |
678 | u8 vendor_oui[3]; | |
679 | u8 vendor_pn[16]; | |
680 | u8 vendor_rev[4]; | |
681 | } data; | |
682 | }; | |
683 | ||
6b7c5b94 | 684 | /******************** Get FW Version *******************/ |
6b7c5b94 SP |
685 | struct be_cmd_req_get_fw_version { |
686 | struct be_cmd_req_hdr hdr; | |
687 | u8 rsvd0[FW_VER_LEN]; | |
688 | u8 rsvd1[FW_VER_LEN]; | |
689 | } __packed; | |
690 | ||
691 | struct be_cmd_resp_get_fw_version { | |
692 | struct be_cmd_resp_hdr hdr; | |
693 | u8 firmware_version_string[FW_VER_LEN]; | |
694 | u8 fw_on_flash_version_string[FW_VER_LEN]; | |
695 | } __packed; | |
696 | ||
697 | /******************** Set Flow Contrl *******************/ | |
698 | struct be_cmd_req_set_flow_control { | |
699 | struct be_cmd_req_hdr hdr; | |
700 | u16 tx_flow_control; | |
701 | u16 rx_flow_control; | |
702 | } __packed; | |
703 | ||
704 | /******************** Get Flow Contrl *******************/ | |
705 | struct be_cmd_req_get_flow_control { | |
706 | struct be_cmd_req_hdr hdr; | |
707 | u32 rsvd; | |
708 | }; | |
709 | ||
710 | struct be_cmd_resp_get_flow_control { | |
711 | struct be_cmd_resp_hdr hdr; | |
712 | u16 tx_flow_control; | |
713 | u16 rx_flow_control; | |
714 | } __packed; | |
715 | ||
716 | /******************** Modify EQ Delay *******************/ | |
717 | struct be_cmd_req_modify_eq_delay { | |
718 | struct be_cmd_req_hdr hdr; | |
719 | u32 num_eq; | |
720 | struct { | |
721 | u32 eq_id; | |
722 | u32 phase; | |
723 | u32 delay_multiplier; | |
724 | } delay[8]; | |
725 | } __packed; | |
726 | ||
727 | struct be_cmd_resp_modify_eq_delay { | |
728 | struct be_cmd_resp_hdr hdr; | |
729 | u32 rsvd0; | |
730 | } __packed; | |
731 | ||
732 | /******************** Get FW Config *******************/ | |
733 | struct be_cmd_req_query_fw_cfg { | |
734 | struct be_cmd_req_hdr hdr; | |
735 | u32 rsvd[30]; | |
736 | }; | |
737 | ||
738 | struct be_cmd_resp_query_fw_cfg { | |
739 | struct be_cmd_resp_hdr hdr; | |
740 | u32 be_config_number; | |
741 | u32 asic_revision; | |
742 | u32 phys_port; | |
84517482 | 743 | u32 function_cap; |
6b7c5b94 SP |
744 | u32 rsvd[26]; |
745 | }; | |
746 | ||
fad9ab2c SB |
747 | /******************** Port Beacon ***************************/ |
748 | ||
749 | #define BEACON_STATE_ENABLED 0x1 | |
750 | #define BEACON_STATE_DISABLED 0x0 | |
751 | ||
752 | struct be_cmd_req_enable_disable_beacon { | |
753 | struct be_cmd_req_hdr hdr; | |
754 | u8 port_num; | |
755 | u8 beacon_state; | |
756 | u8 beacon_duration; | |
757 | u8 status_duration; | |
758 | } __packed; | |
759 | ||
760 | struct be_cmd_resp_enable_disable_beacon { | |
761 | struct be_cmd_resp_hdr resp_hdr; | |
762 | u32 rsvd0; | |
763 | } __packed; | |
764 | ||
765 | struct be_cmd_req_get_beacon_state { | |
766 | struct be_cmd_req_hdr hdr; | |
767 | u8 port_num; | |
768 | u8 rsvd0; | |
769 | u16 rsvd1; | |
770 | } __packed; | |
771 | ||
772 | struct be_cmd_resp_get_beacon_state { | |
773 | struct be_cmd_resp_hdr resp_hdr; | |
774 | u8 beacon_state; | |
775 | u8 rsvd0[3]; | |
776 | } __packed; | |
777 | ||
84517482 AK |
778 | /****************** Firmware Flash ******************/ |
779 | struct flashrom_params { | |
780 | u32 op_code; | |
781 | u32 op_type; | |
782 | u32 data_buf_size; | |
783 | u32 offset; | |
784 | u8 data_buf[4]; | |
785 | }; | |
786 | ||
787 | struct be_cmd_write_flashrom { | |
788 | struct be_cmd_req_hdr hdr; | |
789 | struct flashrom_params params; | |
790 | }; | |
791 | ||
71d8d1b5 AK |
792 | /************************ WOL *******************************/ |
793 | struct be_cmd_req_acpi_wol_magic_config{ | |
794 | struct be_cmd_req_hdr hdr; | |
795 | u32 rsvd0[145]; | |
796 | u8 magic_mac[6]; | |
797 | u8 rsvd2[2]; | |
798 | } __packed; | |
799 | ||
8788fdc2 SP |
800 | extern int be_pci_fnum_get(struct be_adapter *adapter); |
801 | extern int be_cmd_POST(struct be_adapter *adapter); | |
802 | extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, | |
6b7c5b94 | 803 | u8 type, bool permanent, u32 if_handle); |
8788fdc2 | 804 | extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 | 805 | u32 if_id, u32 *pmac_id); |
8788fdc2 | 806 | extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id); |
73d540f2 SP |
807 | extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, |
808 | u32 en_flags, u8 *mac, bool pmac_invalid, | |
809 | u32 *if_handle, u32 *pmac_id); | |
8788fdc2 SP |
810 | extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle); |
811 | extern int be_cmd_eq_create(struct be_adapter *adapter, | |
6b7c5b94 | 812 | struct be_queue_info *eq, int eq_delay); |
8788fdc2 | 813 | extern int be_cmd_cq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
814 | struct be_queue_info *cq, struct be_queue_info *eq, |
815 | bool sol_evts, bool no_delay, | |
816 | int num_cqe_dma_coalesce); | |
8788fdc2 | 817 | extern int be_cmd_mccq_create(struct be_adapter *adapter, |
5fb379ee SP |
818 | struct be_queue_info *mccq, |
819 | struct be_queue_info *cq); | |
8788fdc2 | 820 | extern int be_cmd_txq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
821 | struct be_queue_info *txq, |
822 | struct be_queue_info *cq); | |
8788fdc2 | 823 | extern int be_cmd_rxq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
824 | struct be_queue_info *rxq, u16 cq_id, |
825 | u16 frag_size, u16 max_frame_size, u32 if_id, | |
826 | u32 rss); | |
8788fdc2 | 827 | extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
6b7c5b94 | 828 | int type); |
8788fdc2 | 829 | extern int be_cmd_link_status_query(struct be_adapter *adapter, |
0388f251 | 830 | bool *link_up, u8 *mac_speed, u16 *link_speed); |
8788fdc2 SP |
831 | extern int be_cmd_reset(struct be_adapter *adapter); |
832 | extern int be_cmd_get_stats(struct be_adapter *adapter, | |
6b7c5b94 | 833 | struct be_dma_mem *nonemb_cmd); |
8788fdc2 | 834 | extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver); |
6b7c5b94 | 835 | |
8788fdc2 SP |
836 | extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd); |
837 | extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, | |
6b7c5b94 SP |
838 | u16 *vtag_array, u32 num, bool untagged, |
839 | bool promiscuous); | |
8788fdc2 | 840 | extern int be_cmd_promiscuous_config(struct be_adapter *adapter, |
6b7c5b94 | 841 | u8 port_num, bool en); |
8788fdc2 | 842 | extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id, |
e7b909a6 SP |
843 | struct dev_mc_list *mc_list, u32 mc_count, |
844 | struct be_dma_mem *mem); | |
8788fdc2 | 845 | extern int be_cmd_set_flow_control(struct be_adapter *adapter, |
6b7c5b94 | 846 | u32 tx_fc, u32 rx_fc); |
8788fdc2 | 847 | extern int be_cmd_get_flow_control(struct be_adapter *adapter, |
6b7c5b94 | 848 | u32 *tx_fc, u32 *rx_fc); |
dcb9b564 AK |
849 | extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, |
850 | u32 *port_num, u32 *cap); | |
14074eab | 851 | extern int be_cmd_reset_function(struct be_adapter *adapter); |
b31c50a7 | 852 | extern int be_process_mcc(struct be_adapter *adapter); |
fad9ab2c SB |
853 | extern int be_cmd_set_beacon_state(struct be_adapter *adapter, |
854 | u8 port_num, u8 beacon, u8 status, u8 state); | |
855 | extern int be_cmd_get_beacon_state(struct be_adapter *adapter, | |
856 | u8 port_num, u32 *state); | |
0388f251 SB |
857 | extern int be_cmd_read_port_type(struct be_adapter *adapter, u32 port, |
858 | u8 *connector); | |
84517482 AK |
859 | extern int be_cmd_write_flashrom(struct be_adapter *adapter, |
860 | struct be_dma_mem *cmd, u32 flash_oper, | |
861 | u32 flash_opcode, u32 buf_size); | |
fa9a6fed | 862 | extern int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc); |
71d8d1b5 AK |
863 | extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, |
864 | struct be_dma_mem *nonemb_cmd); | |
2243e2e9 SP |
865 | extern int be_cmd_fw_init(struct be_adapter *adapter); |
866 | extern int be_cmd_fw_clean(struct be_adapter *adapter); |