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net/pcmcia/3c589_cs: using netdev_info and friends where appropriate
[net-next-2.6.git] / drivers / net / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
6b7c5b94 20
8788fdc2 21static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 22{
8788fdc2 23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 24 u32 val = 0;
25
26 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
8788fdc2 28 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 29}
30
31/* To check if valid bit is set, check the entire word as we don't know
32 * the endianness of the data (old entry is host endian while a new entry is
33 * little endian) */
efd2e40a 34static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee
SP		 35{
36 if (compl->flags != 0) {
37 compl->flags = le32_to_cpu(compl->flags);
38 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
39 return true;
40 } else {
41 return false;
42 }
43}
44
45/* Need to reset the entire word that houses the valid bit */
efd2e40a 46static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 47{
48 compl->flags = 0;
49}
50
8788fdc2 51static int be_mcc_compl_process(struct be_adapter *adapter,
efd2e40a 52 struct be_mcc_compl *compl)
5fb379ee
SP		 53{
54 u16 compl_status, extd_status;
55
56 /* Just swap the status to host endian; mcc tag is opaquely copied
57 * from mcc_wrb */
58 be_dws_le_to_cpu(compl, 4);
59
60 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
61 CQE_STATUS_COMPL_MASK;
b31c50a7
SP		 62 if (compl_status == MCC_STATUS_SUCCESS) {
63 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
64 struct be_cmd_resp_get_stats *resp =
65 adapter->stats.cmd.va;
66 be_dws_le_to_cpu(&resp->hw_stats,
67 sizeof(resp->hw_stats));
68 netdev_stats_update(adapter);
69 }
70 } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
5fb379ee
SP		 71 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
72 CQE_STATUS_EXTD_MASK;
5f0b849e 73 dev_warn(&adapter->pdev->dev,
d744b44e
AK		 74 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
75 compl->tag0, compl_status, extd_status);
5fb379ee 76 }
b31c50a7 77 return compl_status;
5fb379ee
SP		 78}
79
a8f447bd 80/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 81static void be_async_link_state_process(struct be_adapter *adapter,
a8f447bd
SP		 82 struct be_async_event_link_state *evt)
83{
8788fdc2
SP		 84 be_link_status_update(adapter,
85 evt->port_link_status == ASYNC_EVENT_LINK_UP);
a8f447bd
SP		 86}
87
88static inline bool is_link_state_evt(u32 trailer)
89{
90 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
91 ASYNC_TRAILER_EVENT_CODE_MASK) ==
92 ASYNC_EVENT_CODE_LINK_STATE);
93}
5fb379ee 94
efd2e40a 95static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 96{
8788fdc2 97 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 98 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 99
100 if (be_mcc_compl_is_new(compl)) {
101 queue_tail_inc(mcc_cq);
102 return compl;
103 }
104 return NULL;
105}
106
7a1e9b20
SP		 107void be_async_mcc_enable(struct be_adapter *adapter)
108{
109 spin_lock_bh(&adapter->mcc_cq_lock);
110
111 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
112 adapter->mcc_obj.rearm_cq = true;
113
114 spin_unlock_bh(&adapter->mcc_cq_lock);
115}
116
117void be_async_mcc_disable(struct be_adapter *adapter)
118{
119 adapter->mcc_obj.rearm_cq = false;
120}
121
f31e50a8 122int be_process_mcc(struct be_adapter *adapter, int *status)
5fb379ee 123{
efd2e40a 124 struct be_mcc_compl *compl;
f31e50a8 125 int num = 0;
7a1e9b20 126 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 127
8788fdc2
SP		 128 spin_lock_bh(&adapter->mcc_cq_lock);
129 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd
SP		 130 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
131 /* Interpret flags as an async trailer */
132 BUG_ON(!is_link_state_evt(compl->flags));
133
134 /* Interpret compl as a async link evt */
8788fdc2 135 be_async_link_state_process(adapter,
a8f447bd 136 (struct be_async_event_link_state *) compl);
b31c50a7 137 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
f31e50a8 138 *status = be_mcc_compl_process(adapter, compl);
7a1e9b20 139 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 140 }
141 be_mcc_compl_use(compl);
142 num++;
143 }
b31c50a7 144
8788fdc2 145 spin_unlock_bh(&adapter->mcc_cq_lock);
f31e50a8 146 return num;
5fb379ee
SP		 147}
148
6ac7b687 149/* Wait till no more pending mcc requests are present */
b31c50a7 150static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 151{
b31c50a7 152#define mcc_timeout 120000 /* 12s timeout */
f31e50a8
SP		 153 int i, num, status = 0;
154 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
155
6ac7b687 156 for (i = 0; i < mcc_timeout; i++) {
f31e50a8
SP		 157 num = be_process_mcc(adapter, &status);
158 if (num)
159 be_cq_notify(adapter, mcc_obj->cq.id,
160 mcc_obj->rearm_cq, num);
b31c50a7 161
f31e50a8 162 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 163 break;
164 udelay(100);
165 }
b31c50a7 166 if (i == mcc_timeout) {
5f0b849e 167 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
b31c50a7
SP		 168 return -1;
169 }
f31e50a8 170 return status;
6ac7b687
SP		 171}
172
173/* Notify MCC requests and wait for completion */
b31c50a7 174static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 175{
8788fdc2 176 be_mcc_notify(adapter);
b31c50a7 177 return be_mcc_wait_compl(adapter);
6ac7b687
SP		 178}
179
5f0b849e 180static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94
SP		 181{
182 int cnt = 0, wait = 5;
183 u32 ready;
184
185 do {
cf588477
SP		 186 ready = ioread32(db);
187 if (ready == 0xffffffff) {
188 dev_err(&adapter->pdev->dev,
189 "pci slot disconnected\n");
190 return -1;
191 }
192
193 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 194 if (ready)
195 break;
196
84517482 197 if (cnt > 4000000) {
5f0b849e 198 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
6b7c5b94
SP		 199 return -1;
200 }
201
202 if (cnt > 50)
203 wait = 200;
204 cnt += wait;
205 udelay(wait);
206 } while (true);
207
208 return 0;
209}
210
211/*
212 * Insert the mailbox address into the doorbell in two steps
5fb379ee 213 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 214 */
b31c50a7 215static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 216{
217 int status;
6b7c5b94 218 u32 val = 0;
8788fdc2
SP		 219 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
220 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 221 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 222 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 223
cf588477
SP		 224 /* wait for ready to be set */
225 status = be_mbox_db_ready_wait(adapter, db);
226 if (status != 0)
227 return status;
228
6b7c5b94
SP		 229 val |= MPU_MAILBOX_DB_HI_MASK;
230 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
231 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
232 iowrite32(val, db);
233
234 /* wait for ready to be set */
5f0b849e 235 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 236 if (status != 0)
237 return status;
238
239 val = 0;
6b7c5b94
SP		 240 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
241 val |= (u32)(mbox_mem->dma >> 4) << 2;
242 iowrite32(val, db);
243
5f0b849e 244 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 245 if (status != 0)
246 return status;
247
5fb379ee 248 /* A cq entry has been made now */
efd2e40a
SP		 249 if (be_mcc_compl_is_new(compl)) {
250 status = be_mcc_compl_process(adapter, &mbox->compl);
251 be_mcc_compl_use(compl);
5fb379ee
SP		 252 if (status)
253 return status;
254 } else {
5f0b849e 255 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 256 return -1;
257 }
5fb379ee 258 return 0;
6b7c5b94
SP		 259}
260
8788fdc2 261static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
6b7c5b94 262{
8788fdc2 263 u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
6b7c5b94
SP		 264
265 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
266 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
267 return -1;
268 else
269 return 0;
270}
271
8788fdc2 272int be_cmd_POST(struct be_adapter *adapter)
6b7c5b94 273{
43a04fdc
SP		 274 u16 stage;
275 int status, timeout = 0;
6b7c5b94 276
43a04fdc
SP		 277 do {
278 status = be_POST_stage_get(adapter, &stage);
279 if (status) {
280 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
281 stage);
282 return -1;
283 } else if (stage != POST_STAGE_ARMFW_RDY) {
284 set_current_state(TASK_INTERRUPTIBLE);
285 schedule_timeout(2 * HZ);
286 timeout += 2;
287 } else {
288 return 0;
289 }
290 } while (timeout < 20);
6b7c5b94 291
43a04fdc
SP		 292 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
293 return -1;
6b7c5b94
SP		 294}
295
296static inline void *embedded_payload(struct be_mcc_wrb *wrb)
297{
298 return wrb->payload.embedded_payload;
299}
300
301static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
302{
303 return &wrb->payload.sgl[0];
304}
305
306/* Don't touch the hdr after it's prepared */
307static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
d744b44e 308 bool embedded, u8 sge_cnt, u32 opcode)
6b7c5b94
SP		 309{
310 if (embedded)
311 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
312 else
313 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
314 MCC_WRB_SGE_CNT_SHIFT;
315 wrb->payload_length = payload_len;
d744b44e 316 wrb->tag0 = opcode;
fa4281bb 317 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 318}
319
320/* Don't touch the hdr after it's prepared */
321static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
322 u8 subsystem, u8 opcode, int cmd_len)
323{
324 req_hdr->opcode = opcode;
325 req_hdr->subsystem = subsystem;
326 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 327 req_hdr->version = 0;
6b7c5b94
SP		 328}
329
330static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
331 struct be_dma_mem *mem)
332{
333 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
334 u64 dma = (u64)mem->dma;
335
336 for (i = 0; i < buf_pages; i++) {
337 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
338 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
339 dma += PAGE_SIZE_4K;
340 }
341}
342
343/* Converts interrupt delay in microseconds to multiplier value */
344static u32 eq_delay_to_mult(u32 usec_delay)
345{
346#define MAX_INTR_RATE 651042
347 const u32 round = 10;
348 u32 multiplier;
349
350 if (usec_delay == 0)
351 multiplier = 0;
352 else {
353 u32 interrupt_rate = 1000000 / usec_delay;
354 /* Max delay, corresponding to the lowest interrupt rate */
355 if (interrupt_rate == 0)
356 multiplier = 1023;
357 else {
358 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
359 multiplier /= interrupt_rate;
360 /* Round the multiplier to the closest value.*/
361 multiplier = (multiplier + round/2) / round;
362 multiplier = min(multiplier, (u32)1023);
363 }
364 }
365 return multiplier;
366}
367
b31c50a7 368static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 369{
b31c50a7
SP		 370 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
371 struct be_mcc_wrb *wrb
372 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
373 memset(wrb, 0, sizeof(*wrb));
374 return wrb;
6b7c5b94
SP		 375}
376
b31c50a7 377static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 378{
b31c50a7
SP		 379 struct be_queue_info *mccq = &adapter->mcc_obj.q;
380 struct be_mcc_wrb *wrb;
381
713d0394
SP		 382 if (atomic_read(&mccq->used) >= mccq->len) {
383 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
384 return NULL;
385 }
386
b31c50a7
SP		 387 wrb = queue_head_node(mccq);
388 queue_head_inc(mccq);
389 atomic_inc(&mccq->used);
390 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 391 return wrb;
392}
393
2243e2e9
SP		 394/* Tell fw we're about to start firing cmds by writing a
395 * special pattern across the wrb hdr; uses mbox
396 */
397int be_cmd_fw_init(struct be_adapter *adapter)
398{
399 u8 *wrb;
400 int status;
401
402 spin_lock(&adapter->mbox_lock);
403
404 wrb = (u8 *)wrb_from_mbox(adapter);
405 *wrb++ = 0xFF;
406 *wrb++ = 0x12;
407 *wrb++ = 0x34;
408 *wrb++ = 0xFF;
409 *wrb++ = 0xFF;
410 *wrb++ = 0x56;
411 *wrb++ = 0x78;
412 *wrb = 0xFF;
413
414 status = be_mbox_notify_wait(adapter);
415
416 spin_unlock(&adapter->mbox_lock);
417 return status;
418}
419
420/* Tell fw we're done with firing cmds by writing a
421 * special pattern across the wrb hdr; uses mbox
422 */
423int be_cmd_fw_clean(struct be_adapter *adapter)
424{
425 u8 *wrb;
426 int status;
427
cf588477
SP		 428 if (adapter->eeh_err)
429 return -EIO;
430
2243e2e9
SP		 431 spin_lock(&adapter->mbox_lock);
432
433 wrb = (u8 *)wrb_from_mbox(adapter);
434 *wrb++ = 0xFF;
435 *wrb++ = 0xAA;
436 *wrb++ = 0xBB;
437 *wrb++ = 0xFF;
438 *wrb++ = 0xFF;
439 *wrb++ = 0xCC;
440 *wrb++ = 0xDD;
441 *wrb = 0xFF;
442
443 status = be_mbox_notify_wait(adapter);
444
445 spin_unlock(&adapter->mbox_lock);
446 return status;
447}
8788fdc2 448int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94
SP		 449 struct be_queue_info *eq, int eq_delay)
450{
b31c50a7
SP		 451 struct be_mcc_wrb *wrb;
452 struct be_cmd_req_eq_create *req;
6b7c5b94
SP		 453 struct be_dma_mem *q_mem = &eq->dma_mem;
454 int status;
455
8788fdc2 456 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 457
458 wrb = wrb_from_mbox(adapter);
459 req = embedded_payload(wrb);
6b7c5b94 460
d744b44e 461 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
6b7c5b94
SP		 462
463 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
464 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
465
466 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
467
6b7c5b94
SP		 468 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
469 /* 4byte eqe*/
470 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
471 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
472 __ilog2_u32(eq->len/256));
473 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
474 eq_delay_to_mult(eq_delay));
475 be_dws_cpu_to_le(req->context, sizeof(req->context));
476
477 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
478
b31c50a7 479 status = be_mbox_notify_wait(adapter);
6b7c5b94 480 if (!status) {
b31c50a7 481 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 482 eq->id = le16_to_cpu(resp->eq_id);
483 eq->created = true;
484 }
b31c50a7 485
8788fdc2 486 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 487 return status;
488}
489
b31c50a7 490/* Uses mbox */
8788fdc2 491int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94
SP		 492 u8 type, bool permanent, u32 if_handle)
493{
b31c50a7
SP		 494 struct be_mcc_wrb *wrb;
495 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 496 int status;
497
8788fdc2 498 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 499
500 wrb = wrb_from_mbox(adapter);
501 req = embedded_payload(wrb);
6b7c5b94 502
d744b44e
AK		 503 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
504 OPCODE_COMMON_NTWK_MAC_QUERY);
6b7c5b94
SP		 505
506 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
507 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
508
509 req->type = type;
510 if (permanent) {
511 req->permanent = 1;
512 } else {
b31c50a7 513 req->if_id = cpu_to_le16((u16) if_handle);
6b7c5b94
SP		 514 req->permanent = 0;
515 }
516
b31c50a7
SP		 517 status = be_mbox_notify_wait(adapter);
518 if (!status) {
519 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
6b7c5b94 520 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 521 }
6b7c5b94 522
8788fdc2 523 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 524 return status;
525}
526
b31c50a7 527/* Uses synchronous MCCQ */
8788fdc2 528int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94
SP		 529 u32 if_id, u32 *pmac_id)
530{
b31c50a7
SP		 531 struct be_mcc_wrb *wrb;
532 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 533 int status;
534
b31c50a7
SP		 535 spin_lock_bh(&adapter->mcc_lock);
536
537 wrb = wrb_from_mccq(adapter);
713d0394
SP		 538 if (!wrb) {
539 status = -EBUSY;
540 goto err;
541 }
b31c50a7 542 req = embedded_payload(wrb);
6b7c5b94 543
d744b44e
AK		 544 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
545 OPCODE_COMMON_NTWK_PMAC_ADD);
6b7c5b94
SP		 546
547 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
548 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
549
550 req->if_id = cpu_to_le32(if_id);
551 memcpy(req->mac_address, mac_addr, ETH_ALEN);
552
b31c50a7 553 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 554 if (!status) {
555 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
556 *pmac_id = le32_to_cpu(resp->pmac_id);
557 }
558
713d0394 559err:
b31c50a7 560 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 561 return status;
562}
563
b31c50a7 564/* Uses synchronous MCCQ */
8788fdc2 565int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
6b7c5b94 566{
b31c50a7
SP		 567 struct be_mcc_wrb *wrb;
568 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 569 int status;
570
b31c50a7
SP		 571 spin_lock_bh(&adapter->mcc_lock);
572
573 wrb = wrb_from_mccq(adapter);
713d0394
SP		 574 if (!wrb) {
575 status = -EBUSY;
576 goto err;
577 }
b31c50a7 578 req = embedded_payload(wrb);
6b7c5b94 579
d744b44e
AK		 580 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
581 OPCODE_COMMON_NTWK_PMAC_DEL);
6b7c5b94
SP		 582
583 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
584 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
585
586 req->if_id = cpu_to_le32(if_id);
587 req->pmac_id = cpu_to_le32(pmac_id);
588
b31c50a7
SP		 589 status = be_mcc_notify_wait(adapter);
590
713d0394 591err:
b31c50a7 592 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 593 return status;
594}
595
b31c50a7 596/* Uses Mbox */
8788fdc2 597int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 598 struct be_queue_info *cq, struct be_queue_info *eq,
599 bool sol_evts, bool no_delay, int coalesce_wm)
600{
b31c50a7
SP		 601 struct be_mcc_wrb *wrb;
602 struct be_cmd_req_cq_create *req;
6b7c5b94 603 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 604 void *ctxt;
6b7c5b94
SP		 605 int status;
606
8788fdc2 607 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 608
609 wrb = wrb_from_mbox(adapter);
610 req = embedded_payload(wrb);
611 ctxt = &req->context;
6b7c5b94 612
d744b44e
AK		 613 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
614 OPCODE_COMMON_CQ_CREATE);
6b7c5b94
SP		 615
616 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
617 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
618
619 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
620
621 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
622 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
623 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
624 __ilog2_u32(cq->len/256));
625 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
626 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
627 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
628 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
5fb379ee 629 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
6b7c5b94
SP		 630 be_dws_cpu_to_le(ctxt, sizeof(req->context));
631
632 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
633
b31c50a7 634 status = be_mbox_notify_wait(adapter);
6b7c5b94 635 if (!status) {
b31c50a7 636 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 637 cq->id = le16_to_cpu(resp->cq_id);
638 cq->created = true;
639 }
b31c50a7 640
8788fdc2 641 spin_unlock(&adapter->mbox_lock);
5fb379ee
SP		 642
643 return status;
644}
645
646static u32 be_encoded_q_len(int q_len)
647{
648 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
649 if (len_encoded == 16)
650 len_encoded = 0;
651 return len_encoded;
652}
653
8788fdc2 654int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 655 struct be_queue_info *mccq,
656 struct be_queue_info *cq)
657{
b31c50a7
SP		 658 struct be_mcc_wrb *wrb;
659 struct be_cmd_req_mcc_create *req;
5fb379ee 660 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 661 void *ctxt;
5fb379ee
SP		 662 int status;
663
8788fdc2 664 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 665
666 wrb = wrb_from_mbox(adapter);
667 req = embedded_payload(wrb);
668 ctxt = &req->context;
5fb379ee 669
d744b44e
AK		 670 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
671 OPCODE_COMMON_MCC_CREATE);
5fb379ee
SP		 672
673 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
674 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
675
d4a2ac3e 676 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
5fb379ee 677
5fb379ee
SP		 678 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
679 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
680 be_encoded_q_len(mccq->len));
681 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
682
683 be_dws_cpu_to_le(ctxt, sizeof(req->context));
684
685 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
686
b31c50a7 687 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 688 if (!status) {
689 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
690 mccq->id = le16_to_cpu(resp->id);
691 mccq->created = true;
692 }
8788fdc2 693 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 694
695 return status;
696}
697
8788fdc2 698int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 699 struct be_queue_info *txq,
700 struct be_queue_info *cq)
701{
b31c50a7
SP		 702 struct be_mcc_wrb *wrb;
703 struct be_cmd_req_eth_tx_create *req;
6b7c5b94 704 struct be_dma_mem *q_mem = &txq->dma_mem;
b31c50a7 705 void *ctxt;
6b7c5b94 706 int status;
6b7c5b94 707
8788fdc2 708 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 709
710 wrb = wrb_from_mbox(adapter);
711 req = embedded_payload(wrb);
712 ctxt = &req->context;
6b7c5b94 713
d744b44e
AK		 714 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
715 OPCODE_ETH_TX_CREATE);
6b7c5b94
SP		 716
717 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
718 sizeof(*req));
719
720 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
721 req->ulp_num = BE_ULP1_NUM;
722 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
723
b31c50a7
SP		 724 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
725 be_encoded_q_len(txq->len));
6b7c5b94
SP		 726 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
727 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
728
729 be_dws_cpu_to_le(ctxt, sizeof(req->context));
730
731 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
732
b31c50a7 733 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 734 if (!status) {
735 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
736 txq->id = le16_to_cpu(resp->cid);
737 txq->created = true;
738 }
b31c50a7 739
8788fdc2 740 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 741
742 return status;
743}
744
b31c50a7 745/* Uses mbox */
8788fdc2 746int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94
SP		 747 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
748 u16 max_frame_size, u32 if_id, u32 rss)
749{
b31c50a7
SP		 750 struct be_mcc_wrb *wrb;
751 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 752 struct be_dma_mem *q_mem = &rxq->dma_mem;
753 int status;
754
8788fdc2 755 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 756
757 wrb = wrb_from_mbox(adapter);
758 req = embedded_payload(wrb);
6b7c5b94 759
d744b44e
AK		 760 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
761 OPCODE_ETH_RX_CREATE);
6b7c5b94
SP		 762
763 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
764 sizeof(*req));
765
766 req->cq_id = cpu_to_le16(cq_id);
767 req->frag_size = fls(frag_size) - 1;
768 req->num_pages = 2;
769 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
770 req->interface_id = cpu_to_le32(if_id);
771 req->max_frame_size = cpu_to_le16(max_frame_size);
772 req->rss_queue = cpu_to_le32(rss);
773
b31c50a7 774 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 775 if (!status) {
776 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
777 rxq->id = le16_to_cpu(resp->id);
778 rxq->created = true;
779 }
b31c50a7 780
8788fdc2 781 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 782
783 return status;
784}
785
b31c50a7
SP		 786/* Generic destroyer function for all types of queues
787 * Uses Mbox
788 */
8788fdc2 789int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94
SP		 790 int queue_type)
791{
b31c50a7
SP		 792 struct be_mcc_wrb *wrb;
793 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 794 u8 subsys = 0, opcode = 0;
795 int status;
796
cf588477
SP		 797 if (adapter->eeh_err)
798 return -EIO;
799
8788fdc2 800 spin_lock(&adapter->mbox_lock);
6b7c5b94 801
b31c50a7
SP		 802 wrb = wrb_from_mbox(adapter);
803 req = embedded_payload(wrb);
804
6b7c5b94
SP		 805 switch (queue_type) {
806 case QTYPE_EQ:
807 subsys = CMD_SUBSYSTEM_COMMON;
808 opcode = OPCODE_COMMON_EQ_DESTROY;
809 break;
810 case QTYPE_CQ:
811 subsys = CMD_SUBSYSTEM_COMMON;
812 opcode = OPCODE_COMMON_CQ_DESTROY;
813 break;
814 case QTYPE_TXQ:
815 subsys = CMD_SUBSYSTEM_ETH;
816 opcode = OPCODE_ETH_TX_DESTROY;
817 break;
818 case QTYPE_RXQ:
819 subsys = CMD_SUBSYSTEM_ETH;
820 opcode = OPCODE_ETH_RX_DESTROY;
821 break;
5fb379ee
SP		 822 case QTYPE_MCCQ:
823 subsys = CMD_SUBSYSTEM_COMMON;
824 opcode = OPCODE_COMMON_MCC_DESTROY;
825 break;
6b7c5b94 826 default:
5f0b849e 827 BUG();
6b7c5b94 828 }
d744b44e
AK		 829
830 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
831
6b7c5b94
SP		 832 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
833 req->id = cpu_to_le16(q->id);
834
b31c50a7 835 status = be_mbox_notify_wait(adapter);
5f0b849e 836
8788fdc2 837 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 838
839 return status;
840}
841
b31c50a7
SP		 842/* Create an rx filtering policy configuration on an i/f
843 * Uses mbox
844 */
73d540f2
SP		 845int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
846 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
6b7c5b94 847{
b31c50a7
SP		 848 struct be_mcc_wrb *wrb;
849 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 850 int status;
851
8788fdc2 852 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 853
854 wrb = wrb_from_mbox(adapter);
855 req = embedded_payload(wrb);
6b7c5b94 856
d744b44e
AK		 857 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
858 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
6b7c5b94
SP		 859
860 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
861 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
862
73d540f2
SP		 863 req->capability_flags = cpu_to_le32(cap_flags);
864 req->enable_flags = cpu_to_le32(en_flags);
b31c50a7 865 req->pmac_invalid = pmac_invalid;
6b7c5b94
SP		 866 if (!pmac_invalid)
867 memcpy(req->mac_addr, mac, ETH_ALEN);
868
b31c50a7 869 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 870 if (!status) {
871 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
872 *if_handle = le32_to_cpu(resp->interface_id);
873 if (!pmac_invalid)
874 *pmac_id = le32_to_cpu(resp->pmac_id);
875 }
876
8788fdc2 877 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 878 return status;
879}
880
b31c50a7 881/* Uses mbox */
8788fdc2 882int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
6b7c5b94 883{
b31c50a7
SP		 884 struct be_mcc_wrb *wrb;
885 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 886 int status;
887
cf588477
SP		 888 if (adapter->eeh_err)
889 return -EIO;
890
8788fdc2 891 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 892
893 wrb = wrb_from_mbox(adapter);
894 req = embedded_payload(wrb);
6b7c5b94 895
d744b44e
AK		 896 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
897 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
6b7c5b94
SP		 898
899 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
900 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
901
902 req->interface_id = cpu_to_le32(interface_id);
b31c50a7
SP		 903
904 status = be_mbox_notify_wait(adapter);
6b7c5b94 905
8788fdc2 906 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 907
908 return status;
909}
910
911/* Get stats is a non embedded command: the request is not embedded inside
912 * WRB but is a separate dma memory block
b31c50a7 913 * Uses asynchronous MCC
6b7c5b94 914 */
8788fdc2 915int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 916{
b31c50a7
SP		 917 struct be_mcc_wrb *wrb;
918 struct be_cmd_req_get_stats *req;
919 struct be_sge *sge;
713d0394 920 int status = 0;
6b7c5b94 921
b31c50a7 922 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 923
b31c50a7 924 wrb = wrb_from_mccq(adapter);
713d0394
SP		 925 if (!wrb) {
926 status = -EBUSY;
927 goto err;
928 }
b31c50a7
SP		 929 req = nonemb_cmd->va;
930 sge = nonembedded_sgl(wrb);
6b7c5b94 931
d744b44e
AK		 932 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
933 OPCODE_ETH_GET_STATISTICS);
6b7c5b94
SP		 934
935 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
936 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
937 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
938 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
939 sge->len = cpu_to_le32(nonemb_cmd->size);
940
b31c50a7 941 be_mcc_notify(adapter);
6b7c5b94 942
713d0394 943err:
b31c50a7 944 spin_unlock_bh(&adapter->mcc_lock);
713d0394 945 return status;
6b7c5b94
SP		 946}
947
b31c50a7 948/* Uses synchronous mcc */
8788fdc2 949int be_cmd_link_status_query(struct be_adapter *adapter,
0388f251 950 bool *link_up, u8 *mac_speed, u16 *link_speed)
6b7c5b94 951{
b31c50a7
SP		 952 struct be_mcc_wrb *wrb;
953 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 954 int status;
955
b31c50a7
SP		 956 spin_lock_bh(&adapter->mcc_lock);
957
958 wrb = wrb_from_mccq(adapter);
713d0394
SP		 959 if (!wrb) {
960 status = -EBUSY;
961 goto err;
962 }
b31c50a7 963 req = embedded_payload(wrb);
a8f447bd
SP		 964
965 *link_up = false;
6b7c5b94 966
d744b44e
AK		 967 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
968 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
6b7c5b94
SP		 969
970 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
971 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
972
b31c50a7 973 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 974 if (!status) {
975 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
0388f251 976 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
a8f447bd 977 *link_up = true;
0388f251
SB		 978 *link_speed = le16_to_cpu(resp->link_speed);
979 *mac_speed = resp->mac_speed;
980 }
6b7c5b94
SP		 981 }
982
713d0394 983err:
b31c50a7 984 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 985 return status;
986}
987
b31c50a7 988/* Uses Mbox */
8788fdc2 989int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
6b7c5b94 990{
b31c50a7
SP		 991 struct be_mcc_wrb *wrb;
992 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 993 int status;
994
8788fdc2 995 spin_lock(&adapter->mbox_lock);
b31c50a7
SP		 996
997 wrb = wrb_from_mbox(adapter);
998 req = embedded_payload(wrb);
6b7c5b94 999
d744b44e
AK		 1000 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1001 OPCODE_COMMON_GET_FW_VERSION);
6b7c5b94
SP		 1002
1003 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1004 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1005
b31c50a7 1006 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 1007 if (!status) {
1008 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1009 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1010 }
1011
8788fdc2 1012 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1013 return status;
1014}
1015
b31c50a7
SP		 1016/* set the EQ delay interval of an EQ to specified value
1017 * Uses async mcc
1018 */
8788fdc2 1019int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
6b7c5b94 1020{
b31c50a7
SP		 1021 struct be_mcc_wrb *wrb;
1022 struct be_cmd_req_modify_eq_delay *req;
713d0394 1023 int status = 0;
6b7c5b94 1024
b31c50a7
SP		 1025 spin_lock_bh(&adapter->mcc_lock);
1026
1027 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1028 if (!wrb) {
1029 status = -EBUSY;
1030 goto err;
1031 }
b31c50a7 1032 req = embedded_payload(wrb);
6b7c5b94 1033
d744b44e
AK		 1034 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1035 OPCODE_COMMON_MODIFY_EQ_DELAY);
6b7c5b94
SP		 1036
1037 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1038 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1039
1040 req->num_eq = cpu_to_le32(1);
1041 req->delay[0].eq_id = cpu_to_le32(eq_id);
1042 req->delay[0].phase = 0;
1043 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1044
b31c50a7 1045 be_mcc_notify(adapter);
6b7c5b94 1046
713d0394 1047err:
b31c50a7 1048 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1049 return status;
6b7c5b94
SP		 1050}
1051
b31c50a7 1052/* Uses sycnhronous mcc */
8788fdc2 1053int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
6b7c5b94
SP		 1054 u32 num, bool untagged, bool promiscuous)
1055{
b31c50a7
SP		 1056 struct be_mcc_wrb *wrb;
1057 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1058 int status;
1059
b31c50a7
SP		 1060 spin_lock_bh(&adapter->mcc_lock);
1061
1062 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1063 if (!wrb) {
1064 status = -EBUSY;
1065 goto err;
1066 }
b31c50a7 1067 req = embedded_payload(wrb);
6b7c5b94 1068
d744b44e
AK		 1069 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1070 OPCODE_COMMON_NTWK_VLAN_CONFIG);
6b7c5b94
SP		 1071
1072 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1073 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1074
1075 req->interface_id = if_id;
1076 req->promiscuous = promiscuous;
1077 req->untagged = untagged;
1078 req->num_vlan = num;
1079 if (!promiscuous) {
1080 memcpy(req->normal_vlan, vtag_array,
1081 req->num_vlan * sizeof(vtag_array[0]));
1082 }
1083
b31c50a7 1084 status = be_mcc_notify_wait(adapter);
6b7c5b94 1085
713d0394 1086err:
b31c50a7 1087 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1088 return status;
1089}
1090
b31c50a7
SP		 1091/* Uses MCC for this command as it may be called in BH context
1092 * Uses synchronous mcc
1093 */
8788fdc2 1094int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
6b7c5b94 1095{
6ac7b687
SP		 1096 struct be_mcc_wrb *wrb;
1097 struct be_cmd_req_promiscuous_config *req;
b31c50a7 1098 int status;
6b7c5b94 1099
8788fdc2 1100 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1101
b31c50a7 1102 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1103 if (!wrb) {
1104 status = -EBUSY;
1105 goto err;
1106 }
6ac7b687 1107 req = embedded_payload(wrb);
6b7c5b94 1108
d744b44e 1109 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
6b7c5b94
SP		 1110
1111 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1112 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1113
1114 if (port_num)
1115 req->port1_promiscuous = en;
1116 else
1117 req->port0_promiscuous = en;
1118
b31c50a7 1119 status = be_mcc_notify_wait(adapter);
6b7c5b94 1120
713d0394 1121err:
8788fdc2 1122 spin_unlock_bh(&adapter->mcc_lock);
b31c50a7 1123 return status;
6b7c5b94
SP		 1124}
1125
6ac7b687 1126/*
b31c50a7 1127 * Uses MCC for this command as it may be called in BH context
6ac7b687
SP		 1128 * (mc == NULL) => multicast promiscous
1129 */
8788fdc2 1130int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
0ddf477b 1131 struct net_device *netdev, struct be_dma_mem *mem)
6b7c5b94 1132{
6ac7b687 1133 struct be_mcc_wrb *wrb;
e7b909a6
SP		 1134 struct be_cmd_req_mcast_mac_config *req = mem->va;
1135 struct be_sge *sge;
1136 int status;
6b7c5b94 1137
8788fdc2 1138 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1139
b31c50a7 1140 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1141 if (!wrb) {
1142 status = -EBUSY;
1143 goto err;
1144 }
e7b909a6
SP		 1145 sge = nonembedded_sgl(wrb);
1146 memset(req, 0, sizeof(*req));
6b7c5b94 1147
d744b44e
AK		 1148 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1149 OPCODE_COMMON_NTWK_MULTICAST_SET);
e7b909a6
SP		 1150 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1151 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1152 sge->len = cpu_to_le32(mem->size);
6b7c5b94
SP		 1153
1154 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1155 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1156
1157 req->interface_id = if_id;
0ddf477b 1158 if (netdev) {
24307eef
SP		 1159 int i;
1160 struct dev_mc_list *mc;
1161
0ddf477b 1162 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
24307eef 1163
0ddf477b
JP		 1164 i = 0;
1165 netdev_for_each_mc_addr(mc, netdev)
24307eef
SP		 1166 memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
1167 } else {
1168 req->promiscuous = 1;
6b7c5b94
SP		 1169 }
1170
e7b909a6 1171 status = be_mcc_notify_wait(adapter);
6b7c5b94 1172
713d0394 1173err:
8788fdc2 1174 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1175 return status;
6b7c5b94
SP		 1176}
1177
b31c50a7 1178/* Uses synchrounous mcc */
8788fdc2 1179int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1180{
b31c50a7
SP		 1181 struct be_mcc_wrb *wrb;
1182 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1183 int status;
1184
b31c50a7 1185 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1186
b31c50a7 1187 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1188 if (!wrb) {
1189 status = -EBUSY;
1190 goto err;
1191 }
b31c50a7 1192 req = embedded_payload(wrb);
6b7c5b94 1193
d744b44e
AK		 1194 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1195 OPCODE_COMMON_SET_FLOW_CONTROL);
6b7c5b94
SP		 1196
1197 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1198 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1199
1200 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1201 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1202
b31c50a7 1203 status = be_mcc_notify_wait(adapter);
6b7c5b94 1204
713d0394 1205err:
b31c50a7 1206 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1207 return status;
1208}
1209
b31c50a7 1210/* Uses sycn mcc */
8788fdc2 1211int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1212{
b31c50a7
SP		 1213 struct be_mcc_wrb *wrb;
1214 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1215 int status;
1216
b31c50a7 1217 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1218
b31c50a7 1219 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1220 if (!wrb) {
1221 status = -EBUSY;
1222 goto err;
1223 }
b31c50a7 1224 req = embedded_payload(wrb);
6b7c5b94 1225
d744b44e
AK		 1226 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1227 OPCODE_COMMON_GET_FLOW_CONTROL);
6b7c5b94
SP		 1228
1229 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1230 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1231
b31c50a7 1232 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1233 if (!status) {
1234 struct be_cmd_resp_get_flow_control *resp =
1235 embedded_payload(wrb);
1236 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1237 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1238 }
1239
713d0394 1240err:
b31c50a7 1241 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1242 return status;
1243}
1244
b31c50a7 1245/* Uses mbox */
dcb9b564 1246int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
6b7c5b94 1247{
b31c50a7
SP		 1248 struct be_mcc_wrb *wrb;
1249 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 1250 int status;
1251
8788fdc2 1252 spin_lock(&adapter->mbox_lock);
6b7c5b94 1253
b31c50a7
SP		 1254 wrb = wrb_from_mbox(adapter);
1255 req = embedded_payload(wrb);
6b7c5b94 1256
d744b44e
AK		 1257 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1258 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
6b7c5b94
SP		 1259
1260 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1261 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1262
b31c50a7 1263 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 1264 if (!status) {
1265 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1266 *port_num = le32_to_cpu(resp->phys_port);
dcb9b564 1267 *cap = le32_to_cpu(resp->function_cap);
6b7c5b94
SP		 1268 }
1269
8788fdc2 1270 spin_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1271 return status;
1272}
14074eab 1273
b31c50a7 1274/* Uses mbox */
14074eab 1275int be_cmd_reset_function(struct be_adapter *adapter)
1276{
b31c50a7
SP		 1277 struct be_mcc_wrb *wrb;
1278 struct be_cmd_req_hdr *req;
14074eab 1279 int status;
1280
1281 spin_lock(&adapter->mbox_lock);
1282
b31c50a7
SP		 1283 wrb = wrb_from_mbox(adapter);
1284 req = embedded_payload(wrb);
14074eab 1285
d744b44e
AK		 1286 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1287 OPCODE_COMMON_FUNCTION_RESET);
14074eab 1288
1289 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1290 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1291
b31c50a7 1292 status = be_mbox_notify_wait(adapter);
14074eab 1293
1294 spin_unlock(&adapter->mbox_lock);
1295 return status;
1296}
84517482 1297
fad9ab2c
SB		 1298/* Uses sync mcc */
1299int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1300 u8 bcn, u8 sts, u8 state)
1301{
1302 struct be_mcc_wrb *wrb;
1303 struct be_cmd_req_enable_disable_beacon *req;
1304 int status;
1305
1306 spin_lock_bh(&adapter->mcc_lock);
1307
1308 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1309 if (!wrb) {
1310 status = -EBUSY;
1311 goto err;
1312 }
fad9ab2c
SB		 1313 req = embedded_payload(wrb);
1314
d744b44e
AK		 1315 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1316 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
fad9ab2c
SB		 1317
1318 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1319 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1320
1321 req->port_num = port_num;
1322 req->beacon_state = state;
1323 req->beacon_duration = bcn;
1324 req->status_duration = sts;
1325
1326 status = be_mcc_notify_wait(adapter);
1327
713d0394 1328err:
fad9ab2c
SB		 1329 spin_unlock_bh(&adapter->mcc_lock);
1330 return status;
1331}
1332
1333/* Uses sync mcc */
1334int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1335{
1336 struct be_mcc_wrb *wrb;
1337 struct be_cmd_req_get_beacon_state *req;
1338 int status;
1339
1340 spin_lock_bh(&adapter->mcc_lock);
1341
1342 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1343 if (!wrb) {
1344 status = -EBUSY;
1345 goto err;
1346 }
fad9ab2c
SB		 1347 req = embedded_payload(wrb);
1348
d744b44e
AK		 1349 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1350 OPCODE_COMMON_GET_BEACON_STATE);
fad9ab2c
SB		 1351
1352 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1353 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1354
1355 req->port_num = port_num;
1356
1357 status = be_mcc_notify_wait(adapter);
1358 if (!status) {
1359 struct be_cmd_resp_get_beacon_state *resp =
1360 embedded_payload(wrb);
1361 *state = resp->beacon_state;
1362 }
1363
713d0394 1364err:
fad9ab2c
SB		 1365 spin_unlock_bh(&adapter->mcc_lock);
1366 return status;
1367}
1368
0388f251
SB		 1369/* Uses sync mcc */
1370int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1371 u8 *connector)
1372{
1373 struct be_mcc_wrb *wrb;
1374 struct be_cmd_req_port_type *req;
1375 int status;
1376
1377 spin_lock_bh(&adapter->mcc_lock);
1378
1379 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1380 if (!wrb) {
1381 status = -EBUSY;
1382 goto err;
1383 }
0388f251
SB		 1384 req = embedded_payload(wrb);
1385
d744b44e
AK		 1386 be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1387 OPCODE_COMMON_READ_TRANSRECV_DATA);
0388f251
SB		 1388
1389 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1390 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1391
1392 req->port = cpu_to_le32(port);
1393 req->page_num = cpu_to_le32(TR_PAGE_A0);
1394 status = be_mcc_notify_wait(adapter);
1395 if (!status) {
1396 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1397 *connector = resp->data.connector;
1398 }
1399
713d0394 1400err:
0388f251
SB		 1401 spin_unlock_bh(&adapter->mcc_lock);
1402 return status;
1403}
1404
84517482
AK		 1405int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1406 u32 flash_type, u32 flash_opcode, u32 buf_size)
1407{
b31c50a7 1408 struct be_mcc_wrb *wrb;
3f0d4560 1409 struct be_cmd_write_flashrom *req;
b31c50a7 1410 struct be_sge *sge;
84517482
AK		 1411 int status;
1412
b31c50a7
SP		 1413 spin_lock_bh(&adapter->mcc_lock);
1414
1415 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1416 if (!wrb) {
1417 status = -EBUSY;
1418 goto err;
1419 }
1420 req = cmd->va;
b31c50a7
SP		 1421 sge = nonembedded_sgl(wrb);
1422
d744b44e
AK		 1423 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1424 OPCODE_COMMON_WRITE_FLASHROM);
84517482
AK		 1425
1426 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1427 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1428 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1429 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1430 sge->len = cpu_to_le32(cmd->size);
1431
1432 req->params.op_type = cpu_to_le32(flash_type);
1433 req->params.op_code = cpu_to_le32(flash_opcode);
1434 req->params.data_buf_size = cpu_to_le32(buf_size);
1435
b31c50a7 1436 status = be_mcc_notify_wait(adapter);
84517482 1437
713d0394 1438err:
b31c50a7 1439 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 1440 return status;
1441}
fa9a6fed 1442
3f0d4560
AK		 1443int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1444 int offset)
fa9a6fed
SB		 1445{
1446 struct be_mcc_wrb *wrb;
1447 struct be_cmd_write_flashrom *req;
1448 int status;
1449
1450 spin_lock_bh(&adapter->mcc_lock);
1451
1452 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1453 if (!wrb) {
1454 status = -EBUSY;
1455 goto err;
1456 }
fa9a6fed
SB		 1457 req = embedded_payload(wrb);
1458
d744b44e
AK		 1459 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1460 OPCODE_COMMON_READ_FLASHROM);
fa9a6fed
SB		 1461
1462 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1463 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1464
3f0d4560 1465 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
fa9a6fed 1466 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
3f0d4560 1467 req->params.offset = offset;
fa9a6fed
SB		 1468 req->params.data_buf_size = 0x4;
1469
1470 status = be_mcc_notify_wait(adapter);
1471 if (!status)
1472 memcpy(flashed_crc, req->params.data_buf, 4);
1473
713d0394 1474err:
fa9a6fed
SB		 1475 spin_unlock_bh(&adapter->mcc_lock);
1476 return status;
1477}
71d8d1b5
AK		 1478
1479extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1480 struct be_dma_mem *nonemb_cmd)
1481{
1482 struct be_mcc_wrb *wrb;
1483 struct be_cmd_req_acpi_wol_magic_config *req;
1484 struct be_sge *sge;
1485 int status;
1486
1487 spin_lock_bh(&adapter->mcc_lock);
1488
1489 wrb = wrb_from_mccq(adapter);
1490 if (!wrb) {
1491 status = -EBUSY;
1492 goto err;
1493 }
1494 req = nonemb_cmd->va;
1495 sge = nonembedded_sgl(wrb);
1496
1497 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1498 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1499
1500 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1501 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1502 memcpy(req->magic_mac, mac, ETH_ALEN);
1503
1504 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1505 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1506 sge->len = cpu_to_le32(nonemb_cmd->size);
1507
1508 status = be_mcc_notify_wait(adapter);
1509
1510err:
1511 spin_unlock_bh(&adapter->mcc_lock);
1512 return status;
1513}
ff33a6e2 1514
fced9999
SB		 1515int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1516 u8 loopback_type, u8 enable)
1517{
1518 struct be_mcc_wrb *wrb;
1519 struct be_cmd_req_set_lmode *req;
1520 int status;
1521
1522 spin_lock_bh(&adapter->mcc_lock);
1523
1524 wrb = wrb_from_mccq(adapter);
1525 if (!wrb) {
1526 status = -EBUSY;
1527 goto err;
1528 }
1529
1530 req = embedded_payload(wrb);
1531
1532 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1533 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1534
1535 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1536 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1537 sizeof(*req));
1538
1539 req->src_port = port_num;
1540 req->dest_port = port_num;
1541 req->loopback_type = loopback_type;
1542 req->loopback_state = enable;
1543
1544 status = be_mcc_notify_wait(adapter);
1545err:
1546 spin_unlock_bh(&adapter->mcc_lock);
1547 return status;
1548}
1549
ff33a6e2
S		 1550int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1551 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1552{
1553 struct be_mcc_wrb *wrb;
1554 struct be_cmd_req_loopback_test *req;
1555 int status;
1556
1557 spin_lock_bh(&adapter->mcc_lock);
1558
1559 wrb = wrb_from_mccq(adapter);
1560 if (!wrb) {
1561 status = -EBUSY;
1562 goto err;
1563 }
1564
1565 req = embedded_payload(wrb);
1566
1567 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1568 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1569
1570 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1571 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
d7b90141 1572 req->hdr.timeout = 4;
ff33a6e2
S		 1573
1574 req->pattern = cpu_to_le64(pattern);
1575 req->src_port = cpu_to_le32(port_num);
1576 req->dest_port = cpu_to_le32(port_num);
1577 req->pkt_size = cpu_to_le32(pkt_size);
1578 req->num_pkts = cpu_to_le32(num_pkts);
1579 req->loopback_type = cpu_to_le32(loopback_type);
1580
1581 status = be_mcc_notify_wait(adapter);
1582 if (!status) {
1583 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1584 status = le32_to_cpu(resp->status);
1585 }
1586
1587err:
1588 spin_unlock_bh(&adapter->mcc_lock);
1589 return status;
1590}
1591
1592int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1593 u32 byte_cnt, struct be_dma_mem *cmd)
1594{
1595 struct be_mcc_wrb *wrb;
1596 struct be_cmd_req_ddrdma_test *req;
1597 struct be_sge *sge;
1598 int status;
1599 int i, j = 0;
1600
1601 spin_lock_bh(&adapter->mcc_lock);
1602
1603 wrb = wrb_from_mccq(adapter);
1604 if (!wrb) {
1605 status = -EBUSY;
1606 goto err;
1607 }
1608 req = cmd->va;
1609 sge = nonembedded_sgl(wrb);
1610 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1611 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1612 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1613 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1614
1615 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1616 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1617 sge->len = cpu_to_le32(cmd->size);
1618
1619 req->pattern = cpu_to_le64(pattern);
1620 req->byte_count = cpu_to_le32(byte_cnt);
1621 for (i = 0; i < byte_cnt; i++) {
1622 req->snd_buff[i] = (u8)(pattern >> (j*8));
1623 j++;
1624 if (j > 7)
1625 j = 0;
1626 }
1627
1628 status = be_mcc_notify_wait(adapter);
1629
1630 if (!status) {
1631 struct be_cmd_resp_ddrdma_test *resp;
1632 resp = cmd->va;
1633 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1634 resp->snd_err) {
1635 status = -1;
1636 }
1637 }
1638
1639err:
1640 spin_unlock_bh(&adapter->mcc_lock);
1641 return status;
1642}
368c0ca2
SB		 1643
1644extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1645 struct be_dma_mem *nonemb_cmd)
1646{
1647 struct be_mcc_wrb *wrb;
1648 struct be_cmd_req_seeprom_read *req;
1649 struct be_sge *sge;
1650 int status;
1651
1652 spin_lock_bh(&adapter->mcc_lock);
1653
1654 wrb = wrb_from_mccq(adapter);
1655 req = nonemb_cmd->va;
1656 sge = nonembedded_sgl(wrb);
1657
1658 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1659 OPCODE_COMMON_SEEPROM_READ);
1660
1661 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1662 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1663
1664 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1665 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1666 sge->len = cpu_to_le32(nonemb_cmd->size);
1667
1668 status = be_mcc_notify_wait(adapter);
1669
1670 spin_unlock_bh(&adapter->mcc_lock);
1671 return status;
1672}
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