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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[net-next-2.6.git] / drivers / net / b44.c
CommitLineData
753f4920 1/* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
1da177e4
LT		 2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
753f4920
MB		 4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
8056bfaf 7 * Copyright (C) 2006 Broadcom Corporation.
753f4920 8 * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
1da177e4
LT		 9 *
10 * Distribute under GPL.
11 */
12
2fc96fff
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
1da177e4
LT		 15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/types.h>
19#include <linux/netdevice.h>
20#include <linux/ethtool.h>
21#include <linux/mii.h>
22#include <linux/if_ether.h>
72f4861e 23#include <linux/if_vlan.h>
1da177e4
LT		 24#include <linux/etherdevice.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/init.h>
89358f90 28#include <linux/dma-mapping.h>
753f4920 29#include <linux/ssb/ssb.h>
5a0e3ad6 30#include <linux/slab.h>
1da177e4
LT		 31
32#include <asm/uaccess.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35
753f4920 36
1da177e4
LT		 37#include "b44.h"
38
39#define DRV_MODULE_NAME "b44"
753f4920 40#define DRV_MODULE_VERSION "2.0"
1da177e4
LT		 41
42#define B44_DEF_MSG_ENABLE \
43 (NETIF_MSG_DRV | \
44 NETIF_MSG_PROBE | \
45 NETIF_MSG_LINK | \
46 NETIF_MSG_TIMER | \
47 NETIF_MSG_IFDOWN | \
48 NETIF_MSG_IFUP | \
49 NETIF_MSG_RX_ERR | \
50 NETIF_MSG_TX_ERR)
51
52/* length of time before we decide the hardware is borked,
53 * and dev->tx_timeout() should be called to fix the problem
54 */
55#define B44_TX_TIMEOUT (5 * HZ)
56
57/* hardware minimum and maximum for a single frame's data payload */
58#define B44_MIN_MTU 60
59#define B44_MAX_MTU 1500
60
61#define B44_RX_RING_SIZE 512
62#define B44_DEF_RX_RING_PENDING 200
63#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
64 B44_RX_RING_SIZE)
65#define B44_TX_RING_SIZE 512
66#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
67#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
68 B44_TX_RING_SIZE)
1da177e4
LT		 69
70#define TX_RING_GAP(BP) \
71 (B44_TX_RING_SIZE - (BP)->tx_pending)
72#define TX_BUFFS_AVAIL(BP) \
73 (((BP)->tx_cons <= (BP)->tx_prod) ? \
74 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
75 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
76#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
77
4ca85795
FF		 78#define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
79#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
1da177e4
LT		 80
81/* minimum number of free TX descriptors required to wake up TX process */
82#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
83
725ad800
GZ		 84/* b44 internal pattern match filter info */
85#define B44_PATTERN_BASE 0x400
86#define B44_PATTERN_SIZE 0x80
87#define B44_PMASK_BASE 0x600
88#define B44_PMASK_SIZE 0x10
89#define B44_MAX_PATTERNS 16
90#define B44_ETHIPV6UDP_HLEN 62
91#define B44_ETHIPV4UDP_HLEN 42
92
1da177e4 93static char version[] __devinitdata =
753f4920 94 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
1da177e4 95
753f4920
MB		 96MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
97MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
1da177e4
LT		 98MODULE_LICENSE("GPL");
99MODULE_VERSION(DRV_MODULE_VERSION);
100
101static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
102module_param(b44_debug, int, 0);
103MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
104
1da177e4 105
753f4920 106#ifdef CONFIG_B44_PCI
a3aa1884 107static DEFINE_PCI_DEVICE_TABLE(b44_pci_tbl) = {
753f4920
MB		 108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
109 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
110 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
111 { 0 } /* terminate list with empty entry */
112};
1da177e4
LT		 113MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
114
753f4920
MB		 115static struct pci_driver b44_pci_driver = {
116 .name = DRV_MODULE_NAME,
117 .id_table = b44_pci_tbl,
118};
119#endif /* CONFIG_B44_PCI */
120
121static const struct ssb_device_id b44_ssb_tbl[] = {
122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
123 SSB_DEVTABLE_END
124};
125MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
126
1da177e4
LT		 127static void b44_halt(struct b44 *);
128static void b44_init_rings(struct b44 *);
5fc7d61a
MC		 129
130#define B44_FULL_RESET 1
131#define B44_FULL_RESET_SKIP_PHY 2
132#define B44_PARTIAL_RESET 3
fedb0eef
MB		 133#define B44_CHIP_RESET_FULL 4
134#define B44_CHIP_RESET_PARTIAL 5
5fc7d61a 135
00e8b3aa 136static void b44_init_hw(struct b44 *, int);
1da177e4 137
9f38c636
JL		 138static int dma_desc_align_mask;
139static int dma_desc_sync_size;
753f4920 140static int instance;
9f38c636 141
3353930d
FR		 142static const char b44_gstrings[][ETH_GSTRING_LEN] = {
143#define _B44(x...) # x,
144B44_STAT_REG_DECLARE
145#undef _B44
146};
147
753f4920
MB		 148static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
149 dma_addr_t dma_base,
150 unsigned long offset,
151 enum dma_data_direction dir)
9f38c636 152{
f225763a
MB		 153 ssb_dma_sync_single_range_for_device(sdev, dma_base,
154 offset & dma_desc_align_mask,
155 dma_desc_sync_size, dir);
9f38c636
JL		 156}
157
753f4920
MB		 158static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
159 dma_addr_t dma_base,
160 unsigned long offset,
161 enum dma_data_direction dir)
9f38c636 162{
f225763a
MB		 163 ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
164 offset & dma_desc_align_mask,
165 dma_desc_sync_size, dir);
9f38c636
JL		 166}
167
1da177e4
LT		 168static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
169{
753f4920 170 return ssb_read32(bp->sdev, reg);
1da177e4
LT		 171}
172
10badc21 173static inline void bw32(const struct b44 *bp,
1da177e4
LT		 174 unsigned long reg, unsigned long val)
175{
753f4920 176 ssb_write32(bp->sdev, reg, val);
1da177e4
LT		 177}
178
179static int b44_wait_bit(struct b44 *bp, unsigned long reg,
180 u32 bit, unsigned long timeout, const int clear)
181{
182 unsigned long i;
183
184 for (i = 0; i < timeout; i++) {
185 u32 val = br32(bp, reg);
186
187 if (clear && !(val & bit))
188 break;
189 if (!clear && (val & bit))
190 break;
191 udelay(10);
192 }
193 if (i == timeout) {
f6ca057f 194 if (net_ratelimit())
2fc96fff
JP		 195 netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
196 bit, reg, clear ? "clear" : "set");
197
1da177e4
LT		 198 return -ENODEV;
199 }
200 return 0;
201}
202
753f4920 203static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 204{
205 u32 val;
206
753f4920
MB		 207 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
208 (index << CAM_CTRL_INDEX_SHIFT)));
1da177e4 209
753f4920 210 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4 211
753f4920 212 val = br32(bp, B44_CAM_DATA_LO);
1da177e4 213
753f4920
MB		 214 data[2] = (val >> 24) & 0xFF;
215 data[3] = (val >> 16) & 0xFF;
216 data[4] = (val >> 8) & 0xFF;
217 data[5] = (val >> 0) & 0xFF;
1da177e4 218
753f4920 219 val = br32(bp, B44_CAM_DATA_HI);
1da177e4 220
753f4920
MB		 221 data[0] = (val >> 8) & 0xFF;
222 data[1] = (val >> 0) & 0xFF;
1da177e4
LT		 223}
224
753f4920 225static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 226{
227 u32 val;
228
229 val = ((u32) data[2]) << 24;
230 val |= ((u32) data[3]) << 16;
231 val |= ((u32) data[4]) << 8;
232 val |= ((u32) data[5]) << 0;
233 bw32(bp, B44_CAM_DATA_LO, val);
10badc21 234 val = (CAM_DATA_HI_VALID |
1da177e4
LT		 235 (((u32) data[0]) << 8) |
236 (((u32) data[1]) << 0));
237 bw32(bp, B44_CAM_DATA_HI, val);
238 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
239 (index << CAM_CTRL_INDEX_SHIFT)));
10badc21 240 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4
LT		 241}
242
243static inline void __b44_disable_ints(struct b44 *bp)
244{
245 bw32(bp, B44_IMASK, 0);
246}
247
248static void b44_disable_ints(struct b44 *bp)
249{
250 __b44_disable_ints(bp);
251
252 /* Flush posted writes. */
253 br32(bp, B44_IMASK);
254}
255
256static void b44_enable_ints(struct b44 *bp)
257{
258 bw32(bp, B44_IMASK, bp->imask);
259}
260
753f4920 261static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
1da177e4
LT		 262{
263 int err;
264
265 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
266 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
267 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
753f4920 268 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 269 (reg << MDIO_DATA_RA_SHIFT) |
270 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
271 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
272 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
273
274 return err;
275}
276
753f4920 277static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
1da177e4
LT		 278{
279 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
280 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
281 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
753f4920 282 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 283 (reg << MDIO_DATA_RA_SHIFT) |
284 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
285 (val & MDIO_DATA_DATA)));
286 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
287}
288
753f4920
MB		 289static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
290{
291 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
292 return 0;
293
294 return __b44_readphy(bp, bp->phy_addr, reg, val);
295}
296
297static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
298{
299 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
300 return 0;
301
302 return __b44_writephy(bp, bp->phy_addr, reg, val);
303}
304
1da177e4 305/* miilib interface */
1da177e4
LT		 306static int b44_mii_read(struct net_device *dev, int phy_id, int location)
307{
308 u32 val;
309 struct b44 *bp = netdev_priv(dev);
753f4920 310 int rc = __b44_readphy(bp, phy_id, location, &val);
1da177e4
LT		 311 if (rc)
312 return 0xffffffff;
313 return val;
314}
315
316static void b44_mii_write(struct net_device *dev, int phy_id, int location,
317 int val)
318{
319 struct b44 *bp = netdev_priv(dev);
753f4920 320 __b44_writephy(bp, phy_id, location, val);
1da177e4
LT		 321}
322
323static int b44_phy_reset(struct b44 *bp)
324{
325 u32 val;
326 int err;
327
753f4920
MB		 328 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
329 return 0;
1da177e4
LT		 330 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
331 if (err)
332 return err;
333 udelay(100);
334 err = b44_readphy(bp, MII_BMCR, &val);
335 if (!err) {
336 if (val & BMCR_RESET) {
2fc96fff 337 netdev_err(bp->dev, "PHY Reset would not complete\n");
1da177e4
LT		 338 err = -ENODEV;
339 }
340 }
341
8850dce1 342 return err;
1da177e4
LT		 343}
344
345static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
346{
347 u32 val;
348
349 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
350 bp->flags |= pause_flags;
351
352 val = br32(bp, B44_RXCONFIG);
353 if (pause_flags & B44_FLAG_RX_PAUSE)
354 val |= RXCONFIG_FLOW;
355 else
356 val &= ~RXCONFIG_FLOW;
357 bw32(bp, B44_RXCONFIG, val);
358
359 val = br32(bp, B44_MAC_FLOW);
360 if (pause_flags & B44_FLAG_TX_PAUSE)
361 val |= (MAC_FLOW_PAUSE_ENAB |
362 (0xc0 & MAC_FLOW_RX_HI_WATER));
363 else
364 val &= ~MAC_FLOW_PAUSE_ENAB;
365 bw32(bp, B44_MAC_FLOW, val);
366}
367
368static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
369{
10badc21 370 u32 pause_enab = 0;
2b474cf5
GZ		 371
372 /* The driver supports only rx pause by default because
10badc21
JG		 373 the b44 mac tx pause mechanism generates excessive
374 pause frames.
2b474cf5
GZ		 375 Use ethtool to turn on b44 tx pause if necessary.
376 */
377 if ((local & ADVERTISE_PAUSE_CAP) &&
10badc21 378 (local & ADVERTISE_PAUSE_ASYM)){
2b474cf5
GZ		 379 if ((remote & LPA_PAUSE_ASYM) &&
380 !(remote & LPA_PAUSE_CAP))
381 pause_enab |= B44_FLAG_RX_PAUSE;
1da177e4
LT		 382 }
383
384 __b44_set_flow_ctrl(bp, pause_enab);
385}
386
753f4920
MB		 387#ifdef SSB_DRIVER_MIPS
388extern char *nvram_get(char *name);
389static void b44_wap54g10_workaround(struct b44 *bp)
390{
391 const char *str;
392 u32 val;
393 int err;
394
395 /*
396 * workaround for bad hardware design in Linksys WAP54G v1.0
397 * see https://dev.openwrt.org/ticket/146
398 * check and reset bit "isolate"
399 */
400 str = nvram_get("boardnum");
401 if (!str)
402 return;
403 if (simple_strtoul(str, NULL, 0) == 2) {
404 err = __b44_readphy(bp, 0, MII_BMCR, &val);
405 if (err)
406 goto error;
407 if (!(val & BMCR_ISOLATE))
408 return;
409 val &= ~BMCR_ISOLATE;
410 err = __b44_writephy(bp, 0, MII_BMCR, val);
411 if (err)
412 goto error;
413 }
414 return;
415error:
2fc96fff 416 pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
753f4920
MB		 417}
418#else
419static inline void b44_wap54g10_workaround(struct b44 *bp)
420{
421}
422#endif
423
1da177e4
LT		 424static int b44_setup_phy(struct b44 *bp)
425{
426 u32 val;
427 int err;
428
753f4920
MB		 429 b44_wap54g10_workaround(bp);
430
431 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
432 return 0;
1da177e4
LT		 433 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
434 goto out;
435 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
436 val & MII_ALEDCTRL_ALLMSK)) != 0)
437 goto out;
438 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
439 goto out;
440 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
441 val | MII_TLEDCTRL_ENABLE)) != 0)
442 goto out;
443
444 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
445 u32 adv = ADVERTISE_CSMA;
446
447 if (bp->flags & B44_FLAG_ADV_10HALF)
448 adv |= ADVERTISE_10HALF;
449 if (bp->flags & B44_FLAG_ADV_10FULL)
450 adv |= ADVERTISE_10FULL;
451 if (bp->flags & B44_FLAG_ADV_100HALF)
452 adv |= ADVERTISE_100HALF;
453 if (bp->flags & B44_FLAG_ADV_100FULL)
454 adv |= ADVERTISE_100FULL;
455
456 if (bp->flags & B44_FLAG_PAUSE_AUTO)
457 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
458
459 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
460 goto out;
461 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
462 BMCR_ANRESTART))) != 0)
463 goto out;
464 } else {
465 u32 bmcr;
466
467 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
468 goto out;
469 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
470 if (bp->flags & B44_FLAG_100_BASE_T)
471 bmcr |= BMCR_SPEED100;
472 if (bp->flags & B44_FLAG_FULL_DUPLEX)
473 bmcr |= BMCR_FULLDPLX;
474 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
475 goto out;
476
477 /* Since we will not be negotiating there is no safe way
478 * to determine if the link partner supports flow control
479 * or not. So just disable it completely in this case.
480 */
481 b44_set_flow_ctrl(bp, 0, 0);
482 }
483
484out:
485 return err;
486}
487
488static void b44_stats_update(struct b44 *bp)
489{
490 unsigned long reg;
491 u32 *val;
492
493 val = &bp->hw_stats.tx_good_octets;
494 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
495 *val++ += br32(bp, reg);
496 }
3353930d
FR		 497
498 /* Pad */
499 reg += 8*4UL;
500
1da177e4
LT		 501 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
502 *val++ += br32(bp, reg);
503 }
504}
505
506static void b44_link_report(struct b44 *bp)
507{
508 if (!netif_carrier_ok(bp->dev)) {
2fc96fff 509 netdev_info(bp->dev, "Link is down\n");
1da177e4 510 } else {
2fc96fff
JP		 511 netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
512 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
513 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
514
515 netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
516 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
517 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
1da177e4
LT		 518 }
519}
520
521static void b44_check_phy(struct b44 *bp)
522{
523 u32 bmsr, aux;
524
753f4920
MB		 525 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
526 bp->flags |= B44_FLAG_100_BASE_T;
527 bp->flags |= B44_FLAG_FULL_DUPLEX;
528 if (!netif_carrier_ok(bp->dev)) {
529 u32 val = br32(bp, B44_TX_CTRL);
530 val |= TX_CTRL_DUPLEX;
531 bw32(bp, B44_TX_CTRL, val);
532 netif_carrier_on(bp->dev);
533 b44_link_report(bp);
534 }
535 return;
536 }
537
1da177e4
LT		 538 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
539 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
540 (bmsr != 0xffff)) {
541 if (aux & MII_AUXCTRL_SPEED)
542 bp->flags |= B44_FLAG_100_BASE_T;
543 else
544 bp->flags &= ~B44_FLAG_100_BASE_T;
545 if (aux & MII_AUXCTRL_DUPLEX)
546 bp->flags |= B44_FLAG_FULL_DUPLEX;
547 else
548 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
549
550 if (!netif_carrier_ok(bp->dev) &&
551 (bmsr & BMSR_LSTATUS)) {
552 u32 val = br32(bp, B44_TX_CTRL);
553 u32 local_adv, remote_adv;
554
555 if (bp->flags & B44_FLAG_FULL_DUPLEX)
556 val |= TX_CTRL_DUPLEX;
557 else
558 val &= ~TX_CTRL_DUPLEX;
559 bw32(bp, B44_TX_CTRL, val);
560
561 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
562 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
563 !b44_readphy(bp, MII_LPA, &remote_adv))
564 b44_set_flow_ctrl(bp, local_adv, remote_adv);
565
566 /* Link now up */
567 netif_carrier_on(bp->dev);
568 b44_link_report(bp);
569 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
570 /* Link now down */
571 netif_carrier_off(bp->dev);
572 b44_link_report(bp);
573 }
574
575 if (bmsr & BMSR_RFAULT)
2fc96fff 576 netdev_warn(bp->dev, "Remote fault detected in PHY\n");
1da177e4 577 if (bmsr & BMSR_JCD)
2fc96fff 578 netdev_warn(bp->dev, "Jabber detected in PHY\n");
1da177e4
LT		 579 }
580}
581
582static void b44_timer(unsigned long __opaque)
583{
584 struct b44 *bp = (struct b44 *) __opaque;
585
586 spin_lock_irq(&bp->lock);
587
588 b44_check_phy(bp);
589
590 b44_stats_update(bp);
591
592 spin_unlock_irq(&bp->lock);
593
a72a8179 594 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
1da177e4
LT		 595}
596
597static void b44_tx(struct b44 *bp)
598{
599 u32 cur, cons;
600
601 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
602 cur /= sizeof(struct dma_desc);
603
604 /* XXX needs updating when NETIF_F_SG is supported */
605 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
606 struct ring_info *rp = &bp->tx_buffers[cons];
607 struct sk_buff *skb = rp->skb;
608
5d9428de 609 BUG_ON(skb == NULL);
1da177e4 610
f225763a
MB		 611 ssb_dma_unmap_single(bp->sdev,
612 rp->mapping,
613 skb->len,
614 DMA_TO_DEVICE);
1da177e4
LT		 615 rp->skb = NULL;
616 dev_kfree_skb_irq(skb);
617 }
618
619 bp->tx_cons = cons;
620 if (netif_queue_stopped(bp->dev) &&
621 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
622 netif_wake_queue(bp->dev);
623
624 bw32(bp, B44_GPTIMER, 0);
625}
626
627/* Works like this. This chip writes a 'struct rx_header" 30 bytes
628 * before the DMA address you give it. So we allocate 30 more bytes
629 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
630 * point the chip at 30 bytes past where the rx_header will go.
631 */
632static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
633{
634 struct dma_desc *dp;
635 struct ring_info *src_map, *map;
636 struct rx_header *rh;
637 struct sk_buff *skb;
638 dma_addr_t mapping;
639 int dest_idx;
640 u32 ctrl;
641
642 src_map = NULL;
643 if (src_idx >= 0)
644 src_map = &bp->rx_buffers[src_idx];
645 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
646 map = &bp->rx_buffers[dest_idx];
bf0dcbd9 647 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
1da177e4
LT		 648 if (skb == NULL)
649 return -ENOMEM;
650
f225763a
MB		 651 mapping = ssb_dma_map_single(bp->sdev, skb->data,
652 RX_PKT_BUF_SZ,
653 DMA_FROM_DEVICE);
1da177e4
LT		 654
655 /* Hardware bug work-around, the chip is unable to do PCI DMA
656 to/from anything above 1GB :-( */
f225763a 657 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
28b76796 658 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
1da177e4 659 /* Sigh... */
f225763a
MB		 660 if (!ssb_dma_mapping_error(bp->sdev, mapping))
661 ssb_dma_unmap_single(bp->sdev, mapping,
662 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
1da177e4 663 dev_kfree_skb_any(skb);
bf0dcbd9 664 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
1da177e4
LT		 665 if (skb == NULL)
666 return -ENOMEM;
f225763a
MB		 667 mapping = ssb_dma_map_single(bp->sdev, skb->data,
668 RX_PKT_BUF_SZ,
669 DMA_FROM_DEVICE);
670 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
28b76796 671 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
f225763a
MB		 672 if (!ssb_dma_mapping_error(bp->sdev, mapping))
673 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
1da177e4
LT		 674 dev_kfree_skb_any(skb);
675 return -ENOMEM;
676 }
a58c891a 677 bp->force_copybreak = 1;
1da177e4
LT		 678 }
679
72f4861e 680 rh = (struct rx_header *) skb->data;
1da177e4 681
1da177e4
LT		 682 rh->len = 0;
683 rh->flags = 0;
684
685 map->skb = skb;
753f4920 686 map->mapping = mapping;
1da177e4
LT		 687
688 if (src_map != NULL)
689 src_map->skb = NULL;
690
4ca85795 691 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
1da177e4
LT		 692 if (dest_idx == (B44_RX_RING_SIZE - 1))
693 ctrl |= DESC_CTRL_EOT;
694
695 dp = &bp->rx_ring[dest_idx];
696 dp->ctrl = cpu_to_le32(ctrl);
4ca85795 697 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
1da177e4 698
9f38c636 699 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 700 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 701 dest_idx * sizeof(*dp),
753f4920 702 DMA_BIDIRECTIONAL);
9f38c636 703
1da177e4
LT		 704 return RX_PKT_BUF_SZ;
705}
706
707static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
708{
709 struct dma_desc *src_desc, *dest_desc;
710 struct ring_info *src_map, *dest_map;
711 struct rx_header *rh;
712 int dest_idx;
a7bed27d 713 __le32 ctrl;
1da177e4
LT		 714
715 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
716 dest_desc = &bp->rx_ring[dest_idx];
717 dest_map = &bp->rx_buffers[dest_idx];
718 src_desc = &bp->rx_ring[src_idx];
719 src_map = &bp->rx_buffers[src_idx];
720
721 dest_map->skb = src_map->skb;
722 rh = (struct rx_header *) src_map->skb->data;
723 rh->len = 0;
724 rh->flags = 0;
753f4920 725 dest_map->mapping = src_map->mapping;
1da177e4 726
9f38c636 727 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 728 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 729 src_idx * sizeof(*src_desc),
753f4920 730 DMA_BIDIRECTIONAL);
9f38c636 731
1da177e4
LT		 732 ctrl = src_desc->ctrl;
733 if (dest_idx == (B44_RX_RING_SIZE - 1))
734 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
735 else
736 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
737
738 dest_desc->ctrl = ctrl;
739 dest_desc->addr = src_desc->addr;
9f38c636 740
1da177e4
LT		 741 src_map->skb = NULL;
742
9f38c636 743 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 744 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 745 dest_idx * sizeof(*dest_desc),
753f4920 746 DMA_BIDIRECTIONAL);
9f38c636 747
37efa239 748 ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
f225763a
MB		 749 RX_PKT_BUF_SZ,
750 DMA_FROM_DEVICE);
1da177e4
LT		 751}
752
753static int b44_rx(struct b44 *bp, int budget)
754{
755 int received;
756 u32 cons, prod;
757
758 received = 0;
759 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
760 prod /= sizeof(struct dma_desc);
761 cons = bp->rx_cons;
762
763 while (cons != prod && budget > 0) {
764 struct ring_info *rp = &bp->rx_buffers[cons];
765 struct sk_buff *skb = rp->skb;
753f4920 766 dma_addr_t map = rp->mapping;
1da177e4
LT		 767 struct rx_header *rh;
768 u16 len;
769
f225763a 770 ssb_dma_sync_single_for_cpu(bp->sdev, map,
1da177e4 771 RX_PKT_BUF_SZ,
753f4920 772 DMA_FROM_DEVICE);
1da177e4 773 rh = (struct rx_header *) skb->data;
a7bed27d 774 len = le16_to_cpu(rh->len);
72f4861e 775 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
1da177e4
LT		 776 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
777 drop_it:
778 b44_recycle_rx(bp, cons, bp->rx_prod);
779 drop_it_no_recycle:
553e2335 780 bp->dev->stats.rx_dropped++;
1da177e4
LT		 781 goto next_pkt;
782 }
783
784 if (len == 0) {
785 int i = 0;
786
787 do {
788 udelay(2);
789 barrier();
a7bed27d 790 len = le16_to_cpu(rh->len);
1da177e4
LT		 791 } while (len == 0 && i++ < 5);
792 if (len == 0)
793 goto drop_it;
794 }
795
796 /* Omit CRC. */
797 len -= 4;
798
a58c891a 799 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
1da177e4
LT		 800 int skb_size;
801 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
802 if (skb_size < 0)
803 goto drop_it;
f225763a
MB		 804 ssb_dma_unmap_single(bp->sdev, map,
805 skb_size, DMA_FROM_DEVICE);
1da177e4 806 /* Leave out rx_header */
4ca85795
FF		 807 skb_put(skb, len + RX_PKT_OFFSET);
808 skb_pull(skb, RX_PKT_OFFSET);
1da177e4
LT		 809 } else {
810 struct sk_buff *copy_skb;
811
812 b44_recycle_rx(bp, cons, bp->rx_prod);
53639207 813 copy_skb = netdev_alloc_skb(bp->dev, len + 2);
1da177e4
LT		 814 if (copy_skb == NULL)
815 goto drop_it_no_recycle;
816
1da177e4
LT		 817 skb_reserve(copy_skb, 2);
818 skb_put(copy_skb, len);
819 /* DMA sync done above, copy just the actual packet */
72f4861e 820 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
d626f62b 821 copy_skb->data, len);
1da177e4
LT		 822 skb = copy_skb;
823 }
824 skb->ip_summed = CHECKSUM_NONE;
825 skb->protocol = eth_type_trans(skb, bp->dev);
826 netif_receive_skb(skb);
1da177e4
LT		 827 received++;
828 budget--;
829 next_pkt:
830 bp->rx_prod = (bp->rx_prod + 1) &
831 (B44_RX_RING_SIZE - 1);
832 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
833 }
834
835 bp->rx_cons = cons;
836 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
837
838 return received;
839}
840
bea3348e 841static int b44_poll(struct napi_struct *napi, int budget)
1da177e4 842{
bea3348e 843 struct b44 *bp = container_of(napi, struct b44, napi);
bea3348e 844 int work_done;
e99b1f04 845 unsigned long flags;
1da177e4 846
e99b1f04 847 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 848
849 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
850 /* spin_lock(&bp->tx_lock); */
851 b44_tx(bp);
852 /* spin_unlock(&bp->tx_lock); */
853 }
e99b1f04 854 spin_unlock_irqrestore(&bp->lock, flags);
1da177e4 855
bea3348e
SH		 856 work_done = 0;
857 if (bp->istat & ISTAT_RX)
858 work_done += b44_rx(bp, budget);
1da177e4
LT		 859
860 if (bp->istat & ISTAT_ERRORS) {
d15e9c4d 861 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 862 b44_halt(bp);
863 b44_init_rings(bp);
5fc7d61a 864 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
1da177e4 865 netif_wake_queue(bp->dev);
d15e9c4d 866 spin_unlock_irqrestore(&bp->lock, flags);
bea3348e 867 work_done = 0;
1da177e4
LT		 868 }
869
bea3348e 870 if (work_done < budget) {
288379f0 871 napi_complete(napi);
1da177e4
LT		 872 b44_enable_ints(bp);
873 }
874
bea3348e 875 return work_done;
1da177e4
LT		 876}
877
7d12e780 878static irqreturn_t b44_interrupt(int irq, void *dev_id)
1da177e4
LT		 879{
880 struct net_device *dev = dev_id;
881 struct b44 *bp = netdev_priv(dev);
1da177e4
LT		 882 u32 istat, imask;
883 int handled = 0;
884
65b984f2 885 spin_lock(&bp->lock);
1da177e4
LT		 886
887 istat = br32(bp, B44_ISTAT);
888 imask = br32(bp, B44_IMASK);
889
e78181fe
JB		 890 /* The interrupt mask register controls which interrupt bits
891 * will actually raise an interrupt to the CPU when set by hw/firmware,
892 * but doesn't mask off the bits.
1da177e4
LT		 893 */
894 istat &= imask;
895 if (istat) {
896 handled = 1;
ba5eec9c
FR		 897
898 if (unlikely(!netif_running(dev))) {
2fc96fff 899 netdev_info(dev, "late interrupt\n");
ba5eec9c
FR		 900 goto irq_ack;
901 }
902
288379f0 903 if (napi_schedule_prep(&bp->napi)) {
1da177e4
LT		 904 /* NOTE: These writes are posted by the readback of
905 * the ISTAT register below.
906 */
907 bp->istat = istat;
908 __b44_disable_ints(bp);
288379f0 909 __napi_schedule(&bp->napi);
1da177e4
LT		 910 }
911
ba5eec9c 912irq_ack:
1da177e4
LT		 913 bw32(bp, B44_ISTAT, istat);
914 br32(bp, B44_ISTAT);
915 }
65b984f2 916 spin_unlock(&bp->lock);
1da177e4
LT		 917 return IRQ_RETVAL(handled);
918}
919
920static void b44_tx_timeout(struct net_device *dev)
921{
922 struct b44 *bp = netdev_priv(dev);
923
2fc96fff 924 netdev_err(dev, "transmit timed out, resetting\n");
1da177e4
LT		 925
926 spin_lock_irq(&bp->lock);
927
928 b44_halt(bp);
929 b44_init_rings(bp);
5fc7d61a 930 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 931
932 spin_unlock_irq(&bp->lock);
933
934 b44_enable_ints(bp);
935
936 netif_wake_queue(dev);
937}
938
61357325 939static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 940{
941 struct b44 *bp = netdev_priv(dev);
c7193693 942 int rc = NETDEV_TX_OK;
1da177e4
LT		 943 dma_addr_t mapping;
944 u32 len, entry, ctrl;
22580f89 945 unsigned long flags;
1da177e4
LT		 946
947 len = skb->len;
22580f89 948 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 949
950 /* This is a hard error, log it. */
951 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
952 netif_stop_queue(dev);
2fc96fff 953 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
c7193693 954 goto err_out;
1da177e4
LT		 955 }
956
f225763a 957 mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
28b76796 958 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
f65a7177
SH		 959 struct sk_buff *bounce_skb;
960
1da177e4 961 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
f225763a
MB		 962 if (!ssb_dma_mapping_error(bp->sdev, mapping))
963 ssb_dma_unmap_single(bp->sdev, mapping, len,
964 DMA_TO_DEVICE);
1da177e4 965
9034f77b 966 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
1da177e4 967 if (!bounce_skb)
c7193693 968 goto err_out;
1da177e4 969
f225763a
MB		 970 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
971 len, DMA_TO_DEVICE);
28b76796 972 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
f225763a
MB		 973 if (!ssb_dma_mapping_error(bp->sdev, mapping))
974 ssb_dma_unmap_single(bp->sdev, mapping,
975 len, DMA_TO_DEVICE);
1da177e4 976 dev_kfree_skb_any(bounce_skb);
c7193693 977 goto err_out;
1da177e4
LT		 978 }
979
f65a7177 980 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
1da177e4
LT		 981 dev_kfree_skb_any(skb);
982 skb = bounce_skb;
983 }
984
985 entry = bp->tx_prod;
986 bp->tx_buffers[entry].skb = skb;
753f4920 987 bp->tx_buffers[entry].mapping = mapping;
1da177e4
LT		 988
989 ctrl = (len & DESC_CTRL_LEN);
990 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
991 if (entry == (B44_TX_RING_SIZE - 1))
992 ctrl |= DESC_CTRL_EOT;
993
994 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
995 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
996
9f38c636 997 if (bp->flags & B44_FLAG_TX_RING_HACK)
753f4920
MB		 998 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
999 entry * sizeof(bp->tx_ring[0]),
1000 DMA_TO_DEVICE);
9f38c636 1001
1da177e4
LT		 1002 entry = NEXT_TX(entry);
1003
1004 bp->tx_prod = entry;
1005
1006 wmb();
1007
1008 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1009 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1010 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1011 if (bp->flags & B44_FLAG_REORDER_BUG)
1012 br32(bp, B44_DMATX_PTR);
1013
1014 if (TX_BUFFS_AVAIL(bp) < 1)
1015 netif_stop_queue(dev);
1016
c7193693
FR		 1017 dev->trans_start = jiffies;
1018
1019out_unlock:
22580f89 1020 spin_unlock_irqrestore(&bp->lock, flags);
1da177e4 1021
c7193693 1022 return rc;
1da177e4 1023
c7193693
FR		 1024err_out:
1025 rc = NETDEV_TX_BUSY;
1026 goto out_unlock;
1da177e4
LT		 1027}
1028
1029static int b44_change_mtu(struct net_device *dev, int new_mtu)
1030{
1031 struct b44 *bp = netdev_priv(dev);
1032
1033 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1034 return -EINVAL;
1035
1036 if (!netif_running(dev)) {
1037 /* We'll just catch it later when the
1038 * device is up'd.
1039 */
1040 dev->mtu = new_mtu;
1041 return 0;
1042 }
1043
1044 spin_lock_irq(&bp->lock);
1045 b44_halt(bp);
1046 dev->mtu = new_mtu;
1047 b44_init_rings(bp);
5fc7d61a 1048 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1049 spin_unlock_irq(&bp->lock);
1050
1051 b44_enable_ints(bp);
10badc21 1052
1da177e4
LT		 1053 return 0;
1054}
1055
1056/* Free up pending packets in all rx/tx rings.
1057 *
1058 * The chip has been shut down and the driver detached from
1059 * the networking, so no interrupts or new tx packets will
1060 * end up in the driver. bp->lock is not held and we are not
1061 * in an interrupt context and thus may sleep.
1062 */
1063static void b44_free_rings(struct b44 *bp)
1064{
1065 struct ring_info *rp;
1066 int i;
1067
1068 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1069 rp = &bp->rx_buffers[i];
1070
1071 if (rp->skb == NULL)
1072 continue;
f225763a
MB		 1073 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1074 DMA_FROM_DEVICE);
1da177e4
LT		 1075 dev_kfree_skb_any(rp->skb);
1076 rp->skb = NULL;
1077 }
1078
1079 /* XXX needs changes once NETIF_F_SG is set... */
1080 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1081 rp = &bp->tx_buffers[i];
1082
1083 if (rp->skb == NULL)
1084 continue;
f225763a
MB		 1085 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1086 DMA_TO_DEVICE);
1da177e4
LT		 1087 dev_kfree_skb_any(rp->skb);
1088 rp->skb = NULL;
1089 }
1090}
1091
1092/* Initialize tx/rx rings for packet processing.
1093 *
1094 * The chip has been shut down and the driver detached from
1095 * the networking, so no interrupts or new tx packets will
874a6214 1096 * end up in the driver.
1da177e4
LT		 1097 */
1098static void b44_init_rings(struct b44 *bp)
1099{
1100 int i;
1101
1102 b44_free_rings(bp);
1103
1104 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1105 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1106
9f38c636 1107 if (bp->flags & B44_FLAG_RX_RING_HACK)
f225763a
MB		 1108 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1109 DMA_TABLE_BYTES,
1110 DMA_BIDIRECTIONAL);
9f38c636
JL		 1111
1112 if (bp->flags & B44_FLAG_TX_RING_HACK)
f225763a
MB		 1113 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1114 DMA_TABLE_BYTES,
1115 DMA_TO_DEVICE);
9f38c636 1116
1da177e4
LT		 1117 for (i = 0; i < bp->rx_pending; i++) {
1118 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1119 break;
1120 }
1121}
1122
1123/*
1124 * Must not be invoked with interrupt sources disabled and
1125 * the hardware shutdown down.
1126 */
1127static void b44_free_consistent(struct b44 *bp)
1128{
b4558ea9
JJ		 1129 kfree(bp->rx_buffers);
1130 bp->rx_buffers = NULL;
1131 kfree(bp->tx_buffers);
1132 bp->tx_buffers = NULL;
1da177e4 1133 if (bp->rx_ring) {
9f38c636 1134 if (bp->flags & B44_FLAG_RX_RING_HACK) {
f225763a
MB		 1135 ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1136 DMA_TABLE_BYTES,
1137 DMA_BIDIRECTIONAL);
9f38c636
JL		 1138 kfree(bp->rx_ring);
1139 } else
f225763a
MB		 1140 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1141 bp->rx_ring, bp->rx_ring_dma,
1142 GFP_KERNEL);
1da177e4 1143 bp->rx_ring = NULL;
9f38c636 1144 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1da177e4
LT		 1145 }
1146 if (bp->tx_ring) {
9f38c636 1147 if (bp->flags & B44_FLAG_TX_RING_HACK) {
f225763a
MB		 1148 ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1149 DMA_TABLE_BYTES,
1150 DMA_TO_DEVICE);
9f38c636
JL		 1151 kfree(bp->tx_ring);
1152 } else
f225763a
MB		 1153 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1154 bp->tx_ring, bp->tx_ring_dma,
1155 GFP_KERNEL);
1da177e4 1156 bp->tx_ring = NULL;
9f38c636 1157 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1da177e4
LT		 1158 }
1159}
1160
1161/*
1162 * Must not be invoked with interrupt sources disabled and
1163 * the hardware shutdown down. Can sleep.
1164 */
753f4920 1165static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1da177e4
LT		 1166{
1167 int size;
1168
1169 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
753f4920 1170 bp->rx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1171 if (!bp->rx_buffers)
1172 goto out_err;
1da177e4
LT		 1173
1174 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
753f4920 1175 bp->tx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1176 if (!bp->tx_buffers)
1177 goto out_err;
1da177e4
LT		 1178
1179 size = DMA_TABLE_BYTES;
f225763a 1180 bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
9f38c636
JL		 1181 if (!bp->rx_ring) {
1182 /* Allocation may have failed due to pci_alloc_consistent
1183 insisting on use of GFP_DMA, which is more restrictive
1184 than necessary... */
1185 struct dma_desc *rx_ring;
1186 dma_addr_t rx_ring_dma;
1187
753f4920 1188 rx_ring = kzalloc(size, gfp);
874a6214 1189 if (!rx_ring)
9f38c636
JL		 1190 goto out_err;
1191
f225763a
MB		 1192 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1193 DMA_TABLE_BYTES,
1194 DMA_BIDIRECTIONAL);
9f38c636 1195
f225763a 1196 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
28b76796 1197 rx_ring_dma + size > DMA_BIT_MASK(30)) {
9f38c636
JL		 1198 kfree(rx_ring);
1199 goto out_err;
1200 }
1201
1202 bp->rx_ring = rx_ring;
1203 bp->rx_ring_dma = rx_ring_dma;
1204 bp->flags |= B44_FLAG_RX_RING_HACK;
1205 }
1da177e4 1206
f225763a 1207 bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
9f38c636 1208 if (!bp->tx_ring) {
f225763a 1209 /* Allocation may have failed due to ssb_dma_alloc_consistent
9f38c636
JL		 1210 insisting on use of GFP_DMA, which is more restrictive
1211 than necessary... */
1212 struct dma_desc *tx_ring;
1213 dma_addr_t tx_ring_dma;
1214
753f4920 1215 tx_ring = kzalloc(size, gfp);
874a6214 1216 if (!tx_ring)
9f38c636
JL		 1217 goto out_err;
1218
f225763a 1219 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
753f4920
MB		 1220 DMA_TABLE_BYTES,
1221 DMA_TO_DEVICE);
9f38c636 1222
f225763a 1223 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
28b76796 1224 tx_ring_dma + size > DMA_BIT_MASK(30)) {
9f38c636
JL		 1225 kfree(tx_ring);
1226 goto out_err;
1227 }
1228
1229 bp->tx_ring = tx_ring;
1230 bp->tx_ring_dma = tx_ring_dma;
1231 bp->flags |= B44_FLAG_TX_RING_HACK;
1232 }
1da177e4
LT		 1233
1234 return 0;
1235
1236out_err:
1237 b44_free_consistent(bp);
1238 return -ENOMEM;
1239}
1240
1241/* bp->lock is held. */
1242static void b44_clear_stats(struct b44 *bp)
1243{
1244 unsigned long reg;
1245
1246 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1247 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1248 br32(bp, reg);
1249 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1250 br32(bp, reg);
1251}
1252
1253/* bp->lock is held. */
fedb0eef 1254static void b44_chip_reset(struct b44 *bp, int reset_kind)
1da177e4 1255{
753f4920 1256 struct ssb_device *sdev = bp->sdev;
f8af11af 1257 bool was_enabled;
753f4920 1258
f8af11af
MB		 1259 was_enabled = ssb_device_is_enabled(bp->sdev);
1260
1261 ssb_device_enable(bp->sdev, 0);
1262 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1263
1264 if (was_enabled) {
1da177e4
LT		 1265 bw32(bp, B44_RCV_LAZY, 0);
1266 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
40ee8c76 1267 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1da177e4
LT		 1268 bw32(bp, B44_DMATX_CTRL, 0);
1269 bp->tx_prod = bp->tx_cons = 0;
1270 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1271 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1272 100, 0);
1273 }
1274 bw32(bp, B44_DMARX_CTRL, 0);
1275 bp->rx_prod = bp->rx_cons = 0;
f8af11af 1276 }
1da177e4
LT		 1277
1278 b44_clear_stats(bp);
1279
fedb0eef
MB		 1280 /*
1281 * Don't enable PHY if we are doing a partial reset
1282 * we are probably going to power down
1283 */
1284 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1285 return;
1286
753f4920
MB		 1287 switch (sdev->bus->bustype) {
1288 case SSB_BUSTYPE_SSB:
1289 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
39506a55
JL		 1290 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1291 B44_MDC_RATIO)
753f4920
MB		 1292 & MDIO_CTRL_MAXF_MASK)));
1293 break;
1294 case SSB_BUSTYPE_PCI:
753f4920
MB		 1295 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1296 (0x0d & MDIO_CTRL_MAXF_MASK)));
1297 break;
98a1e2a9
MB		 1298 case SSB_BUSTYPE_PCMCIA:
1299 case SSB_BUSTYPE_SDIO:
1300 WARN_ON(1); /* A device with this bus does not exist. */
1301 break;
753f4920
MB		 1302 }
1303
1da177e4
LT		 1304 br32(bp, B44_MDIO_CTRL);
1305
1306 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1307 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1308 br32(bp, B44_ENET_CTRL);
1309 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1310 } else {
1311 u32 val = br32(bp, B44_DEVCTRL);
1312
1313 if (val & DEVCTRL_EPR) {
1314 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1315 br32(bp, B44_DEVCTRL);
1316 udelay(100);
1317 }
1318 bp->flags |= B44_FLAG_INTERNAL_PHY;
1319 }
1320}
1321
1322/* bp->lock is held. */
1323static void b44_halt(struct b44 *bp)
1324{
1325 b44_disable_ints(bp);
fedb0eef
MB		 1326 /* reset PHY */
1327 b44_phy_reset(bp);
1328 /* power down PHY */
2fc96fff 1329 netdev_info(bp->dev, "powering down PHY\n");
fedb0eef
MB		 1330 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1331 /* now reset the chip, but without enabling the MAC&PHY
1332 * part of it. This has to be done _after_ we shut down the PHY */
1333 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1da177e4
LT		 1334}
1335
1336/* bp->lock is held. */
1337static void __b44_set_mac_addr(struct b44 *bp)
1338{
1339 bw32(bp, B44_CAM_CTRL, 0);
1340 if (!(bp->dev->flags & IFF_PROMISC)) {
1341 u32 val;
1342
1343 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1344 val = br32(bp, B44_CAM_CTRL);
1345 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1346 }
1347}
1348
1349static int b44_set_mac_addr(struct net_device *dev, void *p)
1350{
1351 struct b44 *bp = netdev_priv(dev);
1352 struct sockaddr *addr = p;
753f4920 1353 u32 val;
1da177e4
LT		 1354
1355 if (netif_running(dev))
1356 return -EBUSY;
1357
391fc09a
GZ		 1358 if (!is_valid_ether_addr(addr->sa_data))
1359 return -EINVAL;
1360
1da177e4
LT		 1361 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1362
1363 spin_lock_irq(&bp->lock);
753f4920
MB		 1364
1365 val = br32(bp, B44_RXCONFIG);
1366 if (!(val & RXCONFIG_CAM_ABSENT))
1367 __b44_set_mac_addr(bp);
1368
1da177e4
LT		 1369 spin_unlock_irq(&bp->lock);
1370
1371 return 0;
1372}
1373
1374/* Called at device open time to get the chip ready for
1375 * packet processing. Invoked with bp->lock held.
1376 */
1377static void __b44_set_rx_mode(struct net_device *);
5fc7d61a 1378static void b44_init_hw(struct b44 *bp, int reset_kind)
1da177e4
LT		 1379{
1380 u32 val;
1381
fedb0eef 1382 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5fc7d61a 1383 if (reset_kind == B44_FULL_RESET) {
00e8b3aa
GZ		 1384 b44_phy_reset(bp);
1385 b44_setup_phy(bp);
1386 }
1da177e4
LT		 1387
1388 /* Enable CRC32, set proper LED modes and power on PHY */
1389 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1390 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1391
1392 /* This sets the MAC address too. */
1393 __b44_set_rx_mode(bp->dev);
1394
1395 /* MTU + eth header + possible VLAN tag + struct rx_header */
1396 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1397 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1398
1399 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
5fc7d61a
MC		 1400 if (reset_kind == B44_PARTIAL_RESET) {
1401 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1402 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
5fc7d61a 1403 } else {
00e8b3aa
GZ		 1404 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1405 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1406 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1407 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
00e8b3aa 1408 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1da177e4 1409
00e8b3aa
GZ		 1410 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1411 bp->rx_prod = bp->rx_pending;
1da177e4 1412
00e8b3aa 1413 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
00e8b3aa 1414 }
1da177e4
LT		 1415
1416 val = br32(bp, B44_ENET_CTRL);
1417 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1418}
1419
1420static int b44_open(struct net_device *dev)
1421{
1422 struct b44 *bp = netdev_priv(dev);
1423 int err;
1424
753f4920 1425 err = b44_alloc_consistent(bp, GFP_KERNEL);
1da177e4 1426 if (err)
6c2f4267 1427 goto out;
1da177e4 1428
bea3348e
SH		 1429 napi_enable(&bp->napi);
1430
1da177e4 1431 b44_init_rings(bp);
5fc7d61a 1432 b44_init_hw(bp, B44_FULL_RESET);
1da177e4 1433
e254e9bf
JL		 1434 b44_check_phy(bp);
1435
1fb9df5d 1436 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
6c2f4267 1437 if (unlikely(err < 0)) {
bea3348e 1438 napi_disable(&bp->napi);
fedb0eef 1439 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
6c2f4267
FR		 1440 b44_free_rings(bp);
1441 b44_free_consistent(bp);
1442 goto out;
1443 }
1da177e4
LT		 1444
1445 init_timer(&bp->timer);
1446 bp->timer.expires = jiffies + HZ;
1447 bp->timer.data = (unsigned long) bp;
1448 bp->timer.function = b44_timer;
1449 add_timer(&bp->timer);
1450
1451 b44_enable_ints(bp);
d9e2d185 1452 netif_start_queue(dev);
6c2f4267 1453out:
1da177e4
LT		 1454 return err;
1455}
1456
1da177e4
LT		 1457#ifdef CONFIG_NET_POLL_CONTROLLER
1458/*
1459 * Polling receive - used by netconsole and other diagnostic tools
1460 * to allow network i/o with interrupts disabled.
1461 */
1462static void b44_poll_controller(struct net_device *dev)
1463{
1464 disable_irq(dev->irq);
7d12e780 1465 b44_interrupt(dev->irq, dev);
1da177e4
LT		 1466 enable_irq(dev->irq);
1467}
1468#endif
1469
725ad800
GZ		 1470static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1471{
1472 u32 i;
1473 u32 *pattern = (u32 *) pp;
1474
1475 for (i = 0; i < bytes; i += sizeof(u32)) {
1476 bw32(bp, B44_FILT_ADDR, table_offset + i);
1477 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1478 }
1479}
1480
1481static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1482{
1483 int magicsync = 6;
1484 int k, j, len = offset;
1485 int ethaddr_bytes = ETH_ALEN;
1486
1487 memset(ppattern + offset, 0xff, magicsync);
1488 for (j = 0; j < magicsync; j++)
1489 set_bit(len++, (unsigned long *) pmask);
1490
1491 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1492 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1493 ethaddr_bytes = ETH_ALEN;
1494 else
1495 ethaddr_bytes = B44_PATTERN_SIZE - len;
1496 if (ethaddr_bytes <=0)
1497 break;
1498 for (k = 0; k< ethaddr_bytes; k++) {
1499 ppattern[offset + magicsync +
1500 (j * ETH_ALEN) + k] = macaddr[k];
e0188829 1501 set_bit(len++, (unsigned long *) pmask);
725ad800
GZ		 1502 }
1503 }
1504 return len - 1;
1505}
1506
1507/* Setup magic packet patterns in the b44 WOL
1508 * pattern matching filter.
1509 */
1510static void b44_setup_pseudo_magicp(struct b44 *bp)
1511{
1512
1513 u32 val;
1514 int plen0, plen1, plen2;
1515 u8 *pwol_pattern;
1516 u8 pwol_mask[B44_PMASK_SIZE];
1517
dd00cc48 1518 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
725ad800 1519 if (!pwol_pattern) {
2fc96fff 1520 pr_err("Memory not available for WOL\n");
725ad800
GZ		 1521 return;
1522 }
1523
1524 /* Ipv4 magic packet pattern - pattern 0.*/
725ad800
GZ		 1525 memset(pwol_mask, 0, B44_PMASK_SIZE);
1526 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1527 B44_ETHIPV4UDP_HLEN);
1528
1529 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1530 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1531
1532 /* Raw ethernet II magic packet pattern - pattern 1 */
1533 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1534 memset(pwol_mask, 0, B44_PMASK_SIZE);
1535 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1536 ETH_HLEN);
1537
1538 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1539 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1540 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1541 B44_PMASK_BASE + B44_PMASK_SIZE);
1542
1543 /* Ipv6 magic packet pattern - pattern 2 */
1544 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1545 memset(pwol_mask, 0, B44_PMASK_SIZE);
1546 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1547 B44_ETHIPV6UDP_HLEN);
1548
1549 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1550 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1551 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1552 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1553
1554 kfree(pwol_pattern);
1555
1556 /* set these pattern's lengths: one less than each real length */
1557 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1558 bw32(bp, B44_WKUP_LEN, val);
1559
1560 /* enable wakeup pattern matching */
1561 val = br32(bp, B44_DEVCTRL);
1562 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1563
1564}
52cafd96 1565
753f4920
MB		 1566#ifdef CONFIG_B44_PCI
1567static void b44_setup_wol_pci(struct b44 *bp)
1568{
1569 u16 val;
1570
1571 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1572 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1573 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1574 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1575 }
1576}
1577#else
1578static inline void b44_setup_wol_pci(struct b44 *bp) { }
1579#endif /* CONFIG_B44_PCI */
1580
52cafd96
GZ		 1581static void b44_setup_wol(struct b44 *bp)
1582{
1583 u32 val;
52cafd96
GZ		 1584
1585 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1586
1587 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1588
1589 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1590
1591 val = bp->dev->dev_addr[2] << 24 |
1592 bp->dev->dev_addr[3] << 16 |
1593 bp->dev->dev_addr[4] << 8 |
1594 bp->dev->dev_addr[5];
1595 bw32(bp, B44_ADDR_LO, val);
1596
1597 val = bp->dev->dev_addr[0] << 8 |
1598 bp->dev->dev_addr[1];
1599 bw32(bp, B44_ADDR_HI, val);
1600
1601 val = br32(bp, B44_DEVCTRL);
1602 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1603
725ad800
GZ		 1604 } else {
1605 b44_setup_pseudo_magicp(bp);
1606 }
753f4920 1607 b44_setup_wol_pci(bp);
52cafd96
GZ		 1608}
1609
1da177e4
LT		 1610static int b44_close(struct net_device *dev)
1611{
1612 struct b44 *bp = netdev_priv(dev);
1613
1614 netif_stop_queue(dev);
1615
bea3348e 1616 napi_disable(&bp->napi);
ba5eec9c 1617
1da177e4
LT		 1618 del_timer_sync(&bp->timer);
1619
1620 spin_lock_irq(&bp->lock);
1621
1da177e4
LT		 1622 b44_halt(bp);
1623 b44_free_rings(bp);
c35ca399 1624 netif_carrier_off(dev);
1da177e4
LT		 1625
1626 spin_unlock_irq(&bp->lock);
1627
1628 free_irq(dev->irq, dev);
1629
52cafd96 1630 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 1631 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 1632 b44_setup_wol(bp);
1633 }
1634
1da177e4
LT		 1635 b44_free_consistent(bp);
1636
1637 return 0;
1638}
1639
1640static struct net_device_stats *b44_get_stats(struct net_device *dev)
1641{
1642 struct b44 *bp = netdev_priv(dev);
553e2335 1643 struct net_device_stats *nstat = &dev->stats;
1da177e4
LT		 1644 struct b44_hw_stats *hwstat = &bp->hw_stats;
1645
1646 /* Convert HW stats into netdevice stats. */
1647 nstat->rx_packets = hwstat->rx_pkts;
1648 nstat->tx_packets = hwstat->tx_pkts;
1649 nstat->rx_bytes = hwstat->rx_octets;
1650 nstat->tx_bytes = hwstat->tx_octets;
1651 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1652 hwstat->tx_oversize_pkts +
1653 hwstat->tx_underruns +
1654 hwstat->tx_excessive_cols +
1655 hwstat->tx_late_cols);
1656 nstat->multicast = hwstat->tx_multicast_pkts;
1657 nstat->collisions = hwstat->tx_total_cols;
1658
1659 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1660 hwstat->rx_undersize);
1661 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1662 nstat->rx_frame_errors = hwstat->rx_align_errs;
1663 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1664 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1665 hwstat->rx_oversize_pkts +
1666 hwstat->rx_missed_pkts +
1667 hwstat->rx_crc_align_errs +
1668 hwstat->rx_undersize +
1669 hwstat->rx_crc_errs +
1670 hwstat->rx_align_errs +
1671 hwstat->rx_symbol_errs);
1672
1673 nstat->tx_aborted_errors = hwstat->tx_underruns;
1674#if 0
1675 /* Carrier lost counter seems to be broken for some devices */
1676 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1677#endif
1678
1679 return nstat;
1680}
1681
1682static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1683{
1684 struct dev_mc_list *mclist;
1685 int i, num_ents;
1686
4cd24eaf 1687 num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
0ddf477b
JP		 1688 i = 0;
1689 netdev_for_each_mc_addr(mclist, dev) {
1690 if (i == num_ents)
1691 break;
1692 __b44_cam_write(bp, mclist->dmi_addr, i++ + 1);
1da177e4
LT		 1693 }
1694 return i+1;
1695}
1696
1697static void __b44_set_rx_mode(struct net_device *dev)
1698{
1699 struct b44 *bp = netdev_priv(dev);
1700 u32 val;
1da177e4
LT		 1701
1702 val = br32(bp, B44_RXCONFIG);
1703 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
753f4920 1704 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1da177e4
LT		 1705 val |= RXCONFIG_PROMISC;
1706 bw32(bp, B44_RXCONFIG, val);
1707 } else {
874a6214 1708 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
cda22aa9 1709 int i = 1;
874a6214 1710
1da177e4
LT		 1711 __b44_set_mac_addr(bp);
1712
2f614fe0 1713 if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf 1714 (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
1da177e4
LT		 1715 val |= RXCONFIG_ALLMULTI;
1716 else
874a6214 1717 i = __b44_load_mcast(bp, dev);
10badc21 1718
2f614fe0 1719 for (; i < 64; i++)
10badc21 1720 __b44_cam_write(bp, zero, i);
2f614fe0 1721
1da177e4
LT		 1722 bw32(bp, B44_RXCONFIG, val);
1723 val = br32(bp, B44_CAM_CTRL);
1724 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1725 }
1726}
1727
1728static void b44_set_rx_mode(struct net_device *dev)
1729{
1730 struct b44 *bp = netdev_priv(dev);
1731
1732 spin_lock_irq(&bp->lock);
1733 __b44_set_rx_mode(dev);
1734 spin_unlock_irq(&bp->lock);
1735}
1736
1737static u32 b44_get_msglevel(struct net_device *dev)
1738{
1739 struct b44 *bp = netdev_priv(dev);
1740 return bp->msg_enable;
1741}
1742
1743static void b44_set_msglevel(struct net_device *dev, u32 value)
1744{
1745 struct b44 *bp = netdev_priv(dev);
1746 bp->msg_enable = value;
1747}
1748
1749static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1750{
1751 struct b44 *bp = netdev_priv(dev);
753f4920 1752 struct ssb_bus *bus = bp->sdev->bus;
1da177e4 1753
27e09551 1754 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1755 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
753f4920
MB		 1756 switch (bus->bustype) {
1757 case SSB_BUSTYPE_PCI:
27e09551 1758 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
753f4920 1759 break;
753f4920 1760 case SSB_BUSTYPE_SSB:
27e09551 1761 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
753f4920 1762 break;
98a1e2a9
MB		 1763 case SSB_BUSTYPE_PCMCIA:
1764 case SSB_BUSTYPE_SDIO:
1765 WARN_ON(1); /* A device with this bus does not exist. */
1766 break;
753f4920 1767 }
1da177e4
LT		 1768}
1769
1770static int b44_nway_reset(struct net_device *dev)
1771{
1772 struct b44 *bp = netdev_priv(dev);
1773 u32 bmcr;
1774 int r;
1775
1776 spin_lock_irq(&bp->lock);
1777 b44_readphy(bp, MII_BMCR, &bmcr);
1778 b44_readphy(bp, MII_BMCR, &bmcr);
1779 r = -EINVAL;
1780 if (bmcr & BMCR_ANENABLE) {
1781 b44_writephy(bp, MII_BMCR,
1782 bmcr | BMCR_ANRESTART);
1783 r = 0;
1784 }
1785 spin_unlock_irq(&bp->lock);
1786
1787 return r;
1788}
1789
1790static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1791{
1792 struct b44 *bp = netdev_priv(dev);
1793
1da177e4
LT		 1794 cmd->supported = (SUPPORTED_Autoneg);
1795 cmd->supported |= (SUPPORTED_100baseT_Half |
1796 SUPPORTED_100baseT_Full |
1797 SUPPORTED_10baseT_Half |
1798 SUPPORTED_10baseT_Full |
1799 SUPPORTED_MII);
1800
1801 cmd->advertising = 0;
1802 if (bp->flags & B44_FLAG_ADV_10HALF)
adf6e000 1803 cmd->advertising |= ADVERTISED_10baseT_Half;
1da177e4 1804 if (bp->flags & B44_FLAG_ADV_10FULL)
adf6e000 1805 cmd->advertising |= ADVERTISED_10baseT_Full;
1da177e4 1806 if (bp->flags & B44_FLAG_ADV_100HALF)
adf6e000 1807 cmd->advertising |= ADVERTISED_100baseT_Half;
1da177e4 1808 if (bp->flags & B44_FLAG_ADV_100FULL)
adf6e000
MW		 1809 cmd->advertising |= ADVERTISED_100baseT_Full;
1810 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1da177e4
LT		 1811 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1812 SPEED_100 : SPEED_10;
1813 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1814 DUPLEX_FULL : DUPLEX_HALF;
1815 cmd->port = 0;
1816 cmd->phy_address = bp->phy_addr;
1817 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1818 XCVR_INTERNAL : XCVR_EXTERNAL;
1819 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1820 AUTONEG_DISABLE : AUTONEG_ENABLE;
47b9c3b1
GZ		 1821 if (cmd->autoneg == AUTONEG_ENABLE)
1822 cmd->advertising |= ADVERTISED_Autoneg;
1823 if (!netif_running(dev)){
1824 cmd->speed = 0;
1825 cmd->duplex = 0xff;
1826 }
1da177e4
LT		 1827 cmd->maxtxpkt = 0;
1828 cmd->maxrxpkt = 0;
1829 return 0;
1830}
1831
1832static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1833{
1834 struct b44 *bp = netdev_priv(dev);
1835
1da177e4
LT		 1836 /* We do not support gigabit. */
1837 if (cmd->autoneg == AUTONEG_ENABLE) {
1838 if (cmd->advertising &
1839 (ADVERTISED_1000baseT_Half |
1840 ADVERTISED_1000baseT_Full))
1841 return -EINVAL;
1842 } else if ((cmd->speed != SPEED_100 &&
1843 cmd->speed != SPEED_10) ||
1844 (cmd->duplex != DUPLEX_HALF &&
1845 cmd->duplex != DUPLEX_FULL)) {
1846 return -EINVAL;
1847 }
1848
1849 spin_lock_irq(&bp->lock);
1850
1851 if (cmd->autoneg == AUTONEG_ENABLE) {
47b9c3b1
GZ		 1852 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1853 B44_FLAG_100_BASE_T |
1854 B44_FLAG_FULL_DUPLEX |
1855 B44_FLAG_ADV_10HALF |
1da177e4
LT		 1856 B44_FLAG_ADV_10FULL |
1857 B44_FLAG_ADV_100HALF |
1858 B44_FLAG_ADV_100FULL);
47b9c3b1
GZ		 1859 if (cmd->advertising == 0) {
1860 bp->flags |= (B44_FLAG_ADV_10HALF |
1861 B44_FLAG_ADV_10FULL |
1862 B44_FLAG_ADV_100HALF |
1863 B44_FLAG_ADV_100FULL);
1864 } else {
1865 if (cmd->advertising & ADVERTISED_10baseT_Half)
1866 bp->flags |= B44_FLAG_ADV_10HALF;
1867 if (cmd->advertising & ADVERTISED_10baseT_Full)
1868 bp->flags |= B44_FLAG_ADV_10FULL;
1869 if (cmd->advertising & ADVERTISED_100baseT_Half)
1870 bp->flags |= B44_FLAG_ADV_100HALF;
1871 if (cmd->advertising & ADVERTISED_100baseT_Full)
1872 bp->flags |= B44_FLAG_ADV_100FULL;
1873 }
1da177e4
LT		 1874 } else {
1875 bp->flags |= B44_FLAG_FORCE_LINK;
47b9c3b1 1876 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1da177e4
LT		 1877 if (cmd->speed == SPEED_100)
1878 bp->flags |= B44_FLAG_100_BASE_T;
1879 if (cmd->duplex == DUPLEX_FULL)
1880 bp->flags |= B44_FLAG_FULL_DUPLEX;
1881 }
1882
47b9c3b1
GZ		 1883 if (netif_running(dev))
1884 b44_setup_phy(bp);
1da177e4
LT		 1885
1886 spin_unlock_irq(&bp->lock);
1887
1888 return 0;
1889}
1890
1891static void b44_get_ringparam(struct net_device *dev,
1892 struct ethtool_ringparam *ering)
1893{
1894 struct b44 *bp = netdev_priv(dev);
1895
1896 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1897 ering->rx_pending = bp->rx_pending;
1898
1899 /* XXX ethtool lacks a tx_max_pending, oops... */
1900}
1901
1902static int b44_set_ringparam(struct net_device *dev,
1903 struct ethtool_ringparam *ering)
1904{
1905 struct b44 *bp = netdev_priv(dev);
1906
1907 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1908 (ering->rx_mini_pending != 0) ||
1909 (ering->rx_jumbo_pending != 0) ||
1910 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1911 return -EINVAL;
1912
1913 spin_lock_irq(&bp->lock);
1914
1915 bp->rx_pending = ering->rx_pending;
1916 bp->tx_pending = ering->tx_pending;
1917
1918 b44_halt(bp);
1919 b44_init_rings(bp);
5fc7d61a 1920 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1921 netif_wake_queue(bp->dev);
1922 spin_unlock_irq(&bp->lock);
1923
1924 b44_enable_ints(bp);
10badc21 1925
1da177e4
LT		 1926 return 0;
1927}
1928
1929static void b44_get_pauseparam(struct net_device *dev,
1930 struct ethtool_pauseparam *epause)
1931{
1932 struct b44 *bp = netdev_priv(dev);
1933
1934 epause->autoneg =
1935 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1936 epause->rx_pause =
1937 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1938 epause->tx_pause =
1939 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1940}
1941
1942static int b44_set_pauseparam(struct net_device *dev,
1943 struct ethtool_pauseparam *epause)
1944{
1945 struct b44 *bp = netdev_priv(dev);
1946
1947 spin_lock_irq(&bp->lock);
1948 if (epause->autoneg)
1949 bp->flags |= B44_FLAG_PAUSE_AUTO;
1950 else
1951 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1952 if (epause->rx_pause)
1953 bp->flags |= B44_FLAG_RX_PAUSE;
1954 else
1955 bp->flags &= ~B44_FLAG_RX_PAUSE;
1956 if (epause->tx_pause)
1957 bp->flags |= B44_FLAG_TX_PAUSE;
1958 else
1959 bp->flags &= ~B44_FLAG_TX_PAUSE;
1960 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1961 b44_halt(bp);
1962 b44_init_rings(bp);
5fc7d61a 1963 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1964 } else {
1965 __b44_set_flow_ctrl(bp, bp->flags);
1966 }
1967 spin_unlock_irq(&bp->lock);
1968
1969 b44_enable_ints(bp);
10badc21 1970
1da177e4
LT		 1971 return 0;
1972}
1973
3353930d
FR		 1974static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1975{
1976 switch(stringset) {
1977 case ETH_SS_STATS:
1978 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1979 break;
1980 }
1981}
1982
b9f2c044 1983static int b44_get_sset_count(struct net_device *dev, int sset)
3353930d 1984{
b9f2c044
JG		 1985 switch (sset) {
1986 case ETH_SS_STATS:
1987 return ARRAY_SIZE(b44_gstrings);
1988 default:
1989 return -EOPNOTSUPP;
1990 }
3353930d
FR		 1991}
1992
1993static void b44_get_ethtool_stats(struct net_device *dev,
1994 struct ethtool_stats *stats, u64 *data)
1995{
1996 struct b44 *bp = netdev_priv(dev);
1997 u32 *val = &bp->hw_stats.tx_good_octets;
1998 u32 i;
1999
2000 spin_lock_irq(&bp->lock);
2001
2002 b44_stats_update(bp);
2003
2004 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2005 *data++ = *val++;
2006
2007 spin_unlock_irq(&bp->lock);
2008}
2009
52cafd96
GZ		 2010static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2011{
2012 struct b44 *bp = netdev_priv(dev);
2013
2014 wol->supported = WAKE_MAGIC;
2015 if (bp->flags & B44_FLAG_WOL_ENABLE)
2016 wol->wolopts = WAKE_MAGIC;
2017 else
2018 wol->wolopts = 0;
2019 memset(&wol->sopass, 0, sizeof(wol->sopass));
2020}
2021
2022static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2023{
2024 struct b44 *bp = netdev_priv(dev);
2025
2026 spin_lock_irq(&bp->lock);
2027 if (wol->wolopts & WAKE_MAGIC)
2028 bp->flags |= B44_FLAG_WOL_ENABLE;
2029 else
2030 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2031 spin_unlock_irq(&bp->lock);
2032
2033 return 0;
2034}
2035
7282d491 2036static const struct ethtool_ops b44_ethtool_ops = {
1da177e4
LT		 2037 .get_drvinfo = b44_get_drvinfo,
2038 .get_settings = b44_get_settings,
2039 .set_settings = b44_set_settings,
2040 .nway_reset = b44_nway_reset,
2041 .get_link = ethtool_op_get_link,
52cafd96
GZ		 2042 .get_wol = b44_get_wol,
2043 .set_wol = b44_set_wol,
1da177e4
LT		 2044 .get_ringparam = b44_get_ringparam,
2045 .set_ringparam = b44_set_ringparam,
2046 .get_pauseparam = b44_get_pauseparam,
2047 .set_pauseparam = b44_set_pauseparam,
2048 .get_msglevel = b44_get_msglevel,
2049 .set_msglevel = b44_set_msglevel,
3353930d 2050 .get_strings = b44_get_strings,
b9f2c044 2051 .get_sset_count = b44_get_sset_count,
3353930d 2052 .get_ethtool_stats = b44_get_ethtool_stats,
1da177e4
LT		 2053};
2054
2055static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2056{
2057 struct mii_ioctl_data *data = if_mii(ifr);
2058 struct b44 *bp = netdev_priv(dev);
3410572d
FR		 2059 int err = -EINVAL;
2060
2061 if (!netif_running(dev))
2062 goto out;
1da177e4
LT		 2063
2064 spin_lock_irq(&bp->lock);
2065 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2066 spin_unlock_irq(&bp->lock);
3410572d 2067out:
1da177e4
LT		 2068 return err;
2069}
2070
1da177e4
LT		 2071static int __devinit b44_get_invariants(struct b44 *bp)
2072{
753f4920
MB		 2073 struct ssb_device *sdev = bp->sdev;
2074 int err = 0;
2075 u8 *addr;
1da177e4 2076
753f4920 2077 bp->dma_offset = ssb_dma_translation(sdev);
1da177e4 2078
753f4920
MB		 2079 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2080 instance > 1) {
458414b2
LF		 2081 addr = sdev->bus->sprom.et1mac;
2082 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
753f4920 2083 } else {
458414b2
LF		 2084 addr = sdev->bus->sprom.et0mac;
2085 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
753f4920 2086 }
5ea79631
MB		 2087 /* Some ROMs have buggy PHY addresses with the high
2088 * bits set (sign extension?). Truncate them to a
2089 * valid PHY address. */
2090 bp->phy_addr &= 0x1F;
2091
753f4920 2092 memcpy(bp->dev->dev_addr, addr, 6);
391fc09a
GZ		 2093
2094 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2fc96fff 2095 pr_err("Invalid MAC address found in EEPROM\n");
391fc09a
GZ		 2096 return -EINVAL;
2097 }
2098
2160de53 2099 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1da177e4 2100
1da177e4
LT		 2101 bp->imask = IMASK_DEF;
2102
10badc21 2103 /* XXX - really required?
1da177e4 2104 bp->flags |= B44_FLAG_BUGGY_TXPTR;
753f4920 2105 */
52cafd96 2106
753f4920
MB		 2107 if (bp->sdev->id.revision >= 7)
2108 bp->flags |= B44_FLAG_B0_ANDLATER;
52cafd96 2109
1da177e4
LT		 2110 return err;
2111}
2112
403413e5
SH		 2113static const struct net_device_ops b44_netdev_ops = {
2114 .ndo_open = b44_open,
2115 .ndo_stop = b44_close,
2116 .ndo_start_xmit = b44_start_xmit,
2117 .ndo_get_stats = b44_get_stats,
2118 .ndo_set_multicast_list = b44_set_rx_mode,
2119 .ndo_set_mac_address = b44_set_mac_addr,
2120 .ndo_validate_addr = eth_validate_addr,
2121 .ndo_do_ioctl = b44_ioctl,
2122 .ndo_tx_timeout = b44_tx_timeout,
2123 .ndo_change_mtu = b44_change_mtu,
2124#ifdef CONFIG_NET_POLL_CONTROLLER
2125 .ndo_poll_controller = b44_poll_controller,
2126#endif
2127};
2128
753f4920
MB		 2129static int __devinit b44_init_one(struct ssb_device *sdev,
2130 const struct ssb_device_id *ent)
1da177e4
LT		 2131{
2132 static int b44_version_printed = 0;
1da177e4
LT		 2133 struct net_device *dev;
2134 struct b44 *bp;
0795af57 2135 int err;
1da177e4 2136
753f4920
MB		 2137 instance++;
2138
1da177e4 2139 if (b44_version_printed++ == 0)
2fc96fff 2140 pr_info("%s", version);
1da177e4 2141
1da177e4
LT		 2142
2143 dev = alloc_etherdev(sizeof(*bp));
2144 if (!dev) {
2fc96fff 2145 dev_err(sdev->dev, "Etherdev alloc failed, aborting\n");
1da177e4 2146 err = -ENOMEM;
753f4920 2147 goto out;
1da177e4
LT		 2148 }
2149
753f4920 2150 SET_NETDEV_DEV(dev, sdev->dev);
1da177e4
LT		 2151
2152 /* No interesting netdevice features in this card... */
2153 dev->features |= 0;
2154
2155 bp = netdev_priv(dev);
753f4920 2156 bp->sdev = sdev;
1da177e4 2157 bp->dev = dev;
a58c891a 2158 bp->force_copybreak = 0;
874a6214
FR		 2159
2160 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1da177e4
LT		 2161
2162 spin_lock_init(&bp->lock);
2163
1da177e4
LT		 2164 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2165 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2166
403413e5 2167 dev->netdev_ops = &b44_netdev_ops;
bea3348e 2168 netif_napi_add(dev, &bp->napi, b44_poll, 64);
1da177e4 2169 dev->watchdog_timeo = B44_TX_TIMEOUT;
753f4920 2170 dev->irq = sdev->irq;
1da177e4
LT		 2171 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2172
c35ca399
SH		 2173 netif_carrier_off(dev);
2174
753f4920
MB		 2175 err = ssb_bus_powerup(sdev->bus, 0);
2176 if (err) {
2177 dev_err(sdev->dev,
2178 "Failed to powerup the bus\n");
2179 goto err_out_free_dev;
2180 }
28b76796 2181 err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
753f4920
MB		 2182 if (err) {
2183 dev_err(sdev->dev,
2fc96fff 2184 "Required 30BIT DMA mask unsupported by the system\n");
753f4920
MB		 2185 goto err_out_powerdown;
2186 }
1da177e4
LT		 2187 err = b44_get_invariants(bp);
2188 if (err) {
753f4920 2189 dev_err(sdev->dev,
2fc96fff 2190 "Problem fetching invariants of chip, aborting\n");
753f4920 2191 goto err_out_powerdown;
1da177e4
LT		 2192 }
2193
2194 bp->mii_if.dev = dev;
2195 bp->mii_if.mdio_read = b44_mii_read;
2196 bp->mii_if.mdio_write = b44_mii_write;
2197 bp->mii_if.phy_id = bp->phy_addr;
2198 bp->mii_if.phy_id_mask = 0x1f;
2199 bp->mii_if.reg_num_mask = 0x1f;
2200
2201 /* By default, advertise all speed/duplex settings. */
2202 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2203 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2204
2205 /* By default, auto-negotiate PAUSE. */
2206 bp->flags |= B44_FLAG_PAUSE_AUTO;
2207
2208 err = register_netdev(dev);
2209 if (err) {
2fc96fff 2210 dev_err(sdev->dev, "Cannot register net device, aborting\n");
753f4920 2211 goto err_out_powerdown;
1da177e4
LT		 2212 }
2213
753f4920 2214 ssb_set_drvdata(sdev, dev);
1da177e4 2215
10badc21 2216 /* Chip reset provides power to the b44 MAC & PCI cores, which
5c513129 2217 * is necessary for MAC register access.
10badc21 2218 */
fedb0eef 2219 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5c513129 2220
8850dce1
HM		 2221 /* do a phy reset to test if there is an active phy */
2222 if (b44_phy_reset(bp) < 0)
2223 bp->phy_addr = B44_PHY_ADDR_NO_PHY;
2224
2fc96fff
JP		 2225 netdev_info(dev, "Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2226 dev->dev_addr);
1da177e4
LT		 2227
2228 return 0;
2229
753f4920
MB		 2230err_out_powerdown:
2231 ssb_bus_may_powerdown(sdev->bus);
1da177e4
LT		 2232
2233err_out_free_dev:
2234 free_netdev(dev);
2235
753f4920 2236out:
1da177e4
LT		 2237 return err;
2238}
2239
753f4920 2240static void __devexit b44_remove_one(struct ssb_device *sdev)
1da177e4 2241{
753f4920 2242 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2243
874a6214 2244 unregister_netdev(dev);
e92aa634 2245 ssb_device_disable(sdev, 0);
753f4920 2246 ssb_bus_may_powerdown(sdev->bus);
874a6214 2247 free_netdev(dev);
fedb0eef 2248 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
753f4920 2249 ssb_set_drvdata(sdev, NULL);
1da177e4
LT		 2250}
2251
753f4920 2252static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
1da177e4 2253{
753f4920 2254 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4
LT		 2255 struct b44 *bp = netdev_priv(dev);
2256
753f4920
MB		 2257 if (!netif_running(dev))
2258 return 0;
1da177e4
LT		 2259
2260 del_timer_sync(&bp->timer);
2261
10badc21 2262 spin_lock_irq(&bp->lock);
1da177e4
LT		 2263
2264 b44_halt(bp);
10badc21 2265 netif_carrier_off(bp->dev);
1da177e4
LT		 2266 netif_device_detach(bp->dev);
2267 b44_free_rings(bp);
2268
2269 spin_unlock_irq(&bp->lock);
46e17853
PM		 2270
2271 free_irq(dev->irq, dev);
52cafd96 2272 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 2273 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 2274 b44_setup_wol(bp);
2275 }
753f4920 2276
fedb0eef 2277 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
1da177e4
LT		 2278 return 0;
2279}
2280
753f4920 2281static int b44_resume(struct ssb_device *sdev)
1da177e4 2282{
753f4920 2283 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2284 struct b44 *bp = netdev_priv(dev);
90afd0e5 2285 int rc = 0;
1da177e4 2286
753f4920 2287 rc = ssb_bus_powerup(sdev->bus, 0);
90afd0e5 2288 if (rc) {
753f4920
MB		 2289 dev_err(sdev->dev,
2290 "Failed to powerup the bus\n");
90afd0e5
DM		 2291 return rc;
2292 }
2293
1da177e4
LT		 2294 if (!netif_running(dev))
2295 return 0;
2296
90afd0e5
DM		 2297 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2298 if (rc) {
2fc96fff 2299 netdev_err(dev, "request_irq failed\n");
90afd0e5
DM		 2300 return rc;
2301 }
46e17853 2302
1da177e4
LT		 2303 spin_lock_irq(&bp->lock);
2304
2305 b44_init_rings(bp);
5fc7d61a 2306 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 2307 netif_device_attach(bp->dev);
2308 spin_unlock_irq(&bp->lock);
2309
1da177e4 2310 b44_enable_ints(bp);
d9e2d185 2311 netif_wake_queue(dev);
a72a8179
SH		 2312
2313 mod_timer(&bp->timer, jiffies + 1);
2314
1da177e4
LT		 2315 return 0;
2316}
2317
753f4920 2318static struct ssb_driver b44_ssb_driver = {
1da177e4 2319 .name = DRV_MODULE_NAME,
753f4920 2320 .id_table = b44_ssb_tbl,
1da177e4
LT		 2321 .probe = b44_init_one,
2322 .remove = __devexit_p(b44_remove_one),
753f4920
MB		 2323 .suspend = b44_suspend,
2324 .resume = b44_resume,
1da177e4
LT		 2325};
2326
753f4920
MB		 2327static inline int b44_pci_init(void)
2328{
2329 int err = 0;
2330#ifdef CONFIG_B44_PCI
2331 err = ssb_pcihost_register(&b44_pci_driver);
2332#endif
2333 return err;
2334}
2335
2336static inline void b44_pci_exit(void)
2337{
2338#ifdef CONFIG_B44_PCI
2339 ssb_pcihost_unregister(&b44_pci_driver);
2340#endif
2341}
2342
1da177e4
LT		 2343static int __init b44_init(void)
2344{
9f38c636 2345 unsigned int dma_desc_align_size = dma_get_cache_alignment();
753f4920 2346 int err;
9f38c636
JL		 2347
2348 /* Setup paramaters for syncing RX/TX DMA descriptors */
2349 dma_desc_align_mask = ~(dma_desc_align_size - 1);
22d4d771 2350 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
9f38c636 2351
753f4920
MB		 2352 err = b44_pci_init();
2353 if (err)
2354 return err;
2355 err = ssb_driver_register(&b44_ssb_driver);
2356 if (err)
2357 b44_pci_exit();
2358 return err;
1da177e4
LT		 2359}
2360
2361static void __exit b44_cleanup(void)
2362{
753f4920
MB		 2363 ssb_driver_unregister(&b44_ssb_driver);
2364 b44_pci_exit();
1da177e4
LT		 2365}
2366
2367module_init(b44_init);
2368module_exit(b44_cleanup);
2369
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