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Merge commit 'v2.6.36-rc1' into HEAD
[net-next-2.6.git] / drivers / net / b44.c
CommitLineData
753f4920 1/* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
1da177e4
LT		 2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
753f4920
MB		 4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
8056bfaf 7 * Copyright (C) 2006 Broadcom Corporation.
753f4920 8 * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
1da177e4
LT		 9 *
10 * Distribute under GPL.
11 */
12
2fc96fff
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
1da177e4
LT		 15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/types.h>
19#include <linux/netdevice.h>
20#include <linux/ethtool.h>
21#include <linux/mii.h>
22#include <linux/if_ether.h>
72f4861e 23#include <linux/if_vlan.h>
1da177e4
LT		 24#include <linux/etherdevice.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/init.h>
89358f90 28#include <linux/dma-mapping.h>
753f4920 29#include <linux/ssb/ssb.h>
5a0e3ad6 30#include <linux/slab.h>
1da177e4
LT		 31
32#include <asm/uaccess.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35
753f4920 36
1da177e4
LT		 37#include "b44.h"
38
39#define DRV_MODULE_NAME "b44"
753f4920 40#define DRV_MODULE_VERSION "2.0"
1da177e4
LT		 41
42#define B44_DEF_MSG_ENABLE \
43 (NETIF_MSG_DRV | \
44 NETIF_MSG_PROBE | \
45 NETIF_MSG_LINK | \
46 NETIF_MSG_TIMER | \
47 NETIF_MSG_IFDOWN | \
48 NETIF_MSG_IFUP | \
49 NETIF_MSG_RX_ERR | \
50 NETIF_MSG_TX_ERR)
51
52/* length of time before we decide the hardware is borked,
53 * and dev->tx_timeout() should be called to fix the problem
54 */
55#define B44_TX_TIMEOUT (5 * HZ)
56
57/* hardware minimum and maximum for a single frame's data payload */
58#define B44_MIN_MTU 60
59#define B44_MAX_MTU 1500
60
61#define B44_RX_RING_SIZE 512
62#define B44_DEF_RX_RING_PENDING 200
63#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
64 B44_RX_RING_SIZE)
65#define B44_TX_RING_SIZE 512
66#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
67#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
68 B44_TX_RING_SIZE)
1da177e4
LT		 69
70#define TX_RING_GAP(BP) \
71 (B44_TX_RING_SIZE - (BP)->tx_pending)
72#define TX_BUFFS_AVAIL(BP) \
73 (((BP)->tx_cons <= (BP)->tx_prod) ? \
74 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
75 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
76#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
77
4ca85795
FF		 78#define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
79#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
1da177e4
LT		 80
81/* minimum number of free TX descriptors required to wake up TX process */
82#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
83
725ad800
GZ		 84/* b44 internal pattern match filter info */
85#define B44_PATTERN_BASE 0x400
86#define B44_PATTERN_SIZE 0x80
87#define B44_PMASK_BASE 0x600
88#define B44_PMASK_SIZE 0x10
89#define B44_MAX_PATTERNS 16
90#define B44_ETHIPV6UDP_HLEN 62
91#define B44_ETHIPV4UDP_HLEN 42
92
1da177e4 93static char version[] __devinitdata =
753f4920 94 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
1da177e4 95
753f4920
MB		 96MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
97MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
1da177e4
LT		 98MODULE_LICENSE("GPL");
99MODULE_VERSION(DRV_MODULE_VERSION);
100
101static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
102module_param(b44_debug, int, 0);
103MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
104
1da177e4 105
753f4920 106#ifdef CONFIG_B44_PCI
a3aa1884 107static DEFINE_PCI_DEVICE_TABLE(b44_pci_tbl) = {
753f4920
MB		 108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
109 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
110 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
111 { 0 } /* terminate list with empty entry */
112};
1da177e4
LT		 113MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
114
753f4920
MB		 115static struct pci_driver b44_pci_driver = {
116 .name = DRV_MODULE_NAME,
117 .id_table = b44_pci_tbl,
118};
119#endif /* CONFIG_B44_PCI */
120
121static const struct ssb_device_id b44_ssb_tbl[] = {
122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
123 SSB_DEVTABLE_END
124};
125MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
126
1da177e4
LT		 127static void b44_halt(struct b44 *);
128static void b44_init_rings(struct b44 *);
5fc7d61a
MC		 129
130#define B44_FULL_RESET 1
131#define B44_FULL_RESET_SKIP_PHY 2
132#define B44_PARTIAL_RESET 3
fedb0eef
MB		 133#define B44_CHIP_RESET_FULL 4
134#define B44_CHIP_RESET_PARTIAL 5
5fc7d61a 135
00e8b3aa 136static void b44_init_hw(struct b44 *, int);
1da177e4 137
9f38c636 138static int dma_desc_sync_size;
753f4920 139static int instance;
9f38c636 140
3353930d
FR		 141static const char b44_gstrings[][ETH_GSTRING_LEN] = {
142#define _B44(x...) # x,
143B44_STAT_REG_DECLARE
144#undef _B44
145};
146
753f4920
MB		 147static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
148 dma_addr_t dma_base,
149 unsigned long offset,
150 enum dma_data_direction dir)
9f38c636 151{
39a6f4bc
FT		 152 dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
153 dma_desc_sync_size, dir);
9f38c636
JL		 154}
155
753f4920
MB		 156static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157 dma_addr_t dma_base,
158 unsigned long offset,
159 enum dma_data_direction dir)
9f38c636 160{
39a6f4bc
FT		 161 dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
162 dma_desc_sync_size, dir);
9f38c636
JL		 163}
164
1da177e4
LT		 165static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
166{
753f4920 167 return ssb_read32(bp->sdev, reg);
1da177e4
LT		 168}
169
10badc21 170static inline void bw32(const struct b44 *bp,
1da177e4
LT		 171 unsigned long reg, unsigned long val)
172{
753f4920 173 ssb_write32(bp->sdev, reg, val);
1da177e4
LT		 174}
175
176static int b44_wait_bit(struct b44 *bp, unsigned long reg,
177 u32 bit, unsigned long timeout, const int clear)
178{
179 unsigned long i;
180
181 for (i = 0; i < timeout; i++) {
182 u32 val = br32(bp, reg);
183
184 if (clear && !(val & bit))
185 break;
186 if (!clear && (val & bit))
187 break;
188 udelay(10);
189 }
190 if (i == timeout) {
f6ca057f 191 if (net_ratelimit())
2fc96fff
JP		 192 netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
193 bit, reg, clear ? "clear" : "set");
194
1da177e4
LT		 195 return -ENODEV;
196 }
197 return 0;
198}
199
753f4920 200static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 201{
202 u32 val;
203
753f4920
MB		 204 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
205 (index << CAM_CTRL_INDEX_SHIFT)));
1da177e4 206
753f4920 207 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4 208
753f4920 209 val = br32(bp, B44_CAM_DATA_LO);
1da177e4 210
753f4920
MB		 211 data[2] = (val >> 24) & 0xFF;
212 data[3] = (val >> 16) & 0xFF;
213 data[4] = (val >> 8) & 0xFF;
214 data[5] = (val >> 0) & 0xFF;
1da177e4 215
753f4920 216 val = br32(bp, B44_CAM_DATA_HI);
1da177e4 217
753f4920
MB		 218 data[0] = (val >> 8) & 0xFF;
219 data[1] = (val >> 0) & 0xFF;
1da177e4
LT		 220}
221
753f4920 222static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 223{
224 u32 val;
225
226 val = ((u32) data[2]) << 24;
227 val |= ((u32) data[3]) << 16;
228 val |= ((u32) data[4]) << 8;
229 val |= ((u32) data[5]) << 0;
230 bw32(bp, B44_CAM_DATA_LO, val);
10badc21 231 val = (CAM_DATA_HI_VALID |
1da177e4
LT		 232 (((u32) data[0]) << 8) |
233 (((u32) data[1]) << 0));
234 bw32(bp, B44_CAM_DATA_HI, val);
235 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
236 (index << CAM_CTRL_INDEX_SHIFT)));
10badc21 237 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4
LT		 238}
239
240static inline void __b44_disable_ints(struct b44 *bp)
241{
242 bw32(bp, B44_IMASK, 0);
243}
244
245static void b44_disable_ints(struct b44 *bp)
246{
247 __b44_disable_ints(bp);
248
249 /* Flush posted writes. */
250 br32(bp, B44_IMASK);
251}
252
253static void b44_enable_ints(struct b44 *bp)
254{
255 bw32(bp, B44_IMASK, bp->imask);
256}
257
753f4920 258static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
1da177e4
LT		 259{
260 int err;
261
262 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
263 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
264 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
753f4920 265 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 266 (reg << MDIO_DATA_RA_SHIFT) |
267 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
268 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
269 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
270
271 return err;
272}
273
753f4920 274static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
1da177e4
LT		 275{
276 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
277 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
278 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
753f4920 279 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 280 (reg << MDIO_DATA_RA_SHIFT) |
281 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
282 (val & MDIO_DATA_DATA)));
283 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
284}
285
753f4920
MB		 286static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
287{
288 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
289 return 0;
290
291 return __b44_readphy(bp, bp->phy_addr, reg, val);
292}
293
294static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
295{
296 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
297 return 0;
298
299 return __b44_writephy(bp, bp->phy_addr, reg, val);
300}
301
1da177e4 302/* miilib interface */
1da177e4
LT		 303static int b44_mii_read(struct net_device *dev, int phy_id, int location)
304{
305 u32 val;
306 struct b44 *bp = netdev_priv(dev);
753f4920 307 int rc = __b44_readphy(bp, phy_id, location, &val);
1da177e4
LT		 308 if (rc)
309 return 0xffffffff;
310 return val;
311}
312
313static void b44_mii_write(struct net_device *dev, int phy_id, int location,
314 int val)
315{
316 struct b44 *bp = netdev_priv(dev);
753f4920 317 __b44_writephy(bp, phy_id, location, val);
1da177e4
LT		 318}
319
320static int b44_phy_reset(struct b44 *bp)
321{
322 u32 val;
323 int err;
324
753f4920
MB		 325 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
326 return 0;
1da177e4
LT		 327 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
328 if (err)
329 return err;
330 udelay(100);
331 err = b44_readphy(bp, MII_BMCR, &val);
332 if (!err) {
333 if (val & BMCR_RESET) {
2fc96fff 334 netdev_err(bp->dev, "PHY Reset would not complete\n");
1da177e4
LT		 335 err = -ENODEV;
336 }
337 }
338
8850dce1 339 return err;
1da177e4
LT		 340}
341
342static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
343{
344 u32 val;
345
346 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
347 bp->flags |= pause_flags;
348
349 val = br32(bp, B44_RXCONFIG);
350 if (pause_flags & B44_FLAG_RX_PAUSE)
351 val |= RXCONFIG_FLOW;
352 else
353 val &= ~RXCONFIG_FLOW;
354 bw32(bp, B44_RXCONFIG, val);
355
356 val = br32(bp, B44_MAC_FLOW);
357 if (pause_flags & B44_FLAG_TX_PAUSE)
358 val |= (MAC_FLOW_PAUSE_ENAB |
359 (0xc0 & MAC_FLOW_RX_HI_WATER));
360 else
361 val &= ~MAC_FLOW_PAUSE_ENAB;
362 bw32(bp, B44_MAC_FLOW, val);
363}
364
365static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
366{
10badc21 367 u32 pause_enab = 0;
2b474cf5
GZ		 368
369 /* The driver supports only rx pause by default because
10badc21
JG		 370 the b44 mac tx pause mechanism generates excessive
371 pause frames.
2b474cf5
GZ		 372 Use ethtool to turn on b44 tx pause if necessary.
373 */
374 if ((local & ADVERTISE_PAUSE_CAP) &&
10badc21 375 (local & ADVERTISE_PAUSE_ASYM)){
2b474cf5
GZ		 376 if ((remote & LPA_PAUSE_ASYM) &&
377 !(remote & LPA_PAUSE_CAP))
378 pause_enab |= B44_FLAG_RX_PAUSE;
1da177e4
LT		 379 }
380
381 __b44_set_flow_ctrl(bp, pause_enab);
382}
383
753f4920
MB		 384#ifdef SSB_DRIVER_MIPS
385extern char *nvram_get(char *name);
386static void b44_wap54g10_workaround(struct b44 *bp)
387{
388 const char *str;
389 u32 val;
390 int err;
391
392 /*
393 * workaround for bad hardware design in Linksys WAP54G v1.0
394 * see https://dev.openwrt.org/ticket/146
395 * check and reset bit "isolate"
396 */
397 str = nvram_get("boardnum");
398 if (!str)
399 return;
400 if (simple_strtoul(str, NULL, 0) == 2) {
401 err = __b44_readphy(bp, 0, MII_BMCR, &val);
402 if (err)
403 goto error;
404 if (!(val & BMCR_ISOLATE))
405 return;
406 val &= ~BMCR_ISOLATE;
407 err = __b44_writephy(bp, 0, MII_BMCR, val);
408 if (err)
409 goto error;
410 }
411 return;
412error:
2fc96fff 413 pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
753f4920
MB		 414}
415#else
416static inline void b44_wap54g10_workaround(struct b44 *bp)
417{
418}
419#endif
420
1da177e4
LT		 421static int b44_setup_phy(struct b44 *bp)
422{
423 u32 val;
424 int err;
425
753f4920
MB		 426 b44_wap54g10_workaround(bp);
427
428 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
429 return 0;
1da177e4
LT		 430 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
431 goto out;
432 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
433 val & MII_ALEDCTRL_ALLMSK)) != 0)
434 goto out;
435 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
436 goto out;
437 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
438 val | MII_TLEDCTRL_ENABLE)) != 0)
439 goto out;
440
441 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
442 u32 adv = ADVERTISE_CSMA;
443
444 if (bp->flags & B44_FLAG_ADV_10HALF)
445 adv |= ADVERTISE_10HALF;
446 if (bp->flags & B44_FLAG_ADV_10FULL)
447 adv |= ADVERTISE_10FULL;
448 if (bp->flags & B44_FLAG_ADV_100HALF)
449 adv |= ADVERTISE_100HALF;
450 if (bp->flags & B44_FLAG_ADV_100FULL)
451 adv |= ADVERTISE_100FULL;
452
453 if (bp->flags & B44_FLAG_PAUSE_AUTO)
454 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
455
456 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
457 goto out;
458 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
459 BMCR_ANRESTART))) != 0)
460 goto out;
461 } else {
462 u32 bmcr;
463
464 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
465 goto out;
466 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
467 if (bp->flags & B44_FLAG_100_BASE_T)
468 bmcr |= BMCR_SPEED100;
469 if (bp->flags & B44_FLAG_FULL_DUPLEX)
470 bmcr |= BMCR_FULLDPLX;
471 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
472 goto out;
473
474 /* Since we will not be negotiating there is no safe way
475 * to determine if the link partner supports flow control
476 * or not. So just disable it completely in this case.
477 */
478 b44_set_flow_ctrl(bp, 0, 0);
479 }
480
481out:
482 return err;
483}
484
485static void b44_stats_update(struct b44 *bp)
486{
487 unsigned long reg;
488 u32 *val;
489
490 val = &bp->hw_stats.tx_good_octets;
491 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
492 *val++ += br32(bp, reg);
493 }
3353930d
FR		 494
495 /* Pad */
496 reg += 8*4UL;
497
1da177e4
LT		 498 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
499 *val++ += br32(bp, reg);
500 }
501}
502
503static void b44_link_report(struct b44 *bp)
504{
505 if (!netif_carrier_ok(bp->dev)) {
2fc96fff 506 netdev_info(bp->dev, "Link is down\n");
1da177e4 507 } else {
2fc96fff
JP		 508 netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
509 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
510 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
511
512 netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
513 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
514 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
1da177e4
LT		 515 }
516}
517
518static void b44_check_phy(struct b44 *bp)
519{
520 u32 bmsr, aux;
521
753f4920
MB		 522 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
523 bp->flags |= B44_FLAG_100_BASE_T;
524 bp->flags |= B44_FLAG_FULL_DUPLEX;
525 if (!netif_carrier_ok(bp->dev)) {
526 u32 val = br32(bp, B44_TX_CTRL);
527 val |= TX_CTRL_DUPLEX;
528 bw32(bp, B44_TX_CTRL, val);
529 netif_carrier_on(bp->dev);
530 b44_link_report(bp);
531 }
532 return;
533 }
534
1da177e4
LT		 535 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
536 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
537 (bmsr != 0xffff)) {
538 if (aux & MII_AUXCTRL_SPEED)
539 bp->flags |= B44_FLAG_100_BASE_T;
540 else
541 bp->flags &= ~B44_FLAG_100_BASE_T;
542 if (aux & MII_AUXCTRL_DUPLEX)
543 bp->flags |= B44_FLAG_FULL_DUPLEX;
544 else
545 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
546
547 if (!netif_carrier_ok(bp->dev) &&
548 (bmsr & BMSR_LSTATUS)) {
549 u32 val = br32(bp, B44_TX_CTRL);
550 u32 local_adv, remote_adv;
551
552 if (bp->flags & B44_FLAG_FULL_DUPLEX)
553 val |= TX_CTRL_DUPLEX;
554 else
555 val &= ~TX_CTRL_DUPLEX;
556 bw32(bp, B44_TX_CTRL, val);
557
558 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
559 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
560 !b44_readphy(bp, MII_LPA, &remote_adv))
561 b44_set_flow_ctrl(bp, local_adv, remote_adv);
562
563 /* Link now up */
564 netif_carrier_on(bp->dev);
565 b44_link_report(bp);
566 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
567 /* Link now down */
568 netif_carrier_off(bp->dev);
569 b44_link_report(bp);
570 }
571
572 if (bmsr & BMSR_RFAULT)
2fc96fff 573 netdev_warn(bp->dev, "Remote fault detected in PHY\n");
1da177e4 574 if (bmsr & BMSR_JCD)
2fc96fff 575 netdev_warn(bp->dev, "Jabber detected in PHY\n");
1da177e4
LT		 576 }
577}
578
579static void b44_timer(unsigned long __opaque)
580{
581 struct b44 *bp = (struct b44 *) __opaque;
582
583 spin_lock_irq(&bp->lock);
584
585 b44_check_phy(bp);
586
587 b44_stats_update(bp);
588
589 spin_unlock_irq(&bp->lock);
590
a72a8179 591 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
1da177e4
LT		 592}
593
594static void b44_tx(struct b44 *bp)
595{
596 u32 cur, cons;
597
598 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
599 cur /= sizeof(struct dma_desc);
600
601 /* XXX needs updating when NETIF_F_SG is supported */
602 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
603 struct ring_info *rp = &bp->tx_buffers[cons];
604 struct sk_buff *skb = rp->skb;
605
5d9428de 606 BUG_ON(skb == NULL);
1da177e4 607
39a6f4bc
FT		 608 dma_unmap_single(bp->sdev->dma_dev,
609 rp->mapping,
610 skb->len,
611 DMA_TO_DEVICE);
1da177e4
LT		 612 rp->skb = NULL;
613 dev_kfree_skb_irq(skb);
614 }
615
616 bp->tx_cons = cons;
617 if (netif_queue_stopped(bp->dev) &&
618 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
619 netif_wake_queue(bp->dev);
620
621 bw32(bp, B44_GPTIMER, 0);
622}
623
624/* Works like this. This chip writes a 'struct rx_header" 30 bytes
625 * before the DMA address you give it. So we allocate 30 more bytes
626 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
627 * point the chip at 30 bytes past where the rx_header will go.
628 */
629static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
630{
631 struct dma_desc *dp;
632 struct ring_info *src_map, *map;
633 struct rx_header *rh;
634 struct sk_buff *skb;
635 dma_addr_t mapping;
636 int dest_idx;
637 u32 ctrl;
638
639 src_map = NULL;
640 if (src_idx >= 0)
641 src_map = &bp->rx_buffers[src_idx];
642 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
643 map = &bp->rx_buffers[dest_idx];
bf0dcbd9 644 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
1da177e4
LT		 645 if (skb == NULL)
646 return -ENOMEM;
647
39a6f4bc
FT		 648 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
649 RX_PKT_BUF_SZ,
650 DMA_FROM_DEVICE);
1da177e4
LT		 651
652 /* Hardware bug work-around, the chip is unable to do PCI DMA
653 to/from anything above 1GB :-( */
39a6f4bc 654 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
28b76796 655 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
1da177e4 656 /* Sigh... */
39a6f4bc
FT		 657 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
658 dma_unmap_single(bp->sdev->dma_dev, mapping,
f225763a 659 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
1da177e4 660 dev_kfree_skb_any(skb);
bf0dcbd9 661 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
1da177e4
LT		 662 if (skb == NULL)
663 return -ENOMEM;
39a6f4bc
FT		 664 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
665 RX_PKT_BUF_SZ,
666 DMA_FROM_DEVICE);
667 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
668 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
669 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
670 dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
1da177e4
LT		 671 dev_kfree_skb_any(skb);
672 return -ENOMEM;
673 }
a58c891a 674 bp->force_copybreak = 1;
1da177e4
LT		 675 }
676
72f4861e 677 rh = (struct rx_header *) skb->data;
1da177e4 678
1da177e4
LT		 679 rh->len = 0;
680 rh->flags = 0;
681
682 map->skb = skb;
753f4920 683 map->mapping = mapping;
1da177e4
LT		 684
685 if (src_map != NULL)
686 src_map->skb = NULL;
687
4ca85795 688 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
1da177e4
LT		 689 if (dest_idx == (B44_RX_RING_SIZE - 1))
690 ctrl |= DESC_CTRL_EOT;
691
692 dp = &bp->rx_ring[dest_idx];
693 dp->ctrl = cpu_to_le32(ctrl);
4ca85795 694 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
1da177e4 695
9f38c636 696 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 697 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 698 dest_idx * sizeof(*dp),
753f4920 699 DMA_BIDIRECTIONAL);
9f38c636 700
1da177e4
LT		 701 return RX_PKT_BUF_SZ;
702}
703
704static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
705{
706 struct dma_desc *src_desc, *dest_desc;
707 struct ring_info *src_map, *dest_map;
708 struct rx_header *rh;
709 int dest_idx;
a7bed27d 710 __le32 ctrl;
1da177e4
LT		 711
712 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
713 dest_desc = &bp->rx_ring[dest_idx];
714 dest_map = &bp->rx_buffers[dest_idx];
715 src_desc = &bp->rx_ring[src_idx];
716 src_map = &bp->rx_buffers[src_idx];
717
718 dest_map->skb = src_map->skb;
719 rh = (struct rx_header *) src_map->skb->data;
720 rh->len = 0;
721 rh->flags = 0;
753f4920 722 dest_map->mapping = src_map->mapping;
1da177e4 723
9f38c636 724 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 725 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 726 src_idx * sizeof(*src_desc),
753f4920 727 DMA_BIDIRECTIONAL);
9f38c636 728
1da177e4
LT		 729 ctrl = src_desc->ctrl;
730 if (dest_idx == (B44_RX_RING_SIZE - 1))
731 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
732 else
733 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
734
735 dest_desc->ctrl = ctrl;
736 dest_desc->addr = src_desc->addr;
9f38c636 737
1da177e4
LT		 738 src_map->skb = NULL;
739
9f38c636 740 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 741 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 742 dest_idx * sizeof(*dest_desc),
753f4920 743 DMA_BIDIRECTIONAL);
9f38c636 744
39a6f4bc
FT		 745 dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
746 RX_PKT_BUF_SZ,
747 DMA_FROM_DEVICE);
1da177e4
LT		 748}
749
750static int b44_rx(struct b44 *bp, int budget)
751{
752 int received;
753 u32 cons, prod;
754
755 received = 0;
756 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
757 prod /= sizeof(struct dma_desc);
758 cons = bp->rx_cons;
759
760 while (cons != prod && budget > 0) {
761 struct ring_info *rp = &bp->rx_buffers[cons];
762 struct sk_buff *skb = rp->skb;
753f4920 763 dma_addr_t map = rp->mapping;
1da177e4
LT		 764 struct rx_header *rh;
765 u16 len;
766
39a6f4bc
FT		 767 dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
768 RX_PKT_BUF_SZ,
769 DMA_FROM_DEVICE);
1da177e4 770 rh = (struct rx_header *) skb->data;
a7bed27d 771 len = le16_to_cpu(rh->len);
72f4861e 772 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
1da177e4
LT		 773 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
774 drop_it:
775 b44_recycle_rx(bp, cons, bp->rx_prod);
776 drop_it_no_recycle:
553e2335 777 bp->dev->stats.rx_dropped++;
1da177e4
LT		 778 goto next_pkt;
779 }
780
781 if (len == 0) {
782 int i = 0;
783
784 do {
785 udelay(2);
786 barrier();
a7bed27d 787 len = le16_to_cpu(rh->len);
1da177e4
LT		 788 } while (len == 0 && i++ < 5);
789 if (len == 0)
790 goto drop_it;
791 }
792
793 /* Omit CRC. */
794 len -= 4;
795
a58c891a 796 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
1da177e4
LT		 797 int skb_size;
798 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
799 if (skb_size < 0)
800 goto drop_it;
39a6f4bc
FT		 801 dma_unmap_single(bp->sdev->dma_dev, map,
802 skb_size, DMA_FROM_DEVICE);
1da177e4 803 /* Leave out rx_header */
4ca85795
FF		 804 skb_put(skb, len + RX_PKT_OFFSET);
805 skb_pull(skb, RX_PKT_OFFSET);
1da177e4
LT		 806 } else {
807 struct sk_buff *copy_skb;
808
809 b44_recycle_rx(bp, cons, bp->rx_prod);
53639207 810 copy_skb = netdev_alloc_skb(bp->dev, len + 2);
1da177e4
LT		 811 if (copy_skb == NULL)
812 goto drop_it_no_recycle;
813
1da177e4
LT		 814 skb_reserve(copy_skb, 2);
815 skb_put(copy_skb, len);
816 /* DMA sync done above, copy just the actual packet */
72f4861e 817 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
d626f62b 818 copy_skb->data, len);
1da177e4
LT		 819 skb = copy_skb;
820 }
821 skb->ip_summed = CHECKSUM_NONE;
822 skb->protocol = eth_type_trans(skb, bp->dev);
823 netif_receive_skb(skb);
1da177e4
LT		 824 received++;
825 budget--;
826 next_pkt:
827 bp->rx_prod = (bp->rx_prod + 1) &
828 (B44_RX_RING_SIZE - 1);
829 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
830 }
831
832 bp->rx_cons = cons;
833 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
834
835 return received;
836}
837
bea3348e 838static int b44_poll(struct napi_struct *napi, int budget)
1da177e4 839{
bea3348e 840 struct b44 *bp = container_of(napi, struct b44, napi);
bea3348e 841 int work_done;
e99b1f04 842 unsigned long flags;
1da177e4 843
e99b1f04 844 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 845
846 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
847 /* spin_lock(&bp->tx_lock); */
848 b44_tx(bp);
849 /* spin_unlock(&bp->tx_lock); */
850 }
e99b1f04 851 spin_unlock_irqrestore(&bp->lock, flags);
1da177e4 852
bea3348e
SH		 853 work_done = 0;
854 if (bp->istat & ISTAT_RX)
855 work_done += b44_rx(bp, budget);
1da177e4
LT		 856
857 if (bp->istat & ISTAT_ERRORS) {
d15e9c4d 858 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 859 b44_halt(bp);
860 b44_init_rings(bp);
5fc7d61a 861 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
1da177e4 862 netif_wake_queue(bp->dev);
d15e9c4d 863 spin_unlock_irqrestore(&bp->lock, flags);
bea3348e 864 work_done = 0;
1da177e4
LT		 865 }
866
bea3348e 867 if (work_done < budget) {
288379f0 868 napi_complete(napi);
1da177e4
LT		 869 b44_enable_ints(bp);
870 }
871
bea3348e 872 return work_done;
1da177e4
LT		 873}
874
7d12e780 875static irqreturn_t b44_interrupt(int irq, void *dev_id)
1da177e4
LT		 876{
877 struct net_device *dev = dev_id;
878 struct b44 *bp = netdev_priv(dev);
1da177e4
LT		 879 u32 istat, imask;
880 int handled = 0;
881
65b984f2 882 spin_lock(&bp->lock);
1da177e4
LT		 883
884 istat = br32(bp, B44_ISTAT);
885 imask = br32(bp, B44_IMASK);
886
e78181fe
JB		 887 /* The interrupt mask register controls which interrupt bits
888 * will actually raise an interrupt to the CPU when set by hw/firmware,
889 * but doesn't mask off the bits.
1da177e4
LT		 890 */
891 istat &= imask;
892 if (istat) {
893 handled = 1;
ba5eec9c
FR		 894
895 if (unlikely(!netif_running(dev))) {
2fc96fff 896 netdev_info(dev, "late interrupt\n");
ba5eec9c
FR		 897 goto irq_ack;
898 }
899
288379f0 900 if (napi_schedule_prep(&bp->napi)) {
1da177e4
LT		 901 /* NOTE: These writes are posted by the readback of
902 * the ISTAT register below.
903 */
904 bp->istat = istat;
905 __b44_disable_ints(bp);
288379f0 906 __napi_schedule(&bp->napi);
1da177e4
LT		 907 }
908
ba5eec9c 909irq_ack:
1da177e4
LT		 910 bw32(bp, B44_ISTAT, istat);
911 br32(bp, B44_ISTAT);
912 }
65b984f2 913 spin_unlock(&bp->lock);
1da177e4
LT		 914 return IRQ_RETVAL(handled);
915}
916
917static void b44_tx_timeout(struct net_device *dev)
918{
919 struct b44 *bp = netdev_priv(dev);
920
2fc96fff 921 netdev_err(dev, "transmit timed out, resetting\n");
1da177e4
LT		 922
923 spin_lock_irq(&bp->lock);
924
925 b44_halt(bp);
926 b44_init_rings(bp);
5fc7d61a 927 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 928
929 spin_unlock_irq(&bp->lock);
930
931 b44_enable_ints(bp);
932
933 netif_wake_queue(dev);
934}
935
61357325 936static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 937{
938 struct b44 *bp = netdev_priv(dev);
c7193693 939 int rc = NETDEV_TX_OK;
1da177e4
LT		 940 dma_addr_t mapping;
941 u32 len, entry, ctrl;
22580f89 942 unsigned long flags;
1da177e4
LT		 943
944 len = skb->len;
22580f89 945 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 946
947 /* This is a hard error, log it. */
948 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
949 netif_stop_queue(dev);
2fc96fff 950 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
c7193693 951 goto err_out;
1da177e4
LT		 952 }
953
39a6f4bc
FT		 954 mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
955 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
f65a7177
SH		 956 struct sk_buff *bounce_skb;
957
1da177e4 958 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
39a6f4bc
FT		 959 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
960 dma_unmap_single(bp->sdev->dma_dev, mapping, len,
f225763a 961 DMA_TO_DEVICE);
1da177e4 962
9034f77b 963 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
1da177e4 964 if (!bounce_skb)
c7193693 965 goto err_out;
1da177e4 966
39a6f4bc
FT		 967 mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
968 len, DMA_TO_DEVICE);
969 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
970 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
971 dma_unmap_single(bp->sdev->dma_dev, mapping,
f225763a 972 len, DMA_TO_DEVICE);
1da177e4 973 dev_kfree_skb_any(bounce_skb);
c7193693 974 goto err_out;
1da177e4
LT		 975 }
976
f65a7177 977 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
1da177e4
LT		 978 dev_kfree_skb_any(skb);
979 skb = bounce_skb;
980 }
981
982 entry = bp->tx_prod;
983 bp->tx_buffers[entry].skb = skb;
753f4920 984 bp->tx_buffers[entry].mapping = mapping;
1da177e4
LT		 985
986 ctrl = (len & DESC_CTRL_LEN);
987 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
988 if (entry == (B44_TX_RING_SIZE - 1))
989 ctrl |= DESC_CTRL_EOT;
990
991 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
992 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
993
9f38c636 994 if (bp->flags & B44_FLAG_TX_RING_HACK)
753f4920
MB		 995 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
996 entry * sizeof(bp->tx_ring[0]),
997 DMA_TO_DEVICE);
9f38c636 998
1da177e4
LT		 999 entry = NEXT_TX(entry);
1000
1001 bp->tx_prod = entry;
1002
1003 wmb();
1004
1005 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1006 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1007 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1008 if (bp->flags & B44_FLAG_REORDER_BUG)
1009 br32(bp, B44_DMATX_PTR);
1010
1011 if (TX_BUFFS_AVAIL(bp) < 1)
1012 netif_stop_queue(dev);
1013
c7193693 1014out_unlock:
22580f89 1015 spin_unlock_irqrestore(&bp->lock, flags);
1da177e4 1016
c7193693 1017 return rc;
1da177e4 1018
c7193693
FR		 1019err_out:
1020 rc = NETDEV_TX_BUSY;
1021 goto out_unlock;
1da177e4
LT		 1022}
1023
1024static int b44_change_mtu(struct net_device *dev, int new_mtu)
1025{
1026 struct b44 *bp = netdev_priv(dev);
1027
1028 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1029 return -EINVAL;
1030
1031 if (!netif_running(dev)) {
1032 /* We'll just catch it later when the
1033 * device is up'd.
1034 */
1035 dev->mtu = new_mtu;
1036 return 0;
1037 }
1038
1039 spin_lock_irq(&bp->lock);
1040 b44_halt(bp);
1041 dev->mtu = new_mtu;
1042 b44_init_rings(bp);
5fc7d61a 1043 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1044 spin_unlock_irq(&bp->lock);
1045
1046 b44_enable_ints(bp);
10badc21 1047
1da177e4
LT		 1048 return 0;
1049}
1050
1051/* Free up pending packets in all rx/tx rings.
1052 *
1053 * The chip has been shut down and the driver detached from
1054 * the networking, so no interrupts or new tx packets will
1055 * end up in the driver. bp->lock is not held and we are not
1056 * in an interrupt context and thus may sleep.
1057 */
1058static void b44_free_rings(struct b44 *bp)
1059{
1060 struct ring_info *rp;
1061 int i;
1062
1063 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1064 rp = &bp->rx_buffers[i];
1065
1066 if (rp->skb == NULL)
1067 continue;
39a6f4bc
FT		 1068 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
1069 DMA_FROM_DEVICE);
1da177e4
LT		 1070 dev_kfree_skb_any(rp->skb);
1071 rp->skb = NULL;
1072 }
1073
1074 /* XXX needs changes once NETIF_F_SG is set... */
1075 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1076 rp = &bp->tx_buffers[i];
1077
1078 if (rp->skb == NULL)
1079 continue;
39a6f4bc
FT		 1080 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
1081 DMA_TO_DEVICE);
1da177e4
LT		 1082 dev_kfree_skb_any(rp->skb);
1083 rp->skb = NULL;
1084 }
1085}
1086
1087/* Initialize tx/rx rings for packet processing.
1088 *
1089 * The chip has been shut down and the driver detached from
1090 * the networking, so no interrupts or new tx packets will
874a6214 1091 * end up in the driver.
1da177e4
LT		 1092 */
1093static void b44_init_rings(struct b44 *bp)
1094{
1095 int i;
1096
1097 b44_free_rings(bp);
1098
1099 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1100 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1101
9f38c636 1102 if (bp->flags & B44_FLAG_RX_RING_HACK)
39a6f4bc
FT		 1103 dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
1104 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
9f38c636
JL		 1105
1106 if (bp->flags & B44_FLAG_TX_RING_HACK)
39a6f4bc
FT		 1107 dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
1108 DMA_TABLE_BYTES, DMA_TO_DEVICE);
9f38c636 1109
1da177e4
LT		 1110 for (i = 0; i < bp->rx_pending; i++) {
1111 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1112 break;
1113 }
1114}
1115
1116/*
1117 * Must not be invoked with interrupt sources disabled and
1118 * the hardware shutdown down.
1119 */
1120static void b44_free_consistent(struct b44 *bp)
1121{
b4558ea9
JJ		 1122 kfree(bp->rx_buffers);
1123 bp->rx_buffers = NULL;
1124 kfree(bp->tx_buffers);
1125 bp->tx_buffers = NULL;
1da177e4 1126 if (bp->rx_ring) {
9f38c636 1127 if (bp->flags & B44_FLAG_RX_RING_HACK) {
39a6f4bc
FT		 1128 dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
1129 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
9f38c636
JL		 1130 kfree(bp->rx_ring);
1131 } else
39a6f4bc
FT		 1132 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1133 bp->rx_ring, bp->rx_ring_dma);
1da177e4 1134 bp->rx_ring = NULL;
9f38c636 1135 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1da177e4
LT		 1136 }
1137 if (bp->tx_ring) {
9f38c636 1138 if (bp->flags & B44_FLAG_TX_RING_HACK) {
39a6f4bc
FT		 1139 dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
1140 DMA_TABLE_BYTES, DMA_TO_DEVICE);
9f38c636
JL		 1141 kfree(bp->tx_ring);
1142 } else
39a6f4bc
FT		 1143 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1144 bp->tx_ring, bp->tx_ring_dma);
1da177e4 1145 bp->tx_ring = NULL;
9f38c636 1146 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1da177e4
LT		 1147 }
1148}
1149
1150/*
1151 * Must not be invoked with interrupt sources disabled and
1152 * the hardware shutdown down. Can sleep.
1153 */
753f4920 1154static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1da177e4
LT		 1155{
1156 int size;
1157
1158 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
753f4920 1159 bp->rx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1160 if (!bp->rx_buffers)
1161 goto out_err;
1da177e4
LT		 1162
1163 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
753f4920 1164 bp->tx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1165 if (!bp->tx_buffers)
1166 goto out_err;
1da177e4
LT		 1167
1168 size = DMA_TABLE_BYTES;
39a6f4bc
FT		 1169 bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1170 &bp->rx_ring_dma, gfp);
9f38c636
JL		 1171 if (!bp->rx_ring) {
1172 /* Allocation may have failed due to pci_alloc_consistent
1173 insisting on use of GFP_DMA, which is more restrictive
1174 than necessary... */
1175 struct dma_desc *rx_ring;
1176 dma_addr_t rx_ring_dma;
1177
753f4920 1178 rx_ring = kzalloc(size, gfp);
874a6214 1179 if (!rx_ring)
9f38c636
JL		 1180 goto out_err;
1181
39a6f4bc
FT		 1182 rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
1183 DMA_TABLE_BYTES,
1184 DMA_BIDIRECTIONAL);
9f38c636 1185
39a6f4bc 1186 if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
28b76796 1187 rx_ring_dma + size > DMA_BIT_MASK(30)) {
9f38c636
JL		 1188 kfree(rx_ring);
1189 goto out_err;
1190 }
1191
1192 bp->rx_ring = rx_ring;
1193 bp->rx_ring_dma = rx_ring_dma;
1194 bp->flags |= B44_FLAG_RX_RING_HACK;
1195 }
1da177e4 1196
39a6f4bc
FT		 1197 bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1198 &bp->tx_ring_dma, gfp);
9f38c636 1199 if (!bp->tx_ring) {
f225763a 1200 /* Allocation may have failed due to ssb_dma_alloc_consistent
9f38c636
JL		 1201 insisting on use of GFP_DMA, which is more restrictive
1202 than necessary... */
1203 struct dma_desc *tx_ring;
1204 dma_addr_t tx_ring_dma;
1205
753f4920 1206 tx_ring = kzalloc(size, gfp);
874a6214 1207 if (!tx_ring)
9f38c636
JL		 1208 goto out_err;
1209
39a6f4bc
FT		 1210 tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
1211 DMA_TABLE_BYTES,
1212 DMA_TO_DEVICE);
9f38c636 1213
39a6f4bc 1214 if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
28b76796 1215 tx_ring_dma + size > DMA_BIT_MASK(30)) {
9f38c636
JL		 1216 kfree(tx_ring);
1217 goto out_err;
1218 }
1219
1220 bp->tx_ring = tx_ring;
1221 bp->tx_ring_dma = tx_ring_dma;
1222 bp->flags |= B44_FLAG_TX_RING_HACK;
1223 }
1da177e4
LT		 1224
1225 return 0;
1226
1227out_err:
1228 b44_free_consistent(bp);
1229 return -ENOMEM;
1230}
1231
1232/* bp->lock is held. */
1233static void b44_clear_stats(struct b44 *bp)
1234{
1235 unsigned long reg;
1236
1237 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1238 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1239 br32(bp, reg);
1240 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1241 br32(bp, reg);
1242}
1243
1244/* bp->lock is held. */
fedb0eef 1245static void b44_chip_reset(struct b44 *bp, int reset_kind)
1da177e4 1246{
753f4920 1247 struct ssb_device *sdev = bp->sdev;
f8af11af 1248 bool was_enabled;
753f4920 1249
f8af11af
MB		 1250 was_enabled = ssb_device_is_enabled(bp->sdev);
1251
1252 ssb_device_enable(bp->sdev, 0);
1253 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1254
1255 if (was_enabled) {
1da177e4
LT		 1256 bw32(bp, B44_RCV_LAZY, 0);
1257 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
40ee8c76 1258 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1da177e4
LT		 1259 bw32(bp, B44_DMATX_CTRL, 0);
1260 bp->tx_prod = bp->tx_cons = 0;
1261 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1262 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1263 100, 0);
1264 }
1265 bw32(bp, B44_DMARX_CTRL, 0);
1266 bp->rx_prod = bp->rx_cons = 0;
f8af11af 1267 }
1da177e4
LT		 1268
1269 b44_clear_stats(bp);
1270
fedb0eef
MB		 1271 /*
1272 * Don't enable PHY if we are doing a partial reset
1273 * we are probably going to power down
1274 */
1275 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1276 return;
1277
753f4920
MB		 1278 switch (sdev->bus->bustype) {
1279 case SSB_BUSTYPE_SSB:
1280 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
39506a55
JL		 1281 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1282 B44_MDC_RATIO)
753f4920
MB		 1283 & MDIO_CTRL_MAXF_MASK)));
1284 break;
1285 case SSB_BUSTYPE_PCI:
753f4920
MB		 1286 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1287 (0x0d & MDIO_CTRL_MAXF_MASK)));
1288 break;
98a1e2a9
MB		 1289 case SSB_BUSTYPE_PCMCIA:
1290 case SSB_BUSTYPE_SDIO:
1291 WARN_ON(1); /* A device with this bus does not exist. */
1292 break;
753f4920
MB		 1293 }
1294
1da177e4
LT		 1295 br32(bp, B44_MDIO_CTRL);
1296
1297 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1298 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1299 br32(bp, B44_ENET_CTRL);
1300 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1301 } else {
1302 u32 val = br32(bp, B44_DEVCTRL);
1303
1304 if (val & DEVCTRL_EPR) {
1305 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1306 br32(bp, B44_DEVCTRL);
1307 udelay(100);
1308 }
1309 bp->flags |= B44_FLAG_INTERNAL_PHY;
1310 }
1311}
1312
1313/* bp->lock is held. */
1314static void b44_halt(struct b44 *bp)
1315{
1316 b44_disable_ints(bp);
fedb0eef
MB		 1317 /* reset PHY */
1318 b44_phy_reset(bp);
1319 /* power down PHY */
2fc96fff 1320 netdev_info(bp->dev, "powering down PHY\n");
fedb0eef
MB		 1321 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1322 /* now reset the chip, but without enabling the MAC&PHY
1323 * part of it. This has to be done _after_ we shut down the PHY */
1324 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1da177e4
LT		 1325}
1326
1327/* bp->lock is held. */
1328static void __b44_set_mac_addr(struct b44 *bp)
1329{
1330 bw32(bp, B44_CAM_CTRL, 0);
1331 if (!(bp->dev->flags & IFF_PROMISC)) {
1332 u32 val;
1333
1334 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1335 val = br32(bp, B44_CAM_CTRL);
1336 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1337 }
1338}
1339
1340static int b44_set_mac_addr(struct net_device *dev, void *p)
1341{
1342 struct b44 *bp = netdev_priv(dev);
1343 struct sockaddr *addr = p;
753f4920 1344 u32 val;
1da177e4
LT		 1345
1346 if (netif_running(dev))
1347 return -EBUSY;
1348
391fc09a
GZ		 1349 if (!is_valid_ether_addr(addr->sa_data))
1350 return -EINVAL;
1351
1da177e4
LT		 1352 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1353
1354 spin_lock_irq(&bp->lock);
753f4920
MB		 1355
1356 val = br32(bp, B44_RXCONFIG);
1357 if (!(val & RXCONFIG_CAM_ABSENT))
1358 __b44_set_mac_addr(bp);
1359
1da177e4
LT		 1360 spin_unlock_irq(&bp->lock);
1361
1362 return 0;
1363}
1364
1365/* Called at device open time to get the chip ready for
1366 * packet processing. Invoked with bp->lock held.
1367 */
1368static void __b44_set_rx_mode(struct net_device *);
5fc7d61a 1369static void b44_init_hw(struct b44 *bp, int reset_kind)
1da177e4
LT		 1370{
1371 u32 val;
1372
fedb0eef 1373 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5fc7d61a 1374 if (reset_kind == B44_FULL_RESET) {
00e8b3aa
GZ		 1375 b44_phy_reset(bp);
1376 b44_setup_phy(bp);
1377 }
1da177e4
LT		 1378
1379 /* Enable CRC32, set proper LED modes and power on PHY */
1380 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1381 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1382
1383 /* This sets the MAC address too. */
1384 __b44_set_rx_mode(bp->dev);
1385
1386 /* MTU + eth header + possible VLAN tag + struct rx_header */
1387 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1388 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1389
1390 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
5fc7d61a
MC		 1391 if (reset_kind == B44_PARTIAL_RESET) {
1392 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1393 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
5fc7d61a 1394 } else {
00e8b3aa
GZ		 1395 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1396 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1397 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1398 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
00e8b3aa 1399 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1da177e4 1400
00e8b3aa
GZ		 1401 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1402 bp->rx_prod = bp->rx_pending;
1da177e4 1403
00e8b3aa 1404 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
00e8b3aa 1405 }
1da177e4
LT		 1406
1407 val = br32(bp, B44_ENET_CTRL);
1408 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1409}
1410
1411static int b44_open(struct net_device *dev)
1412{
1413 struct b44 *bp = netdev_priv(dev);
1414 int err;
1415
753f4920 1416 err = b44_alloc_consistent(bp, GFP_KERNEL);
1da177e4 1417 if (err)
6c2f4267 1418 goto out;
1da177e4 1419
bea3348e
SH		 1420 napi_enable(&bp->napi);
1421
1da177e4 1422 b44_init_rings(bp);
5fc7d61a 1423 b44_init_hw(bp, B44_FULL_RESET);
1da177e4 1424
e254e9bf
JL		 1425 b44_check_phy(bp);
1426
1fb9df5d 1427 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
6c2f4267 1428 if (unlikely(err < 0)) {
bea3348e 1429 napi_disable(&bp->napi);
fedb0eef 1430 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
6c2f4267
FR		 1431 b44_free_rings(bp);
1432 b44_free_consistent(bp);
1433 goto out;
1434 }
1da177e4
LT		 1435
1436 init_timer(&bp->timer);
1437 bp->timer.expires = jiffies + HZ;
1438 bp->timer.data = (unsigned long) bp;
1439 bp->timer.function = b44_timer;
1440 add_timer(&bp->timer);
1441
1442 b44_enable_ints(bp);
d9e2d185 1443 netif_start_queue(dev);
6c2f4267 1444out:
1da177e4
LT		 1445 return err;
1446}
1447
1da177e4
LT		 1448#ifdef CONFIG_NET_POLL_CONTROLLER
1449/*
1450 * Polling receive - used by netconsole and other diagnostic tools
1451 * to allow network i/o with interrupts disabled.
1452 */
1453static void b44_poll_controller(struct net_device *dev)
1454{
1455 disable_irq(dev->irq);
7d12e780 1456 b44_interrupt(dev->irq, dev);
1da177e4
LT		 1457 enable_irq(dev->irq);
1458}
1459#endif
1460
725ad800
GZ		 1461static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1462{
1463 u32 i;
1464 u32 *pattern = (u32 *) pp;
1465
1466 for (i = 0; i < bytes; i += sizeof(u32)) {
1467 bw32(bp, B44_FILT_ADDR, table_offset + i);
1468 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1469 }
1470}
1471
1472static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1473{
1474 int magicsync = 6;
1475 int k, j, len = offset;
1476 int ethaddr_bytes = ETH_ALEN;
1477
1478 memset(ppattern + offset, 0xff, magicsync);
1479 for (j = 0; j < magicsync; j++)
1480 set_bit(len++, (unsigned long *) pmask);
1481
1482 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1483 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1484 ethaddr_bytes = ETH_ALEN;
1485 else
1486 ethaddr_bytes = B44_PATTERN_SIZE - len;
1487 if (ethaddr_bytes <=0)
1488 break;
1489 for (k = 0; k< ethaddr_bytes; k++) {
1490 ppattern[offset + magicsync +
1491 (j * ETH_ALEN) + k] = macaddr[k];
e0188829 1492 set_bit(len++, (unsigned long *) pmask);
725ad800
GZ		 1493 }
1494 }
1495 return len - 1;
1496}
1497
1498/* Setup magic packet patterns in the b44 WOL
1499 * pattern matching filter.
1500 */
1501static void b44_setup_pseudo_magicp(struct b44 *bp)
1502{
1503
1504 u32 val;
1505 int plen0, plen1, plen2;
1506 u8 *pwol_pattern;
1507 u8 pwol_mask[B44_PMASK_SIZE];
1508
dd00cc48 1509 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
725ad800 1510 if (!pwol_pattern) {
2fc96fff 1511 pr_err("Memory not available for WOL\n");
725ad800
GZ		 1512 return;
1513 }
1514
1515 /* Ipv4 magic packet pattern - pattern 0.*/
725ad800
GZ		 1516 memset(pwol_mask, 0, B44_PMASK_SIZE);
1517 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1518 B44_ETHIPV4UDP_HLEN);
1519
1520 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1521 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1522
1523 /* Raw ethernet II magic packet pattern - pattern 1 */
1524 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1525 memset(pwol_mask, 0, B44_PMASK_SIZE);
1526 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1527 ETH_HLEN);
1528
1529 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1530 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1531 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1532 B44_PMASK_BASE + B44_PMASK_SIZE);
1533
1534 /* Ipv6 magic packet pattern - pattern 2 */
1535 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1536 memset(pwol_mask, 0, B44_PMASK_SIZE);
1537 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1538 B44_ETHIPV6UDP_HLEN);
1539
1540 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1541 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1542 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1543 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1544
1545 kfree(pwol_pattern);
1546
1547 /* set these pattern's lengths: one less than each real length */
1548 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1549 bw32(bp, B44_WKUP_LEN, val);
1550
1551 /* enable wakeup pattern matching */
1552 val = br32(bp, B44_DEVCTRL);
1553 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1554
1555}
52cafd96 1556
753f4920
MB		 1557#ifdef CONFIG_B44_PCI
1558static void b44_setup_wol_pci(struct b44 *bp)
1559{
1560 u16 val;
1561
1562 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1563 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1564 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1565 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1566 }
1567}
1568#else
1569static inline void b44_setup_wol_pci(struct b44 *bp) { }
1570#endif /* CONFIG_B44_PCI */
1571
52cafd96
GZ		 1572static void b44_setup_wol(struct b44 *bp)
1573{
1574 u32 val;
52cafd96
GZ		 1575
1576 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1577
1578 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1579
1580 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1581
1582 val = bp->dev->dev_addr[2] << 24 |
1583 bp->dev->dev_addr[3] << 16 |
1584 bp->dev->dev_addr[4] << 8 |
1585 bp->dev->dev_addr[5];
1586 bw32(bp, B44_ADDR_LO, val);
1587
1588 val = bp->dev->dev_addr[0] << 8 |
1589 bp->dev->dev_addr[1];
1590 bw32(bp, B44_ADDR_HI, val);
1591
1592 val = br32(bp, B44_DEVCTRL);
1593 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1594
725ad800
GZ		 1595 } else {
1596 b44_setup_pseudo_magicp(bp);
1597 }
753f4920 1598 b44_setup_wol_pci(bp);
52cafd96
GZ		 1599}
1600
1da177e4
LT		 1601static int b44_close(struct net_device *dev)
1602{
1603 struct b44 *bp = netdev_priv(dev);
1604
1605 netif_stop_queue(dev);
1606
bea3348e 1607 napi_disable(&bp->napi);
ba5eec9c 1608
1da177e4
LT		 1609 del_timer_sync(&bp->timer);
1610
1611 spin_lock_irq(&bp->lock);
1612
1da177e4
LT		 1613 b44_halt(bp);
1614 b44_free_rings(bp);
c35ca399 1615 netif_carrier_off(dev);
1da177e4
LT		 1616
1617 spin_unlock_irq(&bp->lock);
1618
1619 free_irq(dev->irq, dev);
1620
52cafd96 1621 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 1622 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 1623 b44_setup_wol(bp);
1624 }
1625
1da177e4
LT		 1626 b44_free_consistent(bp);
1627
1628 return 0;
1629}
1630
1631static struct net_device_stats *b44_get_stats(struct net_device *dev)
1632{
1633 struct b44 *bp = netdev_priv(dev);
553e2335 1634 struct net_device_stats *nstat = &dev->stats;
1da177e4
LT		 1635 struct b44_hw_stats *hwstat = &bp->hw_stats;
1636
1637 /* Convert HW stats into netdevice stats. */
1638 nstat->rx_packets = hwstat->rx_pkts;
1639 nstat->tx_packets = hwstat->tx_pkts;
1640 nstat->rx_bytes = hwstat->rx_octets;
1641 nstat->tx_bytes = hwstat->tx_octets;
1642 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1643 hwstat->tx_oversize_pkts +
1644 hwstat->tx_underruns +
1645 hwstat->tx_excessive_cols +
1646 hwstat->tx_late_cols);
1647 nstat->multicast = hwstat->tx_multicast_pkts;
1648 nstat->collisions = hwstat->tx_total_cols;
1649
1650 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1651 hwstat->rx_undersize);
1652 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1653 nstat->rx_frame_errors = hwstat->rx_align_errs;
1654 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1655 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1656 hwstat->rx_oversize_pkts +
1657 hwstat->rx_missed_pkts +
1658 hwstat->rx_crc_align_errs +
1659 hwstat->rx_undersize +
1660 hwstat->rx_crc_errs +
1661 hwstat->rx_align_errs +
1662 hwstat->rx_symbol_errs);
1663
1664 nstat->tx_aborted_errors = hwstat->tx_underruns;
1665#if 0
1666 /* Carrier lost counter seems to be broken for some devices */
1667 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1668#endif
1669
1670 return nstat;
1671}
1672
1673static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1674{
22bedad3 1675 struct netdev_hw_addr *ha;
1da177e4
LT		 1676 int i, num_ents;
1677
4cd24eaf 1678 num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
0ddf477b 1679 i = 0;
22bedad3 1680 netdev_for_each_mc_addr(ha, dev) {
0ddf477b
JP		 1681 if (i == num_ents)
1682 break;
22bedad3 1683 __b44_cam_write(bp, ha->addr, i++ + 1);
1da177e4
LT		 1684 }
1685 return i+1;
1686}
1687
1688static void __b44_set_rx_mode(struct net_device *dev)
1689{
1690 struct b44 *bp = netdev_priv(dev);
1691 u32 val;
1da177e4
LT		 1692
1693 val = br32(bp, B44_RXCONFIG);
1694 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
753f4920 1695 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1da177e4
LT		 1696 val |= RXCONFIG_PROMISC;
1697 bw32(bp, B44_RXCONFIG, val);
1698 } else {
874a6214 1699 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
cda22aa9 1700 int i = 1;
874a6214 1701
1da177e4
LT		 1702 __b44_set_mac_addr(bp);
1703
2f614fe0 1704 if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf 1705 (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
1da177e4
LT		 1706 val |= RXCONFIG_ALLMULTI;
1707 else
874a6214 1708 i = __b44_load_mcast(bp, dev);
10badc21 1709
2f614fe0 1710 for (; i < 64; i++)
10badc21 1711 __b44_cam_write(bp, zero, i);
2f614fe0 1712
1da177e4
LT		 1713 bw32(bp, B44_RXCONFIG, val);
1714 val = br32(bp, B44_CAM_CTRL);
1715 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1716 }
1717}
1718
1719static void b44_set_rx_mode(struct net_device *dev)
1720{
1721 struct b44 *bp = netdev_priv(dev);
1722
1723 spin_lock_irq(&bp->lock);
1724 __b44_set_rx_mode(dev);
1725 spin_unlock_irq(&bp->lock);
1726}
1727
1728static u32 b44_get_msglevel(struct net_device *dev)
1729{
1730 struct b44 *bp = netdev_priv(dev);
1731 return bp->msg_enable;
1732}
1733
1734static void b44_set_msglevel(struct net_device *dev, u32 value)
1735{
1736 struct b44 *bp = netdev_priv(dev);
1737 bp->msg_enable = value;
1738}
1739
1740static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1741{
1742 struct b44 *bp = netdev_priv(dev);
753f4920 1743 struct ssb_bus *bus = bp->sdev->bus;
1da177e4 1744
27e09551 1745 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1746 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
753f4920
MB		 1747 switch (bus->bustype) {
1748 case SSB_BUSTYPE_PCI:
27e09551 1749 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
753f4920 1750 break;
753f4920 1751 case SSB_BUSTYPE_SSB:
27e09551 1752 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
753f4920 1753 break;
98a1e2a9
MB		 1754 case SSB_BUSTYPE_PCMCIA:
1755 case SSB_BUSTYPE_SDIO:
1756 WARN_ON(1); /* A device with this bus does not exist. */
1757 break;
753f4920 1758 }
1da177e4
LT		 1759}
1760
1761static int b44_nway_reset(struct net_device *dev)
1762{
1763 struct b44 *bp = netdev_priv(dev);
1764 u32 bmcr;
1765 int r;
1766
1767 spin_lock_irq(&bp->lock);
1768 b44_readphy(bp, MII_BMCR, &bmcr);
1769 b44_readphy(bp, MII_BMCR, &bmcr);
1770 r = -EINVAL;
1771 if (bmcr & BMCR_ANENABLE) {
1772 b44_writephy(bp, MII_BMCR,
1773 bmcr | BMCR_ANRESTART);
1774 r = 0;
1775 }
1776 spin_unlock_irq(&bp->lock);
1777
1778 return r;
1779}
1780
1781static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1782{
1783 struct b44 *bp = netdev_priv(dev);
1784
1da177e4
LT		 1785 cmd->supported = (SUPPORTED_Autoneg);
1786 cmd->supported |= (SUPPORTED_100baseT_Half |
1787 SUPPORTED_100baseT_Full |
1788 SUPPORTED_10baseT_Half |
1789 SUPPORTED_10baseT_Full |
1790 SUPPORTED_MII);
1791
1792 cmd->advertising = 0;
1793 if (bp->flags & B44_FLAG_ADV_10HALF)
adf6e000 1794 cmd->advertising |= ADVERTISED_10baseT_Half;
1da177e4 1795 if (bp->flags & B44_FLAG_ADV_10FULL)
adf6e000 1796 cmd->advertising |= ADVERTISED_10baseT_Full;
1da177e4 1797 if (bp->flags & B44_FLAG_ADV_100HALF)
adf6e000 1798 cmd->advertising |= ADVERTISED_100baseT_Half;
1da177e4 1799 if (bp->flags & B44_FLAG_ADV_100FULL)
adf6e000
MW		 1800 cmd->advertising |= ADVERTISED_100baseT_Full;
1801 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1da177e4
LT		 1802 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1803 SPEED_100 : SPEED_10;
1804 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1805 DUPLEX_FULL : DUPLEX_HALF;
1806 cmd->port = 0;
1807 cmd->phy_address = bp->phy_addr;
1808 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1809 XCVR_INTERNAL : XCVR_EXTERNAL;
1810 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1811 AUTONEG_DISABLE : AUTONEG_ENABLE;
47b9c3b1
GZ		 1812 if (cmd->autoneg == AUTONEG_ENABLE)
1813 cmd->advertising |= ADVERTISED_Autoneg;
1814 if (!netif_running(dev)){
1815 cmd->speed = 0;
1816 cmd->duplex = 0xff;
1817 }
1da177e4
LT		 1818 cmd->maxtxpkt = 0;
1819 cmd->maxrxpkt = 0;
1820 return 0;
1821}
1822
1823static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1824{
1825 struct b44 *bp = netdev_priv(dev);
1826
1da177e4
LT		 1827 /* We do not support gigabit. */
1828 if (cmd->autoneg == AUTONEG_ENABLE) {
1829 if (cmd->advertising &
1830 (ADVERTISED_1000baseT_Half |
1831 ADVERTISED_1000baseT_Full))
1832 return -EINVAL;
1833 } else if ((cmd->speed != SPEED_100 &&
1834 cmd->speed != SPEED_10) ||
1835 (cmd->duplex != DUPLEX_HALF &&
1836 cmd->duplex != DUPLEX_FULL)) {
1837 return -EINVAL;
1838 }
1839
1840 spin_lock_irq(&bp->lock);
1841
1842 if (cmd->autoneg == AUTONEG_ENABLE) {
47b9c3b1
GZ		 1843 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1844 B44_FLAG_100_BASE_T |
1845 B44_FLAG_FULL_DUPLEX |
1846 B44_FLAG_ADV_10HALF |
1da177e4
LT		 1847 B44_FLAG_ADV_10FULL |
1848 B44_FLAG_ADV_100HALF |
1849 B44_FLAG_ADV_100FULL);
47b9c3b1
GZ		 1850 if (cmd->advertising == 0) {
1851 bp->flags |= (B44_FLAG_ADV_10HALF |
1852 B44_FLAG_ADV_10FULL |
1853 B44_FLAG_ADV_100HALF |
1854 B44_FLAG_ADV_100FULL);
1855 } else {
1856 if (cmd->advertising & ADVERTISED_10baseT_Half)
1857 bp->flags |= B44_FLAG_ADV_10HALF;
1858 if (cmd->advertising & ADVERTISED_10baseT_Full)
1859 bp->flags |= B44_FLAG_ADV_10FULL;
1860 if (cmd->advertising & ADVERTISED_100baseT_Half)
1861 bp->flags |= B44_FLAG_ADV_100HALF;
1862 if (cmd->advertising & ADVERTISED_100baseT_Full)
1863 bp->flags |= B44_FLAG_ADV_100FULL;
1864 }
1da177e4
LT		 1865 } else {
1866 bp->flags |= B44_FLAG_FORCE_LINK;
47b9c3b1 1867 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1da177e4
LT		 1868 if (cmd->speed == SPEED_100)
1869 bp->flags |= B44_FLAG_100_BASE_T;
1870 if (cmd->duplex == DUPLEX_FULL)
1871 bp->flags |= B44_FLAG_FULL_DUPLEX;
1872 }
1873
47b9c3b1
GZ		 1874 if (netif_running(dev))
1875 b44_setup_phy(bp);
1da177e4
LT		 1876
1877 spin_unlock_irq(&bp->lock);
1878
1879 return 0;
1880}
1881
1882static void b44_get_ringparam(struct net_device *dev,
1883 struct ethtool_ringparam *ering)
1884{
1885 struct b44 *bp = netdev_priv(dev);
1886
1887 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1888 ering->rx_pending = bp->rx_pending;
1889
1890 /* XXX ethtool lacks a tx_max_pending, oops... */
1891}
1892
1893static int b44_set_ringparam(struct net_device *dev,
1894 struct ethtool_ringparam *ering)
1895{
1896 struct b44 *bp = netdev_priv(dev);
1897
1898 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1899 (ering->rx_mini_pending != 0) ||
1900 (ering->rx_jumbo_pending != 0) ||
1901 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1902 return -EINVAL;
1903
1904 spin_lock_irq(&bp->lock);
1905
1906 bp->rx_pending = ering->rx_pending;
1907 bp->tx_pending = ering->tx_pending;
1908
1909 b44_halt(bp);
1910 b44_init_rings(bp);
5fc7d61a 1911 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1912 netif_wake_queue(bp->dev);
1913 spin_unlock_irq(&bp->lock);
1914
1915 b44_enable_ints(bp);
10badc21 1916
1da177e4
LT		 1917 return 0;
1918}
1919
1920static void b44_get_pauseparam(struct net_device *dev,
1921 struct ethtool_pauseparam *epause)
1922{
1923 struct b44 *bp = netdev_priv(dev);
1924
1925 epause->autoneg =
1926 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1927 epause->rx_pause =
1928 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1929 epause->tx_pause =
1930 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1931}
1932
1933static int b44_set_pauseparam(struct net_device *dev,
1934 struct ethtool_pauseparam *epause)
1935{
1936 struct b44 *bp = netdev_priv(dev);
1937
1938 spin_lock_irq(&bp->lock);
1939 if (epause->autoneg)
1940 bp->flags |= B44_FLAG_PAUSE_AUTO;
1941 else
1942 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1943 if (epause->rx_pause)
1944 bp->flags |= B44_FLAG_RX_PAUSE;
1945 else
1946 bp->flags &= ~B44_FLAG_RX_PAUSE;
1947 if (epause->tx_pause)
1948 bp->flags |= B44_FLAG_TX_PAUSE;
1949 else
1950 bp->flags &= ~B44_FLAG_TX_PAUSE;
1951 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1952 b44_halt(bp);
1953 b44_init_rings(bp);
5fc7d61a 1954 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1955 } else {
1956 __b44_set_flow_ctrl(bp, bp->flags);
1957 }
1958 spin_unlock_irq(&bp->lock);
1959
1960 b44_enable_ints(bp);
10badc21 1961
1da177e4
LT		 1962 return 0;
1963}
1964
3353930d
FR		 1965static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1966{
1967 switch(stringset) {
1968 case ETH_SS_STATS:
1969 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1970 break;
1971 }
1972}
1973
b9f2c044 1974static int b44_get_sset_count(struct net_device *dev, int sset)
3353930d 1975{
b9f2c044
JG		 1976 switch (sset) {
1977 case ETH_SS_STATS:
1978 return ARRAY_SIZE(b44_gstrings);
1979 default:
1980 return -EOPNOTSUPP;
1981 }
3353930d
FR		 1982}
1983
1984static void b44_get_ethtool_stats(struct net_device *dev,
1985 struct ethtool_stats *stats, u64 *data)
1986{
1987 struct b44 *bp = netdev_priv(dev);
1988 u32 *val = &bp->hw_stats.tx_good_octets;
1989 u32 i;
1990
1991 spin_lock_irq(&bp->lock);
1992
1993 b44_stats_update(bp);
1994
1995 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
1996 *data++ = *val++;
1997
1998 spin_unlock_irq(&bp->lock);
1999}
2000
52cafd96
GZ		 2001static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2002{
2003 struct b44 *bp = netdev_priv(dev);
2004
2005 wol->supported = WAKE_MAGIC;
2006 if (bp->flags & B44_FLAG_WOL_ENABLE)
2007 wol->wolopts = WAKE_MAGIC;
2008 else
2009 wol->wolopts = 0;
2010 memset(&wol->sopass, 0, sizeof(wol->sopass));
2011}
2012
2013static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2014{
2015 struct b44 *bp = netdev_priv(dev);
2016
2017 spin_lock_irq(&bp->lock);
2018 if (wol->wolopts & WAKE_MAGIC)
2019 bp->flags |= B44_FLAG_WOL_ENABLE;
2020 else
2021 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2022 spin_unlock_irq(&bp->lock);
2023
2024 return 0;
2025}
2026
7282d491 2027static const struct ethtool_ops b44_ethtool_ops = {
1da177e4
LT		 2028 .get_drvinfo = b44_get_drvinfo,
2029 .get_settings = b44_get_settings,
2030 .set_settings = b44_set_settings,
2031 .nway_reset = b44_nway_reset,
2032 .get_link = ethtool_op_get_link,
52cafd96
GZ		 2033 .get_wol = b44_get_wol,
2034 .set_wol = b44_set_wol,
1da177e4
LT		 2035 .get_ringparam = b44_get_ringparam,
2036 .set_ringparam = b44_set_ringparam,
2037 .get_pauseparam = b44_get_pauseparam,
2038 .set_pauseparam = b44_set_pauseparam,
2039 .get_msglevel = b44_get_msglevel,
2040 .set_msglevel = b44_set_msglevel,
3353930d 2041 .get_strings = b44_get_strings,
b9f2c044 2042 .get_sset_count = b44_get_sset_count,
3353930d 2043 .get_ethtool_stats = b44_get_ethtool_stats,
1da177e4
LT		 2044};
2045
2046static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2047{
2048 struct mii_ioctl_data *data = if_mii(ifr);
2049 struct b44 *bp = netdev_priv(dev);
3410572d
FR		 2050 int err = -EINVAL;
2051
2052 if (!netif_running(dev))
2053 goto out;
1da177e4
LT		 2054
2055 spin_lock_irq(&bp->lock);
2056 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2057 spin_unlock_irq(&bp->lock);
3410572d 2058out:
1da177e4
LT		 2059 return err;
2060}
2061
1da177e4
LT		 2062static int __devinit b44_get_invariants(struct b44 *bp)
2063{
753f4920
MB		 2064 struct ssb_device *sdev = bp->sdev;
2065 int err = 0;
2066 u8 *addr;
1da177e4 2067
753f4920 2068 bp->dma_offset = ssb_dma_translation(sdev);
1da177e4 2069
753f4920
MB		 2070 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2071 instance > 1) {
458414b2
LF		 2072 addr = sdev->bus->sprom.et1mac;
2073 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
753f4920 2074 } else {
458414b2
LF		 2075 addr = sdev->bus->sprom.et0mac;
2076 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
753f4920 2077 }
5ea79631
MB		 2078 /* Some ROMs have buggy PHY addresses with the high
2079 * bits set (sign extension?). Truncate them to a
2080 * valid PHY address. */
2081 bp->phy_addr &= 0x1F;
2082
753f4920 2083 memcpy(bp->dev->dev_addr, addr, 6);
391fc09a
GZ		 2084
2085 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2fc96fff 2086 pr_err("Invalid MAC address found in EEPROM\n");
391fc09a
GZ		 2087 return -EINVAL;
2088 }
2089
2160de53 2090 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1da177e4 2091
1da177e4
LT		 2092 bp->imask = IMASK_DEF;
2093
10badc21 2094 /* XXX - really required?
1da177e4 2095 bp->flags |= B44_FLAG_BUGGY_TXPTR;
753f4920 2096 */
52cafd96 2097
753f4920
MB		 2098 if (bp->sdev->id.revision >= 7)
2099 bp->flags |= B44_FLAG_B0_ANDLATER;
52cafd96 2100
1da177e4
LT		 2101 return err;
2102}
2103
403413e5
SH		 2104static const struct net_device_ops b44_netdev_ops = {
2105 .ndo_open = b44_open,
2106 .ndo_stop = b44_close,
2107 .ndo_start_xmit = b44_start_xmit,
2108 .ndo_get_stats = b44_get_stats,
2109 .ndo_set_multicast_list = b44_set_rx_mode,
2110 .ndo_set_mac_address = b44_set_mac_addr,
2111 .ndo_validate_addr = eth_validate_addr,
2112 .ndo_do_ioctl = b44_ioctl,
2113 .ndo_tx_timeout = b44_tx_timeout,
2114 .ndo_change_mtu = b44_change_mtu,
2115#ifdef CONFIG_NET_POLL_CONTROLLER
2116 .ndo_poll_controller = b44_poll_controller,
2117#endif
2118};
2119
753f4920
MB		 2120static int __devinit b44_init_one(struct ssb_device *sdev,
2121 const struct ssb_device_id *ent)
1da177e4
LT		 2122{
2123 static int b44_version_printed = 0;
1da177e4
LT		 2124 struct net_device *dev;
2125 struct b44 *bp;
0795af57 2126 int err;
1da177e4 2127
753f4920
MB		 2128 instance++;
2129
1da177e4 2130 if (b44_version_printed++ == 0)
2fc96fff 2131 pr_info("%s", version);
1da177e4 2132
1da177e4
LT		 2133
2134 dev = alloc_etherdev(sizeof(*bp));
2135 if (!dev) {
2fc96fff 2136 dev_err(sdev->dev, "Etherdev alloc failed, aborting\n");
1da177e4 2137 err = -ENOMEM;
753f4920 2138 goto out;
1da177e4
LT		 2139 }
2140
753f4920 2141 SET_NETDEV_DEV(dev, sdev->dev);
1da177e4
LT		 2142
2143 /* No interesting netdevice features in this card... */
2144 dev->features |= 0;
2145
2146 bp = netdev_priv(dev);
753f4920 2147 bp->sdev = sdev;
1da177e4 2148 bp->dev = dev;
a58c891a 2149 bp->force_copybreak = 0;
874a6214
FR		 2150
2151 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1da177e4
LT		 2152
2153 spin_lock_init(&bp->lock);
2154
1da177e4
LT		 2155 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2156 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2157
403413e5 2158 dev->netdev_ops = &b44_netdev_ops;
bea3348e 2159 netif_napi_add(dev, &bp->napi, b44_poll, 64);
1da177e4 2160 dev->watchdog_timeo = B44_TX_TIMEOUT;
753f4920 2161 dev->irq = sdev->irq;
1da177e4
LT		 2162 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2163
c35ca399
SH		 2164 netif_carrier_off(dev);
2165
753f4920
MB		 2166 err = ssb_bus_powerup(sdev->bus, 0);
2167 if (err) {
2168 dev_err(sdev->dev,
2169 "Failed to powerup the bus\n");
2170 goto err_out_free_dev;
2171 }
39a6f4bc
FT		 2172
2173 if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
2174 dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
753f4920 2175 dev_err(sdev->dev,
2fc96fff 2176 "Required 30BIT DMA mask unsupported by the system\n");
753f4920
MB		 2177 goto err_out_powerdown;
2178 }
39a6f4bc 2179
1da177e4
LT		 2180 err = b44_get_invariants(bp);
2181 if (err) {
753f4920 2182 dev_err(sdev->dev,
2fc96fff 2183 "Problem fetching invariants of chip, aborting\n");
753f4920 2184 goto err_out_powerdown;
1da177e4
LT		 2185 }
2186
2187 bp->mii_if.dev = dev;
2188 bp->mii_if.mdio_read = b44_mii_read;
2189 bp->mii_if.mdio_write = b44_mii_write;
2190 bp->mii_if.phy_id = bp->phy_addr;
2191 bp->mii_if.phy_id_mask = 0x1f;
2192 bp->mii_if.reg_num_mask = 0x1f;
2193
2194 /* By default, advertise all speed/duplex settings. */
2195 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2196 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2197
2198 /* By default, auto-negotiate PAUSE. */
2199 bp->flags |= B44_FLAG_PAUSE_AUTO;
2200
2201 err = register_netdev(dev);
2202 if (err) {
2fc96fff 2203 dev_err(sdev->dev, "Cannot register net device, aborting\n");
753f4920 2204 goto err_out_powerdown;
1da177e4
LT		 2205 }
2206
753f4920 2207 ssb_set_drvdata(sdev, dev);
1da177e4 2208
10badc21 2209 /* Chip reset provides power to the b44 MAC & PCI cores, which
5c513129 2210 * is necessary for MAC register access.
10badc21 2211 */
fedb0eef 2212 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5c513129 2213
8850dce1
HM		 2214 /* do a phy reset to test if there is an active phy */
2215 if (b44_phy_reset(bp) < 0)
2216 bp->phy_addr = B44_PHY_ADDR_NO_PHY;
2217
2fc96fff
JP		 2218 netdev_info(dev, "Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2219 dev->dev_addr);
1da177e4
LT		 2220
2221 return 0;
2222
753f4920
MB		 2223err_out_powerdown:
2224 ssb_bus_may_powerdown(sdev->bus);
1da177e4
LT		 2225
2226err_out_free_dev:
2227 free_netdev(dev);
2228
753f4920 2229out:
1da177e4
LT		 2230 return err;
2231}
2232
753f4920 2233static void __devexit b44_remove_one(struct ssb_device *sdev)
1da177e4 2234{
753f4920 2235 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2236
874a6214 2237 unregister_netdev(dev);
e92aa634 2238 ssb_device_disable(sdev, 0);
753f4920 2239 ssb_bus_may_powerdown(sdev->bus);
874a6214 2240 free_netdev(dev);
fedb0eef 2241 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
753f4920 2242 ssb_set_drvdata(sdev, NULL);
1da177e4
LT		 2243}
2244
753f4920 2245static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
1da177e4 2246{
753f4920 2247 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4
LT		 2248 struct b44 *bp = netdev_priv(dev);
2249
753f4920
MB		 2250 if (!netif_running(dev))
2251 return 0;
1da177e4
LT		 2252
2253 del_timer_sync(&bp->timer);
2254
10badc21 2255 spin_lock_irq(&bp->lock);
1da177e4
LT		 2256
2257 b44_halt(bp);
10badc21 2258 netif_carrier_off(bp->dev);
1da177e4
LT		 2259 netif_device_detach(bp->dev);
2260 b44_free_rings(bp);
2261
2262 spin_unlock_irq(&bp->lock);
46e17853
PM		 2263
2264 free_irq(dev->irq, dev);
52cafd96 2265 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 2266 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 2267 b44_setup_wol(bp);
2268 }
753f4920 2269
fedb0eef 2270 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
1da177e4
LT		 2271 return 0;
2272}
2273
753f4920 2274static int b44_resume(struct ssb_device *sdev)
1da177e4 2275{
753f4920 2276 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2277 struct b44 *bp = netdev_priv(dev);
90afd0e5 2278 int rc = 0;
1da177e4 2279
753f4920 2280 rc = ssb_bus_powerup(sdev->bus, 0);
90afd0e5 2281 if (rc) {
753f4920
MB		 2282 dev_err(sdev->dev,
2283 "Failed to powerup the bus\n");
90afd0e5
DM		 2284 return rc;
2285 }
2286
1da177e4
LT		 2287 if (!netif_running(dev))
2288 return 0;
2289
90afd0e5
DM		 2290 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2291 if (rc) {
2fc96fff 2292 netdev_err(dev, "request_irq failed\n");
90afd0e5
DM		 2293 return rc;
2294 }
46e17853 2295
1da177e4
LT		 2296 spin_lock_irq(&bp->lock);
2297
2298 b44_init_rings(bp);
5fc7d61a 2299 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 2300 netif_device_attach(bp->dev);
2301 spin_unlock_irq(&bp->lock);
2302
1da177e4 2303 b44_enable_ints(bp);
d9e2d185 2304 netif_wake_queue(dev);
a72a8179
SH		 2305
2306 mod_timer(&bp->timer, jiffies + 1);
2307
1da177e4
LT		 2308 return 0;
2309}
2310
753f4920 2311static struct ssb_driver b44_ssb_driver = {
1da177e4 2312 .name = DRV_MODULE_NAME,
753f4920 2313 .id_table = b44_ssb_tbl,
1da177e4
LT		 2314 .probe = b44_init_one,
2315 .remove = __devexit_p(b44_remove_one),
753f4920
MB		 2316 .suspend = b44_suspend,
2317 .resume = b44_resume,
1da177e4
LT		 2318};
2319
753f4920
MB		 2320static inline int b44_pci_init(void)
2321{
2322 int err = 0;
2323#ifdef CONFIG_B44_PCI
2324 err = ssb_pcihost_register(&b44_pci_driver);
2325#endif
2326 return err;
2327}
2328
2329static inline void b44_pci_exit(void)
2330{
2331#ifdef CONFIG_B44_PCI
2332 ssb_pcihost_unregister(&b44_pci_driver);
2333#endif
2334}
2335
1da177e4
LT		 2336static int __init b44_init(void)
2337{
9f38c636 2338 unsigned int dma_desc_align_size = dma_get_cache_alignment();
753f4920 2339 int err;
9f38c636
JL		 2340
2341 /* Setup paramaters for syncing RX/TX DMA descriptors */
22d4d771 2342 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
9f38c636 2343
753f4920
MB		 2344 err = b44_pci_init();
2345 if (err)
2346 return err;
2347 err = ssb_driver_register(&b44_ssb_driver);
2348 if (err)
2349 b44_pci_exit();
2350 return err;
1da177e4
LT		 2351}
2352
2353static void __exit b44_cleanup(void)
2354{
753f4920
MB		 2355 ssb_driver_unregister(&b44_ssb_driver);
2356 b44_pci_exit();
1da177e4
LT		 2357}
2358
2359module_init(b44_init);
2360module_exit(b44_cleanup);
2361
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