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MIPS: au1000_eth: Get ethernet address from platform_data
[net-next-2.6.git] / drivers / net / au1000_eth.c
CommitLineData
1da177e4
LT
1/*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
89be0501 5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
1da177e4
LT
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
6aa20a22
JG
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
1da177e4 11 * ioctls (SIOCGMIIPHY)
0638dec0
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12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
1da177e4
LT
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
32 *
33 * ########################################################################
34 *
6aa20a22 35 *
1da177e4 36 */
bc36b428 37#include <linux/capability.h>
d791c2bd 38#include <linux/dma-mapping.h>
1da177e4
LT
39#include <linux/module.h>
40#include <linux/kernel.h>
1da177e4
LT
41#include <linux/string.h>
42#include <linux/timer.h>
43#include <linux/errno.h>
44#include <linux/in.h>
45#include <linux/ioport.h>
46#include <linux/bitops.h>
47#include <linux/slab.h>
48#include <linux/interrupt.h>
1da177e4
LT
49#include <linux/init.h>
50#include <linux/netdevice.h>
51#include <linux/etherdevice.h>
52#include <linux/ethtool.h>
53#include <linux/mii.h>
54#include <linux/skbuff.h>
55#include <linux/delay.h>
8cd35da0 56#include <linux/crc32.h>
0638dec0 57#include <linux/phy.h>
bd2302c2 58#include <linux/platform_device.h>
25b31cb1
YY
59
60#include <asm/cpu.h>
1da177e4
LT
61#include <asm/mipsregs.h>
62#include <asm/irq.h>
63#include <asm/io.h>
64#include <asm/processor.h>
65
25b31cb1 66#include <au1000.h>
bd2302c2 67#include <au1xxx_eth.h>
25b31cb1
YY
68#include <prom.h>
69
1da177e4
LT
70#include "au1000_eth.h"
71
72#ifdef AU1000_ETH_DEBUG
73static int au1000_debug = 5;
74#else
75static int au1000_debug = 3;
76#endif
77
7cd2e6e3
FF
78#define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK)
81
89be0501 82#define DRV_NAME "au1000_eth"
8020eb82 83#define DRV_VERSION "1.7"
1da177e4
LT
84#define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
85#define DRV_DESC "Au1xxx on-chip Ethernet driver"
86
87MODULE_AUTHOR(DRV_AUTHOR);
88MODULE_DESCRIPTION(DRV_DESC);
89MODULE_LICENSE("GPL");
13130c7a 90MODULE_VERSION(DRV_VERSION);
1da177e4 91
1da177e4
LT
92/*
93 * Theory of operation
94 *
6aa20a22
JG
95 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
96 * There are four receive and four transmit descriptors. These
97 * descriptors are not in memory; rather, they are just a set of
1da177e4
LT
98 * hardware registers.
99 *
100 * Since the Au1000 has a coherent data cache, the receive and
6aa20a22 101 * transmit buffers are allocated from the KSEG0 segment. The
1da177e4
LT
102 * hardware registers, however, are still mapped at KSEG1 to
103 * make sure there's no out-of-order writes, and that all writes
104 * complete immediately.
105 */
106
1da177e4
LT
107struct au1000_private *au_macs[NUM_ETH_INTERFACES];
108
0638dec0
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109/*
110 * board-specific configurations
111 *
112 * PHY detection algorithm
113 *
bd2302c2 114 * If phy_static_config is undefined, the PHY setup is
0638dec0
HVR
115 * autodetected:
116 *
117 * mii_probe() first searches the current MAC's MII bus for a PHY,
bd2302c2 118 * selecting the first (or last, if phy_search_highest_addr is
0638dec0
HVR
119 * defined) PHY address not already claimed by another netdev.
120 *
121 * If nothing was found that way when searching for the 2nd ethernet
bd2302c2 122 * controller's PHY and phy1_search_mac0 is defined, then
0638dec0
HVR
123 * the first MII bus is searched as well for an unclaimed PHY; this is
124 * needed in case of a dual-PHY accessible only through the MAC0's MII
125 * bus.
126 *
127 * Finally, if no PHY is found, then the corresponding ethernet
128 * controller is not registered to the network subsystem.
1da177e4
LT
129 */
130
bd2302c2 131/* autodetection defaults: phy1_search_mac0 */
1da177e4 132
0638dec0
HVR
133/* static PHY setup
134 *
135 * most boards PHY setup should be detectable properly with the
136 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
137 * you have a switch attached, or want to use the PHY's interrupt
138 * notification capabilities) you can provide a static PHY
139 * configuration here
140 *
141 * IRQs may only be set, if a PHY address was configured
142 * If a PHY address is given, also a bus id is required to be set
143 *
144 * ps: make sure the used irqs are configured properly in the board
145 * specific irq-map
146 */
1da177e4 147
eb049630 148static void au1000_enable_mac(struct net_device *dev, int force_reset)
5ef3041e
FF
149{
150 unsigned long flags;
151 struct au1000_private *aup = netdev_priv(dev);
152
153 spin_lock_irqsave(&aup->lock, flags);
154
155 if(force_reset || (!aup->mac_enabled)) {
156 *aup->enable = MAC_EN_CLOCK_ENABLE;
157 au_sync_delay(2);
158 *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
159 | MAC_EN_CLOCK_ENABLE);
160 au_sync_delay(2);
161
162 aup->mac_enabled = 1;
163 }
164
165 spin_unlock_irqrestore(&aup->lock, flags);
166}
167
0638dec0
HVR
168/*
169 * MII operations
170 */
1210dde7 171static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
1da177e4 172{
454d7c9b 173 struct au1000_private *aup = netdev_priv(dev);
0638dec0
HVR
174 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
175 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT
176 u32 timedout = 20;
177 u32 mii_control;
178
1da177e4
LT
179 while (*mii_control_reg & MAC_MII_BUSY) {
180 mdelay(1);
181 if (--timedout == 0) {
5368c726 182 netdev_err(dev, "read_MII busy timeout!!\n");
1da177e4
LT
183 return -1;
184 }
185 }
186
6aa20a22 187 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 188 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
1da177e4
LT
189
190 *mii_control_reg = mii_control;
191
192 timedout = 20;
193 while (*mii_control_reg & MAC_MII_BUSY) {
194 mdelay(1);
195 if (--timedout == 0) {
5368c726 196 netdev_err(dev, "mdio_read busy timeout!!\n");
1da177e4
LT
197 return -1;
198 }
199 }
200 return (int)*mii_data_reg;
201}
202
1210dde7
AB
203static void au1000_mdio_write(struct net_device *dev, int phy_addr,
204 int reg, u16 value)
1da177e4 205{
454d7c9b 206 struct au1000_private *aup = netdev_priv(dev);
0638dec0
HVR
207 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
208 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT
209 u32 timedout = 20;
210 u32 mii_control;
211
1da177e4
LT
212 while (*mii_control_reg & MAC_MII_BUSY) {
213 mdelay(1);
214 if (--timedout == 0) {
5368c726 215 netdev_err(dev, "mdio_write busy timeout!!\n");
1da177e4
LT
216 return;
217 }
218 }
219
6aa20a22 220 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 221 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
1da177e4
LT
222
223 *mii_data_reg = value;
224 *mii_control_reg = mii_control;
225}
226
1210dde7 227static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
0638dec0
HVR
228{
229 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
230 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
231 struct net_device *const dev = bus->priv;
232
eb049630 233 au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
0638dec0 234 * mii_bus is enabled */
1210dde7 235 return au1000_mdio_read(dev, phy_addr, regnum);
0638dec0 236}
1da177e4 237
1210dde7
AB
238static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
239 u16 value)
1da177e4 240{
0638dec0 241 struct net_device *const dev = bus->priv;
1da177e4 242
eb049630 243 au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
0638dec0 244 * mii_bus is enabled */
1210dde7 245 au1000_mdio_write(dev, phy_addr, regnum, value);
0638dec0 246 return 0;
1da177e4
LT
247}
248
1210dde7 249static int au1000_mdiobus_reset(struct mii_bus *bus)
1da177e4 250{
0638dec0 251 struct net_device *const dev = bus->priv;
1da177e4 252
eb049630 253 au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
0638dec0
HVR
254 * mii_bus is enabled */
255 return 0;
256}
1da177e4 257
eb049630 258static void au1000_hard_stop(struct net_device *dev)
5ef3041e
FF
259{
260 struct au1000_private *aup = netdev_priv(dev);
261
5368c726 262 netif_dbg(aup, drv, dev, "hard stop\n");
5ef3041e
FF
263
264 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
265 au_sync_delay(10);
266}
267
eb049630 268static void au1000_enable_rx_tx(struct net_device *dev)
5ef3041e
FF
269{
270 struct au1000_private *aup = netdev_priv(dev);
271
5368c726 272 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
5ef3041e
FF
273
274 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
275 au_sync_delay(10);
276}
277
278static void
279au1000_adjust_link(struct net_device *dev)
280{
281 struct au1000_private *aup = netdev_priv(dev);
282 struct phy_device *phydev = aup->phy_dev;
283 unsigned long flags;
284
285 int status_change = 0;
286
287 BUG_ON(!aup->phy_dev);
288
289 spin_lock_irqsave(&aup->lock, flags);
290
291 if (phydev->link && (aup->old_speed != phydev->speed)) {
2cc3c6b1 292 /* speed changed */
5ef3041e 293
2cc3c6b1 294 switch (phydev->speed) {
5ef3041e
FF
295 case SPEED_10:
296 case SPEED_100:
297 break;
298 default:
5368c726
FF
299 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
300 phydev->speed);
5ef3041e
FF
301 break;
302 }
303
304 aup->old_speed = phydev->speed;
305
306 status_change = 1;
307 }
308
309 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
2cc3c6b1 310 /* duplex mode changed */
5ef3041e
FF
311
312 /* switching duplex mode requires to disable rx and tx! */
eb049630 313 au1000_hard_stop(dev);
5ef3041e
FF
314
315 if (DUPLEX_FULL == phydev->duplex)
316 aup->mac->control = ((aup->mac->control
317 | MAC_FULL_DUPLEX)
318 & ~MAC_DISABLE_RX_OWN);
319 else
320 aup->mac->control = ((aup->mac->control
321 & ~MAC_FULL_DUPLEX)
322 | MAC_DISABLE_RX_OWN);
323 au_sync_delay(1);
324
eb049630 325 au1000_enable_rx_tx(dev);
5ef3041e
FF
326 aup->old_duplex = phydev->duplex;
327
328 status_change = 1;
329 }
330
2cc3c6b1
FF
331 if (phydev->link != aup->old_link) {
332 /* link state changed */
5ef3041e
FF
333
334 if (!phydev->link) {
335 /* link went down */
336 aup->old_speed = 0;
337 aup->old_duplex = -1;
338 }
339
340 aup->old_link = phydev->link;
341 status_change = 1;
342 }
343
344 spin_unlock_irqrestore(&aup->lock, flags);
345
346 if (status_change) {
347 if (phydev->link)
5368c726
FF
348 netdev_info(dev, "link up (%d/%s)\n",
349 phydev->speed,
5ef3041e
FF
350 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
351 else
5368c726 352 netdev_info(dev, "link down\n");
5ef3041e
FF
353 }
354}
355
eb049630 356static int au1000_mii_probe (struct net_device *dev)
0638dec0 357{
454d7c9b 358 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR
359 struct phy_device *phydev = NULL;
360
bd2302c2
FF
361 if (aup->phy_static_config) {
362 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
0638dec0 363
bd2302c2
FF
364 if (aup->phy_addr)
365 phydev = aup->mii_bus->phy_map[aup->phy_addr];
366 else
5368c726 367 netdev_info(dev, "using PHY-less setup\n");
0638dec0 368 return 0;
bd2302c2
FF
369 } else {
370 int phy_addr;
371
372 /* find the first (lowest address) PHY on the current MAC's MII bus */
373 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
374 if (aup->mii_bus->phy_map[phy_addr]) {
375 phydev = aup->mii_bus->phy_map[phy_addr];
376 if (!aup->phy_search_highest_addr)
377 break; /* break out with first one found */
378 }
1da177e4 379
bd2302c2
FF
380 if (aup->phy1_search_mac0) {
381 /* try harder to find a PHY */
382 if (!phydev && (aup->mac_id == 1)) {
383 /* no PHY found, maybe we have a dual PHY? */
5368c726 384 dev_info(&dev->dev, ": no PHY found on MAC1, "
bd2302c2 385 "let's see if it's attached to MAC0...\n");
0638dec0 386
bd2302c2
FF
387 /* find the first (lowest address) non-attached PHY on
388 * the MAC0 MII bus */
389 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
390 struct phy_device *const tmp_phydev =
391 aup->mii_bus->phy_map[phy_addr];
0638dec0 392
bd2302c2
FF
393 if (aup->mac_id == 1)
394 break;
0638dec0 395
bd2302c2
FF
396 if (!tmp_phydev)
397 continue; /* no PHY here... */
0638dec0 398
bd2302c2
FF
399 if (tmp_phydev->attached_dev)
400 continue; /* already claimed by MAC0 */
0638dec0 401
bd2302c2
FF
402 phydev = tmp_phydev;
403 break; /* found it */
404 }
405 }
1da177e4
LT
406 }
407 }
1da177e4 408
0638dec0 409 if (!phydev) {
5368c726 410 netdev_err(dev, "no PHY found\n");
1da177e4
LT
411 return -1;
412 }
413
0638dec0 414 /* now we are supposed to have a proper phydev, to attach to... */
0638dec0
HVR
415 BUG_ON(phydev->attached_dev);
416
db1d7bf7
KS
417 phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
418 0, PHY_INTERFACE_MODE_MII);
0638dec0
HVR
419
420 if (IS_ERR(phydev)) {
5368c726 421 netdev_err(dev, "Could not attach to PHY\n");
0638dec0
HVR
422 return PTR_ERR(phydev);
423 }
424
425 /* mask with MAC supported features */
426 phydev->supported &= (SUPPORTED_10baseT_Half
427 | SUPPORTED_10baseT_Full
428 | SUPPORTED_100baseT_Half
429 | SUPPORTED_100baseT_Full
430 | SUPPORTED_Autoneg
431 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
432 | SUPPORTED_MII
433 | SUPPORTED_TP);
434
435 phydev->advertising = phydev->supported;
436
437 aup->old_link = 0;
438 aup->old_speed = 0;
439 aup->old_duplex = -1;
440 aup->phy_dev = phydev;
441
5368c726
FF
442 netdev_info(dev, "attached PHY driver [%s] "
443 "(mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7 444 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1da177e4
LT
445
446 return 0;
447}
448
449
450/*
451 * Buffer allocation/deallocation routines. The buffer descriptor returned
6aa20a22 452 * has the virtual and dma address of a buffer suitable for
1da177e4
LT
453 * both, receive and transmit operations.
454 */
eb049630 455static db_dest_t *au1000_GetFreeDB(struct au1000_private *aup)
1da177e4
LT
456{
457 db_dest_t *pDB;
458 pDB = aup->pDBfree;
459
460 if (pDB) {
461 aup->pDBfree = pDB->pnext;
462 }
463 return pDB;
464}
465
eb049630 466void au1000_ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
1da177e4
LT
467{
468 db_dest_t *pDBfree = aup->pDBfree;
469 if (pDBfree)
470 pDBfree->pnext = pDB;
471 aup->pDBfree = pDB;
472}
473
eb049630 474static void au1000_reset_mac_unlocked(struct net_device *dev)
0638dec0 475{
454d7c9b 476 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR
477 int i;
478
eb049630 479 au1000_hard_stop(dev);
0638dec0
HVR
480
481 *aup->enable = MAC_EN_CLOCK_ENABLE;
482 au_sync_delay(2);
483 *aup->enable = 0;
484 au_sync_delay(2);
485
1da177e4
LT
486 aup->tx_full = 0;
487 for (i = 0; i < NUM_RX_DMA; i++) {
488 /* reset control bits */
489 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
490 }
491 for (i = 0; i < NUM_TX_DMA; i++) {
492 /* reset control bits */
493 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
494 }
0638dec0
HVR
495
496 aup->mac_enabled = 0;
497
1da177e4
LT
498}
499
eb049630 500static void au1000_reset_mac(struct net_device *dev)
0638dec0 501{
454d7c9b 502 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR
503 unsigned long flags;
504
5368c726
FF
505 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
506 (unsigned)aup);
0638dec0
HVR
507
508 spin_lock_irqsave(&aup->lock, flags);
509
eb049630 510 au1000_reset_mac_unlocked (dev);
0638dec0
HVR
511
512 spin_unlock_irqrestore(&aup->lock, flags);
513}
1da177e4 514
6aa20a22 515/*
1da177e4
LT
516 * Setup the receive and transmit "rings". These pointers are the addresses
517 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
518 * these are not descriptors sitting in memory.
519 */
6aa20a22 520static void
eb049630 521au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
1da177e4
LT
522{
523 int i;
524
525 for (i = 0; i < NUM_RX_DMA; i++) {
6aa20a22 526 aup->rx_dma_ring[i] =
1da177e4
LT
527 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
528 }
529 for (i = 0; i < NUM_TX_DMA; i++) {
6aa20a22 530 aup->tx_dma_ring[i] =
1da177e4
LT
531 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
532 }
533}
534
0638dec0
HVR
535/*
536 * ethtool operations
537 */
1da177e4 538
0638dec0 539static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 540{
454d7c9b 541 struct au1000_private *aup = netdev_priv(dev);
1da177e4 542
0638dec0
HVR
543 if (aup->phy_dev)
544 return phy_ethtool_gset(aup->phy_dev, cmd);
1da177e4 545
0638dec0 546 return -EINVAL;
1da177e4
LT
547}
548
0638dec0 549static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 550{
454d7c9b 551 struct au1000_private *aup = netdev_priv(dev);
1da177e4 552
0638dec0
HVR
553 if (!capable(CAP_NET_ADMIN))
554 return -EPERM;
1da177e4 555
0638dec0
HVR
556 if (aup->phy_dev)
557 return phy_ethtool_sset(aup->phy_dev, cmd);
1da177e4 558
0638dec0 559 return -EINVAL;
1da177e4
LT
560}
561
562static void
563au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
564{
454d7c9b 565 struct au1000_private *aup = netdev_priv(dev);
1da177e4
LT
566
567 strcpy(info->driver, DRV_NAME);
568 strcpy(info->version, DRV_VERSION);
569 info->fw_version[0] = '\0';
570 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
571 info->regdump_len = 0;
572}
573
7cd2e6e3
FF
574static void au1000_set_msglevel(struct net_device *dev, u32 value)
575{
576 struct au1000_private *aup = netdev_priv(dev);
577 aup->msg_enable = value;
578}
579
580static u32 au1000_get_msglevel(struct net_device *dev)
581{
582 struct au1000_private *aup = netdev_priv(dev);
583 return aup->msg_enable;
584}
585
7282d491 586static const struct ethtool_ops au1000_ethtool_ops = {
1da177e4
LT
587 .get_settings = au1000_get_settings,
588 .set_settings = au1000_set_settings,
589 .get_drvinfo = au1000_get_drvinfo,
0638dec0 590 .get_link = ethtool_op_get_link,
7cd2e6e3
FF
591 .get_msglevel = au1000_get_msglevel,
592 .set_msglevel = au1000_set_msglevel,
1da177e4
LT
593};
594
5ef3041e
FF
595
596/*
597 * Initialize the interface.
598 *
599 * When the device powers up, the clocks are disabled and the
600 * mac is in reset state. When the interface is closed, we
601 * do the same -- reset the device and disable the clocks to
602 * conserve power. Thus, whenever au1000_init() is called,
603 * the device should already be in reset state.
604 */
605static int au1000_init(struct net_device *dev)
1da177e4 606{
5ef3041e
FF
607 struct au1000_private *aup = netdev_priv(dev);
608 unsigned long flags;
609 int i;
610 u32 control;
89be0501 611
5368c726 612 netif_dbg(aup, hw, dev, "au1000_init\n");
1da177e4 613
5ef3041e 614 /* bring the device out of reset */
eb049630 615 au1000_enable_mac(dev, 1);
89be0501 616
5ef3041e 617 spin_lock_irqsave(&aup->lock, flags);
1da177e4 618
5ef3041e
FF
619 aup->mac->control = 0;
620 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
621 aup->tx_tail = aup->tx_head;
622 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
1da177e4 623
5ef3041e
FF
624 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
625 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
626 dev->dev_addr[1]<<8 | dev->dev_addr[0];
627
628 for (i = 0; i < NUM_RX_DMA; i++) {
629 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
1da177e4 630 }
5ef3041e 631 au_sync();
1da177e4 632
5ef3041e
FF
633 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
634#ifndef CONFIG_CPU_LITTLE_ENDIAN
635 control |= MAC_BIG_ENDIAN;
636#endif
637 if (aup->phy_dev) {
638 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
639 control |= MAC_FULL_DUPLEX;
640 else
641 control |= MAC_DISABLE_RX_OWN;
642 } else { /* PHY-less op, assume full-duplex */
643 control |= MAC_FULL_DUPLEX;
1da177e4
LT
644 }
645
5ef3041e
FF
646 aup->mac->control = control;
647 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
648 au_sync();
1da177e4 649
5ef3041e
FF
650 spin_unlock_irqrestore(&aup->lock, flags);
651 return 0;
652}
1da177e4 653
eb049630 654static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
5ef3041e 655{
5ef3041e 656 struct net_device_stats *ps = &dev->stats;
1da177e4 657
5ef3041e
FF
658 ps->rx_packets++;
659 if (status & RX_MCAST_FRAME)
660 ps->multicast++;
1da177e4 661
5ef3041e
FF
662 if (status & RX_ERROR) {
663 ps->rx_errors++;
664 if (status & RX_MISSED_FRAME)
665 ps->rx_missed_errors++;
4989ccb2 666 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
5ef3041e
FF
667 ps->rx_length_errors++;
668 if (status & RX_CRC_ERROR)
669 ps->rx_crc_errors++;
670 if (status & RX_COLL)
671 ps->collisions++;
2cc3c6b1 672 } else
5ef3041e 673 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
298cf9be 674
1da177e4
LT
675}
676
6aa20a22 677/*
5ef3041e 678 * Au1000 receive routine.
1da177e4 679 */
5ef3041e 680static int au1000_rx(struct net_device *dev)
1da177e4 681{
454d7c9b 682 struct au1000_private *aup = netdev_priv(dev);
5ef3041e
FF
683 struct sk_buff *skb;
684 volatile rx_dma_t *prxd;
685 u32 buff_stat, status;
686 db_dest_t *pDB;
687 u32 frmlen;
1da177e4 688
5368c726 689 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
1da177e4 690
5ef3041e
FF
691 prxd = aup->rx_dma_ring[aup->rx_head];
692 buff_stat = prxd->buff_stat;
693 while (buff_stat & RX_T_DONE) {
694 status = prxd->status;
695 pDB = aup->rx_db_inuse[aup->rx_head];
eb049630 696 au1000_update_rx_stats(dev, status);
5ef3041e 697 if (!(status & RX_ERROR)) {
1da177e4 698
5ef3041e
FF
699 /* good frame */
700 frmlen = (status & RX_FRAME_LEN_MASK);
701 frmlen -= 4; /* Remove FCS */
702 skb = dev_alloc_skb(frmlen + 2);
703 if (skb == NULL) {
5368c726 704 netdev_err(dev, "Memory squeeze, dropping packet.\n");
5ef3041e
FF
705 dev->stats.rx_dropped++;
706 continue;
707 }
708 skb_reserve(skb, 2); /* 16 byte IP header align */
709 skb_copy_to_linear_data(skb,
710 (unsigned char *)pDB->vaddr, frmlen);
711 skb_put(skb, frmlen);
712 skb->protocol = eth_type_trans(skb, dev);
713 netif_rx(skb); /* pass the packet to upper layers */
2cc3c6b1 714 } else {
5ef3041e
FF
715 if (au1000_debug > 4) {
716 if (status & RX_MISSED_FRAME)
717 printk("rx miss\n");
718 if (status & RX_WDOG_TIMER)
719 printk("rx wdog\n");
720 if (status & RX_RUNT)
721 printk("rx runt\n");
722 if (status & RX_OVERLEN)
723 printk("rx overlen\n");
724 if (status & RX_COLL)
725 printk("rx coll\n");
726 if (status & RX_MII_ERROR)
727 printk("rx mii error\n");
728 if (status & RX_CRC_ERROR)
729 printk("rx crc error\n");
730 if (status & RX_LEN_ERROR)
731 printk("rx len error\n");
732 if (status & RX_U_CNTRL_FRAME)
733 printk("rx u control frame\n");
5ef3041e
FF
734 }
735 }
736 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
737 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
738 au_sync();
1da177e4 739
5ef3041e
FF
740 /* next descriptor */
741 prxd = aup->rx_dma_ring[aup->rx_head];
742 buff_stat = prxd->buff_stat;
1da177e4 743 }
1da177e4
LT
744 return 0;
745}
746
eb049630 747static void au1000_update_tx_stats(struct net_device *dev, u32 status)
1da177e4 748{
454d7c9b 749 struct au1000_private *aup = netdev_priv(dev);
5ef3041e 750 struct net_device_stats *ps = &dev->stats;
0638dec0 751
5ef3041e
FF
752 if (status & TX_FRAME_ABORTED) {
753 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
754 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
755 /* any other tx errors are only valid
756 * in half duplex mode */
757 ps->tx_errors++;
758 ps->tx_aborted_errors++;
759 }
2cc3c6b1 760 } else {
5ef3041e
FF
761 ps->tx_errors++;
762 ps->tx_aborted_errors++;
763 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
764 ps->tx_carrier_errors++;
765 }
766 }
767}
0638dec0 768
5ef3041e
FF
769/*
770 * Called from the interrupt service routine to acknowledge
771 * the TX DONE bits. This is a must if the irq is setup as
772 * edge triggered.
773 */
774static void au1000_tx_ack(struct net_device *dev)
775{
776 struct au1000_private *aup = netdev_priv(dev);
777 volatile tx_dma_t *ptxd;
0638dec0 778
5ef3041e 779 ptxd = aup->tx_dma_ring[aup->tx_tail];
0638dec0 780
5ef3041e 781 while (ptxd->buff_stat & TX_T_DONE) {
eb049630 782 au1000_update_tx_stats(dev, ptxd->status);
5ef3041e
FF
783 ptxd->buff_stat &= ~TX_T_DONE;
784 ptxd->len = 0;
785 au_sync();
0638dec0 786
5ef3041e
FF
787 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
788 ptxd = aup->tx_dma_ring[aup->tx_tail];
0638dec0 789
5ef3041e
FF
790 if (aup->tx_full) {
791 aup->tx_full = 0;
792 netif_wake_queue(dev);
793 }
1da177e4 794 }
5ef3041e 795}
1da177e4 796
5ef3041e
FF
797/*
798 * Au1000 interrupt service routine.
799 */
800static irqreturn_t au1000_interrupt(int irq, void *dev_id)
801{
802 struct net_device *dev = dev_id;
1da177e4 803
5ef3041e
FF
804 /* Handle RX interrupts first to minimize chance of overrun */
805
806 au1000_rx(dev);
807 au1000_tx_ack(dev);
808 return IRQ_RETVAL(1);
1da177e4
LT
809}
810
811static int au1000_open(struct net_device *dev)
812{
813 int retval;
454d7c9b 814 struct au1000_private *aup = netdev_priv(dev);
1da177e4 815
5368c726 816 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
1da177e4 817
2cc3c6b1
FF
818 retval = request_irq(dev->irq, au1000_interrupt, 0,
819 dev->name, dev);
820 if (retval) {
5368c726 821 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
0638dec0
HVR
822 return retval;
823 }
824
2cc3c6b1
FF
825 retval = au1000_init(dev);
826 if (retval) {
5368c726 827 netdev_err(dev, "error in au1000_init\n");
1da177e4
LT
828 free_irq(dev->irq, dev);
829 return retval;
830 }
1da177e4 831
0638dec0
HVR
832 if (aup->phy_dev) {
833 /* cause the PHY state machine to schedule a link state check */
834 aup->phy_dev->state = PHY_CHANGELINK;
835 phy_start(aup->phy_dev);
1da177e4
LT
836 }
837
0638dec0 838 netif_start_queue(dev);
1da177e4 839
5368c726 840 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
1da177e4
LT
841
842 return 0;
843}
844
845static int au1000_close(struct net_device *dev)
846{
0638dec0 847 unsigned long flags;
454d7c9b 848 struct au1000_private *const aup = netdev_priv(dev);
1da177e4 849
5368c726 850 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
1da177e4 851
0638dec0
HVR
852 if (aup->phy_dev)
853 phy_stop(aup->phy_dev);
1da177e4
LT
854
855 spin_lock_irqsave(&aup->lock, flags);
0638dec0 856
eb049630 857 au1000_reset_mac_unlocked (dev);
0638dec0 858
1da177e4
LT
859 /* stop the device */
860 netif_stop_queue(dev);
861
862 /* disable the interrupt */
863 free_irq(dev->irq, dev);
864 spin_unlock_irqrestore(&aup->lock, flags);
865
866 return 0;
867}
868
1da177e4
LT
869/*
870 * Au1000 transmit routine.
871 */
61357325 872static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1da177e4 873{
454d7c9b 874 struct au1000_private *aup = netdev_priv(dev);
09f75cd7 875 struct net_device_stats *ps = &dev->stats;
1da177e4
LT
876 volatile tx_dma_t *ptxd;
877 u32 buff_stat;
878 db_dest_t *pDB;
879 int i;
880
5368c726
FF
881 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
882 (unsigned)aup, skb->len,
1da177e4
LT
883 skb->data, aup->tx_head);
884
885 ptxd = aup->tx_dma_ring[aup->tx_head];
886 buff_stat = ptxd->buff_stat;
887 if (buff_stat & TX_DMA_ENABLE) {
888 /* We've wrapped around and the transmitter is still busy */
889 netif_stop_queue(dev);
890 aup->tx_full = 1;
5b548140 891 return NETDEV_TX_BUSY;
2cc3c6b1 892 } else if (buff_stat & TX_T_DONE) {
eb049630 893 au1000_update_tx_stats(dev, ptxd->status);
1da177e4
LT
894 ptxd->len = 0;
895 }
896
897 if (aup->tx_full) {
898 aup->tx_full = 0;
899 netif_wake_queue(dev);
900 }
901
902 pDB = aup->tx_db_inuse[aup->tx_head];
bd2302c2 903 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1da177e4 904 if (skb->len < ETH_ZLEN) {
2cc3c6b1 905 for (i = skb->len; i < ETH_ZLEN; i++) {
1da177e4
LT
906 ((char *)pDB->vaddr)[i] = 0;
907 }
908 ptxd->len = ETH_ZLEN;
2cc3c6b1 909 } else
5ef3041e 910 ptxd->len = skb->len;
1da177e4 911
5ef3041e
FF
912 ps->tx_packets++;
913 ps->tx_bytes += ptxd->len;
1da177e4 914
5ef3041e
FF
915 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
916 au_sync();
917 dev_kfree_skb(skb);
918 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
6ed10654 919 return NETDEV_TX_OK;
1da177e4
LT
920}
921
1da177e4
LT
922/*
923 * The Tx ring has been full longer than the watchdog timeout
924 * value. The transmitter must be hung?
925 */
926static void au1000_tx_timeout(struct net_device *dev)
927{
5368c726 928 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
eb049630 929 au1000_reset_mac(dev);
1da177e4 930 au1000_init(dev);
1ae5dc34 931 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT
932 netif_wake_queue(dev);
933}
934
d9a92cee 935static void au1000_multicast_list(struct net_device *dev)
1da177e4 936{
454d7c9b 937 struct au1000_private *aup = netdev_priv(dev);
1da177e4 938
5368c726 939 netif_dbg(aup, drv, dev, "au1000_multicast_list: flags=%x\n", dev->flags);
1da177e4
LT
940
941 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
942 aup->mac->control |= MAC_PROMISCUOUS;
1da177e4 943 } else if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf 944 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1da177e4
LT
945 aup->mac->control |= MAC_PASS_ALL_MULTI;
946 aup->mac->control &= ~MAC_PROMISCUOUS;
5368c726 947 netdev_info(dev, "Pass all multicast\n");
1da177e4 948 } else {
22bedad3 949 struct netdev_hw_addr *ha;
1da177e4
LT
950 u32 mc_filter[2]; /* Multicast hash filter */
951
952 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP
953 netdev_for_each_mc_addr(ha, dev)
954 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1da177e4 955 (long *)mc_filter);
1da177e4
LT
956 aup->mac->multi_hash_high = mc_filter[1];
957 aup->mac->multi_hash_low = mc_filter[0];
958 aup->mac->control &= ~MAC_PROMISCUOUS;
959 aup->mac->control |= MAC_HASH_MODE;
960 }
961}
962
1da177e4
LT
963static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
964{
454d7c9b 965 struct au1000_private *aup = netdev_priv(dev);
1da177e4 966
2cc3c6b1
FF
967 if (!netif_running(dev))
968 return -EINVAL;
1da177e4 969
2cc3c6b1
FF
970 if (!aup->phy_dev)
971 return -EINVAL; /* PHY not controllable */
1da177e4 972
0638dec0 973 return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
1da177e4
LT
974}
975
d9a92cee
AB
976static const struct net_device_ops au1000_netdev_ops = {
977 .ndo_open = au1000_open,
978 .ndo_stop = au1000_close,
979 .ndo_start_xmit = au1000_tx,
980 .ndo_set_multicast_list = au1000_multicast_list,
981 .ndo_do_ioctl = au1000_ioctl,
982 .ndo_tx_timeout = au1000_tx_timeout,
983 .ndo_set_mac_address = eth_mac_addr,
984 .ndo_validate_addr = eth_validate_addr,
985 .ndo_change_mtu = eth_change_mtu,
986};
987
bd2302c2 988static int __devinit au1000_probe(struct platform_device *pdev)
5ef3041e 989{
2cc3c6b1 990 static unsigned version_printed;
5ef3041e 991 struct au1000_private *aup = NULL;
bd2302c2 992 struct au1000_eth_platform_data *pd;
5ef3041e
FF
993 struct net_device *dev = NULL;
994 db_dest_t *pDB, *pDBfree;
bd2302c2
FF
995 int irq, i, err = 0;
996 struct resource *base, *macen;
5ef3041e 997
bd2302c2
FF
998 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
999 if (!base) {
5368c726 1000 dev_err(&pdev->dev, "failed to retrieve base register\n");
bd2302c2
FF
1001 err = -ENODEV;
1002 goto out;
1003 }
5ef3041e 1004
bd2302c2
FF
1005 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1006 if (!macen) {
5368c726 1007 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
bd2302c2
FF
1008 err = -ENODEV;
1009 goto out;
1010 }
5ef3041e 1011
bd2302c2
FF
1012 irq = platform_get_irq(pdev, 0);
1013 if (irq < 0) {
5368c726 1014 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
bd2302c2
FF
1015 err = -ENODEV;
1016 goto out;
1017 }
5ef3041e 1018
bd2302c2 1019 if (!request_mem_region(base->start, resource_size(base), pdev->name)) {
5368c726 1020 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
bd2302c2
FF
1021 err = -ENXIO;
1022 goto out;
1023 }
1024
1025 if (!request_mem_region(macen->start, resource_size(macen), pdev->name)) {
5368c726 1026 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
bd2302c2
FF
1027 err = -ENXIO;
1028 goto err_request;
1029 }
5ef3041e
FF
1030
1031 dev = alloc_etherdev(sizeof(struct au1000_private));
1032 if (!dev) {
5368c726 1033 dev_err(&pdev->dev, "alloc_etherdev failed\n");
bd2302c2
FF
1034 err = -ENOMEM;
1035 goto err_alloc;
5ef3041e
FF
1036 }
1037
bd2302c2
FF
1038 SET_NETDEV_DEV(dev, &pdev->dev);
1039 platform_set_drvdata(pdev, dev);
5ef3041e
FF
1040 aup = netdev_priv(dev);
1041
1042 spin_lock_init(&aup->lock);
7cd2e6e3 1043 aup->msg_enable = (au1000_debug < 4 ? AU1000_DEF_MSG_ENABLE : au1000_debug);
5ef3041e
FF
1044
1045 /* Allocate the data buffers */
1046 /* Snooping works fine with eth on all au1xxx */
1047 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1048 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1049 &aup->dma_addr, 0);
1050 if (!aup->vaddr) {
5368c726 1051 dev_err(&pdev->dev, "failed to allocate data buffers\n");
bd2302c2
FF
1052 err = -ENOMEM;
1053 goto err_vaddr;
5ef3041e
FF
1054 }
1055
1056 /* aup->mac is the base address of the MAC's registers */
bd2302c2
FF
1057 aup->mac = (volatile mac_reg_t *)ioremap_nocache(base->start, resource_size(base));
1058 if (!aup->mac) {
5368c726 1059 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
bd2302c2
FF
1060 err = -ENXIO;
1061 goto err_remap1;
1062 }
5ef3041e 1063
bd2302c2
FF
1064 /* Setup some variables for quick register address access */
1065 aup->enable = (volatile u32 *)ioremap_nocache(macen->start, resource_size(macen));
1066 if (!aup->enable) {
5368c726 1067 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
bd2302c2
FF
1068 err = -ENXIO;
1069 goto err_remap2;
1070 }
1071 aup->mac_id = pdev->id;
5ef3041e 1072
f6673653 1073 if (pdev->id == 0)
eb049630 1074 au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
f6673653 1075 else if (pdev->id == 1)
eb049630 1076 au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
5ef3041e 1077
f6673653
ML
1078 /* set a random MAC now in case platform_data doesn't provide one */
1079 random_ether_addr(dev->dev_addr);
5ef3041e
FF
1080
1081 *aup->enable = 0;
1082 aup->mac_enabled = 0;
1083
bd2302c2
FF
1084 pd = pdev->dev.platform_data;
1085 if (!pd) {
5368c726 1086 dev_info(&pdev->dev, "no platform_data passed, PHY search on MAC0\n");
bd2302c2
FF
1087 aup->phy1_search_mac0 = 1;
1088 } else {
f6673653
ML
1089 if (is_valid_ether_addr(pd->mac))
1090 memcpy(dev->dev_addr, pd->mac, 6);
1091
bd2302c2
FF
1092 aup->phy_static_config = pd->phy_static_config;
1093 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1094 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1095 aup->phy_addr = pd->phy_addr;
1096 aup->phy_busid = pd->phy_busid;
1097 aup->phy_irq = pd->phy_irq;
1098 }
1099
1100 if (aup->phy_busid && aup->phy_busid > 0) {
5368c726 1101 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII"
bd2302c2
FF
1102 "bus not supported yet\n");
1103 err = -ENODEV;
1104 goto err_mdiobus_alloc;
1105 }
1106
5ef3041e 1107 aup->mii_bus = mdiobus_alloc();
bd2302c2 1108 if (aup->mii_bus == NULL) {
5368c726 1109 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
bd2302c2
FF
1110 err = -ENOMEM;
1111 goto err_mdiobus_alloc;
1112 }
5ef3041e
FF
1113
1114 aup->mii_bus->priv = dev;
1115 aup->mii_bus->read = au1000_mdiobus_read;
1116 aup->mii_bus->write = au1000_mdiobus_write;
1117 aup->mii_bus->reset = au1000_mdiobus_reset;
1118 aup->mii_bus->name = "au1000_eth_mii";
1119 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
1120 aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
dcbfef82 1121 if (aup->mii_bus->irq == NULL)
1122 goto err_out;
1123
2cc3c6b1 1124 for (i = 0; i < PHY_MAX_ADDR; ++i)
5ef3041e 1125 aup->mii_bus->irq[i] = PHY_POLL;
5ef3041e 1126 /* if known, set corresponding PHY IRQs */
bd2302c2
FF
1127 if (aup->phy_static_config)
1128 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1129 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1130
1131 err = mdiobus_register(aup->mii_bus);
1132 if (err) {
5368c726 1133 dev_err(&pdev->dev, "failed to register MDIO bus\n");
bd2302c2
FF
1134 goto err_mdiobus_reg;
1135 }
5ef3041e 1136
eb049630 1137 if (au1000_mii_probe(dev) != 0)
5ef3041e 1138 goto err_out;
5ef3041e
FF
1139
1140 pDBfree = NULL;
1141 /* setup the data buffer descriptors and attach a buffer to each one */
1142 pDB = aup->db;
1143 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1144 pDB->pnext = pDBfree;
1145 pDBfree = pDB;
1146 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1147 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1148 pDB++;
1149 }
1150 aup->pDBfree = pDBfree;
1151
1152 for (i = 0; i < NUM_RX_DMA; i++) {
eb049630 1153 pDB = au1000_GetFreeDB(aup);
5ef3041e
FF
1154 if (!pDB) {
1155 goto err_out;
1156 }
1157 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1158 aup->rx_db_inuse[i] = pDB;
1159 }
1160 for (i = 0; i < NUM_TX_DMA; i++) {
eb049630 1161 pDB = au1000_GetFreeDB(aup);
5ef3041e
FF
1162 if (!pDB) {
1163 goto err_out;
1164 }
1165 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1166 aup->tx_dma_ring[i]->len = 0;
1167 aup->tx_db_inuse[i] = pDB;
1168 }
1169
bd2302c2
FF
1170 dev->base_addr = base->start;
1171 dev->irq = irq;
1172 dev->netdev_ops = &au1000_netdev_ops;
1173 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1174 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1175
5ef3041e
FF
1176 /*
1177 * The boot code uses the ethernet controller, so reset it to start
1178 * fresh. au1000_init() expects that the device is in reset state.
1179 */
eb049630 1180 au1000_reset_mac(dev);
5ef3041e 1181
bd2302c2
FF
1182 err = register_netdev(dev);
1183 if (err) {
5368c726 1184 netdev_err(dev, "Cannot register net device, aborting.\n");
bd2302c2
FF
1185 goto err_out;
1186 }
1187
5368c726
FF
1188 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1189 (unsigned long)base->start, irq);
bd2302c2
FF
1190 if (version_printed++ == 0)
1191 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1192
1193 return 0;
5ef3041e
FF
1194
1195err_out:
bd2302c2 1196 if (aup->mii_bus != NULL)
5ef3041e 1197 mdiobus_unregister(aup->mii_bus);
5ef3041e
FF
1198
1199 /* here we should have a valid dev plus aup-> register addresses
1200 * so we can reset the mac properly.*/
eb049630 1201 au1000_reset_mac(dev);
5ef3041e
FF
1202
1203 for (i = 0; i < NUM_RX_DMA; i++) {
1204 if (aup->rx_db_inuse[i])
eb049630 1205 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
5ef3041e
FF
1206 }
1207 for (i = 0; i < NUM_TX_DMA; i++) {
1208 if (aup->tx_db_inuse[i])
eb049630 1209 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
5ef3041e 1210 }
bd2302c2
FF
1211err_mdiobus_reg:
1212 mdiobus_free(aup->mii_bus);
1213err_mdiobus_alloc:
1214 iounmap(aup->enable);
1215err_remap2:
1216 iounmap(aup->mac);
1217err_remap1:
5ef3041e
FF
1218 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1219 (void *)aup->vaddr, aup->dma_addr);
bd2302c2 1220err_vaddr:
5ef3041e 1221 free_netdev(dev);
bd2302c2
FF
1222err_alloc:
1223 release_mem_region(macen->start, resource_size(macen));
1224err_request:
1225 release_mem_region(base->start, resource_size(base));
1226out:
1227 return err;
5ef3041e
FF
1228}
1229
bd2302c2 1230static int __devexit au1000_remove(struct platform_device *pdev)
5ef3041e 1231{
bd2302c2
FF
1232 struct net_device *dev = platform_get_drvdata(pdev);
1233 struct au1000_private *aup = netdev_priv(dev);
1234 int i;
1235 struct resource *base, *macen;
5ef3041e 1236
bd2302c2
FF
1237 platform_set_drvdata(pdev, NULL);
1238
1239 unregister_netdev(dev);
1240 mdiobus_unregister(aup->mii_bus);
1241 mdiobus_free(aup->mii_bus);
1242
1243 for (i = 0; i < NUM_RX_DMA; i++)
1244 if (aup->rx_db_inuse[i])
eb049630 1245 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
bd2302c2
FF
1246
1247 for (i = 0; i < NUM_TX_DMA; i++)
1248 if (aup->tx_db_inuse[i])
eb049630 1249 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
bd2302c2
FF
1250
1251 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1252 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1253 (void *)aup->vaddr, aup->dma_addr);
1254
1255 iounmap(aup->mac);
1256 iounmap(aup->enable);
1257
1258 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1259 release_mem_region(base->start, resource_size(base));
1260
1261 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1262 release_mem_region(macen->start, resource_size(macen));
1263
1264 free_netdev(dev);
5ef3041e 1265
5ef3041e
FF
1266 return 0;
1267}
1268
bd2302c2
FF
1269static struct platform_driver au1000_eth_driver = {
1270 .probe = au1000_probe,
1271 .remove = __devexit_p(au1000_remove),
1272 .driver = {
1273 .name = "au1000-eth",
1274 .owner = THIS_MODULE,
1275 },
1276};
1277MODULE_ALIAS("platform:au1000-eth");
1278
1279
1280static int __init au1000_init_module(void)
1281{
1282 return platform_driver_register(&au1000_eth_driver);
1283}
1284
1285static void __exit au1000_exit_module(void)
5ef3041e 1286{
bd2302c2 1287 platform_driver_unregister(&au1000_eth_driver);
5ef3041e
FF
1288}
1289
1da177e4 1290module_init(au1000_init_module);
bd2302c2 1291module_exit(au1000_exit_module);