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au1000-eth: remove volatiles, switch to I/O accessors
[net-next-2.6.git] / drivers / net / au1000_eth.c
CommitLineData
1da177e4
LT
1/*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
89be0501 5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
1da177e4
LT
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
6aa20a22
JG
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
1da177e4 11 * ioctls (SIOCGMIIPHY)
0638dec0
HVR
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
1da177e4 15 * Author: MontaVista Software, Inc.
ec7eabdd 16 * ppopov@mvista.com or source@mvista.com
1da177e4
LT
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
32 *
33 * ########################################################################
34 *
6aa20a22 35 *
1da177e4 36 */
215e17be
FF
37#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38
bc36b428 39#include <linux/capability.h>
d791c2bd 40#include <linux/dma-mapping.h>
1da177e4
LT
41#include <linux/module.h>
42#include <linux/kernel.h>
1da177e4
LT
43#include <linux/string.h>
44#include <linux/timer.h>
45#include <linux/errno.h>
46#include <linux/in.h>
47#include <linux/ioport.h>
48#include <linux/bitops.h>
49#include <linux/slab.h>
50#include <linux/interrupt.h>
1da177e4
LT
51#include <linux/init.h>
52#include <linux/netdevice.h>
53#include <linux/etherdevice.h>
54#include <linux/ethtool.h>
55#include <linux/mii.h>
56#include <linux/skbuff.h>
57#include <linux/delay.h>
8cd35da0 58#include <linux/crc32.h>
0638dec0 59#include <linux/phy.h>
bd2302c2 60#include <linux/platform_device.h>
49a42c08
FF
61#include <linux/cpu.h>
62#include <linux/io.h>
25b31cb1 63
1da177e4
LT
64#include <asm/mipsregs.h>
65#include <asm/irq.h>
1da177e4
LT
66#include <asm/processor.h>
67
25b31cb1 68#include <au1000.h>
bd2302c2 69#include <au1xxx_eth.h>
25b31cb1
YY
70#include <prom.h>
71
1da177e4
LT
72#include "au1000_eth.h"
73
74#ifdef AU1000_ETH_DEBUG
75static int au1000_debug = 5;
76#else
77static int au1000_debug = 3;
78#endif
79
7cd2e6e3
FF
80#define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
81 NETIF_MSG_PROBE | \
82 NETIF_MSG_LINK)
83
89be0501 84#define DRV_NAME "au1000_eth"
8020eb82 85#define DRV_VERSION "1.7"
1da177e4
LT
86#define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
87#define DRV_DESC "Au1xxx on-chip Ethernet driver"
88
89MODULE_AUTHOR(DRV_AUTHOR);
90MODULE_DESCRIPTION(DRV_DESC);
91MODULE_LICENSE("GPL");
13130c7a 92MODULE_VERSION(DRV_VERSION);
1da177e4 93
1da177e4
LT
94/*
95 * Theory of operation
96 *
6aa20a22
JG
97 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
98 * There are four receive and four transmit descriptors. These
99 * descriptors are not in memory; rather, they are just a set of
1da177e4
LT
100 * hardware registers.
101 *
102 * Since the Au1000 has a coherent data cache, the receive and
6aa20a22 103 * transmit buffers are allocated from the KSEG0 segment. The
1da177e4
LT
104 * hardware registers, however, are still mapped at KSEG1 to
105 * make sure there's no out-of-order writes, and that all writes
106 * complete immediately.
107 */
108
1da177e4
LT
109struct au1000_private *au_macs[NUM_ETH_INTERFACES];
110
0638dec0
HVR
111/*
112 * board-specific configurations
113 *
114 * PHY detection algorithm
115 *
bd2302c2 116 * If phy_static_config is undefined, the PHY setup is
0638dec0
HVR
117 * autodetected:
118 *
119 * mii_probe() first searches the current MAC's MII bus for a PHY,
bd2302c2 120 * selecting the first (or last, if phy_search_highest_addr is
0638dec0
HVR
121 * defined) PHY address not already claimed by another netdev.
122 *
123 * If nothing was found that way when searching for the 2nd ethernet
bd2302c2 124 * controller's PHY and phy1_search_mac0 is defined, then
0638dec0
HVR
125 * the first MII bus is searched as well for an unclaimed PHY; this is
126 * needed in case of a dual-PHY accessible only through the MAC0's MII
127 * bus.
128 *
129 * Finally, if no PHY is found, then the corresponding ethernet
130 * controller is not registered to the network subsystem.
1da177e4
LT
131 */
132
bd2302c2 133/* autodetection defaults: phy1_search_mac0 */
1da177e4 134
0638dec0
HVR
135/* static PHY setup
136 *
137 * most boards PHY setup should be detectable properly with the
138 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
139 * you have a switch attached, or want to use the PHY's interrupt
140 * notification capabilities) you can provide a static PHY
141 * configuration here
142 *
143 * IRQs may only be set, if a PHY address was configured
144 * If a PHY address is given, also a bus id is required to be set
145 *
146 * ps: make sure the used irqs are configured properly in the board
147 * specific irq-map
148 */
1da177e4 149
eb049630 150static void au1000_enable_mac(struct net_device *dev, int force_reset)
5ef3041e
FF
151{
152 unsigned long flags;
153 struct au1000_private *aup = netdev_priv(dev);
154
155 spin_lock_irqsave(&aup->lock, flags);
156
ec7eabdd 157 if (force_reset || (!aup->mac_enabled)) {
d0e7cb5d 158 writel(MAC_EN_CLOCK_ENABLE, &aup->enable);
5ef3041e 159 au_sync_delay(2);
d0e7cb5d
FF
160 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
161 | MAC_EN_CLOCK_ENABLE), &aup->enable);
5ef3041e
FF
162 au_sync_delay(2);
163
164 aup->mac_enabled = 1;
165 }
166
167 spin_unlock_irqrestore(&aup->lock, flags);
168}
169
0638dec0
HVR
170/*
171 * MII operations
172 */
1210dde7 173static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
1da177e4 174{
454d7c9b 175 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d
FF
176 u32 *const mii_control_reg = &aup->mac->mii_control;
177 u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT
178 u32 timedout = 20;
179 u32 mii_control;
180
d0e7cb5d 181 while (readl(mii_control_reg) & MAC_MII_BUSY) {
1da177e4
LT
182 mdelay(1);
183 if (--timedout == 0) {
5368c726 184 netdev_err(dev, "read_MII busy timeout!!\n");
1da177e4
LT
185 return -1;
186 }
187 }
188
6aa20a22 189 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 190 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
1da177e4 191
d0e7cb5d 192 writel(mii_control, mii_control_reg);
1da177e4
LT
193
194 timedout = 20;
d0e7cb5d 195 while (readl(mii_control_reg) & MAC_MII_BUSY) {
1da177e4
LT
196 mdelay(1);
197 if (--timedout == 0) {
5368c726 198 netdev_err(dev, "mdio_read busy timeout!!\n");
1da177e4
LT
199 return -1;
200 }
201 }
d0e7cb5d 202 return readl(mii_data_reg);
1da177e4
LT
203}
204
1210dde7
AB
205static void au1000_mdio_write(struct net_device *dev, int phy_addr,
206 int reg, u16 value)
1da177e4 207{
454d7c9b 208 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d
FF
209 u32 *const mii_control_reg = &aup->mac->mii_control;
210 u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT
211 u32 timedout = 20;
212 u32 mii_control;
213
d0e7cb5d 214 while (readl(mii_control_reg) & MAC_MII_BUSY) {
1da177e4
LT
215 mdelay(1);
216 if (--timedout == 0) {
5368c726 217 netdev_err(dev, "mdio_write busy timeout!!\n");
1da177e4
LT
218 return;
219 }
220 }
221
6aa20a22 222 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 223 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
1da177e4 224
d0e7cb5d
FF
225 writel(value, mii_data_reg);
226 writel(mii_control, mii_control_reg);
1da177e4
LT
227}
228
1210dde7 229static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
0638dec0
HVR
230{
231 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
232 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
233 struct net_device *const dev = bus->priv;
234
eb049630 235 au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
0638dec0 236 * mii_bus is enabled */
1210dde7 237 return au1000_mdio_read(dev, phy_addr, regnum);
0638dec0 238}
1da177e4 239
1210dde7
AB
240static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
241 u16 value)
1da177e4 242{
0638dec0 243 struct net_device *const dev = bus->priv;
1da177e4 244
eb049630 245 au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
0638dec0 246 * mii_bus is enabled */
1210dde7 247 au1000_mdio_write(dev, phy_addr, regnum, value);
0638dec0 248 return 0;
1da177e4
LT
249}
250
1210dde7 251static int au1000_mdiobus_reset(struct mii_bus *bus)
1da177e4 252{
0638dec0 253 struct net_device *const dev = bus->priv;
1da177e4 254
eb049630 255 au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
0638dec0
HVR
256 * mii_bus is enabled */
257 return 0;
258}
1da177e4 259
eb049630 260static void au1000_hard_stop(struct net_device *dev)
5ef3041e
FF
261{
262 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d 263 u32 reg;
5ef3041e 264
5368c726 265 netif_dbg(aup, drv, dev, "hard stop\n");
5ef3041e 266
d0e7cb5d
FF
267 reg = readl(&aup->mac->control);
268 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
269 writel(reg, &aup->mac->control);
5ef3041e
FF
270 au_sync_delay(10);
271}
272
eb049630 273static void au1000_enable_rx_tx(struct net_device *dev)
5ef3041e
FF
274{
275 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d 276 u32 reg;
5ef3041e 277
5368c726 278 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
5ef3041e 279
d0e7cb5d
FF
280 reg = readl(&aup->mac->control);
281 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
282 writel(reg, &aup->mac->control);
5ef3041e
FF
283 au_sync_delay(10);
284}
285
286static void
287au1000_adjust_link(struct net_device *dev)
288{
289 struct au1000_private *aup = netdev_priv(dev);
290 struct phy_device *phydev = aup->phy_dev;
291 unsigned long flags;
d0e7cb5d 292 u32 reg;
5ef3041e
FF
293
294 int status_change = 0;
295
296 BUG_ON(!aup->phy_dev);
297
298 spin_lock_irqsave(&aup->lock, flags);
299
300 if (phydev->link && (aup->old_speed != phydev->speed)) {
2cc3c6b1 301 /* speed changed */
5ef3041e 302
2cc3c6b1 303 switch (phydev->speed) {
5ef3041e
FF
304 case SPEED_10:
305 case SPEED_100:
306 break;
307 default:
5368c726
FF
308 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
309 phydev->speed);
5ef3041e
FF
310 break;
311 }
312
313 aup->old_speed = phydev->speed;
314
315 status_change = 1;
316 }
317
318 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
2cc3c6b1 319 /* duplex mode changed */
5ef3041e
FF
320
321 /* switching duplex mode requires to disable rx and tx! */
eb049630 322 au1000_hard_stop(dev);
5ef3041e 323
d0e7cb5d
FF
324 reg = readl(&aup->mac->control);
325 if (DUPLEX_FULL == phydev->duplex) {
326 reg |= MAC_FULL_DUPLEX;
327 reg &= ~MAC_DISABLE_RX_OWN;
328 } else {
329 reg &= ~MAC_FULL_DUPLEX;
330 reg |= MAC_DISABLE_RX_OWN;
331 }
332 writel(reg, &aup->mac->control);
5ef3041e
FF
333 au_sync_delay(1);
334
eb049630 335 au1000_enable_rx_tx(dev);
5ef3041e
FF
336 aup->old_duplex = phydev->duplex;
337
338 status_change = 1;
339 }
340
2cc3c6b1
FF
341 if (phydev->link != aup->old_link) {
342 /* link state changed */
5ef3041e
FF
343
344 if (!phydev->link) {
345 /* link went down */
346 aup->old_speed = 0;
347 aup->old_duplex = -1;
348 }
349
350 aup->old_link = phydev->link;
351 status_change = 1;
352 }
353
354 spin_unlock_irqrestore(&aup->lock, flags);
355
356 if (status_change) {
357 if (phydev->link)
5368c726
FF
358 netdev_info(dev, "link up (%d/%s)\n",
359 phydev->speed,
5ef3041e
FF
360 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
361 else
5368c726 362 netdev_info(dev, "link down\n");
5ef3041e
FF
363 }
364}
365
ec7eabdd 366static int au1000_mii_probe(struct net_device *dev)
0638dec0 367{
454d7c9b 368 struct au1000_private *const aup = netdev_priv(dev);
0638dec0 369 struct phy_device *phydev = NULL;
18b8e15b 370 int phy_addr;
0638dec0 371
bd2302c2
FF
372 if (aup->phy_static_config) {
373 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
0638dec0 374
bd2302c2
FF
375 if (aup->phy_addr)
376 phydev = aup->mii_bus->phy_map[aup->phy_addr];
377 else
5368c726 378 netdev_info(dev, "using PHY-less setup\n");
0638dec0 379 return 0;
18b8e15b 380 }
0638dec0 381
18b8e15b
FF
382 /* find the first (lowest address) PHY
383 * on the current MAC's MII bus */
384 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
385 if (aup->mii_bus->phy_map[phy_addr]) {
386 phydev = aup->mii_bus->phy_map[phy_addr];
387 if (!aup->phy_search_highest_addr)
388 /* break out with first one found */
389 break;
390 }
0638dec0 391
18b8e15b
FF
392 if (aup->phy1_search_mac0) {
393 /* try harder to find a PHY */
394 if (!phydev && (aup->mac_id == 1)) {
395 /* no PHY found, maybe we have a dual PHY? */
396 dev_info(&dev->dev, ": no PHY found on MAC1, "
397 "let's see if it's attached to MAC0...\n");
398
399 /* find the first (lowest address) non-attached
400 * PHY on the MAC0 MII bus
401 */
402 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
403 struct phy_device *const tmp_phydev =
404 aup->mii_bus->phy_map[phy_addr];
405
406 if (aup->mac_id == 1)
407 break;
408
409 /* no PHY here... */
410 if (!tmp_phydev)
411 continue;
412
413 /* already claimed by MAC0 */
414 if (tmp_phydev->attached_dev)
415 continue;
416
417 phydev = tmp_phydev;
418 break; /* found it */
bd2302c2 419 }
1da177e4
LT
420 }
421 }
1da177e4 422
0638dec0 423 if (!phydev) {
5368c726 424 netdev_err(dev, "no PHY found\n");
1da177e4
LT
425 return -1;
426 }
427
0638dec0 428 /* now we are supposed to have a proper phydev, to attach to... */
0638dec0
HVR
429 BUG_ON(phydev->attached_dev);
430
db1d7bf7
KS
431 phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
432 0, PHY_INTERFACE_MODE_MII);
0638dec0
HVR
433
434 if (IS_ERR(phydev)) {
5368c726 435 netdev_err(dev, "Could not attach to PHY\n");
0638dec0
HVR
436 return PTR_ERR(phydev);
437 }
438
439 /* mask with MAC supported features */
440 phydev->supported &= (SUPPORTED_10baseT_Half
441 | SUPPORTED_10baseT_Full
442 | SUPPORTED_100baseT_Half
443 | SUPPORTED_100baseT_Full
444 | SUPPORTED_Autoneg
445 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
446 | SUPPORTED_MII
447 | SUPPORTED_TP);
448
449 phydev->advertising = phydev->supported;
450
451 aup->old_link = 0;
452 aup->old_speed = 0;
453 aup->old_duplex = -1;
454 aup->phy_dev = phydev;
455
5368c726
FF
456 netdev_info(dev, "attached PHY driver [%s] "
457 "(mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7 458 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1da177e4
LT
459
460 return 0;
461}
462
463
464/*
465 * Buffer allocation/deallocation routines. The buffer descriptor returned
6aa20a22 466 * has the virtual and dma address of a buffer suitable for
1da177e4
LT
467 * both, receive and transmit operations.
468 */
3441592b 469static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
1da177e4 470{
3441592b 471 struct db_dest *pDB;
1da177e4
LT
472 pDB = aup->pDBfree;
473
ec7eabdd 474 if (pDB)
1da177e4 475 aup->pDBfree = pDB->pnext;
ec7eabdd 476
1da177e4
LT
477 return pDB;
478}
479
3441592b 480void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
1da177e4 481{
3441592b 482 struct db_dest *pDBfree = aup->pDBfree;
1da177e4
LT
483 if (pDBfree)
484 pDBfree->pnext = pDB;
485 aup->pDBfree = pDB;
486}
487
eb049630 488static void au1000_reset_mac_unlocked(struct net_device *dev)
0638dec0 489{
454d7c9b 490 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR
491 int i;
492
eb049630 493 au1000_hard_stop(dev);
0638dec0 494
d0e7cb5d 495 writel(MAC_EN_CLOCK_ENABLE, &aup->enable);
0638dec0 496 au_sync_delay(2);
d0e7cb5d 497 writel(0, &aup->enable);
0638dec0
HVR
498 au_sync_delay(2);
499
1da177e4
LT
500 aup->tx_full = 0;
501 for (i = 0; i < NUM_RX_DMA; i++) {
502 /* reset control bits */
503 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
504 }
505 for (i = 0; i < NUM_TX_DMA; i++) {
506 /* reset control bits */
507 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
508 }
0638dec0
HVR
509
510 aup->mac_enabled = 0;
511
1da177e4
LT
512}
513
eb049630 514static void au1000_reset_mac(struct net_device *dev)
0638dec0 515{
454d7c9b 516 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR
517 unsigned long flags;
518
5368c726
FF
519 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
520 (unsigned)aup);
0638dec0
HVR
521
522 spin_lock_irqsave(&aup->lock, flags);
523
ec7eabdd 524 au1000_reset_mac_unlocked(dev);
0638dec0
HVR
525
526 spin_unlock_irqrestore(&aup->lock, flags);
527}
1da177e4 528
6aa20a22 529/*
1da177e4
LT
530 * Setup the receive and transmit "rings". These pointers are the addresses
531 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
532 * these are not descriptors sitting in memory.
533 */
6aa20a22 534static void
eb049630 535au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
1da177e4
LT
536{
537 int i;
538
539 for (i = 0; i < NUM_RX_DMA; i++) {
6aa20a22 540 aup->rx_dma_ring[i] =
d0e7cb5d 541 (struct rx_dma *)
18b8e15b 542 (rx_base + sizeof(struct rx_dma)*i);
1da177e4
LT
543 }
544 for (i = 0; i < NUM_TX_DMA; i++) {
6aa20a22 545 aup->tx_dma_ring[i] =
d0e7cb5d 546 (struct tx_dma *)
18b8e15b 547 (tx_base + sizeof(struct tx_dma)*i);
1da177e4
LT
548 }
549}
550
0638dec0
HVR
551/*
552 * ethtool operations
553 */
1da177e4 554
0638dec0 555static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 556{
454d7c9b 557 struct au1000_private *aup = netdev_priv(dev);
1da177e4 558
0638dec0
HVR
559 if (aup->phy_dev)
560 return phy_ethtool_gset(aup->phy_dev, cmd);
1da177e4 561
0638dec0 562 return -EINVAL;
1da177e4
LT
563}
564
0638dec0 565static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 566{
454d7c9b 567 struct au1000_private *aup = netdev_priv(dev);
1da177e4 568
0638dec0
HVR
569 if (!capable(CAP_NET_ADMIN))
570 return -EPERM;
1da177e4 571
0638dec0
HVR
572 if (aup->phy_dev)
573 return phy_ethtool_sset(aup->phy_dev, cmd);
1da177e4 574
0638dec0 575 return -EINVAL;
1da177e4
LT
576}
577
578static void
579au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
580{
454d7c9b 581 struct au1000_private *aup = netdev_priv(dev);
1da177e4
LT
582
583 strcpy(info->driver, DRV_NAME);
584 strcpy(info->version, DRV_VERSION);
585 info->fw_version[0] = '\0';
586 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
587 info->regdump_len = 0;
588}
589
7cd2e6e3
FF
590static void au1000_set_msglevel(struct net_device *dev, u32 value)
591{
592 struct au1000_private *aup = netdev_priv(dev);
593 aup->msg_enable = value;
594}
595
596static u32 au1000_get_msglevel(struct net_device *dev)
597{
598 struct au1000_private *aup = netdev_priv(dev);
599 return aup->msg_enable;
600}
601
7282d491 602static const struct ethtool_ops au1000_ethtool_ops = {
1da177e4
LT
603 .get_settings = au1000_get_settings,
604 .set_settings = au1000_set_settings,
605 .get_drvinfo = au1000_get_drvinfo,
0638dec0 606 .get_link = ethtool_op_get_link,
7cd2e6e3
FF
607 .get_msglevel = au1000_get_msglevel,
608 .set_msglevel = au1000_set_msglevel,
1da177e4
LT
609};
610
5ef3041e
FF
611
612/*
613 * Initialize the interface.
614 *
615 * When the device powers up, the clocks are disabled and the
616 * mac is in reset state. When the interface is closed, we
617 * do the same -- reset the device and disable the clocks to
618 * conserve power. Thus, whenever au1000_init() is called,
619 * the device should already be in reset state.
620 */
621static int au1000_init(struct net_device *dev)
1da177e4 622{
5ef3041e
FF
623 struct au1000_private *aup = netdev_priv(dev);
624 unsigned long flags;
625 int i;
626 u32 control;
89be0501 627
5368c726 628 netif_dbg(aup, hw, dev, "au1000_init\n");
1da177e4 629
5ef3041e 630 /* bring the device out of reset */
eb049630 631 au1000_enable_mac(dev, 1);
89be0501 632
5ef3041e 633 spin_lock_irqsave(&aup->lock, flags);
1da177e4 634
d0e7cb5d 635 writel(0, &aup->mac->control);
5ef3041e
FF
636 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
637 aup->tx_tail = aup->tx_head;
638 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
1da177e4 639
d0e7cb5d
FF
640 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
641 &aup->mac->mac_addr_high);
642 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
643 dev->dev_addr[1]<<8 | dev->dev_addr[0],
644 &aup->mac->mac_addr_low);
5ef3041e 645
18b8e15b 646
ec7eabdd 647 for (i = 0; i < NUM_RX_DMA; i++)
5ef3041e 648 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
ec7eabdd 649
5ef3041e 650 au_sync();
1da177e4 651
5ef3041e
FF
652 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
653#ifndef CONFIG_CPU_LITTLE_ENDIAN
654 control |= MAC_BIG_ENDIAN;
655#endif
656 if (aup->phy_dev) {
657 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
658 control |= MAC_FULL_DUPLEX;
659 else
660 control |= MAC_DISABLE_RX_OWN;
661 } else { /* PHY-less op, assume full-duplex */
662 control |= MAC_FULL_DUPLEX;
1da177e4
LT
663 }
664
d0e7cb5d
FF
665 writel(control, &aup->mac->control);
666 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
5ef3041e 667 au_sync();
1da177e4 668
5ef3041e
FF
669 spin_unlock_irqrestore(&aup->lock, flags);
670 return 0;
671}
1da177e4 672
eb049630 673static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
5ef3041e 674{
5ef3041e 675 struct net_device_stats *ps = &dev->stats;
1da177e4 676
5ef3041e
FF
677 ps->rx_packets++;
678 if (status & RX_MCAST_FRAME)
679 ps->multicast++;
1da177e4 680
5ef3041e
FF
681 if (status & RX_ERROR) {
682 ps->rx_errors++;
683 if (status & RX_MISSED_FRAME)
684 ps->rx_missed_errors++;
4989ccb2 685 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
5ef3041e
FF
686 ps->rx_length_errors++;
687 if (status & RX_CRC_ERROR)
688 ps->rx_crc_errors++;
689 if (status & RX_COLL)
690 ps->collisions++;
2cc3c6b1 691 } else
5ef3041e 692 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
298cf9be 693
1da177e4
LT
694}
695
6aa20a22 696/*
5ef3041e 697 * Au1000 receive routine.
1da177e4 698 */
5ef3041e 699static int au1000_rx(struct net_device *dev)
1da177e4 700{
454d7c9b 701 struct au1000_private *aup = netdev_priv(dev);
5ef3041e 702 struct sk_buff *skb;
d0e7cb5d 703 struct rx_dma *prxd;
5ef3041e 704 u32 buff_stat, status;
3441592b 705 struct db_dest *pDB;
5ef3041e 706 u32 frmlen;
1da177e4 707
5368c726 708 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
1da177e4 709
5ef3041e
FF
710 prxd = aup->rx_dma_ring[aup->rx_head];
711 buff_stat = prxd->buff_stat;
712 while (buff_stat & RX_T_DONE) {
713 status = prxd->status;
714 pDB = aup->rx_db_inuse[aup->rx_head];
eb049630 715 au1000_update_rx_stats(dev, status);
5ef3041e 716 if (!(status & RX_ERROR)) {
1da177e4 717
5ef3041e
FF
718 /* good frame */
719 frmlen = (status & RX_FRAME_LEN_MASK);
720 frmlen -= 4; /* Remove FCS */
721 skb = dev_alloc_skb(frmlen + 2);
722 if (skb == NULL) {
5368c726 723 netdev_err(dev, "Memory squeeze, dropping packet.\n");
5ef3041e
FF
724 dev->stats.rx_dropped++;
725 continue;
726 }
727 skb_reserve(skb, 2); /* 16 byte IP header align */
728 skb_copy_to_linear_data(skb,
729 (unsigned char *)pDB->vaddr, frmlen);
730 skb_put(skb, frmlen);
731 skb->protocol = eth_type_trans(skb, dev);
732 netif_rx(skb); /* pass the packet to upper layers */
2cc3c6b1 733 } else {
5ef3041e 734 if (au1000_debug > 4) {
215e17be 735 pr_err("rx_error(s):");
5ef3041e 736 if (status & RX_MISSED_FRAME)
215e17be 737 pr_cont(" miss");
5ef3041e 738 if (status & RX_WDOG_TIMER)
215e17be 739 pr_cont(" wdog");
5ef3041e 740 if (status & RX_RUNT)
215e17be 741 pr_cont(" runt");
5ef3041e 742 if (status & RX_OVERLEN)
215e17be 743 pr_cont(" overlen");
5ef3041e 744 if (status & RX_COLL)
215e17be 745 pr_cont(" coll");
5ef3041e 746 if (status & RX_MII_ERROR)
215e17be 747 pr_cont(" mii error");
5ef3041e 748 if (status & RX_CRC_ERROR)
215e17be 749 pr_cont(" crc error");
5ef3041e 750 if (status & RX_LEN_ERROR)
215e17be 751 pr_cont(" len error");
5ef3041e 752 if (status & RX_U_CNTRL_FRAME)
215e17be
FF
753 pr_cont(" u control frame");
754 pr_cont("\n");
5ef3041e
FF
755 }
756 }
757 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
758 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
759 au_sync();
1da177e4 760
5ef3041e
FF
761 /* next descriptor */
762 prxd = aup->rx_dma_ring[aup->rx_head];
763 buff_stat = prxd->buff_stat;
1da177e4 764 }
1da177e4
LT
765 return 0;
766}
767
eb049630 768static void au1000_update_tx_stats(struct net_device *dev, u32 status)
1da177e4 769{
454d7c9b 770 struct au1000_private *aup = netdev_priv(dev);
5ef3041e 771 struct net_device_stats *ps = &dev->stats;
0638dec0 772
5ef3041e
FF
773 if (status & TX_FRAME_ABORTED) {
774 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
775 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
776 /* any other tx errors are only valid
777 * in half duplex mode */
778 ps->tx_errors++;
779 ps->tx_aborted_errors++;
780 }
2cc3c6b1 781 } else {
5ef3041e
FF
782 ps->tx_errors++;
783 ps->tx_aborted_errors++;
784 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
785 ps->tx_carrier_errors++;
786 }
787 }
788}
0638dec0 789
5ef3041e
FF
790/*
791 * Called from the interrupt service routine to acknowledge
792 * the TX DONE bits. This is a must if the irq is setup as
793 * edge triggered.
794 */
795static void au1000_tx_ack(struct net_device *dev)
796{
797 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d 798 struct tx_dma *ptxd;
0638dec0 799
5ef3041e 800 ptxd = aup->tx_dma_ring[aup->tx_tail];
0638dec0 801
5ef3041e 802 while (ptxd->buff_stat & TX_T_DONE) {
eb049630 803 au1000_update_tx_stats(dev, ptxd->status);
5ef3041e
FF
804 ptxd->buff_stat &= ~TX_T_DONE;
805 ptxd->len = 0;
806 au_sync();
0638dec0 807
5ef3041e
FF
808 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
809 ptxd = aup->tx_dma_ring[aup->tx_tail];
0638dec0 810
5ef3041e
FF
811 if (aup->tx_full) {
812 aup->tx_full = 0;
813 netif_wake_queue(dev);
814 }
1da177e4 815 }
5ef3041e 816}
1da177e4 817
5ef3041e
FF
818/*
819 * Au1000 interrupt service routine.
820 */
821static irqreturn_t au1000_interrupt(int irq, void *dev_id)
822{
823 struct net_device *dev = dev_id;
1da177e4 824
5ef3041e
FF
825 /* Handle RX interrupts first to minimize chance of overrun */
826
827 au1000_rx(dev);
828 au1000_tx_ack(dev);
829 return IRQ_RETVAL(1);
1da177e4
LT
830}
831
832static int au1000_open(struct net_device *dev)
833{
834 int retval;
454d7c9b 835 struct au1000_private *aup = netdev_priv(dev);
1da177e4 836
5368c726 837 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
1da177e4 838
2cc3c6b1
FF
839 retval = request_irq(dev->irq, au1000_interrupt, 0,
840 dev->name, dev);
841 if (retval) {
5368c726 842 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
0638dec0
HVR
843 return retval;
844 }
845
2cc3c6b1
FF
846 retval = au1000_init(dev);
847 if (retval) {
5368c726 848 netdev_err(dev, "error in au1000_init\n");
1da177e4
LT
849 free_irq(dev->irq, dev);
850 return retval;
851 }
1da177e4 852
0638dec0
HVR
853 if (aup->phy_dev) {
854 /* cause the PHY state machine to schedule a link state check */
855 aup->phy_dev->state = PHY_CHANGELINK;
856 phy_start(aup->phy_dev);
1da177e4
LT
857 }
858
0638dec0 859 netif_start_queue(dev);
1da177e4 860
5368c726 861 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
1da177e4
LT
862
863 return 0;
864}
865
866static int au1000_close(struct net_device *dev)
867{
0638dec0 868 unsigned long flags;
454d7c9b 869 struct au1000_private *const aup = netdev_priv(dev);
1da177e4 870
5368c726 871 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
1da177e4 872
0638dec0
HVR
873 if (aup->phy_dev)
874 phy_stop(aup->phy_dev);
1da177e4
LT
875
876 spin_lock_irqsave(&aup->lock, flags);
0638dec0 877
ec7eabdd 878 au1000_reset_mac_unlocked(dev);
0638dec0 879
1da177e4
LT
880 /* stop the device */
881 netif_stop_queue(dev);
882
883 /* disable the interrupt */
884 free_irq(dev->irq, dev);
885 spin_unlock_irqrestore(&aup->lock, flags);
886
887 return 0;
888}
889
1da177e4
LT
890/*
891 * Au1000 transmit routine.
892 */
61357325 893static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1da177e4 894{
454d7c9b 895 struct au1000_private *aup = netdev_priv(dev);
09f75cd7 896 struct net_device_stats *ps = &dev->stats;
d0e7cb5d 897 struct tx_dma *ptxd;
1da177e4 898 u32 buff_stat;
3441592b 899 struct db_dest *pDB;
1da177e4
LT
900 int i;
901
5368c726
FF
902 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
903 (unsigned)aup, skb->len,
1da177e4
LT
904 skb->data, aup->tx_head);
905
906 ptxd = aup->tx_dma_ring[aup->tx_head];
907 buff_stat = ptxd->buff_stat;
908 if (buff_stat & TX_DMA_ENABLE) {
909 /* We've wrapped around and the transmitter is still busy */
910 netif_stop_queue(dev);
911 aup->tx_full = 1;
5b548140 912 return NETDEV_TX_BUSY;
2cc3c6b1 913 } else if (buff_stat & TX_T_DONE) {
eb049630 914 au1000_update_tx_stats(dev, ptxd->status);
1da177e4
LT
915 ptxd->len = 0;
916 }
917
918 if (aup->tx_full) {
919 aup->tx_full = 0;
920 netif_wake_queue(dev);
921 }
922
923 pDB = aup->tx_db_inuse[aup->tx_head];
bd2302c2 924 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1da177e4 925 if (skb->len < ETH_ZLEN) {
ec7eabdd 926 for (i = skb->len; i < ETH_ZLEN; i++)
1da177e4 927 ((char *)pDB->vaddr)[i] = 0;
ec7eabdd 928
1da177e4 929 ptxd->len = ETH_ZLEN;
2cc3c6b1 930 } else
5ef3041e 931 ptxd->len = skb->len;
1da177e4 932
5ef3041e
FF
933 ps->tx_packets++;
934 ps->tx_bytes += ptxd->len;
1da177e4 935
5ef3041e
FF
936 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
937 au_sync();
938 dev_kfree_skb(skb);
939 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
6ed10654 940 return NETDEV_TX_OK;
1da177e4
LT
941}
942
1da177e4
LT
943/*
944 * The Tx ring has been full longer than the watchdog timeout
945 * value. The transmitter must be hung?
946 */
947static void au1000_tx_timeout(struct net_device *dev)
948{
5368c726 949 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
eb049630 950 au1000_reset_mac(dev);
1da177e4 951 au1000_init(dev);
1ae5dc34 952 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT
953 netif_wake_queue(dev);
954}
955
d9a92cee 956static void au1000_multicast_list(struct net_device *dev)
1da177e4 957{
454d7c9b 958 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d 959 u32 reg;
1da177e4 960
18b8e15b 961 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
d0e7cb5d 962 reg = readl(&aup->mac->control);
1da177e4 963 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
d0e7cb5d 964 reg |= MAC_PROMISCUOUS;
1da177e4 965 } else if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf 966 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
d0e7cb5d
FF
967 reg |= MAC_PASS_ALL_MULTI;
968 reg &= ~MAC_PROMISCUOUS;
5368c726 969 netdev_info(dev, "Pass all multicast\n");
1da177e4 970 } else {
22bedad3 971 struct netdev_hw_addr *ha;
1da177e4
LT
972 u32 mc_filter[2]; /* Multicast hash filter */
973
974 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP
975 netdev_for_each_mc_addr(ha, dev)
976 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1da177e4 977 (long *)mc_filter);
d0e7cb5d
FF
978 writel(mc_filter[1], &aup->mac->multi_hash_high);
979 writel(mc_filter[0], &aup->mac->multi_hash_low);
980 reg &= ~MAC_PROMISCUOUS;
981 reg |= MAC_HASH_MODE;
1da177e4 982 }
d0e7cb5d 983 writel(reg, &aup->mac->control);
1da177e4
LT
984}
985
1da177e4
LT
986static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
987{
454d7c9b 988 struct au1000_private *aup = netdev_priv(dev);
1da177e4 989
2cc3c6b1
FF
990 if (!netif_running(dev))
991 return -EINVAL;
1da177e4 992
2cc3c6b1
FF
993 if (!aup->phy_dev)
994 return -EINVAL; /* PHY not controllable */
1da177e4 995
28b04113 996 return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1da177e4
LT
997}
998
d9a92cee
AB
999static const struct net_device_ops au1000_netdev_ops = {
1000 .ndo_open = au1000_open,
1001 .ndo_stop = au1000_close,
1002 .ndo_start_xmit = au1000_tx,
1003 .ndo_set_multicast_list = au1000_multicast_list,
1004 .ndo_do_ioctl = au1000_ioctl,
1005 .ndo_tx_timeout = au1000_tx_timeout,
1006 .ndo_set_mac_address = eth_mac_addr,
1007 .ndo_validate_addr = eth_validate_addr,
1008 .ndo_change_mtu = eth_change_mtu,
1009};
1010
bd2302c2 1011static int __devinit au1000_probe(struct platform_device *pdev)
5ef3041e 1012{
2cc3c6b1 1013 static unsigned version_printed;
5ef3041e 1014 struct au1000_private *aup = NULL;
bd2302c2 1015 struct au1000_eth_platform_data *pd;
5ef3041e 1016 struct net_device *dev = NULL;
3441592b 1017 struct db_dest *pDB, *pDBfree;
bd2302c2
FF
1018 int irq, i, err = 0;
1019 struct resource *base, *macen;
5ef3041e 1020
bd2302c2
FF
1021 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1022 if (!base) {
5368c726 1023 dev_err(&pdev->dev, "failed to retrieve base register\n");
bd2302c2
FF
1024 err = -ENODEV;
1025 goto out;
1026 }
5ef3041e 1027
bd2302c2
FF
1028 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1029 if (!macen) {
5368c726 1030 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
bd2302c2
FF
1031 err = -ENODEV;
1032 goto out;
1033 }
5ef3041e 1034
bd2302c2
FF
1035 irq = platform_get_irq(pdev, 0);
1036 if (irq < 0) {
5368c726 1037 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
bd2302c2
FF
1038 err = -ENODEV;
1039 goto out;
1040 }
5ef3041e 1041
18b8e15b
FF
1042 if (!request_mem_region(base->start, resource_size(base),
1043 pdev->name)) {
5368c726 1044 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
bd2302c2
FF
1045 err = -ENXIO;
1046 goto out;
1047 }
1048
18b8e15b
FF
1049 if (!request_mem_region(macen->start, resource_size(macen),
1050 pdev->name)) {
5368c726 1051 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
bd2302c2
FF
1052 err = -ENXIO;
1053 goto err_request;
1054 }
5ef3041e
FF
1055
1056 dev = alloc_etherdev(sizeof(struct au1000_private));
1057 if (!dev) {
5368c726 1058 dev_err(&pdev->dev, "alloc_etherdev failed\n");
bd2302c2
FF
1059 err = -ENOMEM;
1060 goto err_alloc;
5ef3041e
FF
1061 }
1062
bd2302c2
FF
1063 SET_NETDEV_DEV(dev, &pdev->dev);
1064 platform_set_drvdata(pdev, dev);
5ef3041e
FF
1065 aup = netdev_priv(dev);
1066
1067 spin_lock_init(&aup->lock);
18b8e15b
FF
1068 aup->msg_enable = (au1000_debug < 4 ?
1069 AU1000_DEF_MSG_ENABLE : au1000_debug);
5ef3041e
FF
1070
1071 /* Allocate the data buffers */
1072 /* Snooping works fine with eth on all au1xxx */
1073 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1074 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1075 &aup->dma_addr, 0);
1076 if (!aup->vaddr) {
5368c726 1077 dev_err(&pdev->dev, "failed to allocate data buffers\n");
bd2302c2
FF
1078 err = -ENOMEM;
1079 goto err_vaddr;
5ef3041e
FF
1080 }
1081
1082 /* aup->mac is the base address of the MAC's registers */
d0e7cb5d 1083 aup->mac = (struct mac_reg *)
18b8e15b 1084 ioremap_nocache(base->start, resource_size(base));
bd2302c2 1085 if (!aup->mac) {
5368c726 1086 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
bd2302c2
FF
1087 err = -ENXIO;
1088 goto err_remap1;
1089 }
5ef3041e 1090
ec7eabdd 1091 /* Setup some variables for quick register address access */
d0e7cb5d 1092 aup->enable = (u32 *)ioremap_nocache(macen->start,
18b8e15b 1093 resource_size(macen));
bd2302c2 1094 if (!aup->enable) {
5368c726 1095 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
bd2302c2
FF
1096 err = -ENXIO;
1097 goto err_remap2;
1098 }
1099 aup->mac_id = pdev->id;
5ef3041e 1100
f6673653 1101 if (pdev->id == 0)
eb049630 1102 au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
f6673653 1103 else if (pdev->id == 1)
eb049630 1104 au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
5ef3041e 1105
f6673653
ML
1106 /* set a random MAC now in case platform_data doesn't provide one */
1107 random_ether_addr(dev->dev_addr);
5ef3041e 1108
d0e7cb5d 1109 writel(0, &aup->enable);
5ef3041e
FF
1110 aup->mac_enabled = 0;
1111
bd2302c2
FF
1112 pd = pdev->dev.platform_data;
1113 if (!pd) {
18b8e15b
FF
1114 dev_info(&pdev->dev, "no platform_data passed,"
1115 " PHY search on MAC0\n");
bd2302c2
FF
1116 aup->phy1_search_mac0 = 1;
1117 } else {
f6673653
ML
1118 if (is_valid_ether_addr(pd->mac))
1119 memcpy(dev->dev_addr, pd->mac, 6);
1120
bd2302c2
FF
1121 aup->phy_static_config = pd->phy_static_config;
1122 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1123 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1124 aup->phy_addr = pd->phy_addr;
1125 aup->phy_busid = pd->phy_busid;
1126 aup->phy_irq = pd->phy_irq;
1127 }
1128
1129 if (aup->phy_busid && aup->phy_busid > 0) {
18b8e15b 1130 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
bd2302c2
FF
1131 err = -ENODEV;
1132 goto err_mdiobus_alloc;
1133 }
1134
5ef3041e 1135 aup->mii_bus = mdiobus_alloc();
bd2302c2 1136 if (aup->mii_bus == NULL) {
5368c726 1137 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
bd2302c2
FF
1138 err = -ENOMEM;
1139 goto err_mdiobus_alloc;
1140 }
5ef3041e
FF
1141
1142 aup->mii_bus->priv = dev;
1143 aup->mii_bus->read = au1000_mdiobus_read;
1144 aup->mii_bus->write = au1000_mdiobus_write;
1145 aup->mii_bus->reset = au1000_mdiobus_reset;
1146 aup->mii_bus->name = "au1000_eth_mii";
1147 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
1148 aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
dcbfef82 1149 if (aup->mii_bus->irq == NULL)
1150 goto err_out;
1151
2cc3c6b1 1152 for (i = 0; i < PHY_MAX_ADDR; ++i)
5ef3041e 1153 aup->mii_bus->irq[i] = PHY_POLL;
5ef3041e 1154 /* if known, set corresponding PHY IRQs */
bd2302c2
FF
1155 if (aup->phy_static_config)
1156 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1157 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1158
1159 err = mdiobus_register(aup->mii_bus);
1160 if (err) {
5368c726 1161 dev_err(&pdev->dev, "failed to register MDIO bus\n");
bd2302c2
FF
1162 goto err_mdiobus_reg;
1163 }
5ef3041e 1164
eb049630 1165 if (au1000_mii_probe(dev) != 0)
5ef3041e 1166 goto err_out;
5ef3041e
FF
1167
1168 pDBfree = NULL;
1169 /* setup the data buffer descriptors and attach a buffer to each one */
1170 pDB = aup->db;
1171 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1172 pDB->pnext = pDBfree;
1173 pDBfree = pDB;
1174 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1175 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1176 pDB++;
1177 }
1178 aup->pDBfree = pDBfree;
1179
1180 for (i = 0; i < NUM_RX_DMA; i++) {
eb049630 1181 pDB = au1000_GetFreeDB(aup);
ec7eabdd 1182 if (!pDB)
5ef3041e 1183 goto err_out;
ec7eabdd 1184
5ef3041e
FF
1185 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1186 aup->rx_db_inuse[i] = pDB;
1187 }
1188 for (i = 0; i < NUM_TX_DMA; i++) {
eb049630 1189 pDB = au1000_GetFreeDB(aup);
ec7eabdd 1190 if (!pDB)
5ef3041e 1191 goto err_out;
ec7eabdd 1192
5ef3041e
FF
1193 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1194 aup->tx_dma_ring[i]->len = 0;
1195 aup->tx_db_inuse[i] = pDB;
1196 }
1197
bd2302c2
FF
1198 dev->base_addr = base->start;
1199 dev->irq = irq;
1200 dev->netdev_ops = &au1000_netdev_ops;
1201 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1202 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1203
5ef3041e
FF
1204 /*
1205 * The boot code uses the ethernet controller, so reset it to start
1206 * fresh. au1000_init() expects that the device is in reset state.
1207 */
eb049630 1208 au1000_reset_mac(dev);
5ef3041e 1209
bd2302c2
FF
1210 err = register_netdev(dev);
1211 if (err) {
5368c726 1212 netdev_err(dev, "Cannot register net device, aborting.\n");
bd2302c2
FF
1213 goto err_out;
1214 }
1215
5368c726
FF
1216 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1217 (unsigned long)base->start, irq);
bd2302c2 1218 if (version_printed++ == 0)
215e17be
FF
1219 pr_info("%s version %s %s\n",
1220 DRV_NAME, DRV_VERSION, DRV_AUTHOR);
bd2302c2
FF
1221
1222 return 0;
5ef3041e
FF
1223
1224err_out:
bd2302c2 1225 if (aup->mii_bus != NULL)
5ef3041e 1226 mdiobus_unregister(aup->mii_bus);
5ef3041e
FF
1227
1228 /* here we should have a valid dev plus aup-> register addresses
1229 * so we can reset the mac properly.*/
eb049630 1230 au1000_reset_mac(dev);
5ef3041e
FF
1231
1232 for (i = 0; i < NUM_RX_DMA; i++) {
1233 if (aup->rx_db_inuse[i])
eb049630 1234 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
5ef3041e
FF
1235 }
1236 for (i = 0; i < NUM_TX_DMA; i++) {
1237 if (aup->tx_db_inuse[i])
eb049630 1238 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
5ef3041e 1239 }
bd2302c2
FF
1240err_mdiobus_reg:
1241 mdiobus_free(aup->mii_bus);
1242err_mdiobus_alloc:
1243 iounmap(aup->enable);
1244err_remap2:
1245 iounmap(aup->mac);
1246err_remap1:
5ef3041e
FF
1247 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1248 (void *)aup->vaddr, aup->dma_addr);
bd2302c2 1249err_vaddr:
5ef3041e 1250 free_netdev(dev);
bd2302c2
FF
1251err_alloc:
1252 release_mem_region(macen->start, resource_size(macen));
1253err_request:
1254 release_mem_region(base->start, resource_size(base));
1255out:
1256 return err;
5ef3041e
FF
1257}
1258
bd2302c2 1259static int __devexit au1000_remove(struct platform_device *pdev)
5ef3041e 1260{
bd2302c2
FF
1261 struct net_device *dev = platform_get_drvdata(pdev);
1262 struct au1000_private *aup = netdev_priv(dev);
1263 int i;
1264 struct resource *base, *macen;
5ef3041e 1265
bd2302c2
FF
1266 platform_set_drvdata(pdev, NULL);
1267
1268 unregister_netdev(dev);
1269 mdiobus_unregister(aup->mii_bus);
1270 mdiobus_free(aup->mii_bus);
1271
1272 for (i = 0; i < NUM_RX_DMA; i++)
1273 if (aup->rx_db_inuse[i])
eb049630 1274 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
bd2302c2
FF
1275
1276 for (i = 0; i < NUM_TX_DMA; i++)
1277 if (aup->tx_db_inuse[i])
eb049630 1278 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
bd2302c2
FF
1279
1280 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1281 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1282 (void *)aup->vaddr, aup->dma_addr);
1283
1284 iounmap(aup->mac);
1285 iounmap(aup->enable);
1286
1287 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1288 release_mem_region(base->start, resource_size(base));
1289
1290 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1291 release_mem_region(macen->start, resource_size(macen));
1292
1293 free_netdev(dev);
5ef3041e 1294
5ef3041e
FF
1295 return 0;
1296}
1297
bd2302c2
FF
1298static struct platform_driver au1000_eth_driver = {
1299 .probe = au1000_probe,
1300 .remove = __devexit_p(au1000_remove),
1301 .driver = {
1302 .name = "au1000-eth",
1303 .owner = THIS_MODULE,
1304 },
1305};
1306MODULE_ALIAS("platform:au1000-eth");
1307
1308
1309static int __init au1000_init_module(void)
1310{
1311 return platform_driver_register(&au1000_eth_driver);
1312}
1313
1314static void __exit au1000_exit_module(void)
5ef3041e 1315{
bd2302c2 1316 platform_driver_unregister(&au1000_eth_driver);
5ef3041e
FF
1317}
1318
1da177e4 1319module_init(au1000_init_module);
bd2302c2 1320module_exit(au1000_exit_module);