]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/atlx/atl2.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
vlan: Don't check for vlan group before vlan_tx_tag_present.
[net-next-2.6.git] / drivers / net / atlx / atl2.c
CommitLineData
452c1ce2
CS		 1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <asm/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
5a0e3ad6 42#include <linux/slab.h>
452c1ce2
CS		 43#include <linux/spinlock.h>
44#include <linux/string.h>
45#include <linux/tcp.h>
46#include <linux/timer.h>
47#include <linux/types.h>
48#include <linux/workqueue.h>
49
50#include "atl2.h"
51
52#define ATL2_DRV_VERSION "2.2.3"
53
f27e21a8 54static const char atl2_driver_name[] = "atl2";
452c1ce2 55static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
f27e21a8
SH		 56static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
57static const char atl2_driver_version[] = ATL2_DRV_VERSION;
452c1ce2
CS		 58
59MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
60MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(ATL2_DRV_VERSION);
63
64/*
65 * atl2_pci_tbl - PCI Device ID Table
66 */
a3aa1884 67static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = {
452c1ce2
CS		 68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
69 /* required last entry */
70 {0,}
71};
72MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
73
74static void atl2_set_ethtool_ops(struct net_device *netdev);
75
76static void atl2_check_options(struct atl2_adapter *adapter);
77
78/*
79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
80 * @adapter: board private structure to initialize
81 *
82 * atl2_sw_init initializes the Adapter private data structure.
83 * Fields are initialized based on PCI device information and
84 * OS network device settings (MTU size).
85 */
86static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
87{
88 struct atl2_hw *hw = &adapter->hw;
89 struct pci_dev *pdev = adapter->pdev;
90
91 /* PCI config space info */
92 hw->vendor_id = pdev->vendor;
93 hw->device_id = pdev->device;
94 hw->subsystem_vendor_id = pdev->subsystem_vendor;
95 hw->subsystem_id = pdev->subsystem_device;
96
97 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
99
100 adapter->wol = 0;
101 adapter->ict = 50000; /* ~100ms */
102 adapter->link_speed = SPEED_0; /* hardware init */
103 adapter->link_duplex = FULL_DUPLEX;
104
105 hw->phy_configured = false;
106 hw->preamble_len = 7;
107 hw->ipgt = 0x60;
108 hw->min_ifg = 0x50;
109 hw->ipgr1 = 0x40;
110 hw->ipgr2 = 0x60;
111 hw->retry_buf = 2;
112 hw->max_retry = 0xf;
113 hw->lcol = 0x37;
114 hw->jam_ipg = 7;
115 hw->fc_rxd_hi = 0;
116 hw->fc_rxd_lo = 0;
117 hw->max_frame_size = adapter->netdev->mtu;
118
119 spin_lock_init(&adapter->stats_lock);
452c1ce2
CS		 120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124}
125
126/*
127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135static void atl2_set_multi(struct net_device *netdev)
136{
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
22bedad3 139 struct netdev_hw_addr *ha;
452c1ce2
CS		 140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
22bedad3
JP		 161 netdev_for_each_mc_addr(ha, netdev) {
162 hash_value = atl2_hash_mc_addr(hw, ha->addr);
452c1ce2
CS		 163 atl2_hash_set(hw, hash_value);
164 }
165}
166
167static void init_ring_ptrs(struct atl2_adapter *adapter)
168{
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178}
179
180/*
181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186static int atl2_configure(struct atl2_adapter *adapter)
187{
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222/*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225*/
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284}
285
286/*
287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293{
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
314 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
315 offset);
316
317 /* Init TXS Ring */
318 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
319 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
320 adapter->txs_dma += offset;
321 adapter->txs_ring = (struct tx_pkt_status *)
322 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
323
324 /* Init RXD Ring */
325 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
326 offset = (adapter->rxd_dma & 127) ?
327 (128 - (adapter->rxd_dma & 127)) : 0;
328 if (offset > 7)
329 offset -= 8;
330 else
331 offset += (128 - 8);
332
333 adapter->rxd_dma += offset;
334 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
335 (adapter->txs_ring_size * 4 + offset));
336
337/*
338 * Read / Write Ptr Initialize:
339 * init_ring_ptrs(adapter);
340 */
341 return 0;
342}
343
344/*
345 * atl2_irq_enable - Enable default interrupt generation settings
346 * @adapter: board private structure
347 */
348static inline void atl2_irq_enable(struct atl2_adapter *adapter)
349{
350 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
351 ATL2_WRITE_FLUSH(&adapter->hw);
352}
353
354/*
355 * atl2_irq_disable - Mask off interrupt generation on the NIC
356 * @adapter: board private structure
357 */
358static inline void atl2_irq_disable(struct atl2_adapter *adapter)
359{
360 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
361 ATL2_WRITE_FLUSH(&adapter->hw);
362 synchronize_irq(adapter->pdev->irq);
363}
364
365#ifdef NETIF_F_HW_VLAN_TX
366static void atl2_vlan_rx_register(struct net_device *netdev,
367 struct vlan_group *grp)
368{
369 struct atl2_adapter *adapter = netdev_priv(netdev);
370 u32 ctrl;
371
372 atl2_irq_disable(adapter);
373 adapter->vlgrp = grp;
374
375 if (grp) {
376 /* enable VLAN tag insert/strip */
377 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
378 ctrl |= MAC_CTRL_RMV_VLAN;
379 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
380 } else {
381 /* disable VLAN tag insert/strip */
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 ctrl &= ~MAC_CTRL_RMV_VLAN;
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385 }
386
387 atl2_irq_enable(adapter);
388}
389
390static void atl2_restore_vlan(struct atl2_adapter *adapter)
391{
392 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
393}
394#endif
395
396static void atl2_intr_rx(struct atl2_adapter *adapter)
397{
398 struct net_device *netdev = adapter->netdev;
399 struct rx_desc *rxd;
400 struct sk_buff *skb;
401
402 do {
403 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
404 if (!rxd->status.update)
405 break; /* end of tx */
406
407 /* clear this flag at once */
408 rxd->status.update = 0;
409
410 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
411 int rx_size = (int)(rxd->status.pkt_size - 4);
412 /* alloc new buffer */
89d71a66 413 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
452c1ce2
CS		 414 if (NULL == skb) {
415 printk(KERN_WARNING
416 "%s: Mem squeeze, deferring packet.\n",
417 netdev->name);
418 /*
419 * Check that some rx space is free. If not,
420 * free one and mark stats->rx_dropped++.
421 */
02e71731 422 netdev->stats.rx_dropped++;
452c1ce2
CS		 423 break;
424 }
452c1ce2
CS		 425 memcpy(skb->data, rxd->packet, rx_size);
426 skb_put(skb, rx_size);
427 skb->protocol = eth_type_trans(skb, netdev);
428#ifdef NETIF_F_HW_VLAN_TX
429 if (adapter->vlgrp && (rxd->status.vlan)) {
430 u16 vlan_tag = (rxd->status.vtag>>4) |
431 ((rxd->status.vtag&7) << 13) |
432 ((rxd->status.vtag&8) << 9);
433 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
434 } else
435#endif
436 netif_rx(skb);
02e71731
SH		 437 netdev->stats.rx_bytes += rx_size;
438 netdev->stats.rx_packets++;
452c1ce2 439 } else {
02e71731 440 netdev->stats.rx_errors++;
452c1ce2
CS		 441
442 if (rxd->status.ok && rxd->status.pkt_size <= 60)
02e71731 443 netdev->stats.rx_length_errors++;
452c1ce2 444 if (rxd->status.mcast)
02e71731 445 netdev->stats.multicast++;
452c1ce2 446 if (rxd->status.crc)
02e71731 447 netdev->stats.rx_crc_errors++;
452c1ce2 448 if (rxd->status.align)
02e71731 449 netdev->stats.rx_frame_errors++;
452c1ce2
CS		 450 }
451
452 /* advance write ptr */
453 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
454 adapter->rxd_write_ptr = 0;
455 } while (1);
456
457 /* update mailbox? */
458 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
459 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
460}
461
462static void atl2_intr_tx(struct atl2_adapter *adapter)
463{
02e71731 464 struct net_device *netdev = adapter->netdev;
452c1ce2
CS		 465 u32 txd_read_ptr;
466 u32 txs_write_ptr;
467 struct tx_pkt_status *txs;
468 struct tx_pkt_header *txph;
469 int free_hole = 0;
470
471 do {
472 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
473 txs = adapter->txs_ring + txs_write_ptr;
474 if (!txs->update)
475 break; /* tx stop here */
476
477 free_hole = 1;
478 txs->update = 0;
479
480 if (++txs_write_ptr == adapter->txs_ring_size)
481 txs_write_ptr = 0;
482 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
483
484 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
485 txph = (struct tx_pkt_header *)
486 (((u8 *)adapter->txd_ring) + txd_read_ptr);
487
488 if (txph->pkt_size != txs->pkt_size) {
489 struct tx_pkt_status *old_txs = txs;
490 printk(KERN_WARNING
491 "%s: txs packet size not consistent with txd"
492 " txd_:0x%08x, txs_:0x%08x!\n",
493 adapter->netdev->name,
494 *(u32 *)txph, *(u32 *)txs);
495 printk(KERN_WARNING
496 "txd read ptr: 0x%x\n",
497 txd_read_ptr);
498 txs = adapter->txs_ring + txs_write_ptr;
499 printk(KERN_WARNING
500 "txs-behind:0x%08x\n",
501 *(u32 *)txs);
502 if (txs_write_ptr < 2) {
503 txs = adapter->txs_ring +
504 (adapter->txs_ring_size +
505 txs_write_ptr - 2);
506 } else {
507 txs = adapter->txs_ring + (txs_write_ptr - 2);
508 }
509 printk(KERN_WARNING
510 "txs-before:0x%08x\n",
511 *(u32 *)txs);
512 txs = old_txs;
513 }
514
515 /* 4for TPH */
516 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
517 if (txd_read_ptr >= adapter->txd_ring_size)
518 txd_read_ptr -= adapter->txd_ring_size;
519
520 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
521
522 /* tx statistics: */
e2f092ff 523 if (txs->ok) {
02e71731
SH		 524 netdev->stats.tx_bytes += txs->pkt_size;
525 netdev->stats.tx_packets++;
e2f092ff 526 }
452c1ce2 527 else
02e71731 528 netdev->stats.tx_errors++;
452c1ce2
CS		 529
530 if (txs->defer)
02e71731 531 netdev->stats.collisions++;
452c1ce2 532 if (txs->abort_col)
02e71731 533 netdev->stats.tx_aborted_errors++;
452c1ce2 534 if (txs->late_col)
02e71731 535 netdev->stats.tx_window_errors++;
452c1ce2 536 if (txs->underun)
02e71731 537 netdev->stats.tx_fifo_errors++;
452c1ce2
CS		 538 } while (1);
539
540 if (free_hole) {
541 if (netif_queue_stopped(adapter->netdev) &&
542 netif_carrier_ok(adapter->netdev))
543 netif_wake_queue(adapter->netdev);
544 }
545}
546
547static void atl2_check_for_link(struct atl2_adapter *adapter)
548{
549 struct net_device *netdev = adapter->netdev;
550 u16 phy_data = 0;
551
552 spin_lock(&adapter->stats_lock);
553 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
555 spin_unlock(&adapter->stats_lock);
556
557 /* notify upper layer link down ASAP */
558 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
559 if (netif_carrier_ok(netdev)) { /* old link state: Up */
560 printk(KERN_INFO "%s: %s NIC Link is Down\n",
561 atl2_driver_name, netdev->name);
562 adapter->link_speed = SPEED_0;
563 netif_carrier_off(netdev);
564 netif_stop_queue(netdev);
565 }
566 }
567 schedule_work(&adapter->link_chg_task);
568}
569
570static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
571{
572 u16 phy_data;
573 spin_lock(&adapter->stats_lock);
574 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
575 spin_unlock(&adapter->stats_lock);
576}
577
578/*
579 * atl2_intr - Interrupt Handler
580 * @irq: interrupt number
581 * @data: pointer to a network interface device structure
582 * @pt_regs: CPU registers structure
583 */
584static irqreturn_t atl2_intr(int irq, void *data)
585{
586 struct atl2_adapter *adapter = netdev_priv(data);
587 struct atl2_hw *hw = &adapter->hw;
588 u32 status;
589
590 status = ATL2_READ_REG(hw, REG_ISR);
591 if (0 == status)
592 return IRQ_NONE;
593
594 /* link event */
595 if (status & ISR_PHY)
596 atl2_clear_phy_int(adapter);
597
598 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
599 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
600
601 /* check if PCIE PHY Link down */
602 if (status & ISR_PHY_LINKDOWN) {
603 if (netif_running(adapter->netdev)) { /* reset MAC */
604 ATL2_WRITE_REG(hw, REG_ISR, 0);
605 ATL2_WRITE_REG(hw, REG_IMR, 0);
606 ATL2_WRITE_FLUSH(hw);
607 schedule_work(&adapter->reset_task);
608 return IRQ_HANDLED;
609 }
610 }
611
612 /* check if DMA read/write error? */
613 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
614 ATL2_WRITE_REG(hw, REG_ISR, 0);
615 ATL2_WRITE_REG(hw, REG_IMR, 0);
616 ATL2_WRITE_FLUSH(hw);
617 schedule_work(&adapter->reset_task);
618 return IRQ_HANDLED;
619 }
620
621 /* link event */
622 if (status & (ISR_PHY | ISR_MANUAL)) {
02e71731 623 adapter->netdev->stats.tx_carrier_errors++;
452c1ce2
CS		 624 atl2_check_for_link(adapter);
625 }
626
627 /* transmit event */
628 if (status & ISR_TX_EVENT)
629 atl2_intr_tx(adapter);
630
631 /* rx exception */
632 if (status & ISR_RX_EVENT)
633 atl2_intr_rx(adapter);
634
635 /* re-enable Interrupt */
636 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
637 return IRQ_HANDLED;
638}
639
640static int atl2_request_irq(struct atl2_adapter *adapter)
641{
642 struct net_device *netdev = adapter->netdev;
643 int flags, err = 0;
644
645 flags = IRQF_SHARED;
452c1ce2
CS		 646 adapter->have_msi = true;
647 err = pci_enable_msi(adapter->pdev);
648 if (err)
649 adapter->have_msi = false;
650
651 if (adapter->have_msi)
652 flags &= ~IRQF_SHARED;
452c1ce2 653
a0607fd3 654 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
452c1ce2
CS		 655 netdev);
656}
657
658/*
659 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
660 * @adapter: board private structure
661 *
662 * Free all transmit software resources
663 */
664static void atl2_free_ring_resources(struct atl2_adapter *adapter)
665{
666 struct pci_dev *pdev = adapter->pdev;
667 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
668 adapter->ring_dma);
669}
670
671/*
672 * atl2_open - Called when a network interface is made active
673 * @netdev: network interface device structure
674 *
675 * Returns 0 on success, negative value on failure
676 *
677 * The open entry point is called when a network interface is made
678 * active by the system (IFF_UP). At this point all resources needed
679 * for transmit and receive operations are allocated, the interrupt
680 * handler is registered with the OS, the watchdog timer is started,
681 * and the stack is notified that the interface is ready.
682 */
683static int atl2_open(struct net_device *netdev)
684{
685 struct atl2_adapter *adapter = netdev_priv(netdev);
686 int err;
687 u32 val;
688
689 /* disallow open during test */
690 if (test_bit(__ATL2_TESTING, &adapter->flags))
691 return -EBUSY;
692
693 /* allocate transmit descriptors */
694 err = atl2_setup_ring_resources(adapter);
695 if (err)
696 return err;
697
698 err = atl2_init_hw(&adapter->hw);
699 if (err) {
700 err = -EIO;
701 goto err_init_hw;
702 }
703
704 /* hardware has been reset, we need to reload some things */
705 atl2_set_multi(netdev);
706 init_ring_ptrs(adapter);
707
708#ifdef NETIF_F_HW_VLAN_TX
709 atl2_restore_vlan(adapter);
710#endif
711
712 if (atl2_configure(adapter)) {
713 err = -EIO;
714 goto err_config;
715 }
716
717 err = atl2_request_irq(adapter);
718 if (err)
719 goto err_req_irq;
720
721 clear_bit(__ATL2_DOWN, &adapter->flags);
722
e053b628 723 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
452c1ce2
CS		 724
725 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
726 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
727 val | MASTER_CTRL_MANUAL_INT);
728
729 atl2_irq_enable(adapter);
730
731 return 0;
732
733err_init_hw:
734err_req_irq:
735err_config:
736 atl2_free_ring_resources(adapter);
737 atl2_reset_hw(&adapter->hw);
738
739 return err;
740}
741
742static void atl2_down(struct atl2_adapter *adapter)
743{
744 struct net_device *netdev = adapter->netdev;
745
746 /* signal that we're down so the interrupt handler does not
747 * reschedule our watchdog timer */
748 set_bit(__ATL2_DOWN, &adapter->flags);
749
452c1ce2 750 netif_tx_disable(netdev);
452c1ce2
CS		 751
752 /* reset MAC to disable all RX/TX */
753 atl2_reset_hw(&adapter->hw);
754 msleep(1);
755
756 atl2_irq_disable(adapter);
757
758 del_timer_sync(&adapter->watchdog_timer);
759 del_timer_sync(&adapter->phy_config_timer);
760 clear_bit(0, &adapter->cfg_phy);
761
762 netif_carrier_off(netdev);
763 adapter->link_speed = SPEED_0;
764 adapter->link_duplex = -1;
765}
766
767static void atl2_free_irq(struct atl2_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770
771 free_irq(adapter->pdev->irq, netdev);
772
773#ifdef CONFIG_PCI_MSI
774 if (adapter->have_msi)
775 pci_disable_msi(adapter->pdev);
776#endif
777}
778
779/*
780 * atl2_close - Disables a network interface
781 * @netdev: network interface device structure
782 *
783 * Returns 0, this is not allowed to fail
784 *
785 * The close entry point is called when an interface is de-activated
786 * by the OS. The hardware is still under the drivers control, but
787 * needs to be disabled. A global MAC reset is issued to stop the
788 * hardware, and all transmit and receive resources are freed.
789 */
790static int atl2_close(struct net_device *netdev)
791{
792 struct atl2_adapter *adapter = netdev_priv(netdev);
793
794 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
795
796 atl2_down(adapter);
797 atl2_free_irq(adapter);
798 atl2_free_ring_resources(adapter);
799
800 return 0;
801}
802
803static inline int TxsFreeUnit(struct atl2_adapter *adapter)
804{
805 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
806
807 return (adapter->txs_next_clear >= txs_write_ptr) ?
808 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
809 txs_write_ptr - 1) :
810 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
811}
812
813static inline int TxdFreeBytes(struct atl2_adapter *adapter)
814{
815 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
816
817 return (adapter->txd_write_ptr >= txd_read_ptr) ?
818 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
819 txd_read_ptr - 1) :
820 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
821}
822
61357325
SH		 823static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
824 struct net_device *netdev)
452c1ce2
CS		 825{
826 struct atl2_adapter *adapter = netdev_priv(netdev);
452c1ce2
CS		 827 struct tx_pkt_header *txph;
828 u32 offset, copy_len;
829 int txs_unused;
830 int txbuf_unused;
831
832 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
833 dev_kfree_skb_any(skb);
834 return NETDEV_TX_OK;
835 }
836
837 if (unlikely(skb->len <= 0)) {
838 dev_kfree_skb_any(skb);
839 return NETDEV_TX_OK;
840 }
841
452c1ce2
CS		 842 txs_unused = TxsFreeUnit(adapter);
843 txbuf_unused = TxdFreeBytes(adapter);
844
845 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
846 txs_unused < 1) {
847 /* not enough resources */
848 netif_stop_queue(netdev);
452c1ce2
CS		 849 return NETDEV_TX_BUSY;
850 }
851
852 offset = adapter->txd_write_ptr;
853
854 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
855
856 *(u32 *)txph = 0;
857 txph->pkt_size = skb->len;
858
859 offset += 4;
860 if (offset >= adapter->txd_ring_size)
861 offset -= adapter->txd_ring_size;
862 copy_len = adapter->txd_ring_size - offset;
863 if (copy_len >= skb->len) {
864 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
865 offset += ((u32)(skb->len + 3) & ~3);
866 } else {
867 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
868 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
869 skb->len-copy_len);
870 offset = ((u32)(skb->len-copy_len + 3) & ~3);
871 }
872#ifdef NETIF_F_HW_VLAN_TX
eab6d18d 873 if (vlan_tx_tag_present(skb)) {
452c1ce2
CS		 874 u16 vlan_tag = vlan_tx_tag_get(skb);
875 vlan_tag = (vlan_tag << 4) |
876 (vlan_tag >> 13) |
877 ((vlan_tag >> 9) & 0x8);
878 txph->ins_vlan = 1;
879 txph->vlan = vlan_tag;
880 }
881#endif
882 if (offset >= adapter->txd_ring_size)
883 offset -= adapter->txd_ring_size;
884 adapter->txd_write_ptr = offset;
885
886 /* clear txs before send */
887 adapter->txs_ring[adapter->txs_next_clear].update = 0;
888 if (++adapter->txs_next_clear == adapter->txs_ring_size)
889 adapter->txs_next_clear = 0;
890
891 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
892 (adapter->txd_write_ptr >> 2));
893
87241840 894 mmiowb();
452c1ce2
CS		 895 dev_kfree_skb_any(skb);
896 return NETDEV_TX_OK;
897}
898
452c1ce2
CS		 899/*
900 * atl2_change_mtu - Change the Maximum Transfer Unit
901 * @netdev: network interface device structure
902 * @new_mtu: new value for maximum frame size
903 *
904 * Returns 0 on success, negative on failure
905 */
906static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
907{
908 struct atl2_adapter *adapter = netdev_priv(netdev);
909 struct atl2_hw *hw = &adapter->hw;
910
911 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
912 return -EINVAL;
913
914 /* set MTU */
915 if (hw->max_frame_size != new_mtu) {
916 netdev->mtu = new_mtu;
917 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
918 VLAN_SIZE + ETHERNET_FCS_SIZE);
919 }
920
921 return 0;
922}
923
924/*
925 * atl2_set_mac - Change the Ethernet Address of the NIC
926 * @netdev: network interface device structure
927 * @p: pointer to an address structure
928 *
929 * Returns 0 on success, negative on failure
930 */
931static int atl2_set_mac(struct net_device *netdev, void *p)
932{
933 struct atl2_adapter *adapter = netdev_priv(netdev);
934 struct sockaddr *addr = p;
935
936 if (!is_valid_ether_addr(addr->sa_data))
937 return -EADDRNOTAVAIL;
938
939 if (netif_running(netdev))
940 return -EBUSY;
941
942 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
943 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
944
945 atl2_set_mac_addr(&adapter->hw);
946
947 return 0;
948}
949
950/*
951 * atl2_mii_ioctl -
952 * @netdev:
953 * @ifreq:
954 * @cmd:
955 */
956static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
957{
958 struct atl2_adapter *adapter = netdev_priv(netdev);
959 struct mii_ioctl_data *data = if_mii(ifr);
960 unsigned long flags;
961
962 switch (cmd) {
963 case SIOCGMIIPHY:
964 data->phy_id = 0;
965 break;
966 case SIOCGMIIREG:
452c1ce2
CS		 967 spin_lock_irqsave(&adapter->stats_lock, flags);
968 if (atl2_read_phy_reg(&adapter->hw,
969 data->reg_num & 0x1F, &data->val_out)) {
970 spin_unlock_irqrestore(&adapter->stats_lock, flags);
971 return -EIO;
972 }
973 spin_unlock_irqrestore(&adapter->stats_lock, flags);
974 break;
975 case SIOCSMIIREG:
452c1ce2
CS		 976 if (data->reg_num & ~(0x1F))
977 return -EFAULT;
978 spin_lock_irqsave(&adapter->stats_lock, flags);
979 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
980 data->val_in)) {
981 spin_unlock_irqrestore(&adapter->stats_lock, flags);
982 return -EIO;
983 }
984 spin_unlock_irqrestore(&adapter->stats_lock, flags);
985 break;
986 default:
987 return -EOPNOTSUPP;
988 }
989 return 0;
990}
991
992/*
993 * atl2_ioctl -
994 * @netdev:
995 * @ifreq:
996 * @cmd:
997 */
998static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
999{
1000 switch (cmd) {
1001 case SIOCGMIIPHY:
1002 case SIOCGMIIREG:
1003 case SIOCSMIIREG:
1004 return atl2_mii_ioctl(netdev, ifr, cmd);
1005#ifdef ETHTOOL_OPS_COMPAT
1006 case SIOCETHTOOL:
1007 return ethtool_ioctl(ifr);
1008#endif
1009 default:
1010 return -EOPNOTSUPP;
1011 }
1012}
1013
1014/*
1015 * atl2_tx_timeout - Respond to a Tx Hang
1016 * @netdev: network interface device structure
1017 */
1018static void atl2_tx_timeout(struct net_device *netdev)
1019{
1020 struct atl2_adapter *adapter = netdev_priv(netdev);
1021
1022 /* Do the reset outside of interrupt context */
1023 schedule_work(&adapter->reset_task);
1024}
1025
1026/*
1027 * atl2_watchdog - Timer Call-back
1028 * @data: pointer to netdev cast into an unsigned long
1029 */
1030static void atl2_watchdog(unsigned long data)
1031{
1032 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
452c1ce2
CS		 1033
1034 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
02e71731
SH		 1035 u32 drop_rxd, drop_rxs;
1036 unsigned long flags;
1037
452c1ce2
CS		 1038 spin_lock_irqsave(&adapter->stats_lock, flags);
1039 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1040 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
452c1ce2
CS		 1041 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1042
02e71731
SH		 1043 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1044
452c1ce2 1045 /* Reset the timer */
e053b628
SH		 1046 mod_timer(&adapter->watchdog_timer,
1047 round_jiffies(jiffies + 4 * HZ));
452c1ce2
CS		 1048 }
1049}
1050
1051/*
1052 * atl2_phy_config - Timer Call-back
1053 * @data: pointer to netdev cast into an unsigned long
1054 */
1055static void atl2_phy_config(unsigned long data)
1056{
1057 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1058 struct atl2_hw *hw = &adapter->hw;
1059 unsigned long flags;
1060
1061 spin_lock_irqsave(&adapter->stats_lock, flags);
1062 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1063 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1064 MII_CR_RESTART_AUTO_NEG);
1065 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1066 clear_bit(0, &adapter->cfg_phy);
1067}
1068
1069static int atl2_up(struct atl2_adapter *adapter)
1070{
1071 struct net_device *netdev = adapter->netdev;
1072 int err = 0;
1073 u32 val;
1074
1075 /* hardware has been reset, we need to reload some things */
1076
1077 err = atl2_init_hw(&adapter->hw);
1078 if (err) {
1079 err = -EIO;
1080 return err;
1081 }
1082
1083 atl2_set_multi(netdev);
1084 init_ring_ptrs(adapter);
1085
1086#ifdef NETIF_F_HW_VLAN_TX
1087 atl2_restore_vlan(adapter);
1088#endif
1089
1090 if (atl2_configure(adapter)) {
1091 err = -EIO;
1092 goto err_up;
1093 }
1094
1095 clear_bit(__ATL2_DOWN, &adapter->flags);
1096
1097 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1098 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1099 MASTER_CTRL_MANUAL_INT);
1100
1101 atl2_irq_enable(adapter);
1102
1103err_up:
1104 return err;
1105}
1106
1107static void atl2_reinit_locked(struct atl2_adapter *adapter)
1108{
1109 WARN_ON(in_interrupt());
1110 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1111 msleep(1);
1112 atl2_down(adapter);
1113 atl2_up(adapter);
1114 clear_bit(__ATL2_RESETTING, &adapter->flags);
1115}
1116
1117static void atl2_reset_task(struct work_struct *work)
1118{
1119 struct atl2_adapter *adapter;
1120 adapter = container_of(work, struct atl2_adapter, reset_task);
1121
1122 atl2_reinit_locked(adapter);
1123}
1124
1125static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1126{
1127 u32 value;
1128 struct atl2_hw *hw = &adapter->hw;
1129 struct net_device *netdev = adapter->netdev;
1130
1131 /* Config MAC CTRL Register */
1132 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1133
1134 /* duplex */
1135 if (FULL_DUPLEX == adapter->link_duplex)
1136 value |= MAC_CTRL_DUPLX;
1137
1138 /* flow control */
1139 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1140
1141 /* PAD & CRC */
1142 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1143
1144 /* preamble length */
1145 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1146 MAC_CTRL_PRMLEN_SHIFT);
1147
1148 /* vlan */
1149 if (adapter->vlgrp)
1150 value |= MAC_CTRL_RMV_VLAN;
1151
1152 /* filter mode */
1153 value |= MAC_CTRL_BC_EN;
1154 if (netdev->flags & IFF_PROMISC)
1155 value |= MAC_CTRL_PROMIS_EN;
1156 else if (netdev->flags & IFF_ALLMULTI)
1157 value |= MAC_CTRL_MC_ALL_EN;
1158
1159 /* half retry buffer */
1160 value |= (((u32)(adapter->hw.retry_buf &
1161 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1162
1163 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1164}
1165
1166static int atl2_check_link(struct atl2_adapter *adapter)
1167{
1168 struct atl2_hw *hw = &adapter->hw;
1169 struct net_device *netdev = adapter->netdev;
1170 int ret_val;
1171 u16 speed, duplex, phy_data;
1172 int reconfig = 0;
1173
1174 /* MII_BMSR must read twise */
1175 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1176 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1177 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1178 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1179 u32 value;
1180 /* disable rx */
1181 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1182 value &= ~MAC_CTRL_RX_EN;
1183 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1184 adapter->link_speed = SPEED_0;
1185 netif_carrier_off(netdev);
1186 netif_stop_queue(netdev);
1187 }
1188 return 0;
1189 }
1190
1191 /* Link Up */
1192 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1193 if (ret_val)
1194 return ret_val;
1195 switch (hw->MediaType) {
1196 case MEDIA_TYPE_100M_FULL:
1197 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1198 reconfig = 1;
1199 break;
1200 case MEDIA_TYPE_100M_HALF:
1201 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1202 reconfig = 1;
1203 break;
1204 case MEDIA_TYPE_10M_FULL:
1205 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1206 reconfig = 1;
1207 break;
1208 case MEDIA_TYPE_10M_HALF:
1209 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1210 reconfig = 1;
1211 break;
1212 }
1213 /* link result is our setting */
1214 if (reconfig == 0) {
1215 if (adapter->link_speed != speed ||
1216 adapter->link_duplex != duplex) {
1217 adapter->link_speed = speed;
1218 adapter->link_duplex = duplex;
1219 atl2_setup_mac_ctrl(adapter);
1220 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1221 atl2_driver_name, netdev->name,
1222 adapter->link_speed,
1223 adapter->link_duplex == FULL_DUPLEX ?
1224 "Full Duplex" : "Half Duplex");
1225 }
1226
1227 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1228 netif_carrier_on(netdev);
1229 netif_wake_queue(netdev);
1230 }
1231 return 0;
1232 }
1233
1234 /* change original link status */
1235 if (netif_carrier_ok(netdev)) {
1236 u32 value;
1237 /* disable rx */
1238 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1239 value &= ~MAC_CTRL_RX_EN;
1240 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1241
1242 adapter->link_speed = SPEED_0;
1243 netif_carrier_off(netdev);
1244 netif_stop_queue(netdev);
1245 }
1246
1247 /* auto-neg, insert timer to re-config phy
1248 * (if interval smaller than 5 seconds, something strange) */
1249 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1250 if (!test_and_set_bit(0, &adapter->cfg_phy))
e053b628
SH		 1251 mod_timer(&adapter->phy_config_timer,
1252 round_jiffies(jiffies + 5 * HZ));
452c1ce2
CS		 1253 }
1254
1255 return 0;
1256}
1257
1258/*
1259 * atl2_link_chg_task - deal with link change event Out of interrupt context
1260 * @netdev: network interface device structure
1261 */
1262static void atl2_link_chg_task(struct work_struct *work)
1263{
1264 struct atl2_adapter *adapter;
1265 unsigned long flags;
1266
1267 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1268
1269 spin_lock_irqsave(&adapter->stats_lock, flags);
1270 atl2_check_link(adapter);
1271 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1272}
1273
1274static void atl2_setup_pcicmd(struct pci_dev *pdev)
1275{
1276 u16 cmd;
1277
1278 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1279
1280 if (cmd & PCI_COMMAND_INTX_DISABLE)
1281 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1282 if (cmd & PCI_COMMAND_IO)
1283 cmd &= ~PCI_COMMAND_IO;
1284 if (0 == (cmd & PCI_COMMAND_MEMORY))
1285 cmd |= PCI_COMMAND_MEMORY;
1286 if (0 == (cmd & PCI_COMMAND_MASTER))
1287 cmd |= PCI_COMMAND_MASTER;
1288 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1289
1290 /*
1291 * some motherboards BIOS(PXE/EFI) driver may set PME
1292 * while they transfer control to OS (Windows/Linux)
1293 * so we should clear this bit before NIC work normally
1294 */
1295 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1296}
1297
8d1b1fc9
KH		 1298#ifdef CONFIG_NET_POLL_CONTROLLER
1299static void atl2_poll_controller(struct net_device *netdev)
1300{
1301 disable_irq(netdev->irq);
1302 atl2_intr(netdev->irq, netdev);
1303 enable_irq(netdev->irq);
1304}
1305#endif
1306
825a84d1
SH		 1307
1308static const struct net_device_ops atl2_netdev_ops = {
1309 .ndo_open = atl2_open,
1310 .ndo_stop = atl2_close,
00829823 1311 .ndo_start_xmit = atl2_xmit_frame,
825a84d1
SH		 1312 .ndo_set_multicast_list = atl2_set_multi,
1313 .ndo_validate_addr = eth_validate_addr,
1314 .ndo_set_mac_address = atl2_set_mac,
1315 .ndo_change_mtu = atl2_change_mtu,
1316 .ndo_do_ioctl = atl2_ioctl,
1317 .ndo_tx_timeout = atl2_tx_timeout,
1318 .ndo_vlan_rx_register = atl2_vlan_rx_register,
1319#ifdef CONFIG_NET_POLL_CONTROLLER
1320 .ndo_poll_controller = atl2_poll_controller,
1321#endif
1322};
1323
452c1ce2
CS		 1324/*
1325 * atl2_probe - Device Initialization Routine
1326 * @pdev: PCI device information struct
1327 * @ent: entry in atl2_pci_tbl
1328 *
1329 * Returns 0 on success, negative on failure
1330 *
1331 * atl2_probe initializes an adapter identified by a pci_dev structure.
1332 * The OS initialization, configuring of the adapter private structure,
1333 * and a hardware reset occur.
1334 */
1335static int __devinit atl2_probe(struct pci_dev *pdev,
1336 const struct pci_device_id *ent)
1337{
1338 struct net_device *netdev;
1339 struct atl2_adapter *adapter;
1340 static int cards_found;
1341 unsigned long mmio_start;
1342 int mmio_len;
1343 int err;
1344
1345 cards_found = 0;
1346
1347 err = pci_enable_device(pdev);
1348 if (err)
1349 return err;
1350
1351 /*
1352 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1353 * until the kernel has the proper infrastructure to support 64-bit DMA
1354 * on these devices.
1355 */
284901a9
YH		 1356 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1357 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
452c1ce2
CS		 1358 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1359 goto err_dma;
1360 }
1361
1362 /* Mark all PCI regions associated with PCI device
1363 * pdev as being reserved by owner atl2_driver_name */
1364 err = pci_request_regions(pdev, atl2_driver_name);
1365 if (err)
1366 goto err_pci_reg;
1367
1368 /* Enables bus-mastering on the device and calls
1369 * pcibios_set_master to do the needed arch specific settings */
1370 pci_set_master(pdev);
1371
1372 err = -ENOMEM;
1373 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1374 if (!netdev)
1375 goto err_alloc_etherdev;
1376
1377 SET_NETDEV_DEV(netdev, &pdev->dev);
1378
1379 pci_set_drvdata(pdev, netdev);
1380 adapter = netdev_priv(netdev);
1381 adapter->netdev = netdev;
1382 adapter->pdev = pdev;
1383 adapter->hw.back = adapter;
1384
1385 mmio_start = pci_resource_start(pdev, 0x0);
1386 mmio_len = pci_resource_len(pdev, 0x0);
1387
1388 adapter->hw.mem_rang = (u32)mmio_len;
1389 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1390 if (!adapter->hw.hw_addr) {
1391 err = -EIO;
1392 goto err_ioremap;
1393 }
1394
1395 atl2_setup_pcicmd(pdev);
1396
825a84d1 1397 netdev->netdev_ops = &atl2_netdev_ops;
452c1ce2 1398 atl2_set_ethtool_ops(netdev);
452c1ce2 1399 netdev->watchdog_timeo = 5 * HZ;
452c1ce2
CS		 1400 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1401
1402 netdev->mem_start = mmio_start;
1403 netdev->mem_end = mmio_start + mmio_len;
1404 adapter->bd_number = cards_found;
1405 adapter->pci_using_64 = false;
1406
1407 /* setup the private structure */
1408 err = atl2_sw_init(adapter);
1409 if (err)
1410 goto err_sw_init;
1411
1412 err = -EIO;
1413
1414#ifdef NETIF_F_HW_VLAN_TX
1415 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1416#endif
1417
452c1ce2
CS		 1418 /* Init PHY as early as possible due to power saving issue */
1419 atl2_phy_init(&adapter->hw);
1420
1421 /* reset the controller to
1422 * put the device in a known good starting state */
1423
1424 if (atl2_reset_hw(&adapter->hw)) {
1425 err = -EIO;
1426 goto err_reset;
1427 }
1428
1429 /* copy the MAC address out of the EEPROM */
1430 atl2_read_mac_addr(&adapter->hw);
1431 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1432/* FIXME: do we still need this? */
1433#ifdef ETHTOOL_GPERMADDR
1434 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1435
1436 if (!is_valid_ether_addr(netdev->perm_addr)) {
1437#else
1438 if (!is_valid_ether_addr(netdev->dev_addr)) {
1439#endif
1440 err = -EIO;
1441 goto err_eeprom;
1442 }
1443
1444 atl2_check_options(adapter);
1445
1446 init_timer(&adapter->watchdog_timer);
c061b18d 1447 adapter->watchdog_timer.function = atl2_watchdog;
452c1ce2
CS		 1448 adapter->watchdog_timer.data = (unsigned long) adapter;
1449
1450 init_timer(&adapter->phy_config_timer);
c061b18d 1451 adapter->phy_config_timer.function = atl2_phy_config;
452c1ce2
CS		 1452 adapter->phy_config_timer.data = (unsigned long) adapter;
1453
1454 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1455 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1456
1457 strcpy(netdev->name, "eth%d"); /* ?? */
1458 err = register_netdev(netdev);
1459 if (err)
1460 goto err_register;
1461
1462 /* assume we have no link for now */
1463 netif_carrier_off(netdev);
1464 netif_stop_queue(netdev);
1465
1466 cards_found++;
1467
1468 return 0;
1469
1470err_reset:
1471err_register:
1472err_sw_init:
1473err_eeprom:
1474 iounmap(adapter->hw.hw_addr);
1475err_ioremap:
1476 free_netdev(netdev);
1477err_alloc_etherdev:
1478 pci_release_regions(pdev);
1479err_pci_reg:
1480err_dma:
1481 pci_disable_device(pdev);
1482 return err;
1483}
1484
1485/*
1486 * atl2_remove - Device Removal Routine
1487 * @pdev: PCI device information struct
1488 *
1489 * atl2_remove is called by the PCI subsystem to alert the driver
1490 * that it should release a PCI device. The could be caused by a
1491 * Hot-Plug event, or because the driver is going to be removed from
1492 * memory.
1493 */
1494/* FIXME: write the original MAC address back in case it was changed from a
1495 * BIOS-set value, as in atl1 -- CHS */
1496static void __devexit atl2_remove(struct pci_dev *pdev)
1497{
1498 struct net_device *netdev = pci_get_drvdata(pdev);
1499 struct atl2_adapter *adapter = netdev_priv(netdev);
1500
1501 /* flush_scheduled work may reschedule our watchdog task, so
1502 * explicitly disable watchdog tasks from being rescheduled */
1503 set_bit(__ATL2_DOWN, &adapter->flags);
1504
1505 del_timer_sync(&adapter->watchdog_timer);
1506 del_timer_sync(&adapter->phy_config_timer);
1507
1508 flush_scheduled_work();
1509
1510 unregister_netdev(netdev);
1511
1512 atl2_force_ps(&adapter->hw);
1513
1514 iounmap(adapter->hw.hw_addr);
1515 pci_release_regions(pdev);
1516
1517 free_netdev(netdev);
1518
1519 pci_disable_device(pdev);
1520}
1521
1522static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1523{
1524 struct net_device *netdev = pci_get_drvdata(pdev);
1525 struct atl2_adapter *adapter = netdev_priv(netdev);
1526 struct atl2_hw *hw = &adapter->hw;
1527 u16 speed, duplex;
1528 u32 ctrl = 0;
1529 u32 wufc = adapter->wol;
1530
1531#ifdef CONFIG_PM
1532 int retval = 0;
1533#endif
1534
1535 netif_device_detach(netdev);
1536
1537 if (netif_running(netdev)) {
1538 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1539 atl2_down(adapter);
1540 }
1541
1542#ifdef CONFIG_PM
1543 retval = pci_save_state(pdev);
1544 if (retval)
1545 return retval;
1546#endif
1547
1548 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1549 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1550 if (ctrl & BMSR_LSTATUS)
1551 wufc &= ~ATLX_WUFC_LNKC;
1552
1553 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1554 u32 ret_val;
1555 /* get current link speed & duplex */
1556 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1557 if (ret_val) {
1558 printk(KERN_DEBUG
1559 "%s: get speed&duplex error while suspend\n",
1560 atl2_driver_name);
1561 goto wol_dis;
1562 }
1563
1564 ctrl = 0;
1565
1566 /* turn on magic packet wol */
1567 if (wufc & ATLX_WUFC_MAG)
1568 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1569
1570 /* ignore Link Chg event when Link is up */
1571 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1572
1573 /* Config MAC CTRL Register */
1574 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1575 if (FULL_DUPLEX == adapter->link_duplex)
1576 ctrl |= MAC_CTRL_DUPLX;
1577 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1578 ctrl |= (((u32)adapter->hw.preamble_len &
1579 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1580 ctrl |= (((u32)(adapter->hw.retry_buf &
1581 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1582 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1583 if (wufc & ATLX_WUFC_MAG) {
1584 /* magic packet maybe Broadcast&multicast&Unicast */
1585 ctrl |= MAC_CTRL_BC_EN;
1586 }
1587
1588 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1589
1590 /* pcie patch */
1591 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1592 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1593 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1594 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1595 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1596 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1597
1598 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1599 goto suspend_exit;
1600 }
1601
1602 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1603 /* link is down, so only LINK CHG WOL event enable */
1604 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1605 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1606 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1607
1608 /* pcie patch */
1609 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1610 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1611 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1612 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1613 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1614 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1615
1616 hw->phy_configured = false; /* re-init PHY when resume */
1617
1618 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1619
1620 goto suspend_exit;
1621 }
1622
1623wol_dis:
1624 /* WOL disabled */
1625 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1626
1627 /* pcie patch */
1628 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1629 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1630 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1631 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1632 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1633 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1634
1635 atl2_force_ps(hw);
1636 hw->phy_configured = false; /* re-init PHY when resume */
1637
1638 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1639
1640suspend_exit:
1641 if (netif_running(netdev))
1642 atl2_free_irq(adapter);
1643
1644 pci_disable_device(pdev);
1645
1646 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1647
1648 return 0;
1649}
1650
1651#ifdef CONFIG_PM
1652static int atl2_resume(struct pci_dev *pdev)
1653{
1654 struct net_device *netdev = pci_get_drvdata(pdev);
1655 struct atl2_adapter *adapter = netdev_priv(netdev);
1656 u32 err;
1657
1658 pci_set_power_state(pdev, PCI_D0);
1659 pci_restore_state(pdev);
1660
1661 err = pci_enable_device(pdev);
1662 if (err) {
1663 printk(KERN_ERR
1664 "atl2: Cannot enable PCI device from suspend\n");
1665 return err;
1666 }
1667
1668 pci_set_master(pdev);
1669
1670 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1671
1672 pci_enable_wake(pdev, PCI_D3hot, 0);
1673 pci_enable_wake(pdev, PCI_D3cold, 0);
1674
1675 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1676
a849854f
AJ		 1677 if (netif_running(netdev)) {
1678 err = atl2_request_irq(adapter);
1679 if (err)
1680 return err;
1681 }
452c1ce2
CS		 1682
1683 atl2_reset_hw(&adapter->hw);
1684
1685 if (netif_running(netdev))
1686 atl2_up(adapter);
1687
1688 netif_device_attach(netdev);
1689
1690 return 0;
1691}
1692#endif
1693
1694static void atl2_shutdown(struct pci_dev *pdev)
1695{
1696 atl2_suspend(pdev, PMSG_SUSPEND);
1697}
1698
1699static struct pci_driver atl2_driver = {
1700 .name = atl2_driver_name,
1701 .id_table = atl2_pci_tbl,
1702 .probe = atl2_probe,
1703 .remove = __devexit_p(atl2_remove),
1704 /* Power Managment Hooks */
1705 .suspend = atl2_suspend,
1706#ifdef CONFIG_PM
1707 .resume = atl2_resume,
1708#endif
1709 .shutdown = atl2_shutdown,
1710};
1711
1712/*
1713 * atl2_init_module - Driver Registration Routine
1714 *
1715 * atl2_init_module is the first routine called when the driver is
1716 * loaded. All it does is register with the PCI subsystem.
1717 */
1718static int __init atl2_init_module(void)
1719{
1720 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1721 atl2_driver_version);
1722 printk(KERN_INFO "%s\n", atl2_copyright);
1723 return pci_register_driver(&atl2_driver);
1724}
1725module_init(atl2_init_module);
1726
1727/*
1728 * atl2_exit_module - Driver Exit Cleanup Routine
1729 *
1730 * atl2_exit_module is called just before the driver is removed
1731 * from memory.
1732 */
1733static void __exit atl2_exit_module(void)
1734{
1735 pci_unregister_driver(&atl2_driver);
1736}
1737module_exit(atl2_exit_module);
1738
1739static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1740{
1741 struct atl2_adapter *adapter = hw->back;
1742 pci_read_config_word(adapter->pdev, reg, value);
1743}
1744
1745static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1746{
1747 struct atl2_adapter *adapter = hw->back;
1748 pci_write_config_word(adapter->pdev, reg, *value);
1749}
1750
1751static int atl2_get_settings(struct net_device *netdev,
1752 struct ethtool_cmd *ecmd)
1753{
1754 struct atl2_adapter *adapter = netdev_priv(netdev);
1755 struct atl2_hw *hw = &adapter->hw;
1756
1757 ecmd->supported = (SUPPORTED_10baseT_Half |
1758 SUPPORTED_10baseT_Full |
1759 SUPPORTED_100baseT_Half |
1760 SUPPORTED_100baseT_Full |
1761 SUPPORTED_Autoneg |
1762 SUPPORTED_TP);
1763 ecmd->advertising = ADVERTISED_TP;
1764
1765 ecmd->advertising |= ADVERTISED_Autoneg;
1766 ecmd->advertising |= hw->autoneg_advertised;
1767
1768 ecmd->port = PORT_TP;
1769 ecmd->phy_address = 0;
1770 ecmd->transceiver = XCVR_INTERNAL;
1771
1772 if (adapter->link_speed != SPEED_0) {
1773 ecmd->speed = adapter->link_speed;
1774 if (adapter->link_duplex == FULL_DUPLEX)
1775 ecmd->duplex = DUPLEX_FULL;
1776 else
1777 ecmd->duplex = DUPLEX_HALF;
1778 } else {
1779 ecmd->speed = -1;
1780 ecmd->duplex = -1;
1781 }
1782
1783 ecmd->autoneg = AUTONEG_ENABLE;
1784 return 0;
1785}
1786
1787static int atl2_set_settings(struct net_device *netdev,
1788 struct ethtool_cmd *ecmd)
1789{
1790 struct atl2_adapter *adapter = netdev_priv(netdev);
1791 struct atl2_hw *hw = &adapter->hw;
1792
1793 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1794 msleep(1);
1795
1796 if (ecmd->autoneg == AUTONEG_ENABLE) {
1797#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1798 ADVERTISE_10_FULL | \
1799 ADVERTISE_100_HALF| \
1800 ADVERTISE_100_FULL)
1801
1802 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1803 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1804 hw->autoneg_advertised = MY_ADV_MASK;
1805 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1806 ADVERTISE_100_FULL) {
1807 hw->MediaType = MEDIA_TYPE_100M_FULL;
1808 hw->autoneg_advertised = ADVERTISE_100_FULL;
1809 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1810 ADVERTISE_100_HALF) {
1811 hw->MediaType = MEDIA_TYPE_100M_HALF;
1812 hw->autoneg_advertised = ADVERTISE_100_HALF;
1813 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1814 ADVERTISE_10_FULL) {
1815 hw->MediaType = MEDIA_TYPE_10M_FULL;
1816 hw->autoneg_advertised = ADVERTISE_10_FULL;
1817 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1818 ADVERTISE_10_HALF) {
1819 hw->MediaType = MEDIA_TYPE_10M_HALF;
1820 hw->autoneg_advertised = ADVERTISE_10_HALF;
1821 } else {
1822 clear_bit(__ATL2_RESETTING, &adapter->flags);
1823 return -EINVAL;
1824 }
1825 ecmd->advertising = hw->autoneg_advertised |
1826 ADVERTISED_TP | ADVERTISED_Autoneg;
1827 } else {
1828 clear_bit(__ATL2_RESETTING, &adapter->flags);
1829 return -EINVAL;
1830 }
1831
1832 /* reset the link */
1833 if (netif_running(adapter->netdev)) {
1834 atl2_down(adapter);
1835 atl2_up(adapter);
1836 } else
1837 atl2_reset_hw(&adapter->hw);
1838
1839 clear_bit(__ATL2_RESETTING, &adapter->flags);
1840 return 0;
1841}
1842
1843static u32 atl2_get_tx_csum(struct net_device *netdev)
1844{
1845 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1846}
1847
1848static u32 atl2_get_msglevel(struct net_device *netdev)
1849{
1850 return 0;
1851}
1852
1853/*
1854 * It's sane for this to be empty, but we might want to take advantage of this.
1855 */
1856static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1857{
1858}
1859
1860static int atl2_get_regs_len(struct net_device *netdev)
1861{
1862#define ATL2_REGS_LEN 42
1863 return sizeof(u32) * ATL2_REGS_LEN;
1864}
1865
1866static void atl2_get_regs(struct net_device *netdev,
1867 struct ethtool_regs *regs, void *p)
1868{
1869 struct atl2_adapter *adapter = netdev_priv(netdev);
1870 struct atl2_hw *hw = &adapter->hw;
1871 u32 *regs_buff = p;
1872 u16 phy_data;
1873
1874 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1875
1876 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1877
1878 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1879 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1880 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1881 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1882 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1883 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1884 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1885 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1886 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1887 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1888 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1889 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1890 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1891 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1892 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1893 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1894 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1895 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1896 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1897 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1898 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1899 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1900 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1901 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1902 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1903 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1904 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1905 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1906 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1907 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1908 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1909 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1910 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1911 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1912 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1913 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1914 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1915 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1916 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1917
1918 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1919 regs_buff[40] = (u32)phy_data;
1920 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1921 regs_buff[41] = (u32)phy_data;
1922}
1923
1924static int atl2_get_eeprom_len(struct net_device *netdev)
1925{
1926 struct atl2_adapter *adapter = netdev_priv(netdev);
1927
1928 if (!atl2_check_eeprom_exist(&adapter->hw))
1929 return 512;
1930 else
1931 return 0;
1932}
1933
1934static int atl2_get_eeprom(struct net_device *netdev,
1935 struct ethtool_eeprom *eeprom, u8 *bytes)
1936{
1937 struct atl2_adapter *adapter = netdev_priv(netdev);
1938 struct atl2_hw *hw = &adapter->hw;
1939 u32 *eeprom_buff;
1940 int first_dword, last_dword;
1941 int ret_val = 0;
1942 int i;
1943
1944 if (eeprom->len == 0)
1945 return -EINVAL;
1946
1947 if (atl2_check_eeprom_exist(hw))
1948 return -EINVAL;
1949
1950 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1951
1952 first_dword = eeprom->offset >> 2;
1953 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1954
1955 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1956 GFP_KERNEL);
1957 if (!eeprom_buff)
1958 return -ENOMEM;
1959
1960 for (i = first_dword; i < last_dword; i++) {
2467ab95
JS		 1961 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1962 ret_val = -EIO;
1963 goto free;
1964 }
452c1ce2
CS		 1965 }
1966
1967 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1968 eeprom->len);
2467ab95 1969free:
452c1ce2
CS		 1970 kfree(eeprom_buff);
1971
1972 return ret_val;
1973}
1974
1975static int atl2_set_eeprom(struct net_device *netdev,
1976 struct ethtool_eeprom *eeprom, u8 *bytes)
1977{
1978 struct atl2_adapter *adapter = netdev_priv(netdev);
1979 struct atl2_hw *hw = &adapter->hw;
1980 u32 *eeprom_buff;
1981 u32 *ptr;
1982 int max_len, first_dword, last_dword, ret_val = 0;
1983 int i;
1984
1985 if (eeprom->len == 0)
1986 return -EOPNOTSUPP;
1987
1988 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1989 return -EFAULT;
1990
1991 max_len = 512;
1992
1993 first_dword = eeprom->offset >> 2;
1994 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1995 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1996 if (!eeprom_buff)
1997 return -ENOMEM;
1998
1999 ptr = (u32 *)eeprom_buff;
2000
2001 if (eeprom->offset & 3) {
2002 /* need read/modify/write of first changed EEPROM word */
2003 /* only the second byte of the word is being modified */
2004 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2005 return -EIO;
2006 ptr++;
2007 }
2008 if (((eeprom->offset + eeprom->len) & 3)) {
2009 /*
2010 * need read/modify/write of last changed EEPROM word
2011 * only the first byte of the word is being modified
2012 */
2013 if (!atl2_read_eeprom(hw, last_dword * 4,
2014 &(eeprom_buff[last_dword - first_dword])))
2015 return -EIO;
2016 }
2017
2018 /* Device's eeprom is always little-endian, word addressable */
2019 memcpy(ptr, bytes, eeprom->len);
2020
2021 for (i = 0; i < last_dword - first_dword + 1; i++) {
2022 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2023 return -EIO;
2024 }
2025
2026 kfree(eeprom_buff);
2027 return ret_val;
2028}
2029
2030static void atl2_get_drvinfo(struct net_device *netdev,
2031 struct ethtool_drvinfo *drvinfo)
2032{
2033 struct atl2_adapter *adapter = netdev_priv(netdev);
2034
2035 strncpy(drvinfo->driver, atl2_driver_name, 32);
2036 strncpy(drvinfo->version, atl2_driver_version, 32);
2037 strncpy(drvinfo->fw_version, "L2", 32);
2038 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2039 drvinfo->n_stats = 0;
2040 drvinfo->testinfo_len = 0;
2041 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2042 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2043}
2044
2045static void atl2_get_wol(struct net_device *netdev,
2046 struct ethtool_wolinfo *wol)
2047{
2048 struct atl2_adapter *adapter = netdev_priv(netdev);
2049
2050 wol->supported = WAKE_MAGIC;
2051 wol->wolopts = 0;
2052
2053 if (adapter->wol & ATLX_WUFC_EX)
2054 wol->wolopts |= WAKE_UCAST;
2055 if (adapter->wol & ATLX_WUFC_MC)
2056 wol->wolopts |= WAKE_MCAST;
2057 if (adapter->wol & ATLX_WUFC_BC)
2058 wol->wolopts |= WAKE_BCAST;
2059 if (adapter->wol & ATLX_WUFC_MAG)
2060 wol->wolopts |= WAKE_MAGIC;
2061 if (adapter->wol & ATLX_WUFC_LNKC)
2062 wol->wolopts |= WAKE_PHY;
2063}
2064
2065static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2066{
2067 struct atl2_adapter *adapter = netdev_priv(netdev);
2068
2069 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2070 return -EOPNOTSUPP;
2071
41796e91 2072 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
452c1ce2
CS		 2073 return -EOPNOTSUPP;
2074
2075 /* these settings will always override what we currently have */
2076 adapter->wol = 0;
2077
2078 if (wol->wolopts & WAKE_MAGIC)
2079 adapter->wol |= ATLX_WUFC_MAG;
2080 if (wol->wolopts & WAKE_PHY)
2081 adapter->wol |= ATLX_WUFC_LNKC;
2082
2083 return 0;
2084}
2085
2086static int atl2_nway_reset(struct net_device *netdev)
2087{
2088 struct atl2_adapter *adapter = netdev_priv(netdev);
2089 if (netif_running(netdev))
2090 atl2_reinit_locked(adapter);
2091 return 0;
2092}
2093
0fc0b732 2094static const struct ethtool_ops atl2_ethtool_ops = {
452c1ce2
CS		 2095 .get_settings = atl2_get_settings,
2096 .set_settings = atl2_set_settings,
2097 .get_drvinfo = atl2_get_drvinfo,
2098 .get_regs_len = atl2_get_regs_len,
2099 .get_regs = atl2_get_regs,
2100 .get_wol = atl2_get_wol,
2101 .set_wol = atl2_set_wol,
2102 .get_msglevel = atl2_get_msglevel,
2103 .set_msglevel = atl2_set_msglevel,
2104 .nway_reset = atl2_nway_reset,
2105 .get_link = ethtool_op_get_link,
2106 .get_eeprom_len = atl2_get_eeprom_len,
2107 .get_eeprom = atl2_get_eeprom,
2108 .set_eeprom = atl2_set_eeprom,
2109 .get_tx_csum = atl2_get_tx_csum,
2110 .get_sg = ethtool_op_get_sg,
2111 .set_sg = ethtool_op_set_sg,
2112#ifdef NETIF_F_TSO
2113 .get_tso = ethtool_op_get_tso,
2114#endif
2115};
2116
2117static void atl2_set_ethtool_ops(struct net_device *netdev)
2118{
2119 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2120}
2121
2122#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2123 (((a) & 0xff00ff00) >> 8))
2124#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2125#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2126
2127/*
2128 * Reset the transmit and receive units; mask and clear all interrupts.
2129 *
2130 * hw - Struct containing variables accessed by shared code
2131 * return : 0 or idle status (if error)
2132 */
2133static s32 atl2_reset_hw(struct atl2_hw *hw)
2134{
2135 u32 icr;
2136 u16 pci_cfg_cmd_word;
2137 int i;
2138
2139 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2140 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2141 if ((pci_cfg_cmd_word &
2142 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2143 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2144 pci_cfg_cmd_word |=
2145 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2146 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2147 }
2148
2149 /* Clear Interrupt mask to stop board from generating
2150 * interrupts & Clear any pending interrupt events
2151 */
2152 /* FIXME */
2153 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2154 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2155
2156 /* Issue Soft Reset to the MAC. This will reset the chip's
2157 * transmit, receive, DMA. It will not effect
2158 * the current PCI configuration. The global reset bit is self-
2159 * clearing, and should clear within a microsecond.
2160 */
2161 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2162 wmb();
2163 msleep(1); /* delay about 1ms */
2164
2165 /* Wait at least 10ms for All module to be Idle */
2166 for (i = 0; i < 10; i++) {
2167 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2168 if (!icr)
2169 break;
2170 msleep(1); /* delay 1 ms */
2171 cpu_relax();
2172 }
2173
2174 if (icr)
2175 return icr;
2176
2177 return 0;
2178}
2179
2180#define CUSTOM_SPI_CS_SETUP 2
2181#define CUSTOM_SPI_CLK_HI 2
2182#define CUSTOM_SPI_CLK_LO 2
2183#define CUSTOM_SPI_CS_HOLD 2
2184#define CUSTOM_SPI_CS_HI 3
2185
2186static struct atl2_spi_flash_dev flash_table[] =
2187{
2188/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2189{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2190{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2191{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2192};
2193
2194static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2195{
2196 int i;
2197 u32 value;
2198
2199 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2200 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2201
2202 value = SPI_FLASH_CTRL_WAIT_READY |
2203 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2204 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2205 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2206 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2207 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2208 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2209 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2210 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2211 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2212 SPI_FLASH_CTRL_CS_HI_SHIFT |
2213 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2214
2215 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2216
2217 value |= SPI_FLASH_CTRL_START;
2218
2219 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2220
2221 for (i = 0; i < 10; i++) {
2222 msleep(1);
2223 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2224 if (!(value & SPI_FLASH_CTRL_START))
2225 break;
2226 }
2227
2228 if (value & SPI_FLASH_CTRL_START)
2229 return false;
2230
2231 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2232
2233 return true;
2234}
2235
2236/*
2237 * get_permanent_address
2238 * return 0 if get valid mac address,
2239 */
2240static int get_permanent_address(struct atl2_hw *hw)
2241{
2242 u32 Addr[2];
2243 u32 i, Control;
2244 u16 Register;
2245 u8 EthAddr[NODE_ADDRESS_SIZE];
2246 bool KeyValid;
2247
2248 if (is_valid_ether_addr(hw->perm_mac_addr))
2249 return 0;
2250
2251 Addr[0] = 0;
2252 Addr[1] = 0;
2253
2254 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2255 Register = 0;
2256 KeyValid = false;
2257
2258 /* Read out all EEPROM content */
2259 i = 0;
2260 while (1) {
2261 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2262 if (KeyValid) {
2263 if (Register == REG_MAC_STA_ADDR)
2264 Addr[0] = Control;
2265 else if (Register ==
2266 (REG_MAC_STA_ADDR + 4))
2267 Addr[1] = Control;
2268 KeyValid = false;
2269 } else if ((Control & 0xff) == 0x5A) {
2270 KeyValid = true;
2271 Register = (u16) (Control >> 16);
2272 } else {
2273 /* assume data end while encount an invalid KEYWORD */
2274 break;
2275 }
2276 } else {
2277 break; /* read error */
2278 }
2279 i += 4;
2280 }
2281
2282 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2283 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2284
2285 if (is_valid_ether_addr(EthAddr)) {
2286 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2287 return 0;
2288 }
2289 return 1;
2290 }
2291
2292 /* see if SPI flash exists? */
2293 Addr[0] = 0;
2294 Addr[1] = 0;
2295 Register = 0;
2296 KeyValid = false;
2297 i = 0;
2298 while (1) {
2299 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2300 if (KeyValid) {
2301 if (Register == REG_MAC_STA_ADDR)
2302 Addr[0] = Control;
2303 else if (Register == (REG_MAC_STA_ADDR + 4))
2304 Addr[1] = Control;
2305 KeyValid = false;
2306 } else if ((Control & 0xff) == 0x5A) {
2307 KeyValid = true;
2308 Register = (u16) (Control >> 16);
2309 } else {
2310 break; /* data end */
2311 }
2312 } else {
2313 break; /* read error */
2314 }
2315 i += 4;
2316 }
2317
2318 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2319 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2320 if (is_valid_ether_addr(EthAddr)) {
2321 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2322 return 0;
2323 }
2324 /* maybe MAC-address is from BIOS */
2325 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2326 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2327 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2328 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2329
2330 if (is_valid_ether_addr(EthAddr)) {
2331 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2332 return 0;
2333 }
2334
2335 return 1;
2336}
2337
2338/*
2339 * Reads the adapter's MAC address from the EEPROM
2340 *
2341 * hw - Struct containing variables accessed by shared code
2342 */
2343static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2344{
2345 u16 i;
2346
2347 if (get_permanent_address(hw)) {
2348 /* for test */
2349 /* FIXME: shouldn't we use random_ether_addr() here? */
2350 hw->perm_mac_addr[0] = 0x00;
2351 hw->perm_mac_addr[1] = 0x13;
2352 hw->perm_mac_addr[2] = 0x74;
2353 hw->perm_mac_addr[3] = 0x00;
2354 hw->perm_mac_addr[4] = 0x5c;
2355 hw->perm_mac_addr[5] = 0x38;
2356 }
2357
2358 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2359 hw->mac_addr[i] = hw->perm_mac_addr[i];
2360
2361 return 0;
2362}
2363
2364/*
2365 * Hashes an address to determine its location in the multicast table
2366 *
2367 * hw - Struct containing variables accessed by shared code
2368 * mc_addr - the multicast address to hash
2369 *
2370 * atl2_hash_mc_addr
2371 * purpose
2372 * set hash value for a multicast address
2373 * hash calcu processing :
2374 * 1. calcu 32bit CRC for multicast address
2375 * 2. reverse crc with MSB to LSB
2376 */
2377static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2378{
2379 u32 crc32, value;
2380 int i;
2381
2382 value = 0;
2383 crc32 = ether_crc_le(6, mc_addr);
2384
2385 for (i = 0; i < 32; i++)
2386 value |= (((crc32 >> i) & 1) << (31 - i));
2387
2388 return value;
2389}
2390
2391/*
2392 * Sets the bit in the multicast table corresponding to the hash value.
2393 *
2394 * hw - Struct containing variables accessed by shared code
2395 * hash_value - Multicast address hash value
2396 */
2397static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2398{
2399 u32 hash_bit, hash_reg;
2400 u32 mta;
2401
2402 /* The HASH Table is a register array of 2 32-bit registers.
2403 * It is treated like an array of 64 bits. We want to set
2404 * bit BitArray[hash_value]. So we figure out what register
2405 * the bit is in, read it, OR in the new bit, then write
2406 * back the new value. The register is determined by the
2407 * upper 7 bits of the hash value and the bit within that
2408 * register are determined by the lower 5 bits of the value.
2409 */
2410 hash_reg = (hash_value >> 31) & 0x1;
2411 hash_bit = (hash_value >> 26) & 0x1F;
2412
2413 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2414
2415 mta |= (1 << hash_bit);
2416
2417 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2418}
2419
2420/*
2421 * atl2_init_pcie - init PCIE module
2422 */
2423static void atl2_init_pcie(struct atl2_hw *hw)
2424{
2425 u32 value;
2426 value = LTSSM_TEST_MODE_DEF;
2427 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2428
2429 value = PCIE_DLL_TX_CTRL1_DEF;
2430 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2431}
2432
2433static void atl2_init_flash_opcode(struct atl2_hw *hw)
2434{
2435 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2436 hw->flash_vendor = 0; /* ATMEL */
2437
2438 /* Init OP table */
2439 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2440 flash_table[hw->flash_vendor].cmdPROGRAM);
2441 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2442 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2443 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2444 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2445 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2446 flash_table[hw->flash_vendor].cmdRDID);
2447 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2448 flash_table[hw->flash_vendor].cmdWREN);
2449 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2450 flash_table[hw->flash_vendor].cmdRDSR);
2451 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2452 flash_table[hw->flash_vendor].cmdWRSR);
2453 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2454 flash_table[hw->flash_vendor].cmdREAD);
2455}
2456
2457/********************************************************************
2458* Performs basic configuration of the adapter.
2459*
2460* hw - Struct containing variables accessed by shared code
2461* Assumes that the controller has previously been reset and is in a
2462* post-reset uninitialized state. Initializes multicast table,
2463* and Calls routines to setup link
2464* Leaves the transmit and receive units disabled and uninitialized.
2465********************************************************************/
2466static s32 atl2_init_hw(struct atl2_hw *hw)
2467{
2468 u32 ret_val = 0;
2469
2470 atl2_init_pcie(hw);
2471
2472 /* Zero out the Multicast HASH table */
2473 /* clear the old settings from the multicast hash table */
2474 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2475 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2476
2477 atl2_init_flash_opcode(hw);
2478
2479 ret_val = atl2_phy_init(hw);
2480
2481 return ret_val;
2482}
2483
2484/*
2485 * Detects the current speed and duplex settings of the hardware.
2486 *
2487 * hw - Struct containing variables accessed by shared code
2488 * speed - Speed of the connection
2489 * duplex - Duplex setting of the connection
2490 */
2491static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2492 u16 *duplex)
2493{
2494 s32 ret_val;
2495 u16 phy_data;
2496
2497 /* Read PHY Specific Status Register (17) */
2498 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2499 if (ret_val)
2500 return ret_val;
2501
2502 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2503 return ATLX_ERR_PHY_RES;
2504
2505 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2506 case MII_ATLX_PSSR_100MBS:
2507 *speed = SPEED_100;
2508 break;
2509 case MII_ATLX_PSSR_10MBS:
2510 *speed = SPEED_10;
2511 break;
2512 default:
2513 return ATLX_ERR_PHY_SPEED;
2514 break;
2515 }
2516
2517 if (phy_data & MII_ATLX_PSSR_DPLX)
2518 *duplex = FULL_DUPLEX;
2519 else
2520 *duplex = HALF_DUPLEX;
2521
2522 return 0;
2523}
2524
2525/*
2526 * Reads the value from a PHY register
2527 * hw - Struct containing variables accessed by shared code
2528 * reg_addr - address of the PHY register to read
2529 */
2530static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2531{
2532 u32 val;
2533 int i;
2534
2535 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2536 MDIO_START |
2537 MDIO_SUP_PREAMBLE |
2538 MDIO_RW |
2539 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2540 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2541
2542 wmb();
2543
2544 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2545 udelay(2);
2546 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2547 if (!(val & (MDIO_START | MDIO_BUSY)))
2548 break;
2549 wmb();
2550 }
2551 if (!(val & (MDIO_START | MDIO_BUSY))) {
2552 *phy_data = (u16)val;
2553 return 0;
2554 }
2555
2556 return ATLX_ERR_PHY;
2557}
2558
2559/*
2560 * Writes a value to a PHY register
2561 * hw - Struct containing variables accessed by shared code
2562 * reg_addr - address of the PHY register to write
2563 * data - data to write to the PHY
2564 */
2565static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2566{
2567 int i;
2568 u32 val;
2569
2570 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2571 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2572 MDIO_SUP_PREAMBLE |
2573 MDIO_START |
2574 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2575 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2576
2577 wmb();
2578
2579 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2580 udelay(2);
2581 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2582 if (!(val & (MDIO_START | MDIO_BUSY)))
2583 break;
2584
2585 wmb();
2586 }
2587
2588 if (!(val & (MDIO_START | MDIO_BUSY)))
2589 return 0;
2590
2591 return ATLX_ERR_PHY;
2592}
2593
2594/*
2595 * Configures PHY autoneg and flow control advertisement settings
2596 *
2597 * hw - Struct containing variables accessed by shared code
2598 */
2599static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2600{
2601 s32 ret_val;
2602 s16 mii_autoneg_adv_reg;
2603
2604 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2605 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2606
2607 /* Need to parse autoneg_advertised and set up
2608 * the appropriate PHY registers. First we will parse for
2609 * autoneg_advertised software override. Since we can advertise
2610 * a plethora of combinations, we need to check each bit
2611 * individually.
2612 */
2613
2614 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2615 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2616 * the 1000Base-T Control Register (Address 9). */
2617 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2618
2619 /* Need to parse MediaType and setup the
2620 * appropriate PHY registers. */
2621 switch (hw->MediaType) {
2622 case MEDIA_TYPE_AUTO_SENSOR:
2623 mii_autoneg_adv_reg |=
2624 (MII_AR_10T_HD_CAPS |
2625 MII_AR_10T_FD_CAPS |
2626 MII_AR_100TX_HD_CAPS|
2627 MII_AR_100TX_FD_CAPS);
2628 hw->autoneg_advertised =
2629 ADVERTISE_10_HALF |
2630 ADVERTISE_10_FULL |
2631 ADVERTISE_100_HALF|
2632 ADVERTISE_100_FULL;
2633 break;
2634 case MEDIA_TYPE_100M_FULL:
2635 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2636 hw->autoneg_advertised = ADVERTISE_100_FULL;
2637 break;
2638 case MEDIA_TYPE_100M_HALF:
2639 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2640 hw->autoneg_advertised = ADVERTISE_100_HALF;
2641 break;
2642 case MEDIA_TYPE_10M_FULL:
2643 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2644 hw->autoneg_advertised = ADVERTISE_10_FULL;
2645 break;
2646 default:
2647 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2648 hw->autoneg_advertised = ADVERTISE_10_HALF;
2649 break;
2650 }
2651
2652 /* flow control fixed to enable all */
2653 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2654
2655 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2656
2657 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2658
2659 if (ret_val)
2660 return ret_val;
2661
2662 return 0;
2663}
2664
2665/*
2666 * Resets the PHY and make all config validate
2667 *
2668 * hw - Struct containing variables accessed by shared code
2669 *
2670 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2671 */
2672static s32 atl2_phy_commit(struct atl2_hw *hw)
2673{
2674 s32 ret_val;
2675 u16 phy_data;
2676
2677 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2678 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2679 if (ret_val) {
2680 u32 val;
2681 int i;
2682 /* pcie serdes link may be down ! */
2683 for (i = 0; i < 25; i++) {
2684 msleep(1);
2685 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2686 if (!(val & (MDIO_START | MDIO_BUSY)))
2687 break;
2688 }
2689
2690 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2691 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2692 return ret_val;
2693 }
2694 }
2695 return 0;
2696}
2697
2698static s32 atl2_phy_init(struct atl2_hw *hw)
2699{
2700 s32 ret_val;
2701 u16 phy_val;
2702
2703 if (hw->phy_configured)
2704 return 0;
2705
2706 /* Enable PHY */
2707 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2708 ATL2_WRITE_FLUSH(hw);
2709 msleep(1);
2710
2711 /* check if the PHY is in powersaving mode */
2712 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2713 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2714
2715 /* 024E / 124E 0r 0274 / 1274 ? */
2716 if (phy_val & 0x1000) {
2717 phy_val &= ~0x1000;
2718 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2719 }
2720
2721 msleep(1);
2722
2723 /*Enable PHY LinkChange Interrupt */
2724 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2725 if (ret_val)
2726 return ret_val;
2727
2728 /* setup AutoNeg parameters */
2729 ret_val = atl2_phy_setup_autoneg_adv(hw);
2730 if (ret_val)
2731 return ret_val;
2732
2733 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2734 ret_val = atl2_phy_commit(hw);
2735 if (ret_val)
2736 return ret_val;
2737
2738 hw->phy_configured = true;
2739
2740 return ret_val;
2741}
2742
2743static void atl2_set_mac_addr(struct atl2_hw *hw)
2744{
2745 u32 value;
2746 /* 00-0B-6A-F6-00-DC
2747 * 0: 6AF600DC 1: 000B
2748 * low dword */
2749 value = (((u32)hw->mac_addr[2]) << 24) |
2750 (((u32)hw->mac_addr[3]) << 16) |
2751 (((u32)hw->mac_addr[4]) << 8) |
2752 (((u32)hw->mac_addr[5]));
2753 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2754 /* hight dword */
2755 value = (((u32)hw->mac_addr[0]) << 8) |
2756 (((u32)hw->mac_addr[1]));
2757 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2758}
2759
2760/*
2761 * check_eeprom_exist
2762 * return 0 if eeprom exist
2763 */
2764static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2765{
2766 u32 value;
2767
2768 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2769 if (value & SPI_FLASH_CTRL_EN_VPD) {
2770 value &= ~SPI_FLASH_CTRL_EN_VPD;
2771 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2772 }
2773 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2774 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2775}
2776
2777/* FIXME: This doesn't look right. -- CHS */
2778static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2779{
2780 return true;
2781}
2782
2783static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2784{
2785 int i;
2786 u32 Control;
2787
2788 if (Offset & 0x3)
2789 return false; /* address do not align */
2790
2791 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2792 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2793 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2794
2795 for (i = 0; i < 10; i++) {
2796 msleep(2);
2797 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2798 if (Control & VPD_CAP_VPD_FLAG)
2799 break;
2800 }
2801
2802 if (Control & VPD_CAP_VPD_FLAG) {
2803 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2804 return true;
2805 }
2806 return false; /* timeout */
2807}
2808
2809static void atl2_force_ps(struct atl2_hw *hw)
2810{
2811 u16 phy_val;
2812
2813 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2814 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2815 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2816
2817 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2818 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2819 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2820 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2821}
2822
2823/* This is the only thing that needs to be changed to adjust the
2824 * maximum number of ports that the driver can manage.
2825 */
2826#define ATL2_MAX_NIC 4
2827
2828#define OPTION_UNSET -1
2829#define OPTION_DISABLED 0
2830#define OPTION_ENABLED 1
2831
2832/* All parameters are treated the same, as an integer array of values.
2833 * This macro just reduces the need to repeat the same declaration code
2834 * over and over (plus this helps to avoid typo bugs).
2835 */
2836#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2837#ifndef module_param_array
2838/* Module Parameters are always initialized to -1, so that the driver
2839 * can tell the difference between no user specified value or the
2840 * user asking for the default value.
2841 * The true default values are loaded in when atl2_check_options is called.
2842 *
2843 * This is a GCC extension to ANSI C.
2844 * See the item "Labeled Elements in Initializers" in the section
2845 * "Extensions to the C Language Family" of the GCC documentation.
2846 */
2847
2848#define ATL2_PARAM(X, desc) \
2849 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2850 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2851 MODULE_PARM_DESC(X, desc);
2852#else
2853#define ATL2_PARAM(X, desc) \
2854 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
b79d8fff 2855 static unsigned int num_##X; \
452c1ce2
CS		 2856 module_param_array_named(X, X, int, &num_##X, 0); \
2857 MODULE_PARM_DESC(X, desc);
2858#endif
2859
2860/*
2861 * Transmit Memory Size
2862 * Valid Range: 64-2048
2863 * Default Value: 128
2864 */
2865#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2866#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2867#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2868ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2869
2870/*
2871 * Receive Memory Block Count
2872 * Valid Range: 16-512
2873 * Default Value: 128
2874 */
2875#define ATL2_MIN_RXD_COUNT 16
2876#define ATL2_MAX_RXD_COUNT 512
2877#define ATL2_DEFAULT_RXD_COUNT 64
2878ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2879
2880/*
2881 * User Specified MediaType Override
2882 *
2883 * Valid Range: 0-5
2884 * - 0 - auto-negotiate at all supported speeds
2885 * - 1 - only link at 1000Mbps Full Duplex
2886 * - 2 - only link at 100Mbps Full Duplex
2887 * - 3 - only link at 100Mbps Half Duplex
2888 * - 4 - only link at 10Mbps Full Duplex
2889 * - 5 - only link at 10Mbps Half Duplex
2890 * Default Value: 0
2891 */
2892ATL2_PARAM(MediaType, "MediaType Select");
2893
2894/*
2895 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2896 * Valid Range: 10-65535
2897 * Default Value: 45000(90ms)
2898 */
2899#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2900#define INT_MOD_MAX_CNT 65000
2901#define INT_MOD_MIN_CNT 50
2902ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2903
2904/*
2905 * FlashVendor
2906 * Valid Range: 0-2
2907 * 0 - Atmel
2908 * 1 - SST
2909 * 2 - ST
2910 */
2911ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2912
2913#define AUTONEG_ADV_DEFAULT 0x2F
2914#define AUTONEG_ADV_MASK 0x2F
2915#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2916
2917#define FLASH_VENDOR_DEFAULT 0
2918#define FLASH_VENDOR_MIN 0
2919#define FLASH_VENDOR_MAX 2
2920
2921struct atl2_option {
2922 enum { enable_option, range_option, list_option } type;
2923 char *name;
2924 char *err;
2925 int def;
2926 union {
2927 struct { /* range_option info */
2928 int min;
2929 int max;
2930 } r;
2931 struct { /* list_option info */
2932 int nr;
2933 struct atl2_opt_list { int i; char *str; } *p;
2934 } l;
2935 } arg;
2936};
2937
2938static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2939{
2940 int i;
2941 struct atl2_opt_list *ent;
2942
2943 if (*value == OPTION_UNSET) {
2944 *value = opt->def;
2945 return 0;
2946 }
2947
2948 switch (opt->type) {
2949 case enable_option:
2950 switch (*value) {
2951 case OPTION_ENABLED:
2952 printk(KERN_INFO "%s Enabled\n", opt->name);
2953 return 0;
2954 break;
2955 case OPTION_DISABLED:
2956 printk(KERN_INFO "%s Disabled\n", opt->name);
2957 return 0;
2958 break;
2959 }
2960 break;
2961 case range_option:
2962 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2963 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2964 return 0;
2965 }
2966 break;
2967 case list_option:
2968 for (i = 0; i < opt->arg.l.nr; i++) {
2969 ent = &opt->arg.l.p[i];
2970 if (*value == ent->i) {
2971 if (ent->str[0] != '\0')
2972 printk(KERN_INFO "%s\n", ent->str);
2973 return 0;
2974 }
2975 }
2976 break;
2977 default:
2978 BUG();
2979 }
2980
2981 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2982 opt->name, *value, opt->err);
2983 *value = opt->def;
2984 return -1;
2985}
2986
2987/*
2988 * atl2_check_options - Range Checking for Command Line Parameters
2989 * @adapter: board private structure
2990 *
2991 * This routine checks all command line parameters for valid user
2992 * input. If an invalid value is given, or if no user specified
2993 * value exists, a default value is used. The final value is stored
2994 * in a variable in the adapter structure.
2995 */
2996static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2997{
2998 int val;
2999 struct atl2_option opt;
3000 int bd = adapter->bd_number;
3001 if (bd >= ATL2_MAX_NIC) {
3002 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3003 bd);
3004 printk(KERN_NOTICE "Using defaults for all values\n");
3005#ifndef module_param_array
3006 bd = ATL2_MAX_NIC;
3007#endif
3008 }
3009
3010 /* Bytes of Transmit Memory */
3011 opt.type = range_option;
3012 opt.name = "Bytes of Transmit Memory";
3013 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3014 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3015 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3016 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3017#ifdef module_param_array
3018 if (num_TxMemSize > bd) {
3019#endif
3020 val = TxMemSize[bd];
3021 atl2_validate_option(&val, &opt);
3022 adapter->txd_ring_size = ((u32) val) * 1024;
3023#ifdef module_param_array
3024 } else
3025 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3026#endif
3027 /* txs ring size: */
3028 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3029 if (adapter->txs_ring_size > 160)
3030 adapter->txs_ring_size = 160;
3031
3032 /* Receive Memory Block Count */
3033 opt.type = range_option;
3034 opt.name = "Number of receive memory block";
3035 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3036 opt.def = ATL2_DEFAULT_RXD_COUNT;
3037 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3038 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3039#ifdef module_param_array
3040 if (num_RxMemBlock > bd) {
3041#endif
3042 val = RxMemBlock[bd];
3043 atl2_validate_option(&val, &opt);
3044 adapter->rxd_ring_size = (u32)val;
3045 /* FIXME */
3046 /* ((u16)val)&~1; */ /* even number */
3047#ifdef module_param_array
3048 } else
3049 adapter->rxd_ring_size = (u32)opt.def;
3050#endif
3051 /* init RXD Flow control value */
3052 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3053 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3054 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3055 (adapter->rxd_ring_size / 12);
3056
3057 /* Interrupt Moderate Timer */
3058 opt.type = range_option;
3059 opt.name = "Interrupt Moderate Timer";
3060 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3061 opt.def = INT_MOD_DEFAULT_CNT;
3062 opt.arg.r.min = INT_MOD_MIN_CNT;
3063 opt.arg.r.max = INT_MOD_MAX_CNT;
3064#ifdef module_param_array
3065 if (num_IntModTimer > bd) {
3066#endif
3067 val = IntModTimer[bd];
3068 atl2_validate_option(&val, &opt);
3069 adapter->imt = (u16) val;
3070#ifdef module_param_array
3071 } else
3072 adapter->imt = (u16)(opt.def);
3073#endif
3074 /* Flash Vendor */
3075 opt.type = range_option;
3076 opt.name = "SPI Flash Vendor";
3077 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3078 opt.def = FLASH_VENDOR_DEFAULT;
3079 opt.arg.r.min = FLASH_VENDOR_MIN;
3080 opt.arg.r.max = FLASH_VENDOR_MAX;
3081#ifdef module_param_array
3082 if (num_FlashVendor > bd) {
3083#endif
3084 val = FlashVendor[bd];
3085 atl2_validate_option(&val, &opt);
3086 adapter->hw.flash_vendor = (u8) val;
3087#ifdef module_param_array
3088 } else
3089 adapter->hw.flash_vendor = (u8)(opt.def);
3090#endif
3091 /* MediaType */
3092 opt.type = range_option;
3093 opt.name = "Speed/Duplex Selection";
3094 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3095 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3096 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3097 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3098#ifdef module_param_array
3099 if (num_MediaType > bd) {
3100#endif
3101 val = MediaType[bd];
3102 atl2_validate_option(&val, &opt);
3103 adapter->hw.MediaType = (u16) val;
3104#ifdef module_param_array
3105 } else
3106 adapter->hw.MediaType = (u16)(opt.def);
3107#endif
3108}
Clone of davem's net-next-2.6 tree